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© 1999,2000
MOS INTEGRATED CIRCUIT
µ
µ µ
µ
PD16681A
LCD CONTROLLER/DRIVER FOR DOT MATRIX DISPLAY OF JIS LEVEL 1
AND JIS LEVEL 2 KANJI SETS
DATA SHEET
Document No. S14207EJ3V0DS00 (3rd edition)
Date Published June 2002 NS CP(K)
Printed in Japan
The mark ★
★★
★ shows major revised points.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
DESCRIPTION
The
µ
PD16681A is a single-chip controller driver that can display Japanese text; including JIS Level 1 kanji, JIS
Level 2 kanji, hiragana, and katakana. Each chip can display up to four lines containing up to eight full width
characters (11 x 12 dots), or up to four lines containing up to 16 half width characters (5 x 12 dots), as well 96
pictographs.
FEATURES
•LCD controller/driver for dot matrix display of JIS Level 1 and JIS Level 2 kanji sets
•On-chip ROM for character generation
−JIS Level 1 + Level 2 kanji (11 x 12 dots): 6,355 characters
−JIS non-kanji characters (11 x 12 dots): 453 characters
−Half width alphanumeric characters (5 x 12 dots): 192 characters
•On-chip RAM for character generation
−8 types (12 x 13 dots)
•On-chip boost circuit: switchable between 3x and 4x modes
•RAM for pictograph data displays: 96 bits
•Outputs: 96 segments, 52 commons
•Duty settings: 1/39 or 1/52
•Switchable data inputs: serial or 8-bit parallel
•On-chip divider resistor
•Selectable bias settings (1/8 bias, 1/7 bias, or 1/6 bias)
•On-chip oscillation circuit
ORDERING INFORMATION
Part number Package ROM code
µ
PD16681A-001 Wafer Standard
µ
PD16681AP-001 Chip (COG compliant) Standard
Remark Purchasing the above chip entails the exchange of documents such as a separate memorandum or
product quality, so please contact one of our sales representatives.
★
Data Sheet S14207EJ3V0DS
2
µ
µµ
µ
PD16681A
1. BLOCK DIAGRAM
I/O
Buffer
RAM Data
Register
Index
Register Control
Register
RAM Address
Counter
Display Data RAM
Timing Generator
Pictograph
Data RAM
Character
Generator
RAM
Full-width
Character
Generator
ROM
Half-width
Character
Generator
ROM
Address Formation Circuit
Display Attribute Control Circuit
Cursor Control
Circuit Parallel/Serial Conversion Circuit
Smooth Scroll Control Circuit
96 bits
Shift
Register
96 bits
Latch
Circuit
Segment
Driver
Oscillation Circuit
Common
Driver
66
12
6
6
8
7
8
8
84
8
3
DC/DC
Converter
OP Amp.
D/A
Converter
LCD V oltage Generator
6
8
VLC1
VLC2
C1 , C1
STB
WS
E/SCK
TESTOUT
/RESET
SEGINV
COMINV
COM1 to COM51
PCOM1,PCOM2
OSCINOSCOUT OSCBRI
C2 , C2
C3 , C3
VEXT
SEG1 to SEG96
AMPIN(+) AMPIN(−)
AMPOUT
AMPCHA VLCBS1
VLC3 VLCBS2
VLCBS3 VLC4
VLC5
VDD
VSS
D0/DATA
D1 to D7
+−
+
+−
−
VLCD
DACHA
Remark /xxx indicates active low signals.
Data Sheet S14207EJ3V0DS 3
µ
µµ
µ
PD16681A
2. PIN CONFIGURATION (Pad Layout)
Chip size: 2.80 x 10.48 mm2
241 219
218
108
107
83
82
1
Y
X
Data Sheet S14207EJ3V0DS
4
µ
µµ
µ
PD16681A
Table 2-1. Pad Layout
PAD
No.
Pin Name X (
µ
m) Y (
µ
m) PAD
No.
Pin Name X (
µ
m) Y (
µ
m) PAD
No.
Pin Name X (
µ
m) Y (
µ
m) PAD
No.
Pin Name X (
µ
m) Y (
µ
m)
1 DUMMY1 −1273 4800 61 DACHA −1273 −2400 121 SEG90 1273 −3735 181 SEG30 1273 1665
2V
LCBS1 −1273 4680 62 AMPCHA −1273 −2520 122 SEG89 1273 −3645 182 SEG29 1273 1755
3VLCBS1 −1273 4560 63 SEGINV −1273 −2640 123 SEG88 1273 −3555 183 SEG28 1273 1845
4VLCBS2 −1273 4440 64 COMINV −1273 −2760 124 SEG87 1273 −3465 184 SEG27 1273 1935
5VLCBS2 −1273 4320 65 OSCIN −1273 −2880 125 SEG86 1273 −3375 185 SEG26 1273 2025
6VLCBS3 −1273 4200 66 OSCOUT −1273 −3000 126 SEG85 1273 −3285 186 SEG25 1273 2115
7VLCBS3 −1273 4080 67 OSCBRI −1273 −3120 127 SEG84 1273 −3195 187 SEG24 1273 2205
8AMPOUT −1273 3960 68 D0/DATA −1273 −3240 128 SEG83 1273 −3105 188 SEG23 1273 2295
9AMPOUT −1273 3840 69 D1−1273 −3360 129 SEG82 1273 −3015 189 SEG22 1273 2385
10 AMPIN(−)−1273 3720 70 D2−1273 −3480 130 SEG81 1273 −2925 190 SEG21 1273 2475
11 AMPIN(−)−1273 3600 71 D3−1273 −3600 131 SEG80 1273 −2835 191 SEG20 1273 2565
12 AMPIN(+) −1273 3480 72 D4−1273 −3720 132 SEG79 1273 −2745 192 SEG19 1273 2655
13 AMPIN(+) −1273 3360 73 D5−1273 −3840 133 SEG78 1273 −2655 193 SEG18 1273 2745
14 VLC5 −1273 3240 74 D6−1273 −3960 134 SEG77 1273 −2565 194 SEG17 1273 2835
15 VLC5 −1273 3120 75 D7−1273 −4080 135 SEG76 1273 −2475 195 SEG16 1273 2925
16 VLC5 −1273 3000 76 WS −1273 −4200 136 SEG75 1273 −2385 196 SEG15 1273 3015
17 VLC4 −1273 2880 77 STB −1273 −4320 137 SEG74 1273 −2295 197 SEG14 1273 3105
18 VLC4 −1273 2760 78 E/SCK −1273 −4440 138 SEG73 1273 −2205 198 SEG13 1273 3195
19 VLC4 −1273 2640 79 /RESET −1273 −4560 139 SEG72 1273 −2115 199 SEG12 1273 3285
20 VLC3 −1273 2520 80 TESTOUT −1273 −4680 140 SEG71 1273 −2025 200 SEG11 1273 3375
21 VLC3 −1273 2400 81 DUMMY2 −1273 −4800 141 SEG70 1273 −1935 201 SEG10 1273 3465
22 VLC3 −1273 2280 82 DUMMY3 −1273 −4920 142 SEG69 1273 −1845 202 SEG91273 3555
23 VLC2 −1273 2160 83 DUMMY4 −1120 −5113 143 SEG68 1273 −1755 203 SEG81273 3645
24 VLC2 −1273 2040 84 DUMMY5 −1030 −5113 144 SEG67 1273 −1665 204 SEG71273 3735
25 VLC2 −1273 1920 85 COM27 −940 −5113 145 SEG66 1273 −1575 205 SEG61273 3825
26 VLC1 −1273 1800 86 COM28 −850 −5113 146 SEG65 1273 −1485 206 SEG51273 3915
27 VLC1 −1273 1680 87 COM29 −760 −5113 147 SEG64 1273 −1395 207 SEG41273 4005
28 VLC1 −1273 1560 88 COM30 −670 −5113 148 SEG63 1273 −1305 208 SEG31273 4095
29 VLCD −1273 1440 89 COM31 −580 −5113 149 SEG62 1273 −1215 209 SEG21273 4185
30 VLCD −1273 1320 90 COM32 −490 −5113 150 SEG61 1273 −1125 210 SEG11273 4275
31 VLCD −1273 1200 91 COM33 −400 −5113 151 SEG60 1273 −1035 211 COM26 1273 4365
32 C1+−1273 1080 92 COM34 −310 −5113 152 SEG59 1273 −945 212 COM25 1273 4455
33 C1+−1273 960 93 COM35 −220 −5113 153 SEG58 1273 −855 213 COM24 1273 4545
34 C1+−1273 840 94 COM36 −130 −5113 154 SEG57 1273 −765 214 COM23 1273 4635
35 C1−−1273 720 95 COM37 −40 −5113 155 SEG56 1273 −675 215 COM22 1273 4725
36 C1−−1273 600 96 COM38 50 −5113 156 SEG55 1273 −585 216 COM21 1273 4815
37 C1−−1273 480 97 COM39 140 −5113 157 SEG54 1273 −495 217 DUMMY10 1273 4905
38 C2+−1273 360 98 COM40 230 −5113 158 SEG53 1273 −405 218 DUMMY11 1273 4995
39 C2+−1273 240 99 COM41 320 −5113 159 SEG52 1273 −315 219 DUMMY12 950 5113
40 C2+−1273 120 100 COM42 410 −5113 160 SEG51 1273 −225 220 COM20 860 5113
41 C2−−1273 0 101 COM43 500 −5113 161 SEG50 1273 −135 221 COM19 770 5113
42 C2−−1273 −120 102 COM44 590 −5113 162 SEG49 1273 −45 222 COM18 680 5113
43 C2−−1273 −240 103 COM45 680 −5113 163 SEG48 1273 45 223 COM17 590 5113
44 C3+−1273 −360 104 COM46 770 −5113 164 SEG47 1273 135 224 COM16 500 5113
45 C3+−1273 −480 105 COM47 860 −5113 165 SEG46 1273 225 225 COM15 410 5113
46 C3+−1273 −600 106 DUMMY6 950 −5113 166 SEG45 1273 315 226 COM14 320 5113
47 C3−−1273 −720 107 DUMMY7 1040 −5113 167 SEG44 1273 405 227 COM13 230 5113
48 C3−−1273 −840 108 DUMMY8 1273 −4905 168 SEG43 1273 495 228 COM12 140 5113
49 C3−−1273 −960 109 COM48 1273 −4815 169 SEG42 1273 585 229 COM11 50 5113
50 VDD1 −1273 −1080 110 COM49 1273 −4725 170 SEG41 1273 675 230 COM10 −40 5113
51 VDD1 −1273 −1200 111 COM50 1273 −4635 171 SEG40 1273 765 231 COM9−130 5113
52 VDD2 −1273 −1320 112 COM51 1273 −4545 172 SEG39 1273 855 232 COM8−220 5113
53 VDD2 −1273 −1440 113 DUMMY9 1273 −4455 173 SEG38 1273 945 233 COM7−310 5113
54 VDD2 −1273 −1560 114 PCOM21273 −4365 174 SEG37 1273 1035 234 COM6−400 5113
55 VSS −1273 −1680 115 SEG96 1273 −4275 175 SEG36 1273 1125 235 COM5−490 5113
56 VSS −1273 −1800 116 SEG95 1273 −4185 176 SEG35 1273 1215 236 COM4−580 5113
57 VSS −1273 −1920 117 SEG94 1273 −4095 177 SEG34 1273 1305 237 COM3−670 5113
58 VSS −1273 −2040 118 SEG93 1273 −4005 178 SEG33 1273 1395 238 COM2−760 5113
59 VSS −1273 −2160 119 SEG92 1273 −3915 179 SEG32 1273 1485 239 COM1−850 5113
60 VEXT −1273 −2280 120 SEG91 1273 −3825 180 SEG31 1273 1575 240 PCOM1−940 5113
241 DUMMY13 −1030 5113
Data Sheet S14207EJ3V0DS 5
µ
µµ
µ
PD16681A
3. PIN FUNCTIONS
3.1 Power Supply System Pins
Pin Symbol Pin Name Pad No. I/O Description
VDD Logic power supply
Boost circuit power supply
50 to 54 −Power supply pins for logic and boost circuit
VSS Logic ground
Driver ground
55 to 59 −Ground pins for logic and driver circuit
VLCD Driver power supply 29 to 31 −Power supply pins for driver. Output pin for internal boost circuit.
Connect a 1-
µ
F capacitor between these pins and the VSS pins
for boosting.
If not using the internal boost circuit, a direct driver power supply
can be input.
VLC1-VLC5 Reference power supply
pins for driver
14 to 28 −These are reference power supply pins for the LCD driver.
Leave these pins open if an internal bias has been selected.
Connect a capacitor to ground.
VLCBS1-VLCBS3 Bias value setting 2 to 7 −When selecting an internal bias, the bias value can be changed
connecting these pins outside of the IC.
C1+, C1-
C2+, C2-
C3+, C3-
Capacitor connection 32 to 49 −These are capacitor connection pins for the boost circuit.
Connect a 1-
µ
F capacitor.
Data Sheet S14207EJ3V0DS
6
µ
µµ
µ
PD16681A
3.2 Logic System Pins
Pin Symbol Pin Name Pad No. I/O Description
WS Select word length 76 Input Use this pin to select the word length. An 8-bit parallel interface is used
for high level and a serial interface is used for low level. This setting
cannot be changed after the power has been switched on.
DACHA Select D/A converter 61 Input Use this pin to select whether or not to use the D/A converter for
regulating the LCD driver voltage. Select high level to use the D/A
converter or low level to not use it.
STB Strobe 77 Input This is used for the device’s select signal and strobe signal for
communication. Communication is initialized at the rising edge or falling
edge of STB.
Command data receive standby status occurs at the falling edge of STB.
Communication is enabled when STB is low.
Also, enabled status or the shift clock is ignored when STB is high.
E/SCK Enable/shift clock 78 Input This is an input enable pin for data when the parallel interface is used.
During the read-in operation, data is captured in the interface buffer at
the signal’s rising edge. During a read-out operation, data is read-out
from the interface buffer at the signal’s falling edge.
When using a serial interface, this pin is used for the data shift clock.
During the read-in operation, data is captured in the shift register at the
signal’s rising edge. During a read-out operation, data is read from the
shift register at the signal’s falling edge.
D0/DATA Data bus/data 68 I/O This pin is used for data bus bit D0 when using the parallel interface.
When using the serial interface, it is an I/O pin (tri-state) for commands
and display data.
D1-D7Data bus 69 to 75 I/O These pins are used for data bus bits D1 to D7 when using the parallel
interface.
It should be fixed high or low when using the serial interface.
TESTOUT Test output 80 Output This is a test output pin. Leave this pin open when using the device.
/RESET Reset 79 Input This pin is used for internal resets at low-level.
AMPCHA Op amp switch for
LCD driver’s power
supply level
62 Input This pin is used to control the op amp that works with the LCD driver’s
power supply level. High-power mode is set when at low level and
normal mode is set when at high level.
VEXT Reference power
supply switch
60 Input This pin is used to select the reference power supply circuit’s supply
mode. High level sets external mode and low level sets internal mode.
SEGINV Segment direction
switch
63 Input This pin is used to control the segment output direction. Low level sets
forward direction and high level sets reverse direction.
COMINV Common scan
direction switch
64 Input This pin is used to switch the common scan direction. Low level sets
forward direction and high level sets reverse direction.
OSCIN Oscillator 65 Input These pins are connected to a 100-kΩ resistance. When using an
OSCOUT 66 Output external oscillator, input to OSCIN and leave OSCOUT open.
OSCBRI External clock for
blink function
67 Input This is an input pin for the 2-Hz external clock. Internally, it is divided by
half to generate a 1-Hz signal that is used as the synchronization signal
for the blink function.
Data Sheet S14207EJ3V0DS 7
µ
µµ
µ
PD16681A
3.3 Driver System Pins
Pin Symbol Pin Name Pad No. I/O Description
SEG1-SEG96 Segment 115 to 210 Output Segment output pins
COM1-COM51 Common 85 to 105
109 to 112
211 to 216
220 to 239
Output Common output pins
1/52 duty : Use COM1 to COM51
1/39 duty : Use COM1 to COM19, COM27 to COM45 and leave
COM20 to COM26, COM46 to COM51 open
PCOM1,
PCOM2
Pictograph common 240,
114
Output Common output pins for pictographs
The same signal is output from PCOM1 and PCOM2.
AMPIN(+) Op amp inputs 10 to 13 Input These are input pins for the op amp that regulates the LCD driver voltage.
Leave the AMPIN(+) pin unconnected when using the on-chip D/A converter.
When not using the D/A converter, a reference voltage must
AMPIN(−)be input.
Connect the AMPIN(−) pin to a resistor used to regulate the LCD voltage.
(See diagram below.)
AMPOUT Op amp outputs 8,9 Output These are output pins for the op amp that regulates the LCD driver
voltage. Normally, they are connected to resistors that are used to
regulate the LCD voltage. (See diagram below.)
Since the AMPOUT pins are used to stabilize the on-chip amp’s output, we
recommend connecting them to a capacitor that is rated between 0.1 and
1.0
µ
F.
DUMMY DUMMY 1, 81 to 84,
106 to 108, 113,
217 to 219, 241
−DUMMY pins are not connected to the internal circuit. Leave open if they
are not used.
Figure 3−
−−
−1. Voltage Control Circuit
D/A
converter
AMP
IN(−)
AMP
OUT
V
LC1
V
SS
V
EXT
V
LC2
V
LC3
V
LC4
V
LC5
V
LCBS1
V
LCBS2
V
LCBS3
DA
CHA
AMP
IN(+)
R
1
R
2
C
1
−
+
Reference power supply circuit
Data Sheet S14207EJ3V0DS
8
µ
µµ
µ
PD16681A
4. POWER SUPPLY CIRCUIT
A switchable (3x or 4x) boost circuit is included to generate a current for driving the LCD. A connection to a boost-
related capacitor is used to switch the boost circuit’s setting.
The VEXT pin (H: external, L: internal) is used to switch between using an external LCD driver power supply or the
on-chip boost circuit.
4.1 Boost Circuit
When using the internal power supply, connect the boost-related capacitor between C1+ and C1−, C2+ and C2−, and
C3+ and C3−. Also, connect the capacitor for level stabilization between VLCD and VSS, and set VEXT low to boost the
potential between VDD and VSS from 3 to 4 times.
Since the boost circuit uses signals from the internal oscillation circuit, the oscillation circuit must be operating. The
relation between the boosted voltage and the potential is described below.
The C1+ to C3− and VDD pins all relate to the boost circuit, so the wire impedance should be minimized.
Figure 4−
−−
−1. 3x and 4x Boost Mode
V
DD
= 3 V
V
SS
= 0 V
V
LCD
= 3V
DD
=
9 V
(During 3x boost mode )
V
LCD
= 4V
DD
=
12 V
(During 4x boost mode)
Note
Note When set for 3x boost, connect boost-related capacitors between C2− and C3+ and C1+ and C1−.
Data Sheet S14207EJ3V0DS 9
µ
µµ
µ
PD16681A
4.2 Regulation of LCD Driver Voltage
4.2.1 When not using internal power supply select or D/A converter (VEXT = L, DACHA = L)
When using the internal power supply, the boosted voltage is used as the power supply for the op amp incorporated
in the IC for the LCD driver’s voltage. A common mode amplifier circuit can be configured by connecting external
resistors R1 and R2 and inputting the reference voltage VREF to AMPIN(+), and this configuration can be used to
regulate the potential of the LCD driver voltage VLC1. If using a thermistor to regulate the LCD driver voltage to suit
the liquid crystals’ temperature characteristics, we recommend connecting in parallel to R2.
The LCD driver voltage VLC1 can be determined using the following formula.
th2
th2
2
REF
1
2
OUTLC1
RR
RR
'R
V
R
'R
1AMPV
+
×
=
+==
Figure 4−
−−
−2. When Not Using Internal Power Supply Select or D/A Converter
D/A
converter
AMPIN(
−
)AMPOUT VLC1
R2
R1C1
Rth
AMPIN
(+)
VREF
DACHA
To internal drive circuit
+
−
4.2.2 When using internal power supply select and D/A converter (VEXT = L, DACHA = H)
Using the D/A converter enables commands to be entered to control the reference voltage VREF that is input to the +
input of the op amp for the LCD driver voltage.
The D/A converter function sets 6-bit data to the D/A converter set register to set one of the 64 modes for the
reference voltage VREF between VDD and 1/2 VDD.
The formula for VLC1 is the same as in 4.2.1 When not using internal power supply select or D/A converter
(VEXT = L, DACHA = L) above.
Remark
Data Sheet S14207EJ3V0DS
10
µ
µµ
µ
PD16681A
Figure 4−
−−
−3. Using Internal Power Supply Select and D/A Converter
V
DD
D/A
converter
AMP
IN(−)
AMP
OUT
V
LC1
R
2
R
1
C
1
+
−
R
th
AMP
IN(+)
DA
CHA
OPEN
V
REF
V
DD
To internal drive circuit
4.2.3 When using an external power supply (VEXT = H)
When an external power supply is used for the LCD driver voltage, the op amp incorporate in the
µ
PD16681A (used
for the LCD driver voltage) is in OFF mode. Consequently, the LCD driver’s op amp and D/A converter function
cannot be used when using an external power supply. Instead, regulate the LCD driver voltage by inputting directly
to the VLCD and VLC1 pins.
Cautions 1. Maintain the following relation for the voltage input to the VLCD and VLC1 pins : VLCD > VLC1
2. Since the DACHA, AMPIN(+), and AMPIN(−
−−
−) pins are CMOS inputs, they should be fixed either high or
low.
3. The AMPOUT pin should be left unconnected.
4.3 Reference Voltage
4.3.1 When using internal power supply (VEXT = L)
When using the internal power supply, the
µ
PD16681A’s on-chip divider resistor is used to create the six-level
potential (VLC1 to VLC5, and VSS) required for the LCD driver.
4.3.2 When using an external power supply (VEXT = H)
When use of an external power supply has been selected, the op amp incorporated in the
µ
PD16681A for the LCD
driver level power supply is in OFF mode, so a reference potential must be directly input to VLC1 to VLC5.
Ordinarily, these levels are generated by dividing the resistance. Since large resistance values result in poorer LCD
display quality, be sure to select a resistance value that suits the type of LCD panel to be used.
The display quality can be improved by connecting capacitors between the level pins and ground pins. As with the
resistance values described above, the capacitance values of the capacitors should be selected to suit the divided
resistance values and the type of LCD panel to be used.
Data Sheet S14207EJ3V0DS 11
µ
µµ
µ
PD16681A
4.4 Control of Op Amp for Level Power Supply
Input to the AMPCHA pin is used to control the op amp for the LCD driver level power supply.
•High power mode (AMPCHA = L)
This mode maximizes the LCD drive current supply capacity in the op amp for the LCD driver level power supply.
•Normal mode (AMPCHA = H)
This mode uses a lower LCD drive current supply capacity in the op amp for the LCD driver level power supply,
which is suitable for charging the capacitor used to stabilize the external level.
Caution For either mode, be sure to connect a level stabilization capacitor (rated from about 0.1 to 1.0
µ
µµ
µ
F)
for the VLC1 to VLC5 pins. Poorer display quality results when these capacitors are not connected.
Figure 4−
−−
−4. Reference Voltage Circuit
V
LC1
R
Output to SEG and COM
V
LC2
R
V
LC3
R
R
2R
V
LCBS3
V
LCBS2
V
LC4
R
V
LC5
R
AMP
OUT
V
LCBS1
V
SS
Op amp for level driver
+
−
+
−
+
−
+
−
+
−
Output to SEG and COM
Output to SEG and COM
Output to SEG and COM
Output to SEG and COM
Output to SEG and COM
Data Sheet S14207EJ3V0DS
12
µ
µµ
µ
PD16681A
4.5 Bias Value Settings
The bias value can be set as 1/6 bias, 1/7 bias, or 1/8 bias by selecting an internal bias for the (
µ
PD16681A and by
connecting externally from the IC among VLCBS1-VLCBS3 pins.
Bias Value Connected Pin
1/8 bias VLCBS1-VLCBS3 leave open
1/7 bias Between VLCBS1 and VLCBS2 or between VLCBS2 and VLCBS3
1/6 bias Between VLCBS1 and VLCBS3 and VLCBS2 leave open
4.6 Power Supply Circuit Use Example
Figure 4−
−−
−5. Using Internal Power Supply and Normal Mode
VDD
To VDD
VLCD
C1
C1
C2
C2
C3
C3
VSS
VLC5
VLC4
VLC3
VLC2
VLC1
AMPOUT
AMP(−)
AMP(+)
VEXT
R2Rth (thermistor)
R1
C2
C1
C1
C1
VDD
VLCD
C3open
VCHA
VSS
VEXT
C2
C1
+
+
+
+
AMPCHA
VDD
C1
C2
C3
open C2
C1
C1
+
+
+
+
+
+
+
+
+
+
−
+
−
+
−
−
+
+
−
−
+
A) 4x boost (D/A converter is not used.) B) 3x boost
Remarks 1. C1 = 1.0
µ
F, C2 = 1.0
µ
F
2. Leave C2+ and C3− pins open during 3x boost.
3. Leave AMP(+) open when using the D/A converter.
Data Sheet S14207EJ3V0DS 13
µ
µµ
µ
PD16681A
Figure 4−
−−
−6. Using External Power Supply Circuit
VDD
C1
C1
C2
C2
C3
C3
VSS
VLC5
VLC4
VLC3
VLC2
open
VLC1
VLCD
AMPOUT open
AMP(−)
AMP(+)
VEXT
VDD
R
R
4R
R
R
+
−
+
−
+
−
To external drive supply
A) Use 1/8 bias
Remark Fix all open input pins high or low.
Data Sheet S14207EJ3V0DS
14
µ
µµ
µ
PD16681A
5. LCD DISPLAY DRIVER
Either a 1/52 duty driver or a 1/39 duty driver can be selected for the
µ
PD16681A. Both drivers output a drive
waveform using the two-frame AC drive method.
5.1 1/52 Duty Driver
When the 1/52 duty driver is selected for the
µ
PD16681A, a select signal is output once per frame from the dot
block’s common outputs (COM1 to COM51) and from the pictograph block’s common outputs (same signal output
from PCOM1 and PCOM2).
Figure 5−
−−
−1. 1/52 Duty Driver
V
LC1
V
LC2
V
LC3
SEG
1
COM
1
COM
2
PCOM
1
PCOM
2
V
LC4
V
LC5
V
SS
V
LC1
V
LC2
V
LC3
V
LC4
V
LC5
V
SS
V
LC1
V
LC2
V
LC3
V
LC4
V
LC5
V
SS
V
LC1
V
LC2
V
LC3
V
LC4
V
LC5
V
SS
1Frame
1234567 5051521234567 50 51 52
88
Data Sheet S14207EJ3V0DS 15
µ
µµ
µ
PD16681A
5.2 1/39 Duty Driver
When the 1/39 duty driver is selected for the
µ
PD16681A, a select signal is output once per frame from the dot
block’s common outputs (COM1 to COM19, COM27 to COM45) and from the pictograph block’s common outputs (same
signal output from PCOM1 and PCOM2).
Figure 5−
−−
−2. 1/39 Duty Driver
V
LC1
V
LC2
V
LC3
SEG
1
COM
1
COM
2
PCOM
1
PCOM
2
V
LC4
V
LC5
V
SS
V
LC1
V
LC2
V
LC3
V
LC4
V
LC5
V
SS
V
LC1
V
LC2
V
LC3
V
LC4
V
LC5
V
SS
V
LC1
V
LC2
V
LC3
V
LC4
V
LC5
V
SS
1Frame
1234567 3738391234567 37 38 39
88
Data Sheet S14207EJ3V0DS
16
µ
µµ
µ
PD16681A
6. DESCRIPTION OF BLOCKS
6.1 Display Data RAM (DDRAM)
DDRAM is RAM that contains display data consisting of a 16-bit character code plus a character attribute code. The
RAM capacity is 16 x 72 bits, which means that up to 72 characters can be stored in RAM.
The following table shows correspondences between DDRAM addresses and LCD display positions. For further
description of these correspondences, see the section 7.1 LCD Display and DDRAM Addresses.
123456789101112131415161718
1st line 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H
2nd line 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H
3rd line 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H
4th line 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H 45H 46H 47H
6.2 Full Width (11x12 dots) Character Generator ROM (FCGROM)
FCGROM generates a total of 6,808 full width character patterns, of which 6,355 are JIS Level 1 + Level 2 kanji, and
453 are non-kanji characters. These character patterns are displayed in 11 x12 dot font patterns based on 12-bit
character codes. The section entitled 7.2.2 Full width(11 x 12 dots) character code setting examples describes
the correspondence between the character codes set to DDRAM and this full width font pattern.
Also, see the section entitled 7.2 Character Codes for a description of the correspondence between the JIS code
and the character code set to DDRAM.
6.3 Half Width(5 x 12 dots) Character Generator ROM (HCGROM)
FCGROM generates a total of 192 half width (5 x 12 dots) character patterns, displayed in 5 x 12 dot font patterns.
The section entitled 7.2 Character Codes describes the correspondence between the character code set to DDRAM
and the half width font patterns.
★
Data Sheet S14207EJ3V0DS 17
µ
µµ
µ
PD16681A
6.4 Character Generator RAM (CGRAM)
CGRAM is RAM to which the user can freely set character patterns. Eight types of 12 x 13 dot character patterns
can be defined. To display a character pattern that has been stored in CGRAM, the user specifies a value ranging
from “000H” to “007H”.
The relation between character codes and CGRAM addresses used to access CGRAM is shown below.
Figure 6−
−−
−1. The Relation between Character Codes and CGRAM Addresses
D
7
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
6
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
D
4
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
0
0
1
1
0
0
0
D
3
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
1
1
0
0
0
0
0
D
2
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
0
0
0
D
1
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
1
1
0
0
0
0
0
1
0
0
0
D
0
0
1
0
0
0
0
1
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
0
D
7
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
6
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
5
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
1
1
0
0
0
0
0
1
0
0
0
D
4
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
0
0
0
D
3
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
1
1
0
0
0
0
0
D
2
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
0
0
1
1
0
0
0
D
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
D
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
A2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
A3
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
A4
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
A5
0
1
1
A6
0
0
·
·
·
1
A7
0
0
1
C0
0
1
·
·
·
1
C1
0
0
·
·
·
1
C2
0
0
·
·
·
1
C3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C12
0
0
0
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
0
0
0
to
CGRAM Data
A0 ="0" A0 ="1"CGRAM Address
Character code
0
0
0
0
0
0
0
0
0
Data Sheet S14207EJ3V0DS
18
µ
µµ
µ
PD16681A
Remarks 1. CGRAM is selected when the high-order nine bits (C11 to C3) of a character code are all zeros. At that
time, the low-order three bits (C2 to C0) corresponds to CGRAM addresses 7 to 5 (A7 to A5). (Three
bits: eight types.)
2. Display ON is selected when the CGRAM data value is “1”. Display OFF is selected when this data
value is “0”.
3. The CGRAM address 0 (A0) corresponds to the left and right sides of the character pattern.
4. The high-order two bits of CGRAM are used to control the display attributes of the pattern
corresponding to the low-order six bits. In such cases, any display attribute specification made for
DDRAM is ignored. When the value of the high-order two bits is “00”, CGRAM’s pattern is displayed.
5. CGRAM addresses 4 to 1 (A4 to A1) corresponds to the line position of the character pattern. (Four
bits : 13 lines) The ORed result with the cursor is taken and displayed on the 12th line.
6.5 Pictograph Display RAM (PDRAM)
PDRAM is the RAM that contains pictograph display data that has been assigned to PCOM1 and PCOM2. The data
display function is ON when the data value is “1” and OFF when the data value is “0”.
After data is written, the address counter is automatically incremented (by one), and the value after 0FH is 00H.
The correspondence between output from various segments and PDRAM addresses is shown below.
PCOM1, PCOM2
Segment Output No.
Address b7 b6 b5 b4 b3 b2 b1 b0
00H XX654321
01H X X 12 11 10 9 8 7
02H X X 18 17 16 15 14 13
03H X X 24 23 22 21 20 19
04H X X 30 29 28 27 26 25
05H X X 36 35 34 33 32 31
06H X X 42 41 40 39 38 37
07H X X 48 47 46 45 44 43
08H X X 54 53 52 51 50 49
09H X X 60 59 58 57 56 55
0AH X X 666564636261
0BH X X 727170696867
0CH X X 787776757473
0DH X X 848382818079
0EH X X 908988878685
0FH X X 969594939291
Remark X: Don’t care
Data Sheet S14207EJ3V0DS 19
µ
µµ
µ
PD16681A
6.6 Pictograph Blink Data RAM (PBRAM)
PBRAM is the RAM that contains pictograph blink data that has been assigned to PCOM1 and PCOM2. A data
value of “1” is written to the address of the pictograph to be set for a blink display.
After data is written, the address counter is automatically incremented (by one), and the value after 0FH is 00H.
The correspondence between output from various segments and PBRAM addresses is shown below.
PCOM1, PCOM2
Segment Output No.
Address b7 b6 b5 b4 b3 b2 b1 b0
00H XX654321
01H X X 12 11 10 9 8 7
02H X X 18 17 16 15 14 13
03H X X 24 23 22 21 20 19
04H X X 30 29 28 27 26 25
05H X X 36 35 34 33 32 31
06H X X 42 41 40 39 38 37
07H X X 48 47 46 45 44 43
08H X X 54 53 52 51 50 49
09H X X 60 59 58 57 56 55
0AH X X 666564636261
0BH X X 727170696867
0CH X X 787776757473
0DH X X 848382818079
0EH X X 908988878685
0FH X X 969594939291
Remark X : Don’t care
6.7 Relation between Addresses and Various ROM and RAM Devices
The
µ
PD16681A assigned FCGROM addresses as shown below to HCGROM and CGRAM.
Type No. of Characters Address Range
JIS kanji 6,355 Same as kanji ROM IC
Non-JIS kanji 453 Same as kanji ROM IC
Half width alphanumeric characters 192 Uses addresses 0080H to 039FH in the kanji ROM IC
CGRAM 8 Uses addresses 0000H to 0007H in the kanji ROM IC
★
Data Sheet S14207EJ3V0DS
20
µ
µµ
µ
PD16681A
7. LCD DISPLAY
The
µ
PD16681A’s LCD display can display four lines containing up to 8 characters (11 x 12 dots) or 16 characters
(5 x 12 dots) and 96 pictographs.
123
SEG
PCOM
1
PCOM
2
COM
1
COM
2
COM
3
COM
4
COM
5
COM
6
COM
7
COM
8
COM
9
COM
10
COM
11
COM
12
COM
13
COM
14
COM
15
COM
16
COM
17
COM
18
COM
19
COM
47
COM
48
COM
49
COM
50
COM
51
45678910 11 12 13 14 15 16 17 18 85 86 87 88 89 90 91 92 93 94 95 96
Remark The same select signal is output from PCOM1 and PCOM2.
Data Sheet S14207EJ3V0DS 21
µ
µµ
µ
PD16681A
7.1 LCD Display and DDRAM Addresses
The character code used in the
µ
PD16681A contains 16 bits (character code + character attribute code). When
data is stored to an address in DDRAM, a combination of full width (11 x 12 dots) and half width (5 x 12 dots)
characters can be displayed on the LCD.
The relation between the DDRAM’s character area and the actual LCD display when displaying a combination of full
width and half width characters is shown below.
Figure 7−
−−
−1. The Relation between the DDRAM’s Character Area and the Actual LCD Display
LCD Display
Note
Note Half width space
DDRAM
123456789101112131415161718
1st line 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H
2nd line 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H
3rd line 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H
4th line 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H 45H 46H 47H
Remark Shaded areas indicate addresses.
Address characters that are not displayed are used as data for character scrolling.
Data Sheet S14207EJ3V0DS
22
µ
µµ
µ
PD16681A
7.2 Character Codes
The
µ
PD16681A is able to combine full width characters (11 x 12 dots) and half width characters (5 x 12 dots) in the
same display. The character data that is stored in DDRAM is displayed starting from the top left corner of the LCD
screen. A one-dot character interval is added to the left of each character font.
Both full width (11 x 12 dots) and half width (5 x 12 dots) characters are handled using 16-bit code lengths and are
stored in DDRAM. The 16-bit code format uses the low-order 13 bits as the character code. The remaining 3 bits are
the high-order 3 bits, which specify the character width (full or half) and the display attribute. The MSB is the select
bit indicating full width or half width character code: “0” specifies full width characters and “1” specifies half width
characters. The character attribute code is assigned to the next two bits, and can specify attributes such as blinking
for individual characters. (See the section 7.3 Display Attributes.)
7.2.1 Code format
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
F/H A1 A0 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0
Full width(11 x 12 dots) character/
Half width(5 x 12 dots) character specification
Display attribute codes
High-order character code Low-order character code
7.2.2 Full width (11 x 12 dots) character code setting examples
The following shows the correspondence between 16-bit JIS code and the
µ
PD16681A’s 13-bit character code.
This correspondence varies according to the values of the high-order 3 bits (b17, b16, and b15) in the first byte of the
JIS code.
Convert JIS code as shown below to generate character code for the
µ
PD16681A.
(1) JIS level 1 kanji and non-kanji characters
Table 7−
−−
−1. When (b17, b16, b15) = (0, 1, 0)
First byte Second byte
JIS C 6226 b17 b16 b15 b14 b13 b12 b11 b27 b26 b25 b24 b23 b22 b21
Character code C9 C8 C7 C6 C5 C4 C3 C2 C1 C0
Remark C12 = C6 = C5 = 0
Table 7−
−−
−2. When (b17, b16, b15) = (0, 1, 1) or (1, 0, 0)
First byte Second byte
JIS C 6226 b17 b16 b15 b14 b13 b12 b11 b27 b26 b25 b24 b23 b22 b21
Character code C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0
Remark C12 = 0
Data Sheet S14207EJ3V0DS 23
µ
µµ
µ
PD16681A
(2) JIS level 2 kanji and non-kanji characters
Table 7−
−−
−3. When (b17, b16, b15) = (1, 1, 1)
First byte Second byte
JIS C 6226 b17 b16 b15 b14 b13 b12 b11 b27 b26 b25 b24 b23 b22 b21
Character code C9 C8 C7 C11 C10 C4 C3 C2 C1 C0
Remark C12 = 1, C6 = C5 = 0
Table 7−
−−
−4. When (b17, b16, b15) = (1, 0, 1) or (1, 1, 0)
First byte Second byte
JIS C 6226 b17 b16 b15 b14 b13 b12 b11 b27 b26 b25 b24 b23 b22 b21
Character code C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0
Remark C12 = 1
(3) CGRAM
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0XX00000 00000u2u1u0
Remark CGRAM addresses for user font: u2 to u0
Data Sheet S14207EJ3V0DS
24
µ
µµ
µ
PD16681A
7.3 Display Attributes
In the
µ
PD16681A, the character code is assigned to 12 bits of the 16-bit data that is specified as full width (11 x 12
dots) characters or half width (5 x 12 dots) characters and the display attribute code is assigned to two of the
remaining four bits. Normal display or blink display mode can be specified for each character unit.
The blink cycle for blink display mode is 64 frames, so that display blinks on or off once every 32 frames.
7.3.1 Character code format
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
F/H A1 A0 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0
Full width(11 x 12 dots) character/
Half width(5 x 12 dots) character specification
Display attribute codes
High-order character code Low-order character code
7.3.2 Display attribute specifications
A1 A0 Display Mode
0 0 Normal display
0 1 Reverse display
1 0 Character blink
1 1 Reverse character blink
7.3.3 Display examples
(1) Normal display
(2) Reverse display
Data Sheet S14207EJ3V0DS 25
µ
µµ
µ
PD16681A
(3) Blink display
Display alternates
once every 32 frames
(4) Reverse blink display
Display alternates
once every 32 frames
Data Sheet S14207EJ3V0DS
26
µ
µµ
µ
PD16681A
8. COMMANDS
8.1 Basic Format
+
+
++ · · ·
Command register (CR)
Command register (CR) Extended selection register (ESR)
Address register (AR) RAM Address register (RAD)
Command register (CR)
Note
DATA 1(DT1)
Note The command (1 or 2 bytes) immediately follows the falling edge of the STB signal, and whatever is sent
after that is recognized as data.
Table 8−
−−
−1. Command List
Register Contents
Command b7 b6 b5 b4 b3 b2 b1 b0
Reset 00100411
Display ON/OFF 00001b2b1b0
Standby 00010b2b1b0
Duty setting 000110b1b0
Cursor control 000111b1b0
D/A converter setting 00101000
Scroll control 0011b3b2b1b0
Blink setting 010000b1b0
Address register 010010b1b0
Data R/W mode 10110b2b1b0
Test mode 1010b3b2b1b0
8.1.1 Reset
This command resets all of the commands in the
µ
PD16681A.
MSB LSB
0 0 1 0 0 0 1 1
Data Sheet S14207EJ3V0DS 27
µ
µµ
µ
PD16681A
8.1.2 Display ON/OFF
This command controls the display’s ON/OFF status.
MSB LSB
Selection
000 : LCD OFF (SEG
n
, COM
n
, PCOM
n
= V
SS
)
001 : LCD OFF (SEG
n
, COM
n
, PCOM
n
= non-select waveform)
111 : LCD ON
0 0 0 0 1 b2 b1 b0
8.1.3 Standby
This command stops the DC/DC converter, which reduces the supply current. The display is set to OFF mode
(SEGn, COMn = VSS).
MSB LSB
0 0 0 1 0 b2 b1 b0
Selection
000 : Normal operation
001 : Standby (stop DC/DC converter, fulll display off ,stop OSC)
Note
Note SEGn, COMn, PCOMn = VEE
8.1.4 Duty setting
This command specifies the duty setting.
MSB LSB
0 0 0 1 1 0 b1 b0
Selection
00 : 1/52 duty
01 : 1/39 duty
Note
Note Use COM1 to COM19 and COM27 to COM45, leave COM20 to COM26 and COM46 to COM51 open when setting
1/39 duty.
Data Sheet S14207EJ3V0DS
28
µ
µµ
µ
PD16681A
8.1.5 Cursor control
This command controls the cursor’s ON/OFF status.
MSB LSB
0 0 0 1 1 1 b1 b0
Selection
00 : Cursor OFF
10 : Cursor ON (no blink)
11 : Cursor ON (blink)
Note2
Note1
Note3
Notes 1. 00: Sets cursor to OFF mode.
2. 10: Sets cursor to ON mode (cursor is displayed). The cursor is displayed at the character which
occupies the display position of the currently specified DDRAM address. The “address register” + “data
R/W command” combination is used to set data to DDRAM addresses. When accessing RAM, the
address counter in RAM is automatically incremented (+1) or decremented (−1), and the cursor is moved
accordingly.
3. 11: This sets the cursor to ON mode and causes the cursor to blink. The blink cycle is 64 frames. The
correspondence between the cursor and the RAM address is the same as when the cursor is blinking.
Caution The cursor display function is valid only when the display attribute specifies “normal display”
(A0 = 0, A1 = 0).
8.1.6 D/A converter set 1
The D/A converter’s output for the LCD driver is set in 64 steps from VDD to 1/2 VDD.
MSB LSB
0 0 b5 b4 b3 b2 b1 b0
MSB LSB
0 0 1 0 1 0 0 0 +
Extended selection
D/A output selection
00H(MIN.) to 3FH(MAX.)
Remark This value is set to 20H after a reset.
Data Sheet S14207EJ3V0DS 29
µ
µµ
µ
PD16681A
8.1.7 Scroll control
This controls scrolling of displayed characters.
The individual bits in the selection are allocated to their respective display lines. When the data value is “1”,
scrolling is enabled for that line. The distance of the dots’ leftward (horizontal) motion is selected via the extended
selection register that is input after the command. The dot move distance varies depending on the current LCD
display status and the contents of DDRAM. For details, see the section 8.4 Scrolling.
MSB LSB
0 b6 b5 b4 b3 b2 b1 b0
MSB LSB
0 0 1 1 b3 b2 b1 b0 +
Selection
b0 : Scroll selection on fourth line
b1 : Scroll selection on third line
b2 : Scroll selection on second line
b3 : Scroll selection on first line
Dot move distance selection
8.1.8 Pictograph blink setting
This command performs blink control for the pictograph at addresses where the blink (PBRAM) data value is “1”.
MSB LSB
0 1 0 0 0 0 b1 b0
Selection
00 : Stop blink (blink frequency = fOSC/319488)
01 : Stop blink (blink frequency = fBR1 /2)
10 : Start blink (blink frequency = fOSC/319488)
11 : Start blink (blink frequency = fBR1 /2)
Note
Note
Note This refers to the frequency of the external clock that is input from the OSCBR1 pin.
Data Sheet S14207EJ3V0DS
30
µ
µµ
µ
PD16681A
8.1.9 Data R/W command
This command performs data read/write operations.
MSB LSB
b7 b6 b5 b4 b3 b2 b1 b0
MSB LSB
1 0 1 1 0 b2 b1 b0 ++ · · ·
Selection 1
00 : Increments up from the current address
01 : Retains current address
10 : Decrements down from the current address
Note 1
Note 1
Selection 2
0 : Data write
1 : Data read
Note 2
Notes 1. During increment mode, when the current address is the last address the next address becomes 00H.
During decrement mode, when the current address is 00H, the next address becomes the last address.
2. Data read mode is cancelled at the rising edge of the STB signal (mode is switched to command/data write
mode).
Caution During a serial data transfer, write data in 8-bit or 16-bit segments. If the rising edge of STB occurs
during the data transfer operation, the operation is not guaranteed.
8.1.10 Test mode
This command sets the test mode. The test mode is only for confirming the IC’s operation. Regular or continuous
use while in test mode is not guaranteed.
MSB LSB
1 0 1 0 b3 b2 b1 b0
Selection
0000 : Normal operation
0001 to 1111 : Test mode
Data Sheet S14207EJ3V0DS 31
µ
µµ
µ
PD16681A
8.2 Address Register
This command selects the address type and specifies addresses.
MSB LSB
b7 b6 b5 b4 b3 b2 b1 b0
MSB LSB
0 1 0 0 1 0 b1 b0 +
Selection 1
00 : DDRAM address
01 : PDRAM address
10 : PBRAM address
11 : CGRAM address
Selection 2
DDRAM address : 00H to 47H
PDRAM address : 00H to 0FH
PBRAM address : 00H to 0FH
CGRAM address : 00H to F9H
Caution Operation is not guaranteed if an invalid address is set.
8.3 Reset
The contents of the various registers appear as shown below after a reset (command reset or hardware [pin] reset).
Register Contents
Command
b7 b6 b5 b4 b3 b2 b1 b0
Description
Display ON/OFF 00001000LCD OFF (SEG
n, COMn, PCOMn = VSS)
Standby 0 0010000Normal operation
Duty setting 000110001/52 duty
Cursor control 00011100Cursor OFF
D/A converter setting00101000Set to 20H
Scroll control 00110000No specified scroll line
Blink setting 01000000Blink stop
Address register 01001000DDRAM is specified
Data R/W mode 10110000Data write/increment (+1)
Test mode 10100000Normal operation
Data Sheet S14207EJ3V0DS
32
µ
µµ
µ
PD16681A
8.4 Scrolling
Character scrolling is controlled by inputting scroll control commands (8 bits) plus scroll dot count data (8 bits). The
line to be scrolled is specified by the scroll control command and the scroll dot count data sets the number of dots to
be scrolled. When this command is input, the characters on the specified line are shifted leftward by the specified
number of dots.
The number of dots that can be scrolled differs according to the contents of the data stored in DDRAM (for details,
refer to 8.4.1 Scrollable number of dots and 8.4.2 Display and scrollable number of dots). Consequently, if
scrolling is specified for an amount of data that exceeds the scrollable data, the character data, only the scrollable
data is shifted and overwritten, and scrolling must be performed again.
Caution For character scrolling, be sure to input a scroll control command (8 bits) plus the amount of
scrolled data (8 bits).
8.4.1 Scrollable number of dots
Scroll amount = (12 dots x number of non-displayed full width characters that are stored in DDRAM)
+ (6 dots x number of non-displayed half width characters that are stored in DDRAM)
8.4.2 Display and scrollable number of dots
LCD Display:
DDRAM Status
123456789101112131415161718
1st line 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H
2nd line 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H
3rd line 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H
4th line 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H 45H 46H 47H
Remark Shaded areas indicate addresses.
Address characters that are not displayed are used as data for character scrolling.
Data Sheet S14207EJ3V0DS 33
µ
µµ
µ
PD16681A
Character Memory Contents
Remarks 1. Shaded areas indicate addresses.
2. First line: (10 full width (11 x 12 dots) characters)
Second line: (6 full width (11 x 12 dots) characters),
"484"(4 half width (5 x 12 dots) characters)
Third line: "PB"(2 half width (5 x 12 dots) characters)
Fourth line: (2 full width (5 x 12 dots) characters)
Scrollable dot counts;
First line: (12 dots x 10 characters) + (6 dots x 0 characters) = 120 dots
Second line: (12 dots x 6 characters) + (6 dots x 4 characters) = 96 dots
Third line: (12 dots x 0 characters) + (6 dots x 2 characters) = 12 dots
Fourth line: (12 dots x 2 characters) + (6 dots x 0 characters) = 24 dots
If scroll count data that exceeds the scrollable number of dots is entered using the scroll control
command, all dots that are in the area that goes beyond the DDRAM addresses are output as OFF
data.
Data Sheet S14207EJ3V0DS
34
µ
µµ
µ
PD16681A
8.5 Serial Communication Format
(1) Reception 1 (command write, 1 byte)
STB
DATA b7 b6 b5 b2 b1 b0
SCK 123 678
(2) Reception 2 (command/data write, 2 bytes or more)
STB
DATA
SCK 12
Command 1 Command 1/Data
Wait time tWAIT
3 678 12345
b7 b6 b5 b2 b1 b0 b7 b6 b5 b4 b3
(3) Transmission (command/data read)
STB
DATA
SCK 123 678 12345
b7 b6 b5 b2 b1 b0 b7 b6 b5 b4 b3
6
Data read command setting Wait time tWAIT Data read
Data Sheet S14207EJ3V0DS 35
µ
µµ
µ
PD16681A
8.6 Parallel Communication Format
(1) 8-bit parallel interface
STB
D
0
-
D
7
E
Data Sheet S14207EJ3V0DS
36
µ
µµ
µ
PD16681A
9. COMMAND EXAMPLES
Table 9−
−−
−1. Initial Setting (1/39 duty) + Data Input
STBD7D6D5D4D3D2D1D0 Status
Hard Reset
HXXXXXXXX
L 0 0 0 1 1 0 0 1 Duty setting (1/39 duty)
HXXXXXXXX
L 0 1 0 0 1 0 0 0 Address register (DDRAM address selection)
0 0 0 0 0 0 0 0 DDRAM address: 00H
HXXXXXXXX
1 0 1 1 0 0 0 0 Data write, address is incremented starting
from current address
D15 D14 D13 D12 D11 D10 D9 D8 Data for first character
D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 Data for second character
D7 D6 D5 D4 D3 D2 D1 D0
:
D15 D14 D13 D12 D11 D10 D9 D8 Data for 54th character
L
D7 D6 D5 D4 D3 D2 D1 D0
HXXXXXXXX
L 0 1 0 0 1 0 0 1 Address register (PDRAM address selection)
H 0 0 0 0 0 0 0 0 PDRAM address: 00H
LXXXXXXXX
1 0 1 1 0 0 0 0 Data write, address is incremented starting
from current address
X X D D D D D D PDRAM: data at 00H
X X D D D D D D PDRAM: data at 01H
:
L
X X D D D D D D PDRAM: data at 0FH
HXXXXXXXX
0 1 0 0 1 0 1 0 Address register (PBRAM address selection)
L0 0 0 0 0 0 0 0 PBRAM address : 00H
HXXXXXXXX
1 0 1 1 0 0 0 0 Data write, address is incremented starting
from current address
X X D D D D D D PBRAM: data at 00H
X X D D D D D D PBRAM: data at 01H
:
L
X X D D D D D D PBRAM: data at 0FH
HXXXXXXXX
L00001111Display ON
HXXXXXXXX
To next processing
Remark X: Don’t care
Data Sheet S14207EJ3V0DS 37
µ
µµ
µ
PD16681A
Table 9−
−−
−2. CGRAM Data Write
STBD7D6D5D4D3D2D1D0 Status
Start
HXXXXXXXX
0 1 0 0 1 0 1 1 Address register (CGRAM address selection)
L0 0 0 0 0 0 0 0 CGRAM address: 00H
HXXXXXXXX
1 0 1 1 0 0 0 0 Data write, address is incremented starting
from current address
A A D5 D4 D3 D2 D1 D0 Data for first character (at 000H)
A A D5 D4 D3 D2 D1 D0 Data in first line of pattern
A A D5 D4 D3 D2 D1 D0 Data for first character (at 000H)
A A D5 D4 D3 D2 D1 D0 Data in second line of pattern
:
A A D5 D4 D3 D2 D1 D0 Data for Xth character (at 00mH)
L
A A D5 D4 D3 D2 D1 D0 Data in nth line of pattern
HXXXXXXXX
To next processing
Remark X: Don’t care
Data Sheet S14207EJ3V0DS
38
µ
µµ
µ
PD16681A
10. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°
°°
°C, VSS = 0 V)
Parameter Symbol Rating Unit
Supply voltage (4x boost) VDD −0.3 to +3.75 V
Supply voltage (3x boost) VDD −0.3 to +5.0 V
Driver supply voltage VLCD −0.3 to +15.0, VDD ≤ VLCD V
Driver reference supply input voltage VLC1-VLC5 −0.3 to VLCD+0.3 V
Logic system input voltage VIN1 −0.3 to VDD+0.3 V
Logic system output voltage VOUT1 −0.3 to VDD+0.3 V
Logic system input/output voltage VI/O1 −0.3 to VDD+0.3 V
Driver system input voltage VIN2 −0.3 to VLCD+0.3 V
Driver system output voltage VOUT2 −0.3 to VLCD+0.3 V
Operating ambient temperature TA−40 to +85 °C
Storage temperature Tstg −55 to +150 °C
Caution If the absolute maximum rating of even one of the above parameters is exceeded even momentarily,
the quality of the product may be degraded. Absolute maximum ratings, therefore, specify the
values exceeding which the product may be physically damaged. Be sure to use the product within
the range of the absolute maximum ratings.
Recommended Operating Range (TA = –40 to +85°
°°
°C, VSS = 0 V)
Parameter Symbol MIN. TYP. MAX. Unit
Supply voltage (4x boost) VDD 2.0 3.0 V
Supply voltage (3x boost) VDD 2.0 4.0 V
Driver supply voltage VLCD 5.0 10 12 V
Logic system input voltage VIN 0V
DD V
Driver system input voltage VLC1-VLC5 0V
LCD V
Remarks 1. When using an external power supply, be sure to maintain these relations:
VSS < VLC5 < VLC4 < VLC3 < VLC2 < VLC1 ≤ VLCD
2. Maintain VDD ≤ VLCD when turning the power on or off.
3. Keep voltage input to the AMPIN(+) pin between 1.0 V and VDD when using an internal power supply but
not using the D/A converter.
Data Sheet S14207EJ3V0DS 39
µ
µµ
µ
PD16681A
Electrical characteristics (unless otherwise specified, TA = −
−−
−40 to +85°
°°
°C, VDD = 2.0 to 3.0 V during 4x boost
mode or 2.0 to 4.0 V during 3x boost mode)
Parameter Symbol Condition MIN. TYP. MAX. Unit
High-level input voltage VIH 0.8 VDD V
Low-level input voltage VIL 0. 2VDD V
High-level input current IIH1 Except for D0/DATA and D1 to D71
µ
A
Low-level input current IIL1 Except for D0/DATA and D1 to D7−1
µ
A
High-level output voltage VOH IOUT = −1.0 mA, except OSCOUT VDD−0.5 V
Low-level output voltage VOL IOUT = 2.0 mA, except OSCOUT 0.5 V
High-level leakage current ILOH D0/DATA and D1 to D7, VIN/OUT = VDD 10
µ
A
Low-level leakage current ILOL D0/DATA and D1 to D7, VIN/OUT = VSS −10
µ
A
Common output ON resistance RCOM VLCn → COMn, VLCD ≥ 3VDD, ILOL = 50
µ
A2kΩ
Segment output ON resistance RSEG VLCn → SEGn, VLCD ≥ 3VDD, ILOL = 50
µ
A4kΩ
Driver voltage (boost voltage) VLCD During 3x boost 2.7 VDD 3.0 VDD V
During 4x boost 3.6 VDD 4.0 VDD V
Current consumption
(normal mode)
IDD11 fOSC = 375 kHz, all display OFF data
output, VDD = 3.0 V during 3x boost mode
100 180
µ
A
fOSC = 375 kHz, all display OFF data
output, VDD = 3.0 V during 4x boost mode
135 210
µ
A
Current consumption
(high-power mode)
IDD12 fOSC = 375 kHz, all display OFF data
output, VDD = 3.0 V during 3x boost mode
150 280
µ
A
fOSC = 375 kHz, all display OFF data
output, VDD = 3.0 V during 4x boost mode
200 340
µ
A
Driver system current consumption (VDD)
(Standby)
IDD21 VDD = 3.0 V 1 10
µ
A
Remark The TYP. value is a reference value when TA = 25°C
Test Circuit
D/A
Converter
DA
CHA
AMP
IN(−)
AMP
OUT
V
LC1
V
LC2
V
LC3
V
LC4
V
LC5
V
SS
V
EXT
+
−
V
DD
AMP
IN(+)
Reference supply circuit
Data Sheet S14207EJ3V0DS
40
µ
µµ
µ
PD16681A
Switching characteristics (unless otherwise specified, TA = −
−−
−40 to +85°
°°
°C)
VDD = 2.0 to 2.7 V
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Oscillation frequency fOSC Self-oscillation,
oscillation resistance R = 100 kΩ
180 500 kHz
Transfer delay time tPHL SCK↓→DATA↓150 ns
Transfer delay time tPLH SCK↓→DATA↑150 ns
Remark The TYP. value is a reference value when TA = 25°C
VDD = 2.7 to 3.3 V
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Oscillation frequency fOSC Self-oscillation,
oscillation resistance R = 100 kΩ
240 378 560 kHz
Transfer delay time tPHL SCK↓→DATA↓60 ns
Transfer delay time tPLH SCK↓→DATA↑60 ns
Remark Use the following equation to determine the time per frame.
1 frame = 1/fOSC x 96 x number of duty
fOSC = 375 kHz, Given a 1/52 duty,
1 frame = 2.67
µ
s (96 x 52 = 13.1 ms ≅ 75 Hz)
Data Sheet S14207EJ3V0DS 41
µ
µµ
µ
PD16681A
Required timing conditions (unless otherwise specified, TA = −
−−
−40 to +85°
°°
°C)
Common (1) (VDD = 2.0 to 2.7 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Clock frequency fOSC OSCIN external clock 375 kHz
High-level clock pulse width tWHC1 OSCIN external clock 1000 ns
Low-level clock pulse width tWLC1 OSCIN external clock 1000 ns
High-level clock pulse width tWHC2 OSCBRI external clock 1000 ns
Low-level clock pulse width tWLC2 OSCBRI external clock 1000 ns
Rise/fall time tr,tf OSCBRI external clock 100 ns
Reset pulse width tWRE /RESET pin 100
µ
s
Reset cancellation time tRRE /RESET pin 100
µ
s
Remark The TYP. value is a reference value when TA = 25°C
Common (2) (VDD = 2.7 to 3.3 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Clock frequency fOSC OSCIN external clock 240 375 560 kHz
High-level clock pulse width tWHC1 OSCIN external clock 500 ns
Low-level clock pulse width tWLC1 OSCIN external clock 500 ns
High-level clock pulse width tWHC2 OSCBRI external clock 400 ns
Low-level clock pulse width tWLC2 OSCBRI external clock 400 ns
Rise/fall time tr,tfOSCBRI external clock 100 ns
Reset pulse width tWRE /RESET pin 50
µ
s
Reset cancellation time tRRE /RESET pin 50
µ
s
Remark The TYP. value is a reference value when TA = 25°C
Serial interface (1) (VDD = 2.0 to 2.7 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Shift clock cycle tCYK SCK 2000 ns
High-level shift clock pulse width tWHK SCK 1000 ns
Low-level shift clock pulse width tWLK SCK 1000 ns
Shift clock hold time tHSTBK STB↓→SCK↓300 ns
Data setup time tDS1 DATA→SCK↑150 ns
Data hold time tDH1 SCK↑→DATA 150 ns
STB hold time tHKSTB SCK↑→STB↑300 ns
STB pulse width tWSTB 300 ns
Wait time tWAIT 8th SCK↑→1st SCK↓1000 ns
Remarks 1. The TYP. value is a reference value when TA = 25 °C
2. T.B.D. (To be determined.)
Data Sheet S14207EJ3V0DS
42
µ
µµ
µ
PD16681A
Serial interface (2) (VDD = 2.7 to 3.3 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Shift clock cycle tCYK SCK 500 ns
High-level shift clock pulse width tWHK SCK 260 ns
Low-level shift clock pulse width tWLK SCK 210 ns
Shift clock hold time tHSTBK STB↓→SCK↓260 ns
Data setup time tDS1 DATA→SCK↑40 ns
Data hold time tDH1 SCK↑→DATA 40 ns
STB hold time tHKSTB SCK↑→STB↑260 ns
STB pulse width tWSTB 210 ns
Wait time tWAIT 8th SCK↑→1st SCK↓260 ns
Remark The TYP. value is a reference value when TA = 25°C
Parallel interface (1) (VDD = 2.0 to 2.7 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Enable cycle time tCYCE E↑→E↑2000 ns
High-level enable pulse width tWHE E 1000 ns
Low-level enable pulse width tWLE E 1000 ns
STB pulse width tWSTB 300 ns
STB hold time tWKSTB 300 ns
Enable hold time tHSTBK 300 ns
Data setup time tDS2 D0 to D7→E↑150 ns
Data hold time tDH2 D0 to D7→E↓150 ns
Remark The TYP. value is a reference value when TA = 25°C
Parallel interface (2) (VDD = 2.7 to 3.3 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Enable cycle time tCYCE E↑→E↑500 ns
High-level enable pulse width tWHE E 260 ns
Low-level enable pulse width tWLE E 210 ns
STB pulse width tWSTB 210 ns
STB hold time tWKSTB 260 ns
Enable hold time tHSTBK 260 ns
Data setup time tDS2 D0 to D7→E↑40 ns
Data hold time tDH2 D0 to D7→E↓40 ns
Remark The TYP. value is a reference value when TA = 25 °C
Data Sheet S14207EJ3V0DS 43
µ
µµ
µ
PD16681A
AC timing measurement voltages
V
IH
Input V
IL
V
OH
Output V
OL
AC characteristics waveforms
OSC
IN
t
WHC1
t
WLC1
1/f
OSC
t
WHC2
t
WLC2
OSC
VR1
t
f
t
r
Serial interface (input)
STB
SCK
DATA
tHSTBK tHKSTB
tCYK tWHK
tWSTB
tDS1 tDH1
tWLK
Serial interface (output)
SCK
DATA
t
PHL
t
PLH
Data Sheet S14207EJ3V0DS
44
µ
µµ
µ
PD16681A
8-bit parallel interface
t
HSTBK
t
WLE
t
DS2
t
DH2
t
WHE
t
CYCE
STB
E
D
n
t
WKSTB
t
WSTB
Reset
t
WRE
/RESET
t
RRE
Reset time Reset cancellation
time
Data Sheet S14207EJ3V0DS 45
µ
µµ
µ
PD16681A
11. CHARACTER CODE TABLES (standard ROM code,
µ
µµ
µ
PD16681AW/P-001)
The following tables show the correspondences between character codes and characters. Character codes ranging
from 0000H to 0007H are assigned to CGRAM.
Character allocation table (1)
C12 = 0
★
Data Sheet S14207EJ3V0DS
46
µ
µµ
µ
PD16681A
Character allocation table (2)
C12 = 0
Data Sheet S14207EJ3V0DS 47
µ
µµ
µ
PD16681A
Character allocation table (3)
C12 = 0
Data Sheet S14207EJ3V0DS
48
µ
µµ
µ
PD16681A
Character allocation table (4)
C12 = 0
Data Sheet S14207EJ3V0DS 49
µ
µµ
µ
PD16681A
Character allocation table (5)
C12 = 1
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000001111111111111111
00000000111111110000000011111111
00001111000011110000111100001111
00110011001100110011001100110011
01010101010101010101010101010101
陝陟陦陲陬隍隘隕隗險隧隱隲隰隴隶隸隹雎雋雉雍襍雜霍雕雹霄霆霈霓
顱顴顳颪颯颱颶飄飃飆飩飫餃餉餒餔餘餡餝餞餤餠餬餮餽餾饂饉饅饐饋
髻鬆鬘鬚鬟鬢鬣鬥鬧鬨鬩鬪鬮鬯鬲魄魃魏魍魎魑魘魴鮓鮃鮑鮖鮗鮟鮠鮨
鵝鵞鵤鵑鵐鵙鵲鶉鶇鶫鵯鵺鶚鶤鶩鶲鷄鷁鶻鶸鶺鷆鷏鷂鷙鷓鷸鷦鷭鷯鷽
堯槇遙瑤凛煕
霎霑霏霖霙霤霪霰霹霽霾靄靆靈靂靉靜靠靤靦靨勒靫靱靹鞅靼鞁靺鞆鞋鞏
饑饒饌饕馗馘馥馭馮馼駟駛駝駘駑駭駮駱駲駻駸騁騏騅駢騙騫騷驅驂驀驃
鮴鯀鯊鮹鯆鯏鯑鯒鯣鯢鯤鯔鯡鰺鯲鯱鯰鰕鰔鰉鰓鰌鰆鰈鰒鰊鰄鰮鰛鰥鰤鰡
鸚鸛鸞鹵鹹鹽麁麈麋麌麒麕麑麝麥麩麸麪麭靡黌黎黏黐黔黜點黝黠黥黨黯
鞐鞜鞨鞦鞣鞳鞴韃韆韈韋韜韭齏韲竟韶韵頏頌頸頤頡頷頽顆顏顋顫顯顰
騾驕驍驛驗驟驢驥驤驩驫驪骭骰骼髀髏髑髓體髞髟髢髣髦髯髫髮髴髱髷
鰰鱇鰲鱆鰾鱚鱠鱧鱶鱸鳧鳬鳰鴉鴈鳫鴃鴆鴪鴦鶯鴣鴟鵄鴕鴒鵁鴿鴾鵆鵈
黴黶黷黹黻黼黽鼇鼈皷鼕鼡鼬鼾齊齒齔齣齟齠齡齦齧齬齪齷齲齶龕龜龠
C6
C5
C4
C3
C2
C1
C0
012345678910111213141516171819202122232425262728293031
C11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C10
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
C9
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C8
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
C7
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Maintenance area
Maintenance area
Maintenance area
Maintenance area
★
Data Sheet S14207EJ3V0DS
50
µ
µµ
µ
PD16681A
Character allocation table (6)
C12 = 1
Data Sheet S14207EJ3V0DS 51
µ
µµ
µ
PD16681A
Character allocation table (7)
C12 = 1
Data Sheet S14207EJ3V0DS
52
µ
µµ
µ
PD16681A
Character allocation table (8)
C12 = 1
Data Sheet S14207EJ3V0DS 53
µ
µµ
µ
PD16681A
[MEMO]
Data Sheet S14207EJ3V0DS
54
µ
µµ
µ
PD16681A
[MEMO]
Data Sheet S14207EJ3V0DS 55
µ
µµ
µ
PD16681A
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
µ
µµ
µ
PD16681A
Reference Documents
NEC Semiconductor Device Reliability/Quality Control System (C10983E)
Semiconductor Device Mounting Technology (C10535E)
M8E 00. 4
The information in this document is current as of June, 2002. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
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patents, copyrights or other intellectual property rights of NEC or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
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