LL1608-FSLR10JB - TOKO - Datasheet.Directory

Rev. 4182O –CA N–0 9/0 8

Features

•80C51 Core Architecture

•256 Bytes of On-chip RAM

•2048 Bytes of On-chip ERAM

•64K Bytes of On-chip Flash Memory

– Data Retention: 10 Years at 85°C

– Read/Write Cycle: 100K

•2K Bytes of On-chip Flash for Bootloader

•2K Bytes of On-chip EEPROM

Read/Write Cycle: 100K

•Integrated Power Monitor (POR: PFD) To Supervise Internal Power Supply

•14-sources 4-level Interrupts

•Three 16-b it T ime rs /Coun ter s

•Full Duplex UART Compatible 80C51

•High-speed Architecture

– In Standard Mode:

40 MHz (Vcc 3V to 5.5V, both Internal and external code execution)

60 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)

– In X2 mode (6 Clocks/machine cycle)

20 MHz (Vcc 3V to 5.5V, both Internal and external code execution)

30 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)

•Five Ports: 32 + 4 Digital I/O Lines

•Five-channel 16-bit PCA with

– PWM (8-bit)

– High-speed Output

– Timer and Edge Capture

•Double Data Pointer

•21-bit WatchDog Timer (7 Programmable Bits)

•A 10-bit Resolution Analog to Digital Converter (ADC) with 8 Multiplexed Inputs

•SPI Interface, (PLCC52 and VPFP64 packages only)

•Full CAN Controller

– Fully Compliant with CAN Rev 2.0A and 2.0B

– Optimized Structure for Communication Management (Via SFR)

– 15 Independent Message Objects

– Each Message Object Programmable on Transmis sion or Recepti on

– Individual Tag and Mask Filters up to 29-bit Identifier/Channel

– 8-byte Cyclic Data Register (FIFO)/Message Object

– 16-bit Status and Control Register/Message Object

– 16-bit Time-Stamping Register/Message Object

– CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message

Object

– Access to Message Object Control and Data Registers Via SFR

– Programmable Reception Buffer Length Up To 15 Message Objects

– Priority Management of Reception of Hits on Several Message Objects at the

Same Time (Basic CAN Feature)

– Priority Management for Transmission

– Mes sage Obje ct Overrun Interru pt

– Supports

– Time Triggered Communication

– Autobaud and Listening Mode

– Programmable Automa tic Reply Mode

– 1-Mbit/s Maximum Transfer Rate at 8 MHz (1) Crystal Frequency in X2 Mode

– Readable Error Counters

– Programmable Link to On-chip Timer for Time Stamping and Network

Synchronization

– Independent Baud Rate Prescaler

– Data, Remote, Error and Overload Frame Handling

1. At BRP = 1 sampling point will be fixed.

Enhanced 8-bit

MCU with CAN

Controller and

Flash Memory

AT89C51CC03

4182O–CAN–09/08

•On-chip Emulation Logic (Enhanced Hook System)

•Power Saving Modes

– Idle Mode

– Power-down Mode

•Power Supply: 3 volts to 5.5 volts

•Te mperature Range: Industrial (-40° to +85°C), Automotive (-40°C to +125°C)

•Packages: VQFP44, PLCC44, VQFP64, PLCC52

Description The AT89C51CC03 is a member of the family of 8-bit microcontrollers dedicated to CAN

network app li ca tion s.

In X2 mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time.

Besides the full CAN controller AT89C51CC03 provides 64K Bytes of Flash memory

including In-System Programming (ISP), 2K Bytes Boot Flash Memory, 2K Bytes

EEPROM and 2048 byte ERAM.

Primary attention is paid to the reduction of the electro-magnetic emission of

AT89C51CC03.

Block Diagram

Notes: 1. 8 analog Inputs/8 Digital I/O

2. 5-Bit I/O Port

Time r 0 INT

RAM

256x8

T1 RxD

TxD

PSEN

ALE

XTAL2

XTAL1

UART

CPU

Time r 1

INT1

Ctrl

INT0

C51

CORE

Port 0

Port 1 Port 2Port 3

Parallel I/O Ports and Ext. Bus

P1(1)

ERAM

2048

IB-bus

PCA

RESET

Watch

Dog

PCA

ECI

Vss

Vcc

Timer2

T2EX

Port 4

P4(2)

Emul

Unit 10 bit

ADC

Flash

64k x

Boot

loader

2kx8

PROM

2kx8 CAN

CONTROLLER

TxDC

RxDC

SPI

Interface

MOSI

SCK

MISO

AT89C51CC03

4182O–CAN–09/08

Pin Configuration

PLCC44

P1.3/AN3/CEX0

P1.2/AN2/ECI

P1.1/AN1/T2EX

P1.0/AN 0/T2

VAREF

VAGND

RESET

VSS

VCC

XTAL1

XTAL2

P3.7/RD

P4.0/ TxD C

P4.1/RxDC

P2.7/A15

P2.6/A14

P2.5/A13

P2.4/A12

P2.3/A11

P2.2/A10

P2.1/A9

P3.6/WR

ALE

PSEN

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.2/AD2

P0.3/AD3

P0.4/AD4

P0.1/AD1

P0.0/AD0

P2.0/A8

P1.4/AN4/CEX1

P1.5/AN5/CEX2

P1.6/AN6/CEX3

P1.7/AN7/CEX4

P3.0/RxD

P3.1/TxD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

43 42 41 40 3944 38 37 36 35 34

12 13 17161514 201918 21 22

VQFP44

P1.4/AN4/CEX1

P1.5/AN5/CEX2

P1.6/AN6/CEX3

P1.7/AN7/CEX4

P3.0/RxD

P3.1/TxD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

ALE

PSEN

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.2 /AD2

P0.3 /AD3

P0.4 /AD4

P0.1 /AD1

P0.0 /AD0

P2.0/A8

P1.3/AN3/CEX0

P1.2/AN2/ECI

P1.1/AN1/T2EX

P1.0/AN 0/T2

VAREF

VAGND

RESET

VSS

VCC

XTAL1

XTAL2

P3.7/RD

P4.0/TxDC

P4.1/RxDC

P2.7/A15

P2.6/A14

P2.5/A13

P2.4/A12

P2.3/A11

P2.2/A10

P2.1/A9

P3.6/WR

AT89C51CC03

4182O–CAN–09/08

2122 26252423 292827 30 31

5 4 3 2 1 6 52 51 50 49 48

PLCC52

7 47

20 32 33

P1.3/AN3/CEX0

P1.2/AN2/ECI

P1.1/AN1/T2EX

P1.0/AN 0/T2

VAREF

VAGND

RESET

VSS

VCC

XTAL1

XTAL2

TESTI

P1.4/AN4/CEX1

P1.5/AN5/CEX2

P1.6/AN6/CEX3

P1.7/AN7/CEX4

P3.0/RxD

P3.1/TxD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1/SS

P4.3/SCK

ALE

PSEN

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.2 /AD2

P0.3 /AD3

P0.4 /AD4

P0.1 /AD1

P0.0 /AD0

P2.0/A8

P4.4/MOSI

P3.7/RD

P4.0/TxDC

P4.1/RxDC

P2.7/A15

P2.6/A14

P2.5/A13

P2.4/A12

P2.3/A11

P2.2/A10

P2.1/A9

P3.6/WR

P4.2/MISO

TESTI must be connected to VSS

VCC

VQFP64

P1.3/AN3/CEX

P1.2/AN2/ECI

P1.1/AN1/T2E

P1.0/AN0/T2

VAREF

VAGND

RESET

VSS

P3.7/RD

P4.0/TxDC

P4.1/RxDC

P2.7/A15

P2.6/A14

P3.6/WR

ALE

PSEN

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

P1.4/AN4/CEX1

P1.5/AN5/CEX2

P1.6/AN6/CEX3

P1.7/AN7/CEX4

P3.0/RxD 11

P4.3/SCK

P3.1/TxD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1/SS

35 P0.1/AD1

P0.2/AD2

P0.3/AD3

P4.4/MOSI

P0.0/AD0

P2.0/A8

P2.5/A13

P2.4/A12

P2.3/A11

P2.2/A10

P2.1/A9

P4.2/MISO

TESTI

VCC

XTAL1

XTAL2

VCC

TESTI must be connected to VSS

AT89C51CC03

4182O–CAN–09/08

Pin Name Type Description

VSS GND Circuit ground

TESTI I Must be connected to VSS

VCC Supply Voltage

VAREF Reference Voltage for ADC

VAGND Reference Ground for ADC

P0.0:7 I/O Port 0:

Is an 8-bit open drain bi-directional I/O port. Port 0 pins that have 1’s written to them float, and in this state can be used as

high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to exte rnal Program

and Data Memory. In this application it uses strong internal pull-ups when emitting 1’s.

Port 0 also outputs the code Bytes during program validation. External pull-ups are required during program verification.

P1.0:7 I/O Port 1:

Is an 8-bit bi-directional I/O port with internal pull-ups. Port 1 pins can be used for digital input/output or as analog inputs for

the Analog Digital Converter (ADC). Port 1 pins that have 1’s written to them are pulled high by the internal pull-up transistors

and can be used as inputs in this state. As inputs, Port 1 pins that are being pulled low externally will be the source of current

(IIL, see section "Electrical Characteristic") because of the internal pull-ups. Port 1 pins are assigned to be used as analog

inputs via the ADCCF register (in this case the internal pull-ups are disconnected).

As a secondary digital function, port 1 contains the Time r 2 external trigger and clock input; the PCA external clock input and

the PCA module I/O.

P1.0/AN0/T2

Analog input channel 0,

External clock input for Timer/counter2.

P1.1/AN1/T2EX

Analog input channel 1,

Trigger input for T imer/counter2.

P1.2/AN2/ECI

Analog input channel 2,

PCA external clock input.

P1.3/AN3/CEX0

Analog input channel 3,

PCA mod ule 0 Entry of input/PWM out put.

P1.4/AN4/CEX1

Analog input channel 4,

PCA mod ule 1 Entry of input/PWM out put.

P1.5/AN5/CEX2

Analog input channel 5,

PCA mod ule 2 Entry of input/PWM out put.

P1.6/AN6/CEX3

Analog input channel 6,

PCA mod ule 3 Entry of input/PWM out put.

P1.7/AN7/CEX4

Analog input channel 7,

PCA mod ule 4 Entry ot input/PWM out put.

Port 1 receives the low-order address byte during EPROM programming and program verification.

It can drive CMOS inputs without external pull-ups.

P2.0:7 I/O Port 2:

Is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins that have 1’s written to them are pulled high by the internal

pull-ups and can be used as inputs in this state. As inputs, Port 2 pins that are being pulled low externally will be a source of

current (IIL, see section "Electrical Characteristic") because of the internal pull-ups. Port 2 emits the high-order address byte

during accesses to the external Program Memory and during accesses to external Data Memory that uses 16-bit addresses

(MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1’s. During accesses to external Data

Memory that use 8 bit addresses (MOVX @Ri), Port 2 transmits the contents of the P2 special function register.

It also receives high-order addresses and control signals during program validation.

It can drive CMOS inputs without external pull-ups.

AT89C51CC03

4182O–CAN–09/08

P3.0:7 I/O Port 3:

Is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1’s written to them are pulled high by the internal

pull-up transistors and can be used as inputs in this state. As inputs, Port 3 pins that are being pulled low externally will be a

source of current (IIL, see section "Electrical Characteristic") because of the internal pull-ups.

The output latch corresponding to a secondary function must be programmed to one for that function to operate (except for

TxD and WR). The secondary functions are assigned to the pins of port 3 as follows:

P3.0/RxD:

Receiver data input (asynchronous) or data input/output (synchronous) of the serial interface

P3.1/TxD:

Transmitter data output (asynchronous) or clock output (synchronous) of the serial interface

P3.2/INT0:

External interrupt 0 input/timer 0 gate control input

P3.3/INT1:

External interrupt 1 input/timer 1 gate control input

P3.4/T0:

Timer 0 counter input

P3.5/T1/SS:

Timer 1 counter input

SPI Slave Select

P3.6/WR:

External Data Memory write strobe; latches the data byte from port 0 into the external data memory

P3.7/RD:

External Data Memory read strobe; Enables the external data memory.

It can drive CMOS inputs without external pull-ups.

P4.0:4 I/O Port 4:

Is an 2-bit bi-directional I/O port with internal pull-ups. Port 4 pins that have 1’s written to them are pulled high by the internal

pull-ups and can be used as inputs in this state. As inputs, Port 4 pins that are being pulled low externally will be a source of

current (IIL, on the datasheet) because of the internal pull-up transistor.

The output latch corresponding to a secondary function RxDC must be programmed to one for that function to operate. The

secondary functions are assigned to the two pins of port 4 as follows:

P4.0/TxDC:

Transmitter output of CAN controller

P4.1/RxDC:

Receiver input of CAN controller.

P4.2/MISO:

Master Input Slave Output of SPI controller

P4.3/SCK:

Serial Clock of SPI controller

P4.4/MOSI:

Master Ouput Slave Input of SPI controller

It can drive CMOS inputs without external pull-ups.

Pin Name Type Description

AT89C51CC03

4182O–CAN–09/08

I/O Configurations Each Port SFR operates via type-D latches, as illustrated in Figure 1 for Ports 3 and 4. A

CPU "wr ite to latc h" signal initi ates tran sfer of internal bus data into the type -D latc h. A

CPU "read latc h" si gn al tran sfe rs the latche d Q outpu t onto the i nterna l bu s. S im ilar ly, a

"read pin" signal transfers the logical level of the Port pin. Some Port data instructions

activat e the "r ead la tch" s ignal while othe rs ac tiva te the "rea d pin" signa l. Latc h inst ruc-

tions are referred to as Read-Modify-Write instructions. Each I/O line may be

independently programmed as input or output.

Port 1, Po rt 3 and Port 4 Figure 1 shows the struc ture of Por ts 1 and 3, wh ich have in terna l pull-up s. An exter nal

source c an pul l the pin l ow. Ea ch P ort pin can be conf igure d eith er for gener al-pu rpose

I/O or for its alternate input output function.

To use a pin for general-purpose output, set or clear the corresponding bit in the Px reg-

ister (x = 1,3 or 4) . To use a pin fo r gener al-purpo se input, set th e bit in t he Px reg ister.

This turns off the output FET drive.

To configur e a pin for its al ternate functi on, set t he bit in the P x register. W hen the l atch

is set, the "a ltern ate out put function " signa l contr ols the output lev el (see Figu re 1). The

operati on o f P or ts 1, 3 an d 4 is di sc uss ed fur the r in the "qu as i-B idi rec tion al Po rt O pera-

tion" section.

RESET I/O Reset:

A high level on this pin during two machine cycles while the oscillator is running resets the device. An internal pull-down

resistor to VSS permits power-on reset using only an external capacitor to VCC.

ALE O

ALE:

An Address Latch Enable output for latching the low byte of the address during accesses to the external memory. The ALE is

activated every 1/6 oscillator periods (1/3 in X2 mode) except during an external data memory access. When instructions are

executed from an internal Flash (EA = 1), ALE generation can be disabled by the software.

PSEN O

PSEN:

The Program Store Enable output is a control signal that enables the external program memory of the bus during external

fetch operations. It is activated twice each machine cycle during fetches from the external program memory. However, when

executing from of the external program memory two activations of PSEN are skipped during each access to the external Data

memory. The PSEN is not activated for internal fetches.

EA I EA:

When External Access is held at the high level, instructions are fetched from the internal Flash. When held at the low level,

AT89C51CC03 fetches all instructions from the external program memory.

XTAL1 I

XTAL1:

Input of the inverting oscillator amplifier and input of the internal clock generator circuits.

To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. To operate

above a frequency of 16 MHz, a duty cycle of 50% should be maintained.

XTAL2 O XTAL2:

Output from the inverting oscillator amplifier.

Pin Name Type Description

AT89C51CC03

4182O–CAN–09/08

Figure 1. Port 1, Port 3 and Port 4 Structur e

Note: The internal pull-up can be disabled on P1 when analog function is selected.

Port 0 and Po rt 2 Ports 0 and 2 are used for general-purpose I/O or as the external address/data bus. Port

0, shown in Figure 3, differs from the other Ports in not having internal pull-ups. Figure 3

shows the structure of Port 2. An external source can pull a Port 2 pin low.

To use a pin for general-purpose output, set or clear the corresponding bit in the Px reg-

ister (x = 0 or 2). To us e a pin for gen eral-p urpose i nput, se t the bit in the Px regi ster to

turn off the output driver FET.

Figure 2. Port 0 Structure

Notes: 1. Port 0 is precluded from use as general-purpose I/O Ports when used as

address/data bus drivers.

2. Port 0 internal s trong pul l-ups assist the logic -one outp ut for m em ory bus c yc les only.

Except for these bus cycles, the pull-up FET is off, Port 0 outputs are open-drain.

QP1.X

LATCH

INTERNAL

WRITE

LATCH

READ

LATCH P1.

P3.X

P4.X

ALTERNATE

OUTPUT

FUNCTION

VCC

INTERNAL

PULL-UP (1)

ALTERNATE

INPUT

FUNCTION

P3.

P4.

BUS

P0.X

LATCH

INTERNAL

WRITE

LATCH

READ

LATCH

1P0.x (1

)

ADDRESS LOW/

DATA CONTROL VDD

BUS

(2)

AT89C51CC03

4182O–CAN–09/08

Figure 3. Port 2 Structure

Notes: 1. Port 2 is preclu ded from use as gen era l-pu rpo se I/O Ports when as address /data bus

drivers.

2. Port 2 internal strong pull-ups FET (P1 in FiGURE) assist the logic-one output for

memory bus cycle.

When Port 0 and Port 2 are used for an external memory cycle, an internal control signal

switches the output-driver input from the latch output to the internal address/data line.

Read-Modify-Write

Instructions Some in structi ons rea d the l atch data r ather th an t he pin data. The latc h bas ed in stru c-

tions rea d the data , m odi fy th e d ata and th en r ewrite th e l atc h. Thes e ar e ca ll ed "Re ad-

Modify-Write" instructions. Below is a complete list of these special instructions (see

Table ). When the destination operand is a Port or a Port bit, these instructions read the

latch rather than the pin:

It is not obvious the last three instructions in this list are Read-Modify-Write instructions.

These instructions read the port (all 8 bits), modify the specifically addressed bit and

P2.X

LATCH

INTERNAL

WRITE

LATCH

READ

LATCH

1P2.x (1)

ADDRESS HIGH/ CONTROL

BUS

VDD

INTERNAL

PULL-UP (2)

Instruction Description Example

ANL logical AND ANL P1, A

ORL l o gical OR ORL P2, A

XRL logical EX-OR XRL P3, A

JBC jump if bit = 1 and clear bit JBC P1.1, LABEL

CPL complement bit CPL P3.0

INC increment INC P2

DEC decrement DEC P2

DJNZ decrement and jump if not zero DJNZ P3, LABEL

MOV Px.y, C move carry bit to bit y of Port x MOV P1.5, C

CLR Px.y clear bit y of Port x CLR P2.4

SET Px.y set bit y of Port x SET P3.3

AT89C51CC03

4182O–CAN–09/08

write the n ew byte back t o the lat ch. Thes e Read-Mo dify- Write ins truct ions are directe d

to the latch rather than the pin in order to avoid possible misinterpretation of voltage

(and ther efore, lo gic) leve ls at th e pin. For exam ple, a Por t bit used t o driv e the ba se of

an exter nal bipolar transis tor can not rise a bove the transistor’s base-emi tter junctio n

voltage (a value lower than VIL). With a logic one written to the bit, attempts by the CPU

to read th e Port at the pin ar e misinter preted as logi c zero. A read of th e latch rath er

than the pins returns the correct logic-one value.

Quasi-Bidirectional Port

Operation Port 1, Port 2, Port 3 and Port 4 have fixed internal pull-ups and are ref erred to as

"quasi -b idir ect ion al " Por ts . Wh en c onf igu red as an i np ut, th e pi n im ped anc e ap pea rs as

logic one and sources current in response to an external logic zero condition. Port 0 is a

"true bidirectional" pin. The pins float when configured as input. Resets write logic one to

all Por t latches. If lo gical zero i s subseque ntly writte n to a Port lat ch, it can be ret urned

to input conditions by a logical one written to the latch.

Note: Port latch values change near the end of Read-Modify-Write instruction cycles. Output

buffers (and therefore the pin state) update early in the instruction after Read-Modify-

Write instruction cycle.

Logical zero-to-one transitions in Port 1, Port 2, Port 3 and Port 4 use an additional pull-

up (p1) to aid this logic transition (see Figure 4.). This increases switch speed. This

extra pull-up sources 100 times normal internal circuit current during 2 oscillator clock

periods. The internal pull-ups are field-effect transistors rather than linear resistors. Pull-

ups consist of three p-channel FET (pFET) devices. A pFET is on when the gate senses

logical zero and off when the gate senses logical one. pF ET #1 is turned on for two

oscillator per iods immediate ly after a zero-to- one transition in the Port latch. A logical

one at the Po rt pin tur ns on pF E T #3 ( a we ak pull- up ) th rough the i nv erter . Thi s inv er ter

and pFET pair form a latch to drive logical one. pFET #2 is a very weak pull-up switched

on whenever the associat ed nFET is switc hed off. This is tradi tional CMO S switch con-

vention. Current strengths are 1/10 that of pFET #3.

Figure 4. Internal Pull-Up Configurations

Note: Port 2 p1 assists the logic-one output for memory bus cycles.

READ PI N

INPUT DATA

P1.

OUTPUT DATA

2 Osc. PERIODS

p1(1) p2 p3

VCCVCCVCC

P2.

P3.

P4.

AT89C51CC03

4182O–CAN–09/08

SFR Mapping The Special Function Registers (SFRs) of the AT89C51CC03 fall into the following

categories:

MnemonicAddName 76543210

ACCE0hAccumulator ––––––––

B F0hB Register ––––––––

PSW D0h Program St atus Word CY AC F0 RS1 RS0 OV F1 P

SP81hStack Pointer ––––––––

DPL 82h Data Pointer Low

byte

LSB of DPTR ––––––––

DPH 83h Data Pointer High

byte

MSB of DPTR ––––––––

MnemonicAddName 76543210

P080hPort 0 ––––––––

P190hPort 1 ––––––––

P2A0hPort 2 ––––––––

P3B0hPort 3 ––––––––

P4 C0h Port 4 (x5) – – – P4.4 /

MOSI P4.3 /

SCK P4.2 /

MISO P4.1 /

RxDC P4 .0 /

TxDC

MnemonicAddName 76543210

TH0 8Ch Timer/Counter 0 High

byte ––––––––

TL0 8Ah Timer/Counter 0 Low

byte ––––––––

TH1 8Dh Timer/Counter 1 High

byte ––––––––

TL1 8Bh Timer/Counter 1 Low

byte ––––––––

TH2 CDh Timer/Counter 2 High

byte ––––––––

TL2 CCh Timer/Counter 2 Low

byte ––––––––

TCON 88h Timer/Counter 0 and

1 control TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

TMOD 89h T imer/Counter 0 and

1 Modes GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00

AT89C51CC03

4182O–CAN–09/08

T2CON C8h Timer/Counter 2

control TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#

T2MOD C9h Timer/Counter 2

Mode ––––––T2OEDCEN

RCAP2H CBh Timer/Counter 2

Reload/Capture High

byte ––––––––

RCAP2L CAh Timer/Counter 2

Reload/Capture Low

byte ––––––––

WDTRST A6h WatchDog Timer

Reset ––––––––

WDTPRG A7h WatchDog Timer

Program –––––S2S1S0

MnemonicAddName 76543210

SCON 98h Serial Control FE/ SM0 SM1 SM2 REN TB8 RB8 TI RI

SBUF99hSerial Data Buffer––––––––

SADEN B9h S l ave Addres s Mask – – – – – – – –

SADDRA9hSlave Address ––––––––

Mnemonic AddName 76543210

CCON D8h PCA Timer/Counter Control CF CR – CCF4 CCF3 CCF2 CCF1 CCF0

CMOD D9h PCA Timer/Counter Mode CIDL WDTE – – – CPS1 CPS0 ECF

CL E9h P CA Timer/Counter Low byte ––––––––

CH F9h PCA Timer/Counter High byte ––––––––

CCAPM0

CCAPM1

CCAPM2

CCAPM3

CCAPM4

DAh

DBh

DCh

DDh

DEh

PCA Timer/Counter Mode 0

PCA Timer/Counter Mode 1

PCA Timer/Counter Mode 2

PCA Timer/Counter Mode 3

PCA Timer/Counter Mode 4

–

ECOM0

ECOM1

ECOM2

ECOM3

ECOM4

CAPP0

CAPP1

CAPP2

CAPP3

CAPP4

CAPN0

CAPN1

CAPN2

CAPN3

CAPN4

MAT0

MAT1

MAT2

MAT3

MAT4

TOG0

TOG1

TOG2

TOG3

TOG4

PWM0

PWM1

PWM2

PWM3

PWM4

ECCF0

ECCF1

ECCF2

ECCF3

ECCF4

CCAP0H

CCAP1H

CCAP2H

CCAP3H

CCAP4H

FAh

FBh

FCh

FDh

FEh

PCA Compare Capture Module 0 H

PCA Compare Capture Module 1 H

PCA Compare Capture Module 2 H

PCA Compare Capture Module 3 H

PCA Compare Capture Module 4 H

CCAP0H7

CCAP1H7

CCAP2H7

CCAP3H7

CCAP4H7

CCAP0H6

CCAP1H6

CCAP2H6

CCAP3H6

CCAP4H6

CCAP0H5

CCAP1H5

CCAP2H5

CCAP3H5

CCAP4H5

CCAP0H4

CCAP1H4

CCAP2H4

CCAP3H4

CCAP4H4

CCAP0H3

CCAP1H3

CCAP2H3

CCAP3H3

CCAP4H3

CCAP0H2

CCAP1H2

CCAP2H2

CCAP3H2

CCAP4H2

CCAP0H1

CCAP1H1

CCAP2H1

CCAP3H1

CCAP4H1

CCAP0H0

CCAP1H0

CCAP2H0

CCAP3H0

CCAP4H0

CCAP0L

CCAP1L

CCAP2L

CCAP3L

CCAP4L

EAh

EBh

ECh

EDh

EEh

PCA Compare Capture Module 0 L

PCA Compare Capture Module 1 L

PCA Compare Capture Module 2 L

PCA Compare Capture Module 3 L

PCA Compare Capture Module 4 L

CCAP0L7

CCAP1L7

CCAP2L7

CCAP3L7

CCAP4L7

CCAP0L6

CCAP1L6

CCAP2L6

CCAP3L6

CCAP4L6

CCAP0L5

CCAP1L5

CCAP2L5

CCAP3L5

CCAP4L5

CCAP0L4

CCAP1L4

CCAP2L4

CCAP3L4

CCAP4L4

CCAP0L3

CCAP1L3

CCAP2L3

CCAP3L3

CCAP4L3

CCAP0L2

CCAP1L2

CCAP2L2

CCAP3L2

CCAP4L2

CCAP0L1

CCAP1L1

CCAP2L1

CCAP3L1

CCAP4L1

CCAP0L0

CCAP1L0

CCAP2L0

CCAP3L0

CCAP4L0

AT89C51CC03

4182O–CAN–09/08

MnemonicAddName 76543210

IEN0 A8h Interrupt Enable

Control 0 EA EC ET2 ES ET1 EX1 ET0 EX0

IEN1 E8h Interrupt Enable

Control 1 – – – – ESPI ETIM EADC ECAN

IPL0 B8h Interrupt Pr io r i ty

Control Low 0 – PPC PT2 PS PT1 PX1 PT0 PX0

IPH0 B7h Interru p t Priorit y

Control High 0 – PPCH PT2H PSH PT1H PX1H PT0H PX0H

IPL1 F8h Interrupt Pr iority

Control Low 1 – – – – SPIL POVRL PADCL PCANL

IPH1 F7h Interrupt Priorit y

Control High1 – – – – SPIH POVRH PADCH PCANH

MnemonicAddName 76543210

ADCON F3h ADC Control – PSIDLE ADEN ADEOC ADSST SCH2 SCH1 SCH0

ADCF F6h ADC Configura tion CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0

ADCLK F2h ADC Cl ock – – – PRS4 PR S3 PRS2 PRS1 P RS0

ADDH F5h ADC Data High byte ADAT9 ADAT8 ADAT7 A DAT6 ADAT5 ADAT4 ADAT3 ADAT2

ADDL F4h ADC Data Low byte – – – – – – ADAT1 ADAT0

MnemonicAddName 76543210

CANGCON ABh C AN General

Control ABRQ OVRQ TTC SYNCTTC AUT–

BAUD TEST ENA GRES

CANGSTA AAh CAN General

Status – OVFG – TBSY RBSY ENFG BOFF ERRP

CANGIT 9Bh CAN General

Interrupt CANIT – OVRTIM OVRBUF SERG CERG FERG AERG

CANBT 1 B4h CAN Bit Timing 1 – BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 –

CANBT2 B5h CAN Bit Timing 2 – SJW1 SJW0 – PRS2 PRS1 PRS0 –

CANBT3 B6h CAN Bit Timing 3 – PHS22 PHS21 PHS20 PHS12 PHS11 PHS10 SM P

CANEN1 CEh CAN Enable

Channel byte 1 – ENCH14 ENCH13 ENCH12 ENCH11 ENCH10 ENCH9 ENCH8

CANEN2 CFh CAN Enable

Channel byte 2 ENCH7 ENCH6 ENCH5 ENCH4 ENCH3 ENCH2 ENCH1 ENCH0

CANGIE C1h CAN General

Interrupt Enable – – ENRX ENTX ENERCH ENBUF ENERG –

CANIE1 C2h CAN Interrupt

Enable Channel

byte 1 – IECH14 IECH13 IECH12 IECH11 IECH10 IECH9 IECH8

AT89C51CC03

4182O–CAN–09/08

CANIE2 C3h CAN Interrupt

Enable Channel

byte 2 IECH7 IECH6 IECH5 IECH4 IECH3 IECH2 IECH1 IECH0

CANSIT1 BAh CAN Status

Interrupt Channel

byte1 – SIT14 SIT13 SIT12 SIT11 SIT10 SIT9 SIT8

CANSIT2 BBh CAN Status

Interrupt Channel

byte2 SIT7 SIT6 SIT5 SIT4 SIT3 SIT2 SIT1 SIT0

CANTCON A1h CAN Timer

Control TPRESC 7 TPRESC 6 TPRESC 5 TPRESC 4 TPRESC 3 TPRESC 2 TPRESC 1 TPRESC 0

CANTIMH ADh CAN Timer high CANTIM

15 CANTIM

14 CANTIM

13 CANTIM

12 CANTIM

11 CANTIM

10 CANTIM 9 CANTIM 8

CANTIML ACh CAN Timer low CANTIM 7 CANTIM 6 CANTIM 5 CANTIM 4 CANTI M 3 C A NT IM 2 CANTIM 1 CANT I M 0

CANSTMP

HAFh CAN Timer Stamp

high TIMSTMP

15 TIMSTMP

14 TIMSTMP

13 TIMSTMP

12 TIMSTMP

11 TIMSTMP

10 TIMSTMP

9TIMSTMP

CANSTMP

LAEh C AN Timer Stamp

low TIMSTMP7 TIMSTMP

6TIMSTMP

5TIMSTMP

4TIMSTMP

3TIMSTMP

2TIMSTMP

1TIMSTMP

CANTTCH A5h CAN Timer TTC

high TIMTTC 15 TIMTTC 14 TIMTTC 13 TIMTTC 12 TIMTTC 11 TIMTTC 10 TIMTTC

9TIMTTC

CANTTCL A4h C AN Timer TTC

low TIMTTC

7TIMTTC

6TIMTTC

5TIMTTC

4TIMTTC

3TIMTTC

2TIMTTC

1TIMTTC

CANTEC 9Ch CAN Transmit

Error Counter TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0

CANREC 9Dh C AN Receive

Error Counter REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0

CANPAGE B1h CAN Page CHNB3 CHNB2 CHNB1 CHNB0 AINC INDX2 INDX1 INDX0

CANSTCH B2h CAN Status

Channel DLCW TXOK RXOK BERR SERR CERR FERR AERR

CANCONC

HB3h CAN Control

Channel CONCH1 CONCH0 RPLV IDE DLC3 DLC2 DLC1 DLC0

CANMSG A3h CAN Message

Data MSG7 MSG6 MSG5 MSG4 MSG3 MSG2 MSG1 MSG0

CANIDT1 BCh

CAN Identifier Tag

byte 1(Part A) IDT10 IDT9 IDT8 IDT7 IDT6 IDT5 IDT4 IDT3

CAN Identifier Tag

byte 1(PartB) IDT28 IDT27 IDT26 IDT25 IDT24 IDT23 IDT22 IDT21

CANIDT2 BDh

CAN Identifier Tag

byte 2 (PartA)

CAN Identifier Tag

byte 2 (PartB)

IDT2

IDT20

IDT1

IDT19

IDT0

IDT18

–

IDT17

–

IDT16

–

IDT15

–

IDT14

–

IDT13

CANIDT3 BEh

CAN Identifier Tag

byte 3(PartA)

CAN Identifier Tag

byte 3(PartB)

–

IDT12

–

IDT11

–

IDT10

–

IDT9

–

IDT8

–

IDT7

–

IDT6

–

IDT5

MnemonicAddName 76543210

AT89C51CC03

4182O–CAN–09/08

CANIDT4 BFh

CAN Identifier Tag

byte 4(PartA)

CAN Identifier Tag

byte 4(PartB)

–

IDT4

–

IDT3

–

IDT2

–

IDT1

–

IDT0 RTRTAG –

RB1TAG RB0TAF

CANIDM1 C4h

CAN Identifier

Mask byte

1(PartA)

CAN Identifier

Mask byte

1(PartB)

IDMSK10

IDMSK28

IDMSK9

IDMSK27

IDMSK8

IDMSK26

IDMSK7

IDMSK25

IDMSK6

IDMSK24

IDMSK5

IDMSK23

IDMSK4

IDMSK22

IDMSK3

IDMSK21

CANIDM2 C5h

CAN Identifier

Mask byte

2(PartA)

CAN Identifier

Mask byte

2(PartB)

IDMSK2

IDMSK20

IDMSK1

IDMSK19

IDMSK0

IDMSK18

–

IDMSK17

–

IDMSK16

–

IDMSK15

–

IDMSK14

–

IDMSK13

CANIDM3 C6h

CAN Identifier

Mask byte

3(PartA)

CAN Identifier

Mask byte

3(PartB)

–

IDMSK12

–

IDMSK11

–

IDMSK10

–

IDMSK9

–

IDMSK8

–

IDMSK7

–

IDMSK6

–

IDMSK5

CANIDM4 C7h

CAN Identifier

Mask byte

4(PartA)

CAN Identifier

Mask byte

4(PartB)

–

IDMSK4

–

IDMSK3

–

IDMSK2

–

IDMSK1

–

IDMSK0 RTRMSK – IDEMSK

MnemonicAddName 76543210

SPCON D4h SPI Control SPR2 SPEN SSDIS MSTR CPOL CPHA S PR1 SPR0

SPSCR D5h SPI S tatus and

Control SPIF - OVR MODF SPTE UARTM SPTEIE MOFIE

SPDATD6hSPI Data --------

MnemonicAddName 76543210

PCON 87h Power Control SMOD1 SMOD0 – POF GF1 GF0 PD IDL

AUXR 8Eh Auxiliary Register 0 DPU VPFDP M0 XRS2 X RS1 XRS0 EXTRAM A0

AUXR1 A2h Auxiliary Register 1 – – ENBOOT – GF3 0 – DPS

CKCON0 8Fh Clock Control 0 CANX2 WDX2 PCAX 2 SIX2 T2X2 T 1X2 T0X2 X2

CKCON1 9Fh Clock Control 1 - - - - - - - SPIX2

FCON D1h Flash Control FPL3 FPL2 FPL1 FPL0 FPS FMOD1 FMOD0 FBUSY

EECON D2h EEPROM Contol EEPL3 EEPL2 EEPL1 EEPL0 – – EEE EEBUSY

FSTA D3 Flash Status - - - - - - SEQERR FLOAD

AT89C51CC03

4182O–CAN–09/08

Reserved

Note: 1. Do not read or write Reserved Registers

2. These registers are bit–addressable.

Sixteen addresses in the SFR space are both byte–addressable and bit–addressable. The bit–addressable SFR’s are those

whose address ends in 0 and 8. The bit addresses, in this area, are 0x80 through to 0xFF.

Table 1. SFR Mapping

0/8(2) 1/9 2/A 3/B 4/C 5/D 6/E 7/F

F8h IPL1

xxxx x000 CH

0000 0000 CCAP0H

0000 0000 CCAP1H

0000 0000 CCAP2H

0000 0000 CCAP3H

0000 0000 CCAP4H

0000 0000 FFh

F0h B

0000 0000 ADCLK

xxx0 0000 ADCON

x000 0000 ADDL

0000 0000 ADDH

0000 0000 ADCF

0000 0000 IPH1

xxxx x000 F7h

E8h IEN1

xxxx x000 CL

0000 0000 CCAP0L

0000 0000 CCAP1L

0000 0000 CCAP2L

0000 0000 CCAP3L

0000 0000 CCAP4L

0000 0000 EFh

E0h ACC

0000 0000 E7h

D8h CCON

0000 0000 CMOD

00xx x000 CCAPM0

x000 0000 CCAPM1

x000 0000 CCAPM2

x000 0000 CCAPM3

x000 0000 CCAPM4

x000 0000 DFh

D0h PSW

0000 0000 FCON

0000 0000 EECON

xxxx xx00 FSTA

xxxx xx00 SPCON

0001 0100 SPSCR

0000 0000 SPDAT

xxxx xxxx D7h

C8h T2CON

0000 0000 T2MOD

xxxx xx00 RCAP2L

0000 0000 RCAP2H

0000 0000 TL2

0000 0000 TH2

0000 0000 CANEN1

x000 0000 CANEN2

0000 0000 CFh

C0h P4

xxx1 1111 CANGIE

xx00 000x CANIE1

x000 0000 CANIE2

0000 0000 CANIDM1

xxxx xxxx CANIDM2

xxxx xxxx CANIDM3

xxxx xxxx CANIDM4

xxxx xxxx C7h

B8h IPL0

x000 0000 SADEN

0000 0000 CANSIT1

0000 0000 CANSIT2

0000 0000 CANIDT1

xxxx xxxx CANIDT2

xxxx xxxx CANIDT3

xxxx xxxx CANIDT4

xxxx xxxx BFh

B0h P3

1111 1111 CANPAGE

0000 0000 CANSTCH

xxxx xxxx CANCONCH

xxxx xxxx CANBT1

xxxx xxxx CANBT2

xxxx xxxx CANBT3

xxxx xxxx IPH0

x000 0000 B7h

A8h IEN0

0000 0000 SADDR

0000 0000 CANGSTA

x0x0 0000 CANGCON

0000 0x00 CANTIML

0000 0000 CANTIMH

0000 0000 CANSTMPL

0000 0000 CANSTMPH

0000 0000 AFh

A0h P2

1111 1111 CANTCON

0000 0000 AUXR1

xxxx 00x0 CANMSG

xxxx xxxx CANTTCL

0000 0000 CANTTCH

0000 0000 WDTRST

1111 1111 WDTPRG

xxxx x000 A7h

98h SCON

0000 0000 SBUF

0000 0000 CANGIT

0x00 0000 CANTEC

0000 0000 CANREC

0000 0000 CKCON1

xxxx xxx0 9Fh

90h P1

1111 1111 97h

88h TCON

0000 0000 TMOD

0000 0000 TL0

0000 0000 TL1

0000 0000 TH0

0000 0000 TH1

0000 0000 AUXR

x001 0100 CKCON0

0000 0000 8Fh

80h P0

1111 1111 SP

0000 0111 DPL

0000 0000 DPH

0000 0000 PCON

00x1 0000 87h

0/8(2) 1/9 2/A 3/B 4/C 5/D 6/E 7/F

AT89C51CC03

4182O–CAN–09/08

Clock T he AT89C51CC03 c ore needs on ly 6 clo ck periods per machine cycle. Thi s feature,

called”X2”, provides the following advantages:

• Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU

power.

• Saves power consumption while keeping the same CPU power (oscillator power

saving).

• Saves power consumption by dividing dynamic operating frequency by 2 in

operating and idle modes.

• Increases CPU power by 2 while keeping the same crystal frequency.

In order to ke ep the origin al C51 compat ibility, a div ider-by-2 is inserted be tween the

XTAL1 signal and the main clock input of the core (phase generator). This divider may

be disabled by the software.

An extra feature is available to start after Reset in the X2 mode. This feature can be

enabled by a bit X2B in the Hardwar e Security Byte. T his bit is descri bed in the sectio n

"In-System Programming".

Description The X2 bit in the CKCON register (see Table 2) allows switching from 12 clock cy cles

per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated

(STD mode).

Setting this bit activates the X2 feature (X2 mode) for the CPU Clock only (see Figure

5.).

The Timers 0, 1 an d 2, Ua rt , PCA , Wa tc hDog or CAN s witc h in X2 mod e onl y if the co r-

responding bit is cleared in the CKCON register.

The clock for the whole circuit and peripheral is first divided by two before being used by

the CPU core and peripherals. This allows any cyclic ratio to be accepted on the XTAL1

input. In X2 mod e, as thi s div id er is by pas s ed, t he s ignal s o n XT A L1 m us t hav e a cycl ic

ratio between 40 to 60%. Figure 5. shows the clock generation block diagram. The X2

bit is validated on the XTAL1÷2 rising edge to avoid glitches when switching from the X2

to the STD mode. Figure 6 shows the mode switching waveforms.

AT89C51CC03

4182O–CAN–09/08

Figure 5. Clock CPU Generation Diagram

TAL1

TAL2

PCON.1

CPU Core

÷ 2

PERIPH

CLOCK

Clock

Peripheral

CPU

CLOCK

CPU Core Clock Symbol

CKCON.0

X2B

Hardware byte

CANX2

CKCON0.7 WDX2

CKCON0.6 PCAX2

CKCON0.5 SIX2

CKCON0.4 T2X2

CKCON0.3 T1X2

CKCON0.2 T0X2

CKCON0.1

IDL

PCON.0

÷ 2

CKCON.0

FCan Clock

FWd Clock

FPc a Clock

FUart Clock

FT2 Clock

FT1 Clock

FT0 Clock

and ADC

On RESET

÷ 2FSPIClock

SPIX2

CKCON1.0 Clock Symbol

AT89C51CC03

4182O–CAN–09/08

Figure 6. Mode Switching Waveforms

Note: In order to prevent any incorrect operation while operating in the X2 mode, users must be aware that all peripherals using the

clock frequency as a time reference (UART, timers...) will have their time reference divided by two. For example a free running

timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. A UART with a 4800 baud rate will have

a 9600 baud rate.

XTAL1/2

XTAL1

CPU clock

X2 bit

X2 ModeSTD Mode STD Mode

AT89C51CC03

4182O–CAN–09/08

Registers Table 2. CKCON0 Register

CKCON0 (S:8Fh)

Clock Control Register

Note: 1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit

has no effect.

Reset Value = 0000 0000b

76543210

CANX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2

Bit

Number Bit

Mnemonic Description

7CANX2

CAN clock (1)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

6WDX2

WatchDog clock (1)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

5PCAX2

Program m a ble Counter Array cl oc k (1)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

4SIX2

Enhanced UART clock (MODE 0 and 2) (1)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

3T2X2

Timer2 clock (1)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

2T1X2

Timer1 clock (1)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

1T0X2

Timer0 clock (1)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

0X2

CPU clock

Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all

the peripherals.

Set to select 6 clock periods per machine cycle (X2 mode) and to enable the

individual peripherals "X2"bits.

AT89C51CC03

4182O–CAN–09/08

Table 3. CKCON1 Register

CKCON1 (S:9Fh)

Clock Control Register 1

Note: 1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit

has no effect.

Reset Value = 0000 0000b

76543210

SPIX2

Bit

Number Bit

Mnemonic Description

7-1 - Reserved

The value read from these bits is indeterminate. Do not set these bits.

0 SPIX2

SPI clock (1)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

AT89C51CC03

4182O–CAN–09/08

Data Memory The AT89C51CC03 provides data memory access in two different spaces:

1. The internal space mapped in three separate segments:

• the lower 128 Bytes RAM segment.

• the upper 128 Bytes RAM segment.

• the expanded 2048 Bytes RAM segment (ERAM).

2. The external space.

A fourth internal segment is available but dedicated to Special Function Registers,

SFRs, (addres se s 80h to FFh) accessible by direct addressing mode.

Figure 8 shows the internal and external data memory spaces organization.

Figure 7. Internal Memory - RAM

Figure 8. Internal and External Data Memory Organization ERAM-XRAM

Upper

128 Bytes

Internal RAM

Lower

128 Bytes

Internal RAM

Special

Function

Registers

80h 80h

00h

FFh FFh

direct addressing

addressing

7Fh

direct or indirect

indirect addressing

256 up to 2048 Bytes

00h

64K Bytes

External XRAM

0000h

FFFFh

Internal ERAM

EXTRAM = 0 EXTRAM = 1

FFh or 7FFh

Internal External

AT89C51CC03

4182O–CAN–09/08

Internal Space

Lower 128 Bytes RAM The lower 128 Bytes of RAM (see Figure 8) are accessible from address 00h to 7Fh

using direct or indire ct addressing modes. The lowest 32 Bytes are gro uped into 4

banks of 8 registers (R0 to R7). Two bits RS0 and RS1 in PSW register (see Figure 6)

select wh ich ba nk is in use accord ing to T able 4. This allo ws mor e effic ient use of code

space, since register instructions are shorter than instructions that use direct address-

ing, and can be used for context switching in interrupt service routines.

Table 4. Register Bank Selection

The next 16 Bytes above the register banks form a block of bit-addressable memory

space. The C51 instruction set includes a wide selection of single-bit instructions, and

the 128 bits in this area can be directly addressed by these instructions. The bit

addresses in this area are 00h to 7Fh.

Figure 9. Lower 128 Bytes Internal RAM Organization

Upper 128 Bytes RAM The upper 128 Bytes of RAM are accessible from address 80h to FFh using only indirect

addressing mode.

Expanded RAM The on -chi p 204 8 B y tes o f e xpanded RAM ( E RAM ) ar e ac ces sibl e f ro m add re ss 0 000 h

to 07FFh using indirect addressing mode through MOVX instru ctions. In this address

range, the bit EXTRAM in AUXR register is used to select the ERAM (default) or the

XRAM. As shown in Figure 8 when EXTRAM = 0, the ERAM is selected and when

EXTRAM = 1, the XRAM is selected.

The size of ERAM can be configured by XRS2-0 bit in AUXR register (default size is

2048 Bytes).

Note: Lower 128 Bytes RAM, Upper 128 Bytes RAM, and expanded RAM are made of volatile

memory cells. This means that the RAM content is indeterminate after power-up and

must then be initialized properly.

RS1 RS0 Description

0 0 Register bank 0 from 00h to 07h

0 1 Register bank 0 from 08h to 0Fh

1 0 Register bank 0 from 10h to 17h

1 1 Register bank 0 from 18h to 1Fh

Bit-Addressable Space

4 Banks of

8 Registers

R0-R7

30h

7Fh

(Bit Addresses 0-7Fh)

20h

2Fh

18h 1Fh

10h 17h

08h 0Fh

00h 07h

AT89C51CC03

4182O–CAN–09/08

External Space

Memory Interface The external memory interface comprises the external bus (port 0 and port 2) as well as

the bus control signals (RD#, WR#, and ALE).

Figure 10 s hows the structure of the external address bus. P0 c arries address A7:0

while P2 carri es addres s A15:8. Data D7:0 i s multipl exed with A7:0 on P0 . Table 5

describes the external memory interface signals.

Figure 10. External Data Memory Interface Structure

Table 5. External Data Memory Interface Signals

External Bu s Cycles This section describes the bus cycles the AT89C51CC03 executes to read (see

Figure 11), and write data (see Figure 12) in the external data memory.

External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator

clock period in standard mode or 6 oscillator clock periods in X2 mode. For further infor-

mation on X2 mode.

Slow per ipheral s can be acces sed b y stretchi ng the r ead and write cycles. T his is done

using the M0 bit in AUXR register. Setting this bit changes the width of the RD# and

WR# signals from 3 to 15 CPU clock periods.

For simplicity, the accompanying figures depict the bus cycle waveforms in idealized

form and do not provide precise timing information. For bus cycle timing parameters

refer to the Section “AC Characteristics” of the AT89C51CC03 datasheet.

Signal

Name Type Description Alternative

Function

A15:8 O Address Lines

Upper address lines for the external bus. P2.7:0

AD7:0 I/O Address/Data Lines

Multiplexed lower address lines and data for the external

memory. P0.7:0

ALE O Address Latch Enable

ALE signals indicates that valid address information are available

on lines AD7:0. -

RD# O Read

Read signal output to external data memory. P3.7

WR# O Write

Write signal output to external memory. P3.6

RAM

PERIPHERAL

AT89C51CC03

P0 AD7:0

A15:8

A7:0

A15:8

D7:0

A7:0

ALE

OERD#

WR#

Latch

AT89C51CC03

4182O–CAN–09/08

Figure 11 . External Data Read Waveforms

Notes: 1. RD# signal may be stretched using M0 bit in AUXR register.

2. When executing MOVX @Ri instruction, P2 outputs SFR content.

Figure 12. External Data Write Waveforms

Notes: 1. WR# signal may be stretched using M0 bit in AUXR register.

2. When executing MOVX @Ri instruction, P2 outputs SFR content.

ALE

RD#1

DPL or Ri D7:0

DPH or P22

CPU Clock

ALE

WR#1

DPL or Ri D7:0

CPU Clock

DPH or P22

AT89C51CC03

4182O–CAN–09/08

Dual Data Pointer

Description The AT89C51CC03 implements a seco nd data pointer for speeding up code execution

and reducing code size in case of intensive usage of external memory accesses.

DPTR 0 and DPTR 1 are see n by the CP U as DPTR and are ac cess ed using the SFR

addresses 83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1

pointer 1 (see Figure 13).

Figure 13. Dual Data Pointer Implementation

Application Software can take advantage of the additional data pointers to both increase speed and

reduce code size, for example, block operations (copy, compare…) are well served by

using one data pointer as a “source” pointer and the other one as a “destination” pointer.

Hereafter is an example of block move implementation using the two pointers and coded

in asse mbler. The latest C compiler takes a lso advantag e of thi s feature b y providin g

enhanced algorithm libraries.

The INC instruction is a short (2 Bytes) and fast (6 machine cycle) way to manipulate the

DPS bit in the AUXR 1 reg ister. H owever, note that th e INC i nstruc tion do es not d irectly

force the DPS bit to a particular state, but simply toggles it . In simple routines, such as

the bloc k mov e exa mple, onl y the f act tha t DPS i s tog gled i n the pro per s equence m at-

ters, not its actual value. In other words, the block move routine works the same whether

DPS is '0' or '1' on entry.

; A SCI I block move using dual data pointers

; Modifies DPTR0, DPTR1, A and PSW

; Ends when encountering NULL character

; Note: DPS exits opposite to the entry stat e unless an extra INC AUXR1 is added

AUXR1EQU0A2h

move:movDPTR,#SOURCE ; address of SOURCE

incAUXR1 ; switch data pointers

movDPTR,#DEST ; address of DEST

mv_loop:incAUXR1; switch data pointers

movxA,@DPTR; get a byte from SOURCE

incDPTR; increment SOURCE address

incAUXR1; switch data pointers

movx@DP TR,A; write the byte to DEST

incDPTR; increment DEST address

jnzmv_loop; check for NULL terminator

end_move:

DPH0

DPH1

DPL0

DPS AUXR1.0

DPH

DPL

DPL1

DPTR

DPTR0

DPTR1

AT89C51CC03

4182O–CAN–09/08

Registers Table 6. PSW Register

PSW (S:8Eh)

Program Status Word Register

Reset Value = 0000 0000b

Table 7. AUXR Register

AUXR (S:8Eh)

Auxiliary Register

76543210

CY AC F0 RS1 RS0 OV F1 P

Bit

Number Bit

Mnemonic Description

7CY

Carry Flag

Carry out from bit 1 of ALU operands.

6AC

Auxiliary Carry Flag

Carry out from bit 1 of addition operands.

5F0User Definable Flag 0.

4-3 RS1:0 Register Bank Select Bits

Refer to Table 4 for bits description.

2OV

Overflow Flag

Overflow set by arithmetic operations.

1F1User Definable Flag 1

Parity Bit

Set when ACC contains an odd number of 1’s.

Cleared when ACC contains an even number of 1’s.

76543210

- - M0 XRS2 XRS1 XRS0 EXTRAM A0

Bit

Number Bit

Mnemonic Description

7-6 - Reserved

The value read from these bits are indeterminate. Do not set this bit.

5M0

Stret c h MOVX control:

the RD/ and the WR/ pulse length is increased according to the value of M0.

M0 Pulse length in clock period

0 6

1 30

AT89C51CC03

4182O–CAN–09/08

Reset Value = X001 0100b

Not bit address ab le

Table 8. AUXR1 Register

AUXR1 (S:A2h)

Auxiliary Control Register 1

Reset Val ue = XXXX 00X0b

4-2 XRS1-0

ERAM size:

Accessible size of the ERAM

XRS 2:0 ERAM size

000 256 Bytes

001 512 Bytes

010 768 Bytes

011 1024 Bytes

100 1792 Bytes

101 2048 Bytes (default configuration after reset)

110 Reserved

111 Reserved

1EXTRAM

Internal/External RAM (00h - FFh)

access using MOVX @ Ri/@ DPTR

0 - Internal ERAM access using MOVX @ Ri/@ DPTR.

1 - External data memory access.

0A0

Disable/Enable ALE)

0 - ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2

mode is used)

1 - ALE is active only during a MOVX or MOVC instruction.

76543210

- - ENBOOT - GF3 0 - DPS

Bit

Number Bit

Mnemonic Description

7-6 - Reserved

The value read from these bits is indeterminate. Do not set these bits.

5 ENBOOT Enable Boot Fla s h

Set this bit for map the boot Flash between F800h -FFFFh

Clear this bit for disable boot Flash.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

3GF3General-purpose Flag 3

Always Zero

This bit is stuck to logic 0 to allow INC AUXR1 instruction without affecting GF3

flag.

1-Reserved for Data Pointer Extension.

0DPS

Data Pointer Select Bi t

Set to select second dual data pointer: DPTR1.

Clear to select first dual data pointer: DPTR0.

Bit

Number Bit

Mnemonic Description

AT89C51CC03

4182O–CAN–09/08

Power Monitor The POR/PFD function monitors the internal power-supply of the CPU core memories

and the peripherals, and if needed, suspends their activity when the internal power sup-

ply falls below a safety threshold. This is achieved by applying an internal reset to them.

By generating the Reset the Power Monitor insures a correct start up when

AT89C51CC03 is powered up.

Description In order to startup and maintain the microcontroller in correct operating mode, VCC has

to be stabi lized in the VCC opera ting rang e and the oscil lator has to be stabilize d with a

nominal amplitude compatible with logic level VIH/VIL.

These parameters are controlled during the three phases: power-up, normal operation

and power going down. See Figure 14.

Figure 14. Power Monitor Block Diagram

Note: 1. Once XTAL1 high and lo w le vel s reac h abo ve an d b elow VIH/VIL a 102 4 c lo ck pe rio d

delay will exten d the re set co ming from the Powe r Fail Det ect. If the pow er fal ls below

the Power Fail Detect thresthold level, the reset will be applied immediately.

The Voltag e r egu la tor gen erate s a re gulate d i nter na l sup ply fo r t he CPU c or e th e m em-

ories an d the peripherals. Spikes on th e external Vcc are smoothed by the voltage

regulator.

The Powe r fail d etect monit or the s upply gener ated by th e volta ge regula tor and g ener-

ate a reset if this supply falls below a safety threshold as illustrated in the Figure 15.

VCC

Power On Reset

Power Fail Detect

Voltage Regulator

XTAL1 (1)

CPU core

Memories

Peripherals

Regulated

Supply

RST pin

Hardware

Watchdog

PCA

Watchdog

Internal Reset

AT89C51CC03

4182O–CAN–09/08

Figure 15. Power Fail Detect

When the powe r is applied, the Power Mo nitor immediately a sserts a re set. Once the

internal supply after the voltage regulator reach a safety level, the power monitor then

looks a t the XT AL cl oc k inp ut. The inter nal res et wi ll re mai n ass er ted unti l th e X tal 1 le v-

els are above and below VIH and VIL. F urthe r mor e. An interna l co unte r wil l co unt 102 4

clock periods before the reset is de-asserted.

If the internal power supply falls below a safety level, a reset is immediately asserted.

Vcc

Reset

Vcc

AT89C51CC03

4182O–CAN–09/08

Reset

Introduction The reset s ources are : Power Manag ement, Har dware Wa tchdog , PCA Watc hdog an d

Reset input.

Figure 16. Reset Schematic

Reset Input The Reset input can be used to force a reset pulse longer than the internal reset con-

trolled by the Po wer M onitor. RST input has a pull-down resistor allowing power -on

reset by simply connecting an external capacitor to VCC as shown in Figure 17. Resistor

value an d input cha racteri stics ar e discuss ed in the Se ction “D C Charact eristic s” of the

AT89 C5 1C C 03 da t a sh eet . Th e st a tu s of t h e Po rt pi ns d u rin g re se t i s det a il ed i n Ta bl e 9.

Figure 17. Reset Circuitry and Power-On Reset

Power

Monitor

Hardware

Watchdog

PCA

Watchdog

RST

Internal Reset

RST

RRST

VSS

To internal reset

RST

VDD

b. Power-on Rese

a. RST input circuitry

AT89C51CC03

4182O–CAN–09/08

Reset Output

As detailed in Section “Watchdog Timer”, page 81, the WDT generates a 96-clock

period pul se on t he RS T p in. In order to prop erly p ropagat e this pu lse to th e re st of the

application in case of external capacitor or power-supply supervisor circuit, a 1 kΩ resis-

tor must be added as shown Figure 18.

Figure 18. Recommended Reset Output Schematic

RST

VDD

VSS

VDD

RST

To other

on-board

circuitry

AT89C51CC03

4182O–CAN–09/08

Power Management

Introduction Two power reduction modes are implemented in the AT89C51CC03. The Idle mode and

the Power -Down mo de. These mo des are de tailed in t he following sectio ns. In addit ion

to these pow er r edu cti on mo des , t he cl oc ks o f the core and pe ri phe rals c an be dy nam i-

cally divided by 2 using the X2 mode detailed in Section “Clock”, page 17.

Idle Mode Idle mode is a power reduction mode that reduces the power consumption. In this mode,

progra m execution halts . Idle mode freezes the clock to the CPU at kn own states while

the peripherals continue to be clocked. The CPU status before entering Idle mode is

preserved, i.e., the program counter and program status word register retain their data

for the du ratio n of Idle mode. Th e conte nts of t he SFRs and RAM are als o ret ained. Th e

status of the Port pins during Idle mode is detailed in Table 9.

Entering Idle Mode To enter Idle mode, set the IDL bit in PCON register (see Table 10). The AT89C51CC03

enters I dle mod e up on execut ion of th e in structi on that s ets ID L bit. T he inst ructio n that

sets IDL bit is the last instruction executed.

Note: If IDL bit and PD bit are set simultaneously, the AT89C51CC03 enters Power-Down

mode. Then it does not go in Idle mode when exiting Power-Down mode.

Exiting Idle Mode There are two ways to exit Idle mode:

1. Generate an enabled interrupt.

– Hardware clears IDL bit in PCON register which restores the clock to the

CPU. Execution resumes with the interrupt service routine. Upon completion

of the interrupt service routine, program execution resumes with the

instruction immediately following the instruction that activated Idle mode.

The general purpose flags (GF1 and GF0 in PCON register) may be used to

indicate whether an interrupt occurred during normal operation or during Idle

mode. When Idle mode is exited by an interrupt, the interrupt service routine

may examine GF1 and GF0.

2. Generate a reset.

– A logic high on the RST pin clears IDL bit in PCON register directly and

asynchronously. This restores the clock to the CPU. Program execution

momentarily resumes with the instruction immediately following the

instruction that activated the Idle mode and may continue for a number of

clock cycles before the internal reset algorithm takes control. Reset

initializes the AT89C51CC03 and vectors the CPU to address C:0000h.

Note: During the tim e tha t ex ecu tio n res um es , the in ternal RAM cann ot be acc es sed; how e ve r,

it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port

pins, the instruction immediately following the instruction that activated Idle mode should

not write to a Port pin or to the external RAM.

Power-Down Mode The Powe r-Down mode places the AT89C51 CC03 in a very low powe r state. Power-

Down mode stops the osci ll ator, fr eez es all cl oc k at known states . The CPU st atus prior

to entering Power-Down mode is preserved, i.e., the program counter, program status

word register retain their data for the duration of Power-Down mode. In addition, the SFR

and RAM contents are preserved. The status of the Port pins during Power-Down mode

is detailed in Table 9.

Note: VCC may be reduced to as low as VRET during Power-Down mode to further reduce

power dissipation. Take care, howev er, that VDD is not reduced until Power-Down mode

is invoked.

AT89C51CC03

4182O–CAN–09/08

Entering Power-Down Mode To enter P ower-Down mode, set PD bit in PCON register. The AT89C51CC03 enters

the Power-Down mode upon execution of the instruction that sets PD bit. The instruction

that sets PD bit is the last instruction executed.

Exiting Power-Down Mode Note: If VCC was reduced during the Power-Down mode, do not exit Power-Down mode until

VCC is restored to the normal operating level.

There are two ways to exit the Power-Down mode:

1. Generate an enabled external interrupt.

– The AT89C51CC03 provides capability to exit from Power-Down using

INT0#, INT1#.

Hardware clears PD bit in PCON register which starts the oscillator and

restores the clocks to the CPU and peripherals. Using INTx# input,

execution resumes when the input is released (see Figure 19). Execution

resumes with the interrupt service routine. Upon completion of the interrupt

service routine, program execution resumes with the instruction immediately

following the instruction that activated Power-Down mode.

Note: The external interrupt used to exit Power-Down mode must be configured as level sensi-

tive (INT0# and INT1#) and must be assigned the highest priority. In addition, the

duration of the interrupt must be long enough to allow the oscillator to stabilize. The exe-

cution will only resume when the interrupt is deasserted.

Note: Exit fr om pow e r-down by extern al i nte rrupt does not a f f ect the SFRs nor the internal RAM

content.

Figure 19. Power-Down Exit Waveform Using INT1:0#

2. Generate a reset.

– A logic high on the RST pin clears PD bit in PCON register directly and

asynchronously. This starts the oscillator and restores the clock to the CPU

and peripherals. Program execution momentarily resumes with the

instruction immediately following the instruction that activated Power-Down

mode and may continue for a number of clock cycles before the internal

reset algorithm takes control. Reset initializes the AT89C51CC03 and

vectors the CPU to address 0000h.

Note: During the tim e tha t ex ecu tio n res um es , the in ternal RAM cann ot be acc es sed; how e ve r,

it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port

pins, the instruction immediately following the instruction that activated the Power-Down

mode should not write to a Port pin or to the external RAM.

Note: Exit from power-down by reset redefines all the SFRs, but does not affect the internal

RAM content.

INT1:0#

OSC

Power-down phase Oscillator restart phase Active phaseActive phase

AT89C51CC03

4182O–CAN–09/08

Table 9. Pin Conditions in Special Operating Modes

Mode Port 0 Port 1 Port 2 Port 3 Port 4 ALE PSEN#

Reset Floating High High High High High High

Idle

(internal

code) Data Data Data Data Data High High

Idle

(external

code) Floating Data Data Data Data High High

Power-

Down(inter

nal code) Data Data Data Data Data Low Low

Power-

Down

(external

code)

Floating Data Data Data Data Low Low

AT89C51CC03

4182O–CAN–09/08

Registers Table 10. PCON Register

PCON (S87:h) Power configuration Register

Rese t Value= XXXX 0000b

76543210

----GF1GF0PD IDL

Bit

Number Bit

Mnemonic Description

7-4 - Reserved

The value read from these bits is indeterminate. Do not set these bits.

3GF1

General Purpose flag 1

One use is to indicate whether an interrupt occurr ed during normal operation or

during Idle mode.

2GF0

General Purpose flag 0

One use is to indicate whether an interrupt occurr ed during normal operation or

during Idle mode.

1PD

Power-Down Mode bit

Cleared by hardware when an interrupt or reset occurs.

Set to activate the Power-Down mode.

If IDL and PD are both set, PD takes precedence.

0IDL

Idle Mode bit

Cleared by hardware when an interrupt or reset occurs.

Set to activate the Idle mode.

If IDL and PD are both set, PD takes precedence.

AT89C51CC03

4182O–CAN–09/08

EEPROM Data

Memory The 2-Kbyte on-chip EEPROM memory block is located at addresses 0000h to 07FFh of

the XRAM/ERAM memory space and is selected by setting control bits in the EECON

A physi cal w rite i n the E EPROM m emo ry is d one in two step s: wr ite data in the colum n

latches and transfer of all data latches into an EEPROM memory row (programming).

The number of data written on the page may vary from 1 up to 128 Bytes (the page

size). Wh en prog ramming , only th e dat a written in the col umn latch i s progr ammed an d

a ninth bit is used to obtain this feature. This provides the capabil ity to program the

whole memory by Bytes, by page or by a number of Bytes in a page. Indeed, each ninth

bit is se t when the writing th e correspondi ng byte in a ro w and all these n inth bits are

reset after the writing of the complete EEPROM row.

W rite Dat a in the Colu mn

Latches Data is written by byte to the column latches as for an external RAM memory. Out of the

11 addre ss bi ts of the data poi nter , t he 4 MS Bs ar e us ed fo r pag e selection ( ro w) and 7

are used for byte selection. Between two EEPROM programming sessions, all the

addres ses in the c olumn latch es mus t stay on the sa me page, mea ning tha t the 4 MSB

must no be changed.

The following procedure is used to write to the column latches:

• Save and disab le int er rupt.

• Set bit EEE of EECON register

• Load DPTR with the address to write

• Store A register with the data to be written

• Execute a MOVX @DPTR, A

• If needed loop the three last instructions until the end of a 128 Bytes page

• Restore interrupt.

Note: The last page address used when loading the column latch is the one used to select the

page programming address.

Programming The EEPROM programming consists of the following actions:

• writing one or more Bytes of one page in the column latches. Normally, all Bytes

must belong to the same page; if not, the first page address will be latched and the

others discarded.

• launching programming by writing the control sequence (50h followed by A0h) to the

EECON register.

• EEBUSY flag in EECON is then set by hardware to indicate that programming is in

progress and that the EEPROM segment is not available for reading.

• The end of programming is indicated by a hardware clear of the EEBUSY flag.

Note: The sequence 5xh and Axh must be executed without instructions between then other-

wise the program mi ng is aborted .

Read Data The following procedure is used to read the data stored in the EEPROM memory:

• Save and disab le int er ru pt

• Set bit EEE of EECON register

• Load DPTR with the address to read

• Execute a MOVX A, @DPTR

• Restore interrupt

AT89C51CC03

4182O–CAN–09/08

Examples ;*F*************************************************************************;* NAME: api_rd_eeprom_byte

;* DPTR contain address to read.

;* Acc contain the reading value

;* NOTE: before execute this function, be sure the EEPROM is not BUSY

;***************************************************************************

api_rd_eeprom_byte:

MOV EECON, #02h; map EEPROM in XRAM space

MOVX A, @DPTR

MOV EECON, #00h; unmap EEPROM

ret

;*F*************************************************************************

;* NAME: api_ld_eeprom_cl

;* DPTR contain address to load

;* Acc contain value to load

;* NOTE: in this example we load only 1 byte, but it is possible upto

;* 128 Bytes.

;* before execute this function, be sure the EEPROM is not BUSY

;***************************************************************************

api_ld_eeprom_cl:

MOV EECON, #02h ; map EEPROM in XRAM space

MOVX @DPTR, A

MOVEEC ON , #00h; unmap EEPRO M

ret

;*F*************************************************************************

;* NAME: api_wr_eeprom

;* NOTE: before execute this function, be sure the EEPROM is not BUSY

;***************************************************************************

api_wr_eeprom:

MOV EECON, #050h

MOV EECON, #0A0h

ret

AT89C51CC03

4182O–CAN–09/08

Registers Table 11. EECON Register

EECON (S:0D2h)

EEPROM Control Register

Reset Val ue = XXXX XX00 b

Not bit address ab le

76543210

EEPL3 EEPL2 EEPL1 EEPL0 - - EEE EEBUSY

Bit Number Bit

Mnemonic Description

7-4 EEPL3-0 Programming Launch comma nd bits

Write 5Xh followed by AXh to EEPL to launch the programming.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

1EEE

Enable EEPROM Space b it

Set to map the EEPROM space during MOVX instructions (Write in the column

latches)

Clear to map the XRAM space during MOVX.

0EEBUSY

Progr amm ing Busy flag

Set by hardware when programming is in progress.

Cleared by hardware when programming is done.

Can not be set or cleared by software.

AT89C51CC03

4182O–CAN–09/08

Program/Code

Memory The AT89C51CC03 implement 64K Bytes of on-chip program/code memory. Figure 20

shows the partitioning of internal and external program/code memory spaces depending

on the product.

The Flash mem ory incr ease s EPRO M and ROM functio nality by in-cir cuit elec trical era-

sure and programming. Thanks to the internal charge pump, the high voltage needed for

programming or erasing Flash cells is generated on-chip using the standard VDD volt-

age. Thus, the Flash Memory can be programmed using only one voltage and allows In-

System Programming c ommonly known as ISP. Hardware progr amming mode is also

available using specific programming tool.

Figure 20. Program/Code Memory Organization

0000h

64K Bytes

FFFFh

internal

0000h

FFFFh

Flash

64K Bytes

external

memory

EA = 0

EA = 1

AT89C51CC03

4182O–CAN–09/08

External Code Me mory Access

Memory Interface The external memory interface comprises the external bus (port 0 and port 2) as well as

the bus control signals (PSEN#, and ALE).

Figure 21 s hows the structure of the external address bus. P0 c arries address A7:0

while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 21

describes the external memory interface signals.

Figure 21. External Code Memory Interface Structure

External Bu s Cycles This section describes the bus c ycles the AT89C51CC03 executes to fetch code (see

Figure 22) in the external program/code memory.

External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator

clock period in standard mode or 6 oscillator clock periods in X2 mode. For further infor-

mation on X2 mode see section “Clock “.

For simplicity, the accompanying figure depicts the bus cycle waveforms in idealized

form and do not provide precise timing information.

For bus cycling parameters refer to the ‘AC-DC parameters’ section.

Table 12. External Code Memory Interface Signals

Signal

Name Type Description Alternate

Function

A15:8 O Address Lines

Upper address lines for the external bus. P2.7:0

AD7:0 I/O Address/Data Lines

Multiplexed lower address lines and data for the external memory. P0.7:0

ALE O Address Latch Enable

ALE signals indicates that valid address information are available on lines

AD7:0. -

PSEN# O Progra m Store Enab le O utput

This signal is active low during external code fetch or external code read

(MOVC instruction). -

Flash

EPROM

AT89C51CC0

P0 AD7:0

A15:8

A7:0

A15:8

D7:0

A7:0

ALE Latch

OEPSEN#

AT89C51CC03

4182O–CAN–09/08

Figure 22. External Code Fetch Waveforms

Flash Memory

Architecture AT89C51CC03 features two on-chip Flash memories:

•Flash memory FM0:

containing 64K Bytes of program memory (user space) organized into 128 byte

pages,

•Flash memory FM1:

2K Bytes for boot loader and Application Programming Interfaces (API).

The FM0 can be p ro gram by both pa r all el p rogr amm in g a nd S er ial In-Syst em Pr o gr am-

ming (ISP ) wher eas FM 1 sup ports only paral lel pro gram ming by prog ramme rs . The ISP

mode is detailed in the "In-System Programming" section.

All Read/Write access operations on Flash Memory by user application are managed by

a set of API described in the "In-System Programming" section.

The bi t ENBOO T in AUXR 1 regi ster is used to ma p FM1 f rom F80 0h to FF FFh. F igure

23 and Figure 24 show the Flash memory configuration with ENBOOT=1 and

ENBOOT=0.

Figure 23. Flash Memory Architecture with ENBOOT=1 (boot mode)

ALE

PSEN#

PCL

PCHPCH

PCLD7:0 D7:0

PCH

D7:0

CPU Clock

FFFFh

64K Bytes

FM0

0000h

Hardware Security (1 byte)

Column Latches (128 Bytes)

Extra Row (128 Bytes)

2K Bytes

Flash me mo ry

FM1

boot space

FFFFh

F800h

FM1 mapped between FFFFh and

F800h when bit ENBOOT is set in

AUXR1 register

F800h

Memory space not accessible

AT89C51CC03

4182O–CAN–09/08

Figure 24. Flash Memory Architecture with ENBOOT=0 (user modemode)

FFFFh

64K Bytes

FM0

0000h

Hardware Security (1 byte)

Column Latches (128 Bytes)

Extra Row (128 Bytes)

2K Bytes

Flash me mo ry

FM1

boot space

FFFFh

F800h

FM1 mapped between FFFFh and

F800h when bit ENBOOT is set in

AUXR1 register

F800h

Memory space not accessible

AT89C51CC03

4182O–CAN–09/08

FM0 Memory Architect ure The Flash memory is made up of 4 blocks (see Figure 23):

• The memory array (user space) 64K Bytes

• The Extra Row

• The Hardware security bits

• The column latch registers

User Space This space is composed of a 64K Bytes Flash memory organized in 512 pages of 128

Bytes. It contains the user’s application code.

Extra Row (XRow) This ro w is a pa rt of F M0 and has a size o f 12 8 B yt es . The ex tra r ow may c on tain i nfo r-

mation for boot loader usage.

Hardware security Byte (HSB) The Hardware security Byte space is a part of FM0 and has a size of 1 byte.

The 4 MSB can be read/written by software (from FM0 and , the 4 LSB can only be read

by software and written by hardware in parallel mode.

H Hardware Security Byte (HSB)

Column Latches The column latches, also part of FM0, have a size of full page (128 Bytes).

The column latches are the entrance buffers of the three previous memory locations

(user arra y, XR OW an d Hard ware se cu rity byte). T he co lum n lat che s ar e write only and

can be accessed only from FM1 (boot mode) and from external memory

Cross Flash Memory Access

Description The FM0 me mor y can be progr am only from FM 1. Pr og rammi ng FM0 fr om FM0 or from

external memory is impo ssible.

The FM1 memory can be program only by parallel programming.

The Table show all software Flash access allowed.

76543210

X2 BLJB - - - LB2 LB1 LB0

Bit

Number Bit

Mnemonic Description

7X2

X2 Mode

Programmed (=’0’) to force X2 mode (6 clocks per instruction) after reset

Unprogrammed to force X1 mode, Standard Mode, afetr reset (Default)

6BLJB

Boot Loader Jump Bit

When unprogrammed (=’1’), at the next reset :

-ENBOOT=0 (see code space me mory configuration)

-Start address is 0000h (PC=0000h)

When programmed (=’0’)at the nex reset:

-ENBOOT=1 (see code space me mory configuration)

-Start address is F800h (PC=F800h)

5-Reserved

4-Reserved

3-Reserved

2-0 LB2-0 General Memory Lock Bits (only progr a mmable by programmer tools)

Section “Flash Protection from Parallel Prog ramm ing”, page 53

AT89C51CC03

4182O–CAN–09/08

Cross Flash Memory Access

(a) Depend upon general lock bit configuration.

Code executing from

Action FM0

(user Flash) FM1

(boot Flash)

FM0

(user Flash)

Read ok -

Load column latch ok -

Write - -

FM1

(boot Flash)

Read ok ok

Load column latch ok -

Write ok -

External

memory

EA = 0

Read (a) -

Load column latch - -

Write - -

AT89C51CC03

4182O–CAN–09/08

Overview of FM0

Operations

Flash Register s (SFR )

The CPU inte rfaces to the fla sh mem ory through the F CON register, A UXR1 register

and FSTA register.

These register s are used to map the column latche s, HSB, extra row a nd EEDATA in

the working data or code space.

FCON Register Table 13. FCON Register

FCON Register (S:D1h)

Flash Control Register

Reset Value= 0000 0000b

76543210

FPL3 FPL2 FPL1 FPL0 FPS FMOD1 FMOD0 FBUSY

Bit

Number Bit

Mnemonic Description

7-4 FPL3:0 Programming Launch Command Bits

Write 5Xh followed by AXh to launch the programming according to FMOD1:0.

(see Table 16.)

3FPS

Flash Map Program Space

When this bit is set:

The MOVX @DPTR, A instruction writes in the columns latches space

When this bit is cleared:

The MOVX @DPTR, A instruction writes in the regular XDATA memory space

2-1 FMOD1:0 Flash Mode

See Table 16.

0FBUSY

Flash Busy

Set by hardware when programming is in progress.

Clear by hardware when programming is done.

Can not be changed by software.

AT89C51CC03

4182O–CAN–09/08

FSTA Register Table 14. FST A Register

FSTA Register (S:D3h)

Flash Status Register

Reset Value= 0000 0000b

Mapping of the Memory Space By default, the user space is accessed by MOVC A, @DPTR instruction for read only.

The co lumn la tches spa ce is ma de acce ssible by setting th e FPS bit i n FCON r egister .

Writing is possible from 0000h to FFFFh, address bits 6 to 0 are used to select an

addres s within a pag e while bits 15 to 7 are us ed to selec t the progr amming address of

the page.

Setting FPS bit takes precedence on the EXTRAM bit in AUXR register.

The other memory spaces (user, extra row, hardware security) are made accessible in

the code segment by programming bits FMOD0 and FMOD1 in FCON register in accor-

dance with Table 15. A MOVC instruction is then used for reading these spaces.

Table 15. FM0 Blocks Select Bits

Notes: 1. The column latches res et is a n ew o pti on int r odu ce d i n the AT89C51CC0 3, and is no t

available in T89C51CC01/2

Launching Programming FPL3:0 b its in F CON r egister are used to sec ure the l aunch o f prog ramming . A spe cific

sequence must be written in these bits to unlock the write protection and to launch the

programming. This sequence is 5xh followed by Axh. Table 16 summarizes the memory

spaces to program according to FMOD1:0 bits.

76543210

SEQERR FLOAD

Bit

Number Bit

Mnemonic Description

7-2 unusesd

1SEQERR

Flash activation sequence error

Set by hardware when the flash activation sequence(MOV FCON 5X and MOV

FCON AX )is not correct (See Error Repport Sect ion)

Clear by software or clear by hardware if the last activation sequence was

correct (previous error are canceled)

0FLOAD

Flash Co lums la t c h load e d

Set by hardware when the first data is loaded in the column latches.

Clear by hardware when the activation sequence suceed (flash write sucess, or

reset column latch success)

FMOD1 FMOD0 FM0 Adressable space

0 0 User (0000h-FFFFh)

0 1 Extra Row(FF80h-FFFFh)

1 0 Hardware Security Byte (0000h)

1 1 Column latches reset (note1)

AT89C51CC03

4182O–CAN–09/08

Table 16. Programming Spaces

Notes: 1. The sequence 5xh and Axh must be executing without instructions between them

otherwise the programming is not executed (see Flash Status Register)

2. The sequence 5xh and Axh must be executed with the same FMOD0 FMOD1

configuration.

3. Interrupts that may occur during programming time must be disabled to avoid any

spurious exit of the programming mode.

Status of the Flash Memory The bit FBUSY in FCON register is used to indicate the status of programming.

FBUSY is set when programming is in progress.

The flash programming process is launched the second machine cycle following the

sequence 5xh and Axh in FCON. Thus the FBUSY flag should be read by sofware not

duri ng the in sctruct ion afte r the 5xh, Axh se quenc e but the t he secon d instru ction after

the 5xh, Axh sequence in FCON (See next example). FBUSY is cleared when the pro-

gramming is completed.

;*F*************************************************************************

;* NAME: launch_prog

;;***************************************************************************

launch_prog:

MOV FCON, #050h

MOV FCON #0A0h ; Flash Write Sequence

NOP ;Required time before reading busy flag

wait_busy:

MOV A, FCON

JB ACC.0,wait_busy

RET

Selecting FM1 The bit ENBOOT in AUXR1 register is used to map FM1 from F800h to FFFFh.

Loading the Column Latches An y n umb er of da ta from 1-byt e to 1 28 B yte s c an be l oade d in the c ol um n latches . T his

provides the capability to program the whole memory by byte, by page or by any number

of Bytes in a page. Data writte n in the co lumn latches do not have to be in consecuti ve

Wr ite to FCON

OperationFPL3:0 FPS FMOD1 FMOD0

User

5 X 0 0 No action

AX00

Write the column latches in user

space

Extra Row

5 X 0 1 No action

AX01

Write the column latches in extra row

space

Hardware

Security

Byte

5 X 1 0 No action

A X 1 0 Write the fuse bits space

Reset

Columns

Latches

5 X 1 1 No action

A X 1 1 Reset the column latches

AT89C51CC03

4182O–CAN–09/08

order. The page address of the last address loaded in the column latches will be used

for the whole page.

When progra mmin g is laun ched , an aut omati c eras e of the l ocatio ns lo aded in the co l-

umn latches is first performed, then programming is effectively done. Thus no page or

block erase is needed and only the loaded data are programmed in the corresponding

page

Notes: 1. : If no bytes are written in the column latches the SEQERR bit in the FSTA register

will be set.

2. When a flash write sequence is in progress (FBUSY is set) a write sequence to the

column latches will be ignored and the content of the column latches at the time of

the launch write sequence will be preserved.

3. MOVX @DPTR, A instruction must be used to load the column latches. Never use

MOVX @Ri, A instructions.

4. When a programming sequence is launched, Flash bytes corresponding to activated

bytes in the column latches are first erased then the bytes in the column latches are

copied i nto the Fla sh by tes. Fl as h by tes c orre sponding to b yt es in t he column l atc hes

not activ ated (n ot load ed duri ng t he loa d column lat ches seque nce) wil l not be erase d

and written.

The following procedure is used to load the column latches and is summarized in

Figure 25:

• Save and Disable interrupt and map the column latch space by setting FPS bit.

• Load the DPTR with the address to load.

• Load Accumulator register with the data to load.

• Execute the MOVX @DPTR, A instruction.

• If needed loop the three last instructions until the page is completely loaded.

• unmap the column latch.

• Restore Interrupt

AT89C51CC03

4182O–CAN–09/08

Figure 25. Column Latches Loading Procedure

Note: The last page address used when loading the column latch is the one used to select the

page programming address.

Programming the Flash Spaces

User The following procedure is used to program the User space and is summarized in

Figure 26:

• Load up to one page of data in the column latches from address 0000h to FFFFh.

• Save and Disable the interrupts.

• Launch the programming by writing the data sequence 50h followed by A0h in

FCON register (only from FM1).

The end of the programming indicated by the FBUSY flag cleared.

• Restore the interrupts.

Extra Row The foll owing proc edure is used to pr ogram the E xtra Row spa ce and i s summar ized in

Figure 26:

• Load data in the column latch es from address FF80h to FFFFh.

• Save and Disable the interrupts.

• Launch the programming by writing the data sequence 52h followed by A2h in

FCON register (only from FM1).

The end of the programming indicated by the FBUSY flag cleared.

• Restore the interrupts.

Colu m n Latches

Data Load

DPTR = Address

ACC = Data

Exec: MOVX @DPTR, A

Last Byte

to load?

Column Latches Mapping

FCON = 08h (FPS=1)

Data memory Mapping

FCON = 00h (F PS = 0)

Save and Disable IT

EA = 0

Restore IT

AT89C51CC03

4182O–CAN–09/08

Figure 26. Flash and Extra Row Programming Procedure

Hardware Security Byte The following procedure is used to program the Hardware Security Byte space

and is summarized in Figure 27:

• Set FPS and map Hardware byte (FCON = 0x0C)

• Save and disab le the inte rru pts.

• Load DPTR at address 0000h.

• Load Accumulator register with the data to load.

• Execute the MOVX @DPTR, A instruction.

• Launch the programming by writing the data sequence 54h followed by A4h in

FCON register (only from FM1).

The end of the programming indicated by the FBusy flag cleared.

• Restore the interrupts.

Flash Spaces

Programming

Save and Disable IT

EA = 0

Launch Programming

FCON = 5xh

FCON = Axh

End Programming

Restore IT

Column Latches Loading

see Figure 25

FBusy

Cleared?

Clear Mode

FCON = 00h

AT89C51CC03

4182O–CAN–09/08

Figure 27. Hardware Programming Procedure

Reset the Column Latc he s An automatic reset of the column latches is performed after a successful Flash

write sequ ence. Use r can also reset the column latc hes man ually, for instan ce

to reload t he column lat ches befor e wri ting the Fl ash. T he foll owing procedu re is

summarized below.

• Save and disab le the inte rru pts.

• Launch the reset by writing the data sequence 56h followed by A6h in FCON

• Restore the interrupts.

Error Repo rts

Flash Prog ra mmi ng Seq uen ce

Errors When a wrong seque nce is de tected , the SE QERR b it in FS TA regis ter is s et. Possi ble

wrong sequence are :

• MOV FCON, 5xh instruction not immediately followed by a MOV FCON, Ax

instruction.

• A write Flash sequence is launched while no data were loaded in the column latches

The SEQERR bit can be cleared

•By software

• By hardware when a correct programming sequence is completed

When multiple pages are written into the Flash, the user should check FSTA for errors

after each write page sequences, not only at the end of the multiple write pages.

Flash Spaces

Programming

Save and Di sable IT

EA = 0

Launch Programming

FCON = 54h

FCON = A4h

End Programming

RestoreIT

FBusy

Cleared?

Clear Mode

FCON = 00h

Data Load

DPTR = 00h

ACC = Data

Exec: MOVX @DPTR, A

FCON = 0Ch

Save and Disable IT

EA = 0

End Loading

Restore IT

AT89C51CC03

4182O–CAN–09/08

Power Down Request Before entering in Power Down (Set bit PD in PCON register) the user should check that

no write sequence is in progress (check BUSY=0), then check that the column latches

are reset ( FLO AD =0 in F S TA regi st er . Lau nc h a r eset c olu mn l atc he s to clear F LOAD i f

necessary.

Reading the Flash Spaces

User The following procedure is used to read the User space:

• Read one byte in Accumulator by executing MOVC A,@A+DPTR with

A+DPTR=read@.

Note: FCON is supposed to be reset when not needed.

Extra Row The following procedure is used to read the Extra Row space and i s summarized in

Figure 28:

• Map the Extra Row space by writing 02h in FCON register.

• Read one byte in Accumulator by executing MOVC A,@A+DPTR with A = 0 and

DPTR = FF80h to FFFFh.

• Clear FCON to unmap the Extra Row.

Hardware Security Byte The following procedure is used to read the Hardware Security space and is

summarized in Figure 28:

• Map the Hardware Security space by writing 04h in FCON register.

• Read the byte in Accumulator by executing MOVC A,@A+DPTR with A = 0 and

DPTR = 0000h.

Figure 28. Clear FCON to unmap the Hardware Security Byte.Reading Procedure

Flash Protection from Parallel

Programming The three lock bits in Hardware Security Byte (see "In-System Programming" section)

are programmed according to Table 17 provide different level of protection for the on-

chip code and data located in FM0 and FM1.

The only way to write this bits are the parallel mode. They are set by default to level 4

Flash Spaces Reading

Flash Spaces Mapping

FCON= 000 00xx0b

Data Read

DPTR= Address

ACC= 0

Exec: MOVC A, @A+DPTR

Clear Mode

FCON = 00h

AT89C51CC03

4182O–CAN–09/08

Table 17. Program Lock Bit

Program Lock bits

U: unprogrammed

P: programmed

WARNING: Security level 2 and 3 should only be programmed after Flash and Core

verification.

Progr a m Lock Bits

Protection Description

Security

level LB0 LB1 LB2

1 U U U No program lock features enabled.

2PUU

MOVC instruction executed from external program memory are

disabled from fetching code bytes from internal memory, EA is sampled

and latched on reset, and further parallel programming of the Flash is

disabled.

ISP and software programming with API are still allowed.

Writing EEprom Data from external parallel programmer is disabled but

still allowed from internal code execution.

3UPU

Same as 2, also verify through parallel programming interface is

disabled.

Writing And Reading EEPROM Data from external parallel programmer

is disabled but still allowed from internal code execution..

4 U U P Same as 3, also external execut ion is disabled

AT89C51CC03

4182O–CAN–09/08

Operation Cross Memory Access

Space addressable in read and write are:

•RAM

• ERAM (Expanded RAM access by movx)

• XRAM (eXternal RAM)

• EEPROM DATA

• FM0 ( user flash )

• Hardware by te

•XROW

•Boot Flash

• Flash Column latch

The table below provide the different kind of memory which can be accessed from differ-

ent code location.

Note: 1. RWW: Read While Write

Table 18. Cross Memory Access

Action RAM XRAM

ERAM Boot FLASH FM0 E² Data Hardware

Byte XROW

boot FLASH Read OK OK OK OK -

Write - OK(1) OK(1) OK(1) OK(1)

FM0 Read OK OK OK OK -

Writ e - OK (idle) OK(1) -OK

External memory

EA = 0

or Code Roll Over

Read - - OK - -

Write - - OK(1) --

AT89C51CC03

4182O–CAN–09/08

Sharing Instructions Table 19. Instructions sha r ed

Note: by cl : usin g Column Latch

Table 20. Read MOVX A, @DPTR

Table 21. Write MOVX @DPTR,A

Action RAM XRAM

ERAM EEPROM

DATA Boot

FLASH FM0 Hardware

Byte XROW

Read MOV MOVX MOVX MOVC MOVC MOVC MOVC

Write MOV MOVX MOVX - by cl by cl by cl

EEE bi t in

EECON

FCON Register ENBOOT EA XRAM

ERAM EEPROM

DATA

Flash

Column

Latch

00XXOK

01XXOK

10XX OK

11XXOK

EEE bi t in

EECON

FCON Register ENBOOT EA XRAM

ERAM EEPROM

Data

Flash

Column

Latch

00XXOK

01X

1OK

0OK

10XX OK

11X

1OK

0OK

AT89C51CC03

4182O–CAN–09/08

Table 22. Read MOVC A, @DPTR

Code Execution

FCON Register

ENBOOT DPTR FM1 FM0 XROW Hardware

Byte External

CodeFMOD1 FMOD0 FPS

From FM0

00X

0 0000h to FFFFh OK

10000h to F7FF OK

F800h to FFFFh Do not use this configuration

01X X

0000 to 007Fh

See (1) OK

10X X X OK

11X

0 000h to FFFFh OK

10000h to F7FF OK

F800h to FFFFh Do not use this configuration

From FM1

(ENBOOT =1

010000h to F7FF OK

F800h to FFFFh OK

0X NA

11X OK

0X NA

01X 10000h to 007h

See (2)

0NA

10X 1XOK

0NA

11X 1000h to FFFFh OK

0NA

External code :

EA=0 or Code

Roll Over X0X X X OK

1. For DPTR higher than 007Fh only lowest 7 bits are decoded, thus the behavior is the same as for addresses from 0000h to

007Fh

2. For DPTR higher than 007Fh only lowest 7 bits are decoded, thus the behavior is the same as for addresses from 0000h to

007Fh

AT89C51CC03

4182O–CAN–09/08

In-System

Programming (ISP) With the implementation of the User Space (FM0) and the Boot Space (FM1) in Flash

technolo gy the AT89C5 1CC03 al lows the s ystem engin eer the d evel opment of appl ica-

tions wi th a very high l evel of f lexib ility . Th is flexi bilit y is bas ed on t he p ossibi lity t o alter

the customer program at any stages of a product’s life:

• Before assembly the 1st personalization of the product by programming in the FM0

and if needed also a customized Boot loader in the FM1.

Atmel provide also a standard Boot loader by default UART or CAN.

• After assembling on the PCB in its final embedded position by serial mode via the

CAN bus or UART.

This In-System Programming (ISP) allows code modification over the total lifetime of the

product.

Besides the default Boot loader Atmel provide to the customer also all the needed Appli-

cation-Programming-Interfaces (API) which are needed for the ISP. The API are located

also in the Boot memory.

This allow the customer to have a full use of the 64-Kbyte user memory.

Flash Programming and

Erasure There are three methods of programming the Flash memory:

• The Atmel bootloader located in FM1 is activated by the application. Low level API

routines (located in FM1)will be used to program FM0. The interface used for serial

downloading to FM0 is the UART or the CAN. API can be called also by the user’s

bootloader located in FM0 at [SBV]00h.

• A further method exists in activating the Atmel boot loader by hardware activation.

• The FM0 can be programmed also by the parallel mode using a programmer.

Figure 29. Flash Memory Mapping

Boot Process

Software Boot Process

Example Many algorithms can be used for the software boot process. Before describing them,

The description of the different flags and Bytes is given below:

F800h

FFFFh

64K Bytes

Flash memory

2K Bytes IAP

bootloader

FM0

FM1

Custom

Boot Loa der

[SBV]00h

FFFFh

FM1 mapped between F800h and FFFF

when API called

0000h

AT89C51CC03

4182O–CAN–09/08

Boot Loader Jump Bit (BLJB):

- This bi t indicates if on RES ET the user wa nts to jump to this applicat ion at ad dress

@0000h on FM0 or execute the boot loader at address @F800h on FM1.

- BLJB = 0 on parts delivered with bootloader programmed.

- To read or modify this bit, the APIs are used.

Boot Vector Address (SBV):

- This byte contains the MSB of the user boot loader address in FM0.

- The default value of SBV is FCh (no user boot loader in FM0).

- To read or modify this byte, the APIs are used.

Extra Byte (EB) and Boot Status Byte (BSB):

- These Bytes are reserved for customer use.

- To read or modify these Bytes, the APIs are used.

Hardware Boot Proc ess At the falling edge of RESET, the bit ENBOOT in AUXR1 register is initialized with the

value of Boot Loader Jump Bit (BLJB).

Furthe r at the fall ing e dge of RESE T if t he following con dition s (cal led Hardwa re cond i-

tion) are detected:

• PSEN low,

• EA high,

• ALE high (or not connec ted ) .

– After Hardware Condition the FCON register is initialized with the value 00h

and the PC is initiali z ed with F800h (FM1) .

The Hardware condition makes the bootloader to be executed, whatever BLJB value is.

If no hardware condition is detected, the FCON register is initialized with the value F0h.

Check of the BLJB value.

• If bit BLJB = 1:

User application in FM0 will be started at @0000h (standard reset).

• If bit BLJB = 0:

Boot loader will be started at @F800h in FM1.

Note: 1. As PSEN is an output port in normal operating mode (running user applications or

bootloader applications) after reset it is recommended to release PSEN after the fall-

ing edge of Reset is signaled.

The hardware conditions are sampled at reset signal Falling Edge, thus they can be

released at any time when reset input is low.

2. To ensure correct microcontroller startup, the PSEN pin should not be tied to ground

during power-on.

AT89C51CC03

4182O–CAN–09/08

Figure 30. Hardware Boot Process Algorithm

Application

Programming Interface Several Application Program Interface (API) calls are available for use by an application

program to permit selective erasing and programming of Flash pages. All calls are made

by functions.

All thes e APIs are des cribe i n an doc umentat ion : "In- Syst em Progr aming : Flash L ibra ry

for AT89C51CC03" available on the Atmel web site.

XROW Bytes Table 23. XROW Mapping

RESET

Hardware

condition?

BLJB = = 0

bit ENBOOT in AUXR1 registe

is initialized with BLJB.

Hardware

Software

ENBOOT = 1

PC = F800h

ENBOOT = 1

PC = F800h

FCON = 00h

FCON = F0h

Boot Loader

in FM1

ENBOOT = 0

PC = 0000h

Yes

Application

in FM0

Description Default Value Address

Copy of the Manufacturer Code 58h 30h

Copy of the Device ID#1: Family code D7h 31h

Copy of the Device ID#2: Memories size and type FFh 60h

Copy of the Device ID#3: Name and Revision FEh 61h

AT89C51CC03

4182O–CAN–09/08

Hardware Security Byte Table 24. Hardware Security Byte

After erasing the chip in parallel mode, the default value is : FFh

The erasing in ISP mode (from bootloader) does not modify this byte.

Notes: 1. Onl y the 4 MSB bits can be accessed by software.

2. The 4 LSB bits can only be accessed by parallel mode.

76543210

X2B BLJB - - - LB2 LB1 LB0

Bit

Number Bit

Mnemonic Description

7X2B

X2 Bit

Set this bit to start in standard mode

Clear this bit to start in X2 mode.

6BLJB

Boot Loader JumpBit

- 1: To start the user’s application on next RESET (@0000h) located in FM0,

- 0: To start the boot loader(@F800h) located in FM1.

5-3 - Reserved

The value read from these bits are indeterminate.

2-0 LB2:0 Lock Bits

AT89C51CC03

4182O–CAN–09/08

Serial I/O Port The AT89C51CC03 I/O serial port is compatible with the I/O serial port in the 80C52.

It provides both synchronous and asynchronous communication modes. It operates as a

Universal Async hronous Receiver and Transmitter (UART) in three full-duplex modes

(Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously

and at different baud rates

Serial I/O port includes the following enhancements:

• Framing error detection

• Automatic address recognition

Figure 31. Serial I/O Port Block Diagram

Framing Error Detection Framing bit error detection is provided for the three asynchronous modes. To enable the

framing bit error detection feature, set SMOD0 bit in PCON register.

Figure 32. Framing Error Block Diagram

When this feature is enabled, the receiver checks each incoming data frame for a valid

stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous

transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in

SCON registe r bit is set.

The software m ay examine the FE bit after each reception to check for data errors.

Once set, on ly s oftwa re o r a r eset c lea rs t he FE b it. Su bs equ entl y r ec eived fr am es wi th

Write SBUF

RI TI

SBUF

Transmitter

SBUF

Receiver

IB Bus

Mode 0 Transmit

Receive

Shift register

Load SBUF

Read SBUF

SCON reg

Interrupt Request

Serial Port

TXD

RXD

RITIRB8TB8RENSM2SM1SM0/FE

IDLPDGF0GF1POF-SMOD0SMOD

To UART framing error control

SM0 to UART mode control

Set FE bit if stop bit is 0 (framing error)

AT89C51CC03

4182O–CAN–09/08

valid stop bits cannot clear the FE bit. When the FE feature is enabled, RI rises on the

stop bit instead of the last data bit (See Figure 33. and Figure 34.).

Figure 33. UART Timing in Mode 1

Figure 34. UART Timing in Mod es 2 and 3

Automatic Addres s

Recognition The aut oma tic a ddr es s r ec ogn iti on feat ure i s en abl ed when th e m ul tiproce ssor c om mu-

nication feature is enabled (SM2 bit in SCON register is set).

Implemented in the hardware, automatic address recognition enhances the multiproces-

sor communication feature by allowi ng the serial port to examine the addr ess of each

incoming command frame. Only when the serial port recognizes its own address will the

receiver set the RI bit in the SCON register to generate an interrupt. This ensures that

the CPU is not interrupted by command frames addressed to other devices.

If nece ssary, you ca n enable the automatic ad dress rec ognition featu re in mode 1. In

this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when

the received command frame address matches the device’s address and is terminated

by a valid stop bit.

To supp ort automatic a ddr ess re co gni tio n, a dev ic e i s ide nti fie d by a give n add ress an d

a broadcast address.

Note: The multiprocessor communication and automatic address recognition features cannot

be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect).

Data byte

SMOD0=X

Stop

bit

Start

bit

RXD D7D6D5D4D3D2D1D0

SMOD0=1

SMOD0=0

Data byte Ninth

bit Stop

bit

Start

bit

RXD D8D7D6D5D4D3D2D1D0

SMOD0=1

AT89C51CC03

4182O–CAN–09/08

Given Address Each device has an individual address that is specified in the SADDR register; the

SADEN register is a mask byte that contains don’t-care bits (defined by zeros) to form

the device’s given address. The don’t-care bits provide the flexibility to address one or

more slaves at a time. The following example illustrates how a given address is formed.

To address a device by its individual address, the SADEN mask byte must be 1111

1111b.

For example:

SADDR0101 0110b

SADEN1111 1100b

Given0101 01XXb

Here is an example of how to use given addresses to address different slaves:

Slave A:SADDR1111 0001b

SADEN1111 1010b

Given1111 0X0Xb

Slave B:SADDR1111 0011b

SADEN1111 1001b

Given1111 0XX1b

Slave C:SADDR1111 0011b

SADEN1111 1101b

Given1111 00X1b

The SADEN byte is selected so that each slave may be addressed separately.

For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To com-

munic ate with slave A o nly, the ma ster must send an addre ss wher e bit 0 is clea r (e.g.

1111 0000b).

For slave A, bit 1 is a 0; for slaves B and C, bit 1 is a don’t care bit. To communicate with

slaves A and B, but not slave C, the master must send an address with bits 0 and 1 both

set (e.g. 1111 0011b).

To communicate with slaves A, B and C, the master must send an address with bit 0 set,

bit 1 clear, and bit 2 clear (e.g. 1111 0001b).

Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers

with zeros defined as don’t-care bits, e.g.:

SADDR0101 0110b

SADEN1111 1100b

SADDR OR SADEN1111 111Xb

The use of don’t-care bits provides flexibility in defining the broadcast address, however

in most applications, a broadcast address is FFh. The following is an example of using

broadcast addresses:

Slave A:SADDR1111 0001b

SADEN1111 1010b

Given1111 1X11b,

Slave B:SADDR1111 0011b

SADEN1111 1001b

Given1111 1X11B,

Slave C:SADDR=111 1 0010b

SADEN1111 1101b

Given1111 1111b

AT89C51CC03

4182O–CAN–09/08

For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with

all of the s lave s, the ma ster mus t send a n add ress F Fh. To com mun icate with slav es A

and B, but not slave C, the master can send and address FBh.

Registers Table 25. SCON Register

SCON (S:98h)

Serial Control Register

Reset Value = 0000 0000b

Bit addressable

76543210

FE/SM0 SM1 SM2 REN TB8 RB8 TI RI

Bit

Number Bit

Mnemonic Description

7FE

Framing Error bit (SMOD0=1)

Clear to reset the error state, not cleared by a valid stop bit.

Set by hardware when an invalid stop bit is detected.

SM0 Serial port Mode bit 0 (SMOD0=0)

Refer to SM1 for serial port mode selection.

6SM1

Seria l por t Mode bit 1

SM0 SM1 Mode Baud Rate

0 0 Shift Register FXTAL/12 (or FXTAL /6 in mode X2)

0 1 8-bit UART Variable

1 0 9-bit UART FXTAL/64 or FXTAL/32

1 1 9-bit UART Variable

5SM2

Serial port Mode 2 bit/Multiprocessor Communication Enable bit

Clear to disable multiprocessor communication feature.

Set to enable multiprocessor communication feature in mode 2 and 3.

4REN

Reception Enable bit

Clear to disable serial reception.

Set to enable serial reception.

3TB8

Tran smitter Bit 8/Ninth bit to transmit in modes 2 and 3

Clear to transmit a logic 0 in the 9th bit.

Set to transmit a logic 1 in the 9th bit.

2RB8

Receiver Bit 8/Ninth bit received in modes 2 and 3

Cleared by hardware if 9th bit received is a logic 0.

Set by hardware if 9th bit received is a logic 1.

1TI

Transmit Interrupt flag

Clear to acknowledge interrupt.

Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the

stop bit in the other modes.

0RI

Receive Interrupt flag

Clear to acknowledge interrupt.

Set by hardware at the end of the 8th bit time in mode 0, see Figure 33. and

Figure 34. in the other modes.

AT89C51CC03

4182O–CAN–09/08

Table 26. SADEN Register

SADEN (S:B9h)

Slave Address Mask Register

Reset Value = 0000 0000b

Not bit address ab le

Table 27. SADDR Register

SADDR (S:A9h)

Slave Address Register

Reset Value = 0000 0000b

Not bit address ab le

Table 28. SBUF Register

SBUF (S:99h)

Serial Data Buffer

Reset Value = 0000 0000b

Not bit address ab le

76543210

––––––––

Bit

Number Bit

Mnemonic Description

7-0 Mask Data for Slave Individual Address

76543210

––––––––

Bit

Number Bit

Mnemonic Description

7-0 Slave Individual Address

76543210

––––––––

Bit

Number Bit

Mnemonic Description

7-0 Data sent/received by Serial I/O Port

AT89C51CC03

4182O–CAN–09/08

Table 29. PCON Register

PCON (S:87h)

Power Control Register

Reset Value = 00X1 0000b

Not bit address ab le

76543210

SMOD1 SMOD0 – POF GF1 GF0 PD IDL

Bit

Number Bit

Mnemonic Description

7SMOD1

Seria l por t Mode bit 1

Set to select double baud rate in mode 1, 2 or 3.

6SMOD0

Seria l por t Mode bit 0

Clear to select SM0 bit in SCON register.

Set to select FE bit in SCON register.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

4POF

Power-Off Flag

Clear to recognize next reset type.

Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set

by software.

3GF1

General-purpose Flag

Cleared by user for general-purpose usage.

Set by user for general-purpose usage.

2GF0

General-purpose Flag

Cleared by user for general-purpose usage.

Set by user for general-purpose usage.

1PD

Power- Down mode bit

Cleared by hardware when reset occurs.

Set to enter power-down mode.

0IDL

Idle mode bit

Clear by hardware when interrupt or reset occurs.

Set to enter idle mode.

AT89C51CC03

4182O–CAN–09/08

Timers/Counters The AT89C51CC03 implements two general-purpose, 16-bit Timers/Counters. Such are

identi fied as Tim er 0 and Time r 1, an d can be in depende ntly confi gured to operate in a

variety of modes as a Timer or an event Counter. When operating as a Timer, the

Timer/Counter runs for a programmed length of time, then issues an interrupt request.

When oper ating as a Coun ter, the Timer /Counter counts n egative transit ions on an

external pin. After a preset number of counts, the Counter issues an interrupt request.

The v arious o perating m odes of each Time r/Counter are des cribed in the foll owing

sections.

Timer/Counter

Operations A basic operation is Timer registers THx and TLx (x = 0, 1) connected in cascade to

form a 16-bit Timer. Setting the run control bit (TRx) in TCON register (see Figure 30)

turns the Timer on by allowing the selected input to increment TLx. When TLx overflows

it incre ments THx; when THx overflows it sets th e Timer overfl ow flag (TFx) i n TCON

ters can be acc essed to obtai n the cur rent count or to enter pres et value s. They ca n be

read at any time but TRx bit must be cleared to preset their values, otherwise the behav-

ior of the Timer/Counter is unpredictable.

The C/Tx# control bit selects Timer oper ation or Counter operation by selecting the

divided-down peripher al clock or external pin Tx as the source for the counted signal.

TRx bit must be cleared when changing the mode of operation, otherwise the behavior

of the Timer/Counter is unpredictable.

For T imer oper atio n ( C/Tx# = 0 ), t he Ti mer regi ster co unts the divid ed-d own periph era l

clock. The Timer register is incremented once every peripheral cycle (6 peripheral clock

peri ods). The Tim er clo ck ra te is FPER/6, i.e. F OSC/12 in standard mode or FOSC/6 i n X2

mode.

For Count er oper ati on (C/T x # = 1), the T imer reg ister cou nts t he neg ative tran si tions on

the Tx external input pin. The external input is sampled every peripheral cycles. When

the sample is high in one cycle and low in the next one, the Counter is incremented.

Since it takes 2 cycles (12 peripheral clock periods) to recognize a negative transition,

the maximum count rate is FPER/12, i.e. FOSC/24 in standard mode or FOSC/12 in X 2

mode. There are no restrictions on the duty cycle of the external input signal, but to

ensure that a given level is sampled at least once before it changes, it should be held for

at least one full peripheral cycle.

Timer 0 Timer 0 functions as either a Timer or event Counter in four modes of operation.

Figure 35 to Figure 38 show the logical configuration of each mode.

Timer 0 is control led by th e four lower bits of T MOD regi ster (s ee Figur e 31) and bits 0,

1, 4 and 5 of TCON register (see Figure 30). TMOD register selects the method of Timer

gating (GATE0), Timer or Counter operation (T/C0#) and mode of operation (M10 and

M00). TCON register provides Timer 0 control functions: overflow flag (TF0), run control

bit (TR0), interrupt flag (IE0) and interrupt type control bit (IT0).

For norm al Tim er ope ration ( GATE 0 = 0), settin g TR0 allows TL0 to be inc reme nted by

the selected input. Setting GATE0 and TR0 allows external pin INT0# to control Timer

operation.

Timer 0 overflow (count rolls over from all 1s to all 0s) sets TF0 flag generating an inter-

rupt reque st.

It is important to stop Timer/Counter before changing mode.

AT89C51CC03

4182O–CAN–09/08

Mode 0 (13-bit Timer) Mode 0 configure s Timer 0 as an 13-bit T imer which is set up a s an 8-bit T imer (TH0

(see Figure 35) . The upper three bits of TL0 register are indeterminate and s hould be

ignored. Prescaler overflow increments TH0 register.

Figure 35. Timer/Counter x (x = 0 or 1) in Mode 0

Mode 1 (16-bit Timer) Mode 1 configures Timer 0 as a 16-bit Timer with TH0 and TL0 registers connected in

cascade (see Figure 36). The selected input increments TL0 register.

Figure 36. Timer/Counter x (x = 0 or 1) in Mode 1

FTx

CLOCK

TRx

TCON reg

TFx

TCON reg

GATEx

TMOD reg

÷ 6 Overflow Timer x

Interrupt

Request

C/Tx#

TMOD reg

TLx

(5 bits)

THx

(8 bits)

INTx#

See the “Clock” section

TRx

TCON reg

TFx

TCON reg

GATEx

TMOD reg

Overflow Timer x

Interrupt

Request

C/Tx#

TMOD reg

TLx

(8 bits)

THx

(8 bits)

INTx#

FTx

CLOCK ÷ 6

See the “Clock” section

AT89C51CC03

4182O–CAN–09/08

Mode 2 (8-bit Timer with Auto-

Reload) Mode 2 con figures Timer 0 as an 8-bit Timer (TL0 register) that automatically reloads

from TH0 register (see Figure 37). TL0 overflow sets TF0 flag in TCON register and

reloads TL0 with the contents of TH0, which is preset by software. When the interrupt

reques t is ser viced , hard ware clears TF0. The re load l eaves T H0 un chang ed. T he nex t

reload value may be changed at any time by writing it to TH0 register.

Figure 37. Timer/Counter x (x = 0 or 1) in Mode 2

Mode 3 (Two 8-bit Timers) Mode 3 configures Timer 0 such that registers TL0 and TH0 operate as separate 8-bit

Timers (see Figure 38). This mode is provided for applications requiring an additional 8-

bit Timer or Counter. TL0 uses the Timer 0 control bits C/T0# and GATE0 in TMOD reg-

ister, and TR0 and TF0 in TCON register in the normal manner. TH0 is locked into a

Timer func tion (counti ng FPER /6) and takes over use of the Timer 1 in terrupt (TF1 ) and

run contro l (TR1) bits. T hus, operation of T imer 1 is restric ted when Timer 0 is in mode

Figure 38. Timer/Counter 0 in Mode 3: Two 8-bit Counters

TRx

TCON reg

TFx

TCON reg

GATEx

TMOD reg

Overflow Timer x

Interrup

Reques

C/Tx#

TMOD reg

TLx

(8 bits)

THx

(8 bits)

INTx#

FTx

CLOCK ÷ 6

See the “Clock” section

TR0

TCON.4

TF0

TCON.5

INT0#

GATE0

TMOD.3

Overflow Timer 0

Interrup

Reques

C/T0#

TMOD.2

TL0

(8 bits)

TR1

TCON.6

TH0

(8 bits) TF1

TCON.7

Overflow Timer 1

Interrup

Reques

FTx

CLOCK ÷ 6

FTx

CLOCK ÷ 6

See the “Clock” section

AT89C51CC03

4182O–CAN–09/08

Timer 1 Timer 1 is identical to Timer 0 excepted for Mode 3 which is a hold-count mode. The fol-

lowing comments help to understand the differences:

• Timer 1 functions as either a Timer or event Counter in three modes of oper ation.

Figure 35 to Figure 37 show the logical configuration for modes 0, 1, and 2. Timer

1’s mode 3 is a hold-count mode.

• Timer 1 is controlled by the four high-order bits of TMOD register (see Figure 31)

and bits 2, 3, 6 and 7 of TCON register (see Figure 30). TMOD register selects the

method of Timer gating (GATE1), Timer or Counter operation (C/T1#) and mode of

operation (M11 and M01). TCON register provides Timer 1 control functions:

overflow flag (TF1), run control bit (TR1), interrupt flag (IE1) and interrupt type

control bit (IT1).

• Timer 1 can serve as the Baud Rate Generator for the Serial Port. Mode 2 is best

suited for this purpose.

• For normal Timer operation (GATE1 = 0), setting TR1 allows TL1 to be incremented

by the selected input. Setting GATE1 and TR1 allows external pin INT1# to control

Timer operation.

• Timer 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag generating

an interrupt request.

• When Timer 0 is in mode 3, it uses T imer 1’s overflow flag (TF1) and run control bit

(TR1). For this situation, use Timer 1 only for applications that do not require an

interrupt (such as a Baud Rate Generator for the Serial Port) and switch Timer 1 in

and out of mode 3 to turn it off and on.

• It is important to stop Timer/Counter before changing mode.

Mode 0 (13-bit Timer) Mode 0 configures Timer 1 as a 13-bit Timer, which is set up as an 8-bit Timer (TH1 reg-

ister) with a modulo-32 prescaler implemented with the lower 5 bits of the TL1 register

(see Figure 35). The uppe r 3 bits of TL1 regi ster ar e ignor ed. Pre scaler overflo w incr e-

ments TH1 register.

Mode 1 (16-bit Timer) Mode 1 configures Timer 1 as a 16-bit Timer with TH1 and TL1 registers connected in

cascade (see Figure 36). The selected input increments TL1 register.

Mode 2 (8-bit Timer with Auto-

Reload) Mode 2 configures Timer 1 as an 8-bit Timer (TL1 register) with automatic reload from

TH1 r egiste r on ove rflow (see Fi gure 37) . TL1 ov erflow sets TF 1 flag in TCON regis ter

and reloads TL1 with the contents of TH1, which is preset by software. The reload

leaves TH1 unchanged.

Mode 3 (Halt) Placi ng Timer 1 in mode 3 c auses it to ha lt and hold i ts count. Thi s can be used to hal t

Timer 1 when TR1 run control bit is not available i.e. when Timer 0 is in mode 3.

AT89C51CC03

4182O–CAN–09/08

Interrupt Each Timer handles one interrupt source that is the timer overflow flag TF0 or TF1. This

flag is se t eve ry tim e an ov erfl ow oc cur s. Fla gs are cl eared when v ec torin g to the Ti mer

interrupt routine. Interrupts are enabled by setting ETx bit in IEN0 register. This assumes

interrupts are globally enabled by setting EA bit in IEN0 register.

Figure 39. Timer Interrupt System

Registers Table 30. TCON Regis ter

TCON (S:88h)

Timer/Counter Control Register

Reset Value = 0000 0000b

TF0

TCON.5

ET0

IEN0.1

Timer 0

Interrupt Request

TF1

TCON.7

ET1

IEN0.3

Timer 1

Interrupt Request

76543210

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

Bit

Number Bit

Mnemonic Description

7TF1

Timer 1 Overflow Flag

Cleared by hardware when processor vectors to interrupt routine.

Set by hardware on Timer/Counter overflow, when Timer 1 register overflows.

6TR1

Timer 1 Run Control Bit

Clear to turn off Timer/Counter 1.

Set to turn on Timer /Counter 1.

5TF0

Timer 0 Overflow Flag

Cleared by hardware when processor vectors to interrupt routine.

Set by hardware on Timer/Counter overflow, when Timer 0 register overflows.

4TR0

Timer 0 Run Control Bit

Clear to turn off Timer/Counter 0.

Set to turn on Timer /Counter 0.

3IE1

Interrupt 1 Edge Flag

Cleared by hardware when interrupt is processed if edge-triggered (see IT1).

Set by hardware when external interrupt is detected on INT1# pin.

2IT1

Interr upt 1 Type Control Bit

Clear to select low level active (level triggered) for external interrupt 1 (INT1#).

Set to select falling edge active (edge triggered) for external interrupt 1.

1IE0

Interrupt 0 Edge Flag

Cleared by hardware when interrupt is processed if edge-triggered (see IT0).

Set by hardware when external interrupt is detected on INT0# pin.

0IT0

Interr upt 0 Type Control Bit

Clear to select low level active (level triggered) for external interrupt 0 (INT0#).

Set to select falling edge active (edge triggered) for external interrupt 0.

AT89C51CC03

4182O–CAN–09/08

Table 31. TMOD Register

TMOD (S:89h)

Timer/Counter Mode Control Register

Reset Value = 0000 0000b

76543210

GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00

Bit

Number Bit

Mnemonic Description

7GATE1

Timer 1 Gating Control Bit

Clear to enable Timer 1 whenever TR1 bit is set.

Set to enable Timer 1 only while INT1# pin is high and TR1 bit is set.

6C/T1#

Timer 1 Counter/Timer Select Bit

Clear for Timer operation: Timer 1 counts the divided-down system clock.

Set for Counter operation: T imer 1 counts negative transitions on external pin T1.

5M11Timer 1 Mode Select Bits

M11 M01 Operating mode

0 0 Mode 0: 8-bit Timer/Counter (TH1) with 5-bit prescaler (TL1).

0 1 Mode 1: 16-bit Timer/Counter.

1 0 Mode 2: 8-bit auto-reload Timer/Counter (TL1) (1)

1 1 Mode 3: Timer 1 halted. Retains count

1. Reloaded from TH1 at overflow.

4M01

3GATE0

Timer 0 Gating Control Bit

Clear to enable Timer 0 whenever TR0 bit is set.

Set to enable Timer/Counter 0 only while INT0# pin is high and TR0 bit is set.

2C/T0#

Timer 0 Counter/Timer Select Bit

Clear for Timer operation: Timer 0 counts the divided-down system clock.

Set for Counter operation: T imer 0 counts negative transitions on external pin T0.

1M10

Timer 0 Mode Select Bit

M10 M00 Operating mode

0 0 Mode 0: 8-bit Timer/Counter (TH0) with 5-bit prescaler (TL0).

0 1 Mode 1: 16-bit Timer/Counter.

1 0 Mode 2: 8-bit auto-reload Timer/Counter (TL0) (2)

1 1 Mode 3: TL0 is an 8-bit Timer/Counter

TH0 is an 8-bit Timer using Timer 1’s TR0 and TF0 bits .

2. Reloaded from TH0 at overflow.

0M00

AT89C51CC03

4182O–CAN–09/08

Table 32. TH0 Register

TH0 (S:8Ch)

Timer 0 High Byte Register

Reset Value = 0000 0000b

Table 33. TL0 Register

TL0 (S:8Ah)

Timer 0 Low Byte Register

Reset Value = 0000 0000b

Table 34. TH1 Register

TH1 (S:8Dh)

Timer 1 High Byte Register

Reset Value = 0000 0000b

76543210

––––––––

Bit

Number Bit

Mnemonic Description

7:0 High Byte of Timer 0.

76543210

––––––––

Bit

Number Bit

Mnemonic Description

7:0 Low Byte of Timer 0.

76543210

––––––––

Bit

Number Bit

Mnemonic Description

7:0 High Byte of Timer 1.

AT89C51CC03

4182O–CAN–09/08

Table 35. TL1 Register

TL1 (S:8Bh)

Timer 1 Low Byte Register

Reset Value = 0000 0000b

76543210

––––––––

Bit

Number Bit

Mnemonic Description

7:0 Low Byte of Timer 1.

AT89C51CC03

4182O–CAN–09/08

Timer 2 The AT89C51CC03 timer 2 is compatible with timer 2 in the 80C52.

It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2

and TL2 that are cascade- connected. It is controlled by T2CON register (See Table )

and T2MOD register (See Table 38). Timer 2 operation is similar to Timer 0 and Timer

1. C/T2 selects FT2 clock/6 (timer operation) or external pin T2 (counter operation) as

timer clock. Setting TR2 allows TL2 to be incremented by the selected input.

Timer 2 includes the following enhancements:

• Auto-reload mode (up or down counter)

• Programmable clock-output

Auto-Reload Mode The auto-reload mode c onfigures timer 2 as a 16-bit timer or event counter with auto-

matic reload. This feature is controlled by the DCEN bit in T2MOD register (See

Table 38). Setting the DCEN bit enables timer 2 to count up or down as shown in

Figure 40. In this mode the T2EX pin controls the counting direction.

When T2EX is high, timer 2 counts up. Timer overflow occurs at FFFFh which sets the

TF2 fl ag a nd g ener ates an interr upt reques t. T he overfl ow a lso c ause s th e 16 -bit v alu e

in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2.

When T2 EX is low , tim er 2 count s down. T imer un derflow oc curs wh en the c ount in th e

timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers.

The underflow sets TF2 flag and reloads FFFFh into the timer registers.

The EXF2 bi t tog gle s wh en t ime r 2 over flo w or un derfl ow, d epe ndi ng o n the di re ction of

the count. EXF2 does not generate an interrupt. This bit can be used to provide 17-bit

resolution.

Figure 40. Auto-Reload Mode Up/Down Counter

(DOWN COUNTING RELOAD VALUE)

TF2

EXF2

TH2

(8-bit)

TL2

(8-bit)

RCAP2H

(8-bit)

RCAP2L

(8-bit)

FFh

(8-bit) FFh

(8-bit)

TOGGLE

(UP COUNTING RELOAD VALUE)

TIMER 2

INTERRUPT

T2CONreg

T2EX:

1=UP

2=DOWN

CT/2

T2CON.1

TR2

T2CON.2

FT2

CLOCK

see secti on “Cloc k”

AT89C51CC03

4182O–CAN–09/08

Programmable Clock-

Output In clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock genera-

tor (See Figure 41). The input c lock increments TL2 at frequ ency FOSC/2. The timer

repeatedly counts to overflow from a loaded value. At overflow, the contents of RCAP2H

and R CAP 2L regi s ter s are lo aded into T H2 a nd T L2. In th is m ode , t ime r 2 over fl ows d o

not generate interrupts. The formula gives the clock-out frequency depending on the

system oscill ato r freque nc y and the value in the RCAP2H and RCAP2L registe rs:

For a 16 MHz system clock in x1 mode, timer 2 has a programmable frequency range of

61 Hz (FOSC/216) to 4 MHz (FOSC/4). The gene ra ted cl ock s ign al i s b rough t out t o T 2 pi n

(P1.0).

Timer 2 is programmed for the clock-out mode as follows:

• Set T2OE bit in T2MOD register.

•Clear C/T2

bit in T2CON register.

• Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L

registers.

• Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the

reload value or different depending on the application.

• To start the timer, set TR2 run control bit in T2CON register.

It is possible to use timer 2 as a baud rate generator and a clock generator simulta-

neously. For this configuration, the baud rates and clock frequencies are not

independent since both functions use the values in the RCAP2H and RCAP2L registers.

Figure 41. Clock-Out Mode

Clock OutFrequency–FT2clock

4 65536 RCAP2H–RCAP2L⁄()×

-----------------------------------------------------------------------------------------

EXEN2

EXF2

OVERFLOW

T2EX

TH2

(8-bit)

TL2

(8-bit)

TIMER 2

RCAP2H

(8-bit)

RCAP2L

(8-bit)

T2OE

T2C ON re g

T2CON reg

T2MOD reg

INTERRUPT

TR2

T2CON.2

FT2

CLOCK

Q D

Toggle

AT89C51CC03

4182O–CAN–09/08

Registers Table 36. T2CON Register

T2CON (S:C8h)

Timer 2 Control Register

Reset Value = 0000 0000b

Bit addressable

76543210

TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#

Bit

Number Bit

Mnemonic Description

7TF2

Timer 2 Overflow Flag

TF2 is not set if RCLK=1 or TCLK = 1.

Must be cleared by software.

Set by hardware on timer 2 overflow.

6EXF2

Timer 2 External Flag

Set when a capture or a reload is caused by a negative transition on T2EX pin if

EXEN2=1.

Set to cause the CPU to vector to timer 2 interrupt routine when timer 2 interrupt

is enabled.

Must be cleared by software.

5 RCLK Receive Clock bit

Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3.

Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.

4TCLK

Transmit Clock bit

Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.

Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.

3EXEN2

Timer 2 External Enable bit

Clear to ignore events on T2EX pin for timer 2 operation.

Set to cause a capture or reload when a negative transition on T2EX pin is

detected, if timer 2 is not used to clock the serial port.

2TR2

Timer 2 Run Control bit

Clea r to turn off ti mer 2.

Set to tu rn on ti mer 2.

1C/T2#

Timer/Counter 2 Select bit

Clear for timer operation (input from internal clock system: FOSC).

Set for counter operation (input from T2 input pin).

0 CP/RL2#

Timer 2 C a pture / R e load bi t

If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on

timer 2 overflow.

Clear to auto-reload on timer 2 overflows or negative transitions on T2EX pin if

EXEN2=1.

Set to capture on negative transitions on T2EX pin if EXEN2=1.

AT89C51CC03

4182O–CAN–09/08

Table 37. T2MOD Register

T2MOD (S:C9h)

Timer 2 Mode Control Register

Reset Val ue = XXXX XX00 b

Not bit address ab le

Table 38. TH2 Register

TH2 (S:CDh)

Timer 2 High Byte Register

Reset Value = 0000 0000b

Not bit address ab le

76543210

------T2OEDCEN

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

1T2OE

Timer 2 Output Enable bit

Clear to program P1.0/T2 as clock input or I/O port.

Set to program P1.0/T2 as clock output.

0 DCEN Down Counter Enable bit

Clear to disable timer 2 as up/down counter.

Set to enable timer 2 as up/down counter.

76543210

--------

Bit

Number Bit

Mnemonic Description

7-0 High Byte of Timer 2.

AT89C51CC03

4182O–CAN–09/08

Table 39. TL2 Register

TL2 (S:CC h)

Timer 2 Low Byte Register

Reset Value = 0000 0000b

Not bit address ab le

Table 40. RCAP2H Register

RCAP2H (S:CBh)

Timer 2 Reload/Capture High Byte Register

Reset Value = 0000 0000b

Not bit address ab le

Table 41. RCAP2L Register

RCAP2L (S:CAH)

TIMER 2 REload/Capture Low Byte Register

Reset Value = 0000 0000b

Not bit address ab le

76543210

--------

Bit

Number Bit

Mnemonic Description

7-0 Low Byte of Timer 2.

76543210

--------

Bit

Number Bit

Mnemonic Description

7-0 High Byte of Timer 2 Reload/Capture.

76543210

--------

Bit

Number Bit

Mnemonic Description

7-0 Low Byte of Timer 2 Reload/Capture.

AT89C51CC03

4182O–CAN–09/08

Watchdog Timer AT89C51CC03 c ontains a p owerful programm able hardware Watchdog Timer (WDT)

that automatically resets the chip if it software fails to reset the WDT before the selected

time interval has elapsed. It permits large Time-Out ranking from 16ms to 2s @Fosc =

12MHz in X1 mode.

This WDT consists of a 14-bit counter plus a 7-bit programmable counter, a Watchdog

Timer re se t r egister (WDT RS T) a nd a Wa tch dog T ime r pr ogram ming (WD TPRG ) regi s-

ter. When exiting reset, the WDT is -by default- disable.

To enabl e the WDT, the user has to wr ite the sequence 1E H and E 1H into WDTRST

ment every machine cycle while the oscillator is running and there is no way to disable

the WDT except through reset (either hardware reset or WDT overflow reset). When

WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET

puls e duratio n is 96xTOSC, where TOSC=1/FOSC. To make the best use of the WDT, it

should be serviced in those sections of code that will periodically be executed within the

time required to prevent a WDT reset

Note: When the Watchdog is enable it is impossible to change its period.

Figure 42. Watchdog Timer

WDTPRG

RESET Decoder

Control

WDTRST

Enable

14-bit COUNTER 7-bit COUNTER

Outputs

RESET

- - -

- - 2 1 0

Fwd Clock

AT89C51CC03

4182O–CAN–09/08

Watchdog Programming The three lower bits (S0, S1, S2) located into WDTPRG register permit to program the

WDT duration.

Table 42. Machine Cycle Count

To compute WD Time-Out, the following formula is applied:

Note: Svalue represents the decimal value of (S2 S1 S0)

The following table outl ine s the time- out val ue for FoscXTAL = 12 MHz in X1 mode

Table 43. Time-Out Computation

S2 S1 S0 Machine Cycle Count

000 2

001 2

010 2

011 2

100 2

101 2

110 2

111 2

S2 S1 S0 Fosc = 12 MHz Fosc = 16 MHz Fosc = 20 MHz

0 0 0 16.38 ms 12.28 ms 9.82 ms

0 0 1 32.77 ms 24.57 ms 19.66 ms

0 1 0 65.54 ms 49.14 ms 39.32 ms

0 1 1 131.07 ms 98.28 ms 78.64 ms

1 0 0 262.14 ms 196.56 ms 157.28 ms

1 0 1 524.29 ms 393.12 ms 314.56 ms

1 1 0 1.05 s 786.24 ms 629 .12 ms

1 1 1 2.10 s 1.57 s 1.25 s

FTime Out Fosc

62×WDX2X2∧214 2Svalue

×()

-----------------------------------------------------------------------------

=–

AT89C51CC03

4182O–CAN–09/08

Watchdog Timer During

Power-down Mode and

Idle

In Power-down m ode the osc illator stops, whi ch means th e WDT also s tops. While i n

Power-down mode, the user does not need to service the WDT. There are 2 methods of

exiting Power-down mode: by a hardware reset or via a level activated external interrupt

which is enabl ed p rior to e nterin g Po wer-do wn mo de. W hen Powe r-down is e xited wit h

hardware reset, the Watchdog is disabled. Exiting Power-down with an interrupt is sig-

nificantly different. The interrupt shall be held low long enough for the oscillator to

stabi lize. W hen t he int errupt is b rought h igh, the in terrupt is se rvice d. To preven t the

WDT from resetting the device while the interrupt pin is held low, the WDT is not started

until the interrupt is pulled high. It is suggested that the WDT be reset during the inter-

rupt service for the interrupt used to exit Power-down.

To ensure that the WDT does not overflow within a few states of exiting powerdown, it is

best to reset the WDT just before entering powerdown.

In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting

AT89C51CC03 while in Idle mode, the user should always set up a timer that will period-

ically exit Idle, service the WDT, and re-enter Idle mode.

WDTPRG (S:A7h)

Watchdog Timer Duration Programming Register

Reset Val ue = XXXX X000b

76543210

–––––S2S1S0

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

2S2

Wa tchdog T imer Duratio n selection bit 2

Work in conjunction with bit 1 and bit 0.

1S1

Wa tchdog T imer Duratio n selection bit 1

Work in conjunction with bit 2 and bit 0.

0S0

Wa tchdog T imer Duratio n selection bit 0

Work in conjunction with bit 1 and bit 2.

AT89C51CC03

4182O–CAN–09/08

Table 45. WDTRST Register

WDTRST (S:A6h Write only)

Watchdog Timer Enable Register

Reset Value = 1111 1111b

Note: The WDRST register is used to reset/enable the WDT by writing 1EH then E1H in

sequence without instruction between these two sequences.

76543210

––––––––

Bit

Number Bit

Mnemonic Description

7 - Watchdog Control Value

AT89C51CC03

4182O–CAN–09/08

CAN Controller The CAN Cont ro ll er pr ovides al l th e fe atu res r e qui red to im pl eme nt th e s er ia l com mun i-

cation protocol CAN as defined by BOSCH GmbH. The CAN specification as referred to

by ISO/11898 (2.0A and 2.0B) for high speed and ISO/11519-2 for low speed. The CAN

Controll er is ab le to ha ndle al l typ es of fram es (D ata, Remo te, Erro r and Ov erload) and

achieves a bitrate of 1-Mbit/sec at 8 MHz1 Crystal frequ enc y in X2 mod e.

Note: 1. At BRP = 1 sampling point will be fixed.

CAN Protocol The CAN protoc ol is an inte rnatio nal sta ndard de fined in the ISO 11 898 for high speed

and ISO 11519-2 for low speed.

Principles CAN is based on a broadcast communication mechanism. This broadcast communica-

tion is achieved by using a message oriented transmission protocol. These messages

are identified by using a message identifier. Such a message identifier has to be unique

within the whole network and it defines not only the content but also the priority of the

message.

The priority at which a message is transmi tted compared to another less urgent mes-

sage is spe cifie d by th e iden tifier of ea ch message. The priorities are laid down during

system design in the form of corresponding binary values and cannot be changed

dynamically. The identifier with the lowest binary number has the highest priority.

Bus acc ess co nflicts ar e resolved by bit-wis e arbitrati on on the i dentifier s involved by

each node observing the bus level bit for bit. This happens in accordance with the "wired

and" m echanism, b y w hic h t he d omi nan t state ove rw rit es the rece ss ive sta t e. Th e c om-

petit ion for bus alloc ation is l ost by a ll node s wi th r ecessiv e tr ansmis sion a nd do minan t

obser vation. All t he "los ers" a utomati cally become rece ivers of the mess age wi th the

highest priority and do not re-attempt transmission until the bus is available again.

Message Formats The CAN protocol supports two messa ge frame formats, the o nly essential difference

being in the length of the identifier. The CAN standard frame, also known as CAN 2.0 A,

suppor ts a l ength of 11 bit s for the i denti fier, a nd the C AN exte nded frame , also know n

as CAN 2.0 B, supports a length of 29 bits for the identifier.

Can Standard Frame

Figure 43. CAN Standard Fra mes

A message in the CAN standard frame format begins with the "Start Of Frame (SOF)",

this is followed by the "Arbitration field" which consist of the identifier and the "Remote

Transmission Reque st (RTR)" bit u sed to distinguish between the data fram e and the

data request frame called remote frame. The following "Control field" contains the "IDen-

tifier Extension (IDE)" bit and the "Data Length Code (DLC)" used to indicate the

11-bit identifier

ID10..0

Interframe

Space

4-bit DLC

DLC4..0 CRC

del. ACK

del.

15-bit CRC

0 - 8 bytes

SOF

SOF RTR IDE r0 ACK 7 bits Intermission

3 bits

Bus Idle Bus Idle

(Indefinite)

Arbitration

Field Data

Field

Data Frame

Control

Field End of

Frame

CRC

Field ACK

Field Interframe

Space

11-bit identifier

ID10..0

Interframe

Space

4-bit DLC

DLC4..0 CRC

del. ACK

del.

15-bit CRC

SOF

SOF RTR IDE r0 ACK 7 bits Intermission

3 bits

Bus Idle Bus Idle

(Indefinite)

Arbitration

Field

Remote Frame

Control

Field End of

Frame

CRC

Field ACK

Field Interframe

Space

AT89C51CC03

4182O–CAN–09/08

number of follow ing data by tes in the "D ata field ". In a remote frame, the DLC contai ns

the numbe r of reque sted data byt es. The "Data field" that fol lows can hol d up to 8 data

bytes . The fra me integrity is guar anteed by the follo wing "Cyc lic Redund ant Check

(CRC) " sum . The "A CKno wledg e (ACK ) field " comp romis es the ACK sl ot and the ACK

delimiter. The b it in t he A C K sl ot is se nt as a re ce ss iv e bit and is ov erwr itt en a s a dom i-

nant bit by the receivers which have at this time received the data correctly. Correct

messages are acknowledged by the receivers regardless of the result of the acceptance

test. T he end of the mess age is in dicat ed by "E nd Of Fram e (EOF )". The " Inter missio n

Frame Space (IFS)" is the minimum number of bits separating consecutive messages. If

there is no following bus access by any node, the bus remains idle.

CAN Extended Frame

Figure 44. CAN Extended F rames

A mess age i n the C AN ex tended frame format i s li kely t he sa me as a mes sage in CA N

standard frame format. The difference is the length of the identifier used. The identifier is

made up of the exi sting 11-bit id entifier (base id entifier ) and an 18-bit ext ension (iden ti-

fier exten si on). Th e d istin ct ion be tween CA N s tan dar d frame for ma t an d CA N e xtende d

frame for ma t is mad e by us ing the IDE bit whi ch is tr ansmi tted as dominan t in cas e o f a

frame in CAN standard frame format, and transmitted as recessive in the other case.

Format Co-existence As th e two formats have to co- exist on one bus, it is laid down which mes sage has

higher priority on the bus in the case of bus access collision with different formats and

the same identifier / base identifier: The message in CAN standard frame format always

has priority over the message in extended format.

There are three different types of CAN modules available:

– 2.0A - Considers 29 bit ID as an error

– 2.0B Passive - Ignores 29 bit ID messages

– 2.0B Active - Handles both 11 and 29 bit ID Messages

Bit Timing To ensure correct sampling up to the last bit, a CAN node needs to re-synchronize

throughout the entire frame. This is done at the beginning of each message with the fall-

ing edge SOF and on each recessive to dominant edge.

Bit Construction One CAN bit tim e is specifi ed as four non-ov erlapp ing time segments . Each s egment is

construc ted f ro m an in tege r m ul tip le o f the T im e Quan tum. The Ti me Q u antu m or T Q is

the smallest discrete timing resolution used by a CAN node.

11-bit base identifier

IDT28..18

Interframe

Space

CRC

del. ACK

del.

15-bit CRC

0 - 8 bytes

SOF

SOF SRR IDE ACK 7 bits Intermission

3 bits

Bus Idle Bus Idle

(Indefinit

Arbitration

Field

Arbitration

Field Data

Field

Data Frame

Control

Field

Control

Field

End of

Frame

CRC

Field ACK

Field Interframe

Space

11-bit base identifier

IDT28..18

18-bit identifier extension

ID17..0

18-bit identifier extension

ID17..0

Interframe

Space

4-bit DLC

DLC4..0 CRC

del. ACK

del.

15-bit CRC

SOF

SOF SRR IDE r0

4-bit DLC

DLC4..0

RTR

r0r1

r1 ACK 7 bits Intermission

3 bits

Bus Idle Bus Idle

(Indefinite)

Remote Frame

End of

Frame

CRC

Field ACK

Field Interframe

Space

AT89C51CC03

4182O–CAN–09/08

Figure 45. CAN Bit Construction

Synchronization Segment The first segment is used to synchronize the various bus nodes.

On transm ission , at the start of thi s segme nt, the curren t bit leve l is output. If th ere is a

bit state c ha nge b etwe en th e pr ev io us bit and t he c urr ent b it, th en t he bu s s tat e ch ang e

is expected to occur within this segment by the receiving nodes.

Propagation Time Segment This segment is used to compensate for signal delays across the network.

This i s necessa ry to c ompensate for signa l propag ation del ays on the bus li ne and

through the transceivers of the bus nodes.

Phase Segment 1 Phase Segment 1 is used to compensate for edge phase errors.

This segment may be lengthened during resynchronization.

Sample Point The sample point is the point of time at which the bus level is read and interpreted as the

value of the respective bit. Its location is at the end of Phase Segment 1 (between the

two Phase Segme nts ).

Phase Segment 2 This segment is also used to compensate for edge phase errors.

This segm ent may be shortened during resynchroniza tion, but the length has to be at

least as long as the information processing time and may not be more than the length of

Phase Segment 1.

Information Processing Time It is the time required for the logic to determine the bit level of a sampled bit.

The Info rmation processin g Time begin s at the sam ple point , is measur ed in TQ and is

fixed at 2 TQ for the Atmel CAN. Since Phase Segment 2 also begins at the sample

point and is the l ast se gment i n the bit tim e, Pha se Segme nt 2 minimum shall not b e

less than the Information processing Time.

Bit Lengthening As a result of resynchronization, Phase Segment 1 may be lengthened or Phase Seg-

ment 2 may be s hortened to compensa te for oscillator tolerances. If, for example, the

transmitte r oscil lator is slower tha n the recei ver osci llator , the next fal ling edge used for

resynchronization may be delayed. So Phase Segment 1 is lengthened in order to

adjust the sample point and the end of the bit time.

Time Quantum

(producer)

Nominal CAN Bit Time

Segments

(producer) SYNC_SEG PROP_SEG PHASE_SEG_1 PHASE_SEG_2

propagation

delay

Segments

(consumer) SYNC_SEG PROP_SEG PHASE_SEG_1 PHASE_SEG_2

Sample Point

Transmission Point

(producer)

CAN Frame

(producer)

AT89C51CC03

4182O–CAN–09/08

Bit Shortening If, on the other hand, the transmitter oscillator is faster than the receiver one, the next

fallin g edge use d for resy nchroni zation may be too ear ly. So Pha se Segm ent 2 in bit N

is shortened in order to adjust the sample point for bit N+1 and the end of the bit time

Synchronization Jump Width The limit to the amount of lengthening or shortening of the Phase Segments is set by the

Resynchronization Jump Width.

This segment may not be longer than Phase Segment 2.

Programming the Sample Point Programming of the sample point allows "tuning" of the characteristics to suit the bus.

Early sa mpling al lows more T ime Quanta in the Phase Se gment 2 so the Synchron iza-

tion Jump Width can be programmed to its maximum. This maximum capacity to

shorten or lengthen the bit time decreases the sensitivity to node oscillator tolerances,

so that lower cost oscillators such as ceramic resonators may be used.

Late sampling allows more Time Quanta in the Propagation Time Segment which allows

a poorer bus topology and maximum bus length.

Arbitration

Figure 46. Bus Arbitration

The CAN protocol handles bus accesses according to the concept called “Carrier Sense

Multiple Access with Arbitration on Message Priority”.

During trans mission, arbitra tion on the CAN bus can be lost to a com peting device with

a higher priority CAN Identifier. This arbitration concept avoids collisions of messages

whose transmission was started by more than one node simultaneously and makes sure

the most important message is sent first without time loss.

The bu s acces s confl ict is res olved du ring th e arbitr ation fi eld mos tly ove r the iden tifier

value . If a dat a frame and a remo te frame with the sa me identifier ar e initiated at th e

same time, the data frame prevails over the remote frame (c.f. RTR bit).

Errors The CAN protocol signals any errors immediately as they occur. Three error detection

mechanisms are implemented at the message level and two at the bit level:

Error at Message Level • Cyclic Redundancy Check (CRC)

The CRC safeguards the information in the frame by adding redundant check bits at

the transmission end. At the receiver these bits are re-computed and tested against

the received bits. If they do not agree there has been a CRC error.

•Frame Check

This mechanism verifies the structure of the transmitted frame by checking the bit

node A

TXCAN

node B

TXCAN

ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0

SOF

RTR IDE

CAN bus

- - - - - - - - -

Arbitration lost

Node A loses the bus

Node B wins the bus

AT89C51CC03

4182O–CAN–09/08

fields against the fixed format and the frame size. Errors detected by frame checks

are designated "format errors".

• ACK Errors

As already mentioned frames received are acknowledged by all receivers through

positive acknowledgement. If no acknowledgement is received by the transmitter of

the message an ACK error is indicated.

Error at Bit Level • Monitoring

The ability of the transmitter to detect errors is based on the monitoring of bus

signals. Each node which transmits also observes the bus level and thus detects

differences between the bit sent and the bit received. This permits reliable detection

of global errors and errors local to the transmitter.

• Bit Stuffing

The coding of the individual bits is tested at bit level. The bit representation used by

CAN is "Non Return to Zero (NRZ)" coding, which guarantees maximum efficiency

in bit coding. The synchronization edges are generated by means of bit stuffing.

Error Signalling If one or more errors are discovered by at least one node using the above mechanisms,

the current transmission is aborted by sending an "error flag". This prevents other nodes

acceptin g the mes sage and thus ensur es the c onsistency of data th roughout the net-

work. After transmi ssion of an erroneou s message th at has been aborted, the sender

automatically re-attempts transmission.

CAN Controller

Description The CAN Controller accesses are made through SFR.

Several operations are possible by SFR:

• arithmetic and logic operations, transfers and program control (SFR is accessible by

direct addressing).

• 15 independent message objects are implemented, a pagination system manages

their ac ce ss es .

Any me ssage obj ec t c an be pro gr amm ed in a r ec ept ion b u ffe r bl oc k ( ev en non -con sec-

utive buffer s). For th e recepti on of def ined me ssages one or sev eral re ceiver me ssag e

objects can be masked without participating in the buffer feature. An IT is generated

when the buffer is full. The fr am es followi ng the buffe r-ful l i nterr upt will not be take n in to

account until at least one of the buffer message objects is re-enabled in reception.

Higher priori ty of a message object for rec eption or transmi ssion is given to the lower

message object number.

The progr amma ble 16 -bit Time r (CANT IMER ) is u sed to stam p each rec eive d and sent

message in the CANSTMP register. This timer starts counting as soon as the CAN con-

troller is enabled by the ENA bit in the CANGCON register.

The Time Trigger Communication (TTC) protocol is supported by the AT89C51CC03.

AT89C51CC03

4182O–CAN–09/08

Figure 47. CAN Controll er Block Diag r am

CAN Controller Mailbox

and Registers

Organization

The p agin ation al lows m anage me nt of th e 321 re gist ers in cludi ng 300 (15x2 0) Byt es of

mailbox via 34 SFR’s.

All actions on the message object window S FRs apply to the corresponding message

object registers pointed by the message object number find in the Page message object

Bit

Stuffing /Destuffing

Cyclic

Redundanc y Chec k

Receive Transmit

Error

Counter

Rec/Tec

Bit

Timing

Logic

Page

Encoder

µC-Core Interface

Core

Control

Interface

Bus

TxDC

RxDC

AT89C51CC03

4182O–CAN–09/08

Figure 48. CAN Controll er Mem ory Orga ni za tio n

Ch.14 - ID Tag - 1

Ch.14 - ID Tag - 2

Ch.14 - ID Tag - 4

Ch.14 - ID Tag - 3

Ch.14 - ID Mask - 1

Ch.14 - ID Mask - 2

Ch.14 - ID Mask - 4

Ch.14 - ID Mask - 3

Ch.14 - Message Data - byte 0

General Control

General Status

Bit Timing - 1

Bit Timing - 2

Bit Timing - 3

Enable Interrupt

Enable Interrupt message object - 1

Page message object

message object Status

message object Control and DLC

Message Data

ID T ag - 1

ID T ag - 2

ID T ag - 4

ID T ag - 3

ID Mask - 1

ID Mask - 2

ID Mask - 4

ID Mask - 3

message ob ject 0 - Status

message object 0 - Control and DLC

Ch.0 - ID Tag - 1

Ch.0 - ID Tag - 2

Ch.0 - ID Tag - 4

Ch.0 - ID Tag - 3

Ch.0 - Message Data - byte 0

message object 14 - Status

message object 14 - Control and DLC

Enable Interrupt message object - 2

Status Interrupt message object - 1

Status Interrupt message object - 2

(message object number)(Data offset)

SFR’s On-chip CAN Controller registers

15 message objects

8 Bytes

TimStmp High

TimStmp Low

Ch.0 - ID Mask- 1

Ch.0 - ID Mask- 2

Ch.0 - ID Mask - 4

Ch.0 - ID Mask- 3

CANTimer High

CANTimer Low

TimTT C High

TimTTC Low

TEC counter

REC counter

Timer Control

Enable message object - 1

Enable message object - 2

message object Window SFRs

Ch.0 TimStmp High

Ch.0 TimStmp Low

Ch.14 TimStmp High

Ch.14 TimS tmp Low

General Interrupt

AT89C51CC03

4182O–CAN–09/08

Working on Message Obje cts The Page message object register (CANPAGE) is used to select one of the 15 message

objects. Then, message object Control (CANCONCH) and message object Status

(CANSTCH) are available for this selected message object number in the corresponding

SFRs. A single register (CANMSG ) is used for the message. The mail box pointer is

managed by the Page message object register with an auto-incrementation at the end of

each access. The range of this counter is 8.

Note that the mai box is a pure RA M, ded ic ate d to one mes sage ob ject, witho ut ov erla p.

In most cases , it is not nec essary to transfe r the rec eived messag e into t he stand ard

memory. The message to be transmitted can be built di rectly in the maibox. Most calcu-

lations or tests can be executed in the mailbox area which provide quicker access.

CAN Controller

Management In order to enable the CAN Controller correctly the following registers have to be

initialized:

• General Control (CANGCON),

• Bit Timing (CANBT 1, 2 and 3),

• And for each page of 15 message objects

– m es sage obj ec t Control (CANCONCH),

– message object Status (CANSTCH).

Durin g operatio n, the CAN E nable me ssage obj ect regi sters 1 and 2 ( CANEN 1 an d 2)

gives a fast overview of the message objects availability.

The CAN messages can be handled by interrupt or polling modes.

A message object can be configured as follows:

• Transmit message object,

• Receive message object,

• Receive buffer message object.

• Disable

This configuration is made in the CONCH1:2 field of the CANCONCH register (see

Table 46).

When a me ssage obj ect is co nfigured , the corr espondin g ENCH bit of CANEN 1 an d 2

Table 46. Configuration for CONCH1:2

When a Trans mitter or Receiv er actio n of a mes sage obj ect is c omplet ed, the co rre-

spond ing ENCH bi t of the CANE N 1 and 2 regi ster is cl eared . In order to re-enabl e the

message object, it is necessary to re-write the configuration in CANCONCH register.

Non-consecutive message objects can be used for all three types of message objects

(Transmitter, Receiver and Receiver buffer),

CONCH 1 CONCH 2 Type of Message Object

0 0 Disable

0 1 Transmitter

1 0 Receiver

1 1 Receiver buffer

AT89C51CC03

4182O–CAN–09/08

Buffer Mode A ny mess age obje ct can be used t o define one buff er, incl uding non-con secut ive mes-

sage objects, and with no limitation in number of message objects used up to 15.

Each message object of the buffer must be initialized CONCH2 = 1 and CONCH1 = 1;

Figure 49. Buffer mode

The same acceptance filter must be defined for each message objects of the buffer.

When there is no mask on the identifier or the IDE, all messages are accepted.

A received frame will always be stored in the lowest free message object.

When the flag Rxok is set o n one of th e buffer message objects, this m essage objec t

can then be r ea d b y t he a ppl icati on . T hi s flag mu st then be cl eared by th e software an d

the message object re-enabled in buffer reception in order to free the message object.

The OVRBUF flag in the CANGIT register is set when the buffer is full. This flag can

generate an interrupt.

The frames following the buffer-full interrupt will not stored and no status will be over-

written in the CANSTCH registers invo lved in the buffer until at least one of the buffer

message objects is re-enabled in reception.

This flag must be cleared by the software in order to acknowledge the interrupt.

message object 0

message object 1

message object 2

message object 3

message object 4

message object 5

message object 6

message object 7

message object 8

message object 9

message object 10

message object 11

message object 12

message object 13

Block buffe r

buffer 0

buffer 1

buffer 2

buffer 3

buffer 4

buffer 5

buffer 6

buffer 7

message object 14

AT89C51CC03

4182O–CAN–09/08

IT CAN Management The dif fer ent int er rupts are:

• Transmissio n interrupt,

• Recepti on int erru pt,

• Interrupt on error (bit error, stuff error, crc error, form error, acknowledge error),

• Interrupt when Buffer receive is full,

• Interrupt on overrun of CAN Timer.

Figure 50. CAN Controller Interrupt Structure

To enable a transmission interrupt:

• Enable General CAN IT in the interrupt system register,

• Enable interrupt by message object, EICHi,

• Enable transmission interrupt, ENTX.

To enable a reception interrupt:

• Enable General CAN IT in the interrupt system register,

• Enable interrupt by message object, EICHi,

• Enable reception interrupt, ENRX.

To enable an interrupt on message object error:

SIT i

i=0

i=14

OVRIT

ENRX

CANGIE.5 ENTX

CANGIE.4 ENERCH

CANGIE.3

ENBUF

CANGIE.2 ECAN

IEN1.0

RXOK i

CANSTCH.5

TXOK i

CANSTCH.6

BERR i

CANSTCH.4

SERR i

CANSTCH.3

FERR i

CANSTCH.1

CERR i

CANSTCH.2

AERR i

CANSTCH.0

EICH i

CANIE1/2

OVRTIM

CANGIT.5

CANIT

CANGIT.7

OVRBUF

CANGIT.4

FERG

CANGIT.1

AERG

CANGIT.0

SERG

CANGIT.3

CERG

CANGIT.2

ENERG

CANGIE.1

ETIM

IEN1.2

SIT i

CANSIT1/2

AT89C51CC03

4182O–CAN–09/08

• Enable General CAN IT in the interrupt system register,

• Enable interrupt by message object, EICHi,

• Enable interrupt on error, ENERCH.

To enable an interrupt on general error:

• Enable General CAN IT in the interrupt system register,

• Enable interrupt on error, ENERG.

To enable an interrupt on Buffer-full condition:

• Enable General CAN IT in the interrupt system register,

• Enable interrupt on Buffer full, ENBUF.

To enable an interrupt when Timer overruns:

• Enable Overrun IT in the interrupt system register.

When an interrupt occurs, the corresponding message object bit is set in the SIT

To acknowled ge an interrupt, the corres ponding CANSTCH bits (RX OK, TXOK,...) or

CANGIT bits (OVRTIM, OVRBUF,...), must be cleared by the software application.

When the C AN no de is in tr an sm is si on an d dete ct s a For m Err or in its fr ame , a bit Err or

will al so be r ai sed . Conseq uently, two co nse cu tiv e in ter rupts c an oc cur , b oth due to th e

same error.

When a mess age object error occu rs and is set in CANSTCH r egister, no gener al error

are set in CANGIE register.

AT89C51CC03

4182O–CAN–09/08

Bit Timing and Baud Rate

FSM’s (Finite State Machine) of the CAN channel need to be synchronous to the time

quantum. So, the input clock for bit timing is the clock used into CAN channel FSM’s.

Field and se gme nt abbrev ia tions:

• BRP: Baud Rate Prescaler.

• TQ: Time Quantum (output of Baud Rate Prescaler).

• SYNS: SYNchronization Segment is 1 TQ long.

• PRS: PRopagation time Segment is programmable to be 1, 2, ..., 8 TQ long.

• PHS1: PHase Segment 1 is programmable to be 1, 2, ..., 8 TQ long.

• PHS2: PHase Segment 2 is programmable to be superior or equal to the

INFORMATION PROCESSING TIME and inferior or equal to TPSH1.

• INFORMATION PROCESSING TIME is 2 TQ.

• SJW: (Re) Synchronization Jump Width is programmable to be minimum of PHS1

and 4.

The total number of TQ in a bit time has to be programmed at least from 8 to 25.

Figure 51. Sample And Transmission Point

The baud rate selection is made by Tbit calculation:

Tbit = Tsyns + Tprs + Tphs1 + Tphs2

1. Tsyns = Tscl = (BRP[5..0]+ 1)/Fcan = 1TQ.

2. Tprs = (1 to 8) * Tscl = (PRS[2..0]+ 1) * Tscl

3. Tphs1 = (1 to 8) * Tscl = (PHS1[2..0]+ 1) * Tscl

4. Tphs2 = (1 to 8) * Tscl = (PHS2[2..0]+ 1) * Tscl

Tphs2 = Max of (Tphs1 and 2 TQ)

5. Tsjw = (1 to 4) * Tscl = (SJW[1..0]+ 1) * Tscl

The total number of Tscl (Time Quanta) in a bit time must be comprised between 8 to

25.

FCAN

CLOCK Prescal er BRP

PRS 3-bit length

PHS1 3-bit length

PHS2 3-bit length

SJW 2-bit length

Bit Timing

System clock Tsc l

Time Quantum

Sample point

Transmission poin

AT89C51CC03

4182O–CAN–09/08

Figure 52. General Structure of a Bit Period

example of bit timing determination for CAN baudrate of 500kbit/s:

Fosc = 12 MHz in X1 mode => FCAN = 6 MHz

Verify that the CAN baud rate you want is an integer division of FCAN clock.

FCAN/CAN baudrate = 6 MHz/500 kHz = 12

The time quanta TQ must be comprised between 8 and 25: TQ = 12 and BRP = 0

Define the various timing parameters: Tbit = Tsyns + Tprs + Tphs1 + Tphs2 = 12TQ

Tsyns = 1TQ and Tsjw =1TQ => SJW = 0

If we chose a sample point at 66.6% => Tphs2 = 4TQ => PHS2 = 3

Tbit = 12 = 4 + 1 + Tphs1 + Tprs, let us choose Tprs = 3 Tphs1 = 4

PHS1 = 3 and PRS = 2

BRP = 0 so CANBT1 = 00h

SJW = 0 and PRS = 2 so CANBT2 = 04h

PHS2 = 3 and PHS1 = 3 so CANBT3 = 36h

Bit Rate Prescaler

oscillator

1/ Fcan

Tscl

system clock

one nominal bit

Tsyns (*) Tprs

Sample Point

(*) Synchronization Segment: SYNS

Tbit

Tsyns = 1xTscl (fixed)

data

Tbit Tsyns Tprs Tphs1Tphs2++ +=

Tbit calculation:

Transmission Point

Tphs1 + Tsjw (3) Tphs2 - Tsjw (4)

(1) Phase error ≤ 0

(2) Phase error ≥ 0

(3) Phase error > 0

(4) Phase error < 0

Tphs2 (2)

Tphs1 (1)

AT89C51CC03

4182O–CAN–09/08

Fault Confinement With respect to fault confinement, a unit may be in one of the three following status:

• error active

• error passive

• bus off

An error active unit takes part in bus communication and can send an active error frame

when the CAN macro detects an error.

An error passive unit cannot send an active error frame. It takes part in bus communica-

tion, but when an error is detected, a passive error frame is sent. Also, after a

transmission, an error passive unit will wait before initiating further transmission.

A bus off unit is not allowed to have any influence on the bus.

For fault confinement, two error counters (TEC and REC) are implemented.

See CAN Specification for details on Fault confinement.

Figure 53. Line Error Mode

TEC>255

Error

Active

Error

Passive Bus

Off

Init.

TEC<127

and

REC<127

TEC>127

REC>127 128 occurrences

11 consec utiv e

recessive

bit

TEC: Transmit Error Counter

REC: Receive Error Counter

ERRP = 0

BOFF = 0

ERRP = 0

BOFF = 1

ERRP = 1

BOFF = 0

AT89C51CC03

4182O–CAN–09/08

Acceptance Filter Upon a reception hit (i.e., a good comparison between the ID+RTR+RB+IDE received

and an ID+RT R+RB+IDE specified while takin g the comparis on mask into ac count) the

ID+RTR+RB+IDE received are written over the ID TAG Registers.

ID => IDT0-29

RTR => RTRTAG

RB => RB0-1TAG

IDE => IDE in CANCONCH register

Figure 54. Acceptance filter block diagram

example:

To accept only ID = 318h in part A.

ID MSK = 111 1111 1111 b

ID TAG = 011 0001 1000 b

13/32

RxDC

13/32

Write

13/32

Hit

13/32

ID MSK Registers (Ch i)

ID and RB RTR IDE

Rx Shift Register (internal)

ID and RB RTR IDE

Enable (Ch i)

ID TAG Regis ters (Ch i) and CanC o nc h

ID and RB RTR IDE

CAN SFRs

100

AT89C51CC03

4182O–CAN–09/08

Data and Remote Frame Description of the different steps for:

• Data Frame

• Remote Frame, With Automatic Reply,

• Remote Frame

u uu uu

0 1 x 0 0 u uu uu

ENCH

RTR

RPLV

TXOK

RXOK

0 1 x 0 0

c uc uu

0 0 x 1 0 u cc uu

0 0 x 0 1

DATA FRAME

Node A Node B

ENCH

RTR

RPLV

TXOK

RXOK

message object in reception

message object disabled

message object in

message object disabled

transmission

u uu uu

1 1 x 0 0

c uu uc

0 1 x 1 0

c uu

0 0 x 0 1

REMOTE FRAME

DATA FRAME

u uu uu

1 1 1 0 0

u uu cc

0 1 0 0 0

c uc cu

0 0 0 1 0

ENCH

RTR

RPLV

TXOK

RXOK

ENCH

RTR

RPLV

TXOK

RXOK

(immediate)

message object in reception

message object in transmission

message object disabled

message object in

reception by CAN by CAN controller

transmission

controller

message object disabled

u uu uu

1 1 x 0 0 u uu uu

ENCH

RTR

RPLV

TXOK

RXOK

1 1 0 0 0

c uu uc

0 1 x 1 0 u cc uu

1 0 0 0 1

REMOTE FRAME

ENCH

RTR

RPLV

TXOK

RXOK

u uu uu

0 1 x 0 0

c uc uu

0 0 x 1 0

u cc uc

0 0 x 0 1

DATA FRAME

(deferred)

u: modified by user

ic: modified by CAN

messa ge obje ct in re cep tio n

message object in transmission by use

message object disabled

message object in

message object disabled

reception by user

transmission

101

AT89C51CC03

4182O–CAN–09/08

Time Trigger

Communication (TTC)

and Me ss age Sta mping

The AT89C51CC03 has a programmable 16-bit Timer (CANTIMH and CANTIML) for

message stamp and TTC.

This CAN Timer starts after th e CAN control ler is enabled by th e ENA bit in t he CANG -

CON register.

Two modes in the timer are implemented:

• Time Trigge r Comm uni ca tio n:

– Capture of this timer value in the CANTTCH and CANTTCL registers on

Start Of Frame (SOF) or End Of Frame (EOF), depending on the SYNCTTC

bit in the CANGCON register, when the network is configured in TTC by the

TTC bit in the CANGCON register.

Note: In this mode, CAN only sends the frame once, even if an error occurs.

• Messa ge Stamping

– Capture of this timer value in the CANSTMPH and CANSTMPL registers of

the message object which received or sent the frame.

– All messages can be stamps.

– The stamping of a received frame occurs when the RxOk flag is set.

– The stamping of a sent frame occurs when the TxOk flag is set.

The CAN Timer works in a roll-over from FFFFh to 0000h which serves as a time base.

When the timer roll-over from FFFFh to 0000h, an interrupt is generated if the ETIM bit

in the interrupt enable register IEN1 is set.

Figure 55. Block Diagram of CAN Timer

EOF on CAN frame

ENA

CANGCON.1

CANTCON

RXOK i

CANSTCH.5

TXOK i

CANSTCH.4

÷ 6

Fcan

CLOCK

SOF on CAN frame

TTC

CANGCON.5 SYNCTTC

CANGCON.4

CANTTCH and CANTTCL

CANSTMPH and CANSTMPL

CANTIMH and CANTIML

OVRTIM

CANGIT.5

When 0xF FFF to 0x00 00

102

AT89C51CC03

4182O–CAN–09/08

CAN Autobaud and

Listening Mode To activate the Autobaud feature, the AUTOBAUD bit in the CANGCON register must

be set. In this mode , the CAN cont roll er is only list ening to the line withou t ackno wledg-

ing the received messages. It cannot send any message. The error flags are updated.

The bit timing can be adjusted until no error occurs (good configuration find).

In this mode, the error counters are frozen.

To go back to the standard mode, the AUTOBAUD bit must be cleared.

Figure 56. Autobaud Mode

Routines Examples 1. Ini t of CAN macro

// Reset the CAN macro

CANGCON = 01h;

// Disable CAN interrupts

ECAN = 0;

ETIM = 0;

// Init the Mailbox

for num_page =0; num_page <15; num_page++

{

CANPAGE = num_channel << 4;

CANCONCH = 00h

CANSTCH = 00h;

CANIDT1 = 00h;

CANIDT2 = 00h;

CANIDT3 = 00h;

CANIDT4 = 00h;

CANIDM1 = 00h;

CANIDM2 = 00h;

CANIDM3 = 00h;

CANIDM4 = 00h;

for num_data =0; num_data <8; num_data++)

{

CANMSG = 00h;

}

// Configure the bit timing

CANBT1 = xxh

CANBT2 = xxh

CANBT3 = xxh

TxD

RxDC’

AUTOBAUD

CANGCON.3 RxD

TxDC’

103

AT89C51CC03

4182O–CAN–09/08

// Enable the CAN macro

CANGCON = 02h

2. Configure message object 3 in reception to receive only standard (11-bit identi-

fier) message 100h

// Select the message object 3

CANPAGE = 30h

// Enable the interrupt on this message object

CANIE2 = 08h

// Clear the status and control register

CANSTCH = 00h

CANCONCH = 00h

// Init the acceptance filter to accept only message 100h in standard mode

CANIDT1 = 20h

CANIDT2 = 00h

CANIDT3 = 00h

CANIDT4 = 00h

CANIDM1 = FFh

CANIDM2 = FFh

CANIDM3 = FFh

CANIDM4 = FFh

// Enable channel in reception

CANCONCH = 88h // enable reception

Note: To enable the CAN interrupt in reception:

EA = 1

ECAN = 1

CANGIE = 20h

3. Send a message on the message object 12

// Select the message object 12

CANPAGE = C0h

// Enable the interrupt on this message object

CANIE1 = 01h

// Clear the Status register

CANSTCH = 00h;

// load the identifier to send (ex: 555h)

CANIDT1 = AAh;

CANIDT2 = A0h;

// load data to send

CANMSG = 00h

CANMSG = 01h

CANMSG = 02h

CANMSG = 03h

CANMSG = 04h

CANMSG = 05h

CANMSG = 06h

CANMSG = 07h

// configure the control register

CANCONCH = 18h

104

AT89C51CC03

4182O–CAN–09/08

4. Interrupt routine

// Save the current CANPAGE

// Find the first message object which generate an interrupt in CANSIT1 and CANSIT2

// Select the corresponding message object

// Analyse the CANSTCH register to identify which kind of interrupt is generated

// Manage the interrupt

// Clear the status register CANSTCH = 00h;

// if it is not a channel interrupt but a general interrupt

// Manage the general interrupt and clear CANGIT register

// restore the old CANPA G E

105

AT89C51CC03

4182O–CAN–09/08

CAN SFR’s

Table 47. CAN SFR’s With Reset Values

0/8(1) 1/9 2/A 3/B 4/C 5/D 6/E 7/F

F8h IPL1

xxxx x000 CH

0000 0000 CCAP0H

0000 0000 CCAP1H

0000 0000 CCAP2H

0000 0000 CCAP3H

0000 0000 CCAP4H

0000 0000 FFh

F0h B

0000 0000 ADCLK

xx00 x000 ADCON

0000 0000 ADDL

xxxx xx00 ADDH

0000 0000 ADCF

0000 0000 IPH1

xxxx x000 F7h

E8h IEN1

xxxx x000 CL

0000 0000 CCAP0L

0000 0000 CCAP1L

0000 0000 CCAP2L

0000 0000 CCAP3L

0000 0000 CCAP4L

0000 0000 EFh

E0h ACC

0000 0000 E7h

D8h CCON

00xx xx00 CMOD

00xx x000 CCAPM0

x000 0000 CCAPM1

x000 0000 CCAPM2

x000 0000 CCAPM3

x000 0000 CCAPM4

x000 0000 DFh

D0h PSW

0000 0000 FCON

0000 0000 EECON

xxxx xx00 FSTA

xxxx xx00 SPCON

0001 0100 SPSCR

0000 0000 SPDAT

xxxx xxxx D7h

C8h T2CON

0000 0000 T2MOD

xxxx xx00 RCAP2L

0000 0000 RCAP2H

0000 0000 TL2

0000 0000 TH2

0000 0000 CANEN1

xx00 0000 CANEN2

0000 0000 CFh

C0h P4

xxxx xx11 CANGIE

0000 0000 CANIE1

xx00 0000 CANIE2

0000 0000 CANIDM1

xxxx xxxx CANIDM2

xxxx xxxx CANIDM3

xxxx xxxx CANIDM4

xxxx xxxx C7h

B8h IPL0

x000 0000 SADEN

0000 0000 CANSIT1

0x00 0000 CANSIT2

0000 0000 CANIDT1

xxxx xxxx CANIDT2

xxxx xxxx CANIDT3

xxxx xxxx CANIDT4

xxxx xxxx BFh

B0h P3

1111 1111 CANPAGE

0000 0000 CANSTCH

xxxx xxxx CANCONCH

xxxx xxxx CANBT1

xxxx xxxx CANBT2

xxxx xxxx CANBT3

xxxx xxxx IPH0

x000 0000 B7h

A8h IEN0

0000 0000 SADDR

0000 0000 CANGSTA

0000 0000 CANGCON

0000 x000 CANTIML

0000 0000 CANTIMH

0000 0000 CANSTMPL

0000 0000 CANSTMPH

0000 0000 AFh

A0h P2

1111 1111 CANTCON

0000 0000 AUXR1

xxxx 00x0 CANMSG

xxxx xxxx CANTTCL

0000 0000 CANTTCH

0000 0000 WDTRST

1111 1111 WDTPRG

xxxx x000 A7h

98h SCON

0000 0000 SBUF

0000 0000 CANGIT

0x00 0000 CANTEC

0000 0000 CANREC

0000 0000 CKCON1

xxxx xxx0 9Fh

90h P1

1111 1111 97h

88h TCON

0000 0000 TMOD

0000 0000 TL0

0000 0000 TL1

0000 0000 TH0

0000 0000 TH1

0000 0000 AUXR

X001 0100 CKCON

0000 0000 8Fh

80h P0

1111 1111 SP

0000 0111 DPL

0000 0000 DPH

0000 0000 PCON

0000 0000 87h

0/8(1) 1/9 2/A 3/B 4/C 5/D 6/E 7/F

106

AT89C51CC03

4182O–CAN–09/08

Registers Table 48. CANGCON Register

CANGCON (S:ABh)

CAN General Control Register

Reset Value = 0000 0x00b

7654 3210

ABRQ OVRQ TTC SYNCTTC AUTOBAUD TEST ENA GRES

Bit

Number Bit Mnemo n ic Description

7ABRQ

Abort Request

Not an auto-resetable bit. A reset of the ENCH bit (message object control

and DLC register) is done for each message object. The pending transmission

communications are immediately aborted but the on-going communication will

be terminated normally, setting the appropriate status flags, TXOK or RXOK.

6OVRQ

Overload frame request (initiator)

Auto-resetable bit.

Set to send an overload frame after the next received message.

Cleared by the hardware at the beginning of transmission of the overload

frame.

5 TTC Network in Ti mer Trig ger Communication

set to select node in TTC.

clear to disable TTC features.

4 SYNCTTC

Synchronization of TTC

When this bit is set the TTC timer is caught on the last bit of the End Of

Frame.

When this bit is clear the TTC timer is caught on the Start Of Frame.

This bit is only used in the TTC mode.

3 AUTOBAUD AUTOBAUD

Set to activate listening mode.

Clear to disable listening mode

2TEST

Test mode. The test mode is intended for factory testing and not for customer

use.

1ENA/STB

Enable/Standby CAN Controller

When this bit is set, it enables the CAN controller and its input clock.

When this bit is clear, the on-going communication is terminated normally and

the CAN controller state of the machine is frozen (the ENCH bit of each

message object does not change).

In the standby mode, the t ransmitter constantly provides a recessive level; the

receiver is not activated and the input clock is stopped in the CAN controller.

During the disable mode, the registers and the mailbox remain accessible.

Note that two clock periods are needed to start the CAN controller state of the

machine.

0GRES

General Reset (software reset)

Auto-resetable bit. This reset command is ‘ORed’ with the hardware reset in

order to reset the controller. After a reset, the controller is disabled.

107

AT89C51CC03

4182O–CAN–09/08

Table 49. CANGSTA Register

CANGSTA (S:AAh Read Only)

CAN General Status Register

Reset Value = x0x0 0000b

76543210

- OVFG - TBSY RBSY ENFG BOFF ERRP

Bit

Number Bit Mnemo n ic Description

Reserved

The values read from this bit is indeterminate. Do not set this bit.

6OVFG

Overload Frame Flag

This status bit is set by the hardware as long as the produced overload frame

is sent.

This flag does not generate an interrupt

Reserved

The values read from this bit is indeterminate. Do not set this bit.

4TBSY

Transm itter Busy

This status bit is set by the hardware as long as the CAN transmitter

generates a frame (remote, data, overload or error frame) or an ack field. This

bit is also active during an InterFrame Spacing if a frame must be sent.

This flag does not generate an interrupt.

3 RBSY

Receiver Busy

This status bit is set by the hardware as long as the CAN receiver acquires or

monitors a frame.

This flag does not generate an interrupt.

2ENFG

Enable On-chip CAN Controller Flag

Because an enable/disable command is not effective immediately, this status

bit gives the true state of a chosen mode.

This flag does not generate an interrupt.

1BOFF

Bus Off Mode

see Figure 53

0 ERRP Error Passive Mode

see Figure 53

108

AT89C51CC03

4182O–CAN–09/08

Table 50. CANGIT Register

CANGIT (S:9Bh)

CAN General Interrupt

Note: 1. This field is Read Only.

Reset Value = 0x00 0000b

76543210

CANIT - OVRTIM OVRBUF SERG CERG FERG AERG

Bit

Number Bit Mnemo n ic Description

7CANIT

General Interrupt Flag(1)

This status bit is the image of all the CAN controller interrupts sent to the

interrupt controller.

It can be used in the case of the polling method.

Reserved

The values read from this bit is indeterminate. Do not set this bit.

5OVRTIM

Overrun CAN Timer

This status bit is set when the CAN timer switches 0xFF FF to 0x0000.

If the bit ETIM in the IE1 register is set, an interrupt is generated.

Clear this bit in order to reset the interrupt.

4OVRBUF

Overrun BUFFER

0 - no interrupt.

1 - IT turned on

This bit is set when the buffer is full.

Bit resetable by user.

see Figure 50.

3SERG

Stuff Error General

Detection of more than five consecutive bits with the same polarity.

This flag can generate an interrupt. resetable by user.

2CERG

CRC Error General

The receiver performs a CRC check on each destuffed received message

from the start of frame up to the data field.

If this checking does not match with the destuffed CRC field, a CRC error is

set.

This flag can generate an interrupt. resetable by user.

1FERG

Form Error General

The form error results from one or more violations of the fixed form in the

following bit fields:

CRC delimiter

acknowledgment delimiter

end_of_frame

This flag can generate an interrupt. resetable by user.

0AERG

Acknowledgment Error General

No detection of the dominant bit in the acknowledge slot.

This flag can generate an interrupt. resetable by user.

109

AT89C51CC03

4182O–CAN–09/08

Table 51. CANTEC Register

CANTEC (S:9Ch Read Only)

CAN Transmit Error Counter

Reset Value = 00h

Table 52. CANREC Register

CANREC (S:9Dh Read Only)

CAN Reception Error Counter

Reset Value = 00h

76543210

TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0

Bit

Number Bit Mnemo n ic Description

7-0 TEC7:0 Transmit Error Counter

see Figure 53

76543210

REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0

Bit

Number Bit Mnemo n ic Description

7-0 REC7:0 Reception Error Counter

see Figure 53

110

AT89C51CC03

4182O–CAN–09/08

Table 53. CANGIE Register

CANGIE (S:C1h)

CAN General Interrupt Enable

Note: See Figure 50

Reset Value = xx00 000xb

76543210

- - ENRX ENTX ENERCH ENBUF ENERG -

Bit

Number Bit Mnemo n ic Description

7-6 - Reserved

The values read from these bits are indeterminate. Do not set these bits.

5 ENRX Enable Receive Interrupt

0 - Disable

1 - Enable

4ENTX

Enable Tr ansmit Interrupt

0 - Disable

1 - Enable

3 ENERCH Enable Message Object Error Interrupt

0 - Disable

1 - Enable

2 ENBUF Enable BUF Interrupt

0 - Disable

1 - Enable

1 ENERG Enable General Error Interrupt

0 - Disable

1 - Enable

Reserved

The value read from this bit is indeterminate. Do not set this bit.

111

AT89C51CC03

4182O–CAN–09/08

Table 54. CANEN1 Register

CANEN1 (S:CEh Read Only)

CAN Enable Message Object Registers 1

Reset Value = x000 0000b

Table 55. CANEN2 Register

CANEN2 (S:CFh Read Only)

CAN Enable Message Object Registers 2

Reset Value = 0000 0000b

76543210

- ENCH14 ENCH13 ENCH12 ENCH11 ENCH10 ENCH9 ENCH8

Bit

Number Bit Mnemo n ic Description

Reserved

The values read from this bit is indeterminate. Do not set this bit.

6-0 ENCH14:8

Enable Message Object

These bits provide the availability of the MOb.

It is set to one when the MOb is enabled.

Once TXOK or RXOK is set to one (TXOK for automatic reply), the

corresponding ENMOB is reset. ENMO B is also set to zero configuring the

MOb in disabled mode, applying abortion or standby mode.

0 - message object disabled: MOb available for a new transmission or

reception.

1 - message object enabled: MOb in use.

This bit is resetable by re-writing the CANCONCH of the corresponding

message object.

76543210

ENCH7 ENCH6 ENCH5 ENCH4 ENCH3 ENCH2 ENCH1 ENCH0

Bit

Number Bit Mnemo n ic Description

7-0 ENCH7:0

Enable Message Object

These bits provide the availability of the MOb.

It is set to one when the MOb is enabled.

Once TXOK or RXOK is set to one (TXOK for automatic reply), the

corresponding ENMOB is reset. ENMO B is also set to zero configuring the

MOb in disabled mode, applying abortion or standby mode.

0 - message object disabled: MOb available for a new transmission or

reception.

1 - message object enabled: MOb in use.

This bit is resetable by re-writing the CANCONCH of the corresponding

message object.

112

AT89C51CC03

4182O–CAN–09/08

Table 56. CANSIT1 Register

CANSIT1 (S:BAh Read Only)

CAN Status Interrupt Message Object Registers 1

Reset Value = x000 0000b

Table 57. CANSIT2 Register

CANSIT2 (S:BBh Read Only)

CAN Status Interrupt Message Object Registers 2

Reset Value = 0000 0000b

76543210

- SIT14 SIT13 SIT12 SIT11 SIT10 SIT9 SIT8

Bit

Number Bit Mnemo n ic Description

Reserved

The values read from this bit is indeterminate. Do not set this bit.

6-0 SIT14:8

Statu s of Interrupt by Messa ge Object

0 - no interrupt.

1 - IT turned on. Reset when interrupt condition is cleared by user.

SIT14:8 = 0b 0000 1001 -> IT’s on message objects 11 and 8.

see Figure 50.

76543210

SIT7 SIT6 SIT5 SIT4 SIT3 SIT2 SIT1 SIT0

Bit

Number Bit Mnemo n ic Description

7-0 SIT7:0

Statu s of Interrupt by Message Object

0 - no interrupt.

1 - IT turned on. Reset when interrupt condition is cleared by user.

SIT7:0 = 0b 0000 1001 -> IT’s on message objects 3 and 0

see Figure 50.

113

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4182O–CAN–09/08

Table 58. CANIE1 Register

CANIE1 (S:C2h)

CAN Enable Interrupt Message Object Registers 1

Reset Value = x000 0000b

Table 59. CANIE2 Register

CANIE2 (S:C3h)

CAN Enable Interrupt Message Object Registers 2

Reset Value = 0000 0000b

76543210

- IECH14 IECH13 IECH12 IECH11 IECH10 IECH9 IECH8

Bit

Number Bit Mnemo n ic Description

Reserved

The values read from this bit is indeterminate. Do not set this bit.

6-0 IECH14:8

Enable interrupt by Message Object

0 - disable IT.

1 - enable IT.

IECH14:8 = 0b 0000 1100 -> Enable IT’s of message objects 11 and 10.

see Figure 50.

76543210

IECH 7 IECH 6 IECH 5 IECH 4 IECH 3 IECH 2 IECH 1 IECH 0

Bit

Number Bit Mnemo n ic Description

7-0 IECH7:0

Enable interrupt by Message Object

0 - disable IT.

1 - enable IT.

IECH7:0 = 0b 0000 1100 -> Enable IT’s of message objects 3 and 2.

114

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Table 60. CANBT1 Register

CANBT1 (S:B4h)

CAN Bit Timing Registers 1

Note: The CAN con troller bit tim ing reg isters must be acce ssed only i f the C AN c ontrol ler is dis-

abled with the ENA bit of the CANGCON register set to 0.

See Figure 52.

No default value after reset.

76543210

- BRP 5 BRP 4 BRP 3 BRP 2 BRP 1 BRP 0 -

Bit

Number Bit Mnemo n ic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

6-1 BRP5:0

Baud rate prescaler

The period of the CAN controller system clock Tscl is programmable and

determines the individual bit timing.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Tscl = BRP[5..0] + 1

Fcan

115

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4182O–CAN–09/08

Table 61. CANBT2 Register

CANBT2 (S:B5h)

CAN Bit Timing Registers 2

Note: The CAN con troller bit tim ing reg isters must be acce ssed only i f the C AN c ontrol ler is dis-

abled with the ENA bit of the CANGCON register set to 0.

See Figure 52.

No default value after reset.

76543210

- SJW 1 SJW 0 - PRS 2 PRS 1 PRS 0 -

Bit

Number Bit Mnemo n ic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

6-5 SJW1:0

Re-synchronization Jump Wid th

To compensate for phase shifts between clock oscillators of different bus

controllers, the controller must re-synchronize on any relevant signal edge of

the current transmission.

The synchronization jump width defines t he maximum number of clock cycles.

A bit period may be shortened or lengthened by a re-synchronization.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

3-1 PRS2:0

Prog r amming Time Segment

This part of the bit time is used to compensate for the physical delay times

within the network. It is twice the sum of the signal propagation time on the

bus line, the input comparator delay and the output driver delay.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Tsjw = Tscl x (SJW [1..0] +1)

Tprs = Tscl x (PRS[2..0] + 1)

116

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4182O–CAN–09/08

Table 62. CANBT3 Register

CANBT3 (S:B6h)

CAN Bit Timing Registers 3

Note: The CAN con troller bit tim ing reg isters must be acce ssed only i f the C AN c ontrol ler is dis-

abled with the ENA bit of the CANGCON register set to 0.

See Figure 52.

No default value after reset.

76543210

- PHS2 2 PHS2 1 PHS2 0 PHS1 2 PHS1 1 P HS1 0 SMP

Bit

Number Bit Mnemo n ic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

6-4 PHS2 2:0

Phase Segment 2

This phase is used to compensate for phase edge errors. This segment can

be shortened by the re-synchronization jump width.

Phase segment 2 is the maximum of Phase segment 1 and the Information

Processing Time (= 2TQ).

3-1 PHS1 2:0

Phase Segment 1

This phase is used to compensate for phase edge errors. This segment can

be lengthened by the re-synchronization jump width.

0SMP

Sample Type

0 - once, at the sample point.

1 - three times, the threefold sampling of the bus is the sample point and twice

over a distance of a 1/2 period of the Tscl. The result corresponds to the

majority decision of the three values.

Tphs2 = Tscl x (PHS2[2..0] + 1)

Tphs1 = Tscl x (PHS1[2..0] + 1)

117

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Table 63. CANPAGE Register

CANPAGE (S:B1h)

CAN Message Object Page Register

Reset Value = 0000 0000b

Table 64. CANCONCH Register

CANCONCH (S:B3h)

CAN Message Object Control and DLC Register

No default value after reset

76543210

CHNB 3 CHNB 2 CHNB 1 CHNB 0 AINC INDX2 INDX1 INDX0

Bit

Number Bit Mnemo n ic Description

7-4 CHNB3:0 Selection of Message Object Number

The available numbers are: 0 to 14 (see Figure 48).

3AINC

Auto Increment of the Index (active low)

0 - auto-increment of the index (default value).

1 - non-auto-increment of the index.

2-0 INDX2:0 Index

Byte location of the data field for the defined message object (see Figure 48).

76543210

CONCH 1 CONCH 0 RPLV IDE DLC 3 DLC 2 DLC 1 DLC 0

Bit

Number Bit Mnemo n ic Description

7-6 CONCH1:0

Configuration of Message Object

CONCH1 CONCH0

0 0: disable

0 1: Launch transmissi on

1 0: Enable Reception

1 1: Enable Reception Buffer

Note: The user must re-write the configuration to enable the corresponding bit

in the CANEN1:2 registers.

5RPLV

Reply Valid

Used in the automatic reply mode after receiving a remote frame

0 - reply not ready.

1 - reply ready and valid.

4IDE

Identifier Extension

0 - CAN standard rev 2.0 A (ident = 11 bits).

1 - CAN standard rev 2.0 B (ident = 29 bits).

3-0 DLC3:0

Data Length Code

Number of Bytes in the data field of the message.

The range of DLC is from 0 up to 8.

This value is updated when a frame is received (data or remote frame).

If the expected DLC diff ers from the incoming DLC, a warning appears in the

CANSTCH register.

118

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Table 65. CANSTCH Register

CANSTCH (S:B2h)

CAN Message Object Status Register

Note: See Figure 50.

No default value after reset.

76543210

DLCW TXOK RXOK BERR SERR CERR FERR AERR

Bit

Number Bit Mnemo n ic Description

7DLCW

Data Length Code Warning

The incoming message does not have the DLC expected. Whatever the frame

type, the DLC field of the CANCONCH register is updated by the received

DLC.

6TXOK

Transmit OK

The communication enabled by transmission is completed.

When the controller is ready to send a frame, if two or more message objects

are enabled as producers, the lower index message object (0 to 13) is

supplied first.

This flag can generate an interrupt.

5RXOK

Receive OK

The communication enabled by reception is completed.

In the case of two or more message object reception hits, the lower index

message object (0 to 13) is updated first.

This flag can generate an interrupt.

4BERR

Bit Error (Only in Transmission)

The bit value monitored is different from the bit value sent.

Exceptions:

the monitored recessive bit sent as a dominant bit during the arbitration field

and the acknowledge slot detecting a dominant bit during the sending of an

error frame.

This flag can generate an interrupt.

3SERR

Stuff Error

Detection of more than five consecutive bits with the same polarity.

This flag can generate an interrupt.

2CERR

CRC Error

The receiver performs a CRC check on each destuffed received message

from the start of frame up to the data field.

If this checking does not match with the destuffed CRC field, a CRC error is

set.

This flag can generate an interrupt.

1FERR

Form Error

The form error results from one or more violations of the fixed form in the

following bit fields:

CRC delimiter

acknowledgment delimiter

end_of_frame

This flag can generate an interrupt.

0AERR

Acknowledgment Error

No detection of the dominant bit in the acknowledge slot.

This flag can generate an interrupt.

119

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Table 66. CANIDT1 Register for V2.0 part A

CANIDT1 for V2.0 part A (S:BCh)

CAN Identifier Tag Registers 1

No default value after reset.

Table 67. CANIDT2 Register for V2.0 part A

CANIDT2 for V2.0 part A (S:BDh)

CAN Identifier Tag Registers 2

No default value after reset.

Table 68. CANIDT3 Register for V2.0 part A

CANIDT3 for V2.0 part A (S:BEh)

CAN Identifier Tag Registers 3

No default value after reset.

76543210

IDT 10 IDT 9 IDT 8 IDT 7 IDT 6 IDT 5 IDT 4 IDT 3

Bit

Number Bit Mnemo n ic Description

7-0 IDT10:3 IDentifier tag value

See Figure 54.

76543210

IDT 2IDT 1IDT 0-----

Bit

Number Bit Mnemo n ic Description

7-5 IDT2:0 IDentifier tag value

See Figure 54.

4-0 - Reserved

The values read from these bits are indeterminate. Do not set these bits.

76543210

--------

Bit

Number Bit Mnemo n ic Description

7-0 - Reserved

The values read from these bits are indeterminate. Do not set these bits.

120

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Table 69. CANIDT4 Register for V2.0 part A

CANIDT4 for V2.0 part A (S:BFh)

CAN Identifier Tag Registers 4

No default value after reset.

Table 70. CANIDT4 Register for V2.0 part A

CANIDT1 for V2.0 part B (S:BCh)

CAN Identifier Tag Registers 1

No default value after reset.

Table 71. CANIDT2 Register for V2.0 part B

CANIDT2 for V2.0 part B (S:BDh)

CAN Identifier Tag Registers 2

No default value after reset.

76543210

-----RTRTAG-RB0TAG

Bit

Number Bit Mnemo n ic Description

7-3 - Reserved

The values read from these bits are indeterminate. Do not set these bits.

2RTRTAGRemote Transmission Request Tag Val ue.

Reserved

The values read from this bit are indeterminate. Do not set these bit.

0RB0TAGReserved Bit 0 Tag V alue.

76543210

IDT 28 IDT 27 IDT 26 IDT 25 IDT 24 IDT 23 IDT 22 IDT 21

Bit

Number Bit Mnemo n ic Description

7-0 IDT28:21 IDentifier Tag Value

See Figure 54.

76543210

IDT 20 IDT 19 IDT 18 IDT 17 IDT 16 IDT 15 IDT 14 IDT 13

Bit

Number Bit Mnemo n ic Description

7-0 IDT20:13 IDentifier Tag Value

See Figure 54.

121

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Table 72. CANIDT3 Register for V2.0 part B

CANIDT3 for V2.0 part B (S:BEh)

CAN Identifier Tag Registers 3

No default value after reset.

Table 73. CANIDT4 Register for V2.0 part B

CANIDT4 for V2.0 part B (S:BFh)

CAN Identifier Tag Registers 4

No default value after reset.

Table 74. CANIDM1 Register for V2.0 part A

CANIDM1 for V2.0 part A (S:C4h)

CAN Identifier Mask Registers 1

No default value after reset.

76543210

IDT 12 IDT 11 IDT 10 IDT 9 IDT 8 IDT 7 I DT 6 IDT 5

Bit

Number Bit Mnemo n ic Description

7-0 IDT12:5 IDentifier Tag Value

See Figure 54.

76543210

IDT 4 IDT 3 IDT 2 IDT 1 IDT 0 RTRTAG RB1TAG RB0TAG

Bit

Number Bit Mnemo n ic Description

7-3 IDT4:0 IDentifier Tag Value

See Figure 54.

2RTRTAGRemote Transmission Request Tag Val ue

1RB1TAGReserved bit 1 Tag Value

0RB0TAGReserved bit 0 Tag Value

76543210

IDMSK 10 IDMSK 9 IDMSK 8 IDMSK 7 IDMSK 6 I DMSK 5 IDMSK 4 IDMSK 3

Bit

Number Bit Mnemo n ic Description

7-0 IDTMSK10:3

IDentifier mask value

0 - comparison true forced.

1 - bit comparison enabled.

See Figure 54.

122

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Table 75. CANIDM2 Register for V2.0 part A

CANIDM2 for V2.0 part A (S:C5h)

CAN Identifier Mask Registers 2

No default value after reset.

Table 76. CANIDM3 Register for V2.0 part A

CANIDM3 for V2.0 part A (S:C6h)

CAN Identifier Mask Registers 3

No default value after reset.

76543210

IDMSK 2IDMSK 1IDMSK 0-----

Bit

Number Bit Mnemo n ic Description

7-5 IDTMSK2:0

IDentifier Mask Va lue

0 - comparison true forced.

1 - bit comparison enabled.

See Figure 54.

4-0 - Reserved

The values read from these bits are indeterminate. Do not set these bits.

76543210

--------

Bit

Number Bit Mnemo n ic Description

7-0 - Reserved

The values read from these bits are indeterminate.

123

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4182O–CAN–09/08

Table 77. CANIDM4 Register for V2.0 part A

CANIDM4 for V2.0 part A (S:C7h)

CAN Identifier Mask Registers 4

Note: The ID Mask is only used for reception.

No default value after reset.

Table 78. CANIDM1 Register for V2.0 part B

CANIDM1 for V2.0 part B (S:C4h)

CAN Identifier Mask Registers 1

Note: The ID Mask is only used for reception.

No default value after reset.

76543210

-----RTRMSK-IDEMSK

Bit

Number Bit Mnemo n ic Description

7-3 - Reserved

The values read from these bits are indeterminate. Do not set these bits.

2RTRMSK

Remote Transmission Request Mask Value

0 - comparison true forced.

1 - bit comparison enabled.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

0IDEMSK

IDentifier Extension Mask Value

0 - comparison true forced.

1 - bit comparison enabled.

76543210

IDMSK 28 IDMSK 27 IDMSK 26 IDMSK 25 IDMSK 24 IDMSK 23 IDMSK 22 IDMSK 21

Bit

Number Bit Mnemo n ic Description

7-0 IDMSK28:21

IDentifier Mask Va lue

0 - comparison true forced.

1 - bit comparison enabled.

See Figure 54.

124

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4182O–CAN–09/08

Table 79. CANIDM2 Register for V2.0 part B

CANIDM2 for V2.0 part B (S:C5h)

CAN Identifier Mask Registers 2

Note: The ID Mask is only used for reception.

No default value after reset.

Table 80. CANIDM3 Register for V2.0 part B

CANIDM3 for V2.0 part B (S:C6h)

CAN Identifier Mask Registers 3

Note: The ID Mask is only used for reception.

No default value after reset.

76543210

IDMSK 20 IDMSK 19 IDMSK 18 IDMSK 17 IDMSK 16 IDMSK 15 IDMSK 14 IDMSK 13

Bit

Number Bit Mnemo n ic Description

7-0 IDMSK20:13

IDentifier Mask Va lue

0 - comparison true forced.

1 - bit comparison enabled.

See Figure 54.

76543210

IDMSK 12 IDMSK 1 1 IDMSK 10 IDMSK 9 IDMSK 8 IDMSK 7 IDMSK 6 IDMSK 5

Bit

Number Bit Mnemo n ic Description

7-0 IDMSK12:5

IDentifier Mask Va lue

0 - comparison true forced.

1 - bit comparison enabled.

See Figure 54.

125

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4182O–CAN–09/08

Table 81. CANIDM4 Register for V2.0 part B

CANIDM4 for V2.0 part B (S:C7h)

CAN Identifier Mask Registers 4

Note: The ID Mask is only used for reception.

No default value after reset.

Table 82. CANMSG Register

CANMSG (S:A3h)

CAN Message Data Register

No default value after reset.

76543210

IDMSK 4 IDMSK 3 IDMSK 2 IDMSK 1 IDMSK 0 RTRMSK - IDEMSK

Bit

Number Bit Mnemo n ic Description

7-3 IDMSK4:0

IDentifier Mask Va lue

0 - comparison true forced.

1 - bit comparison enabled.

See Figure 54.

2RTRMSK

Remote Transmission Request Mask Value

0 - comparison true forced.

1 - bit comparison enabled.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

0IDEMSK

IDentifier Extension Mask Value

0 - comparison true forced.

1 - bit comparison enabled.

76543210

MSG 7MSG 6MSG 5MSG 4MSG 3MSG 2MSG 1MSG 0

Bit

Number Bit Mnemo n ic Description

7-0 MSG7:0

Message Data

This register contains the mailbox data byte pointed at the page message

object register.

After writing in the page message object register, this byte is equal to the

specified message location (in the mailbox) of the pre-defined identifier +

index. If auto-incrementation is used, at the end of the data register writing or

reading cycle, the mailbox pointer is auto-incremented. The range of the

counting is 8 with no end loop (0, 1,..., 7, 0,...)

126

AT89C51CC03

4182O–CAN–09/08

Table 83. CANTCON Register

CANTCON (S:A1h)

CAN Timer ClockControl

Reset Value = 00h

Table 84. CANTIMH Register

CANTIMH (S:ADh)

CAN Timer High

Reset Value = 0000 0000b

Table 85. CANTIML Register

CANTIML (S:ACh)

CAN Timer Low

Reset Value = 0000 0000b

76543210

TPRES C 7 TPRES C 6 TPRE SC 5 TPRESC 4 TPRE SC 3 TPR ESC 2 TP R ESC 1 TPRESC 0

Bit

Number Bit Mnemo n ic Description

7-0 TPRESC7:0

Timer Prescaler of CAN Timer

This register is a prescaler for the main timer upper counter

range = 0 to 255.

See Figure 55.

76543210

CANGTIM

15 CANGTIM

14 CANGTIM

13 CANGTIM

12 CANGTIM

11 CANGTIM

10 CANGTIM 9 CANGTIM 8

Bit

Number Bit Mnemo n ic Description

7-0 CANGTIM15:

8High byte of Message Timer

See Figure 55.

76543210

CANGTIM 7 CANGTIM 6 CANGTIM 5 CANGTIM 4 CANGTIM 3 CANGTIM 2 CANGTIM 1 CANGTIM 0

Bit

Number Bit Mnemo n ic Description

7-0 CANGTIM7:0 Low byte of Message Timer

See Figure 55.

127

AT89C51CC03

4182O–CAN–09/08

Table 86. CANSTMPH Register

CANSTMPH (S:AFh Read Only)

CAN Stamp Timer High

No default value after reset

Table 87. CANSTMPL Register

CANSTMPL (S:AEh Read Only)

CAN Stamp Timer Low

No default value after reset

Table 88. CANTTCH Register

CANTTCH (S:A5h Read Only)

CAN TTC Timer High

Reset Value = 0000 0000b

76543210

TIMSTMP

15 TIMSTMP

14 TIMSTMP

13 TIMSTMP

12 TIMSTMP

11 TIMSTMP

10 TIMSTMP 9 TI MSTMP 8

Bit

Number Bit Mnemo n ic Description

7-0 TIMSTMP15:

8High byte of T ime Stamp

See Figure 55.

76543210

TIMSTMP 7 TIMSTMP 6 TIMSTMP 5 TIMSTMP 4 TIMSTMP 3 TIMSTMP 2 TIMSTMP 1 TIMSTMP 0

Bit

Number Bit Mnemo n ic Description

7-0 TIMSTMP7:0 Low byte of Time Stamp

See Figure 55.

76543210

TIMTTC 15 TIMTTC 14 TIMTTC 13 TIMTTC 12 TIMTTC 11 TIMTTC 10 TIMTTC 9 TIMTTC 8

Bit

Number Bit Mnemo n ic Description

7-0 TIMTTC15:8 High byt e of TT C T imer

See Figure 55.

128

AT89C51CC03

4182O–CAN–09/08

Table 89. CANTTCL Register

CANTTCL (S:A4h Read Only)

CAN TTC Timer Low

Reset Value = 0000 0000b

76543210

TIMTTC 7 TIMTTC 6 TIMTTC 5 TIMTTC 4 TIMTTC 3 TIMTTC 2 TIMTTC 1 TIMTTC 0

Bit

Number Bit Mnemo n ic Description

7-0 TIMTTC7:0 Low byte of TTC Timer

See Figure 55.

129

AT89C51CC03

4182O–CAN–09/08

Serial Port Interface

(SPI) The Serial Peripheral Interface Module (SPI) allows full-duplex , synchronous, serial

communication between the MCU and peripheral devices, including other MCUs.

Features Features of the SPI Module include the following:

• Full-duplex, three-wire synchronous transfers

• Master or Slave operation

• Six programmable Master clock rates in master mode

• Serial clock with programmable polarity and phase

• Master Mode fault error flag with MCU interrupt capability

Signal Description Figure 57 shows a typical SPI bus configuration using one Master controller and many

Slave peripherals. The bus is made of three wires connecting all the devices.

Figure 57. SPI Master/Slaves Interconnection

The Master device selects the individual Slave devices by using four pins of a parallel

port to control the four SS pins of the Slave devices.

Master Output Slave Input

(MOSI) This 1-bit signal is directly connected between the Master Device and a Slave Device.

The MOSI line is used to transfer data in series from the Master to the Slave. Therefore,

it is an output signal from the Master, and an input signal to a Slave. A Byte (8-bit word)

is transmitted most significant bit (MSB) first, least significant bit (LSB) last.

Master Input Slave Output

(MISO) This 1-bit signal is directly connected between the Slave Device and a Master Device.

The MISO line is used to transfer data in series from the Slave to the Master. Therefore,

it is an output signal from the Slave, and an input signal to the Master. A Byte (8-bit

word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last.

SPI Serial Clock (SCK) This signal is used to synchronize the data transmission both in and out of the devices

through their MOS I and M ISO lines . It is driven by the M aster for eight clock cycles

which allows to exchange one Byte on the serial lines.

Slave Sel ect (SS )Each Slave peripheral is s elected by one Slave Select pin (SS). This signal must stay

low for any messa ge for a Sla ve. It is obvi ous tha t only on e Master (S S high level) can

drive the network. The Master may select each Slave device by software through port

pins (Figu re 58). To pr event bus conflicts on the MISO li ne, only one slave sh ould be

selected at a time by the Master for a transmission.

Slave 1

MISO

MOSI

SCK

MISO

MOSI

SCK

PORT

Slave 3

MISO

MOSI

SCK

Slave 4

MISO

MOSI

SCK

Slave 2

MISO

MOSI

SCK

VDD

Master

130

AT89C51CC03

4182O–CAN–09/08

In a Master config urati on, the SS line c an be used i n conju nctio n with the M ODF flag i n

the SPI Status register (SPSCR) to prevent multiple masters from driving MOSI and

SCK (see Error conditions).

A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state.

The SS pin could be used as a general-purpose if the following conditions are met:

• The device is configured as a Master and the SSDIS control bit in SPCON is set.

This kind of configuration can be found when only one Master is driving the network

and th ere i s no way that the SS pin could be pulled low. Therefore, the MODF flag in

the SPSCR will never be set(1).

• The Device is configured as a Slave with CPHA and SSDIS control bits set(2). This

kind of configuration can happen when the system includes one Master and one

Slave only. Therefore, the device should always be selected and there is no reason

that the Master uses the SS pin to select the communicating Slave device.

Note: 1. Clearing SSDIS control bit does not clear MODF.

2. S p ecial care should be taken not to set SSDIS co ntrol bit when CP HA =’0’ bec ause in

this mode, the SS is used to start the transmission.

Baud Rate In Master mode, the baud rate can be selected from a baud rate generator which is con-

trolled by three bit s in the SPCON re gis te r: SPR2, SPR1 and SPR0 .The Ma ste r cl ock is

selected from one of seven clock rates resulting from the division of the internal clock by

4, 8, 16, 32, 64 or 128.

Table 90 gives the different clock rates selected by SPR2:SPR1:SPR0.

In Slave mode, the maximum baud rate allowed on the SCK input is limited to Fsys/4

Table 90. SPI Master Baud Rate Selection

SPR2 SPR1 SPR0 Clock Rate Baud Rate Divisor (BD)

0 0 0 Don’t Use No BRG

001 F

CLK PERIPH /4 4

010 F

CLK PERIPH/8 8

011 F

CLK PERIPH /16 16

100 F

CLK PERIPH /32 32

101 F

CLK PERIPH /64 64

110 F

CLK PERIPH /128 128

1 1 1 Don’t Use No BRG

131

AT89C51CC03

4182O–CAN–09/08

Functional Description Figure 58 shows a detailed structure of the SPI Module.

Figure 58. SPI Module Block Diagram

Operating Modes The Serial Peripheral Interface can be configured in one of the two modes: Master mode

or Slave mode. The configuration and initialization of the SPI Module is made through

two registe rs:

• The Serial Peripheral Control register (SPCON)

• The Serial Peripheral Status and Control Register (SPSCR)

Once the SPI is configured, the data exchange is made using:

• The Serial Peripheral DATa register (SPDAT)

During an SP I trans mi ssi on, da ta i s s imultaneous ly trans mi tted (shi fted out s eri all y) an d

receiv ed (shifted in serial ly). A s erial cloc k line ( SCK) synchr onizes sh ifting and sam-

pling on the two serial data lines (MOSI and MISO). A Slave Select line (SS) allows

indivi dual selecti on of a Slave SPI devic e; Slave devices that are not selec ted do not

interfere with SPI bus activities.

Shift Registe r01

234567

Internal Bus

Control

Logic MISO

MOSI

SCK

Clock

Logic

SPI In t er r u p t

8-bit bus

1-bit signal

FCLK

Receive Data Register

SPDAT

SPI

Control

Transmit Data Register

-MODFSPIF OVR SPTE UARTMSPTEIEMODFIE

SPSCR

SPEN MSTRSPR2 SSDIS CPOL CPHA SPR1 SPR0

SPCON

Request

PERIPH

132

AT89C51CC03

4182O–CAN–09/08

When the Master device transmits data to the Slave device via the MOSI line, the Slave

device responds by sendi ng data to the Master device via the MISO line. This implies

full-duplex transmission with both data out and data in synchronized with the same clock

(Figure 59).

Figure 59. Full-Duplex Master-Slave Interconnection

Maste r Mode The SPI operates in Master mode when the Master bit, MSTR (1), in the SPCON register

is set. Only one Master SPI device can initiate transmissions. Software begins the trans-

mission from a Ma ster SPI Module by wr iting to the Serial Periphera l Data Register

(SPDAT) . If the shi ft register is empty, th e Byte is immediately transfe rred to the shift

SCK. Simultaneously, another Byte shifts in from the Slave on the Master’s MISO pin.

The transmission ends when the Serial Peripheral transfer data flag, SPIF, in SPSCR

becomes set. At the same time that SPIF becomes set, the received Byte from the Slave

is transferr ed to the receive data register in SPDAT. S oftware clears SPIF by reading

the Serial Peripheral Status register (SPSCR) with the SPIF bit set, and then reading the

SPDAT.

Slave Mode The SPI operates in Slave mode when the Master bit, MSTR (2), in the SPCON register is

cleared. Before a data transmission occurs, the Slave Select pin, SS, of the Slave

device mu st be set to’0’. SS must remain low until the transmission is complete.

In a Slave SPI Module, data enters the shift register under the control of the SCK from

the Master SPI Module. After a Byte enters the shift register, it is immediately trans-

ferred to the rec eive data register in SP DAT, and the SPIF bit is set. To prevent an

overf low condi tion, Sl ave softwa re must th en read the SP DAT befor e another Byte

enters the shift register (3). A Slave SPI must complete the write to the SPDAT (shift reg-

ister) at least one bus cycle before the Master SPI starts a transmission. If the write to

the data r egister is late, the SPI tr ansmits the data al ready in the s hift registe r from the

previous transmission.

Transmission Formats Software can s elect any of four combinations of serial clock ( SCK) phase and polarity

using two bits in the SPCON: the Clock Polarity (CPOL (4)) and the Clock Phase

(CPHA4). CPOL defi nes the default SCK li ne level in idle state. It has no significant

effect on the tr ansmiss ion format. CPHA defines the edges on which the input da ta are

sampled and the edges on whi ch the outp ut data a re s hifted (Figure 60 a nd Figur e 61).

The clock phase and polarity should be identical for the Master SPI device and the com-

municating Slave device.

8-bit Shift register

SPI

Clock Generator

Master MCU

8-bit Shift register

MISOMISO

MOSI MOSI

SCK SCK

VSS

VDD SSSS Slave MCU

1. The SPI Module should be configured as a Master before it is enabled (SPEN set). Also,

the Master SPI should be configured before the Slave SPI.

2. The SPI Module should be configured as a Slave before it is enabled (SPEN set).

3. The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock

speed.

4. Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN =’0’).

133

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Figure 60. Data T ransmission Format (CPHA = 0)

Figure 61. Data T ransmission Format (CPHA = 1)

Figure 62. CPHA/SS Timing

As show n in Figure 60 , the first SCK edg e is the MSB capt ure strobe. T herefore, the

Slave must begin driving its data before the first SCK edge, and a falling edge on the SS

pin is used to start the transmission. The SS pin must be toggled high and then low

between each Byte transmitted (Figure 62).

Figure 61 shows an SPI transmission i n which CPHA is ’1’. In this case, the Master

begins drivi ng its MOSI pin on the fir st SCK edge. Theref ore, the Slave uses the firs t

SCK edge as a start trans mi ssio n signal . The S S pin can remain low between transmis-

sions ( Figur e 62). This format may be preferr ed in syste ms ha ving only one Mast er and

only one Slave driving the MISO data line.

Queuing transmission For an SPI configured in master or slave mode, a queued data byte must be transmit-

ted/received immediately after the previous transmission has completed.

MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB

bit6 bit5 bit4 bit3 bit2 bit1MSB LSB

13245678

Capture Point

SS (to Slave)

MISO (from Slave)

MOSI (from Master)

SCK (CPOL = 1)

SCK (CPOL = 0)

SPEN (Internal)

SCK Cycle Number

MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB

bit6 bit5 bit4 bit3 bit2 bit1

MSB LSB

132 45678

Capture Point

SS (to Slave)

MISO (from Slave)

MOSI (from Ma st er )

SCK (CPOL = 1)

SCK (CPOL = 0)

SPEN (Internal)

SCK Cycle Number

Byte 1 Byte 2 Byte 3

MISO/MOSI

Maste r S S

Slave SS

(CPHA = 1)

Slave SS

(CPHA = 0)

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When a transmission is in progress a new data can be queued and sent as soon as

transmission has been completed. So it is possible to transmit bytes without latency,

useful in some applications.

The SPTE bit in SPSCR is set as long as the transmission buffer is free. It means that

the user application can write SPDAT with the data to be transmitted until the SPTE

becomes cleared.

Figure 63 sho ws a qu eui ng tr an sm is si on in master mode. On ce the Byte 1 is ready , it is

immediately sent on the bus. Meanwhile an other byte is prepared (and the SPT E is

cleared) , it wi ll be s ent at th e end o f the current transmis sion. T he next data m ust be

ready before the end of the cur rent tra nsmi ss ion.

Figure 63. Queuing Tra nsm is s ion In Master Mode

In slave mode it is almost the same except it is the external master that start the

transmission.

Also, in slave mode, if no new data is ready, the last value received will be the next data

byte transmitted.

MSB B6 B5 B4 B3 B2 B1 LSB

MOSI

SCK

MSB B6 B5 B4 B3 B2 B1 LSB

BYTE 1 under transmission

MSB B6 B5 B4 B3 B2 B1 LSB MSB B6 B5 B4 B3 B2 B1 LSB

MISO

Data Byte 1 Byte 2 Byte 3

SPTE BYTE 2 under transmission

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Error Conditions The following flags in the SPSCR register indicate the SPI error conditions:

Mode Fault Erro r (MODF) Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS)

pin is inconsistent with the actual mode of the device.

• Mode fault detection in Master mode:

MODF is set to warn that there may be a multi-master conflict for system control. In this

case, the SPI system is affected in the following ways:

– An SPI receiver/error CPU interrupt request is generated

– The SPEN bit in SPCON is cleared. This disables the SPI

– The MSTR bit in SPCON is cleared

Clearing the MODF bit is accomplished by a read of SPSCR register with MODF bit set,

followed by a write to the SPCON register. SPEN Control bit may be restored to its orig-

inal set state after the MODF bit has been cleared.

Figure 64. Mode Fault Conditions in Master Mode (Cpha =’1’/Cpol =’0’)

Note: When SS is discarded (SS disabled) it is not possible to detect a MODF error in master

mode because the SPI is internally unselected and the SS pin is a general purpose I/O.

• Mode fault detection in Slave mode

In slave mode, the MODF error is detected when SS goes high during a transmission.

A trans mission begins whe n SS goes low an d ends onc e the inco ming SCK goes back

to its idle level following the shift of the eighteen data bit.

A MODF err or oc c urs i f a sl av e i s se lec te d ( SS i s low) a nd l ate r uns el ec ted (SS is hi gh)

even if no SCK is sent to that slave.

At any time, a ’1’ on the SS pin of a slave SPI puts the MISO pin in a high impedance

state and internal state counter is cleared. Also, the slave SPI ignores all incoming SCK

clocks, even if it was already in the middle of a transmission. A new transmission will be

performed as soon as SS pin returns low.

SCK

(master)

1 2 3SCK cycle # 0 0

(slave)

(from master )

MODF detected

B6MSB

SPI enable

MODF detected

MOSI

MISO

(from master )

(from slave)

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Figure 65. Mode Fault Conditions in Slave Mode

Note: when SS is discarded (SS disabled) it is not possible to detect a MODF error in slave

mode because the SPI is internally selected. Also the SS pin becomes a general pur-

pose I/O.

OverRun Condition This error mean that the speed is not adapted for the running application:

An OverRun condition occurs when a byte has been received whereas the previous one

has not been read by the application yet.

The last by te (which ge nerate the ov errun error) does not over write the unre ad data so

that it can still be read. Therefore, an overrun error always indicates the loss of data.

Interrupts Three SPI status flags can generate a CPU interrupt requests:

Table 91. SPI Interrupts

Serial Per ipheral data transfe r flag, SPIF: This bit is set by hardware when a trans fer

has been c ompleted. SPIF b it generates transm itter CPU interrupt request only wh en

SPTEIE is disabled.

Mode Fault flag, MODF: This bit is set to indicate that the level on the SS is inconsistent

with the mode of the SPI (in both master and slave modes).

Serial Peripheral Transmit Register empty flag, SPTE: This bit is set when the transmit

buffer is empt y (other data c an be loaded is SPDAT). SPTE bit generat es transmitter

CPU interrupt request only when SPTEIE is enabled.

Note: Whi le using SPTE i nterruption for “b urst mode” tran sfers (SPTEIE =’1’), the

user softwa re appl icat ion s houl d tak e care to c lear S PTEIE , dur ing the l ast but on e

data reception (to be able to generate an interrupt on SPIF flag at the end of the last

data reception).

SCK

1 2 3SCK cycle # 0

(slave)

(from master)

MODF detected

B6MSB

MODF detected

MOSI

MISO

(from master)

(from slave)

MSB

B5 B4

Flag Request

SPIF (SPI data transfer) SPI Transmitter Interrupt Request

MODF (Mode Fault) SPI mode-fault Interrupt Request

SPTE (Transmit register empty) SPI transmit register empty Interrupt Request

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Figure 66. SPI Interrupt Requests Generation

Registers T hree regist ers in the SPI modu le provide co ntrol, stat us and data storag e functions .

These registers are describe in the following paragraphs.

Serial Peripheral Control

• Selects one of the Master clock rates

• Configure the SPI Module as Master or Slave

• Selects serial clock polarity and phase

• Enable s the SPI Modul e

• Frees the SS pin for a general-purpose

Table 92 describes this register and explains the use of each bit

Table 92. SPCON Register

SPCON - Serial Peripheral Control Register (0D4H)

SPI

CPU Interrupt Request

SPIF

SPTEIE

SPTE

MODF

MODFIE

76543210

SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0

Bit Number Bit Mnemonic Description

7 SPR2 Serial Peripheral Rate 2

Bit with SPR1 and SPR0 define the clock rate (See bits SPR1 and

SPR0 for detail).

6SPEN

Serial Peripheral Enable

Cleared to disable the SPI interface (internal reset of the SPI).

Set to enable the SPI interface.

5 SSDIS

SS Disable

Cleared to enable SS in both Master and Slave modes.

Set to disable SS in both Master and Slave modes. In Slave mode,

this bit has no effect if CPHA =’0’. When SSDIS is set, no MODF

interrupt request is generated.

4MSTR

Serial Peripheral Master

Cleared to configure the SPI as a Slave.

Set to configure the SPI as a Master.

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Reset Value = 0001 0100b

Not bit address ab le

Serial Peripheral Status Register

and Control (SPSCR) The Serial Peripheral Status Register contains flags to signal the following conditions:

• Data transfer complete

• Write collision

• Inconsistent logic level on SS pin (mode fault error)

Table 93. SPSCR Regist er

SPSCR - Serial Peripheral Status and Control register (0D5H)

3CPOL

Clock Polarity

Cleared to have the SCK set to ’0’ in idle state.

Set to have the SCK set to ’1’ in idle state.

2CPHA

Clock Phase

Cleared to have the data sampled when the SCK leaves the idle

state (see CPOL).

Set to have the data sampled when the SCK returns to idle state (see

CPOL).

1 SPR1 SPR2 SPR1 SPR0 Serial Peripheral Rate

0 0 0 Invalid

00 1 F

CLK PERIPH /4

01 0 F

CLK PERIPH /8

01 1F

CLK PERIPH /16

10 0F

CLK PERIPH /32

10 1F

CLK PERIPH /64

11 0F

CLK PERIPH /128

1 1 1 Invalid

0 SPR0

Bit Number Bit Mnemonic Description

76543210

SPIF - OVR MODF SPTE UARTM SPTEIE MODFIE

Bit

Number Bit

Mnemonic Description

7SPIF

Serial Peripheral Data Transfer Flag

Cleared by hardware to indicate data transfe r is in progress or has been

approved by a clearing sequence.

Set by hardware to indicate that the data transfer has been completed.

This bit is cleared when reading or writing SPDATA after reading SPSCR.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

5OVR

Overrun Error Flag

- Set by hardware when a byte is received whereas SPIF is set (the previous

received data is not overwritten).

- Cleared by hardware when reading SPSCR

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Reset Value = 00X0 XXXXb

Not Bit addressable

Serial Peripheral DATa Register

(SPDAT) The Serial Peripheral Data Register (Table 94) is a read/write buffer for the receive data

available in this model.

A Read of the SPDAT returns the value located in the receive buffer and not the content

of the shift register.

Table 94. SPDAT Register

SPDAT - Serial Peripheral Data Register (0D6H)

Reset Value = Indeterm inate

R7:R0: Receive data bits

4MODF

Mo de F a ult

- Set by hardware to indicate that the SS pin is in inappropriate logic level (in both

master and slave modes).

- Cleared by hardware when reading SPSCR

When MODF error occ urred:

- In slave mode: SPI interface ignores all transmitted data while SS remains high.

A new transmission is perform as soon as SS returns low.

- In master mode: SPI interface is disabled (SPEN=0, see description for SPEN

bit in SPCON register).

3 SPTE

Serial Peripheral Transmit register Empty

- Set by hardware when transmit register is empty (if needed, SPDAT can be

loaded with another data).

- Cleared by hardware when transmit register is full (no more data should be

loaded in SPDAT).

2UARTM

Serial Peripheral UART mode

Set and cleared by software:

- Clear: Normal mode, data are transmitted MSB first (default)

- Set: UART mode, data are transmitted LSB first.

1SPTEIE

Interrupt Enable for SPTE

Set and cleared by software:

- Set to enable SPTE interrupt generation (when SPTE goes high, an interrupt is

generated).

- Clear to disable SPTE interrupt generation

Caution: When SPTEIE is set no interrup t generation occurred when SPIF flag

goes high. To enable SPIF interrupt again, SPTEIE should be cleared.

0MODFIE

Interrupt Enable for MODF

Set and cleared by software:

- Set to enable MODF interrupt generation

- Clear to disable MODF interrupt generation

Bit

Number Bit

Mnemonic Description

76543210

R7 R6 R5 R4 R3 R2 R1 R0

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SPCON, SPSTA and S PDAT reg isters may be read and wr itten at any t ime wh ile th ere

is no on-going exchange. However, special care should be taken when writing to them

while a transmission is on-going:

• Do not change SPR2, SPR1 and SPR0

• Do not change CPHA and CPOL

• Do not change MSTR

• Clearing SPEN would immediately disable the peripheral

• Writing to the SPDAT wi ll cause an overflow.

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Programmable

Counter Array (PCA) The PCA provides more timing capabilities with less CPU intervention than the standard

timer/counters. Its advantages include reduced software overhead and improved accu-

racy. T he PCA co nsists of a dedic ated timer /counte r which se rves as the time ba se for

an arra y of fiv e compar e/ca pture mod ules . Its cl ock inp ut can be progra mmed to count

any of the following signals:

• PCA clock frequency/6 (see “clock” section)

• PCA clo ck frequency/2

• Timer 0 overflow

• External input on ECI (P1.2)

Each compare/capture modules can be programmed in any one of the following modes:

• rising and/or falling edg e captu re,

• software timer,

• high-speed output,

• pulse width modulator.

Module 4 can al so be pro grammed as a Watch Dog timer. s ee the "PCA WatchDo g

Timer" section.

When the c ompare /capture m odules are progra mmed in ca pture mo de, software timer,

or high speed output mode, an interrupt can be generated when the module executes its

function. All five modules plus the PCA timer overflow share one interrupt vector.

The PCA timer /counter and compa re/captu re mod ules share P ort 1 for external I/Os.

These pins are lis ted below. If the port is not used for the PCA, it can still be used for

standard I/O.

PCA Timer The PCA timer is a common time base for all five modules (s ee Figure 67). The timer

count source is determined from the CPS1 and CPS0 bits in the CMOD SFR (see Table

8) and can be programmed to run at:

• 1/6 the PCA clock frequency.

• 1/2 the PCA clock frequency.

• the Timer 0 overflow.

• the input on the ECI pin (P1.2).

PCA Component External I/O Pin

16-bit Counter P1.2/ECI

16-bit Module 0 P1.3/CEX0

16-bit Module 1 P1.4/CEX1

16-bit Module 2 P1.5/CEX2

16-bit Module 3 P1.6/CEX3

16-bit Module 4 P1.7/CEX4

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Figure 67. PCA Timer/Counter

The CMOD register includes three additional bits associated with the PCA.

• The CIDL bit which allows the PCA to stop during idle mode.

• The WDTE bit which enables or disables the WatchDog function on module 4.

• The ECF bit which when set causes an interrupt and the PCA overflow flag CF in

CCON register to be set when the PCA timer overflows.

The CCON registe r contains the run c ontrol bit for the P CA and the flags for the PCA

timer and each module.

• The CR bit must be set to run the PCA. The PCA is shut off by clearing this bit.

• The CF bit is set when the PCA counter overflows and an interrupt will be generated

if the ECF bit in CMOD register is set. The CF bit can only be cleared by software.

• The CCF0:4 bits are the flags for the modules (CCF0 for module0...) and are set by

hardware when either a match or a capture occurs. These flags also can be cleared

by software.

PCA Modules Each one of the five compare/capture modules has six possible functions. It can

perform:

• 16-bit Capture, positive-edge triggered

• 16-bit Capture, negative-edge triggered

• 16-bit Capture, both positive and negative-edge triggered

• 16-bit Software Timer

• 16-bit High Speed Output

• 8-bit Pulse Width Modulator.

In addition module 4 can be used as a WatchDog Timer.

CIDL CPS1 CPS0 ECF

CH CL

16 bit up counter

To PCA

modules

FPca/6

FPca/2

T0 OVF

P1.2

Idle

CMOD

0xD9

WDTE

CF CR CCON

0xD8

CCF4 CCF3 CCF2 CCF1 CCF0

overflow

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Each module in the PCA has a specia l functi on register asso ciated with it (CCAP M0 for

module 0 ...) . The CCAPM0:4 reg isters contai n the bits that control the mode that each

module will operate in.

• The ECCF bit enables the CCF flag in the CCON register to generate an interrupt

when a match or compare occurs in the associated module.

• The PWM bit enables the pulse width modulation mode.

• The TOG bit when set causes the CEX output associated with the module to toggle

when there is a match between the PCA counter and the module’s capture/compare

• The match bit MAT when set will cause the CCFn bit in the CCON register to be set

when there is a match between the PCA counter and the module’s capture/compare

• The two bits CAPN and CAPP in CCAPMn register determine the edge that a

capture input will be active on. The CAPN bit enables the negative edge, and the

CAPP bit enables the positive edge. If both bits are set both edges will be enabled.

• The bit ECOM in CCAPM register when set enables the comparator function.

PCA Interrupt

Figure 68. PCA Interrupt System

PCA Capture Mode To use o ne of the P CA mod ules in cap ture mode e ither o ne or both of the CCAPM b its

CAPN and CAPP for that module must be set. The external CEX input for the module

(on port 1) is sa mpl ed fo r a trans i tio n. Wh en a v ali d tr ansi tion occurs the PC A har d war e

loads the value of the PCA counter registers (CH and CL) into the module’s capture reg-

isters (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCON SFR and the

ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated.

CF CR CCON

CCF4 CCF3 CCF2 CCF1 CCF0

Module 4

Module 3

Module 2

Module 1

Module 0

PCA Timer/Counter

ECCFn

CCAPMn.0

To Interr u p

IEN0.7

IEN0.6

ECF

CMOD.0

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Figure 69. PCA Capture Mode

16-bit Soft ware Timer

Mode The PCA mod ules can be used as software tim ers by settin g both the ECOM and MAT

bits in the m odu les CC APMn r egiste r. The PCA timer will be comp ared to the modul e’s

capture registers and when a match occurs an interrupt will occur if the CCFn (CCON

SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set.

Figure 70. PCA 16-bit Software Timer and High Speed Output Mode

CEXn

n = 0, 4

PCA Counter

(8bits) CL

(8bits)

CCAPnH CCAPnL

CCFn

CCON

PCA

Interrup

Reques

7 CCAPMn Register (n = 0, 4) 0

CAPMn CAPNn

ECOMn CAPPn MATn TOGn PWMn ECCFn

CCAPnL

(8 bits)

CCAPnH

(8 bits)

70 CCAPMn Register

(n = 0, 4)

(8 bits) CL

(8 bits)

16-Bit Comparator Match

Enable CCFn

CCON re g

PCA

Interrupt

Request

CEXn

Compare/Capture Module

PCA Counter

“0”

“1”

Reset

Write to

CCAPnL

Write to CCAPnH

For software Ti mer m ode, set ECOMn and MATn.

For high speed output mode, set ECOMn, MATn and TOGn.

Toggle

CAPMn CAPNn

ECOMn CAPPn MATn TOGn PWMn ECCFn

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High Speed Output Mode In this mode the CEX output (on port 1) associated with the PCA module will toggle

each time a match occurs between the PCA counter and the module’s capture registers.

To activ ate this mode the T OG, MAT, and ECO M bits in the module’ s CCAPMn SFR

must be set.

Figure 71. PCA High Speed Output Mode

Pulse Width Modulator

Mode All the PCA modules can be used as PWM outputs. The output frequency depends on

the source for th e PCA timer. All the modules will have the same output frequency

becau se they al l share the PCA ti mer. Th e duty cyc le of eac h modul e is indep endent ly

variable using the module’s c apture register CCAPLn. When the value of the PCA CL

SFR is les s than the v alue in the mo dule’s CC APLn S FR the outp ut will be low, wh en it

is equal to or greater than it, t he output will be hig h. When CL overfl ows from FF to 00,

CCAPLn is reloaded with the value in CCAPHn. the allows the PWM to be updated with-

out glitches. The PWM and ECOM bits in the module’s CCAPMn register must be set to

enable the PWM mode.

CH CL

CCAPnH CCAPnL

ECOMn CCAPMn, n = 0 to 4

0xDA to 0xDE

CAPNn MATn TOGn PWMn ECCFnCAPPn

16-bit comparator Match

CF CR CCON

0xD8

CCF4 CCF3 CCF2 CCF1 CCF0

PCA IT

Enable

CEXn

PCA counter/timer

“1”“0”

Write to

CCAPnL

Reset

Write to

CCAPnH

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Figure 72. PCA PWM Mode

PCA WatchDog Timer An on-board WatchDog timer is available with the PCA to improve system reliabili ty

without increasing chip count. WatchDog timers are useful for systems that are sensitive

to noise, p ower glitches , or elect rostatic discha rge. Module 4 is the only PCA modul e

that can be programmed as a WatchDog. However, this module can still be used for

other m odes if the Wa tchDog is not ne eded. The use r pre-load s a 16-bit value in the

compar e r egi ster s. Just like the o ther com par e mo des, this 16 -bit valu e is co mp ared t o

the PCA tim er valu e. If a match is allowed to occur, an in ternal rese t will be gene rated.

This will not cause the RST pin to be driven high.

To hold off the reset, the user has three options:

• periodically change the compare value so it will never match the PCA timer,

• periodically change the PCA timer value so it will never match the compare values,

• disable the WatchDog by clearing the WDTE bit before a match occurs and then re-

enable it.

The first two options are more reliable because the WatchDog timer is never disabled as

in the third option. If the program counter ever goes astray, a match will eventually occur

and cause an internal reset. If other PCA modules are being used the second option not

recommended either. Remember, the PCA timer is the time base for all modules;

changing the time base for other modules would not be a good idea. Thus, in most appli-

cations the first solution is the best option.

CL rolls over from FFh TO 00h loads

CCAPnH contents into CCAPnL

CCAPnL

CCAPnH

8-Bit

Comparator

CL (8 bits)

“0”

“1”

CL < CCAPnL

CL > = CCAPnL CEX

PWMn

CCAPMn.1

ECOMn

CCAPMn.6

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PCA Registers Table 95. CMOD Register

CMOD (S:D9h)

PCA Counter Mode Register

Reset Val ue = 00XX X00 0b

76543210

CIDL WDTE - - - CPS1 CPS0 ECF

Bit

Number Bit

Mnemonic Description

7CIDL

PCA Counter Idle Control bit

Clear to let the PCA run during Idle mode.

Set to stop the PCA when Idle mode is invoked.

6WDTE

WatchDog Timer Enable

Clear to disable WatchDog Timer function on PCA Module 4,

Set to enable it.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

2CPS1

EWC Coun t Pulse Select bits

CPS1 CPS0 Clock source

0 0 Internal Clock, FPca/6

0 1 Internal Clock, FPca/2

1 0 Timer 0 overflow

1 1 Ext ernal clock at ECI/P1.2 pin (Max. Rate = FPca/4)

1CPS0

Reserved

The value read from this bit is indeterminate. Do not set this bit.

0ECF

Enable PCA Count e r Ov e r flow Inter r upt bit

Clear to disable CF bit in CCON register to generate an interrupt.

Set to enable CF bit in CCON register to generate an interrupt.

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Table 96. CCON Register

CCON (S:D8h)

PCA Counter Control Register

Reset Value = 00X0 0000b

76543210

CF CR - CCF4 CCF3 CCF2 CCF1 CCF0

Bit

Number Bit

Mnemonic Description

7CF

PCA Timer/Counter Overflow flag

Set by hardware when the PCA Timer/Counter rolls over. This generates a PCA

interrupt request if the ECF bit in CMOD register is set.

Must be cleared by software.

6CR

PCA Timer/Counter Run Control bit

Clear to turn the PCA Timer/Counter off.

Set to turn the PCA Timer/Counter on.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

4 CCF4

PCA Module 4 Compare/Capture flag

Set by hardware when a match or capture occurs. This generates a PCA

interrupt request if the ECCF 4 bit in CCAPM 4 register is set.

Must be cleared by software.

3 CCF3

PCA Module 3 Compare/Capture flag

Set by hardware when a match or capture occurs. This generates a PCA

interrupt request if the ECCF 3 bit in CCAPM 3 register is set.

Must be cleared by software.

2 CCF2

PCA Module 2 Compare/Capture flag

Set by hardware when a match or capture occurs. This generates a PCA

interrupt request if the ECCF 2 bit in CCAPM 2 register is set.

Must be cleared by software.

1 CCF1

PCA Module 1 Compare/Capture flag

Set by hardware when a match or capture occurs. This generates a PCA

interrupt request if the ECCF 1 bit in CCAPM 1 register is set.

Must be cleared by software.

0 CCF0

PCA Module 0 Compare/Capture flag

Set by hardware when a match or capture occurs. This generates a PCA

interrupt request if the ECCF 0 bit in CCAPM 0 register is set.

Must be cleared by software.

149

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Table 97. CCAPnH Registers

CCAP0H (S:FAh)

CCAP1H (S:FBh)

CCAP2H (S:FCh)

CCAP3H (S:FDh)

CCAP4H (S:FEh)

PCA High Byte Compare/Capture Module n Register (n=0..4)

Reset Value = 0000 0000b

Table 98. CCAPnL Registers

CCAP0L (S:EAh)

CCAP1L (S:EBh)

CCAP2L (S:ECh)

CCAP3L (S:EDh)

CCAP4L (S:EEh)

PCA Low Byte Compare/Capture Module n Register (n=0..4)

Reset Value = 0000 0000b

76543210

CCAPnH 7 CCAPnH 6 CCAPnH 5 CCAPnH 4 C CAPnH 3 CCAPnH 2 CCAPnH 1 CCAPnH 0

Bit

Number Bit

Mnemonic Description

7:0 CCAPnH

7:0 High byte of EWC-PCA comparison or capture values

76543210

CCAPnL 7 CCAPnL 6 CCAPnL 5 CCAPnL 4 CCAPnL 3 CCA PnL 2 CCAPnL 1 CCAPnL 0

Bit

Number Bit

Mnemonic Description

7:0 CCAPnL

7:0 Low byte of EWC-PCA comparison or capture values

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Table 99. CCAPMn Registers

CCAPM0 (S:DAh)

CCAPM1 (S:DBh)

CCAPM2 (S:DCh)

CCAPM3 (S:DDh)

CCAPM4 (S:DEh)

PCA Compare/Capture Module n Mode registers (n=0..4)

Reset Value = X000 0000b

76543210

- ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn

Bit

Number Bit

Mnemonic Description

Reserved

The Value read from this bit is indeterminate. Do not set this bit.

6ECOMn

Enable Compare Mode Module x bit

Clear to disable the Compare function.

Set to enable the Compare function.

The Compare function is used to implement the software Timer, the high-speed

output, the Pulse Width Modulator (PWM) and the WatchDog Timer (WDT).

5 CAPPn Capture Mode (Positive) Module x bit

Clear to disable the Capture function triggered by a positive edge on CEXx pin.

Set to enable the Capture function triggered by a positive edge on CEXx pin

4CAPNn

Capture Mode (Negative) Modul e x bit

Clear to disable the Capture function triggered by a negative edge on CEXx pin.

Set to enable the Capture function triggered by a negative edge on CEXx pin.

3MATn

Match Module x bit

Set when a match of the PCA Counter with the Compare/Capture register sets

CCFx bit in CCON register, flagging an interrupt.

2 TOGn

Toggle Module x bit

The toggle mode is configured by setting ECOMx, MATx and TOGx bits.

Set when a match of the PCA Counter with the Compare/Capture register

toggles the CEXx pin.

1PWMn

Pulse Wid th Modulation Module x Mode bit

Set to configure the module x as an 8-bit Pulse Width Modulator with output

waveform on CEXx pin.

0ECCFn

Enable CCFx Interrupt bit

Clear to disable CCFx bit in CCON register to generate an interrupt request.

Set to enable CCFx bit in CCON register to generate an interrupt request.

151

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Table 100. CH Register

CH (S:F9h)

PCA Counter Register High Value

Reset Value = 0000 00000b

Table 101. CL Register

CL (S:E9h)

PCA counter Register Low Value

Reset Value = 0000 00000b

76543210

CH 7 CH 6 CH 5 CH 4 CH 3 CH 2 CH 1 CH 0

Bit

Number Bit

Mnemonic Description

7:0 CH 7:0 High byte of Timer/Counter

76543210

CL 7CL 6CL 5CL 4CL 3CL 2CL 1CL 0

Bit

Number Bit

Mnemonic Description

7:0 CL0 7:0 Low byte of Ti mer/Counter

152

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Analog-to-Digital

Converter (ADC) This section describes the on-chip 10 bit analog-to-digital converter of the

AT89C5 1CC03. Eig ht ADC chann els are availa ble for sa mpling of the ex ternal sourc es

AN0 t o AN7. An analog multiple xer all ows the singl e ADC con verter to s elec t one from

the 8 ADC channels as ADC input voltage (ADCIN). ADCIN is converted by the 10-bit

cascad ed pote nti ome tric ADC.

Two kinds of conversion are available:

- Standard conversion (8 bits).

- Precision conversion (10 bits) (Up to 85°C only).

For the precision conversion, set bit PSIDLE in ADCON register and start conversion.

The devic e is in a pseud o-idle mode, the CPU does not run but the peripheral s are

always running . Th is m ode al lows digital nois e to be as low as poss ible , to e nsur e hig h

precision conversion.

For th is mode it is nec essa ry to wo rk w ith end o f conv ersio n inter rupt, wh ich is th e only

way to wake the device up.

If another i nterrupt occurs during the p recision c onversion, it will be treate d only after

this conv ersi on is ended.

Features • 8 channels with multiplexed inputs

• 10-bit cascaded potentiometric ADC

• Conversion time 16 micro-seconds (typ.)

• Zero Error (offset) ± 2 LSB max

• Positive External Reference Voltage Range (VREF) 2.4 to 3.0Volt (typ.)

• ADCIN Range 0 to 3Volt

• Integral non-linearity typical 1 LSB, max. 2 LSB

• Differential non-linearity typical 0.5 LSB, max. 1 LSB

• Conversion Complete Flag or Conversion Complete Interrupt

• Selectable ADC Clock

ADC Port1 I/O Functions Port 1 pins are gener al I/O tha t are sh ared wit h the ADC ch annels . The channel select

bit in ADCF register de fine which A DC channel/por t1 pin will be used as ADCIN. The

remaining ADC channels/port1 pins can be used as general-purpose I/O or as the alter-

nate function that is available.

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Figure 73. ADC Description

Figure 74 shows the timin g dia gram of a com plete conv ersio n. For sim plicit y, th e figu re

depicts the waveforms in idealized form and do not provide precise timing information.

For ADC characteristics and timing parameters refer to the Section “AC Characteristics”

of the AT89C51CC03 datasheet.

Figure 74. Timing Dia gram

Note: Tsetup min = 4 us

Tconv=11 clock ADC = 1sample and hold + 10 bit conversion

The user must ensure that 4 us minimum time between setting ADEN and the start of the first conversion.

AN0/P1.0

AN1/P1.1

AN2/P1.2

AN3/P1.3

AN4/P1.4

AN5/P1.5

AN6/P1.6

AN7/P1.7

000

001

010

011

100

101

110

111

SCH2

ADCON.2 SCH0

ADCON.0

SCH1

ADCON.1

ADC

CLOCK

ADEN

ADCON.5 ADSST

ADCON.3

ADEOC

ADCON.4 ADC

Interrupt

Request

EADC

IEN1.1

CONTROL

AVSS

Sam ple and Ho ld

ADDH

VAREF

R/2R DAC

VAGND

-ADDL

SAR

ADCIN

ADEN

ADSST

ADEOC

TSETUP

TCONV

CLK

154

AT89C51CC03

4182O–CAN–09/08

ADC Converter

Operation A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3).

After completion of the A/D conversion, the ADSST bit is cleared by hardware.

The end-of-conversion flag ADEOC (ADCON.4) is set when the value of conversion is

available in ADDH and ADDL, it must be cleared by software. If the bit EADC (IEN1.1) is

set, an in terrupt occur when flag A DEOC is set ( see Figure 76). Clear this fla g for re-

arming the inte rru pt.

The bits SCH0 to SCH2 in ADCON register are used for the analog input channel

selection.

Table 102. Selected Analog input

Voltage Conversion When the ADCIN is equals to VAREF the ADC converts the signal to 3FFh (full scale). If

the input vol tage equals VAGND, the A DC converts it to 000h. Input v oltage between

VAREF and VAG ND ar e a str ai ght-l ine lin ear c onv er sion . Al l oth er volt ag es w ill r esu lt i n

3FFh if greater than VAREF and 000h if less than VAGND.

Note that ADCIN should not exceed VAREF absolute maximum range! (See section

“AC-DC”)

Clock Selection The ADC cloc k is the same as CPU.

The maximum clock frequency is defined in the DC parameters for A/D converter. A

prescaler is featured (ADCCLH) to generate the ADC clock from the oscillator

frequency.

if PRS = 0 then FADC = Fperiph / 64

if PRS > 0 then FADC = Fperiph / 2 x PRS

SCH2 SCH1 SCH0 Selected Analog input

000AN0

001AN1

010AN2

011AN3

100AN4

101AN5

110AN6

111AN7

155

AT89C51CC03

4182O–CAN–09/08

Figure 75. A/D Converte r Clock

ADC Standby Mode W hen the ADC is not us ed, it is possibl e to set it in stand by mode by clea ring bit ADE N

in ADCON register. In this mode its power dissipation is about 1 µW.

IT ADC Management An interrupt end-of-conversion will occurs when the bit ADEOC is activated and the bit

EADC is set. For re-arming the interrupt the bit ADEOC must be cleared by software.

Figure 76. ADC Interrupt Struct ure

Routines examples 1. Configure P1.2 and P1.3 in ADC channels

// configure channel P1.2 and P1.3 for ADC

ADCF = 0Ch

// Enable the ADC

ADCON = 20h

2. Start a standard conversion

// The variable "channel" contains the channel to convert

// The variable "value_converted" is an unsigned int

// Clear the field SCH[2:0]

ADCON and = F8h

// Select channel

ADCON | = channel

// Start conversion in standard mode

ADCON | = 08h

// Wait flag End of conversion

while((ADCON and 01h)! = 01h)

// Clear the End of conversion flag

ADCON and = EFh

// read the value

value_converted = (ADDH << 2)+(ADDL)

3. Start a precision conversion (need interrupt ADC)

// The variable "channel" contains the channel to convert

// Enable ADC

Prescaler ADCLK A/D

Converter

ADC Clock

CPU

CLOCK

CPU Core Clock Symbol

÷ 2

ADEOC

ADCON.2

EADC

IEN1.1

ADCI

156

AT89C51CC03

4182O–CAN–09/08

EADC = 1

// clear the field SCH[2:0]

ADCON and = F8h

// Select the channel

ADCON | = channel

// Start conversion in precision mode

ADCON | = 48h

Note: to enable the ADC interrupt:

EA = 1

157

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Registers Table 103. ADCF Register

ADCF (S:F6h)

ADC Configuration

Reset Value =0000 000 0b

Table 104. ADCON Register

ADCON (S:F3h)

ADC Control Register

Reset Value =X000 0000b

76543210

CH 7 CH 6 CH 5 CH 4 CH 3 CH 2 CH 1 CH 0

Bit

Number Bit

Mnemonic Description

7-0 CH 0:7 Channel Configuration

Set to use P1.x as ADC input.

Clear to use P1.x as standart I/O port.

76543210

- PSIDLE ADEN ADEOC ADSST SCH2 SCH1 SCH0

Bit

Number Bit

Mnemonic Description

6 PSIDLE Pseudo Idle Mode (Best Precision)

Set to put in idle mode during conversion

Clear to convert without idle mode.

5ADEN

Enable/Standby Mode

Set to enable ADC

Clear for S t andby mode (power dissipation 1 uW).

4ADEOC

End Of Conversion

Set by hardware when ADC result is ready to be read. This flag can generate an

interrupt.

Must be cleared by software.

3 ADSST St art and Status

Set to start an A/D conversion.

Cleared by hardware after completion of the conversion

2-0 SCH2:0 Selection of Channel to Convert

see Table 102

158

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Table 105. ADCLK Register

ADCLK (S:F2h)

ADC Clock Prescaler

Reset Value = XXX0 0000b

Note: 1. In X1 mode:

For PRS > 0 FADC = FXTAL

4xPRS

For PRS = 0 FADC = FXTAL

128

In X2 mode:

For PRS > 0 FADC = FXTAL

2xPRS

For PRS = 0 FADC = FXTAL

Table 106. ADDH Register

ADDH (S:F5h Read Only)

ADC Data High Byte Register

Reset Value = 00h

Table 107. ADDL Register

ADDL (S:F4h Read Only)

ADC Data Low Byte Register

76543210

- - - PRS 4PRS 3PRS 2PRS 1PRS 0

Bit

Number Bit

Mnemonic Description

7-5 - Reserved

The value read from these bits are indeterminate. Do not set these bits.

4-0 PRS4:0 Clock Prescaler

See Note (1)

76543210

ADAT 9 ADAT 8 ADAT 7 ADAT 6 ADAT 5 ADAT 4 ADAT 3 ADAT 2

Bit

Number Bit

Mnemonic Description

7-0 ADAT9:2 ADC result

bits 9-2

76543210

------ADAT 1ADAT 0

159

AT89C51CC03

4182O–CAN–09/08

Reset Value = 00h

Bit

Number Bit

Mnemonic Description

7-2 - Reserved

The value read from these bits are indeterminate. Do not set these bits.

1-0 ADAT1:0 ADC result

bits 1-0

160

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Interrupt System

Introduction The CAN Controller has a total of 10 interrupt vectors: two external interrupts (INT0 and

INT1), three time r interrupts ( timers 0, 1 an d 2), a se rial port in terrupt, a PCA, a CAN

interrupt, a timer overrun interrupt and an ADC. These interrupts are shown below.

Figure 77. Interrupt Control System

ECAN

IEN1.0

EX0

IEN0.0

External

Interrupt 0

INT0#

IEN0.7

EX1

IEN0.2

External

Interrupt 1

INT1#

ET0

IEN0.1

Timer 0

IEN0.6

PCA

ET1

IEN0.3

Timer 1

IEN0.4

UART

EADC

IEN1.1

A to D

Converter

ETIM

IEN1.2

CAN Timer

CAN

Interrupt Enable Lowest Priority Interrupts

Highest

Priority Enable

Priority

Interrup

TxDC

RxDC

AIN1:0

IPH/L

controller

Timer 2

ET2

IEN0.5

TxD

RxD

CEX0:5

ESPI

IEN1.3

SPI

Controller

161

AT89C51CC03

4182O–CAN–09/08

Each of the interrupt sources can be individually enabled or disabled by setting or clear-

ing a bit in the Interrupt Enable register. This register also contains a global disable bit

which must be cleared to disable all the interrupts at the same time.

Each int errupt source can al so be indivi dually programme d to one of fou r priority le vels

by setting or c learing a bit in t he Inter rupt Pr iority regis ters. The Tabl e belo w shows th e

bit values and priority levels associated with each combination.

Table 108. Priority Level Bit Values

A low-priority interrupt can be interrupted by a high priority interrupt but not by another

low-priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt

source.

If two interrupt requests of different priority levels are received simultaneously, the

request of the higher priority level is serviced. If interrupt requests of the same priority

level are received simultaneously, an internal polling sequence determines which

request is servi ced. Thus within ea ch prio rity le vel ther e is a se cond p riority str ucture

determined by the polling sequence, see Table 109.

Table 109. Interrupt priority Within level

IPH.x IPL.x Interrupt Level Priority

0 0 0 (Lowest)

011

102

1 1 3 (Highest)

Interrupt Name Interrupt Address Vector Priority Number

external interrupt (INT0) 0003h 1

Timer0 (TF0) 000Bh 2

external interrupt (INT1) 0013h 3

Timer1 (TF1) 001Bh 4

PCA (CF or CCFn) 0033h 5

UART (RI or TI) 0023h 6

Timer2 (TF2) 002Bh 7

CAN (Txok, Rxok, Err or OvrBuf) 003Bh 8

ADC (ADCI) 0043h 9

CAN Timer Overflow (OVRTIM) 004Bh 10

SPI interrupt 0053h 11

162

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Registers Table 110. IEN0 Regi st er

IEN0 (S:A8h)

Interrupt Enable Register

Reset Value = 0000 0000b

bit addressable

76543210

EA EC ET2 ES ET1 EX1 ET0 EX0

Bit

Number Bit

Mnemonic Description

7EA

Enable All Interrupt bit

Clear to disable all interrupts.

Set to enable all interrupts.

If EA=1, each interrupt source is individually enabled or disabled by setting or

clearing its interrupt enable bit.

6EC

PCA Interrupt Enable

Clear to disable the PCA interrupt.

Set to enable the PCA interrupt.

5ET2

Timer 2 Overflow Interrupt Enable bit

Clear to disable Timer 2 overflow interrupt.

Set to enable Timer 2 overflow interrupt.

4ES

Serial Port Enable bit

Clear to disable serial port interrupt.

Set to enable serial port interrupt.

3ET1

Timer 1 Overflow Interrupt Enable bit

Clear to disable timer 1 overflow interrupt.

Set to enable timer 1 overflow interrupt.

2EX1

External Interrupt 1 Enable bit

Clear to disable external interrupt 1.

Set to enable external interrupt 1.

1ET0

Timer 0 Overflow Interrupt Enable bit

Clear to disable timer 0 overflow interrupt.

Set to enable timer 0 overflow interrupt.

0EX0

External Interrupt 0 Enable bit

Clear to disable external interrupt 0.

Set to enable external interrupt 0.

163

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Table 111. IEN1 Register

IEN1 (S:E8h)

Interrupt Enable Register

Reset Value = xxxx 0000b

bit addressable

76543210

----ESPIETIM EADCECAN

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

3ESPI

SPI Interrupt Enable bit

Clear to disable the SPI interrupt.

Set to enable the SPI interrupt.

2ETIM

TImer Overrun Interrupt Enable bit

Clear to disable the timer overrun interrupt.

Set to enable the timer overrun interrupt.

1 EADC ADC Interrupt Ena ble bit

Clear to disable the ADC interrupt.

Set to enable the ADC interrupt.

0ECAN

CAN Interrupt Ena ble bit

Clear to disable the CAN interrupt.

Set to enable the CAN interrupt.

164

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Table 112. IPL0 Register

IPL0 (S:B8h)

Interrupt Enable Register

Reset Value = X000 0000b

bit addressable

76543210

- PPC PT2 PS PT1 PX1 PT0 PX0

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

6 PPC PCA Interrupt Priority bit

Refer to PPCH for priority level

5PT2

Timer 2 Overflow Interrupt Priority bit

Refer to PT2H for priority level.

4PS

Serial Port Priority bit

Refer to PSH for priority level.

3PT1

Timer 1 Overflow Interrupt Priority bit

Refer to PT1H for priority level.

2PX1

External Interrupt 1 Priority bit

Refer to PX1H for priority level.

1PT0

Timer 0 Overflow Interrupt Priority bit

Refer to PT0H for priority level.

0PX0

External Interrupt 0 Priority bit

Refer to PX0H for priority level.

165

AT89C51CC03

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Table 113. IPL1 Register

IPL1 (S:F8h)

Interrupt Priority Low Register 1

Reset Value = XXXX 0000b

bit addressable

76543210

----SPILPOVRLPADCL PCANL

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

3SPIL

SPI Interrupt Priority Level Less Significant Bit

Ref e r to SPIH fo r prior i t y level.

2POVRL

Timer Overrun Interrupt Priority Level Less Significant Bit

Refer to PI2CH for priority level.

1PADCL

ADC Interrupt Priority Level Less Significant Bit

Refer to PSPIH for priority level.

0PCANL

CAN Interrupt Priority Level Less Significant Bit

Refer to PKBH for priority level.

166

AT89C51CC03

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Table 114. IPL0 Register

IPH0 (B7h)

Interrupt High Priority Register

Reset Value = X000 0000b

76543210

- PPCH PT2H PSH PT1H PX1H PT0H PX0H

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

6 PPCH

PCA Interrupt Priority Level Most Significant bit

PPCH PPC Priority level

0 0 Lowest

0 1

1 0

1 1 Highest priority

5PT2H

Timer 2 Overflow Interrupt High Priority bit

PT2H PT2 Priority Level

0 0 Lowest

0 1

1 0

1 1 Highest

4 PSH

Serial Port High Priority bit

PSH PS Priority Level

0 0 Lowest

0 1

1 0

1 1 Highest

3PT1H

Timer 1 Overflow Interrupt High Priority bit

PT1H PT1 Priority Level

0 0 Lowest

0 1

1 0

1 1 Highest

2PX1H

External Interrupt 1 High Priority bit

PX1H PX1 Priority Level

0 0 Lowest

0 1

1 0

1 1 Highest

1PT0H

Timer 0 Overflow Interrupt High Priority bit

PT0H PT0 Priority Level

0 0 Lowest

0 1

1 0

1 1 Highest

0PX0H

External Interrupt 0 high priority bit

PX0H PX0 Priority Level

0 0 Lowest

0 1

1 0

1 1 Highest

167

AT89C51CC03

4182O–CAN–09/08

Table 115. IPH1 Regist er

IPH1 (S:F7h)

Interrupt High Priority Register 1

Reset Valu e = XXXX 0000b

76543210

----SPIHPOVRHPADCH PCANH

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

3SPIH

SPI Interrupt Priority Level Most Significant bit

SPIH SPIL Priority level

0 0 Lowest

0 1

1 0

1 1 Highest

2POVRH

Timer overrun Interrupt Priority Level Most Significant bit

POVRH POVRL Priority level

0 0 Lowest

0 1

1 0

1 1 Highest

1 PADCH

ADC Interrupt Priority Level Most Significant bit

PADCH PADCL Priority level

0 0 Lowest

0 1

1 0

1 1 Highest

0PCANH

CAN Interrupt Priority Level Most Significant bit

PCANH PCANL Priority level

0 0 Lowest

0 1

1 0

1 1 Highest

168

AT89C51CC03

4182O–CAN–09/08

Electrical Characteristics

Absolute Maximum Ratings

ICCOP Test Conditions

Power Consumption

Management Since the introduction of the first C51 device, every manufacturer made operatin g ICC

measurements under Reset, which made sense for the designs where the CPU was

running under reset. In our new devices, the CPU is no longer active during reset, so the

power c onsumptio n is very low bu t not represen tative of wha t wil l happen in the cu s-

tomer sy stem. T hus, while keepi ng measur ements un der Res et, we pre sent a ne w way

to measure the operating ICC.

Using an internal test ROM, the following code is executed.

Label: SJMP Label (80FE)

Ports 1 and 4 are disconnected, RST = Vcc, XTAL2 is not c onnected and XTAL1 is

driven by the clock.

This is much more representative of the real operating Icc.

DC Parameters for Standard Voltage

Industrial TA = -40°C to +85°C; VSS = 0V;

Automotive TA = -40°C to +125°C; VSS = 0V

VCC =3.0V to 5.5V and F = 0 to 40 MHz (both internal and external code execution)

VCC =4.5V to 5.5V and F = 0 to 60 MHz (internal code execution only)

Ambiant Temperature Un der Bias :

I = industrial.. ..... ...... ..... ...... ................. ...... ..... ....-4 0 °C to 85°C

A = automotive..................................................-40°C to +125°C

Volta ge on VCC from VSS......................................-0.5V to + 6V

Voltage on Any Pin from VSS.............. ..... .. -0.5V to VCC + 0.2V

Power Dissipation..............................................................1 W

Table 116. DC Parameters in Standard Voltage

Symbol Parameter Min Typ(5) Max Unit Test Conditions

VIL Input Low Voltage -0.5 0.2Vcc - 0.1 V

VIH Input High Voltage except XTAL1, RST 0.2 VCC + 0.9 VCC + 0.5 V

VIH1 Input High Voltage, XTAL1, RST 0.7 VCC VCC + 0.5 V

VOL Output Low V oltage, ports 1, 2, 3 and 4(6) 0.3

0.45

1.0

IOL = 100 μA(4)

IOL = 1.6 mA(4)

IOL = 3.5 mA(4)

VOL1 Output Low Voltage, port 0, ALE, PSEN (6) 0.3

0.45

1.0

IOL = 200 μA(4)

IOL = 3.2 mA(4)

IOL = 7.0 mA(4)

Note: Stresses at or a bov e th os e li ste d u nde r “Abs olu t e M axim um

Ratings” may cause permanent damage to the device. This

is a stress rating only and functional operation of the device

at these or any other conditions above those indicated in

the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions may affect

device reli abi li ty.

The power dissipation is based on the maximum allowable

die temperature and the thermal resistance of the package.

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Notes: 1. Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 n s (s ee Figu re 81. ), VIL =

VSS + 0.5V,

VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used (see Figure

78.).

2. I dl e I CC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5V, VIH = VCC -

0.5V; XTAL2 N.C; Port 0 = VCC; EA = RST = VSS (see Figure 79.).

3. P o wer - do w n I CC is measured with all output pins disconnected; EA = VCC, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Fig-

ure 80.). In addition, the WDT must be inactive and the POF flag must be set.

4. Cap ac it ance lo adi ng on Ports 0 and 2 ma y c au se spurious no is e p uls es to be su perimposed o n t he VOLs of ALE an d Po rt s 1

and 3. The no is e is due to ex te rnal bus capacitance discha rgin g in to th e Port 0 and Port 2 pins whe n the se pin s mak e 1 to 0

transitions during bus operation. In the worst cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed

0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary.

5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature.

6. Under steady state (non-transient) conditions, IOL must be externally limited as follows:

Maximum IOL per port pin: 10 mA

Maximum IOL per 8-bit port:

Port 0: 26 mA

Ports 1, 2, 3 and 4: 15 mA

Maximum total IOL for all output pins: 71 mA

If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater

than the listed test conditions.

VOH Output High V oltage, ports 1, 2, 3, and 4 VCC - 0.3

VCC - 0.7

VCC - 1.5

IOH = -10 μA

IOH = -30 μA

IOH = -60 μA

VCC = 3V to 5.5V

VOH1 Output High Voltage, port 0, ALE, PSEN VCC - 0.3

VCC - 0.7

VCC - 1.5

IOH = -200 μA

IOH = -3.2 mA

IOH = -7.0 mA

VCC = 5V ± 10%

RRST RST Pulldown Resistor 20 100 200 k Ω

IIL Logical 0 Input Current ports 1, 2, 3 and 4 -50 μA Vin = 0.45V

ILI Input Leakage Current ±10 μA 0.45V < Vin < VCC

ITL Logical 1 to 0 Transition Current, ports 1, 2, 3

and 4 -650 μA Vin = 2.0V

CIO Capacitance of I/O Buffer 10 pF Fc = 1 MHz

TA = 25°C

IPD

Power-down Current Industrial 75 150 μA3V < V

CC < 5.5V(3)

Power-down Current Automotiv e 100 350 μA3V < V

CC < 5.5V(3)

ICC Power Supply Current ICCOP = 0.4 Frequency (MHz) + 8

ICCIDLE = 0.2 Frequency (MHz) + 8 mA Vcc = 5.5V(1)(2)

ICCWRITE Power Supply Current on flash or EEdata write 0.8 x

Frequency

(MHz) + 15 mA VCC = 5.5V

Table 116. DC Parameters in Standard Voltage (Continued)

Symbol Parameter Min Typ(5) Max Unit Test Conditions

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Power Fail Detect at Ambiant

Temperatures

Note: 1. Threshold Voltage for PFD Release

2. Threshold Voltage for PFD Activation

Figure 78. ICC Test Condition, Active Mode

Figure 79. ICC Test Condition, Idle Mode

Figure 80. ICC Test Condition, Power-Down Mode

VPFDP(1) VPFDM(2) Hysterisis

2.5V typ 2.35V typ 100mV min.

VCC

ICC

(NC)

CLOCK

SIGNAL

VCC

All other pins are disconnected.

RST

XTAL2

XTAL1

VSS

VCC

RST EA

XTAL2

XTAL1

VSS

VCC

ICC

(NC)

VCC

All other pins are disconnected.

CLOCK

SIGNAL

RST EA

XTAL2

XTAL1

VSS

VCC

ICC

(NC)

VCC

All other pins are disconnected.

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Figure 81. Clock Signal Waveform for ICC Tests in Active and Idle Modes

DC Parameters for A/D

Converter Table 117. DC Parameters for AD Converter in Precision Conversion

Note: 1. Typicals are based on a limited number of samples and are not guaranteed.

2. For temper atur es higher than 85°C, use standard conver sion (8-bit only) and

PRS > 2.

3. VREF < VCC + 0.2V for temperatures higher than 85.

AC Parameters

Explanation of the AC

Symbols Each timing symbol has 5 char acters. The first character is always a “ T” (stands for

time). The other characters, depending on their positions, stand for the name of a signal

or the logical status of that signal. The following is a list of all the characters and what

they stand for.

Example: TAVLL = Time for Address Valid to ALE Low.

TLLPL = Time for ALE Low to PSEN Low.

TA = -40°C to +85°C; VSS = 0V; VCC = 3V to 5.5V; F = 0 to 40 MHz.

(Load Capacitance for port 0, ALE and PSEN = 60 pF; Load Capaci tance for all other

outputs = 60 pF.)

Table 118, Table 121 and Table 124 give the description of each AC symbols.

Table 119, Table 123 and Table 125 give for each range the AC parameter.

Table 120, Table 123 a nd Table 126 gi ve the frequency d erating formula of th e AC

paramete r fo r each spe ed r ang e desc ripti on . To calcu la te eac h A C sy mb ols: T ak e the x

value and use this value in the formula.

Example: TLLIV and 20 MHz, Standard clock.

x = 30 ns

T = 50 ns

TCCIV = 4T - x = 170 ns

VCC-0.5V

0.45V 0.7VCC

0.2VCC-0.1

TCLCH

TCHCL

TCLCH = TCHCL = 5ns.

Symbol Parameter Min Typ(1),(2) Max Unit Test Conditions

AVin Analog input voltage Vss- 0.2 Vref + 0.2 V

Rref Resistance between Vref and Vss 12 16 24 kΩ

Vref(3) Reference voltage 2.40 3.00 V

Cai Analog input Capacitance 60 pF During sampling

Rai Analog input Resistor 400 ΩDuring sampling

INL Integral non linearity 1 2lsb

3 Automotive

DNL Dif ferential non linearity 0.5 1 lsb

OE Offset erro r -2 2 lsb

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External Program Memory

Characteristics Table 118. Symbol Description

Table 119. AC Parameters for a Fix Clock (F = 40 MHz)

Symbol Parameter

T Oscillator clock period

TLHLL ALE pulse width

TAVLL Address Va lid to ALE

TLLAX Address Hold After ALE

TLLIV ALE to Valid Instruc tio n In

TLLPL ALE to PSEN

TPLPH PSEN Pulse Width

TPLIV PSEN t o Valid Instruction In

TPXIX Input Instruction Hold After PSEN

TPXIZ Input Instruction Float After PSEN

TAVIV Address to Valid Instruction In

TPLAZ PSEN Low to Address Float

Symbol Min Max Units

T25 ns

TLHLL 40 ns

TAVLL 10 ns

TLLAX 10 ns

TLLIV 70 ns

TLLPL 15 ns

TPLPH 55 ns

TPLIV 35 ns

TPXIX 0ns

TPXIZ 18 ns

TAVIV 85 ns

TPLAZ 10 ns

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Table 120. AC Parameters for a Variable Clock

External Program Memory Read Cycle

Symbol Type Standard

Clock X2 Clock X parameter Units

TLHLL Min 2 T - x T - x 10 ns

TAVLL Min T - x 0.5 T - x 15 ns

TLLAX Min T - x 0.5 T - x 15 ns

TLLIV Max 4 T - x 2 T - x 30 ns

TLLPL Min T - x 0.5 T - x 10 ns

TPLPH Min 3 T - x 1.5 T - x 20 ns

TPLIV Max 3 T - x 1.5 T - x 40 ns

TPXIX Min x x 0 ns

TPXIZ Max T - x 0.5 T - x 7 ns

TAVIV Max 5 T - x 2.5 T - x 40 ns

TPLAZ Max x x 10 ns

TPLIV

TPLAZ

ALE

PSEN

PORT 0

PORT 2

A0-A7A0-A7 INSTR ININSTR IN INSTR IN

ADDRESS

OR SFR-P2 ADDRESS A8-A15ADDRESS A8-A15

12 TCLCL

TAVIV

TLHLL

TAVLL

TLLIV

TLLPL

TPLPH

TPXAV

TPXIX

TPXIZ

TLLAX

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Exte rnal Data Memory

Characteristics Table 121. Symbol Description

Table 122. AC Parameters for a Fix Clock (F=40MHz)

Symbol Parameter

TRLRH RD Pulse Width

TWLWH WR Pulse Width

TRLDV RD to Valid Data In

TRHDX Data Hold After RD

TRHDZ Data Float After RD

TLLDV ALE to Valid Data In

TAVDV Ad d r e ss to Va li d D a ta In

TLLWL ALE to WR or RD

TAVWL Ad dress to WR or RD

TQVWX Dat a Valid to WR Transition

TQVWH Data set-up to WR High

TWHQX Data Hold After WR

TRLAZ RD Low to Address Float

TWHLH RD or WR High to ALE high

Symbol Min Max Units

TRLRH 130 ns

TWLWH 130 ns

TRLDV 100 ns

TRHDX 0ns

TRHDZ 30 ns

TLLDV 160 ns

TAVDV 165 ns

TLLWL 50 100 ns

TAVWL 75 ns

TQVWX 10 ns

TQVWH 160 ns

TWHQX 15 ns

TRLAZ 0ns

TWHLH 10 40 ns

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Table 123. AC Parameters for a Variable Clock

Symbol Type Standard

Clock X2 Clock X parameter Unit s

TRLRH Min 6 T - x 3 T - x 20 ns

TWLWH Min 6 T - x 3 T - x 20 ns

TRLDV Max 5 T - x 2.5 T - x 25 ns

TRHDX Min x x 0 ns

TRHDZ Max 2 T - x T - x 20 ns

TLLDV Max 8 T - x 4T -x 40 ns

TAVDV Max 9 T - x 4.5 T - x 60 ns

TLLWL Min 3 T - x 1.5 T - x 25 ns

TLLWL Max 3 T + x 1.5 T + x 25 ns

TAVWL Min 4 T - x 2 T - x 25 ns

TQVWX Min T - x 0.5 T - x 15 ns

TQVWH M in 7 T - x 3. 5 T - x 25 ns

TWHQX Min T - x 0.5 T - x 10 ns

TRLAZ Max x x 0 ns

TWHLH Min T - x 0.5 T - x 15 ns

TWHLH Max T + x 0.5 T + x 15 ns

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External Data Memory Write Cycle

External Dat a Memory Read Cycle

Serial Port Timing – Shift Register Mode

Table 124. Symbol Description (F = 40 MHz)

TQVWH

TLLAX

ALE

PSEN

PORT 0

PORT 2

A0-A7 DATA OUT

ADDRESS

OR SFR-P2

TAVWL

TLLWL

TQVWX

ADDRESS A8-A15 OR SFR P2

TWHQX

TWHLH

TWLWH

ALE

PSEN

PORT 0

PORT 2

A0-A7 DATA IN

ADDRESS

OR SFR-P2

TAVWL

TLLWL

TRLAZ

ADDRESS A8-A15 OR SFR P2

TRHDZ

TWHLH

TRLRH

TLLDV

TRHDX

TLLAX

TAVDV

Symbol Parameter

TXLXL Serial port clock cycl e time

TQVHX Output data set-up to clock rising edge

TXHQX Output data hold after clock rising edge

TXHDX Input data hold after clock rising edge

TXHDV Clock rising edge to input data valid

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Table 125. AC Parameters for a Fix Clock (F = 40 MHz)

Table 126. AC Parameters for a Variable Clock

Shif t Register Timing

Waveforms

External Clo ck Driv e

Characteristics (XTAL1) Table 127. AC Parameters

Symbol Min Max Units

TXLXL 300 ns

TQVHX 200 ns

TXHQX 30 ns

TXHDX 0ns

TXHDV 117 ns

Symbol Type Standard

Clock X2 Clock X parameter

for -M range Units

TXLXL Min 12 T 6 T ns

TQVHX Min 10 T - x 5 T - x 50 ns

TXHQX Min 2 T - x T - x 20 ns

TXHDX Min x x 0 ns

TXHDV Max 10 T - x 5 T- x 133 ns

VALID VALID VALID VALID VALIDVALID

INPU T D ATA VALID

0123456 87

ALE

CLOCK

OUTPUT DATA

WRIT E to SBUF

CLEAR RI

TXLXL

TQVXH TXHQX

TXHDV TXHDX SET TI

SET RI

INSTRUCTION

01234567

VALID

Symbol Parameter Min Max Units

TCLCL Osc illator Period 25 ns

TCHCX High Time 5 ns

TCLCX Low Time 5 ns

TCLCH Rise Time 5 ns

TCHCL Fall Time 5 ns

TCHCX/TCLCX Cyclic ratio in X2 mode 40 60 %

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External Clo ck Driv e

Waveforms

AC Testing Input/Output

Waveforms

AC in pu ts dur ing tes ting are dri ven a t VCC - 0.5 for a logic “1” and 0.45V for a logic “0” .

Timing measu rement are made at VIH min for a logic “1” and VIL max for a logic “0”.

Float Waveforms

For timing purposes as port pin is no longer floating when a 100 mV change from load

voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level

occurs. IOL/IOH ≥ ± 20 mA.

VCC-0.5V

0.45V

0.7VCC

0.2VCC-0.1

TCHCL TCLCX TCLCL

TCLCH

TCHCX

INPUT/OUTPUT 0.2 VCC + 0.9

0.2 VCC - 0.1

VCC -0.5V

0.45V

FLOAT

VOH - 0.1 V

VOL + 0.1 V

VLOAD VLOAD + 0.1

VLOAD - 0.1 V

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Clock Waveforms Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2.

This diagr am indic ates when signal s ar e clo cked i nter na lly. The ti me it take s the signal s to propaga te to the pins, howe ve r,

ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propaga-

tion also varies from outpu t to output and componen t. Typicall y though (TA=25°C fully loaded) RD and WR propagation

delays are a pproximately 50ns. The other s ignals are typically 85 ns. Propagation delays are incorpo rated in the AC

specifications.

DATA PCL OUT DATA PCL OUT DATA PCL OUT

SAMPLED SAMPLED SAMPLED

STATE4 STATE5 STATE6 STATE1 STATE2 STATE3 STATE4 STATE5

P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2

FLOAT FLOAT FLOAT

THESE SIGNALS ARE NOT ACTIVATED DURING THE

EXECUTION OF A MOVX INSTRUCTION

INDICATES ADDRESS TRANSITIONS

EXTERNAL PROGRAM MEMORY FETCH

FLOAT

DATA

SAMPLED

DPL OR Rt OUT

INDICATES DPH OR P2 SFR TO PCH TRANSITION

PCL OUT (IF PROGRAM

MEMORY IS EXTERN AL)

PCL OUT (EVEN IF PROGRAM

MEMO RY IS INTER N AL)

PCL OUT (IF PROGRA

MEMORY IS EXTERNA

OLD DATANEW DATA P0 PINS SAMPLED

P1, P2, P3 PINS SAMPLED P1, P2, P3 PI N S SA MPLED

P0 PINS SAMPL ED

RXD SAMPLED

INTERNAL

CLOCK

XTAL2

ALE

PSEN

P2 (EXT)

READ CYCLE

WRITE CYC LE

PORT OPERATION

MOV PO RT SR C

MOV DES T P0

MOV DEST PORT (P1. P2. P3)

(INC L U D ES INTO . INT1. TO T1 )

SERIAL PORT SHIFT CLOCK

TXD (MODE 0)

DATA OUT

DPL OR Rt OUT

INDICATES DPH OR P2 SFR TO PCH TRANSITION

RXD SAMPLED

180

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Flash/EEPROM Memory Table 128. Timing Symbol Definitions

Table 129. Memory AC Timing

VDD = 3V to 5.5V, TA = -40 to +85°C

Figure 82. Flash Memory – ISP Waveforms

Figure 83. Flash Memory – Internal Busy Waveforms

A/D Converter Table 130. AC Parameters for A/D Conversion

Signals Conditions

S (Hardware

condition) PSEN#,EA L Low

RRST VValid

B FBUSY flag X No Longer Valid

Symbol Parameter Min Typ Max Unit

TSVRL Input PSEN# Valid to RST Edge 50 ns

TRLSX Input PSEN# Hold after RST Edge 50 ns

TBHBL Flash/EEPROM Internal Busy

(Programming) Time 10 ms

NFCY Number of Flash/EEPROM Erase/Write

Cycles 100 000 cycles

TFDR Flash/EEPROM Data Retention Time 10 years

RST TSVRL

PSEN#1

TRLSX

FBUSY bit TBHBL

Symbol Parameter Min Typ Max Unit

TSETUP 4µs

ADC Clock Frequency 700 KHz

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Timings Test conditions: capacitive load on all pins= 60 pF.

Note: 1. Value of this parameter depends on prescacler ratio defined in bits 0,1 and 7 of SCON Register.In the above table, the ratio

used is 4. As it can be set also to 8, 16, 32, 64 or 128, the factor of TPER must be changed according to the new ratio.E.g.

2TPER-20ns (1) will be cha nge d to 4TPER-20ns(1) if the prescaler ratio equals 8.

Table 1. SPI Interfa ce Maste r AC Timing

VDD = 2.7 to 3.3 V, TA = -40 to +85°C

Symbol Parameter Min Max Unit

Slave Mode

TCHCH Clock Period 6(1) TPER

TCHCX Clock High Time 3(1) TPER

TCLCX Cl ock Low Time 3(1) TPER

TSLCH, TSLCL SS Low to Clock edge 4TPER-20ns(1) ns

TIVCL, TIVCH Input Data Va lid to Clock Edge 50 ns

TCLIX, TCHIX Input Data Hold after Clock Edge 50 ns

TCLOV, TCHOV Output Data Valid after Clock Edge 50 ns

TCLOX, TCHOX Output Data Hold Time after Clock Edge 0 ns

TCLSH, TCHSH SS High aft er Clock Edge 4TPER+20ns(1) ns

TSLOV SS Low to Output Data Valid 4TPER+20ns(1) ns

TSHOX Output Data Hold after SS High 2TPER+100ns(1) ns

TSHSL SS High to SS Low 2TPER+120ns(1)

TOLOH Outpu t Ri se tim e 100 ns

TOHOL Output Fall Ti me 100 ns

Master Mode

TCHCH Clock Period 4(1) TPER

TCHCX Clock High Time 2TPER-20ns(1) TPER

TCLCX Clock Low Time 2TPER-20ns(1) TPER

TIVCL, TIVCH Input Data Va lid to Clock Edge 50 ns

TCLIX, TCHIX Input Data Hold after Clock Edge 0 ns

TCLOV, TCHOV Output Data Valid after Clock Edge 20 ns

TCLOX, TCHOX Output Data Hold Time after Clock Edge 0 ns

TCLCH Ou tput Data Rise time 100 ns

TCHCL Output Data Fall Time 100 ns

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Waveforms Figure 84. SPI Slave Waveforms (SSCPHA= 0)

Note: 1. Not Defined but generally the MSB of the character which has just been received.

Figure 85. SPI Slave Waveforms (SSCPHA= 1)

Note: 1. Not Defined but generally the LSB of the character which has just been received.

TSLCL

TSLCH

TCHCL

TCLCH

MOSI

(input)

SCK

(SSCPOL= 0)

(input)

SCK

(SSCPOL= 1)

(input)

MISO

(output)

TCHCH

TCLCX

TCHCX

TIVCL TCLIX

TCHIX

TIVCH

TCHOV

TCLOV TCHOX

TCLOX

MSB IN BIT 6 LSB IN

SLAVE MSB OUT SLAVE LSB OUTBIT 6

TSLOV

(1)

TSHOX

TSHSL

TCHSH

TCLSH

TCHCL

TCLCH

MOSI

(input)

SCK

(SSCPOL= 0)

(input)

SCK

(SSCPOL= 1)

(input)

MISO

(output)

TCHCH

TCLCX

TCHCX

TIVCL TCLIX

TCHIX

TIVCH

TCLOV

TCHOV TCLOX

TCHOX

MSB IN BIT 6 LSB IN

SLAVE MSB OUT SLAVE LSB OUTBIT 6

TSLOV

(1)

TSHOX

TSHSL

TCHSH

TCLSH

TSLCL

TSLCH

183

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Figure 86. SPI Master Waveforms (SSCPHA= 0)

Note: 1. SS handled by software using general purpose port pin.

Figure 87. SPI Master Waveforms (SSCPHA= 1)

Note: 1. SS handled by software using general purpose port pin.

Note:

MOSI

(input)

SCK

(SSCPOL= 0)

(output)

SCK

(SSCPOL= 1)

(output)

MISO

(output)

TCHCH

TCLCX

TCHCX

TIVCL TCLIX

TCHIX

TIVCH

TCHOV

TCLOV TCHOX

TCLOX

MSB IN BIT 6 LSB IN

MSB OUTPort Data LSB OUT Port DataBIT 6

TCHCL

TCLCH

MOSI

(input)

SCK

(SSCPOL= 0)

(output)

SS(1)

(output)

SCK

(SSCPOL= 1)

(output)

MISO

(output)

TCHCH

TCLCX

TCHCX

TIVCL TCLIX

TCHIX

TIVCH

TCHOV

TCLOV TCHOX

TCLOX

MSB IN BIT 6 LSB IN

MSB OUTPort Data LSB OUT Port DataBIT 6

TCHCL

TCLCH

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Ordering Information

Table 131. Possible Order Entries

Part Number Boot

Loader Temperature

Range Quality Grade Package Packing Product Marki ng

AT89C51CC03U-7CTIM

OBSOLETE

AT89C51CC03U-RLTIM

AT89C51CC03U-SLSIM

AT89C51CC03C-7CTIM

AT89C51CC03C-RLTIM

AT89C51CC03C-SLSIM

AT89C51CC03U-RDTIM

AT89C51CC03U-S3SIM

AT89C51CC03C-RDTIM

AT89C51CC03C-S3SIM

AT89C51CC03UA-RLT UM UART -40 to +85°C Industrial & Green VQFP44 Tray 89C51CC03UA-UM

AT89C51CC03UA-S LSUM UART -40 to +85°C Indust rial & Green P LCC44 Stick 89C51C C03UA-UM

AT89C51CC03CA-RLT UM CAN -40 to +85°C Indust rial & Green VQFP44 Tray 89C51C C03CA-U M

AT89C51CC03CA-S LSUM CAN -40 to +85°C Industrial & Green PLCC44 Stick 89C51CC03CA-U M

AT89C51CC03UA-RDT UM UART -40 to +85°C I ndustrial & Green VQFP64 Tray 89C51C C03UA-U M

AT89C51CC03UA-S 3SUM UART -40 to +85°C Indust rial & Green P LCC52 Stick 89C51CC03UA-UM

AT89C51CC03CA-S 3SUM CAN -40 to +85°C Industrial & Green PLCC52 Stick 89C51CC03CA-U M

AT89C51CC03CA-RDT UM CAN -40 to +85°C Industrial & Green VQFP64 Tray 89C51CC03CA-UM

185

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Package Drawings

VQFP44

186

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4182O–CAN–09/08

STANDARD NOTES FOR PQFP/ VQFP / TQFP / DQFP

1/ CONTROLLING DIMENSIONS : INCHES

2/ ALL DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y 14.5M -

1982.

3/ "D1 AND E1" DIMENSIONS DO NOT INCLUDE MOLD PROTUSIONS.

MOLD PROTUSIONS SHALL NOT EXCEED 0.25 mm (0.010 INCH).

THE TOP PACKAGE BODY SIZE MAY BE SMALLER THAN THE BOTTOM

PACKAGE BODY SIZE BY AS MUCH AS 0.15 mm.

4/ DATUM PLANE "H" LOCATED AT MOLD PARTING LINE AND

COINCIDENT WITH LEAD, WHERE LEAD EXITS PLASTIC BODY AT

BOTTOM OF PARTING LINE.

5/ DATUM "A" AND "D" TO BE DETERMINED AT DATUM PLANE H.

6/ DIMENSION " f " DOES NOT INCLUDE DAMBAR PROTUSION ALLOWABLE

DAMBAR PROTUSION SHALL BE 0.08mm/.003" TOTAL IN EXCESS OF THE

" f " DIMENSION AT MAXIMUM MATERIAL CONDITION .

DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.

187

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PLCC44

188

AT89C51CC03

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STANDARD NOTES FOR PLCC

1/ CONTROLLING DIMENSIONS : INCHES

2/ DIMENSIONING AND TOLERANCING PER ANSI Y 14.5M - 1982.

3/ "D" AND "E1" DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTUSIONS

MOLD FLASH OR PROTUSIONS SHALL NOT EXCEED 0.20 mm (.008 INCH) PER

SIDE.

189

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VQFP64

190

AT89C51CC03

4182O–CAN–09/08

STANDARD NOTES FOR PQFP/ VQFP / TQFP / DQFP

1/ CONTROLLING DIMENSIONS : INCHES

2/ ALL DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y 14.5M -

1982.

3/ "D1 AND E1" DIMENSIONS DO NOT INCLUDE MOLD PROTUSIONS.

MOLD PROTUSIONS SHALL NOT EXCEED 0.25 mm (0.010 INCH).

THE TOP PACKAGE BODY SIZE MAY BE SMALLER THAN THE BOTTOM

PACKAGE BODY SIZE BY AS MUCH AS 0.15 mm.

4/ DATUM PLANE "H" LOCATED AT MOLD PARTING LINE AND

COINCIDENT WITH LEAD, WHERE LEAD EXITS PLASTIC BODY AT

BOTTOM OF PARTING LINE.

5/ DATUM "A" AND "D" TO BE DETERMINED AT DATUM PLANE H.

6/ DIMENSION " f " DOES NOT INCLUDE DAMBAR PROTUSION ALLOWABLE

DAMBAR PROTUSION SHALL BE 0.08mm/.003" TOTAL IN EXCESS OF THE

" f " DIMENSION AT MAXIMUM MATERIAL CONDITION .

DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.

191

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PLCC52

192

AT89C51CC03

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Datasheet Change

Log

Changes from 4182B -

09/03 to 4182C 12/03 1. Added Icc Idle, IPD, and Rrst value in “DC Parameters for A/D Converter” on

page 171.

Changes from 4182C -

12/03 to 4182D 01/04 1. Updated SFR Table.

– SFR : SPSTR changed to SPSCR

– CANSTMH changed to CANSTMPH p15

– CANSTML changed to CANSTMPL p15

– CANCONC changed to CANCONCH p15

2. AC/DC - p.160 IccOP and ICCIdle formulas changed

3. Changed maximum frequency to 60MHz in internal code execution.

Changes from 4182D -

01/04 to 4182E 05/04 1. Added Automotive temperature range.

Changes from 4182E -

05/04 to 4182F 10/04 1. Various minor corrections throughout the document.

Changes from 4182F -

10/04 to 4182G 03/05 1. Change to Watchdog formula, Section “Watchdog Programming”, page 83.

Changes from 4182G

03/05 to 4182H 04/05 1. Refined automotive temperature values.

Changes from 4182H

04/05 to 4182I 06/05 1. Added Green product ordering information.

2. Clarification in W aveform diagram, page 20.

Changes from 4182I

06/05 to 4182J 03/06 1. Additional part numbers added to ordering information.

Changes from 4182J

03/06 to 4182K 04/06 1. Minor corrections throughout the document to incorrect values.

Changes from 4182K

04/06 to 4182L 06/07 1. Modification to ordering information, removed Automotive product versions.

Changes from 4182L

06/07 to 4182M 02/08 1. Modification to ordering information, removed non green product versions.

Changes from 4182M

02/087 to 4182N 03/08 1. Removed CA-BGA package offering from ordering information.

2. Updated package drawings.

193

AT89C51CC03

4182O–CAN–09/08

Changes from 4182N

03/08 to 4182O 09/08 1. Correction to SPDT register address Table 94 on page 139.

i4182O–CAN–09/08

AT89C51CC03

Table of Content s

Features ................................................................................................. 1

Description ............................................................................................ 2

Block Diagram ...................................................................................... 2

Pin Configuration ................................................................................. 3

I/O Configurations................................................................................................. 7

Port 1, Port 3 and Port 4....................................................................................... 7

Port 0 and Port 2................................................................................................... 8

Read-Modify-Write Instructions ............................................................................ 9

Quasi-Bidirectional Port Operation..................................................................... 10

SFR Mapping ....................................................................................... 11

Clock .................................................................................................... 17

Description.......................................................................................................... 17

Registers............................................................................................................. 20

Data Memory ....................................................................................... 22

Internal Space..................................................................................................... 23

External Spa ce ............ ....... ...... ....... ...... ...... ....... ...... .................... ...... ....... ...... ... 24

Dual Data Pointer ............................................................................................... 26

Registers............................................................................................................. 27

Power Monitor ..................................................................................... 29

Description.......................................................................................................... 29

Reset .................................................................................................... 31

Introduction......................................................................................................... 31

Reset Input ..... ....... ...... ....... ...... ....... ...... ................... ....... ...... ....... ...... ................ 31

Reset Output ......... ...... .................... ...... ...... ....... ...... .................... ...... ....... ...... ....3 2

Power Management ............................................................................ 33

Introduction......................................................................................................... 33

Idle Mode............................................................................................................ 33

Power-Down Mode............................................................................................. 33

Registers............................................................................................................. 36

EEPROM Data Memory ...................................................................... 37

Write Data in the Column Latches...................................................................... 37

Programming...................................................................................................... 37

Read Data........................................................................................................... 37

Examples............................................................................................................ 38

4182O–CAN–09/08

AT89C51CC03

Registers............................................................................................................. 39

Program/Code Memory ................. ..... .............. ..... .... ..... .............. ..... . 40

External Code Memory Access .......................................................................... 41

Flash Memory Architecture................................................................................. 42

Overview of FM0 Operations.............................................................................. 46

Operation Cross Memory Access ..................................................... 55

Sharing Instructions ........................................................................... 56

In-System Programming (ISP) ................ .... ..... ..... .............. .... ..... ..... . 58

Flash Programming and Erasure........................................................................ 58

Boot Process ...................................................................................................... 58

Application Programming Interface..................................................................... 60

XROW Bytes....................................................................................................... 60

Hardware Security Byte...................................................................................... 61

Serial I/O Port ..................................................................................... 62

Framing Error Detection .................................................................................... 62

Automatic Address Recognition.......................................................................... 63

Given Address................................................................................................... 64

Broadcast Address ............................................................................................ 64

Registers............................................................................................................. 65

Timers/Counters ................................................................................. 68

Timer/Counter Operations.................................................................................. 68

Timer 0................................................................................................................ 68

Timer 1................................................................................................................ 71

Interrupt .............................................................................................................. 72

Registers............................................................................................................. 72

Timer 2 ................................................................................................. 76

Auto-Reload Mode............................................................................................. 76

Programmable Clock-Output.............................................................................. 77

Registers............................................................................................................. 78

Watchdog Timer ................................................................................. 81

Watchdog Programming..................................................................................... 82

Watchdog Timer During Power-down Mode and Idle......................................... 83

CAN Controller .................................................................................... 85

CAN Protocol...................................................................................................... 85

CAN Controller Description................................................................................. 89

CAN Controller Mailbox and Registers Organization.......................................... 90

CAN Controller Management.............................................................................. 92

iii 4182O–CAN–09/08

AT89C51CC03

IT CAN Management.......................................................................................... 94

Bit Timing and Baud Rate ...................................................................................96

Fault Confinement .............................................................................................. 98

Acceptance Filter................................................................................................ 99

Data and Remote Frame.................................................................................. 100

Time Trigger Communication (TTC) and Message Stamping.......................... 101

CAN Autobaud and Listening Mode ................................................................. 102

Routines Examples........................................................................................... 102

CAN SFR’s ....................................................................................................... 105

Registers........................................................................................................... 106

Serial Port Interface (SPI) ................................................................ 129

Features............................................................................................................ 129

Signal Description............................................................................................. 129

Functional Description ...................................................................................... 131

Programmable Counter Array (PCA) .............. ..... .... ..... ..... ............. 141

PCA Timer........................................................................................................ 141

PCA Modules.................................................................................................... 142

PCA Interrupt.................................................................................................... 143

PCA Capture Mode........................................................................................... 143

16-bit Software Timer Mode ............................................................................. 144

High Speed Output Mode................................................................................. 145

Pulse Width Modulator Mode............................................................................ 145

PCA WatchDog Timer ...................................................................................... 146

PCA Registers.................................................................................................. 147

Analog-to-Digital Converter (ADC) ................................................. 152

Features............................................................................................................ 152

ADC Port1 I/O Functions.................................................................................. 152

ADC Converter Operation................................................................................. 154

Voltage Conversion .......................................................................................... 154

Clock Selection................................................................................................. 154

ADC Standby Mode.......................................................................................... 155

IT ADC Management........................................................................................ 155

Routines examples........................................................................................... 155

Registers........................................................................................................... 157

Interrupt System ............................................................................... 160

Introduction....................................................................................................... 160

Registers........................................................................................................... 162

Electrical Characteristics ................................................................. 168

Absolute Maximum Ratings .............................................................................168

ICCOP Test Conditions .................................................................................... 168

DC Parameters for Standard Voltage ...............................................................168

4182O–CAN–09/08

AT89C51CC03

DC Parameters for A/D Converter.................................................................... 171

AC Parameters .................................................................................................171

Timings............................................................................................................. 181

Ordering Information ........................................................................ 184

Package Drawings ............................................................................ 185

VQFP44............................................................................................................ 185

PLCC44............................................................................................................ 187

VQFP64............................................................................................................ 189

PLCC52............................................................................................................ 191

Datasheet Change Log .................. ..... ..... .... .............. ..... ..... .... ......... 192

Changes from 4182B - 09/03 to 4182C 12/03.................................................. 192

Changes from 4182C - 12/03 to 4182D 01/04.................................................. 192

Changes from 4182D - 01/04 to 4182E 05/04.................................................. 192

Changes from 4182E -05/04 to 4182F 10/04 ................................................... 192

Changes from 4182F - 10/04 to 4182G 03/05.................................................. 192

Changes from 4182G 03/05 to 4182H 04/05.................................................... 192

Changes from 4182H 04/05 to 4182I 06/05...................................................... 192

Changes from 4182I 06/05 to 4182J 03/06 ...................................................... 192

Changes from 4182J 03/06 to 4182K 04/06..................................................... 192

Changes from 4182K 04/06 to 4182L 06/07..................................................... 192

Changes from 4182L 06/07 to 4182M 02/08.................................................... 192

Changes from 4182M 02/087 to 4182N 03/08.................................................. 192

Changes from 4182N 03/08 to 4182O 09/08.................................................... 193

Table of Contents .................................................................................. i

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4182O–CAN–09/08

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