DS90LV001TMX/NOPB - NATIONAL SEMICONDUCTOR

DS90LV001

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SNLS067E –JANUARY 2001–REVISED APRIL 2013

DS90LV001 800 Mbps LVDS Buffer

Check for Samples: DS90LV001

1FEATURES DESCRIPTION

The DS90LV001 LVDS-LVDS Buffer takes an LVDS

2• Single +3.3 V Supply input signal and provides an LVDS output signal. In

• LVDS Receiver Inputs Accept LVPECL Signals many large systems, signals are distributed across

• TRI-STATE Outputs backplanes, and one of the limiting factors for system

speed is the "stub length" or the distance between

• Receiver Input Threshold < ±100 mV the transmission line and the unterminated receivers

• Fast Propagation Delay of 1.4 ns (Typ) on individual cards. Although it is generally

• Low Jitter 800 Mbps Fully Differential Data recognized that this distance should be as short as

Path possible to maximize system performance, real-world

packaging concerns often make it difficult to make the

• 100 ps (Typ) of pk-pk Jitter with PRBS = 223−1stubs as short as the designer would like.

Data Pattern at 800 Mbps The DS90LV001, available in the WSON package,

• Compatible with ANSI/TIA/EIA-644-A LVDS will allow the receiver to be placed very close to the

Standard main transmission line, thus improving system

• 8 pin SOIC and Space Saving (70%) WSON performance.

Package A wide input dynamic range will allow the

• Industrial Temperature Range DS90LV001 to receive differential signals from

LVPECL as well as LVDS sources. This will allow the

device to also fill the role of an LVPECL-LVDS

translator.

An output enable pin is provided, which allows the

user to place the LVDS output in TRI-STATE.

The DS90LV001 is offered in two package options,

an 8 pin WSON and SOIC.

Connection Diagram

Figure 1. Top View

See Package Number D (R-PDSO-G8), NGK0008A

Block Diagram

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

DS90LV001

SNLS067E –JANUARY 2001–REVISED APRIL 2013

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Absolute Maximum Ratings(1)

Supply Voltage (VCC)−0.3V to +4V

LVCMOS/LVTTL Input Voltage (EN) −0.3V to (VCC + 0.3V)

LVDS Receiver Input Voltage (IN+, IN−)−0.3V to +4V

LVDS Driver Output Voltage (OUT+, OUT−)−0.3V to +4V

LVDS Output Short Circuit Current Continuous

Junction Temperature +150°C

Storage Temperature Range −65°C to +150°C

Lead Temperature Range Soldering (4 sec.) +260°C

D Package 726 mW

Derate D Package 5.8 mW/°C above +25°C

Maximum Package Power Dissipation at

25°C NGK Package 2.44 W

Derate NGK Package 19.49 mW/°C above +25°C

(HBM, 1.5kΩ, 100pF) ≥2.5kV

ESD Ratings (EIAJ, 0Ω, 200pF) ≥250V

(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply

that the device should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.

Recommended Operating Conditions Min Typ Max Units

Supply Voltage (VCC) 3.0 3.3 3.6 V

Receiver Input Voltage 0 VCC V

Operating Free Air Temperature −40 +25 +85 °C

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Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified(1)(2)

Symbol Parameter Conditions Min Typ Max Units

LVCMOS/LVTTL DC SPECIFICATIONS (EN)

VIH High Level Input Voltage 2.0 VCC V

VIL Low Level Input Voltage GND 0.8 V

IIH High Level Input Current VIN = 3.6V or 2.0V, VCC = 3.6V +7 +20 μA

IIL Low Level Input Current VIN = GND or 0.8V, VCC = 3.6V ±1 ±10 μA

VCL Input Clamp Voltage ICL =−18 mA −0.6 −1.5 V

LVDS OUTPUT DC SPECIFICATIONS (OUT)

VOD Differential Output Voltage RL= 100Ω250 325 450 mV

Figure 2 and Figure 3

ΔVOD Change in Magnitude of VOD for Complimentary 20 mV

Output States

VOS Offset Voltage RL= 100Ω1.080 1.19 1.375 V

Figure 2

ΔVOS Change in Magnitude of VOS for Complimentary 20 mV

Output States

IOZ Output TRI-STATE Current EN = 0V, VOUT = VCC or GND ±1 ±10 μA

IOFF Power-Off Leakage Current VCC = 0V, VOUT = 3.6V or GND ±1 ±10 μA

IOS Output Short Circuit Current(3) EN = VCC, VOUT+ and VOUT−= 0V −16 −24 mA

IOSD Differential Output Short Circuit Current(3) EN = VCC, VOD = 0V −7−12 mA

LVDS RECEIVER DC SPECIFICATIONS (IN)

VTH Differential Input High Threshold VCM = +0.05V, +1.2V or +3.25V 0 +100 mV

VTL Differential Input Low Threshold −100 0 mV

VCMR Common Mode Voltage Range VID = 100mV, VCC = 3.3V 0.05 3.25 V

IIN Input Current VIN = +3.0V VCC = 3.6V or 0V ±1 ±10 μA

VIN = 0V ±1 ±10 μA

ΔIIN Change in Magnitude of IIN VIN = +3.0V VCC = 3.6V or 0V 1 6 μA

VIN = 0V 1 6 μA

SUPPLY CURRENT

ICCD Total Supply Current EN = VCC, RL= 100Ω, CL= 5 pF 47 70 mA

ICCZ TRI-STATE Supply Current EN = 0V 22 35 mA

(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground

except VOD and ΔVOD.

(2) All typical are given for VCC = +3.3V and TA= +25°C, unless otherwise stated.

(3) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.

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AC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified(1)

Symbol Parameter Conditions Min Typ Max Units

tPHLD Differential Propagation Delay High to Low RL= 100Ω, CL= 5pF 1.0 1.4 2.0 ns

Figure 4 and Figure 5

tPLHD Differential Propagation Delay Low to High 1.0 1.4 2.0 ns

tSKD1 Pulse Skew |tPLHD −tPHLD|(2)(3) 20 200 ps

tSKD3 Part to Part Skew(2)(4) 0 60 ps

tSKD4 Part to Part Skew(2)(5) 400 ps

tLHT Rise Time(2) RL= 100Ω, CL= 5pF 200 320 450 ps

Figure 4 and Figure 6

tHLT Fall Time(2) 200 310 450 ps

tPHZ Disable Time (Active High to Z) RL= 100Ω, CL= 5pF 3 25 ns

Figure 7 and Figure 8

tPLZ Disable Time (Active Low to Z) 3 25 ns

tPZH Enable Time (Z to Active High) 25 45 ns

tPZL Enable Time (Z to Active Low) 25 45 ns

tDJ LVDS Data Jitter, Deterministic (Peak-to-Peak)(6) VID = 300mV; PRBS = 223 −1 data; VCM 100 135 ps

= 1.2V at 800Mbps (NRZ)

tRJ LVDS Clock Jitter, Random(6) VID = 300mV; VCM = 1.2V at 400MHz 2.2 3.5 ps

clock

(1) All typical are given for VCC = +3.3V and TA= +25°C, unless otherwise stated.

(2) The parameters are ensured by design. The limits are based on statistical analysis of the device performance over the PVT (process,

voltage and temperature) range.

(3) tSKD1, |tPLHD −tPHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative

going edge of the same channel.

(4) tSKD3, Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This

specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range.

(5) tSKD4, Part to Part Skew, is the differential channel-to- channel skew of any event between devices. This specification applies to devices

over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max −Min|

differential propagation delay.

(6) The parameters are ensured by design. The limits are based on statistical analysis of the device performance over the PVT range with

the following test equipment setup: HP8133A (pattern pulse generator), 5 feet of RG142B cable with DUT test board and HP83480A

(digital scope mainframe) with HP83484A (50GHz scope module). The HP8133A with RG142B cable exhibit a tDJ = 21ps and tRJ =

1.8ps.

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DC Test Circuits

Figure 2. Differential Driver DC Test Circuit

Figure 3. Differential Driver Full Load DC Test Circuit

AC Test Circuits and Timing Diagrams

Figure 4. LVDS Output Load

Figure 5. Propagation Delay Low-to-High and High-to-Low

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Figure 6. LVDS Output Transition Time

Figure 7. TRI-STATE Delay Test Circuit

Figure 8. Output active to TRI-STATE and TRI-STATE to active output time

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DS90LV001 Pin Descriptions (SOIC and WSON)

Pin Name Pin # Input/Output Description

GND 1 P Ground

IN −2 I Inverting receiver LVDS input pin

IN+ 3 I Non-inverting receiver LVDS input pin

NC 4 No Connect

VCC 5 P Power Supply, 3.3V ± 0.3V.

OUT+ 6 O Non-inverting driver LVDS output pin

OUT - 7 O Inverting driver LVDS output pin

EN 8 I Enable pin. When EN is LOW, the driver is disabled and the LVDS outputs are in TRI-

STATE. When EN is HIGH, the driver is enabled. LVCMOS/LVTTL levels.

DAP NA NA Die Attach Pad or DAP (WSON Package only). The DAP is NOT connected to the

device GND nor any other pin. It is still recommended to connect the DAP to a GND

plane of a PCB for enhenced heat dissipation.

TYPICAL APPLICATIONS

Backplane Stub-Hider Application

Cable Repeater Application

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APPLICATION INFORMATION

MODE OF OPERATION

The DS90LV001 can be used as a "stub-hider." In many systems, signals are distributed across backplanes, and

one of the limiting factors for system speed is the "stub length" or the distance between the transmission line and

the unterminated receivers on the individual cards. Although it is generally recognized that this distance should

be as short as possible to maximize system performance, real-world packaging concerns and PCB designs often

make it difficult to make the stubs as short as the designer would like. The DS90LV001, available in the WSON

package, can improve system performance by allowing the receiver to be placed very close to the main

transmission line either on the backplane itself or very close to the connector on the card. Longer traces to the

LVDS receiver may be placed after the DS90LV001. This very small WSON package is a 75% space savings

over the SOIC package.

INPUT FAILSAFE

The receiver inputs of the DS90LV001 do not have internal failsafe biasing. For point-to-point and multidrop

applications with a single source, failsafe biasing may not be required. When the driver is off, the link is in-active.

If failsafe biasing is required, this can be accomplished with external high value resistors. Using the equations in

the LVDS Owner"s Manual Chapter 4, the IN+ should be pull to VCC (3.3V) with 20kΩand the IN−should be pull

to GND with 12kΩ. This provides a slight positive differential bias, and sets a known HIGH state on the link with a

minimum amount of distortion.

PCB LAYOUT AND POWER SYSTEM BYPASS

Circuit board layout and stack-up for the DS90LV001 should be designed to provide noise-free power to the

device. Good layout practice also will separate high frequency or high level inputs and outputs to minimize

unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by

using thin dielectrics (4 to 10 mils) for power/ground sandwiches. This increases the intrinsic capacitance of the

PCB power system which improves power supply filtering, especially at high frequencies, and makes the value

and placement of external bypass capacitors less critical. External bypass capacitors should include both RF

ceramic and tantalum electrolytic types. RF capacitors may use values in the range 0.01 µF to 0.1 µF. Tantalum

capacitors may be in the range 2.2 µF to 10 µF. Voltage rating for tantalum capacitors should be at least 5X the

power supply voltage being used. It is recommended practice to use two vias at each power pin of the

DS90LV001 as well as all RF bypass capacitor terminals. Dual vias reduce the interconnect inductance by up to

half, thereby reducing interconnect inductance and extending the effective frequency range of the bypass

components.

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The outer layers of the PCB may be flooded with additional ground plane. These planes will improve shielding

and isolation as well as increase the intrinsic capacitance of the power supply plane system. Naturally, to be

effective, these planes must be tied to the ground supply plane at frequent intervals with vias. Frequent via

placement also improves signal integrity on signal transmission lines by providing short paths for image currents

which reduces signal distortion. The planes should be pulled back from all transmission lines and component

mounting pads a distance equal to the width of the widest transmission line or the thickness of the dielectric

separating the transmission line from the internal power or ground plane(s) whichever is greater. Doing so

minimizes effects on transmission line impedances and reduces unwanted parasitic capacitances at component

mounting pads.

There are more common practices which should be followed when designing PCBs for LVDS signaling. Please

see application note AN-1108 for guidelines. In addition, application note AN-1187 has additional information

specifically related to WSON recommendations.

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Typical Performance Curves

Output High Voltage vs Output Low Voltage vs

Power Supply Voltage Power Supply Voltage

Figure 9. Figure 10.

Output Short Circuit Current vs Differential Output Short Circuit Current vs

Power Supply Voltage Power Supply Voltage

Figure 11. Figure 12.

Output TRI-STATE Current vs Offset Voltage vs

Power Supply Voltage Power Supply Voltage

Figure 13. Figure 14.

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Typical Performance Curves (continued)

Differential Output Voltage Differential Output Voltage

vs Power Supply Voltage vs Load Resistor

Figure 15. Figure 16.

Power Supply Current Power Supply Current vs

vs Frequency Power Supply Voltage

Figure 17. Figure 18.

TRI-STATE Power Supply Current vs Differential Transition Voltage vs

Power Supply Voltage Power Supply Voltage

Figure 19. Figure 20.

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Typical Performance Curves (continued)

Differential Propagation Delay vs Differential Propagation Delay vs

Power Supply Voltage Ambient Temperature

Figure 21. Figure 22.

Differential Skew vs Differential Skew vs

Power Supply Voltage Ambient Temperature

Figure 23. Figure 24.

Transition Time vs Transition Time vs

Power Supply Voltage Ambient Temperature

Figure 25. Figure 26.

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Typical Performance Curves (continued)

Differential Propagation Delay vs Differential Propagation Delay vs

Differential Input Voltage Common-Mode Voltage

Figure 27. Figure 28.

Peak-to-Peak Output Jitter at VCM = 0.4V vs Peak-to-Peak Output Jitter at VCM = 2.9V vs

Differential Input Voltage Differential Input Voltage

Figure 29. Figure 30.

Peak-to-Peak Output Jitter at VCM = 1.2V vs Peak-to-Peak Output Jitter at VCM = 1.2V vs

Differential Input Voltage Ambient Temperature

Figure 31. Figure 32.

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REVISION HISTORY

Changes from Revision D (April 2013) to Revision E Page

• Changed layout of National Data Sheet to TI format .......................................................................................................... 13

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PACKAGE OPTION ADDENDUM

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Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

DS90LV001TLD NRND WSON NGK 8 1000 Non-RoHS &

Non-Green Call TI Call TI -40 to 85 001

DS90LV001TLD/NOPB ACTIVE WSON NGK 8 1000 RoHS & Green SN Level-3-260C-168 HR -40 to 85 001

DS90LV001TLDX/NOPB ACTIVE WSON NGK 8 4500 RoHS & Green SN Level-3-260C-168 HR -40 to 85 001

DS90LV001TM NRND SOIC D 8 95 Non-RoHS &

Non-Green Call TI Call TI -40 to 85 LV001

DS90LV001TM/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LV001

DS90LV001TMX NRND SOIC D 8 2500 Non-RoHS &

Non-Green Call TI Call TI -40 to 85 LV001

DS90LV001TMX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LV001

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

DS90LV001TLD WSON NGK 8 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1

DS90LV001TLD/NOPB WSON NGK 8 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1

DS90LV001TLDX/NOPB WSON NGK 8 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1

DS90LV001TMX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

DS90LV001TMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 29-Sep-2019

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

DS90LV001TLD WSON NGK 8 1000 210.0 185.0 35.0

DS90LV001TLD/NOPB WSON NGK 8 1000 210.0 185.0 35.0

DS90LV001TLDX/NOPB WSON NGK 8 4500 367.0 367.0 35.0

DS90LV001TMX SOIC D 8 2500 367.0 367.0 35.0

DS90LV001TMX/NOPB SOIC D 8 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 29-Sep-2019

Pack Materials-Page 2

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PACKAGE OUTLINE

.228-.244 TYP

[5.80-6.19]

.069 MAX

[1.75]

6X .050

[1.27]

8X .012-.020

[0.31-0.51]

.150

[3.81]

.005-.010 TYP

[0.13-0.25]

0 - 8 .004-.010

[0.11-0.25]

.010

[0.25]

.016-.050

[0.41-1.27]

4X (0 -15 )

.189-.197

[4.81-5.00]

NOTE 3

B .150-.157

[3.81-3.98]

NOTE 4

4X (0 -15 )

(.041)

[1.04]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

.010 [0.25] C A B

PIN 1 ID AREA

SEATING PLANE

.004 [0.1] C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 2.800

www.ti.com

EXAMPLE BOARD LAYOUT

.0028 MAX

[0.07]

ALL AROUND

.0028 MIN

[0.07]

ALL AROUND

(.213)

[5.4]

6X (.050 )

[1.27]

8X (.061 )

[1.55]

8X (.024)

[0.6]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

EXPOSED

METAL

OPENING

SOLDER MASK METAL UNDER

SOLDER MASK

DEFINED

EXPOSED

METAL

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SYMM

SEE

DETAILS

SYMM

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EXAMPLE STENCIL DESIGN

8X (.061 )

[1.55]

8X (.024)

[0.6]

6X (.050 )

[1.27] (.213)

[5.4]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

SYMM

MECHANICAL DATA

NGK0008A

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LDA08A (Rev C)

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