DS90LV001
SNLS067E –JANUARY 2001–REVISED APRIL 2013
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AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified(1)
Symbol Parameter Conditions Min Typ Max Units
tPHLD Differential Propagation Delay High to Low RL= 100Ω, CL= 5pF 1.0 1.4 2.0 ns
Figure 4 and Figure 5
tPLHD Differential Propagation Delay Low to High 1.0 1.4 2.0 ns
tSKD1 Pulse Skew |tPLHD −tPHLD|(2)(3) 20 200 ps
tSKD3 Part to Part Skew(2)(4) 0 60 ps
tSKD4 Part to Part Skew(2)(5) 400 ps
tLHT Rise Time(2) RL= 100Ω, CL= 5pF 200 320 450 ps
Figure 4 and Figure 6
tHLT Fall Time(2) 200 310 450 ps
tPHZ Disable Time (Active High to Z) RL= 100Ω, CL= 5pF 3 25 ns
Figure 7 and Figure 8
tPLZ Disable Time (Active Low to Z) 3 25 ns
tPZH Enable Time (Z to Active High) 25 45 ns
tPZL Enable Time (Z to Active Low) 25 45 ns
tDJ LVDS Data Jitter, Deterministic (Peak-to-Peak)(6) VID = 300mV; PRBS = 223 −1 data; VCM 100 135 ps
= 1.2V at 800Mbps (NRZ)
tRJ LVDS Clock Jitter, Random(6) VID = 300mV; VCM = 1.2V at 400MHz 2.2 3.5 ps
clock
(1) All typical are given for VCC = +3.3V and TA= +25°C, unless otherwise stated.
(2) The parameters are ensured by design. The limits are based on statistical analysis of the device performance over the PVT (process,
voltage and temperature) range.
(3) tSKD1, |tPLHD −tPHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative
going edge of the same channel.
(4) tSKD3, Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This
specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
(5) tSKD4, Part to Part Skew, is the differential channel-to- channel skew of any event between devices. This specification applies to devices
over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max −Min|
differential propagation delay.
(6) The parameters are ensured by design. The limits are based on statistical analysis of the device performance over the PVT range with
the following test equipment setup: HP8133A (pattern pulse generator), 5 feet of RG142B cable with DUT test board and HP83480A
(digital scope mainframe) with HP83484A (50GHz scope module). The HP8133A with RG142B cable exhibit a tDJ = 21ps and tRJ =
1.8ps.
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