IBM043610QLAB
IBM041810QLAB
32K X 36 & 64K X 18 SRAM Preliminary
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 10 of 22
03H9038
SA14-4657-05
Revised 5/97
AC Characteristics (TA=0 to +70°C, VDD=3.3 −5% + 10% V)
Parameter Symbol 4H
64K X 18 4H
32K X 36 5F567
Units Note
s
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
K Clock Cycle Time tKHKH 4.5 — 4.5 — 5.0 — 5.0 — 6.0 — 7.0 — ns
K Clock High Pulse Width tKHKL 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns
K Clock Low Pulse Width tKLKH 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns
C Clock Cycle Time tCHCH 5.0 — 5.0 — 5.0 — 5.0 — 6.0 — 7.0 — ns
C Clock High Pulse Width tCHCL 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns
C Clock Low Pulse Width tCLCH 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns
K to C Clock Delay tKHCH 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns
C to K Clock Delay tCHKH 1.0 — 1.0 — 1.0 — 1.0 — 1.0 — 1.0 — ns
K Clock to Output Valid tKHQV — 5.9 — 6.4 — 6.8 — 7.0 — 7.5 — 8.0 ns 1
Data Out Hold Time from K Clock tKHQX 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns 1, 3
K Clock High to Output Active tKHQX4 2.5 — 2.5 — 2.5 — 2.5 — 3.0 — 3.0 — ns 1, 3
C Clock to Output Valid tCHQV — 2.6 — 2.7 — 3.0 — 3.0 — 3.0 — 3.5 ns 1, 4
Data Out Hold Time from C clock tCHQX 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns 1, 4
C Clock High to Output High Z tCHQZ — 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — 3.5 ns 1
C Clock High to Output Active tCHQX2 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns 1, 4
Address Setup Time tAVKH 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns 5
Address Hold Time tKHAX 1.0 — 1.0 — 1.0 — 1.0 — 1.0 — 1.0 — ns
Synchronous Select Setup Time tSVKH 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns 5
Synchronous Select Hold Time tKHSX 1.0 — 1.0 — 1.0 — 1.0 — 1.0 — 1.0 — ns
Write Enables Setup Time tWVKH 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns 5
Write Enables Hold Time tKHWX 1.0 — 1.0 — 1.0 — 1.0 — 1.0 — 1.0 — ns
Data In Setup Time tDVKH 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns 5
Data In Hold Time tKHDX 0.8 — 1.0 — 1.0 — 1.0 — 1.0 — 1.0 — ns
Output Enable to Output Valid tGLQV — 2.5 — 2.5 — 2.5 — 2.5 — 3.0 — 3.5 ns 1
Output Enable to Low Z tGLQX 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns 1
Output Enable to High Z tGHQZ — 2.3 — 2.3 — 2.5 — 2.5 — 3.0 — 3.5 ns 1
Output Enable Set-up Time tGHKH 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns 1, 2
Output Enable Hold TIme tKHGX 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns 1, 2
Sleep Mode Recovery TIme tZZR 5—5—5—5—6—7—ns
Sleep Mode Enable TIme tZZE —5—5—5—5—6—7ns
1. See AC Test Loading figure on page 9.
2. Output Driver Impedance update specifications for G induced updates. Write and Deselect cycles will also induce Output Driver
updates during High Z.
3. tKHQX and tKHQX4 are used in instances where tKHCH = Min. and, therefore, the C Clock may not gate the output data.
4. tCHQV, tCHQX and tCHQX2 are used in instances where the output data is gated by the C Clock.
5. 4H sort Setup times tested/verified at 5ns cycle time.