FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII 3.3 Volt Synchronous x 72 First-In/First-Out Queue Memory Configuration Device Memory Configuration Device 65,536 x 72 32,768 x 72 16,384 x 72 8,192 x 72 FQV72100 FQV7290 FQV7280 FQV7270 4,096 x 72 2,048 x 72 1,024 x 72 512 x 72 FQV7260 FQV7250 FQV7240 FQV7230 Key Features * * * * * * * * * * * * * * * * * * * * * * * Industry leading First-In/First-Out Queues (up to 166 MHz) Write cycle time of 6.0ns independent of Read cycle time (Data Setup time = 2.0ns) Read cycle time of 6.0ns independent of Write cycle time (Data Access time = 4.0ns) User selectable input and output bus-sizing Big Endian/Little Endian user selectable byte representation 3.3V power supply 5V input tolerant on all control and data input pins 5V output tolerant on all flags and data output pins Master Reset clears all previously programmed configurations including Write and Read pointers Partial Reset clears Write and Read pointers but maintains all previously programmed configurations First Word Fall Through (FWFT) and Standard Timing modes Presets for eight different Almost Full and Almost Empty offset values Parallel/Serial programming of PRAF and PRAE offset values Programmable 8-bit or 9-bit parallel programming modes for offset values Full, Empty, Almost Full, Almost Empty, and Half Full indicators PRAF and PRAE operate in either synchronous or asynchronous modes Asynchronous output enable tri-state data output drivers Synchronous Read Chip Select Data retransmission with programmable zero or normal latency modes Boundary Scan (JTAG) Available package: 256 - pin Fine Pitch Ball Grid Array (BGA) (0C to 70C) Commercial operating temperature available for cycle time of 6.0ns and above (-40C to 85C) Industrial operating temperature available for cycle time of 7.5ns and above Product Description HBA's FlexQTM III offers industry leading FIFO queuing bandwidth (up to 12.0 Gbps) with a wide range of memory configurations (from 512 x 72 to 65,536 x 72). System designer has full flexibility of implementing deeper and wider queues using FWFT mode and width expansion features. Full, Empty, and Half-Full indicators allow easy handshaking between transmitters and receivers. User programmable Almost Full and Almost Empty (Parallel/Serial) indicators allow implementation of virtual queue depths. 5V tolerant on all input and output pins allow easy interfacing with devices operating at higher voltage levels. Asynchronous Output Enable pin configures the tri-state data output drivers. In addition, synchronous read chip select is also available to control the state of data output drivers. Independent Write and Read controls provide rate-matching capability. Master Reset clears all previous programmed configurations by providing a low pulse on MRST pin. In addition, Write and Read pointers to the queue are initialized to zero. Partial Reset will not alter previously programmed configurations but will initialize Write and Read pointers to zero. In FWFT mode, first data written into the queue appears on output data bus after the specified latency period at the low to high transition of RCLK. Subsequent reads from the queue will require asserting REN . This feature is useful when implementing depth expansion functions. In this mode, DRDY and QRDY are used instead of FULL and EMPTY respectively. 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 1 of 16 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII Product Description (Continued) In Standard mode, always assert REN for a read operation. FULL and EMPTY are used instead of DRDY and QRDY respectively. Bus matching feature is available with the following configurations: Input Bus Width Output Bus Width x18 x72 x36 x72 x72 x72 x72 x36 x72 x18 In addition, Endian Select is available for implementing byte re-ordering on data outputs. Eight different default offset values are available for Almost Full ( PRAF ) and Almost Empty ( PRAE ) flags. Parallel and Serial programming of these offset values provide total flexibility other than the pre-defined default values. Both 8-bit and 9-bit parallel programming modes for offset values can be selected for convenience. PRAF , PRAE , and HALF are available in either FWFT or Standard mode. In addition, PRAF and PRAE can operate in either synchronous or asynchronous modes. At any time, data previously read from the queue can be retransmitted by asserting RET pin at the low to high transition of RCLK for a retransmit operation. Retransmit initializes the Read pointer to zero. Hence, all re-reads will always start from the physical 0th (Read pointer = zero), location of the queue. Both zero and normal latency timing modes available for retransmit operation. These FlexQTM III devices have low power consumption, hence minimizing system power requirements. In addition, industry standard 256 - pin BGA is offered to save system board space. These queues are ideal for applications such as data communication, telecommunication, graphics, multiprocessing, test equipment, network switching, etc. 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 2 of 16 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII Block Diagram of Single Synchronous Queue 65,536 x 72 / 32,768 x 72 / 16,384 x 72 / 8,192 x 72 / 4,096 x 72 / 2,048 x 72 / 1,024 x 72 / 512 X 72 PARTIAL RESET (PRST ) MASTER RESET (MRST) READ CLOCK (RCLK) WRITE CLOCK (WCLK) READ ENABLE (REN ) WRITE ENABLE (WEN) OUTPUT ENABLE ( OE ) LOAD ( LOAD) READ CHIP SELECT ( RCS ) (SFM) x72, x36, x18 DATA OUT (Q71 - 0) (PFS0) (PFS1) x72, x36, x18 DATA IN (D71 - 0) SERIAL IN CLOCK (SCLK) SERIAL DATA ENABLE (SDEN ) FIRST WORD FALL THROUGH/ SERIAL DATA INPUT (FWFT/SDI) FULL FLAG / INPUT READY ( FULL / DRDY ) PROGRAMMABLE ALMOSTFULL (PRAF ) FQV72100 FQV7290 FQV7280 FQV7270 FQV7260 FQV7250 FQV7240 FQV7230 RETRANSMIT ( RET ) EMPTY FLAG / OUTPUT READY ( EMPTY / QRDY ) PROGRAMMABLE ALMOSTEMPTY ( PRAE ) HALF-FULL FLAG ( HALF ) JTAG CLOCK (TCLK) JTAG RESET ( TRST ) JTAG MODE (TMS) INTERSPERSED PARITY (IPAR) (TDO) ENDIAN SELECT (ES) BUS MATCHING 2 (BM2) (RETLZ) (TDI) BUS MATCHING 1 (BM1) BUS MATCHING 0 (BM0) Figure 1. Single Device Configuration Signal Flow Diagram 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 3 of 16 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII WCLK IPAR WEN LOAD SDEN FWFT/SDI FULL / DRDY Write Control Logic PRAF EMPTY/ QRDY PRAE Offset Register Flag Logic HALF FWFT/SDI SFM Write Pointer PFS1 PFS0 D71-0 x72, x36, x18 Input Register SRAM Output Register Output Buffer Q 71-0 x72, x36, x18 OE Read Pointer JTAG Control (Boundary Scan) TCK TRST TMS TDO TDI Read Control Logic RETZL RET RCLK REN RCS Bus Configuration Reset MRST PRST ES BM2 BM1 BM0 Figure 2. Device Architecture 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 4 of 16 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII A1 BALL PAD CORNER A Q33 Q35 Q47 Q50 Q53 Q65 Q68 Q71 D71 D68 D65 D53 D50 D47 D35 D33 Q32 Q34 Q46 Q49 Q52 Q64 Q67 Q70 D70 D67 D64 D52 D49 D46 D34 D32 Q31 Q30 Q45 Q48 Q51 Q63 Q66 Q69 D69 D66 D63 D51 D48 D45 D30 D31 Q29 Q28 Q27 VCC GND VCC GND TCK TDI TRST TDO TMS GND D27 D28 D29 Q17 Q16 Q15 VCC GND VCC GND VCC GND VCC GND VCC GND D15 D16 D17 Q14 Q13 Q12 VCC GND VCC GND VCC GND VCC GND VCC GND D12 D13 D14 Q11 Q10 Q9 VCC GND VCC GND VCC GND VCC GND VCC GND D9 D10 D11 Q62 Q61 Q60 VCC GND VCC GND VCC GND VCC GND VCC GND D60 D61 D62 Q59 Q58 Q57 VCC GND VCC GND VCC GND VCC GND VCC GND D57 D58 D59 Q56 Q55 Q54 VCC GND VCC GND VCC GND VCC GND VCC GND D54 D55 D56 Q44 Q43 Q42 VCC GND VCC GND VCC GND VCC GND GND BM1 D42 D43 D44 Q41 Q40 Q39 VCC GND VCC GND GND PFS1 PFS0 BM0 GND SCLK D39 D40 D41 Q38 Q37 Q36 RET RETZL SFM BM2 IPAR ES HALF FW FT/SDI LOAD SDEN D36 D37 D38 Q26 Q25 Q18 Q6 Q3 Q0 RCS PRAE M RST PRST D0 D3 D6 D18 D25 D26 Q24 Q21 Q19 Q7 Q4 Q1 OE EMPTY PRAF WEN D1 D4 D7 D19 D21 D24 Q23 Q22 Q20 Q8 Q5 Q2 REN RCLK FULL W CLK D2 D5 D8 D20 D22 D23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 B C D E F G H J K L M N P R T PBGA -256 (Drw No: BB-01A; Order code: BB) Top View Figure 3. Device Pin Out 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 5 of 16 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII Pin # P9 Pin Name Master Reset Pin Symbol MRST Input/Output Description Input Master Reset is required to initialize Write and Read pointers to the first position of the queue by setting MRST low. In Standard mode, FULL and PRAF will go high; EMPTY and PRAE will go low. In FWFT mode, DRDY will go low and QRDY will go high. PRAF and PRAE will go to the same state as Standard mode. In both modes, all data outputs will go low. Previous programmed configurations will not be maintained. P10 Partial Reset PRST Input Partial Reset is required to initialize Write and Read pointers to the first position of the queue by setting PRST low. In Standard mode, FULL and PRAF will go high; EMPTY and PRAE will go low. In FWFT mode, DRDY will go low and QRDY will go high. PRAF and PRAE will go to the same state as Standard mode. In both modes, all data outputs will go low. Previous programmed configurations will be maintained. T10 Write Clock WCLK Input Writes data into queue during low to high transitions of WCLK if WEN is set to low. R10 Write Enable WEN Input Controls write operation into queue or offset registers during low to high transition of WCLK. N12 Load Enable LOAD Input During Master Reset, set LOAD low to select parallel programming or one of eight default offset values. Set LOAD high to select serial programming or one of eight default offset values. After Master Reset, LOAD controls write/read to/from offset registers during low to high transition of WCLK/RCLK respectively. Use in conjunction with WEN / REN . M9 Default Programming 1 PFS1 Input During Master Reset, select one of eight default offset values. Use in conjunction with LOAD and PFS0. M10 Default Programming 0 PFS0 Input During Master Reset, select one of eight default offset values. Use in conjunction with LOAD and PFS1. A9, A10, A11, A12, A13, A14, A15, A16, B9, B10, B11, B12, B13, B14, B15, B16, C9, C10, C11, C12, C13, C14, C15, C16, D14, D15, D16, E14, E15, E16, F14, F15, F16, G14, G15, G16, H14, H15, H16, H14, J 15, J16, K14, K15, K16, L14, L15, L16, M14, M15, M16, N14, N15, N16, P11, P12, P13, P14, P15, P16, R11, R12, R13, R14, R15, R16, T11, T12, T13, T14, T15, T16 Data Inputs D71-0 Input 72 - bit wide input data bus. T8 Read Clock RCLK Input Reads data from queue during low to high transitions of RCLK if REN is set to low. Table 1. Pin Descriptions 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 6 of 16 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII Pin # Pin Name Pin Symbol Input/Output Description T7 Read Enable REN Input Controls read operation from queue or offset registers during low to high transition of RCLK. P7 Read Chip Select RCS Input Setting RCS low during the low to high transition of RCLK activates the data output drivers. Setting RCS high during the low to high transition of RCLK deactivates the data output drivers. OE must be set low when using RCS to control the state of the drivers. R7 Output Enable OE Input Setting OE low activates the data output drivers. Setting OE high deactivates the data output drivers (High-Z). A1, A2, A3, A4, A5, A6, A7, A8, B1, B2, B3, B4, B5, B6, B7, B8, C1, C2, C3, C4, C5, C6, C7, C8, D1, D2, D3, E1, E2, E3, F1, F2, F3, G1, G2, G3, H1, H2, H3, J1, J2, J3, K1, K2, K3, L1, L2, L3, M1, M2, M3, N1, N2, N3, P1, P2, P3, P4, P5, P6, R1, R2, R3, R3, R4, R5, R6, T1, T2, T3, T4, T5, T6 Data Outputs Q71-0 Output N11 First Word Fall Through/Serial Data Input FWFT/SDI Input Selects FWFT timing or Standard timing mode during Master Reset. After Master Reset, if serial programming is selected ( LOAD = high), FWFT/SDI is used as the serial data input for the offset registers. Serial data is written during the low to high transition of WCLK. Use in conjunction with SDEN . M13 Serial Clock SCLK Input During serial programming, SCLK is used to program offset values through SDI. N13 Serial Data Input Enable SDEN Input If serial programming is selected, setting SDEN and LOAD low enables serial data input to be written into offset registers during the low to high transition of SCLK. N7 Bus Matching 2 BM2 Input During Master Reset, select one of five input and output bus width configurations. Use in conjunction with BM1 and BM0. L13 Bus Matching 1 BM1 Input During Master Reset, select one of five input and output bus width configurations. Use in conjunction with BM2 and BM0. M11 Bus Matching 0 BM0 Input During Master Reset, select one of five input and output bus width configurations. Use in conjunction with BM2 and BM1. N9 Endian Select ES Input During Master Reset, set ES high to select byte re-ordering on data outputs or ES low to select no byte re-ordering on data outputs. Input Data previously read from the queue can be retransmitted by asserting RET pin at the low to high transition of RCLK for a retransmit operation. Retransmit initializes the Read pointer to zero. Hence, all re-reads will always start from the physical 0th (Read pointer = zero) location of the queue. N4 Retransmit RET 72 - bit wide output data bus. Table 1. Pin Descriptions (Continued) 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 7 of 16 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII Pin # Pin Name Pin Symbol Input/Output N5 Zero Latency Retransmit RETZL Input During Master Reset, set RETZL low to select zero latency retransmit or RETZL high to select normal latency retransmit. Output Queue is full when FULL goes low during the low to high transition of WCLK. This prohibits further writes into the queue. In FWFT mode, queue is full when DRDY goes high during low to high transition of WCLK. This prohibits further writes into the queue. EMPTY / QRDY Output Queue is empty when EMPTY goes low during the low to high transition of RCLK. This prohibits further reads from the queue. In FWFT mode, queue is empty when QRDY goes high during the low to high transition of RCLK. This prohibits further reads from the queue. Interspersed Parity IPAR Input During Master Reset, set IPAR low to select 9-bit parallel programming mode or IPAR high to select 8bit parallel programming mode. Synchronous Partial Flag Mode SFM Input During Master Reset, set SFM high to select Synchronous Partial Flag mode or SFM low to select Asynchronous Partial Flag mode. Output Queue is almost full when PRAF goes low during the low to high transition of WCLK. Default (Full-offset) or programmed offset values determine the status of PRAF . T9 Full/Data Input Ready Flag R8 Empty/Data Output Ready Flag N8 N6 R9 Description Almost Full FULL / DRDY PRAF P8 Almost Empty PRAE Output Queue is almost empty when PRAE goes low during the low to high transition of RCLK. Default (Empty+offset) or programmed offset values determine the status of PRAE . N10 Half Full HALF Output Queue is more than half full when HALF goes low. Triggered by both WCLK and RCLK. D4, D6, E4, E6, E8, E10, E12, F4, F6, F8, F10, F12, G4, G6, G8, G10, G12, H4, H6, H8, H10, H12, J4, J6, J8, J10, J12, K4, K6, K8, K10, K12, L4, L6, L8, L10, M4, M6 Power Vcc N/A 3.3V power supply. D5, D7, D13, E5, E7, E9, E11, E13, F5, F7, F9, F11, F13, G5, G7, G9, G11, G13, H5, H7, H9, H11, H13, J5, J7, J9, J11, J13, K5, K7, K9, K11, K13, L5, L7, L9, L11, L12, M5, M7, M8, M12 Ground GND N/A 0V Ground. Table 1. Pin Description (Continued) 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 8 of 16 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII Pin # Pin Name Pin Symbol Input/Output Description D8 JTAG Clock TCK Input Clock for JTAG function. TMS and TDI are loaded during low to high transitions of TCK. TDO is loaded during high to low transitions of TCK. D10 JTAG Reset TRST Input Reset control for JTAG function. An asynchronous input for the JTAG controller. D12 JTAG Mode Selection TMS Input Mode select for JTAG function. TMS bits are loaded serially during low to high transitions of the TCK. D9 Test Data Input TDI Input Serial data input for JTAG function. TDI is loaded during low to high transitions of the TCK. D11 Test Data Output Output Serial data output for JTAG function. TDO is unloaded during high to low transitions of the TCK. During SHIFT-DR and SHIFT-IR operations, TDO bus will be tri-stated. TDO Table 1. Pin Description (Continued) 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 9 of 16 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII Symbol Com'l & Ind'l Unit Terminal Voltage with respect to GND -0.5 to + 4.5 V TSTG Storage Temperature -55 to +125 IOUT DC Output Current -50 to +50 VTERM Rating NOTES: Absolute Max Ratings are for reference only. Permanent damage to the device may occur if extended period of operation is outside this range. Standard operation should fall within the Recommended Operating Conditions. C mA Table 2. Absolute Maximum Ratings FQV72100, FQV7290, FQV7280, FQV7270, FQV7260, FQV7250, FQV7240, FQV7230 Commercial Clock = 6ns, 7.5ns, 10ns, 15ns Industrial Clock = 7.5ns, 10ns, 15ns Symbol Parameter Recommended Operating Conditions Min. Typ. Max. Min. Typ. Max. Unit Vcc Supply Voltage Com'l / Ind'l 3.15 3.3 3.45 3.15 3.3 3.45 V GND Supply Voltage 0 0 0 0 0 0 V 2.0 - 5.5 2.0 - 5.5 V - - 0.8 - - 0.8 V 0 - 70 0 - 70 -40 - 85 -40 - 85 Input High Voltage Com'l / Ind'l Input Low Voltage Com'l / Ind'l Operating Temperature Commercial Operating Temperature Industrial VIH VIL TA TA C C DC Electrical Characteristics ILI(1) Input Leakage Current (any input) -1 - 1 -1 - 1 A ILO Output Leakage Current -10 - 10 -10 - 10 A 2.4 - - 2.4 - - V - - 0.4 - - 0.4 V Output Logic "1" Voltage, IOH=-2mA Output Logic "0" Voltage, IOL = 8mA VOH VOL Power Consumption Icc1(2,3) Active Power Supply Current - - 40 - - 40 mA Icc2(4) Standby Current - - 15 - - 15 mA Table 3. DC Specifications 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 10 of 16 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII Capacitance at 100MHz Ambient Temperature (25C) Symbol CIN Parameter (2) Input Capacitance COUT(2,4) Output Capacitance Conditions Max. Unit VIN= 0V 10 pF VOUT= 0V 10 pF NOTES: 1. 2. 3. 4. Measurement with 0.4<=VIN<=Vcc With output tri-stated ( OE = High) Icc(1,2) is measured with WCLK and RCLK at 20 MHz Design simulated, not tested. Table 3. DC Specifications (Continued) 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 11 of 16 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII Commercial FQV72100-6 FQV7290-6 FQV7280-6 FQV7270-6 FQV7260-6 FQV7250-6 FQV7240-6 FQV7230-6 Symbol Parameter Commercial & Industrial FQV72100-7.5 FQV7290-7.5 FQV7280-7.5 FQV7270-7.5 FQV7260-7.5 FQV7250-7.5 FQV7240-7.5 FQV7230-7.5 FQV72100-10 FQV7290-10 FQV7280-10 FQV7270-10 FQV7260-10 FQV7250-10 FQV7240-10 FQV7230-10 FQV72100-15 FQV7290-15 FQV7280-15 FQV7270-15 FQV7260-15 FQV7250-15 FQV7240-15 FQV7230-15 Min. Max. Min. Max. Min. Max. Min. Max. Unit fS Clock Cycle Frequency - 166 - 133 - 100 - 66 MHz tA Data Access Time 1 4 2 5 2 6.5 2 10 ns tWCLK Write Clock Cycle Time 6 - 7.5 - 10 - 15 - ns tWCLKH Write Clock High Time 2.5 - 3.5 - 4.5 - 6 - ns tWCLKL Write Clock Low Time 2.5 - 3.5 - 4.5 - 6 - ns tRCLK Read Clock Cycle Time 6 - 7.5 - 10 - 15 - ns tRCLKH Read Clock High Time 2.5 - 3.5 - 4.5 - 6 - ns tRCLKL Read Clock Low Time 2.5 - 3.5 - 4.5 - 6 - ns tDS Data Set-up Time 2.0 - 2.5 - 3.5 - 4 - ns tDH Data Hold Time 0.5 - 0.5 - 0.5 - 1 - ns tENS Enable Set-up Time 2.0 - 2.5 - 3.5 - 4 - ns tENH Enable Hold Time 0.5 - 0.5 - 0.5 - 1 - ns 8 - 10 - 10 - 15 - ns 15 - 15 - ns (1) tRST Reset Pulse Width tRSTS Reset Set-up Time 10 - 15 tRSTR Reset Recovery Time 10 - 10 - 10 - 15 - ns tRSTF Reset to Flag and Output Time - 10 - 15 - 15 - 15 ns 0 - 0 - 0 - 0 - ns (1) tOLZ Output Enable to Output in Low-Z tOE Output Enable to Output Valid 2 4 2 6 2 6 2 8 ns tOHZ Output Enable to Output in High-Z(1) 2 4 2 6 2 6 2 8 ns tFULL Write Clock to Full Flag - 4 - 5 - 6.5 - 10 ns tEMPTY Read Clock to Empty Flag - 4 - 5 - 6.5 - 10 ns tPRAFS Write Clock to Synchronous Almost-Full Flag - 4 - 5 - 6.5 - 10 ns tPRAES Read Clock to Synchronous AlmostEmpty Flag - 4 - 5 - 6.5 - 10 ns tRCSS RCS Setup Time 2 - 3.5 - 3.5 - 5 - ns tRCSH RCS Hold Time 0.5 - 0.5 - 0.5 - 1 - ns tRCSLZ RCLK to Active from High-Z 2 4 1 6.5 1 6.5 1 10 ns tRCSHZ RCLK to High-Z 2 4 1 6.5 1 6.5 1 10 ns Table 4. AC Electrical Characteristics 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 12 of 16 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII Commercial FQV72100-6 FQV7290-6 FQV7280-6 FQV7270-6 FQV7260-6 FQV7250-6 FQV7240-6 FQV7230-6 Symbol Parameter Commercial & Industrial FQV72100-7.5 FQV7290-7.5 FQV7280-7.5 FQV7270-7.5 FQV7260-7.5 FQV7250-7.5 FQV7240-7.5 FQV7230-7.5 FQV72100-10 FQV7290-10 FQV7280-10 FQV7270-10 FQV7260-10 FQV7250-10 FQV7240-10 FQV7230-10 FQV72100-15 FQV7290-15 FQV7280-15 FQV7270-15 FQV7260-15 FQV7250-15 FQV7240-15 FQV7230-15 Min. Max. Min. Max. Min. Max. Min. Max. Unit tSKEW1 Skew time between Read Clock & Write Clock for Full Flag / Empty Flag 4 - 5 - 7 - 9 - ns tSKEW2 Skew time between Read Clock & Write Clock for PRAE & PRAF 6 - 7 - 10 - 14 - ns tLOADS Load Setup Time 2.0 - 2.5 - 3.5 - 4 - ns tLOADH Load Hold Time 0.5 - 0.5 - 0.5 - 1 - ns tRETS Retransmit Setup Time 2.5 - 3.5 - 3.5 - 4 - ns tHALF Clock to HALF - 12 - 12.5 - 16 - 20 ns tPRAFA Write Clock to Asynchronous Programmable Almost-Full Flag - 12 - 12.5 - 16 - 20 ns tPRAEA Read Clock to Asynchronous Programmable Almost-Empty Flag - 12 - 12.5 - 16 - 20 ns NOTES: 1. Design simulated, not tested. Table 4. AC Electrical Characteristics (Continued) 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 13 of 16 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load, clock = 6ns, 7.5 ns Refer to Figure 4 Output Load*, clock = 10ns, 15ns Refer to Figure 5 & 6 * Include jig and scope capacitances Table 5. AC Test Condition 3.3V Vcc/2 330 50 D.U.T. 30pF* I/O 510 Z0 = 50 Figure 5. Output Load for clock = 10ns, 15ns *Includes jig and scope capacitances. Figure 4. AC Test Load for clock = 6ns, 7.5ns tCD (Typical, ns) 4 3 2 1 20 30 50 80 100 200 Capacitance (pF) Figure 6. Lumped Capacitive Load 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 14 of 16 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII Pin Functions MRST Master Reset is required to initialize Write and Read pointers to the first position of the queue by setting MRST low. In Standard mode, FULL and PRAF will go high, EMPTY and PRAE will go low. In FWFT mode, DRDY will go low and QRDY will go high. PRAF and PRAE will go to the same state as Standard mode. In both modes, all data outputs will go low, and previous programmed configurations will not be maintained. PRST Partial Reset is required to initialize Write and Read pointers to the first position of the queue by setting PRST low. In Standard mode, FULL and PRAF will go high. EMPTY and PRAE will go low. In FWFT mode, DRDY will go low and QRDY will go high. PRAF and PRAE will go to the same state as Standard mode. In both modes, all data outputs will go low, and previously programmed configurations will be maintained. WCLK Writes data into queue during low to high transitions of WCLK if WEN is activated. Synchronizes FULL / DRDY and PRAF flags. WCLK and RCLK are independent of each other. WEN Controls write operation into queue or offset registers during low to high transition of WCLK. LOAD During Master Reset, set LOAD low to select parallel programming or one of eight default offset values. Set LOAD high to select serial programming or one of eight default offset values. After Master Reset, LOAD controls write/read, to/from offset registers during low to high transition of WCLK/RCLK respectively for parallel programming. Use in conjunction with WEN / REN . During programming of offset registers, PRAF and PRAE flag status is invalid. For Serial programming, LOAD is used to enable serial loading of offset registers together with SDEN . Refer to Figure 7 for details. PFS1 During Master Reset, select one of eight default offset values. Use in conjunction with LOAD and PFS0. Refer to Table 11 for details. PFS0 During Master Reset, select one of eight default offset values. Use in conjunction with LOAD and PFS1. Refer to Table 11 for details. D71..0 72 - bit wide input data bus. RCLK Reads data from queue during low to high transitions of RCLK if REN is set low. Synchronizes the EMPTY / QRDY and PRAE flags. RCLK and WCLK are independent of each other. REN Reads data from queue during low to high transitions of RCLK if REN is set to low. This also advances the Read pointer of the queue. RCS Setting RCS low during the low to high transition of RCLK activates the data output drivers. Setting RCS high during the low to high transition of RCLK deactivates the data output drivers. OE must be set low when using RCS to control the state of the drivers. OE Setting OE low activates the data output drivers. Setting OE high deactivates the data output drivers (High-Z). OE does not control advancement of Read pointer. Q71..0 72 - bit wide output data bus. FWFT/SDI Selects First Word Fall Through timing or Standard timing mode during Master Reset. After Master Reset, if serial programming is selected ( LOAD = high), FWFT/SDI is used as the serial data input for the offset registers. Serial data is written during the low to high transition of WCLK. Use in conjunction with SDEN . In FWFT mode, DRDY and QRDY is used instead of FULL and EMPTY . In Standard mode, FULL and EMPTY is used instead of DRDY and QRDY . Refer to Table 8 & 9 for all flags status. SCLK During serial programming, SCLK is used to program offset values through SDI. 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 15 of 16 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII Pin Functions (Continued) SDEN If serial programming is selected, setting SDEN and LOAD low enables serial data to be written into offset registers during the low to high transition of SCLK. During serial programming, PRAF and PRAE flags status is invalid. Refer to Figure 7 for details. BM2 During Master Reset, select one of five input and output bus width configurations. Use in conjunction with BM1 and BM0. Refer to Table 10 for details. BM1 During Master Reset, select one of five input and output bus width configurations. Use in conjunction with BM2 and BM0. Refer to Table 10 for details. BM0 During Master Reset, select one of five input and output bus width configurations. Use in conjunction with BM2 and BM1. Refer to Table 10 for details. ES During Master Reset, set ES high to select byte re-ordering on data outputs or set ES low to select no byte re-ordering on data outputs. ES must be static throughout device operation. Refer to Table 10 for details. RET Data previously read from the queue can be retransmitted by asserting RET pin at the low to high transition of RCLK for a retransmit operation. Retransmit initializes the Read pointer to zero. Hence, all re-reads will always start from the physical 0th (Read pointer = zero) location of the queue. Refer to Diagram 9 & 10 for details. RETZL During Master Reset, set RETZL low to select zero latency retransmit. Set RETZL high to select normal latency retransmit. FULL / DRDY In Standard mode, queue is full when FULL goes low during the low to high transition of WCLK. This prohibits further writes into the queue and prevents advancement of Write pointer. In FWFT mode, queue is full when DRDY goes low during the low to high transition of WCLK. This prohibits further writes into the queue and prevents advancement of Write pointer. Refer to Table 8 & 9 for behavior of FULL / DRDY . EMPTY / QRDY In Standard mode, queue is empty when EMPTY goes low during the low to high transition of RCLK. This prohibits further reads from the queue and prevents advancement of Read pointer. In FWFT mode, queue is empty when QRDY goes low during the low to high transition of RCLK. This prohibits further reads from the queue and prevents advancement of Read pointer. Refer to Table 8 & 9 for behavior of EMPTY / QRDY . IPAR During Master Reset, set IPAR low to select 9-bit parallel programming mode or set IPAR high to select 8-bit parallel programming mode. In 9-bit mode, 9-bit wide data input / output bus width is used for storing / fetching offset values. In 8-bit mode, 8-bit wide data input / output bus is used for storing / fetching offset values. SFM During Master Reset, set SFM high to select Synchronous Partial Flag mode or set SFM low to select Asynchronous Partial Flag mode. In Synchronous mode, PRAF and PRAE are synchronous to WCLK and RCLK respectively. In Asynchronous mode, WCLK synchronizes the assertion of PRAF and de-assertion of PRAE . RCLK synchronizes the assertion of PRAE and de-assertion of PRAF . PRAF Queue is almost full when PRAF goes low during the low to high transition of WCLK. Default (Full-offset) or programmed offset values determine the status of PRAF . Refer to Table 8 & 9 for behavior of PRAF . PRAE Queue is almost empty when PRAE goes low during the low to high transition of RCLK. Default (Empty+offset) or programmed offset values determine the status of PRAE . Refer to Table 8 & 9 for behavior of PRAE . 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 16 of 16 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII Pin Functions (Continued) HALF Queue is more than half full when HALF goes low during the low to high transition of WCLK. Queue is less than half full when HALF goes high during low to high transition of RCLK when. Refer to Table 8 & 9 for details. 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 17 of 17 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII WEN LOAD 0 0 0 1 REN 1 0 SDEN WCLK 1 1 RCLK X SCLK X X X FQV72100 FQV7290 FQV7280 FQV7270 FQV7260 FQV7250 FQV7240 FQV7230 Selection / Sequence Parallel write to offset registers: Empty Offset Full Offset Parallel write to registers: 1. PRAE 2. PRAF Parallel read from offset registers: Empty Offset Full Offset Parallel read from registers: 1. PRAE 2. PRAF 0 1 1 0 X X X 1 1 1 X X X Serial shift into registers: 32 bits for the FQV72100 30 bits for the FQV7290 28 bits for the FQV7280 26 bits for the FQV7270 24 bits for the FQV7260 22 bits for the FQV7250 20 bits for the FQV7240 18 bits for the FQV7230 1 bit for each rising SCLK edge Starting with Empty Offset (Low Byte) Ending with Full Offset (High Byte) No Operation 1 0 X X X X Write Memory 1 X 0 X X X Read Memory 1 1 1 X X X No Operation X Figure 7. Programmable Flag Offset Programming Sequence (FQV72100, FQV7290, FQV7280, FQV7270, FQV7260, FQV7250, FQV7240 and FQV7230) 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 18 of 18 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII Device FQV72100 FQV7290 FQV7280 FQV7270 FQV7260 FQV7250 FQV7240 FQV7230 PRAF Programming (bits) PRAE Programming (bits) D/Q15 - 0 Non-IPAR D/Q15 - 0 Non-IPAR D/Q16 - 9 & D/Q7 - 0 IPAR D/Q16 - 9 & D/Q7 - 0 IPAR D/Q14 - 0 Non-IPAR D/Q14 - 0 Non-IPAR D/Q15 - 9 & D/Q7 - 0 IPAR D/Q15 - 9 & D/Q7 - 0 IPAR D/Q13 - 0 Non-IPAR D/Q13 - 0 Non-IPAR D/Q14 - 9 & D/Q7 - 0 IPAR D/Q14 - 9 & D/Q7 - 0 IPAR D/Q12 - 0 Non-IPAR D/Q12 - 0 Non-IPAR D/Q13 - 9 & D/Q7 - 0 IPAR D/Q13 - 9 & D/Q7 - 0 IPAR D/Q11 - 0 Non-IPAR D/Q11 - 0 Non-IPAR D/Q12 - 9 & D/Q7 - 0 IPAR D/Q12 - 9 & D/Q7 - 0 IPAR D/Q10 - 0 Non-IPAR D/Q10 - 0 Non-IPAR D/Q11 - 9 & D/Q7 - 0 IPAR D/Q11 - 9 & D/Q7 - 0 IPAR D/Q9 - 0 Non-IPAR D/Q9 - 0 Non-IPAR D/Q10 - 9 & D/Q7 - 0 IPAR D/Q10 - 9 & D/Q7 - 0 IPAR D/Q8 - 0 Non-IPAR D/Q8 - 0 Non-IPAR D/Q9 & D/Q7 - 0 IPAR D/Q9 & D/Q7 - 0 IPAR Table 6. Parallel Offset Register Data Mapping Table for x72 & x36 & x18 Device Standard Mode FWFT Mode FVQ72100 65,536 x 72 65,537 x 72 FVQ7290 32,768 x 72 32,769 x 72 FQV7280 16,384 x 72 16,385 x 72 FQV7270 8,192 x 72 8,193 x 72 FQV7260 4,096 x 72 4,097 x 72 FQV7250 2,048 x 72 2,049 x 72 FQV7240 1,024 x 72 1,025 x 72 FQV7230 512 x 72 513 x 72 Table 7. Maximum Depth of Queue for Standard and FWFT Mode 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 19 of 19 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII Data Width D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1st Cycle PRAE Non-Interspersed Parity Interspersed Parity Data Width 15 15 14 13 12 11 10 9 14 13 12 11 10 9 8 D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9 2nd Cycle PRAF Non-Interspersed Parity Interspersed Parity 15 15 14 13 12 11 10 9 14 13 12 11 10 9 8 FQV72100, FQV7290, FQV7280, FQV7270, FQV7260, FQV7250, FQV7240, FQV7230 Parallel Offset Write/Read Cycles for x18 Bus Width Data Width D/Q71 D/Q~ D/Q~ D/Q~ D/Q19 D/Q18 D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1st Cycle PRAE Non-Interspersed Parity Interspersed Parity Data Width 15 D/Q71 D/Q~ D/Q~ D/Q~ 15 14 13 12 11 10 9 14 13 12 11 10 9 8 D/Q19 D/Q18 D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9 2nd Cycle PRAF Non-Interspersed Parity Interspersed Parity 15 15 14 13 12 11 10 9 14 13 12 11 10 9 8 FQV72100, FQV7290, FQV7280, FQV7270, FQV7260, FQV7250, FQV7240, FQV7230 Parallel Offset Write/Read Cycles for x36 Bus Width Data Width D/Q71 D/Q~ D/Q~ D/Q~ D/Q19 D/Q18 D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1st Cycle PRAE Non-Interspersed Parity 15 Interspersed Parity Data Width 15 D/Q71 D/Q~ D/Q~ D/Q~ D/Q19 D/Q18 14 14 13 13 12 12 11 11 10 10 9 9 8 D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9 2nd Cycle PRAF Non-Interspersed Parity Interspersed Parity 15 15 14 13 12 11 10 9 14 13 12 11 10 9 8 FQV72100, FQV7290, FQV7280, FQV7270, FQV7260, FQV7250, FQV7240, FQV7230 Parallel Offset Write/Read Cycles for x72 Bus Width Figure 8. Parallel Offset Write/Read Cycles Diagram 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 20 of 20 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII # of Bits for Offset Registers 16 bits for FQV72100 15 bits for FQV7290 14 bits for FQV7280 13 bits for FQV7270 12 bits for FQV7260 11 bits for FQV7250 10 bits for FQV7240 9 bits for FQV7230 Note: Don't Care applies to all unused bits Figure 8. Parallel Offset Write/Read Cycles Diagram (Continued) 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 21 of 21 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII FQV72100 FULL PRAF HALF PRAE EMPTY 0 1 to y(1) (y+1) to 32,768 32,769 to [65,536-(x+1)] (65,536 -x(2)) to 65,535 65,536 H H H H H L H H H H L L H H H L L L L L H H H H L H H H H H FQV7290 FULL PRAF HALF PRAE EMPTY 0 1 to y(1) (y+1) to 16,384 16,385 to [32,768-(x+1)] (32,768 -x(2)) to 32,767 32,768 H H H H H L H H H H L L H H H L L L L L H H H H L H H H H H FQV7280 FULL PRAF HALF PRAE EMPTY 0 1 to y(1) (y+1) to 8,192 8,193 to [16,384-(x+1)] (16,384 -x(2)) to 16,383 16,384 H H H H H L H H H H L L H H H L L L L L H H H H L H H H H H FQV7270 FULL PRAF HALF PRAE EMPTY 0 1 to y(1) (y+1) to 4,096 4,097 to [8,192-(x+1)] (8,192 -x(2)) to 8,191 8,192 H H H H H L H H H H L L H H H L L L L L H H H H L H H H H H FQV7260 FULL PRAF HALF PRAE EMPTY 0 1 to y(1) (y+1) to 2,048 2,049 to [4,096-(x+1)] (4,096 -x(2)) to 4,095 4,096 H H H H H L H H H H L L H H H L L L L L H H H H L H H H H H FQV7250 FULL PRAF HALF PRAE EMPTY 0 1 to y(1) (y+1) to 1,024 1,025 to [2,048-(x+1)] (2,048 -x(2)) to 2,047 2,048 H H H H H L H H H H L L H H H L L L L L H H H H L H H H H H Table 8. Status Flags (Standard Mode) 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 22 of 22 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII FQV7240 FULL PRAF HALF PRAE EMPTY 0 1 to y(1) (y+1) to 512 513 to [1,024-(x+1)] (1,024 -x(2)) to 1,023 1,024 H H H H H L H H H H L L H H H L L L L L H H H H L H H H H H FQV7230 FULL PRAF HALF PRAE EMPTY 0 1 to y(1) (y+1) to 256 257 to [512-(x+1)] (512 -x(1)) to 511 512 H H H H H L H H H H L L H H H L L L L L H H H H L H H H H H NOTES: 1. See Table 11 for values x, y. Table 8. Status Flags (Standard Mode)(Continued) 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 23 of 23 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII FQV72100 DRDY PRAF HALF PRAE QRDY 0 1 to y+1 (y+2) to 32,769 32,770 to [65,537-(x+1)] (65,537 -x) to 65,536 65,537 L L L L L H H H H H L L H H H L L L L L H H H H H L L L L L FQV7290 DRDY PRAF HALF PRAE QRDY 0 1 to y+1 (y+2) to 16,385 16,386 to [32,769-(x+1)] (32,769 -x) to 32,768 32,769 L L L L L H H H H H L L H H H L L L L L H H H H H L L L L L FQV7280 DRDY PRAF HALF PRAE QRDY 0 1 to y+1 (y+2) to 8,193 8,194 to [16,385-(x+1)] (16,385 -x) to 16,384 16,385 L L L L L H H H H H L L H H H L L L L L H H H H H L L L L L FQV7270 DRDY PRAF HALF PRAE QRDY 0 1 to y+1 (y+2) to 4,097 4,098 to [8,193-(x+1)] (8,193-x) to 8,192 8,193 L L L L L H H H H H L L H H H L L L L L H H H H H L L L L L FQV7260 DRDY PRAF HALF PRAE QRDY 0 1 to y+1 (y+2) to 2,049 2,050 to [4,097-(x+1)] (4,097 -x) to 4,096 4,097 L L L L L H H H H H L L H H H L L L L L H H H H H L L L L L FQV7250 DRDY PRAF HALF PRAE QRDY 0 1 to y+1 (y+2) to 1,025 1,026 to [2,049-(x+1)] (2,049 -x) to 2,048 2,049 L L L L L H H H H H L L H H H L L L L L H H H H H L L L L L Table 9. Status Flags (FWFT Mode) 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 24 of 24 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII FQV7240 DRDY PRAF HALF PRAE QRDY 0 1 to y+1 (y+2) to 513 514 to [1,025-(x+1)] (1,025 -x) to 1,024 1,025 L L L L L H H H H H L L H H H L L L L L H H H H H L L L L L FQV7230 DRDY PRAF HALF PRAE QRDY 0 1 to y+1 (y+2) to 257 258 to [513-(x+1)] (513 -x) to 512 513 L L L L L H H H H H L L H H H L L L L L H H H H H L L L L L Table 9. Status Flags (FWFT Mode)(Continued) 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 25 of 25 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII ES BM2 BM1 BM0 I/O Width D/Q71-54 D/Q53-36 D/Q35-18 D/Q17-0 Sequence X 0 X X I O 72 72 Byte 4 Byte 4 Byte 3 Byte 3 Byte 2 Byte 2 Byte 1 Byte 1 1st Write 1st Read 0 1 0 0 I 72 Byte 4 Byte 3 Byte 2 Byte 1 1st Write O 36 X X X X Byte 4 Byte 2 Byte 3 Byte 1 1st Read 2nd Read I 72 Byte 4 Byte 3 Byte 2 Byte 1 1st Write O 18 X X X X X X X X X X X X Byte 4 Byte 3 Byte 2 Byte1 1st Read 2nd Read 3rd Read 4th Read I 36 X X X X Byte 4 Byte 2 Byte 3 Byte 1 1st Write 2nd Write O 72 Byte 4 Byte 3 Byte 2 Byte 1 1st Read I 18 O 72 X X X X Byte 4 X X X X Byte 3 X X X X Byte 2 Byte 4 Byte 3 Byte 2 Byte1 Byte 1 1st Write 2nd Write 3rd Write 4th Write 1st Read I 72 Byte 4 Byte 3 Byte 2 Byte 1 1st Write O 36 X X X X Byte 2 Byte 4 Byte 1 Byte 3 1st Read 2nd Read 0 1 0 1 0 1 1 1 0 1 1 0 1 0 1 0 1 1 0 1 I O 72 18 Byte 4 X X X X Byte 3 X X X X Byte 2 X X X X Byte 1 Byte 1 Byte 2 Byte 3 Byte4 1st Write 1st Read 2nd Read 3rd Read 4th Read 1 1 1 0 I 36 O 72 X X Byte 2 X X Byte 1 Byte 4 Byte 2 Byte 4 Byte 3 Byte 1 Byte 3 1st Write 2nd Write 1st Read I 18 X X X X X X X X X X X X Byte 4 Byte 3 Byte 2 Byte1 1st Write 2nd Write 3rd Write 4th Write O 72 Byte 1 Byte 2 Byte 3 Byte 4 1st Read 1 1 1 1 Table 10. Bus-Matching Table 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 26 of 26 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII LOAD PFS1 PFS0 FQV7240 FQV7230 Default Offsets x, y(1) 0 0 0 127 0 0 1 255 0 1 0 511 0 1 1 63 1 0 0 31 1 0 1 7 1 1 0 15 1 1 1 3 LOAD PFS1 PFS0 FQV7240 FQV7230 Program Mode 1 X X Serial 0 X X Parallel LOAD PFS1 PFS0 FQV7280 FQV7270 FQV7260 FQV7250 Default Offsets x, y(1) 0 0 0 127 0 0 1 255 0 1 0 511 0 1 1 63 1 0 0 1,023 1 0 1 15 1 1 0 31 1 1 1 7 LOAD PFS1 PFS0 FQV7280 FQV7270 FQV7260 FQV7250 Program Mode 1 X X Serial 0 X X Parallel NOTES: 1. y = PRAE offset, x = PRAF offset Table 11. Default Programmable Flag Offsets 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 27 of 27 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII PFS1 LOAD PFS0 FQV72100 FQV7290 Default Offsets x, y(1) 0 0 0 127 0 0 1 8,191 0 1 0 16,383 0 1 1 4,095 1 0 0 1,023 1 0 1 511 1 1 0 2,047 1 1 1 255 LOAD PFS1 PFS0 FQV72100 FQV7290 Program Mode 1 X X Serial 0 X X Parallel NOTES: 1. y = PRAE offset, x = PRAF offset Table 11. Default Programmable Flag Offsets (Continued) 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 28 of 28 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII JTAG Interface Standard JTAG interface is used for boundary scan purposes. For a complete description, please refer to the IEEE Standard Test Access Port Specification (IEEE STD.1149.1 - 1990) JTAG TIMING SPECIFICATIONS t3 t1 tTCK t4 t2 TCK TDI / TMS tDS tDH TDO TDO t6 tDO TRST t5 Figure 9. Standard JTAG Timing Parameter System Interface Parameters Data Output Data Output Hold Data Input Symbol tDO = Max tDOH tDS tDH JTAG AC Electrical Characteristics JTAG Clock Input Period tTCK JTAG Clock HIGH tTCKHIGH (t2) JTAG Clock Low tTCKLOW (t1) JTAG Clock Rise Time tTCKRise (t4) JTAG Clock Fall Time JTAG Reset JTAG Reset Recovery tTCKFall (t3) tRST (t5) tRSR (t6) Test Conditions Min. FQV72100 FQV7290 FQV7280 FQV7270 FQV7260 FQV7250 FQV7240 FQV7230 Max. - 5 50 ns - 5 30 30 - ns trise = 3ns tfall = 3ns - 100 40 40 - 5 ns ns ns ns - 50 50 5 - ns ns ns Units ns Table 12. JTAG AC Electrical Characteristics 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 29 of 29 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII JTAG BLOCK DIAGRAM HBA's FlexQTM offers IEEE Std. 1149.1-1990 standard JTAG interface to facilitate system debugging in all PBGA packages. STANDARD JTAG INTERFACE ELEMENTS: 1. 2. 3. 4. TAP TAPCNTL IR DR - TEST ACCESS PORT - TAP CONTROLLER - INSTRUCTION REGISTER - DATA REGISTER Boundary Scan Reg. TDO TDI TMS Device ID Reg. Bypass Reg. TAP TCLK TRST Instruction Decode DR Instruction Register IR TAP Controller Figure 10. Boundary Scan Architecture Diagram 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 30 of 30 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII 1. TAP The basic ports to access the JTAG function. That includes four general input ports: TRST , TCK, TMS, and TDI, and one general output port: TDO. 2. TAPCNTL A finite state machine that provide instructions to the Instruction and Data Registers for data capture and update. Individual states are explained blow. 1 0 Test-Logic Reset 0 Run-Test / Idle 1 1 1 Select-DRScan Select-IRScan 0 1 0 1 Capture-DR 0 Capture-IR 0 0 Shift-DR Shift-IR 1 Input = TMS 1 1 Exit1-DR 0 0 0 0 Pause-IR 1 1 Exit2-DR 0 Exit2-IR 1 Update-DR 1 1 Exit1-IR Pause-DR 0 0 0 1 Update-IR 1 0 Figure 11. TAP Controller State Diagram * Capture-IR Data are captured in parallel into the instruction register. * Capture-DR Data are captured in parallel into the data register. * SHIFT-IR LSB of the instruction register is shift in serially during a low to high transition of the TCK through TDI/TDO path * SHIFT-DR LSB of the data register is shift in serially during a low to high transition of the TCK through TDI/TDO path. 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 31 of 31 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII * UPDATE-IR To shift Instruction Register Data to the parallel outputs. Instruction Register Data can be accessed through the internal bus. * UPDATE-DR To shift Data Register Data to the parallel outputs. Data Register Data can be accessed through the internal bus. * EXIT1-IR/ EXIT2-IR A transition state that terminates the scanning process. All Instruction Register data selected will retain their previous instruction state. * EXIT1-DR/ EXIT2-DR A transition state that terminates the scanning process. All Data Register data selected will retain their previous data state. * PAUSE-IR The temporary state to halt all serial shifting process between TDI and TDO. All data will retain their previous instruction state. * PAUSE-DR The temporary state to halt all serial shifting process between TDI and TDO. All data will retain their previous data state. A 4 - bit instruction register that is shifted serially at the rising edge of TCLK. The instruction is latched through the least significant bits of the nearest serial OUTPUT. 3. INSTRUCTION REGISTER Hex Value Instruction Function 0 x 00 EXTEST Select Boundary Scan Register 0 x 02 IDCODE Select Chip Identification data register 0 x 01 SAMPLE/PRELOAD Select Boundary Scan Register 0 x 03 HI-Z JTAG 0 x 0F BYPASS Select Bypass Register Table 13. JTAG Instruction Register Decoding Table * EXTEST An instruction to facilitate external circuitry and board level interconnection verification. * IDCODE An instruction to read out manufacture's identification, part number and version number. * SAMPLE/ PRE-LOAD An instruction to allow snapshots of data flowing through the system pins. SAMPLE instruction MUST be executed prior to the selection of Boundary Scan test. * HIGH Z An Instruction to place all output pins to high impedance state. * BYPASS An Instruction to allow direct serial data shifting through TDI and TDO without any device operation. 4. DATA REGISTER * Device ID Register There are three data registers, Device ID register, BYPASS register, and Boundary Scan register. These parallel-connected registers are access through the common serial input and the common serial output. A 32-bit register that contains the specific manufacturer, part number and version number. 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 32 of 32 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII 31(MSB) Version (4 bits) 0x0 28 27 Part Number (16-bit) 12 11 Manufacturer ID (11-bit) 0x16E Device Part # Field FQV72100 0 x 50 FQV7290 0 x 56 FQV7280 0 x 55 FQV7270 0 x 54 FQV7260 0 x 53 FQV7250 0 x 52 FQV7240 0 x 51 FQV7230 0 x 57 1 0(LSB) 1 Table 14. Device ID Register Decode Table * BYPASS Register The data register that allows direct serial data shifting through TDI and TDO without any device operation. * BOUNDARY SCAN Register The data register that allows the serial writes and read through TDI and TDO. 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 33 of 33 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII Timing Diagrams tRST MRST tRSTS tRSTR tRSTS tRSTR tRSTS tRSTR tRSTS tRSTR REN WEN FWFT/SDI LOAD tRSTS PFS1/PFS0 tRSTS BM2/BM1/BM0 tRSTS ES tRSTS RETZL tRSTS SFM tRSTS IPAR tRSTS RET tRSTS SDEN tRSTF If FWFT = 1,QRDY = 1 EMPTY / QRDY If FWFT = 0, EMPTY = 0 tRSTF If FWFT = 0, FULL = 1 FULL / DRDY If FWFT = 1, DRDY = 0 tRSTF PRAE tRSTF PRAF / HALF tRSTF OE = 1 Q71- 0 OE = 0 Diagram 1. Master Reset Timing 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 34 of 34 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII tRST PRST tRSTS tRSTR tRSTS tRSTR REN WEN tRSTS RET tRSTS SDEN tRSTF If FWFT = 1,QRDY = 1 EMPTY / QRDY If FWFT = 0, EMPTY = 0 tRSTF If FWFT = 0, FULL = 1 FULL / DRDY If FWFT = 1, DRDY = 0 tRSTF PRAE tRSTF PRAF / HALF tRSTF OE = 1 Q71- 0 OE = 0 Diagram 2. Partial Reset Timing 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 35 of 35 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. 2. 1. tRCSS tENS tRCSLZ tSKEW1 tA tENH 1 No Write tFULL 2 tDS tWCLKH DWi tENS tFULL tDH ___________ Data Read tWCLK tWCLKL tA tENH 1 No Write tFULL 2 DWi + 1 __________ Next Data Read tDS ______ LOAD = High, OE = Low. ___________ Diagram 3. Write Cycle and Full Flag Timing (Standard Mode) tDH tFULL If the time between a rising edge of RCLK to the rising edge of WCLK is greater than or equal to tSKEW1, FULL will go high (after one WCLK cycle plus tFULL). If tSKEW1 is not met, then FULL will assert 1 or more WCLK cycles. NOTES: Q 71 - 0 RCS REN RCLK WEN FULL D 71 - 0 WCLK No Write FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII NOVEMBER 2002 Page 36 of 36 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. 2. 3. 1. tENS tOLZ tA tEMPTY tENS tENH tDS tSKEW1 DW1 tOEN tDH tENH tOHZ Last Word No Operation 1 tDS tENS DW2 ______________ tDH tENH tOLZ tEMPTY No Operation 2 tRCLK Last Word tENS tA tRCLKL tENH tA ______________ DW1 tEMPTY tENS tENH DW2 Diagram 4. Read Cycle, Empty Flag and First Data Word Latency Timing (Standard Mode) LOAD = High. First word latency: tSKEW1 + tEMPTY + 1 * tRCLK. ___________ If the time between a rising edge of WCLK to the rising edge of RCLK is greater than or equal to tSKEW11, EMPTY will go high (after RCLK cycle plus tEMPTY). If tSKEW1 is not met, then EMPTY will assert 1 or more RCLK cycles. NOTES: D71 - 0 WEN WCLK OE Q71 - 0 EMPTY REN RCLK tRCLKH FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII NOVEMBER 2002 Page 37 of 37 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. 2. 3. 1. tRCSLZ tRCSS tENS tA tRCSH Last Data - 1 tRCSHZ tA ______________ tRCSLZ tRCSS tDS tENS tSKEW1 tEMPTY DWi tDH tENH Last Data tRCSS 1 tRCSHZ ______________ tEMPTY 2 LOAD = High. First word latency: tSKEW1 + tEMPTY + 1 * tRCLK. ___________ Diagram 5. Read Cycle and Read Chip Select Timing (Standard Mode) If the time between a rising edge of WCLK to the rising edge of RCLK is greater than or equal to tSKEW11, EMPTY will go high (after RCLK cycle plus tEMPTY). If tSKEW1 is not met, then EMPTY will assert 1 or more RCLK cycles. NOTES: D71 - 0 WEN WCLK Q71 - 0 EMPTY RCS REN RCLK FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII NOVEMBER 2002 Page 38 of 38 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. tDS tENS 4. 5. 6. 3. 2. 1. tRCSS 1 DW2 tSKEW1 2 DW3 Previous Output Register Data DW1 tDH tRCLZ 3 tEMPTY tA DW4 tDS DW[y+2] 1 DW[y+3] tSKEW2 2 DW1 DW[y+4] tPRAES DW[(D-1)/2+1] tDS DW[(D-1)/2+2] ____________ tHALF DW[(D-1)/2+3] DW[D-x-1] tDS DW[D-x] DW[D-x+1] 1 DW[D-x+2] 2 tPRAFS DW[D-x+3] DW[D-1] DWD ____________ tFULL tENH ___________ ______ ___________ y = PRAE offset, x = PRAF offset. D = maximum queue depth. Please refer to Table 7 for Depth. First word latency: tSKEW1 + tEMPTY + 2 * tRCLK ___________ LOAD = High, OE = Low. ___________ Diagram 6. Write Timing (FWFT Mode) If the time between a rising edge of WCLK to the rising edge of RCLK is greater than or equal to tSKEW2, PRAE will go high (after one RCLK cycle plus tPRAES). If tSKEW2 is not met, then PRAE will assert 1 or more RCLK cycles. ___________ If the time between a rising edge of WCLK to the rising edge of RCLK is greater than or equal to tSKEW1, QRDY will go low (after two RCLK cycle plus tEMPTY). If tSKEW1 is not met, then QRDY will assert 1 or more RCLK cycles. NOTES: DRDY PRAF HALF PRAE QRDY Q 71 - 0 REN RCS RCLK D 71 - 0 WEN WCLK FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII NOVEMBER 2002 Page 39 of 39 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. tDS tENS 4. 5. 3. 2. 1. DW1 tOHZ DWD tDH tOE DW1 tSKEW1 tENS tFULL tENH tA 1 DW2 DW3 tA 2 tFULL DWx+1 tSKEW2 tA 1 DWx+2 2 tPRAFS DWx+3 DW[(D-1)/2+1] DW[D-y+1] tPRAES DW[D-y+2] DW[D-1] tA ___________ DW[D-y] ___________ tA tENS ____________ DW[D-y-1] 2 ____________ tHALF DW[(D-1)/2+2] tA 1 DWD tEMPTY ________ ___________ y = PRAE Offset, x = PRAF offset. D = maximum queue depth. Please refer to Table 7 for Depth. ___________ LOAD = High, RCS= Low ____________ Diagram 7. Read Timing (FWFT Mode) If the time between a rising edge of RCLK to the rising edge of WCLK is greater than or equal to tSKEW2, PRAF will go high (after one WCLK cycle plus tPRAFS) If tSKEW2 is not met, then PRAF will assert 1 or more WCLK cycles. If the time between a rising edge of RCLK to the rising edge of WCLK is greater than or equal to tSKEW1, DRDY will go low (after one WCLK cycle plus tFULL) . If tSKEW1 is not met, then DRDY will assert 1 or more WCLK cycles. NOTES: DRDY PRAF HALF PRAE QRDY Q 71 - 0 OE REN RCLK D71 - 0 WEN WCLK FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII NOVEMBER 2002 Page 40 of 40 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. tDS tENS 4. 5. 3. 2. 1. DW1 tRCSS DWD tDH tSKEW1 tENS tFULL tRCSHZ tRCSH tENH DW2 tRCSLZ 1 DW3 tA 2 tFULL DWx+2 tSKEW2 tA DWx+3 tPRAFS DWx+4 DW[(D-1)/2+1] tPRAES DW[D-y+1] DW[D-y+2] DW[D-1] tA ___________ DW[D-y] ___________ tA ____________ DW[D-y-1] ____________ tHALF DW[(D-1)/2+2] tA tENS DWD tEMPTY ______ ___________ y = PRAE Offset, x = PRAF offset. D = maximum queue depth. Please refer to Table 7 for Depth. ___________ LOAD = High, OE = Low. ____________ Diagram 8. Read Cycle and Read Chip Select Timing (FWFT Mode) If the time between a rising edge of RCLK to the rising edge of WCLK is greater than or equal to tSKEW2, PRAF will go high (after one WCLK cycle plus tPRAFS) If tSKEW2 is not met, then PRAF will assert 1 or more WCLK cycles. If the time between a rising edge of RCLK to the rising edge of WCLK is greater than or equal to tSKEW1, DRDY will go low (after one WCLK cycle plus tFULL) . If tSKEW1 is not met, then DRDY will assert 1 or more WCLK cycles. NOTES: DRDY PRAF HALF PRAE QRDY Q 71 - 0 RCS REN RCLK D71 - 0 WEN WCLK FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII NOVEMBER 2002 Page 41 of 41 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII RCLK 1 tENS tENH 2 tRETS tENS tENH REN tA Q 71 - 0 tA DWi DWi+1 tA DW1 DW2 tSKEW2 WCLK 1 2 tRETS WEN tENS tENH RET tEMPTY tEMPTY EMPTY tPRAES PRAE tHALF HALF tPRAFS PRAF NOTES: 1. 2. 3. 4. Upon completion of retransmit setup, a read operation can begin only after EMPTY returns high. OE = Low, RCS = Low. DWi = Words written to the queue after MRST . Where i = 1,2,3... depth. Upon reset completion, there must be more than 2 words written to the queue for a retransmit setup to be valid. Diagram 9. Retransmit Timing (Standard Mode) 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 42 of 42 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII RCLK 1 t ENS t ENH 2 t RETS 4 3 t ENS t ENH REN tA Q 71 - 0 DW i DW i+1 tA DW 1 tA DW 2 tA DW 3 DW 4 t SKEW2 W CLK 1 2 t RETS W EN t ENS t ENH RET t EM PTY t EM PTY QRDY t PRAES PRAE t HALF HALF t PRAFS PRAF NOTES: 1. 2. 3. 4. 5. Upon completion of retransmit setup, a read operation can begin only after QRDY returns low. OE = Low, RCS = Low. DWi = Words written to the queue after MRST . Where i = 1,2,3... depth. Upon reset completion, there must be more than 2 words written to the queue for a retransmit setup to be valid. Please refer to Table 8 for Depth. Diagram 10. Retransmit Timing (FWFT Mode) 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 43 of 43 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII RCLK 1 2 3 tENS tENH REN tA Q 71- 0 tA tA DWi+1 DWi DW1 tA DW2 tA DW3 DW4 tSKEW2 WCLK 1 2 tRETS WEN tENS tENH RET EMPTY tPRAES PRAE tHALF HALF tPRAFS PRAF NOTES: 1. 2. 3. 4. 5. 6. If the part is empty at the point of retransmit, the Empty Flag ( EMPTY ) will be updated based on RCLK (Retransmit Clock cycle). Valid data will appear on the output. OE = Low, RCS = Low; enables data to be read on outputs Q71 - 0. DW1= first word written to the queue after Master Reset; DW2= second word written to the queue after Master Reset. No more than D-2 may be written to the queue between reset (Master or Partial) and retransmit setup. Therefore, FULL will be high throughout the retransmit setup procedure. Please refer to Table 7 for Depth. There must be at least two words written to zero latency retransmit from the queue before a retransmit operation can be invoked. RETZL is set Low during MRST . Diagram 11. Zero Latency Retransmit Timing (Standard Mode) 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 44 of 44 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII RCLK 1 2 3 4 5 tENH tENS REN tA tA DWi Q 71 - 0 tA DW i+1 DW1 tA DW2 tA tA DW3 DW4 DW5 tSKEW2 WCLK tRETS WEN tENS tENH RET QRDY tPRAES PRAE tHALF HALF tPRAFS PRAF NOTES: 1. 2. 3. 4. 5. 6. If the part is empty at the point of retransmit, the output ready flag ( QRDY ) will be updated based on RCLK (Retransmit Clock cycle). Valid data will appear on the output. No more than D-2 words maybe written to the queue between reset (Master or Partial) and retransmit setup. Therefore, DRDY will be low throughout the retransmit setup procedure. Please refer to Table 8 for Depth. OE = Low, RCS = Low. DW1, DW2, DW3 = first, second and third words written to the queue after Master Reset. There must be at least two words written to the queue before a retransmit operation can be invoked. RETZL is set low during MRST . Diagram 12. Zero Latency Retransmit Timing (FWFT Mode) 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 45 of 45 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII SCLK tENS tENH tENH tLOADH tLOADH SDEN tLOADS LOAD tDS SDI tDH BIT 0 BIT MSB BIT 0 BIT MSB PRAF offset PRAE offset *Refer to Table 13 Diagram 13. Serial Loading of Programmable Flag Registers (Standard and FWFT Mode) MSB FQV72100 FQV7290 FQV7280 FQV7270 FQV7260 FQV7250 FQV7240 FQV7230 15 14 13 12 11 10 9 8 Table 13. Reference Table for Diagram 13 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 46 of 46 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII tWCLK tWCLKH tWCLKL WCLK tLOADS tLOADH tLOADH LOAD tENS tENH tENH WEN tDS tDH tDS tDH D 71 - 0 PRAE offset PRAF offset Diagram 14. Parallel Loading of Programmable Flag Registers (Standard and FWFT Mode) tRCLK tRCLKH tRCLKL RCLK tLOADS tLOADH tLOADH tENH tENH LOAD tENS REN tA Q 71 - 0 tA Output Register Data PRAE offset PRAF offset NOTES: 1. OE = Low, RCS = Low. Diagram 15. Parallel Read of Programmable Flag Registers (Standard and FWFT Mode) 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 47 of 47 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII tWCLKH tWCLKL WCLK 1 tENS 2 1 2 tENH WEN tPRAFS PRAF tPRAFS D-(x+1) words in Queue D - x words in Queue D - ( x + 1 ) words in Queue tSKEW2 RCLK tENS tENH REN NOTES: ___________ 1. 2. 3. 4. x = PRAF offset. D = maximum queue depth. Please refer to Table 7 for Depth. ___________ If the time between a rising edge of RCLK to the rising edge of WCLK is greater than or equal to tSKEW2, PRAF will go high (after on WCLK cycle ___________ plus tPRAFS). If tSKEW2 is not met, then PRAF will assert 1 or more WCLK cycles. ___________ PRAF synchronizes to the rising edge of WCLK only. Diagram 16. Synchronous Programmable Almost-Full Flag Timing (Standard and FWFT Mode) tWCLKH tWCLKL WCLK tWCLKH tWCLKL WEN y words in Queue(2) ; y+1 words in Queue(3) PRAE tSKEW2 RCLK tPRAES 1 y words in Queue(2) ; y+1 words in Queue(3) y+1 words in Queue(2) ; y+2 words in Queue(3) tPRAES 2 1 tENS 2 tENH REN NOTES: 1. 2. 3. 4. 5. y = PRAE offset. For Standard Mode. For FWFT Mode. If the time between a rising edge of WCLK to the rising edge of RCLK is greater than or equal to tSKEW2, PRAE will go high (after one RCLK cycle plus tPRAES). If tSKEW2 is not met, then PRAE will assert 1 or more RCLK cycles. PRAE synchronizes to the rising edge of RCLK only. Diagram 17. Synchronous Programmable Almost-Empty Flag Timing (Standard and FWFT Mode) 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 48 of 48 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII tWCLKH tWCLKL WCLK tENS tENH WEN tPRAFA D - x words in Queue D - ( x + 1) words in Queue PRAF D - ( x + 1) words in Queue tPRAFA RCLK tENS REN NOTES: 1. 2. 3. 4. x = PRAF offset. D = maximum queue depth. Please refer to Table 8 for Depth. PRAF is asserted to low on WCLK transition and reset to high on RCLK transition. Select this mode by setting SFM low during Master Reset. Diagram 18. Asynchronous Programmable Almost-Full Flag Timing (Standard and FWFT Mode) tWCLKH tWCLKL WCLK tENS tENH WEN tPRAEA PRAE y+1 words in Queue(2); y+2 words in Queue (3) y words in Queue(2); y+1 words in Queue(3) y words in Queue(2); y+1 words in Queue(3) tPRAEA RCLK tENS REN NOTES: 1. 2. 3. 4. 5. y = PRAE offset. For Standard Mode. For FWFT Mode. PRAE is asserted to low on RCLK transition and reset to high on WCLK transition. Select this mode by setting SFM low during Master Reset. Diagram 19. Asynchronous Programmable Almost-Empty Flag Timing (Standard and FWFT Mode) 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 49 of 49 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII tWCLKH tWCLKL WCLK tENS tENH WEN D/2 + 1 words in Queue(1); [(D+1)/2 + 1] words in Queue(2) tHALF HALF D/2 words in Queue(1); [(D+1)/2] words in Queue(2) tHALF D/2 words in Queue(1); [(D+1)/2] words in Queue(2) RCLK tENS REN NOTES: 1. 2. 3. For Standard Mode. For FWFT Mode. Please refer to Table 7 for Depth. Diagram 20. Half-Full Flag Timing (Standard and FWFT Mode) 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2002 Page 50 of 50 FQV72100 * FQV7290 * FQV7280 * FQV7270 * FQV7260 * FQV7250 * FQV7240* FQV7230 FlexQTMIII Order Information: HBA Device Family Device Type Power Speed (ns) * Package** Temperature Range XX FQ XXXXX V72100 (65,536 x 72) X Low XX 6 - 166 MHz XX BB X Blank - Commercial (0C to 70C) V7290 (32,768 x 72) 7-5 - 133 MHz V7280 (16,384 x 72) 10 - 100 MHz V7270 (8,192 x 72) 15 - 66 MHz I - Industrial (-40 to 85C) V7260 (4,096 x 72) V7250 (2,048 x 72) V7240 (1,024 x 72) V7230 (512 x 72) *Speed - 6ns available only in Commercial temp (0C to 70C). Slower speeds available upon request. **Package - 256 pin Fine Pitch Ball Grid Array (BGA) Example: FQV7270L6BB FQV7260L10BBI (8k x 72, 6ns, Commercial temp) (4k x 72, 10ns, Industrial temp) USA 2107 North First Street, Suite 415 San Jose, CA 95131, USA www.hba.com Tel: 408.453.8885 Fax: 408.453.8886 3F372E (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Taiwan No. 81, Suite 8F-9, Shui-Lee Rd. Hsinchu, Taiwan, R.O.C. www.hba.com Tel: 886.3.516.9118 Fax: 886.3.516.9181 NOVEMBER 2002 Page 51 of 51