NOVEMBER 2002
Flex
Q
TMIII
FQV72100 · FQV7290 · FQV7280 · FQV7270 · FQV7260 · FQV7250 · FQV7240· FQV7230
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 1 of 16
3F372E
3.3 Volt Synchronous x 72 First-In/First-Out Queue
Memory Configuration Device Memory Configuration Device
65,536 x 72 FQV72100 4,096 x 72 FQV7260
32,768 x 72 FQV7290 2,048 x 72 FQV7250
16,384 x 72 FQV7280 1,024 x 72 FQV7240
8,192 x 72 FQV7270 512 x 72 FQV7230
Key Features
• Industry leading First-In/First-Out Queues (up to 166 MHz)
• Write cycle time of 6.0ns independent of Read cycle time (Data Setup time = 2.0ns)
• Read cycle time of 6.0ns independent of Write cycle time (Data Access time = 4.0ns)
• User selectable input and output bus-sizing
• Big Endian/Little Endian user selectable byte representation
• 3.3V power supply
• 5V input tolerant on all control and data input pins
• 5V output tolerant on all flags and data output pins
• Master Reset clears all previously programmed configurations including Write and Read pointers
• Partial Reset clears Write and Read pointers but maintains all previously programmed configurations
• First Word Fall Through (FWFT) and Standard Timing modes
• Presets for eight different Almost Full and Almost Empty offset values
• Parallel/Serial programming of PRAF and PRAE offset values
• Programmable 8-bit or 9-bit parallel programming modes for offset values
• Full, Empty, Almost Full, Almost Empty, and Half Full indicators
• PRAF and PRAE operate in either synchronous or asynchronous modes
• Asynchronous output enable tri-state data output drivers
• Synchronous Read Chip Select
• Data retransmission with programmable zero or normal latency modes
• Boundary Scan (JTAG)
• Available package: 256 - pin Fine Pitch Ball Grid Array (BGA)
• (0°C to 70°C) Commercial operating temperature available for cycle time of 6.0ns and above
• (-40°C to 85°C) Industrial operating temperature available for cycle time of 7.5ns and above
Product Description
HBA’s FlexQ™ III offers industry leading FIFO queuing bandwidth (up to 12.0 Gbps) with a wide range of memory
configurations (from 512 x 72 to 65,536 x 72). System designer has full flexibility of implementing deeper and wider queues
using FWFT mode and width expansion features. Full, Empty, and Half-Full indicators allow easy handshaking between
transmitters and receivers. User programmable Almost Full and Almost Empty (Parallel/Serial) indicators allow implementation
of virtual queue depths.
5V tolerant on all input and output pins allow easy interfacing with devices operating at higher voltage levels. Asynchronous
Output Enable pin configures the tri-state data output drivers. In addition, synchronous read chip select is also available to
control the state of data output drivers. Independent Write and Read controls provide rate-matching capability.
Master Reset clears all previous programmed configurations by providing a low pulse on MRST pin. In addition, Write and
Read pointers to the queue are initialized to zero. Partial Reset will not alter previously programmed configurations but will
initialize Write and Read pointers to zero.
In FWFT mode, first data written into the queue appears on output data bus after the specified latency period at the low to high
transition of RCLK. Subsequent reads from the queue will require asserting REN . This feature is useful when implementing
depth expansion functions. In this mode, DRDY and QRDY are used instead of FULL and EMPTY respectively.
NOVEMBER 2002
Flex
Q
TMIII
FQV72100 · FQV7290 · FQV7280 · FQV7270 · FQV7260 · FQV7250 · FQV7240· FQV7230
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 2 of 16
3F372E
Product Description (Continued)
In Standard mode, always assert REN for a read operation. FULL and EMPTY are used instead of DRDY and
QRDY respectively.
Bus matching feature is available with the following configurations:
Input Bus Width Output Bus Width
x18 x72
x36 x72
x72 x72
x72 x36
x72 x18
In addition, Endian Select is available for implementing byte re-ordering on data outputs.
Eight different default offset values are available for Almost Full ( PRAF ) and Almost Empty ( PRAE ) flags. Parallel and Serial
programming of these offset values provide total flexibility other than the pre-defined default values. Both 8-bit and 9-bit
parallel programming modes for offset values can be selected for convenience.
PRAF , PRAE , and HALF are available in either FWFT or Standard mode. In addition, PRAF and PRAE can operate in either
synchronous or asynchronous modes.
At any time, data previously read from the queue can be retransmitted by asserting RET pin at the low to high transition of
RCLK for a retransmit operation. Retransmit initializes the Read pointer to zero. Hence, all re-reads will always start from the
physical 0th (Read pointer = zero), location of the queue. Both zero and normal latency timing modes available for retransmit
operation.
These FlexQ™ III devices have low power consumption, hence minimizing system power requirements. In addition, industry
standard 256 - pin BGA is offered to save system board space.
These queues are ideal for applications such as data communication, telecommunication, graphics, multiprocessing, test
equipment, network switching, etc.
NOVEMBER 2002
Flex
Q
TMIII
FQV72100 · FQV7290 · FQV7280 · FQV7270 · FQV7260 · FQV7250 · FQV7240· FQV7230
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 3 of 16
3F372E
FQV72100
FQV7290
FQV7280
FQV7270
FQV7260
FQV7250
FQV7240
FQV7230
WRITE CLOCK (WCLK)
x72, x36, x18 DATA IN (D71 - 0)
FIRST WORD FALL THROUGH/
SERIAL DATA INPUT (FWFT/SDI)
READ CLOCK (RCLK)
x72, x36, x18 DATA OUT (Q71 - 0)
PROGRAMMABLE ALMOST-
EMPTY ( )
PARTIAL RESET ( ) MASTER RESET ( )
Block Diagram of Single Synchronous Queue
65,536 x 72 / 32,768 x 72 / 16,384 x 72 / 8,192 x 72 / 4,096 x 72 / 2,048 x 72 / 1,024 x 72 / 512 X 72
JTAG CLOCK (TCLK)
BUS
MATCHING 0
(BM0)
BUS
MATCHING 2
(BM2)
BUS
MATCHING 1
(BM1)
PRST MRST
PRAE
RETRANSMIT ( )
RET
OUTPUT ENABLE ( )
OE
READ ENABLE ( )
REN
EMPTY FLAG / OUTPUT READY
( / )
QRDY
EMPTY
FULL FLAG / INPUT READY
( / )
FULL DRDY
PROGRAMMABLE ALMOST-
FULL ( )
PRAF
READ CHIP SELECT ( )
RCS
HALF-FULL FLAG ( )
HALF
JTAG RESET ( )
TRST
JTAG MODE (TMS)
(TDO)
(TDI)ENDIAN SELECT (ES)
INTERSPERSED PARITY (IPAR)
SERIAL IN CLOCK (SCLK)
LOAD ( )
LOAD
WRITE ENABLE ( )
WEN
SERIAL DATA ENABLE ( )
SDEN
(SFM)
(PFS0)
(PFS1) )RETLZ(
Figure 1. Single Device Configuration Signal Flow Diagram
NOVEMBER 2002
Flex
Q
TMIII
FQV72100 · FQV7290 · FQV7280 · FQV7270 · FQV7260 · FQV7250 · FQV7240· FQV7230
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 4 of 16
3F372E
Offset Register
Write Control
Logic
Write Pointer
SRAM
Input Register Output Register
Flag Logic
Output
Buffer Q71-0 x72, x36, x18
x72, x36, x18
D71-0
Read Pointer
Read Control
Logic Reset Bus
Configuration
FWFT/SDIIPAR LOAD SDEN
WCLK
FWFT/SDI
SFM
PFS1
PFS0
PRAF
/
FULL DRDY
PRAE
HALF
EMPTY QRDY
/
OE
MRST PRST BM1BM2 BM0ES
RCLK
RETZ
L
RET REN
WEN
JTAG Control
(Boundary Scan)
TDOTMS TDITCK TRST RCS
Figure 2. Device Architecture
NOVEMBER 2002
Flex
Q
TMIII
FQV72100 · FQV7290 · FQV7280 · FQV7270 · FQV7260 · FQV7250 · FQV7240· FQV7230
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 5 of 16
3F372E
Q33 Q35 Q47 Q50 Q53 Q65 Q68 Q71 D71 D68 D65 D53 D50 D47 D35 D33
Q32 Q34 Q46 Q49 Q52 Q64 Q67 Q70 D70 D67 D64 D52 D49 D46 D34 D32
Q31 Q30 Q45 Q48 Q51 Q63 Q66 Q69 D69 D66 D63 D51 D48 D45 D30 D31
Q29 Q28 Q27 VCC GND VCC GND TCK TDI TDO TMS GND D27 D28 D29
Q17 Q16 Q15 VCC GND VCC GND VCC GND VCC GND VCC GND D15 D16 D17
Q14 Q13 Q12 VCC GND VCC GND VCC GND VCC GND VCC GND D12 D13 D14
Q11 Q10 Q9 VCC GND VCC GND VCC GND VCC GND VCC GND D9 D10 D11
Q62 Q61 Q60 VCC GND VCC GND VCC GND VCC GND VCC GND D60 D61 D62
Q59 Q58 Q57 VCC GND VCC GND VCC GND VCC GND VCC GND D57 D58 D59
Q56 Q55 Q54 GND VCC GND D54 D55 D56
Q44 Q43 Q42 VCC GND VCC GND VCC GND VCC GND GND BM1 D42 D43 D44
Q41 Q40 Q39 VCC GND VCC GND GND PFS1 PFS0 BM0 GND SCLK D39 D40 D41
Q38 Q37 Q36 SFM IPAR ES FWFT/SDI D36 D37 D38
Q26 Q25 Q18 Q6 Q3 Q0 D0 D3 D6 D18 D25 D26
Q24 Q21 Q19 Q7 Q4 Q1 D1 D4 D7 D19 D21 D24
Q23 Q22 Q20 Q8 Q5 Q2 RCLK WCLK D2 D5 D8 D20 D22 D23
TRST
VCC GND VCC GND VCC GND VCC
RET RETZL LOAD
HALF SDENBM2
RCS PRAE MRST PRST
WEN
PRAFEMPTYOE
REN FULL
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
1 2 3 4 5 6 7 8 9 10111213141516
A1 BALL PAD CORNER
PBGA -256 (Drw No: BB-01A; Order code: BB)
Top View
Figure 3. Device Pin Out
NOVEMBER 2002
Flex
Q
TMIII
FQV72100 · FQV7290 · FQV7280 · FQV7270 · FQV7260 · FQV7250 · FQV7240· FQV7230
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 6 of 16
3F372E
Pin # Pin Name Pin Symbol Input/Output Description
P9 Master Reset MRST Input
Master Reset is required to initialize Write and Read
pointers to the first position of the queue by setting
MRST low. In Standard mode, FULL and PRAF will go
high; EMPTY and PRAE will go low. In FWFT mode,
DRDY will go low and QRDY will go high. PRAF
and PRAE will go to the same state as Standard mode. In
both modes, all data outputs will go low. Previous
programmed configurations will not be maintained.
P10 Partial Reset PRST Input
Partial Reset is required to initialize Write and Read
pointers to the first position of the queue by setting PRST
low. In Standard mode, FULL and PRAF will go high;
EMPTY and PRAE will go low. In FWFT mode,
DRDY will go low and QRDY will go high. PRAF and
PRAE will go to the same state as Standard mode. In
both modes, all data outputs will go low. Previous
programmed configurations will be maintained.
T10 Write Clock WCLK Input
Writes data into queue during low to high transitions of
WCLK if WEN is set to low.
R10 Write Enable WEN Input
Controls write operation into queue or offset registers
during low to high transition of WCLK.
N12 Load Enable LOAD Input
During Master Reset, set LOAD low to select parallel
programming or one of eight default offset values. Set
LOAD high to select serial programming or one of eight
default offset values. After Master Reset, LOAD controls
write/read to/from offset registers during low to high
transition of WCLK/RCLK respectively. Use in
conjunction with WEN /REN .
M9 Default
Programming 1 PFS1 Input
During Master Reset, select one of eight default offset
values. Use in conjunction with LOAD and PFS0.
M10 Default
Programming 0 PFS0 Input
During Master Reset, select one of eight default offset
values. Use in conjunction with LOAD and PFS1.
A9, A10, A11, A12, A13,
A14, A15, A16, B9, B10,
B11, B12, B13, B14,
B15, B16, C9, C10, C11,
C12, C13, C14, C15,
C16, D14, D15, D16,
E14, E15, E16, F14, F15,
F16, G14, G15, G16,
H14, H15, H16, H14, J
15, J16, K14, K15, K16,
L14, L15, L16, M14,
M15, M16, N14, N15,
N16, P11, P12, P13, P14,
P15, P16, R11, R12, R13,
R14, R15, R16, T11,
T12, T13, T14, T15, T16
Data Inputs D71-0 Input 72 - bit wide input data bus.
T8 Read Clock RCLK Input
Reads data from queue during low to high transitions of
RCLK if REN is set to low.
Table 1. Pin Descriptions
NOVEMBER 2002
Flex
Q
TMIII
FQV72100 · FQV7290 · FQV7280 · FQV7270 · FQV7260 · FQV7250 · FQV7240· FQV7230
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 7 of 16
3F372E
Pin # Pin Name Pin Symbol Input/Output Description
T7 Read Enable REN Input
Controls read operation from queue or offset registers
during low to high transition of RCLK.
P7 Read Chip
Select RCS Input
Setting RCS low during the low to high transition of
RCLK activates the data output drivers. Setting RCS
high during the low to high transition of RCLK deactivates
the data output drivers. OE must be set low when using
RCS to control the state of the drivers.
R7 Output Enable OE Input
Setting OE low activates the data output drivers. Setting
OE high deactivates the data output drivers (High-Z).
A1, A2, A3, A4, A5, A6,
A7, A8, B1, B2, B3, B4,
B5, B6, B7, B8, C1, C2,
C3, C4, C5, C6, C7, C8,
D1, D2, D3, E1, E2, E3,
F1, F2, F3, G1, G2, G3,
H1, H2, H3, J1, J2, J3,
K1, K2, K3, L1, L2, L3,
M1, M2, M3, N1, N2,
N3, P1, P2, P3, P4, P5,
P6, R1, R2, R3, R3, R4,
R5, R6, T1, T2, T3, T4,
T5, T6
Data Outputs Q71-0 Output 72 - bit wide output data bus.
N11
First Word Fall
Through/Serial
Data Input
FWFT/SDI Input
Selects FWFT timing or Standard timing mode during
Master Reset. After Master Reset, if serial programming
is selected ( LOAD = high), FWFT/SDI is used as the
serial data input for the offset registers. Serial data is
written during the low to high transition of WCLK. Use in
conjunction with SDEN .
M13 Serial Clock SCLK Input
During serial programming, SCLK is used to program
offset values through SDI.
N13 Serial Data Input
Enable SDEN Input
If serial programming is selected, setting SDEN and
LOAD low enables serial data input to be written into
offset registers during the low to high transition of SCLK.
N7 Bus Matching 2 BM2 Input
During Master Reset, select one of five input and output
bus width configurations. Use in conjunction with BM1
and BM0.
L13 Bus Matching 1 BM1 Input
During Master Reset, select one of five input and output
bus width configurations. Use in conjunction with BM2
and BM0.
M11 Bus Matching 0 BM0 Input
During Master Reset, select one of five input and output
bus width configurations. Use in conjunction with BM2
and BM1.
N9 Endian Select ES Input
During Master Reset, set ES high to select byte re-ordering
on data outputs or ES low to select no byte re-ordering on
data outputs.
N4 Retransmit RET Input
Data previously read from the queue can be retransmitted
by asserting RET pin at the low to high transition of
RCLK for a retransmit operation. Retransmit initializes
the Read pointer to zero. Hence, all re-reads will always
start from the physical 0th (Read pointer = zero) location of
the queue.
Table 1. Pin Descriptions (Continued)
NOVEMBER 2002
Flex
Q
TMIII
FQV72100 · FQV7290 · FQV7280 · FQV7270 · FQV7260 · FQV7250 · FQV7240· FQV7230
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 8 of 16
3F372E
Pin # Pin Name Pin Symbol Input/Output Description
N5 Zero Latency
Retransmit RETZL Input
During Master Reset, set RETZL low to select zero
latency retransmit or RETZL high to select normal
latency retransmit.
T9 Full/Data Input
Ready Flag FULL /DRDY Output
Queue is full when FULL goes low during the low to
high transition of WCLK. This prohibits further
writes into the queue. In FWFT mode, queue is full
when DRDY goes high during low to high transition
of WCLK. This prohibits further writes into the
queue.
R8
Empty/Data
Output Ready
Flag
EMPTY / QRDY Output
Queue is empty when EMPTY goes low during the
low to high transition of RCLK. This prohibits further
reads from the queue. In FWFT mode, queue is empty
when QRDY goes high during the low to high
transition of RCLK. This prohibits further reads from
the queue.
N8 Interspersed
Parity IPAR Input
During Master Reset, set IPAR low to select 9-bit
parallel programming mode or IPAR high to select 8-
bit parallel programming mode.
N6
Synchronous
Partial Flag
Mode
SFM Input
During Master Reset, set SFM high to select
Synchronous Partial Flag mode or SFM low to select
Asynchronous Partial Flag mode.
R9 Almost Full PRAF Output
Queue is almost full when PRAF goes low during the
low to high transition of WCLK. Default (Full-offset)
or programmed offset values determine the status of
PRAF .
P8 Almost Empty PRAE Output
Queue is almost empty when PRAE goes low during
the low to high transition of RCLK. Default
(Empty+offset) or programmed offset values
determine the status of PRAE .
N10 Half Full HALF Output
Queue is more than half full when HALF goes low.
Triggered by both WCLK and RCLK.
D4, D6, E4, E6,
E8, E10, E12, F4,
F6, F8, F10, F12,
G4, G6, G8, G10,
G12, H4, H6, H8,
H10, H12, J4, J6,
J8, J10, J12, K4,
K6, K8, K10,
K12, L4, L6, L8,
L10, M4, M6
Power Vcc N/A 3.3V power supply.
D5, D7, D13, E5,
E7, E9, E11, E13,
F5, F7, F9, F11,
F13, G5, G7, G9,
G11, G13, H5,
H7, H9, H11,
H13, J5, J7, J9,
J11, J13, K5, K7,
K9, K11, K13,
L5, L7, L9, L11,
L12, M5, M7,
M8, M12
Ground GND N/A 0V Ground.
Table 1. Pin Description (Continued)
NOVEMBER 2002
Flex
Q
TMIII
FQV72100 · FQV7290 · FQV7280 · FQV7270 · FQV7260 · FQV7250 · FQV7240· FQV7230
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 9 of 16
3F372E
Pin # Pin Name Pin Symbol Input/Output Description
D8 JTAG Clock TCK Input
Clock for JTAG function. TMS and TDI are loaded
during low to high transitions of TCK. TDO is loaded
during high to low transitions of TCK.
D10 JTAG Reset TRST Input
Reset control for JTAG function. An asynchronous
input for the JTAG controller.
D12 JTAG Mode
Selection TMS Input
Mode select for JTAG function. TMS bits are loaded
serially during low to high transitions of the TCK.
D9 Test Data Input TDI Input Serial data input for JTAG function. TDI is loaded
during low to high transitions of the TCK.
D11 Test Data
Output TDO Output
Serial data output for JTAG function. TDO is
unloaded during high to low transitions of the TCK.
During SHIFT-DR and SHIFT-IR operations, TDO
bus will be tri-stated.
Table 1. Pin Description (Continued)
NOVEMBER 2002
Flex
Q
TMIII
FQV72100 · FQV7290 · FQV7280 · FQV7270 · FQV7260 · FQV7250 · FQV7240· FQV7230
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 10 of 16
3F372E
Symbol Rating Com’l & Ind’l Unit
VTERM Terminal Voltage with
respect to GND -0.5 to + 4.5 V
TSTG Storage Temperature -55 to +125 °C
IOUT DC Output Current -50 to +50 mA
NOTES:
Absolute Max Ratings are for reference only. Permanent damage to the device may
occur if extended period of operation is outside this range. Standard operation should
fall within the Recommended Operating Conditions.
Table 2. Absolute Maximum Ratings
FQV72100, FQV7290, FQV7280, FQV7270,
FQV7260, FQV7250, FQV7240, FQV7230
Commercial
Clock = 6ns, 7.5ns, 10ns,
15ns
Industrial
Clock = 7.5ns, 10ns, 15ns
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Unit
Recommended Operating Conditions
Vcc Supply Voltage Com’l / Ind’l 3.15 3.3 3.45 3.15 3.3 3.45 V
GND Supply Voltage 0 0 0 0 0 0 V
VIH Input High Voltage Com’l /
Ind’l 2.0 - 5.5 2.0 - 5.5 V
VIL Input Low Voltage Com’l /
Ind’l - - 0.8 - - 0.8 V
TA Operating Temperature
Commercial 0 - 70 0 - 70 °C
TA Operating Temperature
Industrial -40 - 85 -40 - 85 °C
DC Electrical Characteristics
ILI(1) Input Leakage Current (any
input) -1 - 1 -1 - 1 µA
ILO Output Leakage Current -10 - 10 -10 - 10 µA
VOH Output Logic “1” Voltage,
IOH=-2mA 2.4 - - 2.4 - - V
VOL Output Logic “0” Voltage, IOL
= 8mA - - 0.4 - - 0.4 V
Power Consumption
Icc1(2,3) Active Power Supply Current - - 40 - - 40 mA
Icc2(4) Standby Current - - 15 - - 15 mA
Table 3. DC Specifications
NOVEMBER 2002
Flex
Q
TMIII
FQV72100 · FQV7290 · FQV7280 · FQV7270 · FQV7260 · FQV7250 · FQV7240· FQV7230
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 11 of 16
3F372E
Capacitance at 100MHz Ambient Temperature (25°C)
Symbol Parameter Conditions Max. Unit
CIN(2) Input Capacitance VIN= 0V 10 pF
COUT(2,4) Output Capacitance VOUT= 0V 10 pF
NOTES:
1. Measurement with 0.4<=VIN<=Vcc
2. With output tri-stated ( OE = High)
3. Icc(1,2) is measured with WCLK and RCLK at 20 MHz
4. Design simulated, not tested.
Table 3. DC Specifications (Continued)
NOVEMBER 2002
Flex
Q
TMIII
FQV72100 · FQV7290 · FQV7280 · FQV7270 · FQV7260 · FQV7250 · FQV7240· FQV7230
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 12 of 16
3F372E
Commercial Commercial & Industrial
FQV72100-6
FQV7290-6
FQV7280-6
FQV7270-6
FQV7260-6
FQV7250-6
FQV7240-6
FQV7230-6
FQV72100-7.5
FQV7290-7.5
FQV7280-7.5
FQV7270-7.5
FQV7260-7.5
FQV7250-7.5
FQV7240-7.5
FQV7230-7.5
FQV72100-10
FQV7290-10
FQV7280-10
FQV7270-10
FQV7260-10
FQV7250-10
FQV7240-10
FQV7230-10
FQV72100-15
FQV7290-15
FQV7280-15
FQV7270-15
FQV7260-15
FQV7250-15
FQV7240-15
FQV7230-15
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
fS Clock Cycle Frequency - 166 - 133 - 100 - 66 MHz
tA Data Access Time 1 4 2 5 2 6.5 2 10 ns
tWCLK Write Clock Cycle Time 6 - 7.5 - 10 - 15 - ns
tWCLKH Write Clock High Time 2.5 - 3.5 - 4.5 - 6 - ns
tWCLKL Write Clock Low Time 2.5 - 3.5 - 4.5 - 6 - ns
tRCLK Read Clock Cycle Time 6 - 7.5 - 10 - 15 - ns
tRCLKH Read Clock High Time 2.5 - 3.5 - 4.5 - 6 - ns
tRCLKL Read Clock Low Time 2.5 - 3.5 - 4.5 - 6 - ns
tDS Data Set-up Time 2.0 - 2.5 - 3.5 - 4 - ns
tDH Data Hold Time 0.5 - 0.5 - 0.5 - 1 - ns
tENS Enable Set-up Time 2.0 - 2.5 - 3.5 - 4 - ns
tENH Enable Hold Time 0.5 - 0.5 - 0.5 - 1 - ns
tRST Reset Pulse Width(1) 8 - 10 - 10 - 15 - ns
tRSTS Reset Set-up Time 10 - 15 15 - 15 - ns
tRSTR Reset Recovery Time 10 - 10 - 10 - 15 - ns
tRSTF Reset to Flag and Output Time - 10 - 15 - 15 - 15 ns
tOLZ Output Enable to Output in Low-Z(1) 0 - 0 - 0 - 0 - ns
tOE Output Enable to Output Valid 2 4 2 6 2 6 2 8 ns
tOHZ Output Enable to Output in High-Z(1) 2 4 2 6 2 6 2 8 ns
tFULL Write Clock to Full Flag - 4 - 5 - 6.5 - 10 ns
tEMPTY Read Clock to Empty Flag - 4 - 5 - 6.5 - 10 ns
tPRAFS Write Clock to Synchronous Almost-Full
Flag - 4 - 5 - 6.5 - 10 ns
tPRAES Read Clock to Synchronous Almost-
Empty Flag - 4 - 5 - 6.5 - 10 ns
tRCSS RCS Setup Time 2 - 3.5 - 3.5 - 5 - ns
tRCSH RCS Hold Time 0.5 - 0.5 - 0.5 - 1 - ns
tRCSLZ RCLK to Active from High-Z 2 4 1 6.5 1 6.5 1 10 ns
tRCSHZ RCLK to High-Z 2 4 1 6.5 1 6.5 1 10 ns
Table 4. AC Electrical Characteristics
NOVEMBER 2002
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3F372E
Commercial Commercial & Industrial
FQV72100-6
FQV7290-6
FQV7280-6
FQV7270-6
FQV7260-6
FQV7250-6
FQV7240-6
FQV7230-6
FQV72100-7.5
FQV7290-7.5
FQV7280-7.5
FQV7270-7.5
FQV7260-7.5
FQV7250-7.5
FQV7240-7.5
FQV7230-7.5
FQV72100-10
FQV7290-10
FQV7280-10
FQV7270-10
FQV7260-10
FQV7250-10
FQV7240-10
FQV7230-10
FQV72100-15
FQV7290-15
FQV7280-15
FQV7270-15
FQV7260-15
FQV7250-15
FQV7240-15
FQV7230-15
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
tSKEW1
Skew time between Read Clock &
Write Clock for Full Flag / Empty
Flag
4 - 5 - 7 - 9 - ns
tSKEW2 Skew time between Read Clock &
Write Clock for PRAE & PRAF 6 - 7 - 10 - 14 - ns
tLOADS Load Setup Time 2.0 - 2.5 - 3.5 - 4 - ns
tLOADH Load Hold Time 0.5 - 0.5 - 0.5 - 1 - ns
tRETS Retransmit Setup Time 2.5 - 3.5 - 3.5 - 4 - ns
tHALF Clock to HALF - 12 - 12.5 - 16 - 20 ns
tPRAFA Write Clock to Asynchronous
Programmable Almost-Full Flag - 12 - 12.5 - 16 - 20 ns
tPRAEA Read Clock to Asynchronous
Programmable Almost-Empty Flag - 12 - 12.5 - 16 - 20 ns
NOTES:
1. Design simulated, not tested.
Table 4. AC Electrical Characteristics (Continued)
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3F372E
Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 3ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load, clock = 6ns, 7.5 ns Refer to Figure 4
Output Load*, clock = 10ns, 15ns Refer to Figure 5 & 6
* Include jig and scope capacitances
Table 5. AC Test Condition
20 30 50 80 100 200
1
2
3
4
Capacitance (pF)
t
CD (Typical, ns)
Figure 6. Lumped Capacitive Load
D.U.T.
510Ω
30pF*
330Ω
3.3V
Figure 5. Output Load
*Includes jig and scope capacitances.
for clock = 10ns, 15ns
Vcc/2
50 Ω
Z0 = 50 Ω
I/O
Figure 4. AC Test Load
for clock = 6ns, 7.5ns
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3F372E
Pin Functions
MRST Master Reset is required to initialize Write and Read pointers to the first position of the queue by setting
MRST low. In Standard mode, FULL and PRAF will go high, EMPTY and PRAE will go low. In
FWFT mode, DRDY will go low and QRDY will go high. PRAF and PRAE will go to the same state
as Standard mode. In both modes, all data outputs will go low, and previous programmed configurations
will not be maintained.
PRST Partial Reset is required to initialize Write and Read pointers to the first position of the queue by setting
PRST low. In Standard mode, FULL and PRAF will go high. EMPTY and PRAE will go low. In
FWFT mode, DRDY will go low and QRDY will go high. PRAF and PRAE will go to the same state
as Standard mode. In both modes, all data outputs will go low, and previously programmed
configurations will be maintained.
WCLK Writes data into queue during low to high transitions of WCLK if WEN is activated. Synchronizes
FULL /DRDY and PRAF flags. WCLK and RCLK are independent of each other.
WEN Controls write operation into queue or offset registers during low to high transition of WCLK.
LOAD During Master Reset, set LOAD low to select parallel programming or one of eight default offset values.
Set LOAD high to select serial programming or one of eight default offset values. After Master Reset,
LOAD controls write/read, to/from offset registers during low to high transition of WCLK/RCLK
respectively for parallel programming. Use in conjunction with WEN /REN . During programming of
offset registers, PRAF and PRAE flag status is invalid. For Serial programming, LOAD is used to
enable serial loading of offset registers together with SDEN . Refer to Figure 7 for details.
PFS1 During Master Reset, select one of eight default offset values. Use in conjunction with LOAD and PFS0.
Refer to Table 11 for details.
PFS0 During Master Reset, select one of eight default offset values. Use in conjunction with LOAD and PFS1.
Refer to Table 11 for details.
D71..0 72 - bit wide input data bus.
RCLK Reads data from queue during low to high transitions of RCLK if REN is set low. Synchronizes the
EMPTY /QRDY and PRAE flags. RCLK and WCLK are independent of each other.
REN Reads data from queue during low to high transitions of RCLK if REN is set to low. This also advances
the Read pointer of the queue.
RCS
Setting RCS low during the low to high transition of RCLK activates the data output drivers. Setting
RCS high during the low to high transition of RCLK deactivates the data output drivers. OE must be
set low when using RCS to control the state of the drivers.
OE Setting OE low activates the data output drivers. Setting OE high deactivates the data output drivers
(High-Z). OE does not control advancement of Read pointer.
Q71..0 72 - bit wide output data bus.
FWFT/SDI Selects First Word Fall Through timing or Standard timing mode during Master Reset. After Master
Reset, if serial programming is selected ( LOAD = high), FWFT/SDI is used as the serial data input for
the offset registers. Serial data is written during the low to high transition of WCLK. Use in conjunction
with SDEN . In FWFT mode, DRDY and QRDY is used instead of FULL and EMPTY . In Standard
mode, FULL and EMPTY is used instead of DRDY and QRDY . Refer to Table 8 & 9 for all flags
status.
SCLK
During serial programming, SCLK is used to program offset values through SDI.
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3F372E
Pin Functions (Continued)
SDEN If serial programming is selected, setting SDEN and LOAD low enables serial data to be written
into offset registers during the low to high transition of SCLK. During serial programming, PRAF
and PRAE flags status is invalid. Refer to Figure 7 for details.
BM2 During Master Reset, select one of five input and output bus width configurations. Use in
conjunction with BM1 and BM0. Refer to Table 10 for details.
BM1 During Master Reset, select one of five input and output bus width configurations. Use in
conjunction with BM2 and BM0. Refer to Table 10 for details.
BM0 During Master Reset, select one of five input and output bus width configurations. Use in
conjunction with BM2 and BM1. Refer to Table 10 for details.
ES During Master Reset, set ES high to select byte re-ordering on data outputs or set ES low to select no
byte re-ordering on data outputs. ES must be static throughout device operation. Refer to Table 10
for details.
RET Data previously read from the queue can be retransmitted by asserting RET pin at the low to high
transition of RCLK for a retransmit operation. Retransmit initializes the Read pointer to zero. Hence,
all re-reads will always start from the physical 0th (Read pointer = zero) location of the queue. Refer
to Diagram 9 & 10 for details.
RETZL During Master Reset, set RETZL low to select zero latency retransmit. Set RETZL high to select
normal latency retransmit.
FULL / DRDY In Standard mode, queue is full when FULL goes low during the low to high transition of WCLK.
This prohibits further writes into the queue and prevents advancement of Write pointer. In FWFT
mode, queue is full when DRDY goes low during the low to high transition of WCLK. This
prohibits further writes into the queue and prevents advancement of Write pointer. Refer to Table 8
& 9 for behavior of FULL / DRDY .
EMPTY / QRDY In Standard mode, queue is empty when EMPTY goes low during the low to high transition of
RCLK. This prohibits further reads from the queue and prevents advancement of Read pointer. In
FWFT mode, queue is empty when QRDY goes low during the low to high transition of RCLK.
This prohibits further reads from the queue and prevents advancement of Read pointer. Refer to
Table 8 & 9 for behavior of EMPTY / QRDY .
IPAR During Master Reset, set IPAR low to select 9-bit parallel programming mode or set IPAR high to
select 8-bit parallel programming mode. In 9-bit mode, 9-bit wide data input / output bus width is
used for storing / fetching offset values. In 8-bit mode, 8-bit wide data input / output bus is used for
storing / fetching offset values.
SFM During Master Reset, set SFM high to select Synchronous Partial Flag mode or set SFM low to select
Asynchronous Partial Flag mode. In Synchronous mode, PRAF and PRAE are synchronous to
WCLK and RCLK respectively. In Asynchronous mode, WCLK synchronizes the assertion of
PRAF and de-assertion of PRAE . RCLK synchronizes the assertion of PRAE and de-assertion of
PRAF .
PRAF Queue is almost full when PRAF goes low during the low to high transition of WCLK. Default
(Full-offset) or programmed offset values determine the status of PRAF . Refer to Table 8 & 9 for
behavior of PRAF .
PRAE Queue is almost empty when PRAE goes low during the low to high transition of RCLK. Default
(Empty+offset) or programmed offset values determine the status of PRAE . Refer to Table 8 & 9
for behavior of PRAE .
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3F372E
Pin Functions (Continued)
HALF Queue is more than half full when HALF goes low during the low to high transition of WCLK.
Queue is less than half full when HALF goes high during low to high transition of RCLK when.
Refer to Table 8 & 9 for details.
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3F372E
LOAD WEN REN SDEN WCLK RCLK SCLK
FQV72100
FQV7290
FQV7280
FQV7270
FQV7260
FQV7250
FQV7240
FQV7230
Selection / Sequence
0 0 1 1
X X
Parallel write to offset
registers:
Empty Offset
Full Offset
Parallel write
to registers:
1. PRAE
2. PRAF
0 1 0 1 X
X
Parallel read from offset
registers:
Empty Offset
Full Offset
Parallel read
from registers:
1. PRAE
2. PRAF
0 1 1 0 X X
Serial shift into registers:
32 bits for the FQV72100
30 bits for the FQV7290
28 bits for the FQV7280
26 bits for the FQV7270
24 bits for the FQV7260
22 bits for the FQV7250
20 bits for the FQV7240
18 bits for the FQV7230
1 bit for each rising SCLK edge
Starting with Empty Offset (Low Byte)
Ending with Full Offset (High Byte)
X 1 1 1 X X X
No Operation
1 0 X X
X X Write Memory
1 X 0 X X
X
Read Memory
1 1 1 X X X X No Operation
Figure 7. Programmable Flag Offset Programming Sequence
(FQV72100, FQV7290, FQV7280, FQV7270, FQV7260, FQV7250, FQV7240 and FQV7230)
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3F372E
Device PRAF Programming (bits) PRAE Programming (bits)
D/Q15 - 0 Non-IPAR D/Q15 - 0 Non-IPAR
FQV72100 D/Q16 – 9 & D/Q7 – 0 IPAR D/Q16 – 9 & D/Q7 – 0 IPAR
D/Q14 - 0 Non-IPAR D/Q14 - 0 Non-IPAR
FQV7290 D/Q15 – 9 & D/Q7 – 0 IPAR D/Q15 – 9 & D/Q7 – 0 IPAR
D/Q13 - 0 Non-IPAR D/Q13 - 0 Non-IPAR
FQV7280 D/Q14 – 9 & D/Q7 – 0 IPAR D/Q14 – 9 & D/Q7 – 0 IPAR
D/Q12 - 0 Non-IPAR D/Q12 - 0 Non-IPAR
FQV7270
D/Q13 – 9 & D/Q7 – 0 IPAR D/Q13 – 9 & D/Q7 – 0 IPAR
D/Q11 - 0 Non-IPAR D/Q11 - 0 Non-IPAR
FQV7260 D/Q12 – 9 & D/Q7 – 0 IPAR D/Q12 – 9 & D/Q7 – 0 IPAR
D/Q10 - 0 Non-IPAR D/Q10 - 0 Non-IPAR
FQV7250 D/Q11 – 9 & D/Q7 – 0 IPAR D/Q11 – 9 & D/Q7 – 0 IPAR
D/Q9 - 0 Non-IPAR D/Q9 - 0 Non-IPAR
FQV7240
D/Q10 – 9 & D/Q7 – 0 IPAR D/Q10 – 9 & D/Q7 – 0 IPAR
D/Q8 - 0 Non-IPAR D/Q8 - 0 Non-IPAR
FQV7230 D/Q9 & D/Q7 – 0 IPAR D/Q9 & D/Q7 – 0 IPAR
Table 6. Parallel Offset Register Data Mapping Table for x72 & x36 & x18
Device Standard Mode FWFT Mode
FVQ72100 65,536 x 72 65,537 x 72
FVQ7290 32,768 x 72 32,769 x 72
FQV7280 16,384 x 72 16,385 x 72
FQV7270 8,192 x 72 8,193 x 72
FQV7260 4,096 x 72 4,097 x 72
FQV7250 2,048 x 72 2,049 x 72
FQV7240 1,024 x 72 1,025 x 72
FQV7230 512 x 72 513 x 72
Table 7. Maximum Depth of Queue for Standard and FWFT Mode
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3F372E
Data Width
Non-Interspersed Parity
Interspersed Parity
Data Width
Non-Interspersed Parity
Interspersed Parity
PRAE
PRAF
Data Width
Non-Interspersed Parity
Interspersed Parity
Data Width
Non-Interspersed Parity
Interspersed Parity
FQV72100, FQV7290, FQV7280, FQV7270, FQV7260, FQV7250, FQV7240, FQV7230
Parallel Offset Write/Read Cycles for x18 Bus Width
Data Width
Non-Interspersed Parity
Interspersed Parity
Data Width
Non-Interspersed Parity
Interspersed Parity
PRAE
PRAF
PRAE
PRAF
1st Cycle
1st Cycle
1st Cycle
2nd Cycle
2nd Cycle
2nd Cycle
13
13
12
12
11
11
10
10
98
9875316420
75316420
13
13
12
12
11
11
10
10
98
9875316420
75316420
13
13
12
12
11
11
10
10
98
9875316420
75316420
D/Q18D/Q19D/Q~ D/Q~D/Q~D/Q71 D/Q17 D/Q15 D/Q13 D/Q11 D/Q9
D/Q16 D/Q14 D/Q12 D/Q10 D/Q8 D/Q6 D/Q4 D/Q2 D/Q0
D/Q7 D/Q5 D/Q3 D/Q1
D/Q17 D/Q15 D/Q13 D/Q11 D/Q9
D/Q16 D/Q14 D/Q12 D/Q10 D/Q8 D/Q 6 D/Q4 D/Q2 D/Q0
D/Q7 D/Q5 D/Q3 D/Q1
D/Q18D/Q19D/Q~ D/Q~D/Q~D/Q71
13
13
12
12
11
11
10
10
98
9875316420
75316420
D/Q17 D/Q15 D/Q13 D/Q11 D/Q9
D/Q16 D/Q14 D/Q12 D/Q10 D/Q8 D/Q6 D/Q4 D/Q2 D/Q0
D/Q7 D/Q5 D/Q3 D/Q1
D/Q18D/Q19
D/Q~ D/Q~D/Q~
D/Q71
D/Q17 D/Q15 D/Q13 D/Q11 D/Q9
D/Q16 D/Q14 D/Q12 D/Q10 D/Q8 D/Q6 D/Q4 D/Q2 D/Q0
D/Q7 D/Q5 D/Q3 D/Q1
D/Q18D/Q19D/Q~ D/Q~D/Q~D/Q71
D/Q17 D/Q15 D/Q13 D/Q11 D/Q9
D/Q16 D/Q14 D/Q12 D/Q10 D/Q8 D/Q6 D/Q4 D/Q2 D/Q0
D/Q7 D/Q5 D/Q3 D/Q1
D/Q17 D/Q15 D/Q13 D/Q11 D/Q9
D/Q16 D/Q14 D/Q12 D/Q10 D/Q8 D/Q6 D/Q4 D/Q2 D/Q0D/Q7 D/Q5 D/Q3 D/Q1
75316420
753164208
13 11 912 10
811 912 10
13
75316420
813 11 912 10
75316420811 9
12 10
13
15 14
1415
15 14
1415
15 14
1415
15 14
1415
15 14
1415
15 14
1415
FQV72100, FQV7290, FQV7280, FQV7270, FQV7260, FQV7250, FQV7240, FQV7230
Parallel Offset Write/Read Cycles for x36 Bus Width
FQV72100, FQV7290, FQV7280, FQV7270, FQV7260, FQV7250, FQV7240, FQV7230
Parallel Offset Write/Read Cycles for x72 Bus Width
Figure 8. Parallel Offset Write/Read Cycles Diagram
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3F372E
# of Bits for Offset Registers
16 bits for FQV72100
15 bits for FQV7290
14 bits for FQV7280
13 bits for FQV7270
12 bits for FQV7260
11 bits for FQV7250
10 bits for FQV7240
9 bits for FQV7230
Note: Don’t Care applies to all unused bits
Figure 8. Parallel Offset Write/Read Cycles Diagram (Continued)
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3F372E
FQV72100 FULL PRAF HALF PRAE EMPTY
0 H H H L L
1 to y(1) H H H L H
(y+1) to 32,768 H H H H H
32,769 to [65,536-(x+1)] H H L H H
(65,536 –x(2)) to 65,535 H L L H H
65,536 L L L H H
FQV7290 FULL PRAF HALF PRAE EMPTY
0 H H H L L
1 to y(1) H H H L H
(y+1) to 16,384 H H H H H
16,385 to [32,768-(x+1)] H H L H H
(32,768 –x(2)) to 32,767 H L L H H
32,768 L L L H H
FQV7280 FULL PRAF HALF PRAE EMPTY
0 H H H L L
1 to y(1) H H H L H
(y+1) to 8,192 H H H H H
8,193 to [16,384-(x+1)] H H L H H
(16,384 –x(2)) to 16,383 H L L H H
16,384 L L L H H
FQV7270 FULL PRAF HALF PRAE EMPTY
0 H H H L L
1 to y(1) H H H L H
(y+1) to 4,096 H H H H H
4,097 to [8,192-(x+1)] H H L H H
(8,192 -x(2)) to 8,191 H L L H H
8,192 L L L H H
FQV7260 FULL PRAF HALF PRAE EMPTY
0 H H H L L
1 to y(1) H H H L H
(y+1) to 2,048 H H H H H
2,049 to [4,096-(x+1)] H H L H H
(4,096 –x(2)) to 4,095 H L L H H
4,096 L L L H H
FQV7250 FULL PRAF HALF PRAE EMPTY
0 H H H L L
1 to y(1) H H H L H
(y+1) to 1,024 H H H H H
1,025 to [2,048-(x+1)] H H L H H
(2,048 -x(2)) to 2,047 H L L H H
2,048 L L L H H
Table 8. Status Flags (Standard Mode)
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3F372E
FQV7240 FULL PRAF HALF PRAE EMPTY
0 H H H L L
1 to y(1) H H H L H
(y+1) to 512 H H H H H
513 to [1,024-(x+1)] H H L H H
(1,024 –x(2)) to 1,023 H L L H H
1,024 L L L H H
FQV7230 FULL PRAF HALF PRAE EMPTY
0 H H H L L
1 to y(1) H H H L H
(y+1) to 256 H H H H H
257 to [512-(x+1)] H H L H H
(512 –x(1)) to 511 H L L H H
512 L L L H H
NOTES:
1. See Table 11 for values x, y.
Table 8. Status Flags (Standard Mode)(Continued)
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3F372E
FQV72100 DRDY PRAF HALF PRAE QRDY
0 L H H L H
1 to y+1 L H H L L
(y+2) to 32,769 L H H H L
32,770 to [65,537-(x+1)] L H L H L
(65,537 –x) to 65,536 L L L H L
65,537 H L L H L
FQV7290 DRDY PRAF HALF PRAE QRDY
0 L H H L H
1 to y+1 L H H L L
(y+2) to 16,385 L H H H L
16,386 to [32,769-(x+1)] L H L H L
(32,769 –x) to 32,768 L L L H L
32,769 H L L H L
FQV7280 DRDY PRAF HALF PRAE QRDY
0 L H H L H
1 to y+1 L H H L L
(y+2) to 8,193 L H H H L
8,194 to [16,385-(x+1)] L H L H L
(16,385 -x) to 16,384 L L L H L
16,385 H L L H L
FQV7270 DRDY PRAF HALF PRAE QRDY
0 L H H L H
1 to y+1 L H H L L
(y+2) to 4,097 L H H H L
4,098 to [8,193-(x+1)] L H L H L
(8,193-x) to 8,192 L L L H L
8,193 H L L H L
FQV7260 DRDY PRAF HALF PRAE QRDY
0 L H H L H
1 to y+1 L H H L L
(y+2) to 2,049 L H H H L
2,050 to [4,097-(x+1)] L H L H L
(4,097 -x) to 4,096 L L L H L
4,097 H L L H L
FQV7250 DRDY PRAF HALF PRAE QRDY
0 L H H L H
1 to y+1 L H H L L
(y+2) to 1,025 L H H H L
1,026 to [2,049-(x+1)] L H L H L
(2,049 -x) to 2,048 L L L H L
2,049 H L L H L
Table 9. Status Flags (FWFT Mode)
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3F372E
FQV7240 DRDY PRAF HALF PRAE QRDY
0 L H H L H
1 to y+1 L H H L L
(y+2) to 513 L H H H L
514 to [1,025-(x+1)] L H L H L
(1,025 -x) to 1,024 L L L H L
1,025 H L L H L
FQV7230 DRDY PRAF HALF PRAE QRDY
0 L H H L H
1 to y+1 L H H L L
(y+2) to 257 L H H H L
258 to [513-(x+1)] L H L H L
(513 -x) to 512 L L L H L
513 H L L H L
Table 9. Status Flags (FWFT Mode)(Continued)
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3F372E
ES BM2 BM1 BM0 I/O Width D/Q71-54 D/Q53-36 D/Q35-18 D/Q17-0 Sequence
X 0 X X I 72 Byte 4 Byte 3 Byte 2 Byte 1 1st Write
O 72 Byte 4 Byte 3 Byte 2 Byte 1 1st Read
0 1 0 0 I 72 Byte 4 Byte 3 Byte 2 Byte 1 1st Write
O 36 X X Byte 4 Byte 3 1st Read
X X Byte 2 Byte 1 2
nd Read
0 1 0 1 I 72 Byte 4 Byte 3 Byte 2 Byte 1 1st Write
O 18 X X X Byte 4 1st Read
X X X Byte 3 2nd Read
X X X Byte 2 3rd Read
X X X Byte1 4th Read
0 1 1 0 I 36 X X Byte 4 Byte 3 1st Write
X X Byte 2 Byte 1 2
nd Write
O 72 Byte 4 Byte 3 Byte 2 Byte 1 1st Read
0 1 1 1 I 18 X X X Byte 4 1st Write
X X X Byte 3 2nd Write
X X X Byte 2 3rd Write
X X X Byte1 4th Write
O 72 Byte 4 Byte 3 Byte 2 Byte 1 1st Read
1 1 0 0 I 72 Byte 4 Byte 3 Byte 2 Byte 1 1st Write
O 36 X X Byte 2 Byte 1 1st Read
X X Byte 4 Byte 3 2
nd Read
1 1 0 1 I 72 Byte 4 Byte 3 Byte 2 Byte 1 1st Write
O 18 X X X Byte 1 1st Read
X X X Byte 2 2nd Read
X X X Byte 3 3rd Read
X X X Byte4 4th Read
1 1 1 0 I 36 X X Byte 4 Byte 3 1st Write
X X Byte 2 Byte 1 2
nd Write
O 72 Byte 2 Byte 1 Byte 4 Byte 3 1st Read
1 1 1 1 I 18 X X X Byte 4 1st Write
X X X Byte 3 2nd Write
X X X Byte 2 3rd Write
X X X Byte1 4th Write
O 72 Byte 1 Byte 2 Byte 3 Byte 4 1st Read
Table 10. Bus-Matching Table
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3F372E
FQV7240
FQV7230
LOAD PFS1 PFS0
Default Offsets x, y(1)
0 0 0 127
0 0 1 255
0 1 0 511
0 1 1 63
1 0 0 31
1 0 1 7
1 1 0 15
1 1 1 3
FQV7240
FQV7230
LOAD PFS1 PFS0
Program Mode
1 X X Serial
0 X X Parallel
FQV7280
FQV7270
FQV7260
FQV7250
LOAD PFS1 PFS0
Default Offsets x, y(1)
0 0 0 127
0 0 1 255
0 1 0 511
0 1 1 63
1 0 0 1,023
1 0 1 15
1 1 0 31
1 1 1 7
FQV7280
FQV7270
FQV7260
FQV7250
LOAD PFS1 PFS0
Program Mode
1 X X Serial
0 X X Parallel
NOTES:
1. y = PRAE offset, x = PRAF offset
Table 11. Default Programmable Flag Offsets
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3F372E
FQV72100
FQV7290
LOAD PFS1 PFS0
Default Offsets x, y(1)
0 0 0 127
0 0 1 8,191
0 1 0 16,383
0 1 1 4,095
1 0 0 1,023
1 0 1 511
1 1 0 2,047
1 1 1 255
FQV72100
FQV7290
LOAD PFS1 PFS0
Program Mode
1 X X Serial
0 X X Parallel
NOTES:
1. y = PRAE offset, x = PRAF offset
Table 11. Default Programmable Flag Offsets (Continued)
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3F372E
JTAG Interface
Standard JTAG interface is used for boundary scan purposes. For a complete description, please refer to the IEEE Standard Test
Access Port Specification (IEEE STD.1149.1 – 1990)
JTAG TIMING SPECIFICATIONS
t2t1t4
t3
tTCK
tDO
TDO
t5
t6
tDS tDH
TRST
TDO
TMS/TDI
TCK
Figure 9. Standard JTAG Timing
FQV72100
FQV7290
FQV7280
FQV7270
FQV7260
FQV7250
FQV7240
FQV7230
Parameter Symbol
Test
Conditions Min. Max. Units
System Interface Parameters
Data Output tDO = Max - 5 50 ns
Data Output Hold tDOH - 5 - ns
tDS trise = 3ns 30 -
Data Input tDH tfall = 3ns 30 - ns
JTAG AC Electrical Characteristics
JTAG Clock Input Period tTCK - 100 - ns
JTAG Clock HIGH tTCKHIGH (t2) - 40 - ns
JTAG Clock Low tTCKLOW (t1) - 40 - ns
JTAG Clock Rise Time tTCKRise (t4) - - 5 ns
JTAG Clock Fall Time tTCKFall (t3) - - 5 ns
JTAG Reset tRST (t5) - 50 - ns
JTAG Reset Recovery tRSR (t6) - 50 - ns
Table 12. JTAG AC Electrical Characteristics
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3F372E
JTAG BLOCK DIAGRAM
HBA’s FlexQ™ offers IEEE Std. 1149.1-1990 standard JTAG interface to facilitate system debugging in all PBGA packages.
STANDARD JTAG INTERFACE ELEMENTS:
1. TAP – TEST ACCESS PORT
2. TAPCNTL – TAP CONTROLLER
3. IR – INSTRUCTION REGISTER
4. DR – DATA REGISTER
TAP
TAP
Controller
Instruction Decode
Instruction Register
Boundary Scan Reg.
Device ID Reg.
Bypass Reg.
TDO
TDI
TMS
TCLK
TRST DR
IR
Figure 10. Boundary Scan Architecture Diagram
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3F372E
1. TAP The basic ports to access the JTAG function. That includes four general input ports: TRST ,
TCK, TMS, and TDI, and one general output port: TDO.
2. TAPCNTL A finite state machine that provide instructions to the Instruction and Data Registers for data
capture and update. Individual states are explained blow.
Test-Logic
Reset
Run-Test /
Idle
Select-DR-
Scan
Select-IR-
Scan
Capture-DR Capture-IR
Shift-DR Shift-IR
Exit1-DR Exit1-IR
Pause-DR Pause-IR
Exit2-DR Exit2-IR
Update-DR Update-IR
Input = TMS
1
01
011
11
00 00
00
11
11
00 00
11
00
101
0
11
Figure 11. TAP Controller State Diagram
• Capture-IR Data are captured in parallel into the instruction register.
• Capture-DR Data are captured in parallel into the data register.
• SHIFT-IR LSB of the instruction register is shift in serially during a low to high transition of the
TCK through TDI/TDO path
• SHIFT-DR LSB of the data register is shift in serially during a low to high transition of the TCK
through TDI/TDO path.
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3F372E
3. INSTRUCTION
REGISTER
A 4 - bit instruction register that is shifted serially at the rising edge of TCLK. The instruction is
latched through the least significant bits of the nearest serial OUTPUT.
Hex Value Instruction Function
0 x 00 EXTEST Select Boundary Scan Register
0 x 02 IDCODE Select Chip Identification data register
0 x 01 SAMPLE/PRELOAD Select Boundary Scan Register
0 x 03 HI-Z JTAG
0 x 0F BYPASS Select Bypass Register
Table 13. JTAG Instruction Register Decoding Table
• EXTEST An instruction to facilitate external circuitry and board level interconnection verification.
• IDCODE An instruction to read out manufacture’s identification, part number and version number.
• SAMPLE/
PRE-LOAD
An instruction to allow snapshots of data flowing through the system pins. SAMPLE
instruction MUST be executed prior to the selection of Boundary Scan test.
• HIGH Z An Instruction to place all output pins to high impedance state.
• BYPASS An Instruction to allow direct serial data shifting through TDI and TDO without any device
operation.
4. DATA REGISTER There are three data registers, Device ID register, BYPASS register, and Boundary Scan register.
These parallel-connected registers are access through the common serial input and the common
serial output.
• Device ID
Register
A 32-bit register that contains the specific manufacturer, part number and version
number.
• UPDATE-IR To shift Instruction Register Data to the parallel outputs. Instruction Register Data can
be accessed through the internal bus.
• UPDATE-DR To shift Data Register Data to the parallel outputs. Data Register Data can be accessed
through the internal bus.
• EXIT1-IR/
EXIT2-IR
A transition state that terminates the scanning process. All Instruction Register data
selected will retain their previous instruction state.
• EXIT1-DR/
EXIT2-DR
A transition state that terminates the scanning process. All Data Register data selected
will retain their previous data state.
• PAUSE-IR The temporary state to halt all serial shifting process between TDI and TDO. All data
will retain their previous instruction state.
• PAUSE-DR The temporary state to halt all serial shifting process between TDI and TDO. All data
will retain their previous data state.
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3F372E
31(MSB) 28 27 12 11 1 0(LSB)
Version (4 bits)
0x0
Part Number (16-bit) Manufacturer ID (11-bit)
0x16E
1
Device Part # Field
FQV72100 0 x 50
FQV7290 0 x 56
FQV7280 0 x 55
FQV7270 0 x 54
FQV7260 0 x 53
FQV7250 0 x 52
FQV7240 0 x 51
FQV7230 0 x 57
Table 14. Device ID Register Decode Table
• BYPASS
Register
The data register that allows direct serial data shifting through TDI and TDO without
any device operation.
• BOUNDARY
SCAN Register
The data register that allows the serial writes and read through TDI and TDO.
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3F372E
Timing Diagrams
tRST
tRSTR
tRSTR
tRSTR
tRSTS
FWFT/SDI
tRSTR
tRSTS
tRSTS
PFS1/PFS0
tRSTS
ES
tRSTS
RETZL
tRSTS
SFM
tRSTS
IPAR
Q71- 0
tRSTF
tRSTF
tRSTF
tRSTF
tRSTF
tRSTS
tRSTS
tRSTS
tRSTS
MRST
REN
WEN
LOAD
RET
SDEN
/EMPTY QRDY
PRAE
PRAF HALF/
/
FULL DRDY
If FWFT = 0, = 1
FULL
If FWFT = 1, = 0
DRDY
If FWFT = 1, = 1QRDY
If FWFT = 0, = 0EMPTY
= 0
OE
= 1
OE
tRSTS
BM2/BM1/BM0
Diagram 1. Master Reset Timing
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3F372E
tRST
tRSTR
tRSTR
tRSTF
tRSTF
tRSTF
tRSTF
tRSTF
tRSTS
tRSTS
tRSTS
tRSTS
If FWFT = 0, = 1FULL
If FWFT = 1, = 0
DRDY
If FWFT = 1, = 1QRDY
If FWFT = 0, = 0
EMPTY
= 0
OE
= 1
OE
Q71- 0
RET
SDEN
/
EMPTY QRDY
PRAE
PRAF HALF/
/
FULL DRDY
WEN
REN
PRST
Diagram 2. Partial Reset Timing
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3F372E
DW
i + 1
DW
i
No
Write
No
Write
No
Write
t
WCLK
t
WCLKH
t
WCLKL
t
FULL
t
FULL
t
FULL
t
FULL
t
DS
t
DH
t
DS
t
DH
t
SKEW1
t
RCSS
t
A
t
A
Next Data ReadData Read
WCLK
D
71 - 0
RCLK
Q
71 - 0
FULL
RCS
WEN
12 12
t
ENS
t
ENH
t
ENS
t
ENH
REN
t
RCSLZ
NOTES:
1. If the time between a rising edge of RCLK to the rising edge of WCLK is greater than or equal to tSKEW1, FULL
___________
will go high (after one WCLK cycle plus tFULL). If tSKEW1 is not met, then FULL
__________
will assert 1
or more WCLK cycles.
2. LOAD
___________
= High, OE
______
= Low.
Diagram 3. Write Cycle and Full Flag Timing (Standard Mode)
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3F372E
DW
1
DW
2
DW
1
Last Word Last Word DW
2
t
RCLK
t
RCLKH
t
RCLKL
t
ENH
t
ENS
t
ENH
t
ENS
t
EMPTY
t
EMPTY
t
EMPTY
t
A
t
A
t
OEN
t
OHZ
t
OLZ
t
OLZ
t
SKEW1
t
ENS
t
ENH
t
ENS
t
ENH
t
ENH
t
ENS
t
DS
t
DH
t
DS
t
DH
t
A
RCLK
Q
71 - 0
WCLK
D
71 - 0
OE
WEN
EMPTY
REN
12
No Operation No Operation
NOTES:
1. If the time between a rising edge of WCLK to the rising edge of RCLK is greater than or equal to tSKEW11, EMPTY
______________
will go high (after RCLK cycle plus tEMPTY). If tSKEW1 is not met, then EMPTY
______________
will assert 1 or
more RCLK cycles.
2. LOAD
___________
= High.
3. First word latency: tSKEW1 + tEMPTY + 1 * tRCLK.
Diagram 4. Read Cycle, Empty Flag and First Data Word Latency Timing (Standard Mode)
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3F372E
Last Data - 1
t
EMPTY
t
EMPTY
t
A
t
ENS
t
ENH
t
ENS
RCLK
Q
71 - 0
WCLK
D
71 - 0
WEN
EMPTY
REN
12
t
RCSS
t
RCSS
RCS
t
RCSS
t
RCSH
t
A
t
RCSLZ
t
RCSHZ
t
RCSLZ
t
RCSHZ
t
SKEW1
t
DH
t
DS
Last Data
DW
i
NOTES:
1. If the time between a rising edge of WCLK to the rising edge of RCLK is greater than or equal to tSKEW11, EMPTY
______________
will go high (after RCLK cycle plus tEMPTY). If tSKEW1 is not met, then EMPTY
______________
will assert 1 or
more RCLK cycles.
2. LOAD
___________
= High.
3. First word latency: tSKEW1 + tEMPTY + 1 * tRCLK.
Diagram 5. Read Cycle and Read Chip Select Timing (Standard Mode)
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3F372E
DW
[y+2]
DW
D
DW
[D-1]
DW
[D-x+3]
DW
[D-x+2]
DW
[D-x+1]
DW
[D-x]
DW
[D-x -1]
DW
[(D-1)/ 2+3]
DW
[(D-1)/2+2]
DW
[(D-1)/2+1]
DW
[y+4]
DW
[y+3]
DW
4
DW
3
DW
2
DW
1
312 12
WCLK
D
71 - 0
RCLK
t
ENS
t
DH
t
DS
t
DS
t
DS
t
DS
t
ENH
t
SKEW1
t
SKEW2
1
WEN
2
Q
71 - 0
QRDY
PRAE
HALF
PRAF
DRDY
t
FULL
t
HALF
t
PRAES
t
A
t
EMPTY
Previous Output Register Data
DW
1
REN
RCS
t
RCSS
t
PRAFS
t
RCLZ
NOTES:
1. If the time between a rising edge of WCLK to the rising edge of RCLK is greater than or equal to tSKEW1, QRDY
____________
will go low (after two RCLK cycle plus tEMPTY). If tSKEW1 is not met, then QRDY
____________
will assert 1 or more
RCLK cycles.
2. If the time between a rising edge of WCLK to the rising edge of RCLK is greater than or equal to tSKEW2, PRAE
___________
will go high (after one RCLK cycle plus tPRAES). If tSKEW2 is not met, then PRAE
___________
will assert 1 or more
RCLK cycles.
3. LOAD
___________
= High, OE
______
= Low.
4. y = PRAE
___________
offset, x = PRAF
___________
offset.
5. D = maximum queue depth. Please refer to Table 7 for Depth.
6. First word latency: tSKEW1 + tEMPTY + 2 * tRCLK
Diagram 6. Write Timing (FWFT Mode)
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3F372E
DW
1
DW
D
DW
[D-1]
DW
[D-y+2]
DW
[D-y+1]
DW
[D-y-1]
DW
[(D-1)/2+2]
DW
x+3
DW
x+2
DW
x+1
DW
3
DW
2
DW
1
DW
[D-y ]
DW
[(D-1)/2+1]
DW
D
t
ENS
t
ENH
t
SKEW1
t
SKEW2
t
DS
t
DH
t
ENS
t
OHZ
t
OE
t
A
t
A
t
A
t
A
t
A
t
A
t
ENS
t
EMPTY
t
PRAES
t
HALF
t
PRAFS
t
FULL
t
FULL
WCLK
WEN
D
71 - 0
RCLK
REN
OE
Q
71 - 0
QRDY
PRAE
HALF
PRAF
DRDY
1212
12
NOTES:
1. If the time between a rising edge of RCLK to the rising edge of WCLK is greater than or equal to tSKEW1, DRDY
____________
will go low (after one WCLK cycle plus tFULL) . If tSKEW1 is not met, then DRDY
____________
will assert 1 or more
WCLK cycles.
2. If the time between a rising edge of RCLK to the rising edge of WCLK is greater than or equal to tSKEW2, PRAF
___________
will go high (after one WCLK cycle plus tPRAFS) If tSKEW2 is not met, then PRAF
___________
will assert 1 or more
WCLK cycles.
3. LOAD
____________
= High, RCS
________
= Low
4. y = PRAE
___________
Offset, x = PRAF
___________
offset.
5. D = maximum queue depth. Please refer to Table 7 for Depth.
Diagram 7. Read Timing (FWFT Mode)
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3F372E
DW
1
DW
D
DW
[D-1]
DW
[D-y+2]
DW
[D-y+1]
DW
[D-y-1]
DW
[(D-1)/2+2]
DW
x+4
DW
x+3
DW
x+2
DW
3
DW
2
DW
[D-y]
DW
[(D-1)/2+1]
DW
D
t
ENS
t
ENH
t
SKEW1
t
SKEW2
t
DS
t
DH
t
ENS
t
A
t
A
t
A
t
A
t
A
t
ENS
t
EMPTY
t
PRAES
t
HALF
t
PRAFS
t
FULL
t
FULL
WCLK
WEN
D
71 - 0
RCLK
REN
RCS
Q
71 - 0
QRDY
PRAE
HALF
PRAF
DRDY
12
t
RCSHZ
t
RCSS
t
RCSH
t
RCSLZ
NOTES:
1. If the time between a rising edge of RCLK to the rising edge of WCLK is greater than or equal to tSKEW1, DRDY
____________
will go low (after one WCLK cycle plus tFULL) . If tSKEW1 is not met, then DRDY
____________
will assert 1 or more
WCLK cycles.
2. If the time between a rising edge of RCLK to the rising edge of WCLK is greater than or equal to tSKEW2, PRAF
___________
will go high (after one WCLK cycle plus tPRAFS) If tSKEW2 is not met, then PRAF
___________
will assert 1 or more
WCLK cycles.
3. LOAD
____________
= High, OE
______
= Low.
4. y = PRAE
___________
Offset, x = PRAF
___________
offset.
5. D = maximum queue depth. Please refer to Table 7 for Depth.
Diagram 8. Read Cycle and Read Chip Select Timing (FWFT Mode)
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3F372E
DWiDWi+1 DW1DW2
RCLK
Q 71 - 0
WCLK
tENS tENH tRETS
tAtA
tENS tENH
tA
tSKEW2
tRETS
tENS tENH
tEMPTY
tHALF
tEMPTY
tPRAES
tPRAFS
REN
WEN
RET
EMPTY
PRAE
HALF
PRAF
12
12
NOTES:
1. Upon completion of retransmit setup, a read operation can begin only after EMPTY returns high.
2. OE = Low, RCS = Low.
3. DWi = Words written to the queue after MRST . Where i = 1,2,3… depth.
4. Upon reset completion, there must be more than 2 words written to the queue for a retransmit setup to be valid.
Diagram 9. Retransmit Timing (Standard Mode)
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FQV72100 · FQV7290 · FQV7280 · FQV7270 · FQV7260 · FQV7250 · FQV7240· FQV7230
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3F372E
DW3
DW1
DWiDWi+1 DW2
RCLK
Q 71 - 0
WCLK
tENS tENH tRETS
tA
tSKEW2
tRETS
tENS tENH
tEMPTY
tHALF
tEMPTY
tPRAES
tPRAFS
1
tENH
tA
23
DW4
tAtA
tENS
PRAF
HALF
PRAE
QRDY
RET
WEN
REN
4
12
NOTES:
1. Upon completion of retransmit setup, a read operation can begin only after QRDY returns low.
2. OE = Low, RCS = Low.
3. DWi = Words written to the queue after MRST . Where i = 1,2,3… depth.
4. Upon reset completion, there must be more than 2 words written to the queue for a retransmit setup to be valid.
5. Please refer to Table 8 for Depth.
Diagram 10. Retransmit Timing (FWFT Mode)
NOVEMBER 2002
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TMIII
FQV72100 · FQV7290 · FQV7280 · FQV7270 · FQV7260 · FQV7250 · FQV7240· FQV7230
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 44 of 44
3F372E
RCLK
Q 71- 0
WCLK
DWiDWi+1 DW1DW2DW3DW4
tRETS
tENS tENH
tSKEW2
tAtAtAtAtA
tENS tENH
tPRAES
tHALF
tPRAFS
WEN
REN
RET
EMPTY
PRAE
HALF
PRAF
123
12
NOTES:
1. If the part is empty at the point of retransmit, the Empty Flag ( EMPTY ) will be updated based on RCLK (Retransmit Clock cycle). Valid data will
appear on the output.
2. OE = Low, RCS = Low; enables data to be read on outputs Q71 – 0.
3. DW1= first word written to the queue after Master Reset; DW2= second word written to the queue after Master Reset.
4. No more than D-2 may be written to the queue between reset (Master or Partial) and retransmit setup. Therefore, FULL will be high throughout the
retransmit setup procedure. Please refer to Table 7 for Depth.
5. There must be at least two words written to zero latency retransmit from the queue before a retransmit operation can be invoked.
6. RETZL is set Low during MRST .
Diagram 11. Zero Latency Retransmit Timing (Standard Mode)
NOVEMBER 2002
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FQV72100 · FQV7290 · FQV7280 · FQV7270 · FQV7260 · FQV7250 · FQV7240· FQV7230
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 45 of 45
3F372E
RCLK
Q 71 - 0
WCLK
DWiDW i+1 DW1DW2DW3DW4
tRETS
tENS tENH
tSKEW2
tAtAtAtAtA
tENS tENH
tPRAES
tHALF
tPRAFS
DW5
tA
PRAF
HALF
PRAE
QRDY
RET
WEN
REN
12345
NOTES:
1. If the part is empty at the point of retransmit, the output ready flag ( QRDY ) will be updated based on RCLK (Retransmit Clock cycle). Valid data will
appear on the output.
2. No more than D-2 words maybe written to the queue between reset (Master or Partial) and retransmit setup. Therefore, DRDY will be low throughout
the retransmit setup procedure. Please refer to Table 8 for Depth.
3. OE = Low, RCS = Low.
4. DW1, DW2, DW3 = first, second and third words written to the queue after Master Reset.
5. There must be at least two words written to the queue before a retransmit operation can be invoked.
6. RETZL is set low during MRST .
Diagram 12. Zero Latency Retransmit Timing (FWFT Mode)
NOVEMBER 2002
Flex
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TMIII
FQV72100 · FQV7290 · FQV7280 · FQV7270 · FQV7260 · FQV7250 · FQV7240· FQV7230
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 46 of 46
3F372E
SCLK
SDI
tENHtENS
tLOADHtLOADS
tDS
offset offset
tENH
tLOADH
tDH
BIT 0 BIT MSB BIT 0 BIT MSB
SDEN
LOAD
PRAE PRAF
*Refer to Table 13
Diagram 13. Serial Loading of Programmable Flag Registers (Standard and FWFT Mode)
FQV72100 FQV7290 FQV7280 FQV7270 FQV7260 FQV7250 FQV7240 FQV7230
MSB 15 14 13 12 11 10 9 8
Table 13. Reference Table for Diagram 13
NOVEMBER 2002
Flex
Q
TMIII
FQV72100 · FQV7290 · FQV7280 · FQV7270 · FQV7260 · FQV7250 · FQV7240· FQV7230
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 47 of 47
3F372E
tLOADS
tENS
tLOADH
tENH
tLOADH
tENH
tWCLKH tWCLKL
tWCLK
WCLK
D 71 - 0
offset
tDS tDH tDS tDH
WEN
LOAD
PRAE offset
PRAF
Diagram 14. Parallel Loading of Programmable Flag Registers (Standard and FWFT Mode)
tLOADS
tENS
tLOADH
tENH
tLOADH
tENH
RCLK
Q 71 - 0 Output Register Data
tAtA
offset offset
LOAD
REN
PRAE PRAF
tRCLK
tRCLKH tRCLKL
NOTES:
1. OE = Low, RCS = Low.
Diagram 15. Parallel Read of Programmable Flag Registers (Standard and FWFT Mode)
NOVEMBER 2002
Flex
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TMIII
FQV72100 · FQV7290 · FQV7280 · FQV7270 · FQV7260 · FQV7250 · FQV7240· FQV7230
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 48 of 48
3F372E
tWCLKH tWCLKL
tENHtENS
tSKEW2
tENS tENH
tPRAFS tPRAFS
12 12
D - ( x + 1 ) words in Queue D - x words in Queue D - ( x + 1 )
words in Queue
WCLK
WEN
PRAF
RCLK
REN
NOTES:
1. x = PRAF
___________
offset.
2. D = maximum queue depth. Please refer to Table 7 for Depth.
3. If the time between a rising edge of RCLK to the rising edge of WCLK is greater than or equal to tSKEW2, PRAF
___________
will go high (after on WCLK cycle
plus tPRAFS). If tSKEW2 is not met, then PRAF
___________
will assert 1 or more WCLK cycles.
4. PRAF
___________
synchronizes to the rising edge of WCLK only.
Diagram 16. Synchronous Programmable Almost-Full Flag Timing (Standard and FWFT Mode)
tWCLKH tWCLKL
tWCLKLtWCLKH
tENS tENH
y words in Queue(2) ; y+1 words in Queue(3) y+1 words in Queue(2) ; y+2 words in Queue(3)
y words in Queue(2) ;
y+1 words in Queue(3)
tPRAEStPRAEStSKEW2
12 1 2
WCLK
RCLK
WEN
PRAE
REN
NOTES:
1. y = PRAE offset.
2. For Standard Mode.
3. For FWFT Mode.
4. If the time between a rising edge of WCLK to the rising edge of RCLK is greater than or equal to tSKEW2, PRAE will go high (after one RCLK cycle
plus tPRAES). If tSKEW2 is not met, then PRAE will assert 1 or more RCLK cycles.
5. PRAE synchronizes to the rising edge of RCLK only.
Diagram 17. Synchronous Programmable Almost-Empty Flag Timing (Standard and FWFT Mode)
NOVEMBER 2002
Flex
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TMIII
FQV72100 · FQV7290 · FQV7280 · FQV7270 · FQV7260 · FQV7250 · FQV7240· FQV7230
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 49 of 49
3F372E
tWCLKH tWCLKL
tENS tENH
tPRAFA
tPRAFA
tENS
D - ( x + 1) words in Queue
D - x words in
Queue D - ( x + 1) words in Queue
WCLK
RCLK
WEN
PRAF
REN
NOTES:
1. x = PRAF offset.
2. D = maximum queue depth. Please refer to Table 8 for Depth.
3. PRAF is asserted to low on WCLK transition and reset to high on RCLK transition.
4. Select this mode by setting SFM low during Master Reset.
Diagram 18. Asynchronous Programmable Almost-Full Flag Timing (Standard and FWFT Mode)
tWCLKH tWCLKL
tENS tENH
tPRAEA
tPRAEA
tENS
y words in Queue(2); y+1 words in Queue(3) y+1 words in
Queue(2); y+2
words in Queue (3)
y words in Queue(2); y+1 words in Queue(3)
WCLK
RCLK
WEN
PRAE
REN
NOTES:
1. y = PRAE offset.
2. For Standard Mode.
3. For FWFT Mode.
4. PRAE is asserted to low on RCLK transition and reset to high on WCLK transition.
5. Select this mode by setting SFM low during Master Reset.
Diagram 19. Asynchronous Programmable Almost-Empty Flag Timing (Standard and FWFT Mode)
NOVEMBER 2002
Flex
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TMIII
FQV72100 · FQV7290 · FQV7280 · FQV7270 · FQV7260 · FQV7250 · FQV7240· FQV7230
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 50 of 50
3F372E
D/2 words in Queue(1); [(D+1)/2] words in Queue(2)
D/2 + 1 words in
Queue(1);
[(D+1)/2 + 1] words
in Queue(2)
D/2 words in Queue(1);
[(D+1)/2] words in Queue(2)
tWCLKH tWCLKL
tENS tENH
tHALF
tHALF
tENS
WCLK
RCLK
WEN
HALF
REN
NOTES:
1. For Standard Mode.
2. For FWFT Mode.
3. Please refer to Table 7 for Depth.
Diagram 20. Half-Full Flag Timing (Standard and FWFT Mode)
NOVEMBER 2002
Flex
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TMIII
FQV72100 · FQV7290 · FQV7280 · FQV7270 · FQV7260 · FQV7250 · FQV7240· FQV7230
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 51 of 51
3F372E
Order Information:
HBA
Device Family
Device Type
Power
Speed (ns) *
Package**
Temperature Range
XX XXXXX X XX XX X
FQ V72100 (65,536 x 72) Low 6 – 166 MHz BB Blank – Commercial (0°C to 70°C)
V7290 (32,768 x 72) 7-5 – 133 MHz I – Industrial (-40° to 85°C)
V7280 (16,384 x 72) 10 – 100 MHz
V7270 (8,192 x 72) 15 – 66 MHz
V7260 (4,096 x 72)
V7250 (2,048 x 72)
V7240 (1,024 x 72)
V7230 (512 x 72)
*Speed – 6ns available only in Commercial temp (0°C to 70°C). Slower speeds available upon request.
**Package – 256 pin Fine Pitch Ball Grid Array (BGA)
Example:
FQV7270L6BB (8k x 72, 6ns, Commercial temp)
FQV7260L10BBI (4k x 72, 10ns, Industrial temp)
USA
Taiwan
2107 North First Street, Suite 415
San Jose, CA 95131, USA
www.hba.com
Tel: 408.453.8885
Fax: 408.453.8886
No. 81, Suite 8F-9, Shui-Lee Rd.
Hsinchu, Taiwan, R.O.C.
www.hba.com
Tel: 886.3.516.9118
Fax: 886.3.516.9181
