16-Bit, 250 kSPS PulSAR
ADC in MSOP/QFN
AD7685
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2004–2011 Analog Devices, Inc. All rights reserved.
FEATURES
16-bit resolution with no missing codes
Throughput: 250 kSPS
INL: ±0.6 LSB typical, ±2 LSB maximum (±0.003% of FSR)
SINAD: 93.5 dB @ 20 kHz
THD: −110 dB @ 20 kHz
Pseudo differential analog input range
0 V to VREF with VREF up to VDD
No pipeline delay
Single-supply operation 2.3 V to 5.5 V with
1.8 V to 5 V logic interface
Serial interface SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible
Daisy-chain multiple ADCs, BUSY indicator
Power dissipation
1.4 μW @ 2.5 V/100 SPS
1.35 mW @ 2.5 V/100 kSPS, 4 mW @ 5 V/100 kSPS
Standby current: 1 nA
10-lead package: MSOP (MSOP-8 size) and
3 mm × 3 mm QFN (LFCSP) (SOT-23 size)
Pin-for-pin-compatible with 10-lead MSOP/QFN PulSAR® ADCs
APPLICATIONS
Battery-powered equipment
Medical instruments
Mobile communications
Personal digital assistants (PDAs)
Data acquisition
Instrumentation
Process controls
02968-005
CODE
655360 16384 32768 49152
INL (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
POSITIVE INL = +0.33LSB
NEGATIVE INL = –0.50LSB
Figure 1. Integral Nonlinearity vs. Code.
APPLICATION DIAGRAM
AD7685
REF
GND
VDD
IN+
IN
VIO
SDI
SCK
SDO
CNV
1.8V TO VDD
3- OR 4-WIRE INTERFACE
(SPI, DAISY CHAIN, CS)
0.5
V
TO VDD 2.5
V
TO 5V
0 TO VREF
02968-001
Figure 2.
Table 1. MSOP, QFN (LFCSP)/SOT-23
14-/16-/18-Bit PulSAR ADC
Type
100
kSPS
250
kSPS
400 kSPS
to
500 kSPS
1000
kSPS
ADC
Driver
18-Bit True AD7691 AD7690 AD7982 ADA4941
Differential AD7982 ADA4841
16-Bit True AD7684 AD7687 AD7688 ADA4941
Differential AD7693 ADA4841
16-Bit Pseudo AD7680 AD7685 AD7686 AD7980 ADA4841
Differential AD7683 AD7694
14-Bit Pseudo AD7940 AD7942 AD7946 ADA4841
Differential
GENERAL DESCRIPTION
The AD7685 is a 16-bit, charge redistribution successive
approximation, analog-to-digital converter (ADC) that operates
from a single power supply, VDD, between 2.3 V to 5.5 V. It
contains a low power, high speed, 16-bit sampling ADC with no
missing codes, an internal conversion clock, and a versatile serial
interface port. The part also contains a low noise, wide bandwidth,
short aperture delay, track-and-hold circuit. On the CNV rising
edge, it samples an analog input IN+ between 0 V to REF with
respect to a ground sense IN−. The reference voltage, REF, is
applied externally and can be set up to the supply voltage.
Power dissipation scales linearly with throughput.
The SPI-compatible serial interface also features the ability,
using the SDI input, to daisy chain several ADCs on a single
3-wire bus or provides an optional BUSY indicator. It is
compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic using the
separate supply VIO.
The AD7685 is housed in a 10-lead MSOP or a 10-lead QFN
(LFCSP) with operation specified from −40°C to +85°C.
AD7685
Rev. C | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Application Diagram........................................................................ 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications....................................................................... 5
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Terminology ...................................................................................... 9
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 13
Circuit Information.................................................................... 13
Converter Operation.................................................................. 13
Typical Connection Diagram ................................................... 14
Analog Inputs.............................................................................. 15
Driver Amplifier Choice ........................................................... 16
Voltage Reference Input ............................................................ 16
Power Supply............................................................................... 16
Supplying the ADC from the Reference.................................. 17
Digital Interface.......................................................................... 17
CS Mode 3-Wire, No BUSY Indicator..................................... 18
CS Mode 3-Wire with BUSY Indicator ................................... 19
CS Mode 4-Wire, No BUSY Indicator..................................... 20
CS Mode 4-Wire with BUSY Indicator ................................... 21
Chain Mode, No BUSY Indicator ............................................ 22
Chain Mode with BUSY Indicator........................................... 23
Application Hints ........................................................................... 24
Layout .......................................................................................... 24
Evaluating the Performance of the AD7685............................... 24
True 16-Bit Isolated Application Example.............................. 25
Outline Dimensions....................................................................... 26
Ordering Guide .......................................................................... 27
REVISION HISTORY
8/11—Rev. B to Rev. C
Changes to Figure 6 and Table 7..................................................... 8
Updated Outline Dimensions....................................................... 26
Changes to Ordering Guide .......................................................... 27
3/07—Rev. A to Rev. B
Changes to Features and Table 1 .................................................... 1
Changes to Table 3............................................................................ 4
Moved Figure 3 and Figure 4 to Page............................................. 6
Inserted Figure 6; Renumbered Sequentially................................ 8
Changes to Figure 13 and Figure 14............................................. 11
Changes to Figure 27...................................................................... 14
Changes to Table 9.......................................................................... 16
Changes to Figure 32...................................................................... 17
Changes to Figure 43...................................................................... 22
Changes to Figure 45...................................................................... 23
Updated Outline Dimensions....................................................... 26
Changes to Ordering Guide .......................................................... 27
12/04—Rev. 0 to Rev. A
Changes to Specifications.................................................................3
Changes to Figure 17 Captions..................................................... 11
Changes to Power Supply Section................................................ 17
Changes to Digital Interface Section ........................................... 18
Changes to CS Mode 4-Wire No Busy Indicator Section ......... 21
Changes to CS Mode 4-Wire with Busy Indicator Section....... 22
Changes to Chain Mode, No Busy Indicator Section................ 23
Changes to Chain Mode with Busy Indicator Section .............. 24
Added True 16-Bit Isolated Application Example Section ....... 26
Added Figure 47 ............................................................................. 26
Changes to Ordering Guide.......................................................... 28
4/04—Revision 0: Initial Revision
AD7685
Rev. C | Page 3 of 28
SPECIFICATIONS
VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, TA = –40°C to +85°C, unless otherwise noted.
Table 2.
A Grade B Grade C Grade
Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION 16 16 16 Bits
ANALOG INPUT
Voltage Range IN+ − IN− 0 VREF 0 VREF 0 VREF V
Absolute Input Voltage IN+ −0.1 VDD +
0.1
−0.1 VDD +
0.1
−0.1 VDD +
0.1
V
IN− −0.1 +0.1 −0.1 +0.1 −0.1 +0.1 V
Analog Input CMRR fIN = 250 kHz 65 65 65 dB
Leakage Current at 25°C Acquisition phase 1 1 1 nA
Input Impedance See the
Analog Inputs section
See the
Analog Inputs section
See the
Analog Inputs section
ACCURACY
No Missing Codes 15 16 16 Bits
Differential Linearity Error −1 ±0.7 −1 ±0.5 +1.5 LSB1
Integral Linearity Error −6 +6 −3 ±1 +3 −2 ±0.6 +2 LSB
Transition Noise REF = VDD = 5 V 0.5 0.5 0.45 LSB
Gain Error2, TMIN to TMAX ±2 ±30 ±2 ±30 ±2 ±15 LSB
Gain Error Temperature Drift ±0.3 ±0.3 ±0.3 ppm/°C
Offset Error2, TMIN to TMAX VDD = 4.5 V to 5.5 V ±0.1 ±1.6 ±0.1 ±1.6 ±0.1 ±1.6 mV
VDD = 2.3 V to 4.5 V ±0.7 ±3.5 ±0.7 ±3.5 ±0.7 ±3.5 mV
Offset Temperature Drift ±0.3 ±0.3 ±0.3 ppm/°C
Power Supply Sensitivity VDD = 5 V ± 5% ±0.05 ±0.05 ±0.05 LSB
THROUGHPUT
Conversion Rate VDD = 4.5 V to 5.5 V 0 250 0 250 0 250 kSPS
VDD = 2.3 V to 4.5 V 0 200 0 200 0 200 kSPS
Transient Response Full-scale step 1.8 1.8 1.8 μs
AC ACCURACY
Signal-to-Noise Ratio fIN = 20 kHz,
VREF = 5 V
90 90 92 91.5 93.5 dB3
f
IN = 20 kHz,
VREF = 2.5 V
86 86 88 87.5 88.5 dB
Spurious-Free Dynamic
Range
fIN = 20 kHz −100 −106 −110 dB
Total Harmonic Distortion fIN = 20 kHz −100 −106 −110 dB
Signal-to-(Noise + Distortion) fIN = 20 kHz,
VREF = 5 V
89 90 92 91.5 93.5 dB
f
IN = 20 kHz,
VREF = 5 V,
−60 dB input
32 33.5 dB
f
IN = 20 kHz,
VREF = 2.5 V
86 85.5 87.5 87 88.5 dB
Intermodulation Distortion4 −110 −115 dB
1 LSB means least significant bit. With the 5 V input range, 1 LSB is 76.3 μV.
2 See Terminology section. These specifications do include full temperature range variation but do not include the error contribution from the external reference.
3 All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.
4 fIN1 = 21.4 kHz, fIN2 = 18.9 kHz, each tone at −7 dB below full scale.
AD7685
Rev. C | Page 4 of 28
VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, TA = –40°C to +85°C, unless otherwise noted.
Table 3.
Parameter Conditions Min Typ Max Unit
REFERENCE
Voltage Range 0.5 VDD + 0.3 V
Load Current 250 kSPS, REF = 5 V 50 μA
SAMPLING DYNAMICS
−3 dB Input Bandwidth 2 MHz
Aperture Delay VDD = 5 V 2.5 ns
DIGITAL INPUTS
Logic Levels
VIL –0.3 0.3 × VIO V
VIH 0.7 × VIO VIO + 0.3 V
IIL −1 +1 μA
IIH −1 +1 μA
DIGITAL OUTPUTS
Data Format Serial 16 bits straight binary
Pipeline Delay Conversion results available immediately
after completed conversion
VOL I
SINK = +500 μA 0.4 V
VOH I
SOURCE = −500 μA VIO − 0.3 V
POWER SUPPLIES
VDD Specified performance 2.3 5.5 V
VIO Specified performance 2.3 VDD + 0.3 V
VIO Range 1.8 VDD + 0.3 V
Standby Current1, 2 VDD and VIO = 5 V, 25°C 1 50 nA
Power Dissipation VDD = 2.5 V, 100 SPS throughput 1.4 μW
VDD = 2.5 V, 100 kSPS throughput 1.35 2.4 mW
VDD = 2.5 V, 200 kSPS throughput 2.7 4.8 mW
VDD = 5 V, 100 kSPS throughput 4 6 mW
VDD = 5 V, 250 kSPS throughput 10 15 mW
TEMPERATURE RANGE3
Specified Performance TMIN to TMAX −40 +85 °C
1 With all digital inputs forced to VIO or GND as required.
2 During acquisition phase.
3 Contact sales for extended temperature range.
AD7685
Rev. C | Page 5 of 28
TIMING SPECIFICATIONS
−40°C to +85°C, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.
Table 4. VDD = 4.5 V to 5.5 V1
Parameter Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge To Data Available tCONV 0.5 2.2 μs
Acquisition Time tACQ 1.8 μs
Time Between Conversions tCYC 4 μs
CNV Pulse Width (CS Mode) tCNVH 10 ns
SCK Period (CS Mode) tSCK 15 ns
SCK Period (Chain Mode) tSCK
VIO Above 4.5 V 17 ns
VIO Above 3 V 18 ns
VIO Above 2.7 V 19 ns
VIO Above 2.3 V 20 ns
SCK Low Time tSCKL 7 ns
SCK High Time tSCKH 7 ns
SCK Falling Edge to Data Remains Valid tHSDO 5 ns
SCK Falling Edge to Data Valid Delay tDSDO
VIO Above 4.5 V 14 ns
VIO Above 3 V 15 ns
VIO Above 2.7 V 16 ns
VIO Above 2.3 V 17 ns
CNV or SDI Low to SDO D15 MSB Valid (CS Mode) tEN
VIO Above 4.5 V 15 ns
VIO Above 2.7 V 18 ns
VIO Above 2.3 V 22 ns
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) tDIS 25 ns
SDI Valid Setup Time from CNV Rising Edge (CS Mode) tSSDICNV 15 ns
SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 0 ns
SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns
SCK Valid Hold Time from CNV Rising Edge (Chain Mode) tHSCKCNV 5 ns
SDI Valid Setup Time from SCK Falling Edge (Chain Mode) tSSDISCK 3 ns
SDI Valid Hold Time from SCK Falling Edge (Chain Mode) tHSDISCK 4 ns
SDI High to SDO High (Chain Mode with Busy Indicator) tDSDOSDI
VIO Above 4.5 V 15 ns
VIO Above 2.3 V 26 ns
1 See Figure 3 and Figure 4 for load conditions.
AD7685
Rev. C | Page 6 of 28
−40°C to +85°C, VIO = 2.3 V to 4.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.
Table 5. VDD = 2.3V to 4.5 V1
Parameter Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available tCONV 0.7 3.2 μs
Acquisition Time tACQ 1.8 μs
Time Between Conversions tCYC 5 μs
CNV Pulse Width (CS Mode) tCNVH 10 ns
SCK Period (CS Mode) tSCK 25 ns
SCK Period (Chain Mode) tSCK
VIO Above 3 V 29 ns
VIO Above 2.7 V 35 ns
VIO Above 2.3 V 40 ns
SCK Low Time tSCKL 12 ns
SCK High Time tSCKH 12 ns
SCK Falling Edge to Data Remains Valid tHSDO 5 ns
SCK Falling Edge to Data Valid Delay tDSDO
VIO Above 3 V 24 ns
VIO Above 2.7 V 30 ns
VIO Above 2.3 V 35 ns
CNV or SDI Low to SDO D15 MSB Valid (CS Mode) tEN
VIO Above 2.7 V 18 ns
VIO Above 2.3 V 22 ns
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) tDIS 25 ns
SDI Valid Setup Time from CNV Rising Edge (CS Mode) tSSDICNV 30 ns
SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 0 ns
SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns
SCK Valid Hold Time from CNV Rising Edge (Chain Mode) tHSCKCNV 8 ns
SDI Valid Setup Time from SCK Falling Edge (Chain Mode) tSSDISCK 5 ns
SDI Valid Hold Time from SCK Falling Edge (Chain Mode) tHSDISCK 4 ns
SDI High to SDO High (Chain Mode with Busy Indicator) tDSDOSDI 36 ns
1 See Figure 3 and Figure 4 for load conditions.
500µA I
OL
500µA I
OH
1.4V
TO SDO
C
L
50pF
02968-002
Figure 3. Load Circuit for Digital Interface Timing
30% VIO
70% VIO
2V OR VIO – 0.5V
1
0.8V OR 0.5V
2
0.8V OR 0.5V
2
2V OR VIO – 0.5V
1
tDELAY tDELAY
02968-003
NOTES
1. 2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.
2. 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
Figure 4. Voltage Levels for Timing
AD7685
Rev. C | Page 7 of 28
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Rating
Analog Inputs
IN+1, IN−1, REF GND − 0.3 V to VDD + 0.3 V
or ±130 mA
Supply Voltages
VDD, VIO to GND −0.3 V to +7 V
VDD to VIO ±7 V
Digital Inputs to GND −0.3 V to VIO + 0.3 V
Digital Outputs to GND −0.3 V to VIO + 0.3 V
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance 200°C/W (MSOP-10)
θJC Thermal Impedance 44°C/W (MSOP-10)
Lead Temperature
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
1 See the Analog Inputs section.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD7685
Rev. C | Page 8 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
REF
1
VDD
2
IN+
3
IN–
4
GND
5
VIO
10
SDI
9
SCK
8
SDO
7
CNV
6
AD7685
TOP VIEW
(Not to Scale)
02968-004
Figure 5. 10-Lead MSOP Pin Configuration
1REF
2VDD
3IN+
4IN–
5GND
10 VIO
9SDI
8SCK
7SDO
6CNV
TOP VIEW
(Not to Scale)
AD7685
02968-005
NOTES
1. EXPOSED PAD CONNECTED TO GND. THIS
CONNECTION IS NOT REQUIRED TO MEE
T
THE ELECTRICAL PERFORMANCES.
Figure 6. 10-Lead QFN (LFCSP) Pin Configuration
Table 7. Pin Function Descriptions
Pin No Mnemonic Type1 Description
1 REF AI
Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This pin should
be decoupled closely to the pin with a 10 μF capacitor.
2 VDD P Power Supply.
3 IN+ AI Analog Input. It is referred to IN−. The voltage range, that is, the difference between IN+ and IN−, is 0 V to VREF.
4 IN− AI Analog Input Ground Sense. Connect to the analog ground plane or to a remote sense ground.
5 GND P Power Supply Ground.
6 CNV DI
Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and
selects the interface mode of the part, chain, or CS mode. In CS mode, it enables the SDO pin when low.
In chain mode, the data should be read when CNV is high.
7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
8 SCK DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
9 SDI DI Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input
to daisy chain the conversion results of two or more ADCs onto a single SDO line. The digital data level
on SDI is output on SDO with a delay of 16 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable
the serial output signals when low, and if SDI or CNV is low when the conversion is complete, the BUSY
indicator feature is enabled.
10 VIO P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V).
EPAD
Exposed Pad. Exposed pad connected to GND. This connection is not required to meet the electrical
performances.
1AI = analog input, DI = digital input, DO = digital output, and P = power.
AD7685
Rev. C | Page 9 of 28
TERMINOLOGY
Integral Nonlinearity Error (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (see Figure 26).
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Offset Error
The first transition should occur at a level ½ LSB above analog
ground (38.1 μV for the 0 V to 5 V range). The offset error is
the deviation of the actual transition from that point.
Gain Error
The last transition (from 111 . . . 10 to 111 . . . 11) should
occur for an analog voltage 1½ LSB below the nominal full
scale (4.999886 V for the 0 V to 5 V range). The gain error is the
deviation of the actual level of the last transition from the ideal
level after the offset is adjusted out.
Spurious-Free Dynamic Range (SFDR)
The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD by
ENOB = (SINADdB − 1.76)/6.02
and is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in dB.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in dB.
Signal-to-(Noise + Distortion), SINAD
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in dB.
Aperture Delay
Aperture delay is a measure of the acquisition performance and
is the time between the rising edge of the CNV input and when
the input signal is held for a conversion.
Transient Response
The time required for the ADC to accurately acquire its input
after a full-scale step function is applied.
AD7685
Rev. C | Page 10 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
02968-047
CODE
655360 16384 32768 49152
INL (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
POSITIVE INL = +0.33LSB
NEGATIVE INL = –0.50LSB
Figure 7. Integral Nonlinearity vs. Code
02968-006
CODE IN HEX
80EA 80EB 80EC 80ED80E5 80E6 80E7 80E8 80E9
COUNTS
250000
200000
150000
100000
50000
0
0012 00
204292
27755
29041
20
VDD = REF = 5V
Figure 8. Histogram of a DC Input at the Code Center
02968-007
FREQUENCY (kHz)
1200 20406080100
AMPLITUDE (dB OF FULL SCALE)
0
–20
–40
–60
–80
–100
–120
–160
–140
–180
8192 POINT FFT
VDD = REF = 5V
f
S
= 250kSPS
f
IN
= 20.45kHz
SNR = 93.3dB
THD = –111.6dB
SFDR = –113.7dB
SECOND HARMONIC = –113.7dB
THIRD HARMONIC = –117.6dB
Figure 9. FFT Plot
02968-008
CODE
655360 16384 32768 49152
DNL (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
POSITIVE DNL = +0.21LSB
NEGATIVE DNL = –0.30LSB
Figure 10. Differential Nonlinearity vs. Code
02968-009
CODE IN HEX
8058804E 804F 8050 8051 8052 8053 8054 8055 8056 8057
COUNTS
140000
120000
100000
80000
60000
40000
20000
0
02
213
6956
179 0 0
60966
125055
8667
59082
VDD = REF = 2.5V
Figure 11. Histogram of a DC Input at the Code Center
02968-010
FREQUENCY (kHz)
1200 20406080100
AMPLITUDE (dB OF FULL SCALE)
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
16384 POINT FFT
VDD = REF = 2.5V
f
S
= 250kSPS
f
IN
= 20.45kHz
SNR = 88.8dB
THD = –103.5dB
SFDR = –104.5dB
SECOND HARMONIC = –112.4dB
THIRD HARMONIC = –105.4dB
Figure 12. FFT Plot
AD7685
Rev. C | Page 11 of 28
02968-011
REFERENCE VOLTAGE (V)
5.52.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1
ENOB (Bits)
13
17
16
15
14
SINAD (dB)
100
95
90
85
80
SNR
SINAD
ENOB
Figure 13. SNR, SINAD, and ENOB vs. Reference Voltage
02968-012
SINAD (dB)
FREQUENCY (kHz)
2000 50 100 150
100
95
90
85
80
75
70
V
REF
= 5V, –1dB
V
REF
= 2.5V, –1dB
V
REF
= 5V, –10dB
Figure 14. SINAD vs. Frequency
02968-013
TEMPERATURE (°C)
125–55 –35 –15 5 25 45 65 85 105
SNR (dB)
100
95
90
85
80
75
70
V
REF
= 5V
V
REF
= 2.5V
Figure 15. SNR vs. Temperature
02968-014
REFERENCE VOLTAGE (V)
5.52.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1
THD, SFDR (dB)
90
–95
–100
–105
–110
–115
–120
–125
–130
SFDR
THD
Figure 16. THD, SFDR vs. Reference Voltage
02968-015
FREQUENCY (kHz)
2000 50 100 150
THD (dB)
60
–70
–80
–90
–100
–110
–120
V
REF
= 2.5V, –1dB
V
REF
= 5V, –1dB
V
REF
= 5V, –10dB
Figure 17. THD vs. Frequency
02968-016
TEMPERATURE (°C)
125–55 –35 –15 5 25 45 65 85 105
THD (dB)
90
–100
–110
–120
–130
V
REF
= 2.5V
V
REF
= 5V
Figure 18. THD vs. Temperature
AD7685
Rev. C | Page 12 of 28
02968-017
INPUT LEVEL (dB)
0–10 –8 –6 –4 –2
THD (dB)
–120
105
–110
–115
SNR REFERENCE TO FULL SCALE (dB)
95
94
93
92
91
90
SNR
THD
02968-020
TEMPERATURE (°C)
125–55 –35 –15 5 25 45 65 85 105
OPER
A
TING CURRENTS (µA)
1000
750
500
250
0
VDD = 5V
VIO
f
S
= 100kSPS
VDD = 2.5V
Figure 19. SNR and THD vs. Input Level Figure 22. Operating Currents vs. Temperature
02968-021
TEMPERATURE (°C)
125–55 –35 –15 5 25 45 65 85 105
OFFSET, GAIN ERROR (LSB)
6
4
5
2
3
0
1
–2
–1
–4
–3
–6
–5
GAIN ERROR
OFFSET ERROR
02968-018
SUPPLY (V)
5.52.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1
OPER
A
TING CURRENTS (µA)
1000
750
500
250
0
VDD
VIO
f
S
= 100kSPS
Figure 23. Offset and Gain Error vs. Temperature
Figure 20. Operating Currents vs. Supply
02968-022
SDO CAPACITIVE LOAD (pF)
120020406080100
t
DSDO
DELAY (ns)
25
20
15
10
5
0
VDD = 2.5V, 85°C
VDD = 3.3V, 25°C
VDD = 3.3V, 85°C
VDD = 5V, 85°C
VDD = 5V, 25°C
VDD = 2.5V, 25°C
02968-019
TEMPERATURE (°C)
125–55 –35 –15 5 25 45 65 85 105
POWER-DOWN CURRENTS (nA)
1000
750
500
250
0
VDD + VIO
Figure 24. tDSDO Delay vs. Capacitance Load and Supply
Figure 21. Power-Down Currents vs. Temperature
AD7685
Rev. C | Page 13 of 28
THEORY OF OPERATION
SW+MSB
16,384C
IN+
LSB
COMP CONTROL
LOGIC
SW I T CHES CONTROL
BUSY
OUTPUT CODE
CNV
REF
GND
IN–
4C 2C C C32,768C
SW–MSB
16,384C
LSB
4C 2C C C32,768C
02968-023
Figure 25. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7685 is a fast, low power, single-supply, precise 16-bit
ADC using a successive approximation architecture.
The AD7685 is capable of converting 250,000 samples per
second (250 kSPS) and powers down between conversions.
When operating at 100 SPS, for example, it consumes typically
1.35 μW with a 2.5 V supply, ideal for battery-powered
applications.
The AD7685 provides the user with on-chip, track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple multiplexed channel applications.
The AD7685 is specified from 2.3 V to 5.5 V and can be
interfaced to any 1.8 V to 5 V digital logic family. It is housed in
a 10-lead MSOP or a tiny 10-lead QFN (LFCSP) that combines
space savings and allows flexible configurations.
It is pin-for-pin-compatible with the AD7686, AD7687, and
AD7688.
CONVERTER OPERATION
The AD7685 is a successive approximation ADC based on a
charge redistribution DAC. Figure 25 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary weighted capacitors, which are
connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to GND via SW+ and SW−.
All independent switches are connected to the analog inputs.
Therefore, the capacitor arrays are used as sampling capacitors
and acquire the analog signal on the IN+ and IN− inputs. When
the acquisition phase is complete and the CNV input goes high,
a conversion phase is initiated. When the conversion phase
begins, SW+ and SW− are opened rst. e two capacitor
arrays are then disconnected from the inputs and connected to
the GND input. Therefore, the differential voltage between the
inputs IN+ and IN− captured at the end of the acquisition phase
is applied to the comparator inputs, causing the comparator to
become unbalanced. By switching each element of the capacitor
array between GND and REF, the comparator input varies by
binary weighted voltage steps (VREF/2, VREF/4 . . . VREF/65536).
The control logic toggles these switches, starting with the MSB,
to bring the comparator back into a balanced condition. After
the completion of this process, the part powers down and
returns to the acquisition phase, and the control logic generates
the ADC output code and a BUSY signal indicator.
Because the AD7685 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
AD7685
Rev. C | Page 14 of 28
Transfer Functions
The ideal transfer characteristic for the AD7685 is shown in
Figure 26 and Table 8.
000...000
000...001
000...010
111...101
111...110
111...111
ADC CODE (STRAIGHT BIN
A
R
Y)
ANALOG INPUT
+FS – 1.5 LSB
+FS – 1 LSB
–FS + 1 LSB
–FS
–FS + 0.5 LSB
02968-024
Figure 26. ADC Ideal Transfer Function
TYPICAL CONNECTION DIAGRAM
Figure 27 shows an example of the recommended connection
diagram for the AD7685 when multiple supplies are available.
AD7685
REF
GND
VDD
IN–
IN+
VIO
SDI
SCK
SDO
CNV
3- OR 4-WIRE INTERFACE
5
100nF
100nF
5V
10µF
2
7V
7V
–2V
1.8V TO VDD
REF
1
0 TO VREF
33
2.7nF
3
4
02968-025
NOTES
1. SEE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION.
2. C
REF
IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
3. SEE DRIVER AMPLIFIER CHOICE SECTION.
4. OPTIONAL FILTER. SEE ANALOG INPUT SECTION.
5. SEE DIGITAL INTERFACE FOR MOST CONVENIENT INTERFACE MODE.
Figure 27. Typical Application Diagram with Multiple Supplies
Table 8. Output Codes and Ideal Input Voltages
Description Analog Input VREF = 5 V Digital Output Code Hexa
FSR – 1 LSB 4.999924 V FFFF1
Midscale + 1 LSB 2.500076 V 8001
Midscale 2.5 V 8000
Midscale – 1 LSB 2.499924 V 7FFF
–FSR + 1 LSB 76.3 μV 0001
–FSR 0 V 00002
1 This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND).
2 This is also the code for an underranged analog input (VIN+ − VIN− below VGND).
AD7685
Rev. C | Page 15 of 28
ANALOG INPUTS
Figure 28 shows an equivalent circuit of the input structure of
the AD7685.
The two diodes, D1 and D2, provide ESD protection for the
analog inputs IN+ and IN−. Care must be taken to ensure that
the analog input signal never exceeds the supply rails by more
than 0.3 V because this will cause these diodes to begin to
forward-bias and start conducting current. These diodes can
handle a forward-biased current of 130 mA maximum. For
instance, these conditions could eventually occur when the
input buffer’s (U1) supplies are different from VDD. In such a
case, an input buffer with a short-circuit current limitation can
be used to protect the part.
C
IN
R
IN
D1
D2
C
PIN
IN+
OR IN
GND
V
DD
02968-026
Figure 28. Equivalent Analog Input Circuit
This analog input structure allows the sampling of the
differential signal between IN+ and IN−. By using this
differential input, small signals common to both inputs are
rejected, as shown in Figure 29, which represents the typical
CMRR over frequency. For instance, by using IN to sense a
remote signal ground, ground potential differences between
the sensor and the local ADC ground are eliminated.
02968-027
FREQUENCY (kHz)
100001 10 100 1000
CMRR (dB)
80
70
60
50
40
V
DD
= 5V
V
DD
= 2.5V
Figure 29. Analog Input CMRR vs. Frequency
During the acquisition phase, the impedance of the analog
inputs (IN+ or IN−) can be modeled as a parallel combination
of capacitor CPIN and the network formed by the series connection
of RIN and CIN. CPIN is primarily the pin capacitance. RIN is
typically 3 kΩ and is a lumped component made up of some
serial resistors and the on resistance of the switches. CIN is
typically 30 pF and is mainly the ADC sampling capacitor.
During the conversion phase, where the switches are opened,
the input impedance is limited to CPIN. RIN and CIN make a
1-pole, low-pass filter that reduces undesirable aliasing effects
and limits the noise.
When the source impedance of the driving circuit is low, the
AD7685 can be driven directly. Large source impedances
significantly affect the ac performance, especially THD. The dc
performances are less sensitive to the input impedance. The
maximum source impedance depends on the amount of THD
that can be tolerated. The THD degrades as a function of the
source impedance and the maximum input frequency, as shown
in Figure 30.
02968-028
FREQUENCY (kHz)
1000 255075
THD (dB)
60
–70
–80
–90
–100
–110
–120
R
S
= 33
R
S
= 50
R
S
= 100
R
S
= 250
Figure 30. THD vs. Analog Input Frequency and Source Resistance
AD7685
Rev. C | Page 16 of 28
DRIVER AMPLIFIER CHOICE
Although the AD7685 is easy to drive, the driver amplifier
needs to meet the following requirements:
The noise generated by the driver amplifier needs to be kept
as low as possible to preserve the SNR and transition noise
performance of the AD7685. Note that the AD7685 has a
noise much lower than most of the other 16-bit ADCs and,
therefore, can be driven by a noisier amplifier to meet a given
system noise specification. The noise coming from the
amplifier is filtered by the AD7685 analog input circuit low-
pass filter made by RIN and CIN or by an external filter, if one
is used. Because the typical noise of the AD7685 is 35 μV
rms, the SNR degradation due to the amplifier is
+
=
2
3dB
2)(f
2
π
35
35
20log
N
LOSS
Ne
SNR
where:
f–3dB is the input bandwidth in MHz of the AD7685
(2 MHz) or the cutoff frequency of the input filter, if one is
used.
N is the noise gain of the amplifier (for example, 1 in buffer
configuration).
eN is the equivalent input noise voltage of the op amp, in
nV/√Hz.
For ac applications, the driver should have a THD
performance commensurate with the AD7685. Figure 17
shows the AD7685’s THD vs. frequency.
For multichannel, multiplexed applications, the driver
amplifier and the AD7685 analog input circuit must settle a
full-scale step onto the capacitor array at a 16-bit level
(0.0015%). In the amplifier’s data sheet, settling at 0.1% to
0.01% is more commonly specified. This could differ
significantly from the settling time at a 16-bit level and
should be verified prior to driver selection.
Table 9. Recommended Driver Amplifiers
Amplifier Typical Application
ADA4841-x Very low noise and low power
AD8605, AD8615 5 V single-supply, low power
AD8655 5 V single-supply, low power
OP184 Low power, low noise, and low frequency
AD8021 Very low noise and high frequency
AD8022 Very low noise and high frequency
AD8519 Small, low power and low frequency
AD8031 High frequency and low power
VOLTAGE REFERENCE INPUT
The AD7685 voltage reference input, REF, has a dynamic input
impedance and should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.
When REF is driven by a very low impedance source, for
example, a reference buffer using the AD8031 or the AD8605, a
10 μF (X5R, 0805 size) ceramic chip capacitor is appropriate for
optimum performance.
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 μF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift ADR43x reference.
If desired, smaller reference decoupling capacitor values down
to 2.2 μF can be used with a minimal impact on performance,
especially DNL.
POWER SUPPLY
The AD7685 is specified over a wide operating range from
2.3 V to 5.5 V. It has, unlike other low voltage converters, a
noise low enough to design a 16-bit resolution system with low
supply and respectable performance. It uses two power supply
pins: a core supply VDD and a digital input/output interface
supply VIO. VIO allows direct interface with any logic between
1.8 V and VDD. To reduce the number of supplies needed, the
VIO and VDD can be tied together. The AD7685 is independent of
power supply sequencing between VIO and VDD. Additionally,
it is very insensitive to power supply variations over a wide
frequency range, as shown in Figure 31, which represents PSRR
over frequency.
02968-029
FREQUENCY (kHz)
100001 10 100 1000
PSRR (dB)
110
80
90
100
70
60
50
40
30
VDD = 5V
VDD = 2.5V
Figure 31. PSRR vs. Frequency
AD7685
Rev. C | Page 17 of 28
The AD7685 powers down automatically at the end of each
conversion phase and, therefore, the power scales linearly with
the sampling rate, as shown in Figure 32. This makes the part
ideal for low sampling rate (even a few Hz) and low battery-
powered applications.
02968-030
SAMPLING RATE (SPS)
100000010 100 1000 10000 100000
OPER
A
TING CURRENTS (µA)
1000
10
0.1
0.001
10000
100
1
0.01
VDD = 5V
VIO
VDD = 2.5V
Figure 32. Operating Currents vs. Sampling Rate
SUPPLYING THE ADC FROM THE REFERENCE
For simplified applications, the AD7685, with its low operating
current, can be supplied directly using the reference circuit, as
shown in Figure 33. The reference line can be driven by either:
The system power supply directly.
A reference voltage with enough current output capability,
such as the ADR43x.
A reference buffer, such as the AD8031, that can also filter
the system power supply, as shown in Figure 33.
AD8031
AD7685
VIOREF VDD
10µF 1µF
10
10k
5V
5V
5V
1µF
1
02968-031
1
OPTIONAL REFERENCE BUFFER AND FILTER.
Figure 33. Example of Application Circuit
DIGITAL INTERFACE
Though the AD7685 has a reduced number of pins, it offers
substantial flexibility in its serial interface modes.
The AD7685, when in CS mode, is compatible with SPI, QSPI,
digital hosts, and DSPs, for example, Blackfin® ADSP-BF53x or
ADSP-219x. This interface can use either 3-wire or 4-wire. A
3-wire interface using the CNV, SCK, and SDO signals minimizes
wiring connections, useful, for instance, in isolated applications.
A 4-wire interface using the SDI, CNV, SCK, and SDO signals
allows CNV, which initiates the conversions, to be independent
of the readback timing (SDI). This is useful in low jitter
sampling or simultaneous sampling applications.
The AD7685, when in chain mode, provides a daisy-chain
feature using the SDI input for cascading multiple ADCs on a
single data line similar to a shift register.
The mode in which the part operates depends on the SDI level
when the CNV rising edge occurs. The CS mode is selected if
SDI is high and the chain mode is selected if SDI is low. The
SDI hold time is such that when SDI and CNV are connected
together, the chain mode is always selected.
In either the CS mode or the chain mode, the AD7685 offers the
flexibility to optionally force a start bit in front of the data bits.
This start bit can be used as a BUSY signal indicator to
interrupt the digital host and trigger the data reading.
Otherwise, without a BUSY indicator, the user must time out
the maximum conversion time prior to readback.
The BUSY indicator feature is enabled as follows:
In the CS mode, if CNV or SDI is low when the ADC
conversion ends (see and ). Figure 37 Figure 41
In the chain mode, if SCK is high during the CNV rising edge
(see Figure 45).
AD7685
Rev. C | Page 18 of 28
CS MODE 3-WIRE, NO BUSY INDICATOR
This mode is usually used when a single AD7685 is connected
to an SPI-compatible digital host.
The connection diagram is shown in Figure 34, and the
corresponding timing is given in Figure 35.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. Once a conversion is initiated, it will continue to
completion irrespective of the state of CNV. For instance, it
could be useful to bring CNV low to select other SPI devices,
such as analog multiplexers, but CNV must be returned high
before the minimum conversion time and held high until the
maximum conversion time to avoid the generation of the BUSY
signal indicator. When conversion is completed, the AD7685
enters the acquisition phase and powers down. When CNV
goes low, the MSB is output onto SDO. The remaining data bits
are then clocked by subsequent SCK falling edges. The data is
valid on both SCK edges. Although the rising edge can be used
to capture the data, a digital host using the SCK falling edge will
allow a faster reading rate provided it has an acceptable hold
time. After the 16th SCK falling edge or when CNV goes high,
whichever is earlier, SDO returns to high impedance.
CNV
SCK
SDOSDI DATA IN
CLK
CONVERT
V
IO
DIGITAL HOST
AD7685
02968-032
Figure 34. CS Mode 3-Wire, No BUSY Indicator
Connection Diagram (SDI High)
SDO D15 D14 D13 D1 D0
t
DIS
SCK
1 2 3 14 15 16
t
SCK
t
SCKL
t
SCKH
t
HSDO
t
DSDO
CNV
CONVERSIONACQUISITION
t
CONV
t
CYC
ACQUISITION
SDI = 1
t
CNVH
t
ACQ
t
EN
02968-033
Figure 35. CS Mode 3-Wire, No BUSY Indicator Serial Interface Timing (SDI High)
AD7685
Rev. C | Page 19 of 28
CS MODE 3-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7685 is connected
to an SPI-compatible digital host having an interrupt input.
The connection diagram is shown in Figure 36, and the
corresponding timing is given in Figure 37.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV could be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time and
held low until the maximum conversion time to guarantee the
generation of the BUSY signal indicator. When the conversion
is complete, SDO goes from high impedance to low. With a
pull-up on the SDO line, this transition can be used as an
interrupt signal to initiate the data reading controlled by the
digital host. The AD7685 then enters the acquisition phase and
powers down. The data bits are then clocked out, MSB first, by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge will allow a faster reading
rate provided it has an acceptable hold time. After the optional
17th SCK falling edge, or when CNV goes high, whichever is
earlier, SDO returns to high impedance.
DATA IN
IRQ
CLK
CONVERT
VIO DIGITAL HOST
02968-034
47k
CNV
SCK
SDOSDI
V
IO
AD7685
Figure 36. CS Mode 3-Wire with BUSY Indicator
Connection Diagram (SDI High)
SDO
D15 D14 D1 D0
t
DIS
SCK
1 2 3 15 16 17
t
SCK
t
SCKL
t
SCKH
t
HSDO
t
DSDO
CNV
CONVERSIONACQUISITION
t
CONV
t
CYC
t
CNVH
t
ACQ
ACQUISITION
SDI = 1
2968-035
Figure 37. CS Mode 3-Wire with BUSY Indicator Serial Interface Timing (SDI High)
AD7685
Rev. C | Page 20 of 28
CS MODE 4-WIRE, NO BUSY INDICATOR
This mode is usually used when multiple AD7685s are
connected to an SPI-compatible digital host.
A connection diagram example using two AD7685s is shown in
Figure 38, and the corresponding timing is given in Figure 39.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI could
be used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion
time and held high until the maximum conversion time to
avoid the generation of the BUSY signal indicator. When the
conversion is complete, the AD7685 enters the acquisition
phase and powers down. Each ADC result can be read by
bringing low its SDI input, which consequently outputs the
MSB onto SDO. The remaining data bits are then clocked by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge will allow a faster
reading rate, provided it has an acceptable hold time. After the
16th SCK falling edge, or when SDI goes high, whichever is
earlier, SDO returns to high impedance and another AD7685
can be read.
If multiple AD7685s are selected at the same time, the SDO
output pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended to keep this contention
as short as possible to limit extra power dissipation.
DATA IN
CLK
CS1
CONVERT
CS2
DIGITAL HOST
02968-036
CNV
SCK
SDOSDI
AD7685
CNV
SCK
SDOSDI
AD7685
Figure 38. CS Mode 4-Wire, No BUSY Indicator Connection Diagram
SDO D15 D14 D13 D1 D0
tDIS
SCK 123 303132
tHSDO
tDSDO
tEN
CONVERSIONACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
SDI(CS1)
CNV
tSSDICNV
tHSDICNV
D1
14 15
tSCK
tSCKL
tSCKH
D0 D15 D14
17 1816
SDI(CS2)
02968-037
Figure 39. CS Mode 4-Wire, No BUSY Indicator Serial Interface Timing