AD7190 - Analog Devices - Datasheet.Directory

4.8 kHz Ultra-Low Noise 24-Bit

Sigma-Delta ADC with PGA

Preliminary Technical Data

AD7190

Rev.PrD 7/08

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Tel: 781.329.4700 www.analog.com

FEATURES

RMS Noise: 7 nV @ 4.7 Hz (gain = 128)

16.5 noise free bits @ 2.4 kHz (gain = 128)

Up to 23 noise free bits (gain = 1)

Offset drift: 5 nV/°C

Gain drift: 2 ppm/°C

Specified drift over time

Programmable gain (1 – 128)

Update rate: 4.7 Hz to 4.8 kHz

Internal or external clock

Simultaneous 50 Hz/60 Hz rejection

Four general purpose digital outputs

Power supply: 3 V to 5.25 V

Current: 6 mA

Temperature range: –40°C to +105°C

INTERFACE

3-wire serial

SPI®, QSPI™, MICROWIRE™, and DSP compatible

Schmitt trigger on SCLK

APPLICATIONS

Weigh scales

Strain gauge transducers

Pressure measurement

Temperature measurement

Chromatography

PLC/DCS Analog Input Modules

Data Acquisition

Medical and Scientific instrumentation

GENERAL DESCRIPTION

The AD7190 is a low noise, complete analog front end for high

precision measurement applications. It contains a low noise, 24-

bit ∑-∆ ADC. The on-chip low noise gain stage means that

signals of small amplitude can be interfaced directly to the

ADC.

The device can be configured to have two differential inputs or

four pseudo-differential inputs. The device can be operated

with either the internal clock or an external clock. The output

data rate from the part can be varied from 4.7 Hz to 4.8 kHz.

The device can be operated with a sinc3 or a sinc4 digital filter.

At the lower update rates, the sinc3 is useful to optimize the

settling time. The benefit of the sinc4 at low update rates is the

superior 50 Hz/60 Hz rejection. At the higher update rates, the

sinc4 filter gives best noise performance. For applications that

require all conversions to be settled, the AD7190 includes a

zero-latency feature.

The part operates with a power supply from 3 V to 5.25 V. It

consumes a current of 6 mA. It is housed in a 24-lead TSSOP

package.

FUNCTIONAL BLOCK DIAGRAM

AIN1

AIN2

MUX

AVDD

AGND

AIN3

AIN4

AD7190

SERIAL

INTERFACE

AND CONTROL

LOGIC

MCLK1

SIGMA DELTA

ADC

PGA

REFIN1(+) REFIN1(-)

REFERENCE

DETECT

AGNDAVDD

DOUT/RDY

DIN

SCLK

CLOCK

CIRCUITRY

MCLK2

AINCOM

DGNDDVDD

SYNC

REFIN2

(

)

REFIN2

(

)

TEMP

SENSOR

BPDSW

AGND

Figure 1.

AD7190 Preliminary Technical Data

Rev.PrD 7/08 | Page 2

SPECIFICATIONS

AVDD = 3 V to 5.25 V; DVDD = 2.7 V to 5.25 V; GND = 0 V; REFIN1(+) = AVDD ; REFIN1(-) = GND; MCLK = 4.9152 MHz; Sinc4 filter

selected; all specifications TMIN to TMAX, unless otherwise noted.

Table 1.

Parameter1 AD7190B Unit Test Conditions/Comments

Output Update Rate 4.7 to 4800 Hz nom Chop Disabled

1.17 to 1200 Hz nom Chop Enabled

No Missing Codes2 24 Bits min FS > 1

Resolution See RMS Noise and

Resolution

Specifications

RMS Noise and Update Rates See RMS Noise and

Resolution

Specifications

Integral Nonlinearity ±15 ppm of FSR max

Offset Error3 ±100/Gain µV typ Chop Disabled

±0.5 µV typ Chop Enabled

Offset Error Drift vs. Temperature4 ±150/Gain nV/°C typ Gain = 1 to 16. Chop Disabled

±10 nV/°C typ Gain = 32 to 128. Chop Disabled

±5 nV/°C typ Chop Enabled

Offset Error Drift vs. Time 25 nV/1000 Hours typ

Full-Scale Error3, 5 ±10 µV typ

Gain Drift vs. Temperature4 ±1 ppm/°C typ

Gain Drift vs. Time 10 ppm/1000 Hours typ

Power Supply Rejection 100 dB min VIN = 1 V/Gain. 120 dB typical.

ANALOG INPUTS

Differential Input Voltage Ranges ± VREF/gain V nom VREF = REFIN(+) − REFIN(−) , gain = 1 to 128

± (AVDD – 1V)/gain V min/max gain > 1

Absolute AIN Voltage Limits2

Unbuffered Mode GND − 50 mV V min

AVDD + 50 mV V max

Buffered Mode GND + 200 mV V min

AVDD − 200 mV V max

Analog Input Current

Buffered Mode

Input Current2 ±1 nA max Gain = 1

±3 nA typ Gain > 1

Input Current Drift ±2 pA/°C typ

Unbuffered Mode

Input Current ±5 µA/V typ Gain = 1. Input current varies with input voltage

±1 µA/V typ Gain > 1.

Input Current Drift ±50 pA/V/°C typ

Normal Mode Rejection2

@ 50 Hz, 60 Hz 98 dB min 10 Hz Update Rate, 50 ± 1 Hz, 60 ± 1 Hz

TBD dB min 50 Hz Update Rate, REJ606 = 1, 50 ± 1 Hz, 60 ± 1 Hz

@ 50 Hz TBD dB min 50 Hz Update Rate, 50 ± 1 Hz

@ 60 Hz TBD dB min 60 Hz Update Rate, 60 ± 1 Hz

Common-Mode Rejection

@ DC 100 dB min AIN = 1 V/gain

@ 50 Hz, 60 Hz2 100 dB min 10 Hz Update Rate, 50 ± 1 Hz, 60 ± 1 Hz

@ 50 Hz, 60 Hz2 100 dB min 50 ± 1 Hz (50 Hz Update Rate), 60 ± 1 Hz (60 Hz

Update Rate)

REFERENCE INPUT

REFIN Voltage AVDD V nom REFIN = REFIN(+) − REFIN(−)

Preliminary Technical Data AD7190

Rev.PrD 7/08 | Page 3

Parameter1 AD7190B Unit Test Conditions/Comments

Reference Voltage Range2 1 V min

AVDD V max The differential input must be limited to ± (AVDD –

1V)/gain when gain > 1

Absolute REFIN Voltage Limits2 GND – 50 mV V min

AVDD + 50 mV V max

Average Reference Input Current 6 µA/V typ

Average Reference Input Current

Drift

±0.03 nA/V/°C typ

Normal Mode Rejection2 Same as for analog

inputs

Common-Mode Rejection 100 dB typ

Reference Detect Levels 0.3 V min

0.5 V max

TEMPERATURE SENSOR

Accuracy +2 °C typ Applies after user-calibration at one temperature

Sensitivity 2800 codes/°C typ

LOW SIDE POWER SWITCH

RON 7

Ω max AVDD = 5 V

Ω max AVDD = 3 V

Allowable Current2 30 mA max Continuous Current

BURNOUT CURRENTS

AIN Current 500 nA nom

DIGITAL OUTPUTS (P0 – P3)

VOH, Output High Voltage2 AVDD − 0.6 V min AVDD = 3V, ISOURCE = 100 µA

VOL, Output Low Voltage2 0.4 V max

AVDD = 3V, ISINK = 100 µA

VOH, Output High Voltage2 4 V min

AVDD = 5V, ISOURCE = 200 µA

VOL, Output Low Voltage2 0.4 V max

AVDD = 5V, ISINK = 800 µA

Floating-State Leakage Current ±10 µA max

Floating-State Output Capacitance 10 pF typ

INTERNAL/EXTERNAL CLOCK

Internal Clock

Frequency 4.92 + 4% MHz min/max

Duty Cycle 50:50 % typ

External Clock/Crystal

Frequency 4.9152 MHz nom

2.4576/5.12 MHz min/max

VINL, Input Low Voltage 0.8 V max DVDD = 5 V

0.4 V max DVDD = 3 V

VINH, Input High Voltage 2.5 V min DVDD = 3 V

3.5 V min DVDD = 5 V

Input Current ±10 µA max MCLKIN = DVDD or GND

LOGIC INPUTS

VT(+) 1.4/2 V min/V max DVDD = 5 V

VT(−) 0.8/1.7 V min/V max DVDD = 5 V

VT(+) − VT(−) 0.1/0.17 V min/V max DVDD = 5 V

VT(+) 0.9/2 V min/V max DVDD = 3 V

VT(−) 0.4/1.35 V min/V max DVDD = 3 V

VT(+)− VT(−) 0.06/0.13 V min/V max DVDD = 3 V

Input Currents ±10 µA max VIN = DVDD or GND

LOGIC OUTPUT (DOUT/RDY)

VOH, Output High Voltage2 DVDD − 0.6 V min DVDD = 3 V, ISOURCE = 100 µA

VOL, Output Low Voltage2 0.4 V max DVDD = 3 V, ISINK = 100 µA

VOH, Output High Voltage2 4 V min DVDD = 5 V, ISOURCE = 200 µA

AD7190 Preliminary Technical Data

Rev.PrD 7/08 | Page 4

Parameter1 AD7190B Unit Test Conditions/Comments

VOL, Output Low Voltage2 0.4 V max DVDD = 5 V, ISINK = 1.6 mA

Floating-State Leakage Current ±10 µA max

Floating-State Output Capacitance 10 pF typ

Data Output Coding Offset binary

SYSTEM CALIBRATION2

Full-Scale Calibration Limit 1.05 × FS V max

Zero-Scale Calibration Limit −1.05 × FS V min

Input Span 0.8 × FS V min

2.1 × FS V max

POWER REQUIREMENTS7

Power Supply Voltage

AVDD − AGND 3/5.25 V min/max

DVDD − DGND 2.7/5.25 V min/max

Power Supply Currents

AIDD Current TBD mA max Gain = 1, Buffer off

TBD mA max Gain = 8, Buffer off

TBD mA max Gain = 8, Buffer on

TBD mA max Gain = 16 – 128, Buffer off

TBD mA max Gain = 16 – 128, Buffer on

DIDD Current TBD mA max DVDD = 3 V

1 mA max DVDD = 5 V

IDD (Power-Down Mode) 1 µA max

1 Temperature range: −40°C to +105°C.

2 Specification is not production tested but is supported by characterization data at initial product release.

3 Following a calibration, this error will be in the order of the noise for the programmed gain and update rate selected.

4 Recalibration at any temperature will remove these errors.

5 Full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (AVDD = 5 V, gain = 1, TA = 25°C).

6 REJ60 is a bit in the Mode Register. When the update rate is set to 50 Hz, setting REJ60 to ‘1’ places a notch at 60 Hz, allowing simultaneous 50 Hz/60 Hz rejection.

7 Digital inputs equal to DVDD or GND.

Preliminary Technical Data AD7190

Rev.PrD 7/08 | Page 5

TIMING CHARACTERISTICS

AVDD = 3 V to 5.25 V; DVDD = 2.7 V to 5.25 V; GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted.

Table 2.

Parameter1, 2 Limit at TMIN, TMAX (B Version) Unit Conditions/Comments

t3 100 ns min SCLK high pulse width

t4 100 ns min SCLK low pulse width

Read Operation

t1 0 ns min CS falling edge to DOUT/RDY active time

60 ns max DVDD = 4.75 V to 5.25 V

80 ns max DVDD = 2.7 V to 3.6 V

t23 0 ns min SCLK active edge to data valid delay4

60 ns max DVDD = 4.75 V to 5.25 V

80 ns max DVDD = 2.7 V to 3.6 V

t55, 6 10 ns min Bus relinquish time after CS inactive edge

80 ns max

t6 0 ns min SCLK inactive edge to CS inactive edge

t7 10 ns min SCLK inactive edge to DOUT/RDY high

Write Operation

t8 0 ns min CS falling edge to SCLK active edge setup time4

t9 30 ns min Data valid to SCLK edge setup time

t10 25 ns min Data valid to SCLK edge hold time

t11 0 ns min CS rising edge to SCLK edge hold time

1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.

2 See Figure 3 and Figure 4.

3 These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.

4 SCLK active edge is falling edge of SCLK.

5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number

is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the

true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.

6 RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high,

although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read

only once.

04854-002

SINK

(1.6mA WITH DV

= 5V,

100µA WITH DV

= 3V)

SOURCE

(200µA WITH DV

= 5V,

100µA WITH DV

= 3V)

1.6V

OUTPUT

PIN 50pF

Figure 2. Load Circuit for Timing Characterization

AD7190 Preliminary Technical Data

Rev.PrD 7/08 | Page 6

TIMING DIAGRAMS

04854-003

t1t6t5

CS (I)

DOUT/RDY (O)

SCLK (I)

I = INPUT, O = OUTPUT

MSB LSB

Figure 3. Read Cycle Timing Diagram

04854-004

I = INPUT, O = OUTPUT

CS (I)

CLK (I)

DIN (I) MSB LSB

Figure 4. Write Cycle Timing Diagram

Preliminary Technical Data AD7190

Rev.PrD 7/08 | Page 7

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to GND −0.3 V to +6.5 V

DVDD to GND −0.3 V to +6.5 V

Analog Input Voltage to GND −0.3 V to AVDD + 0.3 V

Reference Input Voltage to GND −0.3 V to AVDD + 0.3 V

Digital Input Voltage to GND −0.3 V to DVDD + 0.3 V

Digital Output Voltage to GND −0.3 V to DVDD + 0.3 V

AIN/Digital Input Current 10 mA

Operating Temperature Range −40°C to +105°C

Storage Temperature Range −65°C to +150°C

Maximum Junction Temperature 150°C

TSSOP

θJA Thermal Impedance 97.9°C/W

θJC Thermal Impedance 14°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those listed in the operational sections

of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the

human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

AD7190 Preliminary Technical Data

Rev.PrD 7/08 | Page 8

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SCLK

MCLK1

MCLK2

P1/REFIN2(+)

P0/REFIN2(-)

AINCOM

AIN1

AIN2

SYNC

DVDD

AVDD

DIN

DGND

AGND

BPDSW

REFIN1(-)

REFIN1(+)

AIN4

AIN3

DOUT/RDY

AD7190

TOP VIEW

(Not To

Scale)

Figure 5. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 MCLK1 When the master clock for the device is provided externally by a crystal, the crystal is connected between

MCLK1 and MCLK2.

2 MCLK2 Master Clock signal for the device. The AD7190 has an internal 4.92 MHz clock. This internal clock can be

made available on the MCLK2 pin.

The clock for the AD7190 can be provided externally also in the form of a crystal or external clock. A crystal

can be tied across the MCLK1 and MCLK2 pins. Alternatively, the MCLK2 pin can be driven with a CMOS-

compatible clock and MCLK1 left unconnected.

3 SCLK Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitt-

triggered input, making the interface suitable for opto-isolated applications. The serial clock can be

continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a

noncontinuous clock with the information being transmitted to or from the ADC in smaller batches of data.

4 CS Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC

in systems with more than one device on the serial bus or as a frame synchronization signal in

communicating with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode

with SCLK, DIN, and DOUT used to interface with the device.

5 P3 Digital Output Pin. This pin can function as a general purpose output bit referenced between AVDD and AGND.

6 P2 Digital Output Pin. This pin can function as a general purpose output bit referenced between AVDD and AGND.

7 P1/REFIN2(+) Digital Output Pin/Positive Reference Input.

This pin functions as a general purpose output bit referenced between AVDD and AGND.

When REFSEL = 1, this pin functions as REFIN2(+). An external reference can be applied between REFIN2(+)

and REFIN2(−). REFIN2(+) can lie anywhere between AVDD and GND + 1 V. The nominal reference voltage,

(REFIN2(+) − REFIN2(−)), is AVDD, but the part functions with a reference from 1 V to AVDD.

8 P0/REFIN2(-) Digital Output Pin/Negative Reference Input.

This pin functions as a general purpose output bit referenced between AVDD and AGND.

When REFSEL = 1, this pin functions as REFIN2(-). This reference input can lie anywhere between GND and

AVDD − 1 V.

9 NC No Connect. This pin should be tied to AGND.

10 AINCOM Analog inputs AIN1 to AIN4 are referenced to this input when configured for pseudo-differential operation.

11 AIN1 Analog Input. It can be configured as the positive input of a fully differential input pair when used with

AIN2 or as a pseudo-differential input when used with AINCOM.

12 AIN2 Analog Input. It can be configured as the negative input of a fully differential input pair when used with

AIN1 or as a pseudo-differential input when used with AINCOM.

13 AIN3 Analog Input. It can be configured as the positive input of a fully differential input pair when used with

Preliminary Technical Data AD7190

Rev.PrD 7/08 | Page 9

Pin No. Mnemonic Description

AIN4 or as a pseudo-differential input when used with AINCOM.

14 AIN4 Analog Input. It can be configured as the negative input of a fully differential input pair when used with

AIN3 or as a pseudo-differential input when used with AINCOM.

15 REFIN1(+) Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(−).

REFIN1(+) can lie anywhere between AVDD and GND + 1 V. The nominal reference voltage, (REFIN1(+) −

REFIN1(−)), is AVDD, but the part functions with a reference from 1 V to AVDD.

16 REFIN1(−) Negative Reference Input. This reference input can lie anywhere between GND and AVDD − 1 V.

17 BPDSW Low Side Power Switch to AGND.

18 AGND Analog Ground Reference Point.

19 DGND Digital Ground Reference Point.

20 AVDD Analog Supply Voltage, 3 V to 5.25 V. AVDD is independent of DVDD. Therefore DVDD can be operated at 3 V

with AVDD at 5 V or vice versa.

21 DVDD Digital Supply Voltage, 2.7 V to 5.25 V. DVDD is independent of AVDD. Therefore AVDD can be operated at 3 V

with DVDD at 5 V or vice versa.

22 SYNC Logic Input that allows for synchronization of the digital filters and analog modulators when using a

number of AD7190 devices. While SYNC is low, the nodes of the digital filter, the filter control logic and the

calibration control logic are reset and the analog modulator is also held in its reset state. SYNC does not

affect the digital interface but does reset RDY to a high state if it is low. SYNC has a pull- up resistor

internally to DVDD.

23 DOUT/RDY Serial Data Output/Data Ready Output. DOUT/RDYserves a dual purpose. It functions as a serial data

output pin to access the output shift register of the ADC. The output shift register can contain data from

any of the on-chip data or control registers. In addition, DOUT/RDYoperates as a data ready pin, going low

to indicate the completion of a conversion. If the data is not read after the conversion, the pin will go high

before the next update occurs.

The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is

available. With an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the

data/control word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the

SCLK rising edge.

24 DIN Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the

control registers within the ADC, the register selection bits of the communications register identifying the

appropriate register.

AD7190 Preliminary Technical Data

Rev.PrD 7/08 | Page 10

RMS NOISE AND RESOLUTION SPECIFICATIONS

The AD7190 can be operated with chop enabled or chop

disabled. With chop enabled, the settling time is two times the

conversion time. The offset is continuously removed by the

ADC leading to low offset and low offset drift. With chop

disabled, higher update rates can be achieved from the ADC.

The settling time is three times (sinc3) or four times (sinc4) the

selected update rate. With chop disabled, the offset is not

removed by the ADC. The offset and offset drift is comparable

between chop enabled and chop disabled for gains of 32 or

higher. For lower gains, however, periodic offset calibrations

may be required to remove offset due to drift.

SINC4 FILTER

The sinc4 filter optimizes the 50 Hz/60 Hz rejection. At the

higher update rates, it also gives better rms noise performance

compared with the sinc3 filter.

CHOP DISABLED

Table 5 shows the rms noise of the AD7190 for some of the

update rates and gain settings with chop disabled. The

numbers given are for the bipolar input range with the

external 5 V reference. These numbers are typical and are

generated with a differential input voltage of 0 V. Table 6

shows the effective resolution while the output peak-to-peak

(p-p) resolution is listed in brackets. It is important to note

that the effective resolution is calculated using the rms noise,

while the p-p resolution is calculated based on peak-to-peak

noise. The p-p resolution represents the resolution for which

there will be no code flicker. These numbers are typical and

are rounded to the nearest half-LSB.

Table 5. RMS Noise (nV) vs. Gain and Output Update Rate (continuous conversion mode) Using a 5 V Reference - Chop Disabled

Filter Word

(Decimal)

Update

Rate (Hz) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128

1023 4.7

174 24.71 12.65 10 8.3 7

640 7.5

196 30.28 14.52 12.28 10.37 9.5

480 10

246 38 19.33 14.14 12.00 10.26

96 50

558 87 44 35.66 27.78 25.3

16 300

1344 186 105 72.82 68.57 52.66

2 2400

4254 582 322 232 200 167

1 4800

13000 1776 900 678 497 376

Table 6. Typical Resolution (Bits) vs. Gain and Output Update Rate (continuous conversion mode) Using a 5 V Reference - Chop

Disabled

Filter Word

(Decimal)

Update

Rate (Hz) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128

1023 4.7 24 (23) 24 (23) 24 (23) 24 (22) 24 (21.5) 23.5 (21)

640 7.5

24 (23) 24 (22.5) 24 (22.5) 24 (22) 24 (21.5) 23 (20.5)

480 10

24 (22.5) 24 (22.5) 24 (22) 24 (21.5) 23.5 (21) 23 (20.5)

96 50

24 (21.5) 24 (21.5) 24 (21.5) 23 (20.5) 22.5 (20) 21.5 (19)

16 300

23(20.5) 22.5 (20) 22.5 (20) 22 (19.5) 21 (18.5) 20.5 (18)

2 2400

21 (18.5) 21 (18.5) 21 (18.5) 20.5 (18) 19.5 (17) 19 (16.5)

1 4800

19.5 (17) 19.5 (17) 19.5 (17) 19 (16.5) 18 (15.5) 17.5 (15)

Preliminary Technical Data AD7190

Rev.PrD 7/08 | Page 11

CHOP ENABLED

Table 7 shows the AD7190’s rms noise for some of the update

rates and gain settings. The numbers given are for the bipolar

input range with an external 5 V reference. These numbers are

typical and are generated with a differential input voltage of 0 V.

Table 8 shows the effective resolution, while the output peak-to-

peak (p-p) resolution is listed in brackets. It is important to note

that the effective resolution is calculated using the rms noise,

while the p-p resolution is calculated based on peak-to-peak

noise. The p-p resolution represents the resolution for which

there will be no code flicker. These numbers are typical and are

rounded to the nearest half-LSB.

Table 7. RMS Noise (nV) vs. Gain and Output Update Rate (continuous conversion mode) Using a 5 V Reference - Chop Enabled

Filter

Word

(Decimal)

Update

Rate (Hz) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128

1023 1.175

123 17.47 8.94 7.07 5.87 5

640 1.875

138 21.41 10.27 8.68 7.33 7.07

480 2.5 174 26.87 13.67 10 8.49 7.25

96 12.5

395 61.52 31.11 25.22 19.64 17.9

16 75 950 132 74.25 51.5 48.49 37.24

2 600

3008 412 228 164 141 118

1 1200

9192 1255 636 479 351 266

Table 8. Typical Resolution (Bits) vs. Gain and Output Update Rate (continuous conversion mode) Using a 5 V Reference - Chop

Enabled

Filter Word

(Decimal)

Update

Rate (Hz) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128

1023 1.175 24 (23.5) 24 (23.5) 24 (23.5) 24 (22.5) 24 (22) 24 (21.5)

640 1.875

24 (23.5) 24 (23) 24 (23) 24 (22.5) 24 (21.5) 23.5 (21)

480 2.5 24 (23) 24 (22.5) 24 (22.5) 24 (22) 24 (21.5) 23 (20.5)

96 12.5

24 (22) 24 (21.5) 24 (21.5) 23.5 (21) 23 (20.5) 22 (19.5)

16 75 23.5 (21) 23 (20.5) 23 (20.5) 22.5 (20) 21.5 (19) 21 (18.5)

2 600

21.5 (19) 21.5 (19) 21.5 (19) 21 (18.5) 20 (17.5) 19.5 (17)

1 1200

20 (17.5) 20 (17.5) 20 (17.5) 19.5 (17) 18.5 (16) 18 (15.5)

AD7190 Preliminary Technical Data

Rev.PrD 7/08 | Page 12

SINC3 FILTER

For a given update rate, the sinc3 filter has lower settling time

than the sinc3 filter. At low update rates, the rms noise is

comparable between the sinc3 filter and the sinc4 filter. So, the

user can optimize the settling time without compromising the

rms noise. At high update rates, the sinc4 filter is needed for

optimum performance of the AD7190.

CHOP DISABLED

Table 9 shows the rms noise of the AD7190 for some of the

update rates and gain settings with chop disabled. The

numbers given are for the bipolar input range with the

external 5 V reference. These numbers are typical and are

generated with a differential input voltage of 0 V. Table 10

shows the effective resolution while the output peak-to-peak

(p-p) resolution is listed in brackets. It is important to note

that the effective resolution is calculated using the rms noise,

while the p-p resolution is calculated based on peak-to-peak

noise. The p-p resolution represents the resolution for which

there will be no code flicker. These numbers are typical and

are rounded to the nearest half-LSB.

Table 9. RMS Noise (nV) vs. Gain and Output Update Rate (continuous conversion mode) Using a 5 V Reference - Chop Disabled

Filter Word

(Decimal)

Update

Rate (Hz) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128

1023 4.7 177 26.5 13.22 10.52 8.7 7.68

640 7.5 200 31 16.12 13.13 10.97 10.02

480 10 276 41 20.48 15.42 12.82 10.74

96 50 606 93 48 36.92 29.68 25.66

16 300

1400 205 112 84 73.21 60

2 2400

57510 7000 3570 1770 896 464

1 4800

438100 54690 27340 14220 6890 3480

Table 10. Typical Resolution (Bits) vs. Gain and Output Update Rate (continuous conversion mode) Using a 5 V Reference - Chop

Disabled

Filter Word

(Decimal)

Update

Rate (Hz) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128

1023 4.7 24 (23) 24 (23) 24 (23) 24 (22) 24 (21.5) 23.5 (21)

640 7.5

24 (23) 24 (22.5) 24 (22.5) 24 (22) 24 (21.5) 23 (20.5)

480 10

24 (22.5) 24 (22) 24 (22) 24 (21.5) 23.5 (21) 23 (20.5)

96 50

24 (21.5) 23.5 (21) 23.5 (21) 23 (20.5) 22.5 (20) 21.5 (19)

16 300

23(20.5) 22.5 (20) 22.5 (20) 22 (19.5) 21 (18.5) 20.5 (18)

2 2400

17.5 (15) 17.5 (15) 17.5 (15) 17.5 (15) 17.5 (15) 17.5 (15)

1 4800

14.5 (12) 14.5 (12) 14.5 (12) 14.5 (12) 14.5 (12) 14.5 (12)

Preliminary Technical Data AD7190

Rev.PrD 7/08 | Page 13

CHOP ENABLED

Table 11 shows the AD7190’s rms noise for some of the update

rates and gain settings. The numbers given are for the bipolar

input range with an external 5 V reference. These numbers are

typical and are generated with a differential input voltage of 0 V.

Table 12 shows the effective resolution, while the output peak-

to-peak (p-p) resolution is listed in brackets. It is important to

note that the effective resolution is calculated using the rms

noise, while the p-p resolution is calculated based on peak-to-

peak noise. The p-p resolution represents the resolution for

which there will be no code flicker. These numbers are typical

and are rounded to the nearest half-LSB.

Table 11. RMS Noise (nV) vs. Gain and Output Update Rate (continuous conversion mode) Using a 5 V Reference - Chop Enabled

Filter Word

(Decimal)

Update

Rate (Hz) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128

1023 1.56 125 18.74 9.35 7.44 6.15 5.43

640 2.5 173 21.92 11.4 9.28 7.76 7.09

480 3.33

195 29 14.48 10.90 9.06 7.59

96 16.6

429 66 34 26.11 20.99 18.14

16 100

990 145 79.2 59.4 51.77 44.62

2 800

40666 4950 2524 1252 634 328

1 1600

309783 38672 19332 10055 4872 2461

Table 12. Typical Resolution (Bits) vs. Gain and Output Update Rate (continuous conversion mode) Using a 5 V Reference - Chop

Enabled

Filter Word

(Decimal)

Update

Rate (Hz) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128

1023 1.56 24 (23.5) 24 (23.5) 24 (23.5) 24 (22.5) 24 (22) 24 (21.5)

640 2.5 24 (23.5) 24 (23) 24 (23) 24 (22.5) 24 (21.5) 23.5 (21)

480 3.33

24 (23) 24 (22.5) 24 (22.5) 24 (22) 24 (21.5) 23 (20.5)

96 16.6

24 (22) 24 (21.5) 24 (21.5) 23.5 (21) 23 (20.5) 22 (19.5)

16 100

23.5 (21) 23 (20.5) 23 (20.5) 22.5 (20) 21.5 (19) 21 (18.5)

2 800

18 (15.5) 18 (15.5) 18 (15.5) 18 (15.5) 18 (15.5) 18 (15.5)

1 1600

15 (12.5) 15 (12.5) 15 (12.5) 15 (12.5) 15 (12.5) 15 (12.5)

AD7190 Preliminary Technical Data

Rev.PrD 7/08 | Page 14

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Figure 10.

Figure 11.

Preliminary Technical Data AD7190

Rev.PrD 7/08 | Page 15

ON-CHIP REGISTERS

The ADC is controlled and configured via a number of on-chip

registers, which are described on the following pages. In the

following descriptions, set implies a Logic 1 state and cleared

implies a Logic 0 state, unless otherwise noted.

COMMUNICATIONS REGISTER

(RS2, RS1, RS0 = 0, 0, 0)

The communications register is an 8-bit write-only register. All

communications to the part must start with a write operation to

the communications register. The data written to the communi-

cations register determines whether the next operation is a read

or write operation, and to which register this operation takes

place. For read or write operations, once the subsequent read or

write operation to the selected register is complete, the interface

returns to where it expects a write operation to the communi-

cations register. This is the default state of the interface and, on

power-up or after a reset, the ADC is in this default state

waiting for a write operation to the communications register. In

situations where the interface sequence is lost, a write operation

of at least 40 serial clock cycles with DIN high returns the ADC

to this default state by resetting the entire part. Table 13 outlines

the bit designations for the communications register. CR0

through CR7 indicate the bit location, CR denoting the bits are

in the communications register. CR7 denotes the first bit of the

data stream. The number in brackets indicates the power-

on/reset default status of that bit.

CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0

WEN(0) R/W(0) RS2(0) RS1(0) RS0(0) CREAD(0) 0(0) 0(0)

Table 13. Communications Register Bit Designations

Bit Location Bit Name Description

CR7 WEN Write Enable Bit. A 0 must be written to this bit so that the write to the communications register actually

occurs. If a 1 is the first bit written, the part will not clock on to subsequent bits in the register. It will stay at

this bit location until a 0 is written to this bit. Once a 0 is written to the WEN bit, the next seven bits will be

loaded to the communications register.

CR6 R/W A 0 in this bit location indicates that the next operation will be a write to a specified register. A 1 in this

position indicates that the next operation will be a read from the designated register.

CR5 to CR3 RS2 to RS0 Register Address Bits. These address bits are used to select which registers of the ADC are being selected

during this serial interface communication. See Table 14.

CR2 CREAD Continuous Read of the Data Register. When this bit is set to 1 (and the data register is selected), the serial

interface is configured so that the data register can be continuously read, that is, the contents of the data

goes low to indicate that a conversion is complete. The communications register does not have to be

written to for subsequent data reads. To enable continuous read, the instruction 01011100 must be written

to the communications register. To disable continuous read, the instruction 01011000 must be written to

the communications register while the RDY pin is low. While continuous read is enabled, the ADC monitors

activity on the DIN line so that it can receive the instruction to disable continuous read. Additionally, a

reset will occur if 40 consecutive 1s are seen on DIN. Therefore, DIN should be held low until an instruction

is to be written to the device.

CR1 to CR0 0 These bits must be programmed to Logic 0 for correct operation.

Table 14. Register Selection

RS2 RS1 RS0 Register Register Size

0 0 0 Communications Register During a Write Operation 8-bit

0 0 0 Status Register During a Read Operation 8-bit

0 0 1 Mode Register 24-bit

0 1 0 Configuration Register 24-bit

0 1 1 Data Register / Data Register + Status Information 24-bit / 32-bit

1 0 0 ID Register 8-bit

1 0 1 GPOCON Register 8-bit

1 1 0 Offset Register 24-bit

1 1 1 Full-Scale Register 24-bit

AD7190 Preliminary Technical Data

Rev.PrD 7/08 | Page 16

STATUS REGISTER

(RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80)

The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register,

select the next operation to be a read, and load Bit RS2, Bit RS1, and Bit RS0 with 0. Table 15 outlines the bit designations for the status

register. SR0 through SR7 indicate the bit locations, SR denoting the bits are in the status register. SR7 denotes the first bit of the data

stream. The number in brackets indicates the power-on/reset default status of that bit.

SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0

RDY(1) ERR(0) NOREF(0) PARITY(0) CHD3(0) CHD2(0) CHD1(0) CHD0(0)

Table 15. Status Register Bit Designations

Bit Location Bit Name Description

SR7 RDY Ready Bit for ADC. Cleared when data is written to the ADC data register. The RDY bit is set automatically

after the ADC data register has been read or a period of time before the data register is updated with a

new conversion result to indicate to the user not to read the conversion data. It is also set when the part is

placed in power-down mode, idle mode or when SYNC is taken low.

The end of a conversion is also indicated by the DOUT/RDY pin. This pin can be used as an alternative to

the status register for monitoring the ADC for conversion data.

SR6 ERR ADC Error Bit. This bit is written to at the same time as the RDY bit. Set to indicate that the result written to

the ADC data register has been clamped to all 0s or all 1s. Error sources include overrange, underrange, or

the absence of a reference voltage. Cleared by a write operation to start a conversion.

SR5 NOREF No External Reference Bit. Set to indicate that the selected reference (REFIN1 or REFIN2) is at a voltage that

is below a specified threshold. When set, conversion results are clamped to all ones. Cleared to indicate

that a valid reference is applied to the selected reference pins. The NOXREF bit is enabled by setting the

REF_DET bit in the configuration register to 1. The ERR bit is also set if the voltage applied to the selected

reference input is invalid.

SR4 PARITY Parity Check of Data Register.

If the ENPAR bit is set, the PARITY bit is set if there is an odd number of 1s in the data register. It is cleared if

there is an even number of 1s in the data register. The DAT_STA bit should be set when the parity check is

used. When the DAT_STA bit is set, the contents of the status register are transmitted along with the data

for each data register read.

SR3 to SR0 CHD3 to

CHD0

These bits indicate which channel corresponds to the data register contents. They do not indicate which

channel is presently being converted but indicate which channel was selected when the conversion

contained in the data register was being generated.

MODE REGISTER

(RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x080060)

The mode register is a 24-bit register from which data can be read or to which data can be written. This register is used to select the

operating mode, the update rate, and the clock source. Table 16 outlines the bit designations for the mode register. MR0 through MR23

indicate the bit locations, MR denoting the bits are in the mode register. MR23 denotes the first bit of the data stream. The number in

brackets indicates the power-on/reset default status of that bit. Any write to the mode register resets the modulator and filter and sets the

RDY bit.

MR23 MR22 MR21 MR20 MR19 MR18 MR17 MR16

MD2(0) MD1(0) MD0(0) DAT_STA(0) CLK1(1) CLK0(0) 0 0

MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8

SINC3(0) 0 ENPAR(0) 0 SINGLE(0) REJ60(0) FS9(0) FS8(0)

MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0

FS7(0) FS6(1) FS5(1) FS4(0) FS3(0) FS2(0) FS1(0) FS0(0)

Table 16. Mode Register Bit Designations

Bit Location Bit Name Description

MR23 to MR21 MD2 to MD0 Mode Select Bits. These bits select the operational mode of the AD7190 (see Table 17).

MR20 DAT_STA Transmit status register contents after each data register read.

When DAT_STA is set, the contents of the status register are transmitted along with each data register

Preliminary Technical Data AD7190

Rev.PrD 7/08 | Page 17

Bit Location Bit Name Description

read. This function is useful when several channels are selected as the status register identifies the

channel to which the data register value corresponds.

MR19 to MR18 CLK1 to CLK0 These bits are used to select the clock source for the AD7190. Either the on-chip 4.92 MHz clock can

be used or an external clock can be used. The ability to use an external clock allows several AD7190

devices to be synchronized. Also, 50 Hz/60 Hz rejection is improved when an accurate external clock

drives the AD7190.

CLK1 CLK0 ADC Clock Source

0 0 External crystal used. The external crystal is connected from MCLK1 to MCLK2.

0 1 External clock used. The external clock is applied to the MCLK2 pin.

1 0 Internal 4.92 MHz clock. Pin MCLK2 is tri-stated.

1 1 Internal 4.92 MHz clock. The internal clock is available on MCLK2.

MR17 to MR16 0 These bits must be programmed with a Logic 0 for correct operation.

MR15 SINC3 Sinc3 Filter Select pin.

When this bit is cleared, the sinc4 filter is used (default value).

When this bit is set, a sinc3 filter is used.

The benefit of the sinc3 filter compared to the sinc4 filter is its lower settling time when chop is

disabled. For a given update rate fADC, the sinc3 filter has a settling time of fADC/3 while the sinc4 filter

has a settling time of fADC/4. The sinc4 filter, due to its deeper notches, gives better 50 Hz/60 Hz

rejection.

At low update rates, both filters give similar rms noise and similar no missing codes for a given update

rate. At higher update rates (FS values less than 5), the sinc4 filter gives better performance than the

sinc3 filter for rms noise and no missing codes.

MR14 0 This bit must be programmed with a Logic 0 for correct operation.

MR13 ENPAR Enable Parity bit.

When ENPAR is set, parity checking on the data register is enabled. The DAT_STA bit should be set

when the parity check is used. When the DAT_STA bit is set, the contents of the status register are

transmitted along with the data for each data register read.

MR12 0 This bit must be programmed with a Logic 0 for correct operation.

MR11 SINGLE Single Cycle Conversion Enable Bit.

When this bit is set, the AD7190 allows the complete settling time to perform each conversion. So, the

device functions as a zero-latency ADC.

MR10 REJ60 Enables a notch at 60 Hz when the update rate is equal to 50 Hz.

When REJ60 is set, a filter notch is placed at 60 Hz when the update rate selected is 50 Hz. This allows

simultaneous 50 Hz/60 Hz rejection.

MR9 to MR0 FS9 to FS0 Filter Update Rate Select Bits.

The 10 bits of data programmed into these bits determine the filter cut-off frequency, the position of

the first notch of the filter and the data rate for the part. In association with the gain selection, it also

determines the output noise (and hence the effective resolution) of the device. When chop is disabled

and continuous conversion mode is selected, the first notch of the filter occurs at a frequency

determined by the relationship:

filter first notch frequency = (fmod/64)/FS

where FS is the decimal equivalent of the code in bits FS0 to FS9 and is in the range 1 to 1023 and

fmod is the modulator frequency which is equal to MCLK/16. With the nominal MCLK of 4.92 MHz, this

results in a first notch frequency range from 4.69 Hz to 4.8 kHz.

Changing the filter notch frequency, as well as the selected gain, impacts resolution. Tables 5 through

8 show the effect of the filter notch frequency and gain on the effective resolution of the AD7190. The

output data rate (or effective conversion time) for the device is equal to the frequency selected for the

first notch of the filter. For example, if the first notch of the filter is selected at 50 Hz then a new word

is available at a 50 Hz rate or every 20 ms. If the first notch is at 1.2 kHz, a new word is available every

0.83 ms. The settling time of the filter to a full-scale step input change is worst case (N + 1)/(output

data rate) where N = 3 when the sinc3 filter is selected and N = 4 when the sinc4 filter is selected. For

example, with the first filter notch at 50 Hz, the settling time of the filter to a full-scale step input

change is 100 ms max when N = 4. This settling time can be reduced to N/(output data rate) by

synchronizing the step input change to a reset of the digital filter. In other words, if the step input

takes place with the SYNC input low, the settling time will be N/(output data rate) from when SYNC

returns high. If a change of channel takes place, the settling time is N/(output data rate) regardless of

the SYNC status as the part issues an internal reset command when requested to change channels.

The –3 dB frequency is determined by the programmed first notch frequency according to the

AD7190 Preliminary Technical Data

Rev.PrD 7/08 | Page 18

Bit Location Bit Name Description

relationship:

filter –3 dB frequency = 0.23 x filter first notch frequency.

When chop is enabled, the conversion time equals

Conversion rate = (fmod/64)/(NxFS)

where FS is the decimal equivalent of the code in bits FS0 to FS9 and is in the range 1 to 1023 and

fmod is the modulator frequency which is equal to MCLK/16. With the nominal MCLK of 4.92 MHz, this

results in a conversion rate from 4.69/N Hz to 4.8/N kHz where N is the order of the sinc filter. The first

notch in the frequency response is placed at conversion rate/2. The settling time is equal to 2 x

conversion time.

Table 17. Operating Modes

MD2 MD1 MD0 Mode

0 0 0 Continuous Conversion Mode (Default).

In continuous conversion mode, the ADC continuously performs conversions and places the result in the data

bit in the communications register to ‘1’ which enables continuous read. When continuous read is enabled, the

conversions are automatically placed on the DOUT line when SCLK pulses are applied. Alternatively, the user can

instruct the ADC to output each conversion by writing to the communications register.

After power-on, a reset or a re-configuration of the ADC, the complete settling time of the filter is required to

generate the first valid conversion. Subsequent conversions are available at the selected update rate which is

dependent on filter choice.

0 0 1 Single Conversion Mode.

When single conversion mode is selected, the ADC powers up and performs a single conversion on the selected

channel. The oscillator requires 1 ms to power up and settle. The ADC then performs the conversion which requires

the complete settling time of the filter. The conversion result is placed in the data register, RDY goes low, and the

ADC returns to power-down mode. The conversion remains in the data register and RDY remains active (low) until

the data is read or another conversion is performed.

0 1 0 Idle Mode.

In idle mode, the ADC filter and modulator are held in a reset state although the modulator clocks are still provided.

0 1 1 Power-Down Mode.

In power-down mode, all the AD7190 circuitry, except the power switch, is powered down. The power switch

remains active as the user may need to power up the sensor prior to powering up the AD7190 for settling reasons.

The external crystal, if present, is left active.

1 0 0 Internal Zero-Scale Calibration.

An internal short is automatically connected to the input. RDY goes high when the calibration is initiated and

returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured

offset coefficient is placed in the offset register of the selected channel.

1 0 1 Internal Full-Scale Calibration.

A full-scale input voltage is automatically connected to the input for this calibration.

RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed

in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the

selected channel.

A full-scale calibration is required each time the gain of a channel is changed to minimize the full-scale error.

1 1 0 System Zero-Scale Calibration.

User should connect the system zero-scale input to the channel input pins as selected by the CH7 to CH0 bits. RDY

goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in

idle mode following a calibration. The measured offset coefficient is placed in the offset register of the selected

channel.

1 1 1 System Full-Scale Calibration.

User should connect the system full-scale input to the channel input pins as selected by the CH7–CH0 bits.

RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed

in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the

selected channel.

A full-scale calibration is required each time the gain of a channel is changed.

Preliminary Technical Data AD7190

Rev.PrD 7/08 | Page 19

CONFIGURATION REGISTER

(RS2, RS1, RS0 = 0, 1, 0; Power-On/Reset = 0x000117)

The configuration register is a 24-bit register from which data can be read or to which data can be written. This register is used to

configure the ADC for unipolar or bipolar mode, enable or disable the buffer, enable or disable the burnout currents, select the gain,

and select the analog input channel.

Table 18 outlines the bit designations for the filter register. CON0 through CON23 indicate the bit locations. CON denotes that the bits

are in the configuration register. CON23 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset

default status of that bit.

CON23 CON22 CON21 CON20 CON19 CON18 CON17 CON16

CHOP(0) 0(0) 0(0) REFSEL(0) 0(0) 0(0) 0(0) (0)

CON15 CON14 CON13 CON12 CON11 CON10 CON9 CON8

CH7(0) CH6(0) CH5(0) CH4(0) CH3(0) CH2(0) CH1(0) CH0(1)

CON7 CON6 CON5 CON4 CON3 CON2 CON1 CON0

BURN(0) REFDET(0) 0(0) BUF(1) U/B (0) GN2(1) GN1(1) GN0(1)

Table 18. Configuration Register Bit Designations

Bit

Location Bit Name Description

CON23 CHOP Chop Enable Bit.

When CHOP is cleared, chop is disabled.

When CHOP is set, chop is disabled.

When chop is enabled, the offset and offset drift is continuously removed by the ADC. However, it

increases the conversion time and settling time of the ADC. For example, when FS = 96 decimal and the

sinc4 filter is selected, the conversion time with chop enabled equals 80 ms and the settling time equals

160 ms. With chop disabled, higher conversion rates are allowed. For an SF word of 96 decimal and the

sinc4 filter selected, the conversion time is 20 ms and the settling time is 80 ms. However, at low gains,

periodic calibrations may be required to remove the offset and offset drift.

CON22,

CON21

0 These bits must be programmed with a Logic 0 for correct operation.

CON20 REFSEL Reference Select Bits. The reference source for the ADC is selected using these bits.

REFSEL Reference Voltage

0 External reference applied between REFIN1(+) and REFIN1(−)

1 External reference applied between the P1 and P0 pins.

CON19 to

CON16

0 These bits must be programmed with a Logic 0 for correct operation.

CON15 to

CON8

CH7 to CH0 Channel Select Bits.

These bits are used to select which channels are enabled on the AD7190. See Table 19. Several channels

can be selected and the AD7190 will automatically sequence between them. The conversion on each

channel will require the complete settling time.

CON7 BURN When this bit is set to 1 by the user, the 500 nA current sources in the signal path are enabled. When

BURN = 0, the burnout currents are disabled. The burnout currents can be enabled only when the buffer

is active.

CON6 REFDET Enables the Reference Detect Function.

When set, the NOXREF bit in the status register indicates when the external reference being used by the

ADC is open circuit or less than 0.5 V.

CON5 0 This bit must be programmed with a Logic 0 for correct operation.

CON4 BUF Configures the ADC for buffered or unbuffered mode of operation. If cleared, the ADC operates in

unbuffered mode, lowering the power consumption of the device. If set, the ADC operates in buffered

mode, allowing the user to place source impedances on the front end without contributing gain errors

to the system.

With the buffer disabled, the voltage on the analog input pins can be from 50 mV below GND to 50 mV

above AVDD. When the buffer is enabled, it requires some headroom so the voltage on any input pin must

be limited to 200 mV within the power supply rails.

AD7190 Preliminary Technical Data

Rev.PrD 7/08 | Page 20

Bit

Location Bit Name Description

CON3 U/B Polarity Select bit.

When this bit is set, unipolar operation is selected.

When this but is cleared, bipolar operation is selected.

CON2 to

CON0

G2 to G0 Gain Select Bits.

Written by the user to select the ADC input range as follows:

G2 G1 G0 Gain ADC Input Range (5 V Reference)

0 0 0 1 5 V

0 0 1 Reserved

0 1 0 Reserved

0 1 1 8 625 mV

1 0 0 16 312.5 mV

1 0 1 32 156.2 mV

1 1 0 64 78.125 mV

1 1 1 128 39.06 mV

Table 19. Channel Selection

CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 Channel CHD[3:0] Calibration Pair

X X X X X X X 1 AIN1 − AIN2 0000 0

X X X X X X 1 X

AIN3 − AIN4 0001 1

X X X X X 1 X X Temp Sensor 0010 None

X X X X 1 X X X AIN2 − AIN2 0011 0

X X X 1 X X X X AIN1 − AINCOM 0100 0

X X 1 X X X X X AIN2 − AINCOM 0101 1

X 1 X X X X X X AIN3 − AINCOM 0110 2

1 X X X X X X X AIN4 − AINCOM 0111 3

DATA REGISTER

(RS2, RS1, RS0 = 0, 1, 1; Power-On/Reset = 0x000000)

The conversion result from the ADC is stored in this data register. This is a read-only register. On completion of a read operation from

this register, the RDY bit/pin is set. The AD7190 can be configured for 24-bit transfers or 32-bit transfers. When 24-bit transfers are

selected, the 24-bit data conversion is transmitted. When 32-bit transfers are selected, the 24-bit conversion is followed by the contents of

the status register. When several channels are enabled, the ADC will automatically step between channels. So, 32-bit transmissions are

required so that the user can identify the channel from which the conversions originated.

GPOCON REGISTER

(RS2, RS1, RS0 = 1, 0, 1; Power-On/Reset = 0x00)

The GPOCON register is an 8-bit register from which data can be read or to which data can be written. This register is used to enable the

general purpose digital outputs.

Table 20 outlines the bit designations for the GPOCON register. GP0 through GP7 indicate the bit locations. GP denotes that the bits are

in the GPOCON register. GP7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status

of that bit.

GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0

0(0) BPDSW(0) GP32EN(0) GP10EN(0) P3DAT(0) P2DAT(0) P1DAT(0) P0DAT(0)

Preliminary Technical Data AD7190

Rev.PrD 7/08 | Page 21 PR07640-0-7/08(PrD)

Table 20. Register Bit Designations

Bit Location Bit Name Description

GP7 0 This bit must be programmed with a Logic 0 for correct operation.

GP 6 BPDSW Power Switch Control Bit. Set by user to close the power switch BPDSW to AGND. The power switch

can sink up to 30 mA. Cleared by user to open the power switch. When the ADC is placed in power-

down mode, the power switch remains active.

GP5 GP32EN Digital Outputs P3 and P2 Enable.

When GP32EN is set, the digital outputs P3 and P2 are active. When GP32EN is cleared, the pins P3

and P2 are tri-stated and bits P3DAT and P2DAT are ignored.

GP4 GP10EN Digital Outputs P1 and P0 Enable.

When GP10EN is set, the digital outputs P1 and P0 are active. When GP10EN is cleared, the P1 and

P0 outputs are tri-stated and bits P1DAT and P0DAT are ignored. The pins P1 and P0 can be used as a

reference input REFIN2 when bit REFSEL in the configuration register is set to 1.

GP3 P3DAT Digital Output P3. When GP32EN is set, the P3DAT bit sets the value of the general purpose output

pin P3. When P3DAT is high, the output P3 is high. When P3DAT is low, the output P3 is low.

GP2 P2DAT Digital Output P2. When GP32EN is set, the P2DAT bit sets the value of the general purpose output

pin P2. When P2DAT is high, the output P2 is high. When P2DAT is low, the output P2 is low.

GP1 P1DAT Digital Output P1. When GP10EN is set, the P1DAT bit sets the value of the general purpose output

pin P1. When P1DAT is high, the output P1 is high. When P1DAT is low, the output P1 is low.

GP0 P0DAT Digital Output P0. When GP10EN is set, the P0DAT bit sets the value of the general purpose output

pin P0. When P0DAT is high, the output P0 is high. When P0DAT is low, the output P0 is low.