High Performance Configurable 8-bit Microcontroller ver 3.01 OVERVIEW CPU FEATURES DR80390 is a high performance, area optimized soft core of a single-chip 8-bit embedded controller dedicated for operation with fast (typically on-chip) and slow (off-chip) memories. The core has been designed with a special concern about low power consumption. Additionally an advanced power management unit makes DR80390 core perfect for portable equipment where low power consumption is mandatory. DR80390 soft core is 100% binarycompatible with the industry standard 80C390 8-bit microcontroller. There are two configurations of DR80390: Harward where external data and program buses are separated, and von Neumann with common program and external data bus. DR80390 has RISC architecture 6.7 times faster compared to standard architecture and executes 65-200 million instructions per second. This performance can also be exploited to great advantage in low power applications where the core can be clocked up to seven times more slowly than the original implementation for no performance penalty. DR80390 is delivered with fully automated testbench and complete set of tests allowing easy package validation at each stage of SoC design flow. 100% software compatible with industry standard 80390 All trademarks mentioned in this document are trademarks of their respective owners. LARGE mode - 8051 instruction set FLAT mode - 80390 instruction set RISC architecture enables to execute instructions 6.7 times faster compared to standard 8051 12 times faster multiplication 9.6 times faster division Up to 256 bytes of internal (on-chip) Data Memory Up to 16M bytes of contiguous Program Memory Up to 16M bytes of external (off-chip) Data Memory User programmable Program Memory Wait States solution for wide range of memories speed User programmable External Data Memory Wait States solution for wide range of memories speed De-multiplexed Address/Data bus to allow easy connection to memory Interface for additional Special Function Registers http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. Fully synthesizable, static synchronous design with positive edge clocking and no internal tri-states Scan test ready 1.3 GHz virtual clock frequency in a 0.35u technological process Read/write of single line and 8-bit group Two 16-bit timer/counters Timers clocked by internal source Auto reload 8-bit timers Externally gated event counters Full-duplex serial port PERIPHERALS DoCDTM debug unit Processor execution control Synchronous mode, fixed baud rate 8-bit asynchronous mode, fixed baud rate 9-bit asynchronous mode, fixed baud rate 9-bit asynchronous mode, variable baud rate Run Halt CONFIGURATION Step into instruction Skip instruction Read-write all processor contents Program Counter (PC) Program Memory Internal (direct) Data Memory Special Function Registers (SFRs) External Data Memory The following parameters of the DR80390 core can be easy adjusted to requirements of dedicated application and technology. Configuration of the core can be prepared by effortless changing appropriate constants in package file. There is no need to change any parts of the code. * Memory style - Harward - von Neumann * Program Memory type - synchronous - asynchronous Hardware execution breakpoints Program Memory Internal (direct) Data Memory Special Function Registers (SFRs) External Data Memory Hardware breakpoints activated at a certain Program address (PC) * Program Memory waitstates * Program Memory writes - used - unused * Internal Data Memory type - synchronous - asynchronous * External Data Memory size - 64 kB - 16 MB Address by any write into memory Address by any read from memory Address by write into memory a required data Address by read from memory a required data Three wire communication interface Power Management Unit Power management mode * External Data Memory wait-states Interrupt Controller 2 priority levels 2 external interrupt sources 3 interrupt sources from peripherals Four 8-bit I/O Ports - used (0-7) - unused subroutines location * Interrupts - * Power Management Mode - used - unused * Stop mode - used - unused * DoCDa debug unit - used - unused Switchback feature Stop mode - used (0-7) - unused Besides mentioned above parameters all available peripherals and external interrupts can be excluded from the core by changing appropriate constants in package file. Bit addressable data direction for each line All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. SYMBOL DELIVERABLES Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist VHDL & VERILOG test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes HDL core specification Datasheet Synthesis scripts Example application Technical support IP Core implementation support 3 months maintenance Delivery the IP Core updates, minor and major versions changes Delivery the documentation updates Phone & email support clk reset ramdatai(7:0) ramdatao(7:0) ramaddr(7:0) ramoe ramwe sfrdatao(7:0) sfraddr(7:0) sfroe sfrwe prgdatao(7:0) prgdataz prgaddr(23:0) prgrd prgwr sfrdatai(7:0) prgdatai(7:0) xramdatai(7:0) int0 int1 xramdatao(7:0) xramdataz xramaddr(23:0) xramrd xramwr docddatai LICENSING Comprehensible and clearly defined licensing methods without royalty fees make using of IP Core easy and simply. Single Design license allows use IP Core in single FPGA bitstream and ASIC implementation. Unlimited Designs, One Year licenses allow use IP Core in unlimited number of FPGA bitstreams and ASIC implementations. port0i(7:0) port1i(7:0) port2i(7:0) port3i(7:0) docddatao docdclk stop pmm port0o(7:0) port1o(7:0) port2o(7:0) port3o(7:0) t0 gate0 t1 gate1 rxd0i rxd0o txd0 In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited. There is no time restriction except One Year license where time of use is limited to 12 months. Single Design license for VHDL, Verilog source code called HDL Source Encrypted, or plain text EDIF called Netlist One Year license for Encrypted Netlist only Unlimited Designs license for HDL Source Netlist Upgrade from HDL Source to Netlist Single Design to Unlimited Designs All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. BLOCK DIAGRAM ramdatao[7:0] output Data bus for Internal Data Memory ramaddr[7:0] output Internal Data Memory address bus clk reset ramoe output Internal Data Memory output enable ramwe output Internal Data Memory write enable Opcode Decoder prgdatai(7:0) prgdatao(7:0) prgdataz prgaddr(23:0) prgrd prgwr Program Memory Interface xramdatai(7:0) xramdatao(7:0) xramdataz xramaddr(23:0) xramrd xramwr ramdatai(7:0) ramdatao(7:0) ramaddr(7:0) ramoe ramwe ALU Control Unit External Memory Interface Interrupt Controller Internal Data Memory Interface I/O Ports sfrdatai(7:0) sfrdatao(7:0) sfraddr(7:0) sfroe sfrwe User SFR Interface docddatai docddatao docdclk DoCDTM Debug Unit rxd0o rxd0i txd0 Power Management Unit Timers 0 & 1 UART 0 int0 int1 port0i(7:0) port1i(7:0) port2i(7:0) port3i(7:0) port0o(7:0) port1o(7:0) port2o(7:0) port3o(7:0) stop pmm t0 gate0 t1 gate1 PINS DESCRIPTION PIN TYPE DESCRIPTION clk input Global clock reset input Global synchronous reset ramdatai[7:0] input Data bus from Internal Data Memory sfrdatai[7:0] input Data bus from user SFRs prgdatai[7:0] input Input data bus from Program Memory xramdatai[7:0] input Data bus from External Data Memory int0 input External interrupt 0 line int1 input External interrupt 1 line docddatai input DoCDTM data input port0i[7:0] input Port 0 input port1i[7:0] input Port 1 input port2i[7:0] input Port 2 input port3i[7:0] input Port 3 input t0 input Timer 0 clock line gate0 input Timer 0 clock line gate control t1 input Timer 1 clock line gate1 input Timer 1 clock line gate control rxd0i input Serial receiver input 0 All trademarks mentioned in this document are trademarks of their respective owners. sfrdatao[7:0] output Data bus for user SFRs sfraddr[7:0] output User SFRs address bus sfroe output User SFRs output enable sfrwe output User SFRs write enable prgaddr[23:0] output Program Memory address bus prgdatao[7:0] output Output data bus for Program Memory prgdataz output PRGDATA tri-state buffers control line prgrd output Program Memory read prgwr output Program Memory write xramdatao[7:0] output Data bus for External Data Memory xramdataz output XDATA tri-state buffers control line xramaddr[23:0] output External Data Memory address bus xramrd output External Data Memory read xramwr output External Data Memory write docddatao output DoCDTM data output docdclk output DoCDTM clock line pmm output Power management mode indicator stop output Stop mode indicator port0o[7:0] output Port 0 output port1o[7:0] output Port 1 output port2o[7:0] output Port 2 output port3o[7:0] output Port 3 output rxd0o output Serial receiver output 0 txd0 output Serial transmitter line 0 rxd1o output Serial receiver output 1 txd1 output Serial transmitter line 1 UNITS SUMMARY ALU - Arithmetic Logic Unit performs the arithmetic and logic operations during execution of an instruction. It contains accumulator (ACC), Program Status Word (PSW), (B) registers and related logic such as arithmetic unit, logic unit, multiplier and divider. Opcode Decoder - Performs an instruction opcode decoding and the control functions for all other blocks. Control Unit - Performs the core synchronization and data flow control. This module is directly connected to Opcode Decoder and manages execution of all microcontroller tasks. Program Memory Interface - Contains Program Counter (PC) and related logic. It performs the instructions code fetching. Program Memory can be also written. This feature allows usage of a small boot loader loading new http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. program into RAM, EPROM or FLASH EEPROM storage via UART, SPI, I2C or DoCDTM module. Program fetch cycle length can be programmed by user. This feature is called Program Memory Wait States, and allows core to work with different speed program memories. External Memory Interface - Contains memory access related registers such as Data Pointer High (DPH0), Data Pointer Low (DPL0), Data Page Pointer (DPP0), MOVX @Ri address register (MXAX) and STRETCH registers. It performs the memory addressing and data transfers. Allows applications software to access up to 16 MB of external data memory. The DPP0 register is used for segments swapping. STRETCH register allows flexible timing management while accessing different speed system devices by programming XRAMWR and XRAMRD pulse width between 1 - 8 clock periods. Internal Data Memory Interface - Internal Data Memory interface controls access into the internal 256 bytes memory. It contains 8-bit Stack Pointer (SP) register and related logic. User SFRs Interface - Special Function Registers interface controls access to the special registers. It contains standard and used defined registers and related logic. User defined external devices can be quickly accessed (read, written, modified) using all direct addressing mode instructions. Interrupt Controller - Interrupt control module is responsible for the interrupt manage system for the external and internal interrupt sources. It contains interrupt related registers such as Interrupt Enable (IE), Interrupt Priority (IP) and (TCON) registers. I/O Ports - Block contains 8051's general purpose I/O ports. Each of port's pin can be read/write as a single bit or as an 8-bit bus called P0, P1, P2, P3. Power Management Unit - Block contains advanced power saving mechanisms with switchback feature, allowing external clock control logic to stop clocking (Stop mode) or run core in lower clock frequency (Power Management Mode) to significantly reduce power consumption. Switchback feature allows UARTs, and interrupts to be processed in full speed mode if enabled. It is very desired when microcontroller is planned to use in portable and power critical applications. All trademarks mentioned in this document are trademarks of their respective owners. DoCDTM Debug Unit - it's a real-time hardware debugger provides debugging capability of a whole SoC system. In contrast to other onchip debuggers DoCDTM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller including all registers, internal, external, program memories, all SFRs including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware breakpoint is executed if any write/read occurred at particular address with certain data pattern or without pattern. The DoCDTM system includes three-wire interface and complete set of tools to communicate and work with core in real time debugging. It is built as scalable unit and some features can be turned off to save silicon and reduce power consumption. A special care on power consumption has been taken, and when debugger is not used it is automatically switched in power save mode. Finally whole debugger is turned off when debug option is no longer used. Timers - System timers module. Contains two 16 bits configurable timers: Timer 0 (TH0, TL0), Timer 1 (TH1, TL1) and Timers Mode (TMOD) registers. In the timer mode, timer registers are incremented every 12 CLK periods when appropriate timer is enabled. In the counter mode the timer registers are incremented every falling transition on their corresponding input pins (T0, T1), if gates are opened (GATE0, GATE1). T0, T1 input pins are sampled every CLK period. It can be used as clock source for UARTs. UART0 - Universal Asynchronous Receiver & Transmitter module is full duplex, meaning it can transmit and receive concurrently. Includes Serial Configuration register (SCON), serial receiver and transmitter buffer (SBUF) registers. Its receiver is double-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register. Writing to SBUF0 loads the transmit register, and reading SBUF0 reads a physically separate receive register. Works in 3 asynchronous and 1 synchronous modes. UART0 can be synchronized by Timer 1. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. PERFORMANCE The following tables give a survey about the Core area and performance in Programmable Logic Devices after Place & Route (CPU features and peripherals have been included): Device ORCA 4E Speed grade -3 Fmax 44 MHz Core performance in LATTICE(R) devices For a user the most important is application speed improvement. The most commonly used arithmetic functions and their improvements are shown in table below. An improvement was computed as {80C51 clock periods} divided by {DR80390 clock periods} required to execute an identical function. More details are available in core documentation. Function 8-bit addition (immediate data) 8-bit addition (direct addressing) 8-bit addition (indirect addressing) 8-bit addition (register addressing) 8-bit subtraction (immediate data) 8-bit subtraction (direct addressing) 8-bit subtraction (indirect addressing) 8-bit subtraction (register addressing) 8-bit multiplication 8-bit division 16-bit addition 16-bit subtraction 16-bit multiplication 32-bit addition 32-bit subtraction 32-bit multiplication Average speed improvement: Improvement 7,20 6,00 6,00 7,20 7,20 6,00 6,00 7,20 10,67 9,60 7,20 7,64 9,75 7,20 7,43 9,04 7,58 Dhrystone Benchmark Version 2.1 was used to measure Core performance. The following table gives a survey about the DR80390 performance in terms of Dhrystone/sec and VAX MIPS rating. Device Target 80C51 80C310 DR80390 ORCA 4E Clock frequency 12 MHz 33 MHz 40 MHz Dhry/sec (VAX MIPS) 268 (0.153) 1550 (0.882) 6420 (3.654) Core performance in terms of Dhrystones 8000 6420 6000 4000 1550 2000 268 0 80C51 (12MHz) 80C310 (33MHz) DR80390 (40MHz) Area utilized by the each unit of DR80390 core in vendor specific technologies is summarized in table below. Component CPU* Interrupt Controller Power Management Unit I/O ports Timers UART0 Total area Area [LC/PFU] [FFs] 1590 150 10 100 150 200 2200/357 250 40 5 35 50 60 430 *CPU - consisted of ALU, Opcode Decoder, Control Unit, Program & Internal & External Memory Interfaces, User SFRs Interface Core components area utilization All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. - - - - - - Fixed Point Coprocessor Floating Point Coprocessor 4 4 SPI 1 2 2 I\O Ports 2 3 Master I C Bus Controller 2 Slave I C Bus Controller UART 1 1 2 Watchdog Timer/Counters 2 2 2 Compare/Capture Data Pointers 2 5 15 Program Memory Wait States Interrupt levels DR80390CPU 6.7 16M 256 256 16M DR80390 6.7 16M 256 256 16M DR80390XP 6.7 16M 64k 256 16M Interrupt sources Internal Data Memory space External Data Memory space External Data Memory Wait States Power Management Unit Interface for additional SFRs Stack space size Program Memory space Design Architecture speed grade The main features of each DR80390 family member have been summarized in table below. It gives a briefly member characterization helping user to select the most suitable IP Core for its application. User can specify its own peripheral set (including listed below and the others) and requests the core modifications. - - DR80390 family of High Performance Microcontroller Cores - - - - - - DR8051 family of High Performance Microcontroller Cores All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. Fixed Point Coprocessor Floating Point Coprocessor 4 4 SPI 1 2 Master I C Bus Controller 2 Slave I C Bus Controller I\O Ports 2 3 2 UART 1 1 2 Watchdog Timer/Counters 2 2 2 Compare/Capture Data Pointers 2 5 15 Program Memory Wait States Interrupt levels Internal Data Memory space External Data Memory space External Data Memory Wait States Power Management Unit Interface for additional SFRs Stack space size 6.7 64k 256 256 16M 6.7 64k 256 256 16M 6.7 64k 256 256 16M Interrupt sources DR8051CPU DR8051 DR8051XP Program Memory space Design Architecture speed grade The main features of each DR8051 family member have been summarized in table below. It gives a briefly member characterization helping user to select the most suitable IP Core for its application. User can specify its own peripheral set (including listed below and the others) and requests the core modifications. - - CONTACTS For any modification or special request please contact to Digital Core Design or local distributors. Headquarters: Wroclawska 94 41-902 Bytom, POLAND e-mail: iinnffoo@ @ddccdd..ppll tel. : +48 32 282 82 66 fax : +48 32 282 74 37 Field Office: Texas Research Park 14815 Omicron Dr. suite 100 San Antonio, TX 78245,USA e-mail: iinnffooU USS@ @ddccdd..ppll tel. : +1 210 422 8268 fax : +1 210 679 7511 Distributors: MTC - Micro Tech Components GmbH AM Reitweg 15 89407 Dillingen, GERMANY MTTC Ciinnffoo@ @m mttcc..ddee e-mail : M tel. : +49 9071 7945-0 fax : +49 9071 7945-20 Territory: Germany, Austria, Switzerland All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.