19-3920; Rev 0; 12/05 MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits The MAX12527/MAX12528/MAX12529/MAX12557/ MAX12558/MAX12559 evaluation kits (EV kits) are fully assembled and tested circuit boards that contain all the components necessary to evaluate the performance of this family of 12-bit and 14-bit, dual analog-to-digital converters (ADCs). These ADCs accept differential analog input signals. The EV kits generate these signals from user-provided single-ended input sources. The digital outputs produced by the ADCs can be easily sampled with a user-provided high-speed logic analyzer or data-acquisition system. The EV kits operate from 2.0V and 3.3V power supplies. Part Selection Table Features Low-Voltage and Low-Power Operation On-Board Clock-Shaping Circuitry Option On-Board Output Drivers Fully Assembled and Tested Ordering Information PART TEMP RANGE* IC PACKAGE MAX12527EVKIT 0C to +70C 68 TQFN-EP** MAX12528EVKIT 0C to +70C 68 TQFN-EP** SAMPLING RATE (Msps) RESOLUTION (Bits) MAX12529EVKIT 0C to +70C 68 TQFN-EP** MAX12557EVKIT 0C to +70C 68 TQFN-EP** MAX12559ETK 96 14 MAX12558EVKIT 0C to +70C 68 TQFN-EP** MAX12558ETK 80 14 MAX12559EVKIT 0C to +70C 68 TQFN-EP** MAX12557ETK 65 14 MAX12529ETK 96 12 MAX12528ETK 80 12 MAX12527ETK 65 12 PART *EV kit PC board temperature range only. **EP = Exposed paddle. Component List DESIGNATION QTY C1-C4 0 DESCRIPTION Not installed (0603) DESIGNATION QTY DESCRIPTION C33-C38, C47, C53 8 220F 20%, 6.3V tantalum capacitors (C case) AVX TPSC227M006R0250 C39, C40, C41, C55, C61, C66 6 10F 20%, 6.3V X5R ceramic capacitors (0805) TDK C2012X5R0J106M C5, C6, C11, C13, C14, C16, C17, C28-C32, C45, C46, C57-C60, C62-C65 22 C7-C10 4 5.6pF 0.5pF, 50V C0G ceramic capacitors (0402) TDK C1005C0G1H5R6D C42, C43, C44, C56 4 1.0F 20%, 10V X5R ceramic capacitors (0603) TDK C1608X5R1A105M C12, C21-C27 8 4.7F 20%, 6.3V X5R ceramic capacitors (0603) TDK C1608X5R0J475M C51, C52 2 0.01F 5%, 25V C0G ceramic capacitors (0603) TDK C1608C0G1E103J C15, C18 C19, C20 4 0.1F 20%, 6.3V X5R ceramic capacitors (0201) TDK C0603X5R0J104M C67 1 1.0F 20%, 6.3V X5R ceramic capacitor (0402) TDK C1005X5R0J105M 0.1F 20%, 10V X5R ceramic capacitors (0402) TDK C1005X5R1A104M ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 Evaluate: MAX12527/28/29/57/58/59 General Description MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits Evaluate: MAX12527/28/29/57/58/59 Component List (continued) DESIGNATION QTY DESCRIPTION J1, J2, J7 3 Dual Schottky diode (SOT23) Central Semiconductor CMPD6263S Vishay BAS70-04 Diodes Inc. BAS70-04 SMA PC mount connectors J3, J4, J8 3 2-pin headers J5, J6 2 Dual-row, 40-pin headers (2 x 20) JU1-JU6 6 3-pin headers 4 EMI filters Murata NFM41PC204F1H3B D1 L1-L4 1 R1-R8, R13-R16, R21-R32, R37, R40-R45 R9-R12 0 Not installed (0603) 4 75 0.5% resistors (0603) R17-R20 4 110 0.5% resistors (0603) R33-R36 0 Not installed (0402) R38, R39 2 49.9 1% resistors (0603) R46, R47 2 100 1% resistors (0603) R48 1 10k potentiometer R49-R52 4 24.9 0.5% resistors (0402) DESIGNATION QTY DESCRIPTION RA1-RA8 8 220 5% resistor arrays Panasonic EXB-2HV-221J T1-T4 4 1:1 RF transformers Mini-Circuits ADT1-1WT T5 1 1:2 RF transformer Coilcraft TTWB-2-B TP1-TP6 6 Test points U1 1 See the EV Kit Specific Component List U2, U3 2 Low-voltage 16-bit registers (48-pin TSSOP) Pericom PI74ALVTC16374 or Texas Instruments SN74AVC16374DGGR U4 1 TinyLogic ULP-A buffer (SC70-5) Fairchild NC7SV125P5 U5 1 TinyLogic ULP-A inverter (SC70-6) Fairchild NC7WV04P6 None 6 Shunts None 1 MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 PC board EV Kit Specific Component List EV KIT PART NUMBER REFERENCE DESIGNATOR DESCRIPTION MAX12527EVKIT Maxim MAX12527ETK (68-pin thin QFN, 10mm x 10mm x 0.8mm) MAX12528EVKIT Maxim MAX12528ETK (68-pin thin QFN, 10mm x 10mm x 0.8mm) MAX12529EVKIT MAX12557EVKIT U1 Maxim MAX12529ETK (68-pin thin QFN, 10mm x 10mm x 0.8mm) Maxim MAX12557ETK (68-pin thin QFN, 10mm x 10mm x 0.8mm) MAX12558EVKIT Maxim MAX12558ETK (68-pin thin QFN, 10mm x 10mm x 0.8mm) MAX12559EVKIT Maxim MAX12559ETK (68-pin thin QFN, 10mm x 10mm x 0.8mm) 2 _______________________________________________________________________________________ MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits SUPPLIER PHONE FAX WEBSITE AVX 843-946-0238 843-626-3123 www.avxcorp.com Central Semiconductor 631-435-1110 631-435-1824 www.centralsemi.com Coilcraft 847-639-6400 847-639-1469 www.coilcraft.com Diodes Inc. 805-446-4800 805-446-4850 www.diodes.com Fairchild 888-522-5372 -- Murata 770-436-1300 770-436-3030 www.murata.com Panasonic 714-373-7366 714-737-7323 www.panasonic.com Pericom 800-435-2336 408-435-1100 www.pericom.com TDK 847-803-6100 847-390-4405 www.component.tdk.com Texas Instruments 972-644-5580 214-480-7800 www.ti.com www.fairchildsemi.com Note: Indicate that you are using the MAX12527, MAX12528, MAX12529, MAX12557, MAX12558, and MAX12559 when contacting these component suppliers. Quick Start Recommended Equipment * DC power supplies: Analog (VDD) 3.3V, 500mA Digital (OVDD) 2.0V, 50mA Buffers (VLOGIC) 2.0V, 100mA * Signal generator with low phase noise and low jitter for clock input signal (e.g., HP/Agilent 8644B) * Two signal generators with low phase noise for analog signal inputs (e.g., HP/Agilent 8644B) * Logic analyzer or data-acquisition system (e.g., HP/Agilent 16500C) * Narrow-band analog bandpass filters (e.g., Allen Avionics, K&L Microwave) for input signals and clock signal * Digital multimeter Procedure The EV kit is a fully assembled and tested printed circuit (PC) board. Follow the steps below to verify board operation. Do not turn on power supplies or enable signal generators until all connections are completed. 1) Verify that shunts are installed in the following locations: JU1 (2-3) Independent reference mode JU2 (2-3) ADC active (not in power-down mode) JU3 (2-3) Outputs in two's-complement format JU4 (1-2) Differential clock input JU5 (2-3) No clock division JU6 (2-3) No clock division 2) Connect the clock signal generator to the input of the clock bandpass filter. 3) Connect the output of the clock bandpass filter to the SMA connector labeled J7. 4) Connect the analog input signal generators to the inputs of the desired analog bandpass filters. For best results, connect the bandpass filter directly to the SMA connector and forego any cables in between. 5) Connect the output of the analog bandpass filters to the SMA connectors labeled J1 and J2. The analog input signals can be monitored at J3 and J4. Eliminate cables between bandpass filter outputs and SMA connectors. If cables must be used, they should be as short as possible. Add a 3dB to 6dB attenuator between bandpass filter and SMA connectors to control undesired distortion components induced by the signal generator. 6) Connect the logic analyzer to headers J5 and J6 to collect digitized data from channels A and B. See the Output Bit Locations section in this document for header connections. 7) Connect a 3.3V, 500mA power supply to VDD and connect its ground terminal to the GND pad. 8) Connect a 2.0V, 50mA power supply to OVDD and connect its ground terminal to the GND pad. 9) Connect a 2.0V, 100mA power supply to VLOGIC and connect its ground terminal to the GND pad. 10) Short the VCLK pad to the corresponding GND pad. Note: The VCLK supply is only required when the data converter is operating in single-ended clock mode. See the Configuring the EV Kit for Single-Ended Clock Operation section in this document for further details. _______________________________________________________________________________________ 3 Evaluate: MAX12527/28/29/57/58/59 Component Suppliers Evaluate: MAX12527/28/29/57/58/59 MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits 11) Turn on all the power supplies. 12) Enable the signal generators. 13) Set the clock signal generator to the desired clock frequency. See the Part Selection Table for the appropriate frequency settings for each EV kit. The amplitude of the generator should be sufficient to produce a 16dBm signal at the SMA input of the EV kit. Insertion losses due to the series-connected filter (step 2) and the interconnecting cables decrease the amount of power seen at the EV kit input. Account for these losses when setting the signal generator amplitude. 14) Set the analog input signal generators to output the desired test frequency. The amplitude of the generator should produce a signal that is no larger than 7.5dBm as measured at the SMA input of the EV kit. Insertion losses due to the series-connected filter (step 5) and the interconnecting cables decrease the amount of power seen at the EV kit input. Account for these losses when setting the signal generator amplitude. Also account for the attenuation from the 3dB to 6dB attenuator. 15) All signal generators should be phase-locked to each other. Power Supplies For best performance, the EV kits require separate analog, digital, clock, and buffer power-supply sources. Individual 3.3V and 2.0V power supplies are recommended to power the analog (VDD) and digital (OVDD) portions of the converter. A separate 2.0V power supply (VLOGIC) is used to power the output buffers (U2, U3) of the EV kit. The on-board clock circuitry (VCLK) is powered by a 3.3V power supply. The VCLK supply is only required when the ADC is operating in single-ended clock mode. See the Configuring the EV Kit for Single-Ended Clock Operation section for further details. Converter Power-Down The MAX12527, MAX12528, MAX12529, MAX12557, MAX12558, and MAX12559 each feature an active-high global device power-down pin. Jumper JU2 controls this feature. See Table 1 for shunt positions. Table 1. Power-Down Shunt Settings (JU2) SHUNT POSITION PD PIN 1-2 OVDD 2-3* GND DESCRIPTION ADC powered down ADC active (normal operation) *Default configuration: JU2 (2-3). 16) Enable the logic analyzer. 17) Collect data using the logic analyzer. Detailed Description The EV kit is a fully assembled and tested circuit board that contains all the components necessary to evaluate the performance of the MAX12527, MAX12528, MAX12529, MAX12557, MAX12558, or MAX12559. The ADCs accept differential input signals; however, onboard transformers (T1-T4) convert a readily available single-ended source output to the required differential signal. The input signals of the ADC can be measured using a differential oscilloscope probe at headers J3 and J4. Output drivers (U2 and U3) buffer the output signals of the data converter. The digital outputs of the EV kit are accessible at headers J5 and J6. The EV kits are designed as a four-layer PC board to optimize the performance of this family of ADCs. Separate analog, digital, clock, and buffer power planes minimize noise coupling between analog and digital signals. 100 differential microstrip transmission lines are used for analog and clock inputs. 50 microstrip transmission lines are used for all digital outputs. The trace lengths of the 100 differential input lines are matched to within a few thousandths of an inch to minimize layout-dependent input-signal skew. 4 Clock Additionally, the data converter allows for either differential or single-ended signals to drive the clock inputs. The MAX12527/MAX12528/MAX12529/MAX12557/ MAX12558/MAX12559 EV kits support both methods. In single-ended operation, the clock signal is applied to the ADC through a buffer (U5). In differential mode, an on-board transformer converts a user-provided singleended analog input and generates a differential analog signal, which is then applied to the ADC's input pins. Jumper JU4 controls the ADC clock input. See Table 2 for jumper configuration. Table 2. Clock Selection Shunt Settings (JU4) SHUNT POSITION DIFFCLK/ SECLK PIN 1-2* OVDD 2-3 GND DESCRIPTION Differential clock mode. Single-ended clock mode. See the Configuring the EV Kit for Single-Ended Clock Operation section for further details. *Default configuration: JU4 (1-2). _______________________________________________________________________________________ MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits 2) Install 0 resistors at locations R40, R42, and R45. 3) Install a 49.9 1% resistor at location R37. Optimizing the Analog Input Network for Different Input Frequencies The EV kits are designed for excellent AC performance across a broad 3MHz to 400MHz input frequency range. The design can be further optimized by adjusting components C7-C10 and R49-R52. See Table 4 for the appropriate component values for specific input frequency ranges. Table 4. Component Selection for Optimized AC Performance 4) Connect a 3.3V power supply to VCLK (needs to be capable of sourcing up to 10mA output current). Connect the ground terminal of this supply to GND. INPUT FREQUENCY RANGE (MHz) In single-ended clock configuration, potentiometer R48 can be utilized to control the duty cycle of the clock input signal. Measure the clock input at J8 and adjust R48 until the desired duty cycle is achieved. Clock-Divider Control The MAX12527, MAX12528, MAX12529, MAX12557, MAX12558, and MAX12559 each feature internal divide-by-2/divide-by-4 clock-divider circuitry (DIV2, DIV4). Jumpers JU5 and JU6 control this circuitry. Refer to the individual ADC data sheets for a detailed explanation of the internal clock divider. See Table 3 for jumper configuration. Table 3. Clock-Divider Shunt Settings (JU5, JU6) SHUNT POSITION JU5 JU6 2-3* 1-2 PIN CONNECTION DESCRIPTION DIV2 DIV4 2-3* GND GND Normal clock mode 2-3 OVDD GND Divide-by-2 clock mode (DIV2) 2-3 1-2 GND 1-2 1-2 OVDD OVDD Divide-by-4 clock mode (DIV4) C7-C10 COMPONENT VALUES (pF) R49-R52 COMPONENT VALUES () 3 to 400* 5.6 25 < 10 12 to 22 0 10 to 125 12 25 to 50 > 125 5.6 to 12 0 *Default EV kit configuration. Reference The MAX12527, MAX12528, MAX12529, MAX12557, MAX12558, and MAX12559 feature numerous reference operation modes. The default EV kit configuration connects the ADC's internal 2.048V reference output to the reference input. In this case, the converter generates the REFN, REFP, and COM voltages from this input (refer to the individual ADC's data sheet for a more detailed explanation). To apply a user-supplied reference, cut the trace at location R33 and connect the desired external reference to the REFIN pad. Alternatively, the EV kit can be configured to use a divided internal reference value. If the desired reference voltage is less than 2.048V, cut the trace at location R33 and install resistors in locations R33 and R34. Calculate the resistor values from the equations below: OVDD INVALID R34 = *Default configuration: JU5 (2-3), JU6 (2-3). Input Signal Although this family of ADCs accepts differential analog input signals, the EV kit only requires single-ended analog input signals, with amplitudes less than 7.5dBm. Insertion losses due to a series-connected filter and the interconnecting cables decrease the amount of power seen at the EV kit input. Account for these losses when setting the signal generator amplitude. On-board transformers (T1-T4) convert the single-ended analog input signals and generate the recommended differential analog signals at the ADCs' differential input pins. VREF VREFOUT x RT R33 = RT - R34 where: VREF = desired reference voltage VREFOUT = ADC's internal reference voltage of 2.048V RT = ADC's minimum reference resistance 10k _______________________________________________________________________________________ 5 Evaluate: MAX12527/28/29/57/58/59 Configuring the EV Kits for Single-Ended Clock Operation To configure the MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 EV kits for singleended clock operation, the following modifications must be made to the clock circuit: 1) Cut the trace at locations R41, R43, and R44. Evaluate: MAX12527/28/29/57/58/59 MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits Shared Reference Mode To maximize isolation between the two input channels, the MAX12527, MAX12528, MAX12529, MAX12557, MAX12558, and MAX12559 feature two independent references. To improve channel matching this family of ADCs provides a mode where both input channels share the same reference. Jumper JU1 controls this shared reference feature. See Table 5 for the desired jumper configuration. Table 5. Shared Reference Shunt Settings (JU1) SHUNT POSITION 1-2 2-3* SHREF PIN OVDD GND DESCRIPTION Shared reference mode. Install 0 resistors at locations R35 and R36. Independent reference mode. Remove any component at locations R35 and R36. *Default configuration: JU1 (2-3). Alternative Reference Mode The MAX12527, MAX12528, MAX12529, MAX12557, MAX12558, and MAX12559 derive their REFP, REFN, and COM voltages from the REFIN input. To override these derived voltages, follow the board modifications given below. 1) Cut the trace at location R33. 2) Remove resistor R34 (not installed by default). 3) Connect the REFIN pad to GND. 4) Apply the desired voltages to test points TP1-TP6. See Table 6 for a detailed description of test point connections. Table 6. Reference Test Point Connections TEST POINT CONNECTION TP1 COMA TP2 COMB TP3 REFPA TP4 REFNA TP5 REFPB TP6 REFNB DESCRIPTION Common-mode voltage for channel A. Common-mode voltage for channel B. Positive voltage reference terminal for channel A. Negative voltage reference terminal for channel A. Positive voltage reference terminal for channel B. Negative voltage reference terminal for channel B. Note: Refer to the respective ADC data sheet for REFP, REFN, and COM voltage ranges. Output Signal The MAX12527, MAX12528, and MAX12529 feature two 12-bit, parallel, CMOS-compatible digital outputs that transmit the converted analog input signals. The higherresolution MAX12557, MAX12558, and MAX12559 feature two 14-bit, parallel, CMOS-compatible digital outputs that transmit the converted analog input signals. Each set of 12-bit or 14-bit digital outputs also includes a clock (CLK) bit and overrange (DORA/B) bit to accommodate data synchronization and error detection. See the Output Bit Locations section for more details on how to configure these 12-bit and 14-bit converter outputs. Output Format Set the digital output coding to either two's-complement or Gray code, by configuring jumper JU3. See Table 7 for the jumper configuration. Table 7. Output Format Shunt Settings (JU3) SHUNT POSITION G/T Pin 1-2 OVDD 2-3* GND DESCRIPTION Gray code selected. Digital output format is Gray code. Two's complement selected. Digital output format is two's complement. *Default configuration: JU3 (2-3). 6 _______________________________________________________________________________________ MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits Note: Silkscreen markings on the EV kit PC board indicate pin markings for the MAX12557, MAX12558, and MAX12559. These pin markings are not valid for the MAX12527, MAX12528, or MAX12529. Use the connections outlined in Table 9. Table 8. Output Bit Locations (MAX12557, MAX12558, MAX12559--14-Bit, Dual ADCs) Table 9. Output Bit Locations (MAX12527, MAX12528, MAX12529--12-Bit, Dual ADCs) CHANNEL DESCRIPTION SIGNAL J6-37 Data Bit 0 (LSB) J6-35 Data Bit 1 J5-33 J6-33 D3 J5-31 D4 J5-29 D5 SIGNAL A B D0 J5-37 D1 J5-35 D2 CHANNEL DESCRIPTION A B N.C. J5-37 J6-37 N.C. J5-35 J6-35 N.C. Data Bit 2 D0 J5-33 J6-33 Data Bit 0 (LSB) J6-31 Data Bit 3 D1 J5-31 J6-31 Data Bit 1 J6-29 Data Bit 4 D2 J5-29 J6-29 Data Bit 2 J5-27 J6-27 Data Bit 5 D3 J5-27 J6-27 Data Bit 3 D6 J5-25 J6-25 Data Bit 6 D4 J5-25 J6-25 Data Bit 4 D7 J5-23 J6-23 Data Bit 7 D5 J5-23 J6-23 Data Bit 5 D8 J5-21 J6-21 Data Bit 8 D6 J5-21 J6-21 Data Bit 6 N.C. D9 J5-19 J6-19 Data Bit 9 D7 J5-19 J6-19 Data Bit 7 D10 J5-17 J6-17 Data Bit 10 D8 J5-17 J6-17 Data Bit 8 D11 J5-15 J6-15 Data Bit 11 D9 J5-15 J6-15 Data Bit 9 D12 J5-13 J6-13 Data Bit 12 D10 J5-13 J6-13 Data Bit 10 D13 J5-11 J6-11 Data Bit 13 (MSB) D11 J5-11 J6-11 Data Bit 11 (MSB) DOR J5-9 J6-9 Over Range Bit DOR J5-9 J6-9 Over Range Bit CLK J5-3 J6-3 Clock Bit CLK J5-3 J6-3 Clock Bit Note: Pins 1, 2, 5, 6, 39, and 40 of J5 and pins 1, 2, 5, 6, 7, 39, and 40 of J6 are open. All other pins that are not listed in Table 8 are connected to GND. Note: Pins 1, 2, 5, 6, 39, and 40 of J5 and pins 1, 2, 5, 6, 7, 39, and 40 of J6 are open. All other pins that are not listed in Table 9 are connected to GND. _______________________________________________________________________________________ 7 Evaluate: MAX12527/28/29/57/58/59 Output Bit Locations Two drivers (U2 and U3) buffer the digital outputs of the individual ADCs. These drivers can drive large capacitive loads, which may be present at the logic analyzer connection. The outputs of the buffers are connected to 40-pin headers J5 and J6. See Table 8 (14-bit ADCs) and Table 9 (12-bit ADCs) for bit locations of headers J5 and J6. J2 J1 R3 OPEN C2 SHORT (PC TRACE) R4 SHORT (PC TRACE) R2 SHORT (PC TRACE) R1 OPEN R8 OPEN 4 3 6 2 T2 5 1 R7 OPEN R6 OPEN 4 3 6 2 T1 5 1 C4 OPEN C3 OPEN REFIN R12 75 0.5% R11 75 0.5% R10 75 0.5% R9 75 0.5% C12 4.7F 4 3 6 4 2 6 2 R16 OPEN T4 R15 OPEN R14 OPEN T3 5 1 3 5 1 R36 OPEN R27 OPEN R25 OPEN C17 0.1F C13 0.1F R34 OPEN R20 110 0.5% R19 110 0.5% R18 110 0.5% R17 110 0.5% C5 0.1F R26 SHORT (PC TRACE) C6 0.1F C16 0.1F C14 0.1F C22 4.7F C21 4.7F R28 SHORT (PC TRACE) R24 SHORT (PC TRACE) TP2 R23 SHORT (PC TRACE) R22 SHORT (PC TRACE) TP1 R21 SHORT (PC TRACE) R49 24.9 0.5% R51 24.9 0.5% C9 5.6pF _______________________________________________________________________________________ JU2 1 2 3 1 2 3 JU1 OVDD TP5 TP3 JU3 OVDD 1 2 3 TP6 TP4 CLKP C11 0.1F COMB COMA CLKN R35 OPEN OVDD C18 0.1F C15 0.1F J4 R33 SHORT (PC TRACE) C10 R32 5.6pF SHORT R52 (PC TRACE) 24.9 0.5% C20 0.1F COMB J3 R31 SHORT (PC TRACE) C8 R30 5.6pF SHORT R50 (PC TRACE) 24.9 0.5% C19 0.1F COMA C7 5.6pF R29 SHORT (PC TRACE) 64 65 66 11 10 8 7 20 19 68 67 16 12 15 3 6 2 OVDD VDD VDD G/T PD SHREF REFPB REFNB REFNA REFPA CLKP CLKN REFIN 1 REFOUT INBP COMB INBN INAN COMA INAP VDD 4 5 VDD MAX12557 MAX12558 MAX12559 U1 OVDD DIV2 DIV4 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DORB DAV DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 DA12 DA13 DORA DIFFCLK/SECLK OVDD 23 24 25 26 61 62 63 27 43 60 VDD GND R13 OPEN VDD 9 13 14 17 GND R5 OPEN VDD GND OVDD GND GND 8 GND Figure 1. MAX12557/MAX12558/MAX12559 EV Kit Schematic (Sheet 1 of 4) GND C1 SHORT (PC TRACE) VDD 18 21 22 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 JU4 1 2 3 OVDD 1 2 3 OVDD JU5 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DORB LATCH DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 DA12 DA13 DORA JU6 1 2 3 OVDD Evaluate: MAX12527/28/29/57/58/59 MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits _______________________________________________________________________________________ DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 DA13 DA12 DORA GND 15 14 13 12 11 10 9 3 4 6 7 8 5 16 9 8 2 10 7 1 11 6 RA2 220 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 2D6 1 1OE 24 2OE 47 46 44 43 41 40 38 37 30 2D5 32 2D4 33 2D3 35 2D2 36 2D1 13 12 5 29 14 2D7 27 15 3 4 2D8 1CLK 2 26 48 16 LATCH 2 3 1 RA1 220 C33 220F 6.3V 1 L1 2 7 18 VLOGIC C36 220F 6.3V 31 42 C39 10F U2 PI74ALVTC16374 VCC C34 220F 6.3V VCC C42 1.0F 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2CLK 3 4 10 15 21 28 34 45 39 C29 0.1F 16 15 14 3 4 5 6 7 8 1 2 3 4 5 6 7 8 20 19 17 16 14 13 12 11 9 8 6 5 3 2 9 10 11 12 13 9 10 11 12 13 14 15 2 22 RA6 220 CLK VDD C25 4.7F 16 C23 4.7F RA5 220 C43 1.0F 1 LATCH C40 10F 23 25 C28 0.1F C37 220F 6.3V C24 4.7F C26 4.7F C30 0.1F J5-8 J5-38 J5-40 J5-36 J5-39 J5-34 J5-32 J5-30 J5-28 J5-26 J5-24 J5-22 J5-20 J5-18 J5-16 J5-14 J5-12 J5-10 J5-37 J5-35 J5-33 J5-31 J5-29 J5-27 J5-25 J5-23 J5-21 J5-19 J5-17 J5-15 J5-11 J5-13 J5-7 J5-9 J5-6 J5-4 J5-3 J5-5 J5-2 J5-1 J5 40-PIN HEADER C27 4.7F C31 0.1F OVDD C32 0.1F Evaluate: MAX12527/28/29/57/58/59 VDD GND VCC GND GND GND GND GND GND 1 VCC L2 GND GND OVDD MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits Figure 2. MAX12557/MAX12558/MAX12559 EV Kit Schematic (Sheet 2 of 4) 9 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB12 DB11 DORB DB13 15 14 13 12 11 10 9 3 4 6 7 8 5 16 9 8 2 10 7 1 11 6 RA4 220 14 3 4 5 15 2 13 12 16 RA3 220 1 C35 220F 6.3V 2 LATCH 3 1CLK 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1 1OE 24 2OE 47 46 44 43 41 40 38 37 26 2D8 27 2D7 29 2D6 30 2D5 32 2D4 33 2D3 35 2D2 36 2D1 48 C38 220F 6.3V 18 31 VCC 42 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 Figure 3. MAX12557/MAX12558/MAX12559 EV Kit Schematic (Sheet 3 of 4) ______________________________________________________________________________________ 4 10 15 21 28 34 45 39 A 10 9 6 7 8 1 2 3 4 5 6 7 8 16 13 12 11 9 8 6 5 3 2 14 17 4 5 9 10 11 12 13 14 15 16 11 12 14 13 15 19 16 3 RA8 220 RA7 220 Y 4 20 GND C60 0.1F CLK C67 1.0F VLOGIC C59 0.1F VCC 5 U4 NC7SV125 C58 0.1F 22 3 1 OE 2 C57 0.1F 1 2 23 25 C44 1.0F 2CLK LATCH C66 10F U3 PI74ALVTC16374 7 VLOGIC C41 10F VCC GND 1 VCC VLOGIC VCC GND GND GND GND GND GND 10 GND GND L3 C61 10F C63 0.1F J6-8 J6-39 J6-37 J6-35 J6-33 J6-31 J6-29 J6-27 J6-25 J6-23 J6-21 J6-19 J6-17 J6-13 J6-15 J6-40 J6-38 J6-36 J6-34 J6-32 J6-30 J6-28 J6-26 J6-24 J6-22 J6-20 J6-18 J6-14 J6-16 J6-10 J6-12 J6-6 J6-7 J6-9 J6-11 J6-4 J6-5 J6-2 J6-3 J6-1 J6 40-PIN HEADER C62 0.1F C64 0.1F C65 0.1F VLOGIC Evaluate: MAX12527/28/29/57/58/59 MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits ______________________________________________________________________________________ J2 J1 R3 OPEN C2 SHORT (PC TRACE) R4 SHORT (PC TRACE) R2 SHORT (PC TRACE) R1 OPEN R8 OPEN 4 3 6 2 T2 5 1 R7 OPEN R6 OPEN 4 3 6 2 T1 5 1 C4 OPEN C3 OPEN REFIN R12 75 0.5% R11 75 0.5% R10 75 0.5% R9 75 0.5% C12 4.7F 4 3 6 4 2 6 2 R16 OPEN T4 R15 OPEN R14 OPEN T3 5 1 3 5 1 R36 OPEN R27 OPEN R25 OPEN C17 0.1F C13 0.1F R34 OPEN R20 110 0.5% R19 110 0.5% R18 110 0.5% R17 110 0.5% C5 0.1F R26 SHORT (PC TRACE) C6 0.1F C16 0.1F C14 0.1F C22 4.7F C21 4.7F R28 SHORT (PC TRACE) R24 SHORT (PC TRACE) TP2 R23 SHORT (PC TRACE) R22 SHORT (PC TRACE) TP1 R49 24.9 0.5% R51 24.9 0.5% C9 5.6pF JU2 1 2 3 1 2 3 JU1 OVDD TP5 TP3 JU3 OVDD 1 2 3 TP6 TP4 CLKP C11 0.1F COMB COMA CLKN R35 OPEN OVDD C18 0.1F C15 0.1F J4 R33 SHORT (PC TRACE) C10 R32 5.6pF SHORT R52 (PC TRACE) 24.9 0.5% C20 0.1F COMB J3 R31 SHORT (PC TRACE) C8 R30 5.6pF SHORT R50 (PC TRACE) 24.9 0.5% C19 0.1F COMA C7 5.6pF 64 65 66 11 10 8 7 20 19 68 67 16 12 15 3 6 2 VDD VDD G/T PD SHREF REFPB REFNB REFNA REFPA CLKP CLKN REFIN 1 REFOUT INBP COMB INBN INAN COMA INAP VDD 4 5 MAX12527 MAX12528 MAX12529 U1 OVDD DIFFCLK/SECLK DIV2 DIV4 N.C. N.C. DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DORB DAV N.C. N.C. DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 DORA OVDD 23 24 25 26 61 62 63 27 43 60 VDD GND R29 SHORT (PC TRACE) VDD 9 13 14 17 GND R21 SHORT (PC TRACE) VDD GND R13 OPEN VDD GND R5 OPEN OVDD OVDD GND GND GND 18 21 22 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 JU4 1 2 3 OVDD 1 2 3 OVDD JU5 N.C. N.C. DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DORB LATCH N.C. N.C. DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 DORA JU6 1 2 3 OVDD Evaluate: MAX12527/28/29/57/58/59 C1 SHORT (PC TRACE) VDD MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits Figure 4. MAX12527/MAX12528/MAX12529 EV Kit Schematic (Sheet 1 of 4) 11 Figure 5. MAX12527/MAX12528/MAX12529 EV Kit Schematic (Sheet 2 of 4) ______________________________________________________________________________________ N.C. N.C. DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA11 DA10 DORA GND 11 10 9 6 7 8 5 13 12 4 8 14 9 7 3 10 15 11 6 16 12 5 2 14 13 3 4 1 15 2 RA2 220 16 1 RA1 220 C33 220F 6.3V 1 LATCH 2 L1 2D8 1CLK 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1 1OE 24 2OE 47 46 44 43 41 40 38 37 2D7 29 2D6 30 2D5 32 2D4 33 2D3 35 2D2 36 2D1 27 26 48 3 2 7 18 VLOGIC C36 220F 6.3V 31 42 C39 10F U2 PI74ALVTC16374 VCC C34 220F 6.3V VCC VDD GND 1 VCC OVDD VCC C42 1.0F 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2CLK 3 4 10 15 21 28 34 45 39 GND GND GND GND GND GND 12 GND GND L2 C29 0.1F 16 15 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 20 19 17 16 14 13 12 11 9 8 6 5 3 2 9 10 11 12 13 14 9 10 11 12 13 14 15 1 RA6 220 CLK VDD C25 4.7F 16 C23 4.7F RA5 220 C43 1.0F 22 LATCH C40 10F 23 25 C28 0.1F C37 220F 6.3V C24 4.7F C26 4.7F C30 0.1F J5-38 J5-40 J5-36 J5-39 J5-34 J5-32 J5-30 J5-28 J5-26 J5-24 J5-22 J5-20 J5-18 J5-16 J5-14 J5-12 J5-10 J5-8 J5-6 J5-4 J5-2 J5-37 J5-35 J5-33 J5-31 J5-29 J5-27 J5-25 J5-23 J5-21 J5-19 J5-17 J5-15 J5-11 J5-13 J5-7 J5-9 J5-5 J5-3 J5-1 J5 40-PIN HEADER C27 4.7F C31 0.1F OVDD C32 0.1F Evaluate: MAX12527/28/29/57/58/59 MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits ______________________________________________________________________________________ N.C. N.C. DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB10 DB9 DORB DB11 15 14 13 12 11 10 9 3 4 6 7 8 5 16 9 8 2 10 7 1 11 6 RA4 220 14 3 4 5 15 2 13 12 16 1 RA3 220 2 LATCH 1CLK 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1 1OE 24 2OE 47 46 44 43 41 40 38 37 26 2D8 27 2D7 29 2D6 30 2D5 32 2D4 33 2D3 35 2D2 36 2D1 48 C38 220F 6.3V 18 31 VCC 42 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 4 10 15 21 28 34 45 39 A VCC 5 10 9 11 10 9 6 7 8 1 2 3 4 5 6 7 8 16 13 12 11 9 8 6 5 3 2 14 17 12 13 14 15 16 11 12 14 13 15 4 5 22 19 16 3 RA8 220 RA7 220 Y 4 20 GND C60 0.1F CLK C67 1.0F VLOGIC C59 0.1F 1 2 3 C58 0.1F U4 NC7SV125P5 1 OE 2 C57 0.1F 23 25 C44 1.0F 2CLK LATCH C66 10F U3 PI74ALVTC16374 7 VLOGIC C41 10F VCC C35 220F 6.3V 3 VCC GND 1 VCC GND GND GND GND GND GND VLOGIC GND GND C61 10F C63 0.1F J6-8 J6-39 J6-37 J6-35 J6-33 J6-31 J6-29 J6-27 J6-25 J6-23 J6-21 J6-19 J6-17 J6-13 J6-15 J6-40 J6-38 J6-36 J6-34 J6-32 J6-30 J6-28 J6-26 J6-24 J6-22 J6-20 J6-18 J6-14 J6-16 J6-10 J6-12 J6-6 J6-7 J6-9 J6-11 J6-4 J6-5 J6-2 J6-3 J6-1 J6 40-PIN HEADER C62 0.1F C64 0.1F C65 0.1F VLOGIC Evaluate: MAX12527/28/29/57/58/59 L3 MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits Figure 6. MAX12527/MAX12528/MAX12529 EV Kit Schematic (Sheet 3 of 4) 13 Evaluate: MAX12527/28/29/57/58/59 MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits R43 SHORT (PC TRACE) C51 0.01F R41 SHORT (PC TRACE) C45 0.1F J7 CLKN 1 R37 OPEN T5 R38 49.9 1% 6 2 5 3 4 2 D1 R45 OPEN 1 J8 R39 49.9 1% 3 CLKP VCLK R44 SHORT (PC TRACE) C52 0.01F R46 100 1% VCLK R48 10k C46 R47 100 1% 0.01F 5 1 R40 OPEN U5-A U5-B 6 3 4 R42 OPEN 2 VCLK L4 VCLK GND 1 C53 220F 6.3V 3 2 C47 220F 6.3V C55 10F C56 1F Figure 7. MAX12527/MAX12528/MAX12529/MAX12557/MAX12558/MAX12559 EV Kit Schematic (Sheet 4 of 4) 14 ______________________________________________________________________________________ MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits Evaluate: MAX12527/28/29/57/58/59 Figure 8. MAX12527/MAX12528/MAX12529/MAX12557/MAX12558/MAX12559 EV Kit Component Placement Guide--Component Side ______________________________________________________________________________________ 15 Evaluate: MAX12527/28/29/57/58/59 MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits Figure 9. MAX12527/MAX12528/MAX12529/MAX12557/MAX12558/MAX12559 EV Kit PC Board Layout--Component Side 16 ______________________________________________________________________________________ MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits Evaluate: MAX12527/28/29/57/58/59 Figure 10. MAX12527/MAX12528/MAX12529/MAX12557/MAX12558/MAX12559 EV Kit PC Board Layout (Inner Layer 2)--Ground Planes ______________________________________________________________________________________ 17 Evaluate: MAX12527/28/29/57/58/59 MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits Figure 11. MAX12527/MAX12528/MAX12529/MAX12557/MAX12558/MAX12559 EV Kit PC Board Layout (Inner Layer 3)--Power Planes 18 ______________________________________________________________________________________ MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits Evaluate: MAX12527/28/29/57/58/59 Figure 12. MAX12527/MAX12528/MAX12529/MAX12557/MAX12558/MAX12559 EV Kit PC Board Layout--Solder Side ______________________________________________________________________________________ 19 Evaluate: MAX12527/28/29/57/58/59 MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits Figure 13. MAX12527/MAX12528/MAX12529/MAX12557/MAX12558/MAX12559 EV Kit PC Board Component Placement Guide--Solder Side Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.