W942516CH
Publication Release Date: May 20, 2003
- 11 - Revision A2
7.6 AC Characteristics and Operating Condition
(Notes: 10, 12)
-7 -75
SYMBOL PARAMETER MIN. MAX. MIN. MAX.
UNITS NOTES
tRC Active to Ref/Active Command Period 65 65
tRFC Ref to Ref/Active Command Period 75 75
tRAS Active to Precharge Command Period 45 100000 45 100000
tRCD Active to Read/Write Command Delay Time 20 20
tRAP Active to Read with Auto Precharge Enable 15 15
nS
tCCD Read/Write(a) to Read/Write(b) Command Period 1 1 tCK
tRP Precharge to Active Command Period 20 20
tRRD Active(a) to Active(b) Command Period 15 15
tWR Write Recovery Time 15 15
tDAL Auto Precharge Write Recovery + Precharge Time 30 30
CL = 2 7.5 15 8 15
tCK CLK Cycle Time CL = 2.5 7 15 7.5 15
tAC Data Access Time from CLK, CLK -0.75 0.75 -0.75 0.75
tDQSCK DQS Output Access Time from CLK, CLK -0.75 0.75 -0.75 0.75
16
tDQSQ Data Strobe Edge to Output Data Edge Skew 0.5 0.5
nS
tCH CLk High Level Width 0.45 0.55 0.45 0.55
tCL CLK Low Level Width 0.45 0.55 0.45 0.55 tCK 11
tHP CLK Half Period (minimum of actual tCH, tCL) Min.
(tCL,tCH) Min.
(tCL,tCH)
tQH DQ Output Data Hold Time from DQS THP
-0.75 THP
-0.75
nS
tRPRE DQS Read Preamble Time 0.9 1.1 0.9 1.1
tRPST DQS Read Postamble Time 0.4 0.6 0.4 0.6 tCK 11
tDS DQ and DM Setup Time 0.5 0.5
tDH DQ and DM Hold Time 0.5 0.5
tDIPW DQ and DM Input Pulse Width (for each input) 1.75 1.75
nS
tDQSH DQS Input High Pulse Width 0.35 0.35
tDQSL DQS Input Low Pulse Width 0.35 0.35
tDSS DQS Falling Edge to CLK Setup Time 0.2 0.2
tDSH DQS Falling Edge Hold Time from CLK 0.2 0.2
tCK 11
tWPRES Clock to DQS Write Preamble Set-up Time 0 0 nS
tWPRE DQS Write Preamble Time 0.25 0.25
tWPST DQS Write Postamble Time 0.4 0.4
tDQSS Write Command to First DQS Latching Transition 0.75 1.25 0.75 1.25
11
tDSSK UDQS – LDQS Skew (x 16) -0.25 0.25 -0.25 0.25
tCK
tIS Input Setup Time 0.9 0.9
tIH Input Hold Time 0.9 0.9
tIPW Control & Address Input Pulse Width (for each input) 2.2 2.2
tHZ Data-out High-impedance Time from CLK, CLK -0.75 0.75 -0.75 0.75
tLZ Data-out Low-impedance Time from CLK, CLK -0.75 0.75 -0.75 0.75
tT(SS) SSTL Input Transition 0.5 1.5 0.5 1.5
nS
tWTR Internal Write to Read Command Delay 1 1 tCK
tXSNR Exit Self Refresh to non-Read Command 75 75 ns
tXSRD Exit Self Refresh to Read Command 10 10 tCK
tREF Refresh Time (8k) 64 64 mS
tMRD Mode Register Set Cycle Time 15 15 nS