#!- !! ( )"-$# ((&, &$(( $# SLUS400D - AUGUST 2000 Protects Sensitive Lithium-Ion Cells From Overcharging and Over-Discharging Dedicated for One-Cell Applications Integrated Low-Impedance MOSFET Switch and Sense Resistor Precision Trimmed Overcharge and Overdischarge Voltage Limits Extremely Low Power Drain 3-A Current Capacity Overcurrent and Short-Circuit Protection Reverse Charger Protection Thermal Protection PW PACKAGE (TOP VIEW) TCLK NC BNEG BNEG BNEG BNEG BNEG BNEG 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 PACK+ CBPS NC PACK- PACK- PACK- PACK- PACK- description DP PACKAGE (TOP VIEW) The UCC3952 monolithic BiCMOS lithium-ion battery protection circuit increases the useful operating life of a one-cell rechargeable battery pack. Cell protection features include internally trimmed charge and discharge voltage limits, discharge current limit with a delayed shutdown, and an ultra-low-current sleep mode state when the cell is discharged. Additional features include an on-chip MOSFET for reduced external component count and a charge pump for reduced power losses while charging or discharging a low-cellvoltage battery pack. This protection circuit requires one external capacitor and can operate and safely shut down in a short circuit condition. TCLK NC NC SUB SUB BNEG BNEG BNEG 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 PACK+ CBPS NC SUB SUB PACK- PACK- PACK- Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2000, Texas Instruments Incorporated #$&"( $# ' )&&#( ' $ %)! ( $# ( &$)(' $#$&" ($ '% ( $#' %& ( (&"' $ +' #'(&)"#(' '(#& *&&#(, &$)( $# %&$'' # $' #$( #''& !, #!) ('( # $ !! %&"(&' POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SLUS400D - AUGUST 2000 application diagram PACK + 1 TCLK 16 3 k + 2 N/C 15 3 BNEG 4 BNEG PACK - 13 5 BNEG PACK - 12 6 BNEG PACK - 11 7 BNEG PACK - 10 CBPS 0.1F 14 NC 8 CHARGER LOAD 9 BNEG PACK - AVAILABLE OPTIONS PACKAGES TA -20C to 70 C 2 TSSOP-16 (PW) SOIC-16 (DP) UCC3952PW-1 UCC3952DP-1 UCC3952PW-2 UCC3952DP-2 UCC3952PW-3 UCC3952DP-3 UCC3952PW-4 UCC3952DP-4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLUS400D - AUGUST 2000 absolute maximum ratings over operating free-air temperature (unless otherwise noted) Supply voltage (PACK+ to BNEG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Maximum forward voltage (PACK+ to PACK-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V Maximum reverse voltage (where PACK+ to BNEG = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -8 V Maximum cell continuous charge current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 A Junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to 150C Storage Temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Data Book for thermal limitations and considerations of packages. All voltages are referenced to GND. electrical characteristics, TA = -20C to 70C, all voltages are with respect to BNEG (unless otherwise stated) state transition threshold PARAMETER V(OV) V(OVR) Normal to overcharge voltage Overcharge to normal recovery voltage g TEST CONDITIONS MIN TYP MAX UCC3952-1 4.15 4.20 4.25 UCC3952-2 4.20 4.25 4.30 UCC3952-3 4.25 4.30 4.35 UCC3952-4 4.30 4.35 4.40 UCC3952-1 3.85 3.90 3.95 UCC3952-2 3.90 3.95 4.00 UCC3952-3 3.95 4.00 4.05 UCC3952-4 4.00 4.05 4.10 UNITS V V V(UV) V(UVR) Normal to undercharge 2.25 2.35 2.45 V Undercharge to normal recovery 2.55 2.65 2.75 V td(OD) Overcharge delay time 10 25 40 MIN TYP MAX ms short circuit protection PARAMETER TEST CONDITIONS I(THLD) td(DLY) Discharge current limit PACK+ = 3.7 V Discharge current delay PACK+ = 3.7 V, R(RESET) Discharge current reset resistance PACK+ = 3.7 V UNITS 3.0 6.0 A 1 3.0 ms II = 6 A 7.5 M bias PARAMETER IDD IDD(OV) I(SD) TEST CONDITIONS Supply current Operating supply current in overvoltage V(UV) < V(PACK) < V(OV) V(OV) < V(PACK) Shutdown current V(PACK) = 2.0 V V(min) Minimum cell voltage when all circuits are fully functional td(OV) Overvoltage delay time MIN * DALLAS, TEXAS 75265 MAX 5 8 A 11 1 POST OFFICE BOX 655303 TYP UNITS 24 A 2.5 A 1.7 V 2 s 3 SLUS400D - AUGUST 2000 electrical characteristics, TA = -20C to 70C, all voltages are with respect to BNEG (unless otherwise stated) (continued) FET switch PARAMETER TEST CONDITIONS MIN PACK+ > VOV , I(SWITCH) = 1 mA to 2 A, Battery overcharged state switch permits discharge current only. V(PACK-) RON Voltage at PACK PACK- Series resistance of the device PACK+ = 2.5V, I(SWITCH) = -1 mA to -2 A, Battery overdischarged state switch permits charge current only. -600 PACK+ = 2.5 V, In normal mode (when not in OV or UV). This value includes package and bondwire resistance. TYP MAX UNITS 100 400 mV -100 50 mV 75 m thermal shutdown PARAMETER T(SD) TEST CONDITIONS Thermal shutdown temperature (see Note 2) MIN TYP 135 MAX UNITS C NOTE 2: This parameter is ensured by design and is not production tested. detailed description pin descriptions BNEG Connect the negative terminal of the battery to this pin. PACK+ Connect to the positive terminal of the battery. This pin is available to the user. CBPS This power supply bypass pin is connected to PACK+ through an internal 3-k resistor. An external 0.1-F capacitor must be connected between this pin and BNEG. PACK- The negative terminal of the battery pack (negative terminal available to the user). The internal FET switch connects this terminal to the BNEG terminal to give the battery pack user appropriate access to the battery. In an overcharged state, only discharge current is permitted. In an overdischarged state, only charge current is permitted. SUB (DP Package Only) Do not connect. These pins must be electrically isolated from all other pins. The SUB pins may be soldered to an isolated copper pad for heatsinking. However, most applications do not require heatsinking. TCLK Production test mode pin. This pin is used to provide a high-frequency clock to the IC during production testing. In an application, this pin is left unconnected or tied to BNEG. 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLUS400D - AUGUST 2000 APPLICATION INFORMATION PACK+ 16 CBPS 15 3k V UV V UVR V OVR TCLK 1 N/C 2 4-1 MUX T DEL 1SEC OV THRESHOLD COMPARATOR V OV STATE MACHINE LOGIC 1.5V SEL T DEL 10mS UV CLK BNEG 3 BNEG 4 BNEG 5 SYSTEM CLOCK GENERATOR TDLS 1mS V PUMP BNEG 6 BNEG 7 BNEG 8 PACK- 9 PACK- 10 PACK- 11 PACK- 12 PACK- 13 NC 14 SETD 50mV 2M 50mV RST THERMAL SHUTDOWN Figure 1. Detailed Block Diagram battery voltage monitoring The battery cell voltage is sampled every 8 ms by connecting a resistor divider across it and comparing the resulting voltage to a precision internal reference voltage. Under normal conditions (cell voltage is below overvoltage threshold and above undervoltage threshold), the UCC3952 consumes less than 10 A of current and the internal MOSFET is fully turned on with the aid of a charge pump. When the cell voltage falls below the undervoltage threshold for two consecutive samples, the IC disconnects the load from the battery pack and enters a super-low-power mode. The pack remains in this state until it detects the application of a charger, at which point charging is enabled. The requirement of two consecutive readings below the undervoltage threshold filters out momentary drops in cell voltage due to load transients, preventing nuisance trips. If the cell voltage exceeds the overvoltage threshold for 1 second, charging is disabled; however, discharge current is still allowed. This feature of the IC is explained further in the controlled charge/discharge mode section of this document. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SLUS400D - AUGUST 2000 APPLICATION INFORMATION overcurrent monitoring and protection Discharge current is continuously monitored via an internal sense resistor. In the event of excessive current, an overcurrent condition is declared if the high current (over 3 A) persists for over 1 ms. This delay allows for charging of the system bypass capacitors without tripping the overcurrent protection. A 0.1-F capacitor on the CBPS pin provides momentary holdup for the IC to assure proper operation in the event that a hard short suddenly pulls the cell voltage below the minimum operating voltage. Once an overcurrent condition has been declared, the internal MOSFET turns off. To return the device to normal operation, the UCC3952 requires a load impedance greater than 7.5 M across PACK+ to PACK-. This impedance is typically achieved by removing the battery pack from the system. At this point, the pack returns to its normal state of operation. controlled charge/discharge mode When the chip senses an overvoltage condition, it prevents any additional charging, but allows discharge. This is accomplished by activating a linear control loop, which controls the gate of the MOSFET based on the differential voltage across its drain-to-source terminals. The linear loop attempts to regulate the differential voltage across the MOSFET to 100 mV. When a light load is applied to the part, the loop adjusts the impedance of the MOSFET to maintain 100 mV across it. As the load increases, the impedance of the MOSFET is decreased to maintain the 100-mV control. At heavy loads (still below the overcurrent limit), the loop does not maintain regulation and drives the gate of the MOSFET to the battery voltage (not the charge-pump output voltage). The MOSFET RDS(on) in the overvoltage state is higher than RDS(on) during normal operation. The voltage drop (and associated power loss) across the internal MOSFET in this mode of operation is still significantly lower than the typical solution of two external back-to-back MOSFETs, where the body diode is conducting. When the chip senses an undervoltage condition, it disconnects the load from the battery pack and shuts itself down to minimize current drain from the battery. Several circuits remain powered and detect placement of the battery pack into a charger. Once the charger presence is detected, the linear loop is activated and the chip allows charging current into the battery. This linear control mode of operation is in effect until the battery voltage reaches a level of VUVR , at which time normal operation is resumed. 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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