IRFP450APBF - Vishay / Semiconductor

Document Number: 91230 www.vishay.com

S-81271-Rev. A, 16-Jun-08 1

Power MOSFET

IRFP450A, SiHFP450A

Vishay Siliconix

FEATURES

• Low Gate Charge Qg Results in Simple Drive

Requirement

• Improved Gate, Avalanche and Dynamic dV/dt

Ruggedness

• Fully Characterized Capacitance and

Avalanche Voltage and Current

• Effective Coss Specified

• Lead (Pb)-free Available

APPLICATIONS

• Switch Mode Power Supply (SMPS)

• Uninterruptable Power Supply

• High Speed Power Switching

TYPICAL SMPS TOPOLOGIES

• Two Transistor Forward

• Half Bridge, Full Bridge

• PFC Boost

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).

b. Starting TJ = 25 °C, L = 7.8 mH, RG = 25 Ω, IAS = 14 A (see fig. 12).

c. ISD ≤ 14 A, dI/dt ≤ 130 A/µs, VDD ≤ VDS, TJ ≤ 150 °C.

d. 1.6 mm from case.

PRODUCT SUMMARY

VDS (V) 500

RDS(on) (Ω)V

GS = 10 V 0.40

Qg (Max.) (nC) 64

Qgs (nC) 16

Qgd (nC) 26

Configuration Single

N-Channel MOSFET

TO-247

Available

RoHS*

COMPLIANT

ORDERING INFORMATION

Package TO-247

Lead (Pb)-free IRFP450APbF

SiHFP450A-E3

SnPb IRFP450A

SiHFP450A

ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted

PARAMETER SYMBOL LIMIT UNIT

Drain-Source Voltage VDS 500 V

Gate-Source Voltage VGS ± 30

Continuous Drain Current VGS at 10 V TC = 25 °C ID

ATC = 100 °C 8.7

Pulsed Drain CurrentaIDM 56

Linear Derating Factor 1.5 W/°C

Single Pulse Avalanche EnergybEAS 760 mJ

Repetitive Avalanche CurrentaIAR 14 A

Repetitive Avalanche EnergyaEAR 19 mJ

Maximum Power Dissipation TC = 25 °C PD190 W

Peak Diode Recovery dV/dtcdV/dt 4.1 V/ns

Operating Junction and Storage Temperature Range TJ, Tstg - 55 to + 150 °C

Soldering Recommendations (Peak Temperature) for 10 s 300d

Mounting Torque 6-32 or M3 screw 10 lbf · in

1.1 N · m

* Pb containing terminations are not RoHS compliant, exemptions may apply

www.vishay.com Document Number: 91230

2S-81271-Rev. A, 16-Jun-08

IRFP450A, SiHFP450A

Vishay Siliconix

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).

b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.

c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80 % VDS.

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYP. MAX. UNIT

Maximum Junction-to-Ambient RthJA -40

°C/WCase-to-Sink, Flat, Greased Surface RthCS 0.24 -

Maximum Junction-to-Case (Drain) RthJC -0.65

SPECIFICATIONS TJ = 25 °C, unless otherwise noted

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Static

Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = 250 µA 500 - - V

VDS Temperature Coefficient ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.58 - V/°C

Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = 250 µA 2.0 - 4.0 V

Gate-Source Leakage IGSS V

GS = ± 30 V - - ± 100 nA

Zero Gate Voltage Drain Current IDSS

VDS = 500 V, VGS = 0 V - - 25 µA

VDS = 400 V, VGS = 0 V, TJ = 125 °C - - 250

Drain-Source On-State Resistance RDS(on) V

GS = 10 V ID = 8.4 Ab--0.40Ω

Forward Transconductance gfs VDS = 50 V, ID = 8.4 Ab7.8 - - S

Dynamic

Input Capacitance Ciss VGS = 0 V,

VDS = 25 V,

f = 1.0 MHz, see fig. 5

- 2038 -

Output Capacitance Coss - 307 -

Reverse Transfer Capacitance Crss -10-

Output Capacitance Coss V

GS = 0 V; VDS = 1.0 V, f = 1.0 MHz 2859

Output Capacitance Coss V

GS = 0 V; VDS = 400 V, f = 1.0 MHz 81

Effective Output Capacitance Coss eff. VGS = 0 V; VDS = 0 V to 400 Vc96

Total Gate Charge Qg

VGS = 10 V ID = 14 A, VDS = 400 V,

see fig. 6 and 13b

--64

nC Gate-Source Charge Qgs --16

Gate-Drain Charge Qgd --26

Turn-On Delay Time td(on)

VDD = 250 V, ID = 14 A,

RG = 6.2 Ω, RD = 17 Ω, see fig. 10b

-15-

Rise Time tr -36-

Turn-Off Delay Time td(off) -35-

Fall Time tf -29-

Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode Current IS

MOSFET symbol

showing the

integral reverse

p - n junction diode

--14

Pulsed Diode Forward CurrentaISM --56

Body Diode Voltage VSD TJ = 25 °C, IS = 14 A, VGS = 0 Vb--1.4

Body Diode Reverse Recovery Time trr TJ = 25 °C, IF = 14 A, dI/dt = 100 A/µsb- 487 731 ns

Body Diode Reverse Recovery Charge Qrr -3.95.8µC

Forward Turn-On Time ton Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

Document Number: 91230 www.vishay.com

S-81271-Rev. A, 16-Jun-08 3

IRFP450A, SiHFP450A

Vishay Siliconix

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

Fig. 1 - Typical Output Characteristics

Fig. 2 - Typical Output Characteristics

Fig. 3 - Typical Transfer Characteristics

Fig. 4 - Normalized On-Resistance vs. Temperature

www.vishay.com Document Number: 91230

4S-81271-Rev. A, 16-Jun-08

IRFP450A, SiHFP450A

Vishay Siliconix

Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

Fig. 7 - Typical Source-Drain Diode Forward Voltage

Fig. 8 - Maximum Safe Operating Area

Document Number: 91230 www.vishay.com

S-81271-Rev. A, 16-Jun-08 5

IRFP450A, SiHFP450A

Vishay Siliconix

Fig. 9 - Maximum Drain Current vs. Case Temperature

Fig. 10a - Switching Time Test Circuit

Fig. 10b - Switching Time Waveforms

Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms

Pulse width ≤ 1 µs

Duty factor ≤ 0.1 %

D.U.T.

10 V

VDS

90 %

10 %

VGS

td(on) trtd(off) tf

IAS

0.01 Ω

D.U.T.

VDS

-VDD

Driver

15 V

20 VIAS

VDS

www.vishay.com Document Number: 91230

6S-81271-Rev. A, 16-Jun-08

IRFP450A, SiHFP450A

Vishay Siliconix

Fig. 12c - Maximum Avalanche Energy vs. Drain Current

Fig. 13a - Basic Gate Charge Waveform

Fig. 12d - Typical Drain-to-Source Voltage vs.

Avalanche Current

Fig. 13b - Gate Charge Test Circuit

QGS QGD

Charge

10 V

D.U.T.

3 mA

VGS

VDS

IGID

0.3 µF

0.2 µF

50 kΩ

12 V

Current regulator

Current sampling resistors

Same type as D.U.T.

Document Number: 91230 www.vishay.com

S-81271-Rev. A, 16-Jun-08 7

IRFP450A, SiHFP450A

Vishay Siliconix

Fig. 14 - For N-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon

Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and

reliability data, see htt p://www.vishay.com/ppg?91230.

P.W.Period

dI/dt

Diode recovery

dV/dt

Ripple ≤5 %

Body diode forward drop

Re-applied

voltage

Reverse

recovery

current

Body diode forward

current

= 10 V*

Driver gate drive

D.U.T. I

waveform

D.U.T. V

waveform

Inductor current

D = P.W.

Period

* VGS = 5 V for logic level devices

Peak Diode Recovery dV/dt Test Circuit

VDD

• dV/dt controlled by RG

• Driver same type as D.U.T.

• ISD controlled by duty factor "D"

• D.U.T. - device under test

D.U.T. Circuit layout considerations

• Low stray inductance

• Ground plane

• Low leakage inductance

current transformer

Package Information

www.vishay.com Vishay Siliconix

Revision: 01-Jul-13 1Document Number: 91360

For technical questions, contact: hvm@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

TO-247AC (High Voltage)

Notes

1. Dimensioning and tolerancing per ASME Y14.5M-1994.

2. Contour of slot optional.

3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at

the outermost extremes of the plastic body.

4. Thermal pad contour optional with dimensions D1 and E1.

5. Lead finish uncontrolled in L1.

6. Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154").

7. Outline conforms to JEDEC outline TO-247 with exception of dimension c.

8. Xian and Mingxin actually photo.

MILLIMETERS INCHES MILLIMETERS INCHES

DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.

A 4.58 5.31 0.180 0.209 D2 0.51 1.30 0.020 0.051

A1 2.21 2.59 0.087 0.102 E 15.29 15.87 0.602 0.625

A2 1.17 2.49 0.046 0.098 E1 13.72 - 0.540 -

b 0.99 1.40 0.039 0.055 e 5.46 BSC 0.215 BSC

b1 0.99 1.35 0.039 0.053 Ø k 0.254 0.010

b2 1.53 2.39 0.060 0.094 L 14.20 16.25 0.559 0.640

b3 1.65 2.37 0.065 0.093 L1 3.71 4.29 0.146 0.169

b4 2.42 3.43 0.095 0.135 N 7.62 BSC 0.300 BSC

b5 2.59 3.38 0.102 0.133 Ø P 3.51 3.66 0.138 0.144

c 0.38 0.86 0.015 0.034 Ø P1 - 7.39 - 0.291

c1 0.38 0.76 0.015 0.030 Q 5.31 5.69 0.209 0.224

D 19.71 20.82 0.776 0.820 R 4.52 5.49 0.178 0.216

D1 13.08 - 0.515 - S 5.51 BSC 0.217 BSC

ECN: X13-0103-Rev. D, 01-Jul-13

DWG: 5971

0.10 AC

M M

E/2

(2)

(4)

R/2

2 x R

See view B

2 x e

3 x b

2 x b2

123

Ø k BD

M M

ØP (Datum B)

ØP1

0.01 BD

M M

View A - A

Thermal pad

DDE E

View B

(b1, b3, b5) Base metal

(b, b2, b4)

Section C - C, D - D, E - E

(c)

Planting

Lead Assignments

1. Gate

2. Drain

3. Source

4. Drain

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Revision: 08-Feb-17 1Document Number: 91000

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