LTC1041
1
1041fa
■
Micropower 1.5µW (1 Sample/Second)
■
Wide Supply Range 2.8V to 16V
■
High Accuracy
Guaranteed
SET POINT Error ±0.5mV Max
Guaranteed
Deadband ±0.1% of Value Max
■
Wide Input Voltage Range V
+
to Ground
■
TTL Outputs with 5V Supply
■
Two
Independent
Ground-Referred Control Inputs
■
Small Size 8-Pin SO
The LTC
®
1041 is a monolithic CMOS BANG-BANG
controller manufactured using Linear Technology’s
enhanced LTCMOS™ silicon gate process. BANG-BANG
loops are characterized by turning the control element
fully ON or fully OFF to regulate the average value of
the parameter to be controlled. The SET POINT input
determines the average control value and the DELTA input
sets the deadband. The deadband is always 2 x DELTA and
is centered around the SET POINT. Independent control
of the SET POINT and deadband, with no interaction, is
made possible by the unique sampling input structure of
the LTC1041.
An external RC connected to the OSC pin sets the sampling
rate. At the start of each sample, internal power to the
analog section is switched on for ≈ 80µs. During this time,
the analog inputs are sampled and compared. After the
comparison is complete, power is switched off. This
achieves extremely low average power consumption
at low sampling rates. CMOS logic holds the output
continuously while consuming virtually no power.
To keep system power at an absolute minimum, a switched
power output (V
P-P
) is provided. External loads, such as
bridge networks and resistive dividers, can be driven by
this switched output.
The output logic sense (i.e., ON = V
+
) can be reversed
(i.e., ON = GND) by interchanging the V
IN
and SET POINT
inputs. This has no other effect on the operation of
the LTC1041.
BANG-BANG Controller
, LTC and LT are registered trademarks of Linear Technology Corporation.
FEATURES
APPLICATIO S
U
DESCRIPTIO
U
■
Temperature Control (Thermostats)
■
Motor Speed Control
■
Battery Charger
■
Any ON-OFF Control Loop
LTCMOS is a trademark of Linear Technology Corporation.
Ultralow Power 50°F to 100°F (2.4µW) Thermostat
Supply Current vs Sampling Frequency
TYPICAL APPLICATIO
U
1N4002
(4)
0.1µF
26V AC 2-WIRE THERMOSTAT
4.32k
5k
6.81k
49.9Ω
ALL RESISTORS 1%. YELLOW SPRINGS INSTRUMENT CO., INC. P/N 44007.
DRIVING THERMISTOR WITH VP-P ELIMINATES 3.8°F ERROR DUE TO SELF-HEATING
4.99k
1µF6V
+
10M
LTC1041 • TA01
56Ω
IS
400nA
8
7
6
5
1
2
3
4
DELTA = 0.5°F
2N6660
†
†
LTC1041
SAMPLING FREQUENCY, fS (Hz)
0.1
0.01
SUPPLY CURRENT, IS (µA)
0.1
1
10
100
1000
10000
1 10 100 1000
LTC1041 • TA02
10000
VS = 6V
TOTAL SUPPLY
CURRENT
LTC1041 SUPPLY
CURRENT
LTC1041
2
1041fa
ORDER PART
NUMBER
LTC1041CN8
LTC1041CS8
LTC1041MJ8
J8 PACKAGE
8-LEAD CERDIP
T
JMAX
= 150°C, θ
JA
= 100°C/W
N8 PACKAGE
8-LEAD PDIP
TOP VIEW
1
2
3
4
8
7
6
5
ON / OFF
V
IN
SET POINT
GND
V
+
V
P-P
OSC
DELTA
S8 PACKAGE
8-LEAD PDIP
T
JMAX
= 110°C, θ
JA
= 150°C/W (N8)
T
JMAX
= 150°C, θ
JA
= 150°C/W (S8)
Total Supply Voltage (V
+
to V
–
) .............................. 18V
Input Voltage ........................ (V
+
+ 0.3V) to (V
–
– 0.3V)
Operating Temperature Range
LTC1041C......................................... –40°C to 85°C
LTC1041M (OBSOLETE) .................. –55°C to125°C
Storage Temperature Range ................. –55°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
Output Short Circuit Duration .......................Continuous
Consult LTC Marketing for parts specified with wider operating temperature ranges.
(Note 1)
ABSOLUTE AXI U RATI GS
WWWU
PACKAGE/ORDER I FOR ATIO
UU
W
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test Conditions: V+ = 5V, unless otherwise specified.
ELECTRICAL CHARACTERISTICS
TC1041M/LTC1041C
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SET POINT Error (Note 3) V
+
= 2.8V to 6V (Note 2) ±0.3 ±0.5 mV
● + +
±0.05 ±0.1 % of DELTA
V
+
= 6V to 15V (Note 2) ±1±3mV
●+ +
±0.05 ±0.1 % of DELTA
Deadband Error (Note 4) V
+
= 2.8V to 6V (Note 2) ±0.6 ±1mV
●+ +
±0.1 ±0.2 % of DELTA
V
+
= 6V to 15V (Note 2) ±2±6
●+ +
±0.1 ±0.2 % of DELTA
I
OS
Input Current V
+
= 5V, T
A
= 25°C, OSC = GND ±0.3 nA
(V
IN
, SET POINT and DELTA Inputs)
R
IN
Equivalent Input Resistance f
S
= 1kHz (Note 5) ●10 15 MΩ
Input Voltage Range ●GND V
+
V
P
SR
Power Supply Range ●2.8 16 V
I
S(ON)
Power Supply ON V
+
= 5V, V
P-P
ON ● 1.2 3 mA
Current (Note 6)
I
S(OFF)
Power Supply OFF V
+
= 5V, V
P-P
OFF LTC1041C ●0.001 0.5 µA
Current (Note 6) LTC1041M ●0.001 5 µA
t
D
Response Time (Note 7) V
+
= 5V 60 80 100 µs
ON/OFF Output (Note 8)
V
OH
Logical “1” Output Voltage V
+
= 4.75V, I
OUT
= –360µA●2.4 4.4 V
V
OL
Logical “0” Output Voltage V
+
= 4.75V, I
OUT
= 1.6mA 0.25 0.4 V
R
EXT
External Timing Resistor Resistor Connected between V
+
and OSC Pin ●100 10,000 kΩ
f
S
Sampling Frequency V
+
= 5V, T
A
= 25°C, 5 Hz
R
EXT
= 1M C
EXT
= 0.1µF
OBSOLETE PACKAGE
Consider the N8 Package as an Alternate Source
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired. Note 2: Applies over input voltage range limit and includes gain
uncertainty.
LTC1041
3
1041fa
ELECTRICAL CHARACTERISTICS
Note 3: SET POINT error ≡ – SET POINT
where V
U
= upper band limit and V
L
= lower band limit.
Note 4: Deadband error ≡ (V
U
– V
L
) – 2 • DELTA where V
U
= upper band
limit and V
L
= lower band limit.
V
U
+ V
L
2
( )
TYPICAL PERFOR A CE CHARACTERISTICS
UW
IS(ON) vs V+Sampling Rate vs REXT, CEXT
Normalized Sampling
Frequency vs V+, Temperature
Response Time
vs Supply Voltage
SUPPLY VOLTAGE, V
+
(V)
2
0
I
S(ON)
(mA)
2
6
8
10
20
14
610 12
LTC1041 • TPC01
4
16
18
12
4814 16
25°C
125°C
–55°C
SUPPLY VOLTAGE, V
+
(V)
0
(f
S
AT 5V, 25°C)
NORMALIZED SAMPLING FREQUENCY
1.4
1.8
16
LTC1041 • TPC02
1.0
0.6 4812
2610 14
2.2
1.2
1.6
0.8
2.0
T
A
= 125°C
T
A
= 25°C
T
A
= –55°C
R = 1M, C = 0.1µF
REXT (Ω)
100k
0.1
1
10
102
SAMPLE RATE, fS (Hz)
103
1M 10M
LTC1041 • TPC03
C
EXT
= 1µF
C
EXT
= 0.1µF
C
EXT
= 0.05µF
C
EXT
= 0.01µF
C
EXT
= 1000pF
SUPPLY VOLTAGE, V
+
(V)
2
RESPONSE TIME, t
D
(µs)
200
250
300
812
LTC1041 • TPC04
150
100
46 10 14 16
50
0
T
A
= 25°C
Response Time
vs Temperature
AMBIENT TEMPERATURE, T
A
(°C)
–50
40
RESPONSE TIME, t
D
(µs)
50
70
80
90
50
130
LTC1041 • TPC05
60
0
–25 10075
25 125
100
110
120
V
+
= 5V
Note 5: R
IN
is guaranteed by design and is not tested.
R
IN
= 1/(f
S
x 66pF).
Note 6: Average supply current = t
D
• I
S(ON)
• f
S
+ (1 – t
D
• f
S
) l
S(OFF)
.
Note 7: Response time is set by an internal oscillator and is independent
of overdrive voltage. t
D
= V
P-P
pulse width.
Note 8: Output also capable of meeting EIA/JEDEC standard B series
CMOS drive specifications.
LTC1041
4
1041fa
APPLICATIO S I FOR ATIO
WUUU
The LTC1041 uses sampled data techniques to achieve
its unique characteristics. It consists of two comparators,
each of which has two differential inputs (Figure 1a).
When the sum of the voltages on a comparator’s inputs is
positive, the output is high and when the sum is negative,
the output is low. The inputs are interconnected such that
the R
S
flip-flop is reset (ON/OFF = GND) when
V
IN
> (SET POINT + DELTA) and is set (ON/OFF = V
+
) when
V
IN
< (SET POINT – DELTA). This makes a very precise
hysteresis loop of 2 • DELTA centered around the
SET POINT. (See Figure 1b.)
For R
S
< 10kΩ
The dual differential input structure is made with CMOS
switches and a precision capacitor array. Input
impedance characteristics of the LTC1041 can be
determined from the equivalent circuit shown in Figure 2.
The input capacitance will charge with a time constant of
VP-P Output Voltage
vs Load Current RIN vs Sampling Frequency
LOAD CURRENT, IL (mA)
0
TYPICAL OUTPUT VOLTAGE DROP (V+ – VP-P) (V)
0.8
0.4
0
8
LTC1041 • TPC06
1.2
1.6
2.0
0.6
0.2
1.0
1.4
1.8
21 43 67 9
510
V+ = 2.8V
V+ = 16V
V+ = 5V
V+ = 10V
SAMPLING FREQUENCY fS (Hz)
1
107
AVERAGE INPUT RESISTANCE, RIN (1/fS • 66pF) (Ω)
109
1011
102104
103
10
LTC1041 • TPC07
108
1010
TYPICAL PERFOR A CE CHARACTERISTICS
UW
LTC1041 • AI01a
OSC
(6)
GND
(4)
DELTA
(5)
SET POINT
(3)
VIN
(2)
CEXT
REXT
POWER ON
VP-P
(7)
V+
(8)
ON/OFF
(1)
V+
V+
80µs
4
–
–
+
+COMP B
4
TIMING
GENERATOR VP-P
CIRCUIT
–
–
+
+COMP A
(a)
LTC1041 • AI01b
V
+
GND0V
INPUT VOLTAGE, V
IN
V
L
V
U
SET POINT
DEADBAND
DELTA –
+
DELTA
ON/OFF OUTPUT
Figure 1. LTC1041 Block Diagram
(b)
LTC1041
5
1041fa
APPLICATIO S I FOR ATIO
WUUU
R
S
• C
IN
. The ability to fully charge C
IN
from the signal
source during the controller’s active time is critical in
determining errors caused by the input charging current.
For source resistances less than 10kΩ, C
IN
fully charges
and no error is caused by the charging current.
For R
S
> 10kΩ
For source resistances greater than 10kΩ, C
IN
cannot fully
charge, causing voltage errors. To minimize these errors,
an input bypass capacitor, C
S
, should be used. Charge is
shared between C
IN
and C
S
, causing a small voltage error.
The magnitude of this error is A
V
= V
IN
• C
IN
(C
IN
+ C
S
). This
error can be made arbitrarily small by increasing C
S
.
The averaging effect of the bypass capacitor, C
S
, causes
another error term. Each time the input switches cycle
between the plus and minus inputs, C
IN
is charged and
discharged. The average input current due to this is
I
AVG
= V
IN
• C
IN
• f
S
, where f
S
is the sampling frequency.
Because the input current is directly proportional to the
differential input voltage, the LTC1041 can be said to have
an average input resistance of R
IN
= V
IN
/I
AVG
= I/(f
S
• C
IN
).
Since two comparator inputs are connected in parallel, R
IN
is one half of this value (see typical curve of R
IN
versus
Sampling Frequency). This finite input resistance causes
an error due to the voltage divider between R
S
and R
IN
.
The input voltage error caused by both of these effects is
V
ERROR
= V
IN
[2C
IN
/(2C
IN
+ C
S
) + R
S
/(R
S
+ R
IN
)].
Example: assume f
S
= 10Hz, R
S
= 1M, C
S
= 1µF, V
IN
= 1V,
V
ERROR
= 1V(66µV + 660µV) = 726µV. Notice that most of
the error is caused by R
IN
. If the sampling frequency is
reduced to 1Hz, the voltage error from the input
impedance effects is reduced to 136µV.
Figure 2. Equivalent Input Circuit
V
IN
R
S
C
S
LTC1041 • AI01
S1
S2
C
IN
(≈ 33pF)
V
–
LTC1041 DIFFERENTIAL INPUT
+
–
Input Voltage Range
The input switches of the LTC1041 are capable of
switching either to the V
+
supply or ground. Consequently,
the input voltage range includes both supply rails. This is
a further benefit of the sampling input structure.
Error Specifications
The only measurable errors on the LTC1041 are the
deviations from “ideal” of the upper and lower switching
levels (Figure 1b). From a control standpoint, the error in
the SET POINT and deadband is critical. These errors may
be defined in terms of V
U
and V
L
.
SET POINT error VSET POINT
deadband error V
U
U
≡+
≡
()
V
V DELTA
L
L
2
2
–
––•
The specified error limits (see electrical characteristics)
include error due to offset, power supply variation, gain,
time and temperature.
Pulsed Power (V
P-P
) Output
It is often desirable to use the LTC1041 with resistive
networks such as bridges and voltage dividers. The power
consumed by these resistive networks can far exceed that
of the LTC1041 itself.
At low sample rates the LTC1041 spends most of its time
off. A switched power output, V
P-P
, is provided to drive the
input network, reducing its average power as well. V
P-P
is
switched to V
+
during the controller’s active time (≈ 80µs)
and to a high impedance (open circuit) when internal
power is switched off.
Figure 3 shows the V
P-P
output circuit. The V
P-P
output
voltage is not precisely controlled when driving a load
(see typical curve of V
P-P
Output Voltage vs Load Current).
In spite of this, high precision can be achieved in two ways:
(1) driving ratiometric networks and (2) driving fast set-
tling references.
In ratiometric networks all the inputs are proportional to
V
P-P
(Figure 4). Consequently, the absolute value of V
P-P
does not affect accuracy.
LTC1041
6
1041fa
APPLICATIO S I FOR ATIO
WUUU
If the best possible performance is needed, the inputs to
the LTC1041 must completely settle within 4µs of the start
of the comparison cycle (V
P-P
high impedance to V
+
transition). Also, it is critical that the input voltages do not
change during the 80µs active time. When driving resistive
input networks with V
P-P
, capacitive loading should be
minimized to meet the 4µs settling time requirement.
Further, care should be exercised in layout when driving
networks with source impedances, as seen by the LTC1041,
of greater than 10kΩ (see For R
S
> 10kΩ).
Figure 5. Driving Reference with VP-P Output
V
IN
I
L
LTC1041 • AI05
LT1009-2.5
8
7
6
5
1
2
3
4
LTC1041
SET POINT
DELTA
R2
R3
R4
R1 V
+
Figure 3. VP-P Output Switch
LTC1041 • AI03
80µs
COMPARATOR ON TIME
8
V
+
47
GND
Q1 P1
V
P-P
Figure 4. Ratiometric Network Driven by VP-P
R3
R1
SET POINT
GND DELTA
V
IN
V
+
V
P-P
R2
R4
R5
R6
LTC1041 • AI04
8
7
6
5
1
2
3
4
LTC1041
In applications where an absolute reference is required,
the V
P-P
output can be used to drive a fast settling
reference. The LTC1009 2.5V reference settles in ≈ 2µs
and is ideal for this application (Figure 5). The current
through R1 must be large enough to supply the LT1009
minimum bias current (≈ 1mA) and the load current, I
L
.
Internal Oscillator
An internal oscillator allows the LTC1041 to strobe itself.
The frequency of the oscillation, and hence the sampling
rate, is set with an external RC network (see typical curve,
Sampling Rate R
EXT
, C
EXT
). R
EXT
and C
EXT
are connected
as shown in Figure 1. To assure oscillation, R
EXT
must be
between 100kΩ and 10MΩ. There is no limit to the size of
C
EXT
.
At low sampling rates, R
EXT
is very important in
determining the power consumption. R
EXT
consumes
power continuously. The average voltage at the OSC pin
is approximately V
+
/2, giving a power dissipation of
P
REXT
= (V
+
/ 2)
2
/R
EXT
.
Example: assume R
EXT
= 1MΩ, V
+
= 5V, P
REXT
=
(2.5)
2
/10
6
= 6.25/µW. This is approximately four times the
power consumed by the LTC1041 at V
+
= 5V and
f
S
= 1 sample/second. Where power is a premium,
R
EXT
should be made as large as possible. Note that the
power dissipated by R
EXT
is
not
a function of f
S
or C
EXT
.
If high sampling rates are needed and power consumption
is of secondary importance, a convenient way to get the
maximum possible sampling rate is to make R
EXT
= 100kΩ
and C
EXT
= 0. The sampling rate, set by the controller’s
active time, will nominally be ≈ 10kHz.
To synchronize the Sampling of the LTC1041 to an
external frequency source, the OSC pin can be driven by a
CMOS gate. A CMOS gate is necessary because the input
trip points of the oscillator are close to the supply rails and
TTL does not have enough output swing. Externally driven,
there will be a delay from the rising edge of the OSC input
and the start of the sampling cycle of approximately 5µs.
LTC1041
7
1041fa
Battery Charger
TYPICAL APPLICATIO S
U
LTC1041 • TA04
13Ω
0.1µF
SCR FIRES AT ZERO CROSSING.
SET BATTERY VOLTAGE. BATTERY IS
MEASURED WITH ZERO CHARGE CURRENT
100µF
1N4022
100k
1N4002
1N4002
36.5k
10k
40k
2kΩ
2.21k
OUT
24V
1A
IN
12V
LEAD
ACID
GE 106B
†
UTC D0T20
74C00
74C00
V
+
74C00
89
†
8
7
6
5
1
2
3
4
LTC1041
LT1019-5
5V
115VAC
60 Hz
*
+
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
Motor Speed Controller
320k 24k 20k
500Ω
DEADBAND
3k
SPEED
DEMAND
LT1009
1.1k
320pF
V+
LTC1041 • TA03
1N4002
TACH
8
7
6
5
1
2
3
4
LTC1041
V+
MOTOR*
100k 10k
2N6387
*CANNON CKT26-T5-3SAE
LTC1041
8
1041fa
U
PACKAGE DESCRIPTIO
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
LW/TP 1202 1K REV A • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1985
N8 Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
.016 – .050
(0.406 – 1.270)
.010 – .020
(0.254 – 0.508)× 45°
0°– 8° TYP
.008 – .010
(0.203 – 0.254)
SO8 0502
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
1
N
234
N/2
.150 – .157
(3.810 – 3.988)
NOTE 3
8765
.189 – .197
(4.801 – 5.004)
NOTE 3
.228 – .244
(5.791 – 6.197)
.245
MIN
N
123 N/2
.160 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
.050 BSC
.030 ±.005
TYP
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
N8 1002
.065
(1.651)
TYP
.045 – .065
(1.143 – 1.651)
.130 ± .005
(3.302 ± 0.127)
.020
(0.508)
MIN
.018 ± .003
(0.457 ± 0.076)
.120
(3.048)
MIN
.008 – .015
(0.203 – 0.381)
.300 – .325
(7.620 – 8.255)
.325 +.035
–.015
+0.889
–0.381
8.255
()
12 34
8765
.255 ± .015*
(6.477 ± 0.381)
.400*
(10.160)
MAX
NOTE:
1. DIMENSIONS ARE INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
.100
(2.54)
BSC
J8 Package
8-Lead CERDIP (Narrow .300 Inch, Hermetic)
(Reference LTC DWG # 05-08-1110)
OBSOLETE PACKAGE
J8 0801
.014 – .026
(0.360 – 0.660)
.200
(5.080)
MAX
.015 – .060
(0.381 – 1.524)
.125
3.175
MIN
.100
(2.54)
BSC
.300 BSC
(7.62 BSC)
.008 – .018
(0.203 – 0.457) 0° – 15°
.045 – .065
(1.143 – 1.651)
.045 – .068
(1.143 – 1.650)
FULL LEAD
OPTION
.023 – .045
(0.584 – 1.143)
HALF LEAD
OPTION
CORNER LEADS OPTION
(4 PLCS) .005
(0.127)
MIN
.405
(10.287)
MAX
.220 – .310
(5.588 – 7.874)
1234
8765
.025
(0.635)
RAD TYP
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE
OR TIN PLATE LEADS
