FUJITSU SEMICONDUCTOR DATA SHEET DS04-27237-1E ASSP for Power Supply Applications (DC/DC converter for DSC/camcorder) 5 ch DC/DC Converter IC with Synchronous Rectification MB39A108 DESCRIPTION The MB39A108 is 5-channel DC/DC converter IC using pulse width modulation (PWM), and is suitable for up conversion, down conversion, and up/down conversion. The MB39A108 is built in 5 channels into TSSOP-38P/ BCC-40P package and operates at 2 MHz maximum. Each channel can be controlled with soft-start. The MB39A108 is suitable for power supply of high performance portable instruments such as DSC. FEATURES * * * * * * Supports for down-conversion with synchronous rectification (CH1) Supports for down-conversion and up/down Zeta conversion (CH2, CH3) Supports for up-conversion and up/down Sepic conversion (CH4, CH5) Low voltage start-up (CH4, CH5) : 1.7 V Power supply voltage range : 2.5 V to 11 V Reference voltage : 2.0 V 1% (Continued) PACKAGES 38-pin plastic TSSOP 40-pin plastic BCC (FPT-38P-M03) (LCC-40P-M07) MB39A108 (Continued) * Error amplifier threshold voltage : 1.00 V 1% (CH1), 1.23 V 1% (CH2 to CH5) * Oscillation frequency range : 200 kHz to 2.0 MHz * Standby current : 0 A (Typ) * Built-in soft-start circuit independent of loads * Built-in totem-pole type output for MOS FET * Short-circuit detection capability by external signal ( - INS terminal) 2 MB39A108 PIN ASSIGNMENT (TOP VIEW) CS2 1 38 CS1 -INE2 2 37 -INE1 FB2 3 36 FB1 DTC2 4 35 VCCO VCC 5 34 OUT1-1 CTL 6 33 OUT1-2 CTL3 7 32 OUT2 CTL4 8 31 OUT3 CTL5 9 30 OUT4 -INS 10 29 OUT5 VREF 11 28 GNDO RT 12 27 CS5 CT 13 26 -INE5 GND 14 25 FB5 CSCP 15 24 DTC5 DTC3 16 23 DTC4 FB3 17 22 FB4 -INE3 18 21 -INE4 CS3 19 20 CS4 (FPT-38P-M03) (Continued) 3 MB39A108 (Continued) DTC2 FB2 -INE2 CS2 N.C. CS1 -INE1 FB1 VCCO <TOP VIEW (Penetration diagram from surface)> 40 39 38 37 36 35 34 33 32 3 29 OUT2 CTL4 4 28 OUT3 CTL5 5 27 OUT4 -INS 6 26 OUT5 VREF 7 25 GNDO RT 8 24 CS5 CT 9 23 -INE5 GND 10 22 FB5 21 DTC5 12 13 CSCP DTC3 FB3 14 -INE3 11 15 16 17 18 19 20 DTC4 CTL3 FB4 OUT1-2 -INE4 30 CS4 2 CTL N.C. OUT1-1 1 CS3 31 VCC (LCC-40P-M07) 4 MB39A108 PIN DESCRIPTION Pin No. Block PKG Pin name I/O TSSOP BCC 36 33 FB1 O Error amplifier output terminal. 37 34 - INE1 I Error amplifier inverted input terminal. 38 35 CS1 Soft-start setting capacitor connection terminal. 34 31 OUT1-1 O Pch drive output terminal. (External main side FET gate driving) 33 30 OUT1-2 O Nch drive output terminal. (External synchronous rectification side FET gate driving). 4 40 DTC2 I Dead time control terminal. 3 39 FB2 O Error amplifier output terminal 2 38 - INE2 I Error amplifier inverted input terminal. 1 37 CS2 Soft-start setting capacitor connection terminal. 32 29 OUT2 O Pch drive output terminal. 16 12 DTC3 I Dead time control terminal. 17 13 FB3 O Error amplifier output terminal 18 14 - INE3 I Error amplifier inverted input terminal. 19 15 CS3 Soft-start setting capacitor connection terminal. 31 28 OUT3 O Pch drive output terminal. 23 20 DTC4 I Dead time control terminal. 22 19 FB4 O Error amplifier output terminal. 21 18 - INE4 I Error amplifier inverted input terminal. 20 17 CS4 Soft-start setting capacitor connection terminal. 30 27 OUT4 O Nch drive output terminal. 24 21 DTC5 I Dead time control terminal. 25 22 FB5 O Error amplifier output terminal. 26 23 - INE5 I Error amplifier inverted input terminal. 27 24 CS5 Soft-start setting capacitor connection terminal. 29 26 OUT5 O Nch drive output terminal. 13 9 CT Triangular wave frequency setting capacitor connection terminal. 12 8 RT Triangular wave frequency setting resistor connection terminal. CH1 CH2 CH3 CH4 CH5 OSC Description (Continued) 5 MB39A108 (Continued) Pin No. Block Control Power PKG Pin name I/O Description TSSOP BCC 6 2 CTL I Power supply control terminal. 7 3 CTL3 I CH3 control terminal. 8 4 CTL4 I CH4 control terminal. 9 5 CTL5 I CH5 control terminal. 15 11 CSCP 10 6 - INS I 35 32 VCCO Drive output block power supply terminal. 5 1 VCC Power supply terminal. 11 7 VREF O Reference voltage output terminal. 28 25 GNDO Drive output block ground terminal. 14 10 GND Ground terminal. Short-circuit detection circuit capacitor connection terminal. Short-circuit detection comparator inverted input terminal. Note : The terminal number which has been described in the text is the one of the TSSOP-38P package after this. 6 MB39A108 BLOCK DIAGRAM L <<CH1>> Io = 130 mA at VCCO = 4 V Drive1-1 Pch VREF priority Error - Amp1 + + 10 A CS1 38 + PWM Comp.1 - Dead Time -INE1 37 1.0 V FB1 36 Threshold voltage 1.0 V 1% Drive1-2 Nch Dead Time (td = 50 ns) -INE2 2 L VREF priority Error Amp2 10 A - Max Duty VREF 90% 5% + + CS2 1 35 VCCO 34 OUT1-1 33 OUT1-2 Io = 130 mA at VCCO = 4 V L priority <<CH2>> PWM + Comp.2 + - Drive2 Pch 32 OUT2 1.23 V Io = 130 mA at VCCO = 4 V FB2 3 DTC2 4 -INE3 18 CS3 19 Threshold voltage 1.23 V 1% L VREF priority Error Amp3 1 A - + + L <<CH3>> Max Duty VREF priority 90% 5% PWM Comp.3 + + - Drive3 Pch 31 OUT3 1.23 V FB3 17 DTC3 16 -INE4 21 CS4 20 Io = 130 mA at VCCO = 4 V Threshold voltage 1.23 V 1% L VREF priority Error Amp4 1 A - + + L <<CH4>> Max Duty VREF priority 90% 5% PWM + Comp.4 + - Drive4 Nch 30 OUT4 1.23 V FB4 22 DTC4 23 -INE5 26 CS5 27 Io = 130 mA at VCCO = 4 V Threshold voltage 1.23 V 1% L VREF priority Error Amp5 1 A - + + L <<CH5>> Max Duty VREF priority 90% 5% PWM + Comp.5 + - Drive5 Nch 29 OUT5 1.23 V FB5 25 DTC5 24 28 GNDO VREF 100 k -INS 10 Short-circuit detection signal (L: at short-circuit) Io = 130 mA at VCCO = 4 V Threshold voltage 1.23 V 1% 1V - + SCP Comp. H: at SCP SCP CSCP 15 0.9 V CTL3 7 CTL4 8 CTL5 9 CH CTL H: release UVLO Error Amp power supply SCP Comp. power supply Error Amp reference 0.4 V UVLO2 OSC 12 13 RT CT bias VREF UVLO1 2.0 V 11 VREF 5 VCC 1.23 V Power VR ON/OFF CTL 6 CTL Accuracy 0.8% 14 GND 7 MB39A108 ABSOLUTE MAXIMUM RATINGS Parameter Power supply voltage Symbol VCC Conditions Ratings Unit Min Max VCC, VCCO terminal 12 V Output current IO OUT1 to OUT5 terminal 20 mA Peak output current IOP OUT1 to OUT5 terminal Duty 5% (t = 1/fosc x Duty) 400 mA Power dissipation PD Ta + 25 C (TSSOP-38P) 1680*1 mW Ta + 25 C (BCC-40P) 1020*2 mW - 55 + 125 C Storage temperature TSTG *1 : When mounted on a 76 mm x 76 mm x 1.6 mm FR-4 boards. *2 : When mounted on a 117 mm x 84 mm x 0.8 mm FR-4 boards. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 8 MB39A108 RECOMMENDED OPERATING CONDITIONS Parameter Symbol Conditions Start power supply voltage VCC Power supply voltage Reference voltage output current Input voltage Control input voltage Output current Value Unit Min Typ Max VCC, VCCO terminal (CH4, CH5) 1.7 11 V VCC VCC, VCCO terminal (CH1 to CH5) 2.5 4 11 V IREF VREF terminal -1 0 mA - INE1 to - INE5 terminal 0 VCC - 0.9 V - INS terminal 0 VREF V VDTC DTC2 to DTC5 terminal 0 VREF V VCTL CTL, CTL3 to CTL5 terminal 0 11 V OUT1 to OUT5 terminal - 15 + 15 mA * 0.2 0.97 2.0 MHz VINE IO Oscillation frequency fOSC Timing capacitor CT 27 100 680 pF Timing resistor RT 3.0 6.8 39 k Soft-start capacitor CS 0.1 1.0 F CS1 to CS5 terminal Short-circuit detection capacitor CSCP 0.1 1.0 F Reference voltage output capacitor CREF 0.1 1.0 F Ta - 30 + 25 + 85 C Operating ambient temperature * : Refer to "SETTING THE TRIANGULAR WAVE OSCILLATION FREQUENCY". WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 9 MB39A108 ELECTRICAL CHARACTERISTICS (VCC = VCCO = 4 V, Ta = + 25 C) Parameter Conditions Symbol Pin No. Value Min Typ Max Unit VREF1 11 VREF = 0 mA 1.98 2.00 2.02 V VREF2 11 VCC = 2.5 V to 11 V 1.975 2.000 2.025 V VREF3 11 VREF = 0 mA to - 1 mA 1.975 2.000 2.025 V Input stability Line 11 VCC = 2.5 V to 11 V 2* mV Load stability Load 11 VREF = 0 mA to - 1 mA 2* mV Temperature stability VREF/ VREF 11 Ta = 0 C to + 85 C 0.20* % Short-circuit output current IOS 11 VREF = 0 V - 130* mA Under voltage lockout protection circuit block (CH1 to CH3) [UVLO1_3] Threshold voltage VTH 34 VCC = 1.7 1.8 1.9 V Hysteresis width VH 34 0.05 0.1 0.2 V Reset voltage VRST 34 VCC = 1.55 1.7 1.85 V Under voltage lockout protection circuit block (CH4, CH5) [UVLO4_5] Threshold voltage VTH 30 VCC = 1.35 1.5 1.65 V Hysteresis width VH 30 0.02 0.05 0.1 V Reset voltage VRST 30 1.27 1.45 1.63 V Threshold voltage VTH 15 0.65 0.70 0.75 V Input source current ICSCP 15 - 1.4 - 1.0 - 0.6 A 0.92 0.97 1.02 MHz Output voltage Reference voltage block [VREF] Short-circuit detection block [SCP] VCC = fOSC1 29 to 34 CT = 100 pF, RT = 6.8 k fOSC2 29 to 34 CT = 100 pF, RT = 6.8 k 0.917 VCC = 2.5 V to 11 V 0.97 1.023 MHz Frequency input stability fOSC/ fOSC 29 to 34 CT = 100 pF, RT = 6.8 k VCC = 2.5 V to 11 V 1.0* % Frequency temperature stability fOSC/ fOSC 29 to 34 CT = 100 pF, RT = 6.8 k Ta = 0 C to + 85 C 1.0* % 1, 38 - 13 - 10 -7 A - 1.3 - 1.0 - 0.7 A Oscillation frequency Triangular wave oscillator block [OSC] Soft-start block (CH1, CH2) [CS1, CS2] Charge current ICS Soft-start block (CH3 to CH5) [CS3 to CS5] Charge current ICS CS1, CS2 = 0 V 19, 20, CS3 to CS5 = 0 V 27 * : Standard design value (Continued) 10 MB39A108 (VCC = VCCO = 4 V, Ta = + 25 C) Parameter Symbol Pin No. Conditions VTH1 37 VTH2 Input bias current Error amp block Voltage gain (CH1) Frequency [Error Amp1] bandwidth Output voltage Output source current Output sink current Typ Max VCC = 2.5 V to 11 V Ta = + 25 C 0.990 1.000 1.010 V 37 VCC = 2.5 V to 11 V Ta = 0 C to + 85 C 0.988 1.000 1.012 V VTH/ VTH 37 Ta = 0 C to + 85 C 0.1* % IB 37 - INE1 = 0 V - 120 - 30 nA AV 36 DC 100* dB BW 36 Av = 0 dB 1.4* MHz VOH 36 1.7 1.9 V VOL 36 40 200 mV ISOURCE 36 FB1 = 0.65 V -2 -1 mA ISINK 36 FB1 = 0.65 V 150 200 A VTH1 2, 18, 21, 26 VCC = 2.5 V to 11 V Ta = + 25 C 1.217 1.230 1.243 V VTH2 2, 18, 21, 26 VCC = 2.5 V to 11 V Ta = 0 C to + 85 C 1.215 1.230 1.245 V VTH/ VTH 2, 18, 21, 26 Ta = 0 C to + 85 C 0.1* % IB 2, 18, 21, 26 - INE2 to - INE5 =0V - 120 - 30 nA AV 3, 17, 22, 25 DC 100* dB BW 3, 17, 22, 25 AV = 0 dB 1.4* MHz VOH 3, 17, 22, 25 1.7 1.9 V VOL 3, 17, 22, 25 40 200 mV ISOURCE 3, 17, 22, 25 FB2 to FB5 = 0.65 V -2 -1 mA ISINK 3, 17, 22, 25 FB2 to FB5 = 0.65 V 150 200 A Threshold voltage Temperature stability Input bias current Error amp block Voltage gain (CH2 to CH5) [Error Amp2 to Frequency Error Amp5] bandwidth Output voltage Output source current Output sink current Unit Min Threshold voltage Temperature stability Value * : Standard design value (Continued) 11 MB39A108 (Continued) ( VCC = VCCO = 4 V, Ta = + 25 C) Parameter PWM comparator block (CH1) [PWM Comp.1] PWM comparator block (CH2 to CH5) [PWM Comp.2 to PWM Comp.5] Threshold voltage Threshold voltage Maximum duty cycle Output source current Output sink Output block current (CH1 to CH5) [Drive1 to Drive5] Output on resistor Control block (CTL, CTL3 to CTL5) [CTL, CHCTL] 33, 34 VT100 33, 34 VT0 VT100 Value Unit Min Typ Max Duty cycle = 0% 0.35 0.4 0.45 V Duty cycle = 100% 0.85 0.9 0.95 V 29 to 32 Duty cycle = 0% 0.35 0.4 0.45 V 29 to 32 Duty cycle = 100% 0.85 0.9 0.95 V Dtr 29 to 32 CT = 100 pF, RT = 6.8 k 85 90 95 % ISOURCE 29 to 34 Duty 5% (t = 1/fosc x Duty) OUT = 0 V - 130 - 75 mA ISINK 29 to 34 Duty 5% (t = 1/fosc x Duty) OUT = 4 V 75 130 mA ROH 29 to 34 OUT = - 15 mA 18 27 ROL 29 to 34 OUT = 15 mA 18 27 OUT2 - OUT1 50* ns tD2 33, 34 OUT1 - OUT2 50* ns Threshold voltage VTH 34 0.97 1.00 1.03 V Input bias current IB 10 - 25 - 20 - 17 A Output on condition VIH 6, 7 to 9 CTL, CTL3 to CTL5 1.5 11 V Output off condition VIL 6, 7 to 9 CTL, CTL3 to CTL5 0 0.5 V ICTLH 6, 7 to 9 CTL, CTL3 to CTL5 = 3 V 5 30 60 A ICTLL 6, 7 to 9 CTL, CTL3 to CTL5 = 0 V 1 A Standby current Power supply current * : Standard design value 12 VT0 Conditions 33, 34 Input current General Pin No. tD1 Dead time Short-circuit detection block [SCP Comp.] Symbol - INS = 0 V ICCS 5 CTL, CTL3 to CTL5 = 0 V 0 2 A ICCSO 35 CTL = 0 V 0 1 A ICC 5 CTL = 3 V 4 6 mA MB39A108 TYPICAL CHARACTERISTICS Reference voltage vs. Power supply voltage 5 Reference voltage VREF (V) Power supply current ICC (mA) Power supply current vs. Power supply voltage Ta = + 25 C CTL = 3 V 4 3 2 1 5 Ta = + 25 C CTL = 3 V VREF = 0 mA 4 3 2 1 0 0 0 2 4 6 8 10 0 12 2 4 6 8 10 12 Power supply voltage VCC (V) Power supply voltage VCC (V) Reference voltage VREF (V) Reference voltage vs. Operating ambient temperature 2.05 VCC = 4 V CTL = 3 V VREF = 0 mA 2.04 2.03 2.02 2.01 2.00 1.99 1.98 1.97 1.96 1.95 -40 -20 0 20 40 60 80 100 Operating ambient temperature Ta ( C) CTL terminal current vs. CTL terminal voltage Reference voltage VREF (V) 5.0 Ta = + 25 C VCC = 4 V VREF = 0 mA 4.0 3.0 2.0 1.0 0.0 0 2 4 6 8 10 CTL terminal voltage VCTL (V) 12 CTL terminal current ICTL (A) Reference voltage vs. CTL terminal voltage 250 200 150 100 50 Ta = + 25 C VCC = 4 V 0 0 2 4 6 8 10 12 CTL terminal voltage VCTL (V) (Continued) 13 MB39A108 Triangular wave oscillation frequency vs. Timing capacitor Triangular wave oscillation frequency vs. Timing resistor CT = 27 pF 10000 Ta = + 25 C VCC = 4 V CTL = 3 V Triangular wave oscillation frequency fOSC (kHz) Triangular wave oscillation frequency fOSC (kHz) 10000 1000 CT = 100 pF CT = 680 pF 100 CT = 220 pF 10 1 10 100 1000 Ta = + 25 C VCC = 4 V CTL = 3 V 1000 RT = 2.4 k RT = 36 k 100 10 10 100 Timing resistor RT (k) 1.10 Upper limit 0.80 0.70 0.60 Lower limit 0.40 0.30 0.20 0 10000 Triangular wave upper and lower limit voltage vs. Operating ambient temperature Triangular wave upper and lower limit voltage VCT (V) Triangular wave upper and lower limit voltage VCT (V) 1.20 0.50 1000 Timing capacitor CT (pF) Triangular wave upper and lower limit voltage vs. Triangular wave oscillation frequency Ta = + 25 C VCC = 4 V 1.00 CTL = 3 V 0.90 RT = 6.8 k RT = 6.8 k RT = 13 k 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 Triangular wave oscillation frequency fOSC (kHz) 1.20 1.10 1.00 0.90 VCC = 4 V CTL = 3 V RT = 6.8 k CT = 100 pF Upper limit 0.80 0.70 0.60 0.50 0.40 Lower limit 0.30 0.20 -40 -20 0 20 40 60 80 100 Operating ambient temperature Ta ( C) Triangular wave oscillation frequency vs. Operating ambient temperature Triangular wave oscillation frequency fOSC (kHz) 1100 VCC = 4 V CTL = 3 V RT = 6.8 k CT = 100 pF 1080 1060 1040 1020 1000 980 960 940 920 900 -40 -20 0 20 40 60 80 100 Operating ambient temperature Ta ( C) (Continued) 14 MB39A108 (Continued) Start power supply voltage vs. Timing resistor ON Duty vs. DTC terminal voltage 100 85 80 Start power supply voltage VCC (V) 90 ON Duty (%) 2 Ta = + 25 C VCC = 4 V CTL = 3 V FB = 2 V RT = 6.8 k CT = 100 pF 95 75 70 Calculating value 65 Measurement value 60 55 50 0.6 0.65 0.7 0.75 0.8 0.85 At evaluating Fujitsu EV board system Ta = - 30 C Ta = + 25 C 1.5 CTL = VCC CT = 100 pF 1 0.9 1 10 DTC terminal voltage VDTC (V) 100 Timing resistor RT (k) Error amplifier voltage gain and phase vs. Frequency 225 Ta = + 25 C 180 VCC = 4 V 135 40 Av 30 20 90 10 45 0 0 -10 -45 -20 -90 -30 -135 -40 -180 -50 1k 10 k 100 k 1M 2.0 V 240 k 10 k 1 F + Phase (deg) Error amplifier voltage gain AV (dB) 50 2.4 k IN 10 k 37 - 38 + + 1.5 V 1.0 V 36 OUT Error Amp1 the same as other channels -225 10 M Frequency f (Hz) 2000 Power dissipation vs. Operating ambient temperature (BCC-40P) Power dissipation PD (mW) Power dissipation PD (mW) Power dissipation vs. Operating ambient temperature (TSSOP-38P) 1800 1680 1600 1400 1200 1000 800 600 400 200 0 -40 -20 0 20 40 60 80 100 Operating ambient temperature Ta ( C) 1200 1020 1000 800 600 400 200 0 -40 -20 0 20 40 60 80 100 Operating ambient temperature Ta ( C) 15 MB39A108 FUNCTIONAL DESCRIPTION 1. DC/DC Converter Function (1) Reference voltage block (VREF) The reference voltage circuit generates the reference voltage (2.0 V Typ) to which it makes amends for the temperature by the voltage supplied by the power supply terminal (pin 5). It is used as a reference in IC voltage. It is also possible to supply the load current of up to 1 mA to external device as a output reference voltage through the VREF terminal (pin 11). (2) Triangular wave oscillator block (OSC) The triangular wave oscillator block generates the triangular wave oscillation waveforms of amplitude 0.4 V to 0.9 V by connecting the timing capacitor for and timing resistor to the CT terminal (pin 13) and RT terminal (pin 12) respectively. The triangular wave is input to the PWM comparator in the IC. (3) Error amplifier block (Error Amp1 to Error Amp5) The error amplifier detects output voltage of DC/DC converter and outputs PWM control signals. In addition, an arbitrary loop gain can be set by connecting a feedback resistor and capacitor from the output terminal to inverted input terminal of the error amplifier, enabling stable phase compensation to the system. The CS1 terminal (pin 38) to CS5 terminal (pin 27) that are non-inverted input terminal of error amplifier can prevent rush currents at power supply startup, by connecting a soft-start capacitor. The soft-start time is detected by the error amplifier, which provides a constant soft-start time independent of output load of DC/DC converter. Also, it is possible to prevent rush current at power supply start-up by connecting a soft-start capacitor with CS1 terminal (pin 38) to CS5 terminal (pin 27) which are the non-inverted input terminal for Error Amp. The use of Error Amp for soft-start detection makes it possible for a system to operate on a fixed soft-start time that is independent of the output load on the DC/DC converter. (4) PWM comparator block (PWM Comp.1 to PWM Comp.5) The PWM comparator block is a voltage-pulse width converter that controls the output duty depending on the input/output voltage. When the error amplifier output voltage and DTC voltage remain higher than the triangular wave voltage, output transistor is turned on. (5) Output block (Drive1 to Drive5) The output block is in the totem-pole type, capable of driving an external P-ch MOS FET (CH1 main side, and CH2 and CH3) and N-ch MOS FET (CH1 synchronous rectification side, and CH4 and CH5). 16 MB39A108 2. Channel Control Function Main and each channel are set to ON/OFF by CTL terminal (pin 6) , CS1 terminal (pin 38) , CS2 terminal (pin 1) , CTL3 terminal (pin 7) , CTL4 terminal (pin 8) , and CTL5 terminal (pin 9) . ON/OFF setting condition of each channel CTL CS1 CS2 CTL3 CTL4 CTL5 Power CH1 CH2 CH3 CH4 CH5 L X X X X X OFF Stops Stops Stops Stops Stops H GND GND L L L ON Stops Stops Stops Stops Stops H HiZ GND L L L ON Operation Stops Stops Stops Stops H GND HiZ L L L ON Stops Operation Stops Stops Stops H GND GND H L L ON Stops Stops Operation Stops Stops H GND GND L H L ON Stops Stops Stops Operation Stops H GND GND L L H ON Stops Stops Stops Stops Operation H HiZ HiZ H H H ON Operation Operation Operation Operation Operation Note : Note that current over stand-by current flows into VCC terminal when the CTL terminal is in "L" level and one of terminals between CTL3 to CTL5 is set to "H" level. (Refer to CTL3 to CTL5 terminal equivalent circuit) * CTL3 to CTL5 terminal equivalent circuit VCC 5 CTL3 to 200 k X CTL5 ESD protection element 86 k 223 k GND 14 17 MB39A108 3. Protection Function (1) Timer-latch short-circuit protection circuit (SCP, SCP Comp.) The short-circuit detection comparator (SCP) detects the output voltage level of each channel, and if any channel output voltage becomes the short-circuit detection voltage or less, the timer circuits are actuated to start charging the external capacitor Cscp connected to the CSCP terminal (pin 15) . When the capacitor (Cscp) voltage reaches about 0.7 V, the circuit is turned off the output transistor and sets the dead time to 100%. In addition, the short-circuit detection from external input is capable by using -INS terminal (pin 10) on shortcircuit detection comparator (SCP Comp.) . To release the actuated protection circuit, either turn the power supply off and on again or set the CTL terminal (pin 6) to the "L" level to lower the VREF terminal (pin 11) voltage to 1.27 V (Min) or less (See "SETTING TIME CONSTANT FOR TIMER-LATCH SHORT-CIRCUIT PROTECTION CIRCUIT") . (2) Under voltage lockout protection circuit block (UVLO) The transient state or a momentary decrease in the power supply voltage, which occurs when the power supply is turned on, may cause the IC to malfunction, resulting in breakdown or degradation of the system. To prevent such malfunctions, under voltage lockout protection circuit detects a decrease in internal reference voltage with respect to the power supply voltage, turned off the output transistor, and set the dead time to 100 % while holding the CSCP terminal (pin 15) at "L" level. The circuit restores the output transistor to normal when the power supply voltage reaches the threshold voltage of the under-voltage lockout protection circuit. PROTECTION CIRCUIT OPERATING FUNCTION TABLE This table refers to output condition when protection circuit is operating. Operation circuit OUT1-1 OUT1-2 OUT2 18 OUT3 OUT4 OUT5 Short-circuit protection circuit H L H H L L Under voltage lockout protection circuit H L H H L L MB39A108 SETTING THE OUTPUT VOLTAGE CH1 Vo R1 Error Amp - -INE1 R2 1.00 V Vo = + + (R1 + R2) R2 1.00 V CS1 CH2 to CH5 Vo R1 Error Amp - -INEX R2 + + 1.23 V Vo = (R1 + R2) R2 1.23 V CSX X : Each channel No. SETTING THE TRIANGULAR WAVE OSCILLATION FREQUENCY The triangular wave oscillation frequency can be set by the timing resistor (RT) connected to the RT terminal (pin 12) and the timing capacitor (CT) connected to the CT terminal (pin 13). Triangular wave oscillation frequency : fosc fosc (kHz) =: 659600 CT (pF) * RT (k) 19 MB39A108 SETTING THE SOFT-START TIME To prevent rush currents when the IC is turned on, you can set a soft-start by connecting soft-start capacitors (CS1 to CS5) to the CS1 terminal (pin 38) to CS5 terminal (pin 27) respectively. As shown in the figure below, changing CTLX from "H" to "L" in the CH1 and CH2 circuits causes the external soft-start capacitors (CS1 and CS2) connected to CS1 and CS2 terminals to start charging with a current approximately 10 A. As shown in the figure on the next page, changing CTLX from "L" to "H" in the CH3 to CH5 circuits causes the external soft-start capacitors connected to CS3 to CS5 terminals to start charging with a current of approximately 1 A. The error amplifier output (FB1 to FB5) is determined by comparison between the lower voltage of the two noninverted input terminal voltage (1.23 V (CH : 1.0 V), CS terminal voltages) and the inverted input terminal voltage ( - INE1 to - INE5). The FB terminal voltage is decided for the soft-start period (CS terminal voltage < 1.23 V (CH1 : 1.0 V)) by the comparison between - INE terminal voltage and CS terminal voltage. The DC/DC converter output voltage rises in proportion to the CS terminal voltage as the soft-start capacitor externally connected to the CS terminal is charged. The soft-start time is obtained from the following formula : Soft-start time : ts(time to output 100%) CH1 : ts (s) =: 0.100 x CSX (F) CH2 : ts (s) =: 0.123 x CSX (F) CH3 to CH5 : ts (s) =: 1.23 x CSX (F) * Soft-start circuit (CH1, CH2) VREF Vo 10 A R1 -INEX R2 L priority Error Amp CSX CSX - + + 1.0 V/ 1.23 V CTLX FBX X : Each channel No. 20 MB39A108 * Soft-start circuit (CH3 to CH5) VREF Vo 1 A R1 -INEX R2 L priority Error Amp - + + CSX 1.23 V CSX FBX CTLX CHCTL X : Each channel No. 21 MB39A108 PROCESSING WHEN NOT USING CS TERMINAL When soft-start function is not used, leave the CS1 terminal (pin 38), CS2 terminal (pin 1), CS3 terminal (pin 19), CS4 terminal (pin 20), and CS5 terminal (pin 27) open. * When not setting soft-start time "Open" "Open" 1 CS2 CS1 38 "Open" CS5 27 CS4 20 "Open" "Open" 19 22 CS3 MB39A108 SETTING TIME CONSTANT FOR TIMER-LATCH SHORT-CIRCUIT PROTECTION CIRCUIT Each channel uses the short-circuit detection comparator (SCP Comp.) to always compare the error amplifier's output level to the reference voltage. While DC/DC converter load conditions are stable on all channels, the short-circuit detection comparator output remains at "L" level, and the CSCP terminal (pin 15) is held at "L" level. If the load condition on a channel changes rapidly due to a short-circuit of the load, causing the output voltage to drop, the output of the short-circuit detection comparator on that channel goes to "H" level. This causes the external short-circuit protection capacitor Cscp connected to the CSCP terminal to be charged at 1 A. Short-circuit detection time : tcscp tcscp (s) =: 0.70 x Cscp (F) When the capacitor Cscp is charged to the threshold voltage (VTH =: 0.7V), the latch is set to and the external FET is turned off (dead time is set to 100%). At this time, the latch input is closed and CSCP terminal (pin 15) is held at "L" level. In addition, the short-circuit detection from external input is capable by using -INS terminal (pin 10) on the shortcircuit detection comparator (SCP Comp.) . The short-circuit detection operation starts when -INS terminal voltage is less than threshold voltage (VTH =: 1 V) . When the power supply is turn off and on again or VREF terminal (pin 11) voltage is less than 1.27 V (Min) by setting CTL terminal (pin 6) to "L" level, the latch is released. * Timer-latch short-circuit protection circuit Vo FBX R1 - -INEX Error Amp + R2 1.23 V (CH1 : 1.0 V) SCP Comp. + + - 1.1 V 1 A CSCP To each channel drive CTL 15 VREF CSCP S R Latch UVLO X : Each channel No. 23 MB39A108 PROCESSING WHEN NOT USING CSCP TERMINAL When not using the timer-latch short-circuit protection circuit, connect the CSCP terminal (pin 15) to GND with the shortest distance. * When not using CSCP terminal 24 14 GND 15 CSCP MB39A108 SETTING THE DEAD TIME When the device is set for step-up or inverted output based on the step-up, step-up/down Zeta conversion, stepup/down Sepic conversion, or flyback conversion, the FB terminal voltage may reach and exceed the triangular wave voltage due to load fluctuation. If this is the case, the output transistor is fixed to a full-ON state (ON duty = 100 %). To prevent this, set the maximum duty of the output transistor. When the DTC terminal is opened, the maximum duty is 90% (Typ) because of this IC built-in resistance which sets the DTC terminal voltage. When the DTC terminal is not used, connect it directly to the VREF terminal (pin 11) as shown below (when no dead time is set). * When no dead time is set * When dead time is set (Setting by built-in resistance =: 90%) VREF "Open" DTCX DTCX X : Each channel No. X : Each channel No. Set the DTC terminal voltage by resistance devider from VREF terminal voltage when you change the maximum duty by external resistance. (Refer to "* When dead time is set (Setting by external resistance)". ) When the DTC terminal voltage is higher than the triangular wave voltage, the output transistor is turned on. The maximum duty calculation formula assuming that triangular wave amplitude : = 0.5 V and triangular wave lower voltage : = 0.4 V is given below. It is possible to set DTC terminal voltage (dead time) by disregarding built-in resistance (include the tolerance) by adjusting external resistance to 1/10 or less of built-in resistance. Set to become 1mA or less in total of each channel the load current of VREF terminal. DUTY (ON) Max=: Vdt = Rb Ra + Rb Vdt - 0.4 V 0.5 V x 100 (%)* x VREF (condition : Ra < R1 10 , Rb < R2 10 ) * : DUTY obtained by the above-mentioned formula is a calculated value. For setting, refer to "ON Duty vs. DTC terminal voltage" in TYPICAL CHARACTERISTICS. 25 MB39A108 * When dead time is set (Setting by external resistance) VREF Ra R1 : 131.9 k DTCX Vdt Rb GND To PWM Comp. R2 : 97.5 k X : Each channel No. Example setting : For an aim Max duty (ON) of 80% (Vdt = 0.8 V) with Ra = 13.7 k and Rb = 9.1 k * Calculation using external resistors Ra and Rb only Vdt = Rb Ra + Rb DUTY (ON) Max =: x VREF =: 0.80 V Vdt - 0.4 V 0.5 V x 100 (%) =: 80%* [1] * Calculation considering internal resistor (tolerance 20%) also Vdt = (Rb and R2 combined resistance) (Ra and R1 combined resistance) + (Rb and R2 combined resistance) DUTY (ON) Max =: Vdt - 0.4 V 0.5 V x VREF =: 0.80 V 0.13% x 100 (%) =: 80% 0.2%* [2] * : Based on [1] and [2] above, selecting external resistances of 1/10th or less of the built-in resistance enables the built-in resistance to be ignored. As for the duty difference, please expect 5% (at fOSC = 1 MHz) . It is because of being with the difference of a triangular wave amplitude. 26 MB39A108 OPERATION EXPLANATION WHEN CTL TURNING ON AND OFF When CTL is turned on, internal reference voltage VR and VREF generate. When VREF exceeds each threshold voltage (VTH1,VTH2) of UVLO1 and UVLO2 (under voltage lockout protection circuit), UVLO1 and UVLO2 are released, and the operation of output drive circuit of each channel becomes possible. When CTL is off, VR and VREF fall. When VREF decreases and UVLO1 and UVLO2 fall below each reset voltage (VRST1,VRST2), UVLO operates and output Drive circuit of each channel is forcibly done the operation stop, and makes the output off state. When period to reaching to 2.0 V by VREF voltage after UVLO1 and UVLO2 are released by turning on CTL (refer to a and b in "* Timing chart") and VREF decreases from 2.0 V after turning off CTL and the period until do the operation of UVLO1 and UVLO2(refer to a' and b' in "* Timing chart"), the bias voltage and the bias current in IC do not reach a prescribed value because VREF which is the reference voltage does not reach 2.0 V, and the speed of response for IC has decreased. Moreover, when it does the turning on and off of the input sudden change, the load sudden change, and CTL3 to CTL5 in this period, IC cannot conform and the output might overshoot. Therefore, impress the voltage to CTL terminal by which the VREF terminal voltage never stays in the abovementioned period. * CTL block equivalent circuit H: at SCP CH1 to CH3 To output Drive circuit H: Possible to operate L: Forcibly stop To CS1 to CS3 charge/ discharge circuit H: Possible to charge L: Forcibly discharge SCP UVLO2 H: UVLO release ErrorAmp Reference 1.0 V/1.23 V UVLO1 CH4 and CH5 To output Drive circuit H: Possible to operate L: Forcibly stop To CS4 and CS5 charge/ discharge circuit H: Possible to charge L: Forcibly discharge bias 5 H: UVLO release VREF VR Power ON/OFF CTL 6 VCC CTL 11 VREF 27 MB39A108 * Timing chart V VR = 1.23 V (Typ) Error Amp Reference voltage VR VTH1 VTH2 VREF = 2.00 V (Typ) VRST1 Reference voltage VREF UVLO4_5 release b UVLO4_5 VRST2 b' Valid UVLO4_5 a UVLO1_3 release a' UVLO1_3 Valid UVLO1_3 CH4 and CH5 Output drive circuit control Possible operate Fixed full-off Fixed full-off Possible operate CH1 to CH3 Output drive circuit control CTL terminal voltage Fixed full-off Fixed full-off 1.1 V 0.2 V (Typ) t 28 MB39A108 ABOUT THE LOW VOLTAGE OPERATION 1.7 V or more is necessary for the VCC terminal and the VCCO terminal for the self-power supply type to use the step-up circuit as the start voltage. Even if VIN decreases up to 1.5 V afterwards, it is possible to operate if the VCC terminal voltage and the VCCO terminal voltage rise to 2.5 V or more after start-up. However, it is necessary not to exceed the maximum duty set value by the duty due to the VIN decrease. Include other channels, and confirm an enough operation margin when using it. * Example of self-power supply method circuit VIN A Step up <<CH5>> Error VREF Amp5 R1 R2 -INE5 - + + 1.23 V VCCO PWM Comp.5 Drive5 + + Nch - A Vo5 (5 V) OUT5 CS5 Max duty 90% 5% 0.9 V VCC 0.4 V DTC5 29 MB39A108 I/O EQUIVALENT CIRCUIT VCC 5 1.23 V ESD protection element + - VCC CTL 6 CTLX 53 k 11 VREF ESD protection element * Channel control block (CH3 to to CH5) * Control block * Reference voltage block 86 k 79 k 124 k ESD protection element 278 k 223 k GND GND GND 14 * Soft-start block * Short-circuit detection comparator block * Short-circuit detection block VCC VREF (2.0 V) VREF (2.0 V) VREF (2.0 V) CSX -INS 10 100 k (1V) 2 k 15 CSCP GND GND * Triangular wave oscillator block (CT) * Triangular wave oscillator block (RT) VREF (2.0 V) VREF (2.0 V) 0.64 V GND + - 12 RT CT 13 GND GND * Error amplifier block (CH1 to CH5) VCC VREF (2.0 V) -INEX CSX FBX 1.0 V (CH1) 1.23 V (CH2 to CH5) GND X : Each channel No. (Continued) 30 MB39A108 (Continued) * PMW comparator block * Output block (CH1 to CH5) VCC VCCO 35 VREF (2.0 V) 131.9 k FB2 to FB5 CT OUTX DTCX 97.5 k GNDO 28 GND X : Each channel No. 31 MB39A108 APPLICATION EXAMPLE B R39 R40 510 15 k -INE2 R41 15 k C27 0.1 F VIN (2.5 V to 5 V) CS2 35 34 Q1 VCCO C24 0.1 F OUT1-1 DVo1 1.2 V/500 mA 10 H C1 1 F 33 C2 4.7 F D1 Q2 OUT1-2 Step down B L2 Q3 2 DVo2 2.5 V/250 mA 15 H 1 R42 1 k 32 <<CH2>> C3 1 F OUT2 C4 4.7 F D2 Transformer C D4 Q5 TVo1-1 15 V/10 mA T1 D5 C8 1 F 31 <<CH3>> C10 2.2 F C9 2.2 F OUT3 C11 1 F 30 <<CH4>> OUT4 D6 10 F C12 4.7 L5 F 15 Q7 H SVo1 3.3 V/500 mA C13 10 F Transformer E D7 T2 D8 29 <<CH5>> 28 Q9 OUT5 GNDO C14 1 F -INS CSCP 15 5 CTL3 7 CTL4 8 CTL5 9 6 12 RT R63 6.8 k 13 CT C36 100 pF 11 VREF C37 0.1 F 14 GND VCC C23 0.1 F CTL D9 TVo1-2 5.0 V/50 mA Step up/down D L4 Short-circuit 10 detection signal (L: at short-circuit) 32 L1 <<CH1>> FB2 3 C28 0.047 F DTC2 4 R45 R46 680 30 k -INE3 C 18 R47 10 k CS3 19 R48 C29 1 k 0.1 F FB3 17 C30 0.1 F DTC3 16 R51 R52 300 30 k -INE4 D 21 R53 18 k CS4 20 R54 C31 1 k 0.1 F FB4 22 C32 0.1 F DTC4 23 R57 R58 680 30 k -INE5 E 26 R59 10 k CS5 27 R60 C33 0.1 F 1 k FB5 25 C34 0.1 F DTC5 24 C35 2200 pF Step down A R35 R36 510 4.3 k -INE1 A 37 R37 24 k CS1 38 R38 C25 2 k 0.1 F FB1 36 C26 0.047 F C16 C17 C18 2.2 F 2.2 F 2.2 F TVo2-1 15 V/10 mA TVo2-2 5.0 V/50 mA TVo2-3 -7.5 V/-5 mA MB39A108 PARTS LIST COMPONENT ITEM SPECIFICATION VENDOR PARTS No. Q1, Q3 Q2, Q7, Q9 Q5 Pch FET Nch FET Pch FET VDS = - 12 V, ID = - 1.5 A VDS = 20 V, ID = 1.8 A VDS = - 20 V, ID = - 2 A SANYO SANYO SANYO MCH3317 MCH3405 MCH3306 D1, D2, D6 D4, D5, D7 to D9 Diode Diode VF = 0.4 V (Max), at IF = 1 A VF = 0.55 V (Max), at IF = 0.5 A SANYO SANYO SBS004 SB05-05CP L1, L4 L2, L5 Inductor Inductor 10 H 15 H 0.94 A, 56 m 0.76 A, 97 m TDK TDK RLF5018T100MR94 RLF5018T150MR76 T1, T2 Transformer SUMIDA CLQ52 5388-T138 C1, C3 C2, C4, C12 C8, C11 C9, C10 C13 C14 C16 to C18 C23 to C25, C27 C26, C28 C29 to C34 C35 C36 C37 Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser 1 F 4.7 F 1 F 2.2 F 10 F 1 F 2.2 F 0.1 F 0.047 F 0.1 F 2200 pF 100 pF 0.1 F 25 V 16 V 25 V 25 V 6.3 V 25 V 25 V 50 V 50 V 50 V 50 V 50 V 50 V TDK TDK TDK TDK TDK TDK TDK TDK TDK TDK TDK TDK TDK C3216JB1E105K C3216JB1C475K C3216JB1E105K C3216JB1E225K C3216JB0J106K C3216JB1E105K C3216JB1E225K C1608JB1H104K C1608JB1H473K C1608JB1H104K C1608JB1H222K C1608CH1H101J C1608JB1H104K R35, R39 R36 R37 R38 R40, R41 R42, R48, R54 R45, R57 R46, R52, R58 R47, R59 R51 R53 R60 R63 Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor 510 4.3 k 24 k 2 k 15 k 1 k 680 30 k 10 k 300 18 k 1 k 6.8 k 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% ssm ssm ssm ssm ssm ssm ssm ssm ssm ssm ssm ssm ssm RR0816P-511-D RR0816P-432-D RR0816P-243-D RR0816P-202-D RR0816P-153-D RR0816P-102-D RR0816P-681-D RR0816P-303-D RR0816P-103-D RR0816P-301-D RR0816P-183-D RR0816P-102-D RR0816P-682-D Note : SANYO : SANYO Electric Co., Ltd. TDK : TDK Corporation SUMIDA : Sumida Corporation ssm : SUSUMU CO., LTD. 33 MB39A108 REFERENCE DATA Total efficiency vs. Input voltage 100 TOTAL efficiency (%) 95 IC stops by the short-circuit detection operation of CH2 in VIN =: 2.6 V or less. 90 85 80 Ta = + 25 C DVO1 = 1.2 V, 500 mA DVO2 = 2.5 V, 250 mA TVO1-1 = 15 V , 10 mA TVO1-2 = 5 V, 50 mA SVO1 = 3.3 V, 500 mA TVO2-1 = 15 V, 10 mA TVO2-2 = 5 V, 50 mA TVO2-3 = 7.5 V, -5 mA fOSC = 1 MHz setting 75 70 65 60 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 Input voltage VIN (V) Each CH efficiency vs. Input voltage 100 Each CH Efficiency (%) 95 90 CH2 85 CH4 CH1 80 CH5 Ta = + 25 C DVO1 = 1.2 V, 500 mA DVO2 = 2.5 V, 250 mA TVO1-1 = 15 V , 10 mA TVO1-2 = 5 V, 50 mA SVO1 = 3.3 V, 500 mA TVO2-1 = 15 V, 10 mA TVO2-2 = 5 V, 50 mA TVO2-3 = -7.5 V, -5 mA fOSC = 1 MHz Setting 75 70 65 60 2.0 2.5 3.0 3.5 4.0 CH3 Note : Only concerned CH is ON. Driving current of external SW Tr is contained. 4.5 5.0 5.5 6.0 6.5 7.0 Input voltage VIN (V) (Continued) 34 MB39A108 CH1 and CH4 efficiency vs. Load current 100 VIN = 3.6 V CH1 and CH4 efficiency (%) 95 Ta = +25 C 90 CH1 85 CH4 80 75 70 DIO1 (CH1) 50 mA : discontinuance mode SIO1 (CH4) 80 mA : discontinuance mode 65 Note : Only concerned CH is ON. Driving current of external SW Tr is contained. 60 0 50 100 150 200 250 300 350 400 450 500 Load current IO (mA) CH2 efficiency vs. Load current 100 VIN = 3.6 V 95 Ta = +25 C CH2 CH2 efficiency (%) 90 85 80 75 70 65 DIO2 (CH2) 30 mA : discontinuance mode Note : Only concerned CH is ON. Driving current of external SW Tr is contained. 60 0 25 50 75 100 125 150 175 200 225 250 Load current IO (mA) (Continued) 35 MB39A108 CH3 and CH5 efficiency vs. Load current 100 Note * Only feedback controlling output is get by using transformer channel. TVO1-1 (15 V) : IO = 10 mA fixed TVO2-1 (15 V) : IO = 10 mA fixed TVO2-3 ( - 7.5 V) : IO = - 5 mA fixed * Only concerned CH is ON. Driving current of external SW Tr is contained. CH3 and CH5 efficiency (%) 95 90 85 VIN = 3.6 V Ta = +25 C CH5 80 75 CH3 70 65 TIO1-2 (CH3), TIO2-2 (CH5) 10 mA : discontinuance mode 60 0 10 20 30 40 50 60 Load current IO (mA) (Continued) 36 MB39A108 Switching waveform (CH1) Ta = +25 C VIN = 3.6 V DVo1 = 1.2 V lo1 = 500 mA OUT1-1 [V] 5 0 OUT1-2 [V] 5 0 VD [V] 4 2 0 t [s] 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Switching waveform (CH2) Ta = +25 C VIN = 3.6 V DVo2 = 2.5 V lo2 = 250 mA OUT2 [V] 5 0 VD [V] 4 2 0 t [s] 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Switching waveform (CH3) Ta = +25 C VIN = 3.6 V TVo1-1 = 15 V Tlo1-1 = 10 mA TVo1-2 = 5 V TVo3 = 50 mA OUT3 [V] 5 0 VD [V] 5 0 -5 -10 t [s] 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 (Continued) 37 MB39A108 (Continued) Switching waveform (CH4) Ta = +25 C VIN = 3.6 V SVo1 = 3.3 V Slo1 = 500 mA OUT4 [V] 5 0 VD [V] 10 5 0 t [s] 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Switching waveform (CH5) Ta = +25 C VIN = 3.6 V TVo2-1 = 15 V Tlo2-1 = 10 mA TVo2-2 = 5 V Tlo2-2 = 50 mA TVo2-3 = -7.5 V Tlo2-3 = -5 mA OUT5 [V] 5 0 VD [V] 10 5 0 t [s] 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 38 MB39A108 USAGE PRECAUTIONS * Printed circuit board ground lines should be set up with consideration for common impedance. * Take appropriate static electricity measures. * Containers for semiconductor materials should have anti-static protection or be made of conductive material. * After mounting, printed circuit boards should be stored and shipped in conductive bags or containers. * Work platforms, tools, and instruments should be properly grounded. * Working personnel should be grounded with resistance of 250 k to 1 M between body and ground. * Do not apply negative voltages. * The use of negative voltages below -0.3 V may create parasitic transistors on LSI lines, which can cause abnormal operation. ORDERING INFORMATION Part number Package MB39A108PFT 38-pin plastic TSSOP (FPT-38P- M03) MB39A108PV2 40-pin plastic BCC (LCC-40P-M07) Remarks 39 MB39A108 PACKAGE DIMENSION 38-pin plastic TSSOP (FPT-38P- M03) 9.700.10(.382.004) 1.10(.043) MAX 0~8 0.600.10 (.024.004) 0.25(.010) 0.100.10 (.004.004) 4.400.10 6.400.10 (.173.004) (.252.004) INDEX 0.1270.05 (.005.002) 0.50(.020) 0.900.05 (.035.002) 0.10(.004) 9.00(.354) C 2002 FUJITSU LIMITED F38003Sc-1-1 Dimensions in mm (inches). Note : The values in parentheses are reference values. (Continued) 40 MB39A108 (Continued) 40-pin plastic BCC (LCC-40P-M07) 21 31 5.20(.205)TYP 5.10(.201)TYP 0.80(.031)MAX (Mount height) 6.000.10(.236.004) 0.50(.020) TYP 21 0.500.10 (.020.004) 0.50(.020) TYP 0.14(.006) MIN 6.000.10 (.236.004) 31 5.25(.207) REF 5.20(.205) TYP 4.00(.157) REF 0.500.10 (.020.004) INDEX AREA 5.10(.201) TYP "C" 11 1 11 "B" 0.0750.025 (.003.001) (Stand off) Details of "A" part 0.14(.006) MIN "A" 4.00(.157)REF 5.25(.207)REF Details of "B" part 0.700.06 (.028.002) 1 0.550.06 (.022.002) Details of "C" part C0.20(.008) 0.550.06 (.022.002) 0.05(.002) 0.600.06 (.024.002) C 0.300.06 (.012.002) 0.550.06 (.022.002) 0.550.06 (.022.002) 2004 FUJITSU LIMITED C40057S-c-1-1 Dimensions in mm (inches). Note : The values in parentheses are reference values. 41 MB39A108 FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0502 (c) 2005 FUJITSU LIMITED Printed in Japan