December 2017
DocID028379 Rev 5
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This is information on a product in full production.
www.st.com
RHFL6000A
2 A rad-hard adjustable positive voltage regulator
Datasheet - production data
Features
Input voltage range from 2.5 V to 12 V
2 A guaranteed output current
Low dropout voltage: 0.3 V typ. @ 0.4 A
Embedded overtemperature and overcurrent
protection
Adjustable overcurrent limitation
Output overload monitoring/signalling
Adjustable output voltage
Internal control loop accessible via an
external pin, optional
Inhibit (ON/OFF) TTL compatible control
Programmable output short-circuit current
Remote sensing operation
Rad-hard: guaranteed up to 300 krad
MIL-STD-883J method 1019.9 high dose
rate and 0.01 rad/s in ELDRS conditions
Radiation environment: SET/SEL/SEB:
- SEL free @ LET=120 MeV*cm2/mg
- SET: less than 3.3% of VOUT @ 120 MeV
Heavy-ions SET dedicated internal circuitry
implemented for absorbing output transient
Operating junction temperature range:
-55 °C to 125 °C
Description
The RHFL6000A high-performance adjustable
positive voltage regulator provides exceptional
radiation performance. It is tested in accordance
with mil MIL-STD-883J method 1019.9, in ELDRS
conditions. The device is available in the
FLAT-16P. A dedicated internal circuitry is
implemented for absorbing output transients
during SET events. The operating input voltage
goes from 2.5 V to 12 V.
Table 1: Device summary
Part number
Quality level
EPPL
Package
Lead finish
Mass (g)
RHFL6000AKP1
-
Engineering
model
-
FLAT-16P
Gold
0.70
RHFL6000AKP01V (1)
5962F1521601VXC
QML-V flight
Target
RHFL6000AKP02V (1)
5962F1521601VXA
QML-V flight
Target
Tin
Notes:
(1) Contact ST sales office for information about the specific conditions for products in die form and other quality levels.
Contents
RHFL6000A
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Contents
1 Diagram ............................................................................................ 5
2 Pin configuration ............................................................................. 6
3 Maximum ratings ............................................................................. 8
4 Electrical characteristics ................................................................ 9
5 Typical application diagram ......................................................... 12
6 Radiations ...................................................................................... 13
6.1 Total ionizing dose (MIL-STD-883 test method 1019) ..................... 13
6.2 Heavy-ions ...................................................................................... 14
7 Additional guidelines for SET mitigation ..................................... 16
7.1 Ground connections ........................................................................ 16
7.2 Capacitor selection .......................................................................... 16
8 Device description ......................................................................... 17
8.1 ADJ pin ........................................................................................... 17
8.2 Inhibit ON-OFF control .................................................................... 17
8.3 Overtemperature protection ............................................................ 17
8.4 Overcurrent protection .................................................................... 17
8.5 OCM pin .......................................................................................... 17
8.6 STAB pin ......................................................................................... 18
8.7 FILT C pin ....................................................................................... 18
9 Application information ................................................................ 19
9.1 Notes on the 16-pin hermetic flat package ...................................... 20
9.2 FPGA supply ................................................................................... 20
10 Typical performance characteristics ........................................... 21
11 Package information ..................................................................... 26
11.1 FLAT-16P package information ....................................................... 26
12 Ordering information ..................................................................... 28
12.1 Traceability information ................................................................... 28
12.2 Documentation ................................................................................ 29
13 Revision history ............................................................................ 30
RHFL6000A
List of tables
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List of tables
Table 1: Device summary ........................................................................................................................... 1
Table 2: Pin description .............................................................................................................................. 7
Table 3: Absolute maximum ratings ........................................................................................................... 8
Table 4: Thermal data ................................................................................................................................. 8
Table 5: Electrical characteristics ............................................................................................................... 9
Table 6: TID tests results .......................................................................................................................... 13
Table 7: Heavy-ion results ........................................................................................................................ 14
Table 8: Bias configurations ..................................................................................................................... 15
Table 9: Test configurations ..................................................................................................................... 15
Table 10: Flat-16P package mechanical data .......................................................................................... 27
Table 11: Order code ................................................................................................................................ 28
Table 12: Date code.................................................................................................................................. 28
Table 13: Table of documentation by product .......................................................................................... 29
Table 14: Document revision history ........................................................................................................ 30
List of figures
RHFL6000A
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List of figures
Figure 1: Block diagram .............................................................................................................................. 5
Figure 2: Pin configuration (top view) ......................................................................................................... 6
Figure 3: Typical application diagram ....................................................................................................... 12
Figure 4: Heavy-ion test configuration ...................................................................................................... 14
Figure 5: Output voltage vs temperature .................................................................................................. 21
Figure 6: Output voltage vs temperature .................................................................................................. 21
Figure 7: Output voltage vs temperature .................................................................................................. 21
Figure 8: Output voltage vs temperature .................................................................................................. 21
Figure 9: Line regulation vs temperature .................................................................................................. 22
Figure 10: Load regulation vs temperature (IOUT = 5 mA to 400 mA) ....................................................... 22
Figure 11: Load regulation vs temperature (IOUT = 5 mA to 1 A, VIN = 2.5 V) ........................................... 22
Figure 12: Dropout voltage vs temperature (IOUT = 0.4 A) ........................................................................ 22
Figure 13: Dropout voltage vs temperature (IOUT = 1 A) ........................................................................... 23
Figure 14: Dropout voltage vs temperature (IOUT = 2 A) ........................................................................... 23
Figure 15: Quiescent current (OFF mode)................................................................................................ 23
Figure 16: Quiescent current .................................................................................................................... 23
Figure 17: Quiescent current (ON mode, IOUT = 1 A) ................................................................................ 24
Figure 18: Quiescent current (ON mode, IOUT = 2 A) ................................................................................ 24
Figure 19: Short-circuit current vs RSHORT ................................................................................................. 24
Figure 20: SVR vs frequency .................................................................................................................... 24
Figure 21: SVR vs frequency (T = 90 °C) ................................................................................................. 24
Figure 22: Turn-on transient ..................................................................................................................... 24
Figure 23: Turn-off transient ..................................................................................................................... 25
Figure 24: Line transient (IOUT = 0.8 A, VOUT = 3 V) .................................................................................. 25
Figure 25: Line transient (IOUT = 2 A, VOUT = 2.5 V) .................................................................................. 25
Figure 26: Load transient .......................................................................................................................... 25
Figure 27: Stability area for ceramic capacitor ......................................................................................... 25
Figure 28: Stability area for tantalum capacitor ........................................................................................ 25
Figure 29: Flat-16P package outline ......................................................................................................... 26
RHFL6000A
Diagram
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1 Diagram
Figure 1: Block diagram
bandgap
start-up/
curr.gen.
ON-OFF
control
overload prot.
thermal
shutdown
overcurrent
monitoring
antisaturating
stage
error
ampl. driver VO
VI
ADJ
STAB
FILT _C
OCM
R2 (ext.)
R1 (ext.)
ISC
A
B
A
B
INHIBIT
GIPD250620151147MT
Pin configuration
RHFL6000A
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2 Pin configuration
Figure 2: Pin configuration (top view)
The upper metallic package lid is connected to ground. The bottom metallization
is electrically floating.
GIPD250620151148MT
RHFL6000A
Pin configuration
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Table 2: Pin description
Pin name
FLAT-16P
Pin description
VO(1)
1, 2, 6, 7
Output port of the regulator.
VI(2)
3, 4, 5
Input port of the regulator.
GND
12, 13
Ground.
ISC
8
Current limit setting pin. Connect a resistor between this pin and
VI to set the current limit threshold.
OCM
10
Overcurrent monitor flag. Open collector, internally pulled up.
The signal on this pin goes to low logic level when the current limit
activates.
INHIBIT
14
Device Inhibit pin. Internally pulled-down.
The regulator is off when this pin is set at high logic level.
ADJ
15
Feedback pin. Connect to external resistor divider for output
voltage setting.
FILT C
9
Filter capacitor pin. An optional capacitor can be connected
between this pin and GND.
STAB
11
An optional R-C network can be connected between this pin and
GND to tune the internal control loop.
NC
16
Not internally connected.
Notes:
(1)All ouput pins must be connected together on the PCB.
(2)All input pins must be connected together on the PCB.
The upper metallic package lid is connected to ground. The bottom metallization
is electrically floating.
Maximum ratings
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3 Maximum ratings
Table 3: Absolute maximum ratings
Symbol
Parameter
Value
Unit
VI
DC input voltage, VI-VGROUND
-0.3 to 12
V
VO
DC output voltage range
-0.3 to (VI + 0.3)
V
VADJ
Adjustable pin voltage
-0.3 to (VO + 0.3)
V
IO
Continuous output current
2
A
VOCM
Over current monitor pin voltage vs GND
-0.3 to 12
V
VISC
Current limit pin voltage vs GND
-0.3 to 12
V
INHIBIT
Inhibit pin voltage
-0.3 to 12
V
STAB
Stability capacitor pin voltage
-0.3 to 2.5
V
FILT C
Filter capacitor pin voltage
-0.3 to 1.3
V
TSTG
Storage temperature range
-65 to +150
°C
TOP
Operating junction temperature range
-55 to +125
°C
ESD
Human body model (HBM)
2
kV
Machine model (MM)
200
V
Charged device model (CDM)
500
V
Absolute maximum ratings are those values beyond which damage to the device
may occur. Functional operation under these condition is not implied.
Table 4: Thermal data
Symbol
Parameter
Value
Unit
RthJC
Thermal resistance junction-case, FLAT-16P
8.3
°C/W
TSOLD
Maximum soldering temperature, 10 s
300
°C
RHFL6000A
Electrical characteristics
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4 Electrical characteristics
TJ = 25 °C, VI = 2.5 V, VO = VADJ, CI = CO = 10 µF (tantalum), unless otherwise specified.
Table 5: Electrical characteristics
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Operating
input voltage
IO = 1 A,
TJ = -55 to 125 °C
2.5
12
V
VADJ
Reference
voltage
IO = 5 mA to 1 A,
VO = Vadj,
TJ = -55 to 125 °C
1.205
1.245
1.285
V
ISHORT
Output current
limit (1)
Adjustable by external resistor
1
3
A
∆VO/∆VI
Line regulation
VI = 2.5 V to 12 V,
IO = 5 mA, TJ = +25 °C
0.1
0.4
%
VI = 2.5 V to 12 V,
IO = 5 mA, TJ = -55 °C
0.2
0.5
VI = 2.5 V to 12 V,
IO = 5 mA, TJ = +125 °C
0.08
0.35
∆VO/ ∆IO
Load
regulation
VI = 2.5 V,
IO = 5 to 400 mA,
TJ = +25 °C
0.02
0.4
%
VI = 2.5 V,
IO = 5 to 400 mA,
TJ = -55 °C
0.2
0.5
VI = 2.5 V,
IO = 5 to 400 mA,
TJ = +125 °C
0.03
0.3
VI = 2.5 V,
IO = 5 mA to 1 A,
TJ = +25 °C
0.3
0.5
VI = 2.5 V,
IO = 5 mA to 1 A,
TJ = -55 °C
0.3
0.6
VI = 2.5 V,
IO = 5 mA to 1 A,
TJ = +125 °C
0.3
0.6
VI = 2.5 V,
IO = 5 mA to 2 A,
TJ = -40 to 125 °C
0.6
VI = 3.0 V,
IO = 5 mA to 2 A,
TJ = -55 to -40 °C
Electrical characteristics
RHFL6000A
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DocID028379 Rev 5
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
ZOUT
Output
impedance
IO = 100 mA DC and 20 mA rms
100
mΩ
Iq
Quiescent
current (2)
ON mode
VI = 2.5 V to 12 V, IO = 5 mA,
TJ = +25 °C
7
mA
VI = 2.5 V to 12 V, IO = 30 mA,
TJ = +25 °C
7
VI = 2.5 V to 12 V, IO = 300 mA,
TJ = +25 °C
30
VI = 2.5 V to 12 V, IO = 1 A,
TJ = +25 °C
60
VI = 2.5 V to 12 V, IO = 30 mA,
TJ = -55 °C
7
VI = 2.5 V to 12 V, IO = 300 mA,
TJ = -55 °C
35
VI = 2.5 V to 12 V, IO = 1 A,
TJ = -55 °C
80
VI = 2.5 V to 12 V, IO = 30 mA,
TJ = +125 °C
7
VI = 2.5 V to 12 V, IO = 300 mA,
TJ = +125 °C
30
VI = 2.5 V to 12 V, IO = 1 A,
TJ = +125 °C
60
IqOFF
Quiescent
current
OFF mode
VI = 2.5 V, VINH = 2.4 V,
OFF mode,
TJ = -55 to +125 °C
0.2
1
mA
Vd
Dropout
voltage
IO = 400 mA, VO = 2.5 to 9 V,
(+25 °C)
300
450
mV
IO = 400 mA, VO = 2.5 to 9 V,
(-55 °C)
250
400
IO = 400 mA, VO = 2.5 to 9 V,
(+125 °C)
350
550
IO = 1 A, VO = 2.5 to 9 V, (+25 °C)
570
800
IO = 1 A, VO = 2.5 to 9 V, (-55 °C)
470
700
IO = 1 A, VO = 2.5 to 9 V,
(+125 °C)
700
900
IO = 2 A, VO = 2.5 to 9 V, (+25 °C)
550
IO = 2 A, VO = 2.5 to 9 V, (-55 °C)
500
IO = 2 A, VO = 2.5 to 9 V,
(+125 °C)
700
RHFL6000A
Electrical characteristics
DocID028379 Rev 5
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Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VINH(ON)
Inhibit voltage
IO = 5 mA, TJ = -55 to +125 °C
0.8
V
VINH(OFF)
Inhibit voltage
IO = 5 mA, TJ = -55 to +125 °C
2.4
SVR
Supply voltage
rejection (3)
VI = VO + 2.5 V ± 0.5 V,
VO = 3 V IO = 5 mA
f = 120 Hz
60
70
dB
f = 33 Hz
30
40
ISH
Shutdown
input current
VINH = 5 V
15
µA
VOCM
OCM pin
voltage
Sinked IOCM = 24 mA active low
0.38
V
tPLH
Inhibit
propagation
delay,
turn-off (3)
VI = VO + 2.5 V,
VINH = from 0 V to 2.4 V,
IO = 400 mA ,
VO = 3 V, CI = CO = 10 µF
30
µs
tPHL
Inhibit
propagation
delay,
turn-on (3)
VI = VO + 2.5 V,
VINH = from 2.4 V to 0 V,
IO = 400 mA ,
VO = 3 V,
CI = CO = 10 µF
100
µs
eN
Output noise
voltage (3)
B = 10 Hz to 100 kHz,
IO = 5 mA to 2 A
40
µVrms
Notes:
(1)These values are guaranteed by design. For each application it is strongly recommended to comply with the
maximum current limit of the package used.
(2) See Table 6: "TID tests results".
(3)These values are guaranteed by design.
Typical application diagram
RHFL6000A
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5 Typical application diagram
Figure 3: Typical application diagram
RHFL6000A
Radiations
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6 Radiations
6.1 Total ionizing dose (MIL-STD-883 test method 1019)
The products that are guaranteed in radiation within RHA QML-V system, fully comply with
the MIL-STD-883 test method 1019 specification. The RHFL6000A is being RHA QML-V
qualified, tested and characterized in full compliance with the MIL-STD-883 specification,
both below 10 mrad/s (low dose rate) and between 50 and 300 rad/s (high dose rate).
Testing is performed in accordance with MIL-prf-38535 and the test method 1019 of
the MIL-STD-883 for total ionizing dose (TID).
ELDRS characterization is performed in qualification only on both biased and
unbiased parts, on a sample of ten units from two different wafer lots.
Each wafer lot is tested at high dose rate only, in the worst bias case condition, based
on the results obtained during the initial qualification.
Table 6: TID test results
Type
Conditions
Value
Unit
TID
50 rad(Si)/s high dose rate up to
300
krad
10 mrad(Si)/s low dose rate up to (1)
100
ELDRS free up to (1)
100
Output voltage radiation drift
From 0 krad to 300 krad at 50 rad/s,
MIL-STD-883J method 1019.9
<1.1
ppm/krad
Quiescent current (ON-state)
From 0 krad to 300 krad at 50 rad/s ,
MIL-STD-883J method 1019.9
VI = 2.5 V to 12 V,
IO = 5 to 30 mA,
TJ = -55 to +125 °C
<15
mA
Notes:
(1)300 krad low dose rate test ongoing.
Radiations
RHFL6000A
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6.2 Heavy-ions
The heavy-ion trials are performed on qualification lots only. No additional test is
performed. Table below summarizes the results of heavy ions tests.
Table 7: Heavy-ion results
Feature
Conditions
Value
Unit
SEL/B performance
LET = 120 MeV*cm2/mg VI = 12 V
No latch-up/burn-out
-
SET performance
during events
LET = 32 MeV*cm2/mg
Saturated cross-section = 6.18*10-5 cm²
VIN up to 9 V
VI - VO ≤ 7.5 V
IOUT < 300 mA
± 15% max. over less
than 300 ns
% of VO
LET = 120 MeV*cm2/mg
VIN up to 12 V
VI - VO < 3.0 V
IOUT < 300 mA
No SET above ± 3%
LET = 120 MeV*cm2/mg
VIN up to 4 V
VI - VO < 1.5 V
IOUT < 1 A
No SET above ± 3.3%
SEL and SET performances described here below are related to the circuit configuration
and bias conditions shown in Figure 4: "Heavy Ion test configuration" and Table 8: "Bias
configurations" and Table 9: "Test configurations".
Figure 4: Heavy-ion test configuration
RHFL6000A
Radiations
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Table 8: Bias configurations
Test mode
Bias conditions
SEL
VIN = 12 V, VOUT = 9 V, VINHIBIT= 0 V, IOUT = 5 mA
SET
VIN = 3 V, VOUT = 1.5 V, VINHIBIT= 0 V, IOUT = 1 mA
VIN = 9 V, VOUT = 0 V, VINHIBIT= 9 V, IOUT = 0 mA
VIN = 4 V, VOUT = 2.5 V, VINHIBIT = 0 V, IOUT = 1 A
VIN = 7 V, VOUT = 5 V, VINHIBIT = 0 V, IOUT = 300 mA
VIN = 12 V, VOUT = 9 V, VINHIBIT = 0 V, IOUT = 300 mA
Table 9: Test configurations
Test mode
Test configurations
SEL
Sel configuration
CIN1 = 100 µF
COUT1 = COUT2 = 47 µF
CIN2 = COUT4 = COUT5 = 100 nF
Cbyp = 47 nF
Cfilt = 22 nF
RISC = 8.2 kΩ
Rload = 1.8 kΩ
SET
SET 1
CIN1 = 100 µF
COUT1 = COUT2 = 47 µF
CIN2 = COUT4 = COUT5 = 100 nF
Cbyp = 47 nF
Cfilt = 22 nF
RISC = 8.2 kΩ
Rload = depending on bias conditions
SET 2
CIN1 = COUT1 = 220 µF
COUT5 = COUT2 = not connected
CIN2 = COUT4 = 100 nF
Cbyp = 47 nF
Cfilt = 22 nF
RISC = 8.2 kΩ
Rload = depending on bias conditions
Additional guidelines for SET mitigation
RHFL6000A
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7 Additional guidelines for SET mitigation
This section provides detailed design guidelines necessary to obtain the required
performance against SET. In this respect, we can identify two main areas for intervention:
ground connection and external components selection.
7.1 Ground connections
To achieve the best performance in terms of output voltage accuracy, noise immunity and
robustness against single event effects, it is recommended to implement a proper PCB
layout by following the suggestions described below.
According to qualitative simulations of single events, some very short SET (i.e., a duration
in the 100 ns range) are strongly dependent on the stray inductances versus GND. The
best solution to reduce the parasitic inductance is the adoption of a GND plane (with
separate power and sense paths where possible). By minimizing the stray GND
impedance, this approach is of great assistance in controlling the amplitude of the SET
events near the load.
If this solution is not applicable, we suggest using a star-bus topology, where the PCB
reference GND connection is close to the GND pin of the regulator.
To achieve a good GND sense, it is necessary to comply with the following rules:
connect the regulator GND pin and load GND node both to the sense and power GND
traces on the PCB using vias to minimize the path;
an array of multiple via structures works better than a single large one;
for GND connectors/plugs: use separate plugs for power supply and testing probes;
connect input/output capacitors GND terminals to GND sense on the PCB.
7.2 Capacitor selection
With reference to Figure 4: "Heavy Ion test configuration", a combination of capacitors must
be present on the input and output ports. For the INPUT terminals, this may consist of a
100 µF bulk capacitor (CIN1) in parallel with a polyester 100 nF one (CIN2) used for
decoupling purposes.
For each of the two OUTPUT connections (pins 1, 2 and 6, 7) we suggest using a
combination of a 47µF bulk capacitor (COUT1, COUT2,) in parallel with a polyester 100 nF one
(COUT4, COUT5) for decoupling purposes.
Regarding parts selection, for the 100 nF elements we suggest low-ESL and low ESR
capacitors.
Concerning the selection of the three bulk capacitors, we suggest:
using tantalum SMD;
selecting size and ESL as small as possible;
placing capacitors as close as possible to the input/output terminals;
using an array of capacitors in parallel, where possible. This works better than a single
capacitor against the short events.
RHFL6000A
Device description
DocID028379 Rev 5
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8 Device description
The RHFL6000A adjustable voltage regulator contains a PNP type power element
controlled by a signal resulting from an amplified comparison between the internal
temperature-compensated band-gap and the fraction of the desired output voltage value
obtained from an external resistor divider bridge. The device is protected by several
functional blocks.
8.1 ADJ pin
The feedback voltage necessary for the loop regulation comes from the load through an
external resistor divider (R1, R2 as in Figure 3: "Typical application diagram") whose mid
point is connected to the ADJ pin (allowing all possible output voltage settings as per user
requirements).
8.2 Inhibit ON-OFF control
By setting the INHIBIT pin to TTL high level, the device switches off. The device is in ON
state when the INHIBIT pin is set low. Since the INHIBIT pin is pulled down internally, it can
be left floating whenever the inhibit function is not used.
8.3 Overtemperature protection
A temperature detector internally monitors the power element junction temperature. The
device turns off when a temperature of approximately 175 °C is reached, returning to ON
mode when the temperature decreases down to approximately 135 °C.
It should be noted that when the internal temperature detector reaches 175 °C, the active
power element can be as high as 225 °C. Prolonged operation under these conditions may
exceed the maximum operating ratings and device reliability cannot be guaranteed.
8.4 Overcurrent protection
A default internal costant current limit is set at ISHORT = 3 A (when VO is at 0 V).
This value can be decreased via an external resistor (RSHORT) connected between the ISC
and VI pins, with a typical value range of 10 kΩ to 200 kΩ.
To maintain optimal regulation, it is necessary to set ISHORT 1.6 times greater than the
desired maximum operating current (IO). When IO reaches ISHORT–300 mA, the current
limiter intervenes, VO starts to drop and the OCM flag is raised. When no current limitation
adjustment is required, the ISC pin must be left unbiased.
The combination of overcurrent and overtemperature circuits provides the RHFL6000A with
a high level of protection against destructive junction temperature excursions in all load
conditions.
8.5 OCM pin
The OCM pin is an open collector flag normally pulled up at VI by a 5 kΩ resistor.
It goes to low state when the current limit becomes active. It is buffered and can sink
10 mA.
Device description
RHFL6000A
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DocID028379 Rev 5
8.6 STAB pin
The STAB pin gives user direct access to regulator internal control loop stability
adjustment. Its usage is optional and it should be left unconnected when not used.
8.7 FILT C pin
The FILT C pin helps reduce SET rate when bypassed to GND through a 22 nF ceramic
capacitor. Its usage is optional and it should be left unconnected when not used.
RHFL6000A
Application information
DocID028379 Rev 5
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9 Application information
To adjust the output voltage, the R2 resistor must be connected between the VO and ADJ
pins. The R1 resistor must be connected between ADJ and ground. Resistor values can be
derived from the following formula:
where
The minimum output voltage is therefore VADJ and minimum input voltage is 2.5 V.
The RHFL6000A operates correctly when the VI - VO voltage difference is slightly above
the power element saturation voltage (Vd, dropout voltage).
A minimum load current of 0.5 mA must be set to ensure proper regulation under no-load
condition. It is advisable to make this current flow into the resistor divider.
For this reason, we suggest selecting an R1 value not higher than 10 kΩ.
The RHFL6000 FLAT-16 package offers multiple input and output pins.
All of the available VI pins should always be externally interconnected. The same must be
applied to all the available VO pins, otherwise the stability and reliability of the device
cannot be guaranteed.
The inhibit function switches off the output current very quickly. According to Lenz’s Law,
external circuitry reacts with LdI/dt terms which can be of high amplitude in case of serial
inductive elements or large stray PCB inductance. Large transient voltage would develop
on both device terminals. It is advisable to protect the device output with Schottky diodes to
prevent negative voltage excursions. A14 V Zener diode could protect the device input.
The input and output capacitors must be connected as close as possible to the device
terminals.
Since the RHFL6000A voltage regulator is manufactured with very high speed bipolar
technology (6 GHz fT transistors), the PCB layout must be designed with exceptional care,
with very low inductance and low mutually coupling lines. Otherwise, high frequency
parasitic signals may be picked up by the device resulting in system self-oscillation.
On the other hand, the benefit of this technology is SVR performance extended to high
frequencies.
VO= VADJ (R1+ R2) / R1
ADJ = 1.248 V typ.
V
Application information
RHFL6000A
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9.1 Notes on the 16-pin hermetic FLAT package
The RHFL6000A adjustable voltage regulator is available in a high thermal dissipation 16-
pin hermetic FLAT package, whose bottom flange is metallized to allow direct soldering or
gluing to a heat sink (efficient thermal conductivity). The upper metallic package lid is
connected to ground. The bottom metallization is electrically floating.
9.2 FPGA supply
FPGA devices are very sensitive to VDD transients beyond a few % of their nominal supply
voltage (usually 1.5 V).
The RHFL6000A includes specific integrated circuitry designed to absorb the output
transients under heavy ion beams, rendering it suitable for safe FPGA supply operation.
RHFL6000A
Typical performance characteristics
DocID028379 Rev 5
21/31
10 Typical performance characteristics
(CIN = COUT = 10 µF tantalum, unless otherwise specified)
Figure 5: Output voltage vs temperature
(VIN = 2.5 V, IOUT = 5 mA)
Figure 6: Output voltage vs temperature
(VIN = 2.5 V, IOUT = 400 mA)
Figure 7: Output voltage vs temperature
(VIN = 2.5 V IOUT = 1 A)
Figure 8: Output voltage vs temperature
(VIN = 2.5 V IOUT = 2 A)
GIPD240620151357MT
1.18
1.19
1.2
1.21
1.22
1.23
1.24
1.25
1.26
1.27
1.28
-55 -40 -25 0 25 55 85 125
Temperature ºC
Output voltage
GIPD240620151216MT
1.18
1.19
1.2
1.21
1.22
1.23
1.24
1.25
1.26
1.27
1.28
-55 -40 -25 0 25 55 85 125
Temperature ºC
Output voltage
GIPD240620151155MT
1.18
1.19
1.2
1.21
1.22
1.23
1.24
1.25
1.26
1.27
1.28
-55 -40 -25 0 25 55 85 125
Temperature ºC
Output voltage
GIPD240620151148MT
1.18
1.19
1.2
1.21
1.22
1.23
1.24
1.25
1.26
1.27
1.28
-55 -40 -25 0 25 55 85 125
Temperature ºC
Output voltage
Typical performance characteristics
RHFL6000A
22/31
DocID028379 Rev 5
Figure 9: Line regulation vs temperature
Figure 10: Load regulation vs temperature
(IOUT = 5 mA to 400 mA)
Figure 11: Load regulation vs temperature
(IOUT = 5 mA to 1 A, VIN = 2.5 V)
Figure 12: Dropout voltage vs temperature
(IOUT = 0.4 A)
GIPD240620151125MT
0
0.1
0.2
0.3
0.4
0.5
0.6
-55 25 125
Temperature ºC
0.7
0.8
Loadregulation [%]
GIPD290620151104MT
0
100
200
300
400
500
600
100
Temperature ºC
120 140
-80 -60 -40 -20 020 40 60 80
DropoutVoltage[mV]
Vout=9V
Vout=2.5V
RHFL6000A
Typical performance characteristics
DocID028379 Rev 5
23/31
Figure 13: Dropout voltage vs temperature
(IOUT = 1 A)
Figure 14: Dropout voltage vs temperature
(IOUT = 2 A)
Figure 15: Quiescent current (OFF mode)
Figure 16: Quiescent current
(ON mode, IOUT = 5 mA)
GIPD240620151103MT
0
100
200
300
400
500
600
100
Temperature ºC
120 140
-80 -60 -40 -20 020 40 60 80
700
800
900
1000
DropoutVoltage[mV]
Vout=9V
Vout=2.5V
GIPD230620151454MT
500
600
700
800
900
1000
100
Temperature ºC
120 140
-80 -60 -40 -20 020 40 60 80
1400
DropoutVoltage [mV]
1500
1600
1300
1200
1100
400
Vout=9V
Vout=2.5V
GIPD230620151442MT
500
600
700
800
900
100
Temperature ºC
120 140
-80 -60 -40 -20 020 40 60 80
1000
400
100
200
300
0
Iq off [ uA]
VIN = 2.5 V, VINH = 2.4 V
GIPD230620151432MT
0.005
0.006
0.007
0.008
100
Temperature ºC
120 140
-80 -60 -40 -20 020 40 60 80
0.004
0.001
0.002
0.003
0
Iq [A]
VIN = 2.5 V
Typical performance characteristics
RHFL6000A
24/31
DocID028379 Rev 5
Figure 17: Quiescent current (ON mode, IOUT = 1 A)
Figure 18: Quiescent current (ON mode, IOUT = 2 A)
Figure 19: Short-circuit current vs RSHORT
Figure 20: SVR vs frequency
Figure 21: SVR vs frequency (T = 90 °C)
Figure 22: Turn-on transient
GIPD230620151152MT
0.005
0.006
Temperature ºC
125
-55 -25 025 55 85
0.004
0.001
0.002
0.003
0
Iq [A]
VIN = 2.5 V
GIPD260620151051MT
0.05
0.06
Temperature ºC
125
-55 -25 025 55 85
0.04
0.01
0.02
0.03
0
Iq [A]
VIN = 2.5 V
0.07
0.08
0.09
0.1
0.11
0.12
GIPD230620151141MT
1.5
2
040
0.5
1
0
ISHORT [A]
2.5
3
3.5
4
RSH [Kohm]
10 20 6030 50 10070 80 12090 110 130 140 150
VEN to Gnd, C
IN=COUT=1µF, VIN=6V, Vout in short circuit condition
GIPD230620151129MT
100
10
20
0
SVR[dB]
Frequency[Hz]
1000 10000 100000
VIN = from 5 to 6V, VOUT=3V, IOUT=5mA, C
IN=COUT=1µF tantalum
30
40
60
70
80
90
50
100
GIPD230620151047MT
100
10
20
0
SVR[dB]
Frequency[Hz]
1000 10000 100000
VIN = from 3.5 to 4.5V, CIN=COUT=1µF tantalum,T=90°C, V
OUT=2.5V
30
40
60
70
80
90
50
100
Iout=5mA
Iout=1A
RHFL6000A
Typical performance characteristics
DocID028379 Rev 5
25/31
Figure 23: Turn-off transient
Figure 24: Line transient (IOUT = 0.8 A, VOUT = 3 V)
Figure 25: Line transient (IOUT = 2 A, VOUT = 2.5 V)
Figure 26: Load transient
Figure 27: Stability area for ceramic capacitor
Figure 28: Stability area for tantalum capacitor
Package information
RHFL6000A
26/31
DocID028379 Rev 5
11 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
11.1 FLAT-16P package information
Figure 29: FLAT-16P package outline
8241681_4
RHFL6000A
Package information
DocID028379 Rev 5
27/31
Table 10: FLAT-16P package mechanical data
Dim.
mm
Inch
Min.
Typ.
Max.
Min.
Typ.
Max.
A
2.42
2.88
0.095
0.113
b
0.38
0.48
0.015
0.019
c
0.10
0.18
0.004
0.007
D
9.71
10.11
0.382
0.398
E
6.71
7.11
0.264
0.280
E2
3.30
3.45
3.60
0.130
0.136
0.142
E3
0.76
0.030
e
1.27
0.050
L
6.35
7.36
0.250
0.290
Q
0.66
1.14
0.026
0.045
S1
0.13
0.005
Ordering information
RHFL6000A
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DocID028379 Rev 5
12 Ordering information
Table 11: Order code
Part number
SMD pin
Quality
level
EPPL
Package
Lead
finish
Marking (1)
Packing
RHFL6000AKP1
-
Engineering
model
-
FLAT-16P
Gold
RHFL6000KPA1
Strip
pack
RHFL6000AKP01V
5962F1521601VXC
QML-V
flight
Target
FLAT-16P
Gold
5962F1521601VXC
Strip
pack
RHFL6000AKP02V
5962F1521601VXA
QML-V
flight
Target
FLAT-16P
Tin
5962F1521601VXA
Strip
pack
Notes:
(1)Specific marking only. The full marking includes in addition:
- for the engineering models : ST logo, date code, country of origin (FR)
- for QML flight parts : ST logo, date code, country of origin (FR), manufacturer code (CSTM), serial number of
the part within the assembly lot.
Contact ST sales office for information about the specific conditions for:
1) Products in die form
2) Other quality levels
3) Tape and reel packing
12.1 Traceability information
Date code in formation is structured as described below:
Table 12: Date code
Model
Date code
EM
3yywwN
QML flight
yywwN
where:
yy = year
ww = week number
N = lot index in the week
RHFL6000A
Ordering information
DocID028379 Rev 5
29/31
12.2 Documentation
The table below gives a summary of the documentation provided with each type of
products:
Table 13: Table of documentation by product
Quality level
Documentation
Engineering model
-
QML-V flight
Certificate of conformance (including group C and D reference)
Precap report (100% high and low magnification)
SEM report
Screening summary
Group A summary (quality conformance inspection of electrical tests)
Group B summary (quality conformance inspection of mechanical tests)
Group E (quality conformance inspection of wafer lot radiation verification test)
Revision history
RHFL6000A
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DocID028379 Rev 5
13 Revision history
Table 14: Document revision history
Date
Revision
Changes
21-Sep-2015
1
First release.
12-Oct-2015
2
Updated Table 7: "Heavy ions results".
Minor text changes.
15-Feb-2016
3
Document status promoted from preliminary data to production data.
Updated Table 1: "Device summary" and Table 11: "Order code".
Minor text changes.
14-Apr-2016
4
Updated Table 5: "Electrical characteristics".
Minor text changes.
05-Dec-2017
5
Updated the description in cover page.
Minor text changes.
RHFL6000A
DocID028379 Rev 5
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