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PRELIMINARY DATA
December 2001
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PSD4235G2
Flash In-System Programmable (ISP) Peripherals
For 16-bit MCUs (5V Supply)
FEATURES SUMMARY
PSD provides an integrat ed solution to 16-bit MCU
based applications that includes configurable
memories, PLD logic and I/O:
■Dual Bank Flash Mem ories
– 4 Mbit of Primary Flash Memory (8 uniform
sectors, 32K x 16)
– 256 Kbit Secondary Flash Memory with 4
sectors
– Conc urrent operation: read from one memory
while erasing and writing the other
■64 Kbit SRAM (Battery Backed)
■PLD wi th macrocells
– Over 3000 Gates of PLD: CPLD and DPLD
– CPLD with 16 Output Macrocells (OMCs) and
24 Input Macrocells (I MCs)
– DPLD – user d efined in ternal chip select de-
coding
■Seven l/ O Ports with 52 I/O pins
– 52 individually conf igurable I / O port p ins that
can be used for the following functions:
– MCU I/Os
–PLD I/Os
– Latched MCU address output
– Special function l/Os
– l/O ports may be configured as open-drain
outputs
■In-System Programmi ng (ISP) with JTAG
– Built-in JTAG compl iant s erial por t allows full-
chip In-Sy stem Programmability
– Efficient manufacturing allow easy product
testing and program mi ng
– Use low cost FlashLINK cable with PC
■Page Register
– Internal page register that can be used to ex-
pand the microcont roller address space by a
facto r of 256
■Program mable power man agem ent
■High Endurance:
– 100,000 Erase/Write Cycles of Flash Memory
– 1,000 Eras eWrite Cycles of PLD
– 15 Year Data Retention
■Single Supply Voltage
–5V ±10%
■Memo ry Speed
– 70ns Fl ash memory and SRAM access time
Figure 1. Packages
TQFP80 (U)
PSD4235G2
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TABLE OF CONT ENTS
Summary Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
In-System Programming (ISP) via JTAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
In-Application Programming (IAP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PSDsoft Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PSD Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
MCU Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
ISP via JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
In-System Programming (ISP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
In-Application Programming (IAP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Powe r Manage ment Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Developm ent System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1
PSD Register Description and Address Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Register Bit Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Detailed Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Memory Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
R eading Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3
Programming Flash Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Erasing Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Flash Memory Sector Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8
SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Mem ory Select Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Page Re gister . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0
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PSD4235G2
Memory ID Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1
PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Decod e PLD (DPLD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
MCU Bus Interfa ce. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Port Operating M odes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Ports A, B and C – Func tionality and Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Port D – Functionality and Stru cture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Port E – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7
Port F – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8
Port G – Functi onality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
PLD Power Managem ent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Power On Reset, Warm Reset and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Programming In-Circuit using the JTAG Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Initial Deliv ery State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
AC/DC Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table. Absolute M aximum Ra tings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Table. Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table. CPLD Combinatorial Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Table . CPLD M acroc ell Synchronous Clock Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table . CPLD M acroc ell Asynchronous Clock Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table. Input Macrocell Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table . Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table. Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table . Port F P eripheral Data Mode Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table . Port F P eripheral Data Mode Write Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table. Reset (Reset)Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table. VSTBYON T iming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2
Table. Program, Write and Erase Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table. ISC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table. Power-down Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4
PSD4235G2
4/89
Package Mechani cal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table . TQFP 80 - 80 lead Plastic Quad Flatpac k. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table . Pin Assign ments – T QFP80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
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PSD4235G2
SUMMARY DESCRIPTION
The PSD f amily o f memory syst e ms for micro co n-
trollers (MCUs) bri n gs I n-System-Programmabi l ity
(ISP) to Flash memory and programmable logic.
The result is a simple and flexible solution for em-
bedded designs. PSD devices combine many of
the peripheral functions found in MCU based ap-
plications.
PSD devices integrate an optimized Macrocell log-
ic architecture. The Macrocell was created to ad-
dress the unique requirements of embedded
system designs. It allows direct connection be-
tween the system address/ data bus, and the int er-
nal PSD registers, to simplify communication
between the MCU and other supporting devices .
Table 1. Pi n Names
The PSD family offer s two methods to program the
PSD Flash memory w hile the PSD is soldered to
the circuit board: In-System Programming (ISP)
via JTAG, and In-Appli cation Programming (IAP).
In-System Pr ogrammi ng (ISP) via JTAG
An IEEE 1149.1 compliant JTAG In-System Pro-
gramming (ISP) interface is included on the PSD
enabling the en tire dev ice (Flas h m emories, PLD,
configuration) to be rapidly programmed whi le sol -
dered to the circuit board. This requires no MCU
participation, which means the PSD can be pro-
grammed anytime, even when com pletely blank.
The innovative J T AG interface to Flash mem ories
is an industry first, solving key prob lems faced by
designers and manuf acturin g houses, such as:
Figure 2. Logic Diagram
First time programming. How do I ge t firmware
into the Flash memory the very first time? JTAG is
the answer . Program the blank PSD with no MCU
involvement.
Inventory build-up of pre-programmed devic-
es. How do I maintain an accurate count of pre-
programmed Flash memory and PLD devices
based on customer demand? How many and what
version? JTAG is t he answer. Build your hardware
with blank PSDs soldered directly to the board and
then custom program just before they are shipped
to the custome r. N o more labels on chips, and no
more wasted inventory.
Expensive sockets. How do I eliminate the need
for expensive and unreliable sockets? JTAG is the
answer. Solder the PSD directly to the circuit
board. Program first time and subsequent times
with JTAG. No need to handle devices and b end
the fragile leads.
PA0-PA7 Port-A
PB0-PB7 Port-B
PC0-PC7 Port-C
PD0-PD3 Port-D
PE0-PE7 Port-E
PF0-PF7 Port-F
PG0-PG7 Port-G
AD0-AD15 Address/Data
CNTL0-CNTL2 Control
RESET Reset
VCC Supply Voltage
VSS Ground
AI04916
16
AD0-AD15
PF0-PF7
VCC
PSD4xxxGx
VSS
8
PG0-PG7
8
PB0-PB7
8
PA0-PA7
8
3
CNTL0-
CNTL2
RESET
PD0-PD3
4
PC0-PC7
8
PE0-PE7
8
PSD4235G2
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Figu re 3. T QFP Conn ec ti ons
In - A ppl i ca tio n P r og ra m ming (IA P)
Two independent Flash memory arrays are includ-
ed so that the MCU can execute code from one
while erasing a nd program m ing the o the r. Robust
product firm ware updat es in the f iled are possible
over any communication channel (CAN, Ethernet,
UART, J1850, e tc) using this unique architec ture.
Designers are relieved of these problems:
Simultaneous read and write to Flash memo-
ry. How can the MCU program the same memory
from which it execut ing cod e? It c anno t. The P SD
allows the MCU t o operate t he tw o Flash me mory
blocks concurren tly, reading code from one while
erasing and programm ing the other during IAP.
Compl ex memory mappi ng. How can I map
these two m emories efficiently? A programmable
Decode PLD (DPLD) is embedded in the PSD.
The concurrent PSD memories can be mapped
anywhere in MCU address space, segment by
segment with extermely high address resolution.
As an option, t he secondary Flash memory can be
swapped out of the system memory map when
IAP is complete. A built-in page register breaks the
MCU a ddress lim it .
Separa te Program an d Data space. How can I
write to Flash m em ory while it reside s in Program
space during field firmware updates? My
80C51XA will not allow it. The PSD provides
means t o reclassify F lash m em ory as Data space
during IAP, then back to Program space when
complete.
60 CNTL1
59 CNTL0
58 PA7
57 PA6
56 PA5
55 PA4
54 PA3
53 PA2
52 PA1
51 PA0
50 GND
49 GND
48 PC7
47 PC6
46 PC5
45 PC4
44 PC3
43 PC2
42 PC1
41 PC0
PD2
PD3
AD0
AD1
AD2
AD3
AD4
GND
VCC
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PD1
PD0
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
GND
VCC
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
VCC
GND
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
RESET
CNTL2
AI04943
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PSD4235G2
PSDsoft Express
PSDsoft Express, a software development tool
from ST, guides you through the design process
step-by-step making it possible to complete an
embedded MCU design capabl e of I SP/IAP in just
hours. Select your MCU and PSDsoft Express
takes you through the remainder of the design with
point and click entry, covering PSD selection, pin
definitions, programmable logic inputs and outpus,
MCU memory map definition, ANSI-C code gener-
ation for your MCU, and merging your MCU firm-
ware with the PSD design. When complete, two
different device programmers are supported di-
rectly from PSDsoft Express: FlashLINK (JTAG)
and PSDpro.
Figure 4 . PSD Block Diagram
Note: Additional address lines can be brought in to the device via Por t A, B , C, D or F.
PROG.
MCU BUS
INTRF.
ADIO
PORT
CNTL0,
CNTL1,
CNTL2
AD0 – AD15
CLKIN
CLKIN
CLKIN
PLD
INPUT
BUS
PROG.
PORT
PORT
A
PROG.
PORT
PORT
B
POWER
MANGMT
UNIT
4 MBIT PRIMARY
FLASH MEMORY
16 SECTORS
VSTDBY
PA0 – PA7
PB0 – PB7
PROG.
PORT
PORT
C
PROG.
PORT
PORT
D
PC0 – PC7
PD0 – PD3
ADDRESS/DATA/CONTROL BUS
PORT A & B
8 EXT CS TO PORT C or F
24 INPUT MACROCELLS
PORT A ,B & C
82
82
256 KBIT SECONDARY
FLASH MEMORY
(BOOT OR DATA)
4 SECTORS
64 KBIT BATTERY
BACKUP SRAM
RUNTIME CONTROL
AND I/O REGISTERS
SRAM SELECT
PERIP I/O MODE SELECTS
MACROCELL FEEDBACK OR PORT INPUT
CSIOP
FLASH ISP CPLD
(CPLD) 16 OUTPUT MACROCELLS
FLASH DECODE
PLD (DPLD)
PLD, CONFIGURATION
& FLASH MEMORY
LOADER
JTAG
SERIAL
CHANNEL
(PE6)
PAGE
REGISTER EMBEDDED
ALGORITHM
SECTOR
SELECTS
SECTOR
SELECTS
GLOBAL
CONFIG. &
SECURITY
AI04990
8
PROG.
PORT
PORT
E
PE0 – PE7
PORT F
PROG.
PORT
PORT
F
PF0 – PF7
PROG.
PORT
PORT
G
PG0 – PG7
PSD4235G2
8/89
PSD ARCHITECTURAL OVERVIEW
PSD devices contain several major functional
blocks. Figure 4 shows the archi tecture of the PSD
device family. The funct ions of each blo ck are de-
scribed briefly in the following sections. Many of
the blocks perform multiple functions and are user
configurable.
Memory
Each of the memory blocks is briefly discussed in
the following paragrap hs. A m ore det ailed di scus-
sion can be found in the section ent itled “Memory
Blocks“ on page 20.
The 4 Mbit primary Flash memory is the main
memory of the PSD. It is divided into 8 equally-
sized sectors that are individually selec table.
The 256 Kbit secondary F lash m emory i s divided
into 4 equally-sized sectors. Each sector is individ-
ually selectable.
The 64 Kbit SRAM is intended for use as a
scratch-pad memory or as an extension to the
MCU SRAM. If an external battery is connected to
the PSD’ s Voltage Stand-by (VSTBY, PE6) signal,
data is retained in the event of pow er failure.
Each memory block can be located in a different
address space as defined by the user. The access
times for all memory types includes the address
latching and DPLD decoding time.
PLDs
The device contains two PLD blocks, the Decode
PLD (DPLD) and the Complex PLD (CPLD), as
shown in Table 2, each optimized for a different
function. The functional partitioning of the PLDs
reduces power consumption, optimizes cost/per-
formance, and eases design ent ry.
The DPLD is used to decode addresses and to
generate Sector Sel ect signals for the PSD inter-
nal memory a nd regis ters. Th e DPLD has combi-
natorial outputs, while the CPLD can implement
more general user-defined logic functions. The
CPLD has 16 Output Macrocells (OMC) and 8
com binatorial output s. The PSD also has 24 Input
Macrocells (IMC) that can be configured as i nputs
to the PLDs. The PLDs receive their inputs from
the PLD Inp ut Bus and are di fferentiated by their
output destinat i ons, number of product terms, and
Macrocells.
The PLDs consume minimal power. The speed
and power consumption of the PLD is controlled
by the Turbo bit in PMMR0 and other bits in
PMMR2. These registers are set by the MCU at
run-time. There is a slight penalty to PLD pr opaga-
tion time when not in the Turbo mode.
I/O Port s
The PSD has 52 I/O pins divided among seven
ports (Port A, B, C, D, E, F and G). Each I/O pin
can be individually configured for different func-
tions. Ports can be configured as standard MCU I /
O ports, PLD I/O, or latched address outputs for
MCUs using multiplexed address/data bus es
The JTAG pins can be enabled on Port E for In-
System Program ming (ISP ).
Table 2. PLD I/O
MCU Bus Inter face
The PSD e asily interfaces easily with most 16-bit
MCUs, either with multiple xe d or non -multiplexed
address/data buses. The device is configured to
respond t o the MCU’ s control pins, which are also
used as inputs to the PLDs.
I SP vi a JTA G Port
In-System Programming (ISP) can be performed
through the J TAG signals on Port E. This serial i n-
terface allows compl ete progr ammi ng of t he entire
PSD device. A blank device can be completely
programmed. The JTAG signals (TMS, TCK,
TSTAT, TERR, TDI, TDO) can be multiplexed with
other functions on Port E. Table 3 indicates the
JTAG pin assignment s .
In-Sy stem Pr og r a mmi ng (ISP)
Using the JTAG signals on Port E , the entire PSD
device (memory, logic, configuration) can be pro-
grammed or erased without the use of the MCU.
Table 3. JTAG S Ignal s on Por t E
In-Application Programming (IAP)
The primary Flash memory can also be pro-
grammed, or re-programmed, in-system by the
MCU execut ing the programming algorithms out of
the secondary Flash memory, or SRAM. The sec-
ondary Flash memory can be programmed the
same way by executing out of the primary Flash
memory. Table 4 indicates which programming
methods can program different functional blocks
of the PSD.
Name Inputs Outputs Product
Terms
Decode PLD (DPLD) 82 17 43
Complex PLD (CPLD) 82 24 150
Port E Pins JTAG Signa l
PE0 TMS
PE1 TCK
PE2 TDI
PE3 TDO
PE4 TSTAT
PE5 TERR
9/89
PSD4235G2
Page Regi s te r
The 8-bit Page Register expands the address
range of the MCU by up to 256 times. The pa ged
address can be used as part of the address space
to access external memory and peripherals, or in-
ternal memory and I/O. The Page Register can
also be used to change the address mapping of
the Flash memory blocks into different memory
spaces for IAP.
Power Management Unit (PMU)
The Power Management Unit (PMU) gives the
user control of the power consumption on selected
functional blocks based on system requirements.
The PMU includes an Automatic Power-down
(APD) Unit that turns off device functions during
MCU inactivity. The APD Unit has a Power-down
m ode t hat helps reduc e pow er c ons umpt ion.
The PSD also has some bi ts that are configured at
run-time by the MCU to reduce power consump-
tion of the CPLD. The Turbo bit in PMMR0 can be
reset to 0 and the CPLD latches its outputs and
goes to Stand-by mode until the next transi tion on
its inputs.
Additionally, bits in PMMR2 can be set by the
MCU to block signals from entering the CPLD to
reduce power consumption. See the section enti-
tled “Power Management” on page 59 f or more de-
tails.
Tabl e 4. Methods of Programming Different Functional Blocks of the PSD
Functional Block JTAG-ISP Device Programmer IAP
Primary Flash Memory Yes Yes Yes
Secondary Flash memory Yes Yes Yes
PLD Array (DPLD and CPLD) Yes Yes No
PSD Configuration Yes Yes No
PSD4235G2
10/89
DE VELOPMENT SYSTEM
The PSD fami ly i s supported by PSDsoft Express,
a Windows-based software development tool
(Windows-95, Windows-98, Windows-2000, Win-
dows-NT). A PSD design is quickly and easily pro-
duced in a point and click environment. The
designer does not need to enter Hardware De-
scription Language (HDL) equations, unless de-
sired, to define PSD pin functions and memory
map information. The general design flow is
shown in Figure 5. PSDsoft Express is available
from our web site (the address is given on the back
page of this data sheet) or other dist ri bution chan-
nels.
PSDsoft Express directly supports two low cost
device programmers form ST: PSDpro and
FlashLINK (JTAG). Both of these programmers
may be purchased through your local distributor/
representative, or directly f rom our web s ite us ing
a credit card. The PSD is also supported by thid
party device programmers. See our web site for
th e current list.
Figure 5. PSDsoft Express D evelopment Tool
Merge MCU Firmware
with PSD Configuration
PSD Programmer
*.OBJ FILE
PSDPro, or
FlashLINK (JTAG)
A composite object file is created
containing MCU firmware and
PSD configuration
C Code Generation
GENERATE C CODE
SPECIFIC TO PSD
FUNCTIONS
USER'S CHOICE OF
MICROCONTROLLER
COMPILER/LINKER
*.OBJ FILE
AVAILABLE
FOR 3rd PARTY
PROGRAMMERS
(CONVENTIONAL or
JTAG-ISC)
MCU FIRMWARE
HEX OR S-RECORD
FORMAT
AI04919
Define General Purpose
Logic in CPLD
Point and click definition of combin-
atorial and registered logic in CPLD.
Access HDL is available if needed
Define PSD Pin and
Node Functions
Point and click definition of
PSD pin functions, internal nodes,
and MCU system memory map
Choose MCU and PSD
Automatically configures MCU
bus interface and other
PSD attributes
11/89
PSD4235G2
PIN DESCRIP TION
Table 5 describes the signal names and signal
functions of the PSD. Those that have multiple names or functions are def ined using PSDsoft Ex-
press.
Table 5. Pin Descriptio n (for the TQFP package)
Pin Name Pin Type Description
ADIO0-
ADIO7 3-7
10-12 I/O
This is the lower Address/Data port. Connect your MCU address or address/data bus
according to the following rules:
1. If your MCU has a multiplexed address/data bus where the data is multiplexed with
the lower address bits, connect AD0-AD7 to this port.
2. If your MCU does not have a multiplexed address/data bus, connect A0-A7 to this
port.
3. If you are using an 80C51XA in burst mode, connect A4/D0 through A11/D7 to this
port.
ALE or AS latches the address. The PSD driv es data out only if the read signal is active
and one of the PSD functional blocks has been selected. The addresses on this port
are passed to the PLDs.
ADIO8-
ADIO15 13-20 I/O
This is the upper Address/Data port. Connect your MCU address or address/data bus
according to the following rules:
1. If your MCU has a multiplexed address/data bus where the data is multiplexed with
the upper address bits, connect A8-A15 to this port.
2. If your MCU does not have a multiplexed address/data bus, connect A8-A15 to this
port.
3. If you are using an 80C51XA in burst mode , connect A12/D8 through A19/D15 to this
port.
ALE or AS latches the address. The PSD driv es data out only if the read signal is active
and one of the PSD functional blocks has been selected. The addresses on this port
are passed to the PLDs.
CNTL0 59 I
The following control signals can be connected to this pin, based on your MCU:
1. WR – active Low, Write Strobe input.
2. R_W – active High, read/active Low write input.
3. WRL – active Low, Write to Low-byte.
This pin is connected to the PLDs. Therefore, these signals can be used in decode and
other logic equat ions.
CNTL1 60 I
The following control signals can be connected to this pin, based on your MCU:
1. RD – active Low, Read Strobe input.
2. E – E clock input.
3. DS – active Low, Data Strobe input.
4. LDS – active Low, Strobe for low data byte.
This pin is connected to the PLDs. Therefore, these signals can be used in decode and
other logic equat ions.
CNTL2 40 I
Read or other Control input pin, with multiple configurations. Depending on the MCU
interface selected, this pin can be:
1. PSEN – Program Select Enable, active Low in code fetch bus cycle (80C51XA
mode).
2. BHE – High-byte enable, 16-bit data bus.
3. UDS – active Low, Strobe for high data byte, 16-bit data bus mode.
4. SIZ0 – Byte enable input.
5. LSTRB – Low Strobe input.
This pin is also connected to the PLDs.
Reset 39 I Active Low input. Resets I/O Ports, PLD Macrocells and some of the Configuration
Registers and JTAG registers. Must be Low at Power-up. Reset also aborts any Flash
memory Program or Erase cycle that is currently in progress.
PSD4235G2
12/89
PA0-PA7 51-58
I/O
CMOS
or
Open
Drain
These pins make up Port A. These port pins are configurable and can have the
following functions:
1. MCU I/O – standard output or input port.
2. CPLD Macrocell (McellA0-McellA7) outputs.
3. Latched, transparent or registered PLD inputs (can also be PLD input for address
A16 and above).
PB0-PB7 61-68
I/O
CMOS
or
Open
Drain
These pins make up Port B. These port pins are configurable and can have the
following functions:
1. MCU I/O – standard output or input port.
2. CPLD Macrocell (McellB0-McellB7) outputs.
3. Latched, transparent or registered PLD inputs (can also be PLD input for address
A16 and above).
PC0-PC7 41-48
I/O
CMOS
or
Slew
Rate
These pins make up Port C. These port pins are configurable and can have the
following functions:
1. MCU I/O – standard output or input port.
2. External Chip Select (ECS0-ECS7) outputs.
3. Latched, transparent or registered PLD inputs (can also be PLD input for address
A16 and above).
PD0 79
I/O
CMOS
or
Open
Drain
PD0 pin of Port D. This port pin can be configured to have the following functions:
1. ALE/AS input – latches address on ADIO0-ADIO15.
2. AS input – latches address on ADIO0-ADIO15 on the rising edge.
3. MCU I/O – standard output or input port.
4. Transparent PLD input (can also be PLD input for address A16 and above).
PD1 80
I/O
CMOS
or
Open
Drain
PD1 pin of Port D. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Transparent PLD input (can also be PLD input for address A16 and above).
3. CLKIN – clock input to the CPLD Macrocells, the APD Unit’s Power-down counter,
and the CPLD AND Array.
PD2 1
I/O
CMOS
or
Open
Drain
PD2 pin of Port D. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Transparent PLD input (can also be PLD input for address A16 and above).
3. PSD Chip Select Input (CSI). When Lo w , the MCU can access the PSD memory and
I/O. When High, the PSD memory blocks are disabled to conserve power. The falling
edge of this signal can be used to get the device out of Power-down mode.
PD3 2
I/O
CMOS
or
Open
Drain
PD3 pin of Port D. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Transparent PLD input (can also be PLD input for address A16 and above).
3. WRH – for 16-bit data bus, write to high byte, active low.
PE0 71
I/O
CMOS
or
Open
Drain
PE0 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Latched address output.
3. TMS Input for the JTAG Serial Interface.
PE1 72
I/O
CMOS
or
Open
Drain
PE1 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Latched address output.
3. TCK Input for the JTAG Serial Interface.
PE2 73
I/O
CMOS
or
Open
Drain
PE2 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Latched address output.
3. TDI input for the JTAG Serial Interface.
Pin Name Pin Type Description
13/89
PSD4235G2
PE3 74
I/O
CMOS
or
Open
Drain
PE3 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Latched address output.
3. TDO output for the JTAG Serial Interface.
PE4 75
I/O
CMOS
or
Open
Drain
PE4 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Latched address output.
3. TSTAT output for the JTAG Serial Interface.
4. Ready/Busy output for parallel In-System Programming (ISP).
PE5 76
I/O
CMOS
or
Open
Drain
PE5 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Latched address output.
3. TERR active Low output for the JTAG Serial Interface.
PE6 77
I/O
CMOS
or
Open
Drain
PE6 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Latched address output.
3. VSTBY – SRAM stand-by voltage input for SRAM battery backup.
PE7 78
I/O
CMOS
or
Open
Drain
PE7 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Latched address output.
3. Battery-on Indicator (VBATON). Goes High when power is being drawn from the
external battery.
PF0-PF7 31-38
I/O
CMOS
or
Open
Drain
These pins make up P ort F. These port pins are configurable and can have the following
functions:
1. MCU I/O – standard output or input port.
2. External Chip Select (ECS0-ECS7) outputs, or inputs to CPLD.
3. Latched address outputs.
4. Address A1-A3 inputs in 80C51XA mode (PF0 is grounded)
5. Data bus port (D0-D7) in a non-multiplexed bus configuration.
6. Peripheral I/O mode.
7. MCU reset mode.
PG0-PG7 21-28
I/O
CMOS
or
Open
Drain
These pins make up Port G. These port pins are configurable and can have the
following functions:
1. MCU I/O – standard output or input port.
2. Latched address outputs.
3. Data bus port (D8-D15) in a non-multiplexed bus configuration.
4. MCU reset mode.
VCC 9, 29,
69 Supply Voltage
GND 8, 30,
49,
50, 70 Ground pins
Pin Name Pin Type Description
PSD4235G2
14/89
PSD REGIS TER DESCRIPTION AND ADDRESS OFFSETS
Table 6 shows the offset addresses to the PSD
registers relative to the CSIOP base address. The
CSIOP space is the 256 bytes of address that is al-
located by the user to the internal PSD registers.
Table 6 provides brief descriptions of the registers
in CSIOP space. The following sections give a
more detailed description.
Table 6. Regi ster Address Offset
Note: 1. Other registers that are not part of t he I /O ports.
Register Name Port
A Port
B Port
C P ort
D Port
E Port
F Port
G Other1 Description
Data In 00 01 10 11 30 40 41 Reads Port pin as input, MCU I/O input mode
Control 32 42 43 Selects mode between MCU I/O or Address
Out
Data Out 04 05 14 15 34 44 45 Stores data for output to Port pins, MCU I/O
output mode
Direction 06 07 16 17 36 46 47 Configures Port pin as input or output
Drive Select 08 09 18 19 38 48 49 Configures Port pins as either CMOS or
Open Drain on some pins, while selecting
high slew rate on other pins.
Input Macrocell 0A 0B 1A Reads Input Macrocells
Enable Out 0C 0D 1C 4C Reads the status of the output enable to the
I/O Port driver
Output
Macrocells A 20 Read – reads output of Macrocells A
Write – loads Macrocell Flip-flops
Output
Macrocells B 21 Read – reads output of Macrocells B
Write – loads Macrocell Flip-flops
Mask
Macrocells A 22 Blocks writing to the Output Macrocells A
Mask
Macrocells B 23 Blocks writing to the Output Macrocells B
Flash Memory
Protection C0 Read only – Primary Flash Sector Protection
Flash Boot
Protection C2 Read only – PSD Security and Secondary
Flash memory Sector Protection
JTAG Enable C7 Enables JTAG Port
PMMR0 B0 Power Management Register 0
PMMR2 B4 Power Management Register 2
Page E0 Page Register
VM E2
Places PSD memory areas in Program and/
or Data space on an individual basis.
Memory_ID0 F0 Read only – SRAM and Primary memory
size
Memory_ID1 F1 Read only – Secondary memory type and
size
15/89
PSD4235G2
REGISTE R BIT DEFINITION
All the registers of the PSD are included here, f or
reference. Detailed descriptions of these registers
can be found in the following sections.
Table 7. Data-In Registers – Ports A, B, C, D, E, F, G
Not e: Bit Definitions (Read-only registers):
Read Port pi n st atus when Por t i s i n MCU I/ O i nput mod e.
Table 8. Data-Out Registers – Ports A, B, C, D, E , F, G
Not e: Bit Definiti o ns:
Latched data for out put to Port pin when pin is configured in MCU I /O outp ut m ode.
Table 9. Direction Registers – Ports A, B, C, D, E, F, G
Not e: Bit Definiti o ns:
Po rt pin <i > 0 = Port pin <i> is configured in Input mode (default).
Po rt pin <i > 1 = Port pi n < i > i s conf i gured in Ou tput mo de.
Table 10. C ontro l Registe rs – Ports E, F, G
Not e: Bit Definiti o ns:
Po rt pin <i > 0 = Port pin <i> is configured in MCU I/O mode (default).
Po rt pin <i > 1 = Port pin <i> is configured in Latched Address Out mode.
Table 11. Drive Registers – Ports A, B, D, E, G
Not e: Bit Definiti o ns:
Po rt pin <i > 0 = Port pin <i> is configured for CMOS Output driver (default ).
Po rt pin <i > 1 = Port pi n <i > i s configured fo r Open Drain output dri ver.
Table 12. D rive Registers – Ports C, F
Not e: Bit Definiti o ns:
Po rt pin <i > 0 = Port pin <i> is configured for CMOS Output driver (default ).
Po rt pin <i > 1 = Port pin <i> is configured in Slew Rate mode.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Port pin 7 Port pin 6 Port pin 5 Port pin 4 Port pin 3 Port pin 2 Port pin 1 Port pin 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Port pin 7 Port pin 6 Port pin 5 Port pin 4 Port pin 3 Port pin 2 Port pin 1 Port pin 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Port pin 7 Port pin 6 Port pin 5 Port pin 4 Port pin 3 Port pin 2 Port pin 1 Port pin 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Port pin 7 Port pin 6 Port pin 5 Port pin 4 Port pin 3 Port pin 2 Port pin 1 Port pin 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Port pin 7 Port pin 6 Port pin 5 Port pin 4 Port pin 3 Port pin 2 Port pin 1 Port pin 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Port pin 7 Port pin 6 Port pin 5 Port pin 4 Port pin 3 Port pin 2 Port pin 1 Port pin 0
PSD4235G2
16/89
Table 13. En able-Ou t Registers – Ports A, B, C, F
Not e: Bit Definitions (Read-only registers):
Po rt pin <i > 0 = Port pin <i> i s i n t ri -state driver (default).
Po rt pin <i > 1 = Port pin <i> is enabled.
Table 14. Input M acroc ells – Ports A, B, C
Not e: Bit Definitions (Read-only registers):
Read Input Macrocel l (IMC7-IMC0) status on Po rts A, B an d C.
Table 15. Outp ut Macrocell s A Register
Not e: Bit Definiti o ns:
Write Register: Load M CellA7-MCe l l A0 with 0 or 1.
Rea d Registe r : Read MCellA7-M CellA0 output st atus.
Table 16. Outp ut Macrocell s B Register
Not e: Bit Definiti o ns:
Write Register: Load M CellB7-MCe l l B0 with 0 or 1.
Rea d Registe r : Read MCellB7-M CellB0 output st atus.
Table 17. Mask Macro cel ls A Register
Not e: Bit Definiti o ns:
McellA<i>_Prot 0 = Allow MCellA<i> flip-flop to be loaded by MCU (default).
McellA<i>_Prot 1 = Prevent MC el lA<i> fli p-f l op from bein g l oaded by MCU.
Table 18. Mask Macro cel ls B Register
Not e: Bit Definiti o ns:
McellB<i>_Prot 0 = Allow MCellB<i> flip-flop to be loaded by MCU (default).
McellB<i>_Prot 1 = Pr event MCellB< i> fli p-flop fr om being loaded by MCU.
Table 19. Fla sh Memory P rotection Register
Not e: Bit Definitions (Read-only register):
Sec<i>_Prot 1 = Primary Flash memory Sector <i> is write protected.
Sec<i>_Prot 0 = Pri m ary Fla sh m emory Sec to r <i > i s not write protected.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Port pin 7 Port pin 6 Port pin 5 Port pin 4 Port pin 3 Port pin 2 Port pin 1 Port pin 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IMcell 7 IMcell 6 IMcell 5 IMcell 4 IMcell 3 IMcell 2 IMcell 1 IMcell 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mcella 7 Mcella 6 Mcella 5 Mcella 4 Mcella 3 Mcella 2 Mcella 1 Mcella 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mcellb 7 Mcellb 6 Mcellb 5 Mcellb 4 Mcellb 3 Mcellb 2 Mcellb 1 Mcellb 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mcella 7 Mcella 6 Mcella 5 Mcella 4 Mcella 3 Mcella 2 Mcella 1 Mcella 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mcellb 7 Mcellb 6 Mcellb 5 Mcellb 4 Mcellb 3 Mcellb 2 Mcellb 1 Mcellb 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Sec7_Prot Sec6_Prot Sec5_Prot Sec4_Prot Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot
17/89
PSD4235G2
Table 20. Fla sh Boot Protection Register
Not e: Bit Definiti o ns:
Sec<i>_ Prot 1 = Secondary Flash memory Sector <i > is write protected.
Sec<i>_Prot 0 = Secondary Fl ash memo ry Sector <i> is not write protected.
Security_Bit 0 = Security Bit in device has not been set.
Security_Bit 1 = Security Bit in device has been set.
Table 21. JTAG Enabl e Register
Not e: Bit Definiti o ns:
JTAGE na ble 1 = JTAG Po rt is enable d.
JTAGEn able 0 = JTA G Port is dis abl ed.
Table 22. Pag e Register
Not e: Bit Definiti o ns:
Configure Page input to PLD. Default is PGR7-PGR0=0.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Security_Bit not used not used not used Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
not used not used not used not used not used not used not used JTAGEnable
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PGR 7 PGR 6 PGR 5 PGR 4 PGR 3 PGR 2 PGR 1 PGR 0
PSD4235G2
18/89
Table 23. PM M R0 Register
No te : The bits of this regi ster ar e cl eared to zero f ol l owing Power-up. Subsequent Reset (Reset) pulse s do not clear the registe rs.
Not e: Bit Definiti o ns:
APD Enable 0 = Aut om atic Po wer-down (APD) i s disabl ed.
1 = Aut om atic Po wer-down (APD) i s enabl ed.
PLD Turbo 0 = PLD Tu rbo is on.
1 = PLD Turb o i s of f , s aving po wer.
PLD Array CLK 0 = CLKIN to the PLD A ND array is connected. Ev ery CLKIN change p owers up t he PLD when Turbo b i t is off.
1 = CLKIN to the PLD AND array is disconnected, s aving po wer.
PLD MCells CLK 0 = CLKIN to the PLD Macrocell s is c onnecte d.
1 = CLKIN to the PLD Macrocells is disconnected, saving power.
Table 24. PM M R2 Register
Note: Fo r Bit 4, Bit 3, Bit 2: See Table 34 for the signa l s t hat are blocked on pi ns CNTL0-CNTL2.
Not e: Bit Definiti o ns:
PLD Array Addr 0 = Address A7-A0 are connected to t he PLD arr ay.
1 = Address A7-A0 are bl ocked from the PLD array, saving po wer.
(Note: in X A mode, A3 -A0 come from PF3-PF0, and A7 -A4 come f rom ADIO7-AD IO4)
PLD Array CNTL20 = CNT L2 inpu t to the PLD AN D array is c onnecte d.
1 = CNT L2 inpu t to the PLD AN D array is disconnected, saving power.
PLD Array CNTL10 = CNT L1 inpu t to the PLD AN D array is c onnecte d.
1 = CNT L1 inpu t to the PLD AN D array is disconnected, saving power.
PLD Array CNTL00 = CNT L0 inpu t to the PLD AN D array is c onnecte d.
1 = CNT L0 inpu t to the PLD AN D array is disconnected, saving power.
PLD Array ALE 0 = ALE i nput to the P LD AND arra y i s c onnecte d.
1 = ALE i nput to the P LD AND arra y i s disconn ected, saving power.
PLD Array WRH 0 = WRH/DBE input to the PLD AND array is connected.
1 = WRH/DBE input to the PLD A ND array is di sc onnect ed, saving power.
Table 25. VM Register
Note: On reset, Bit1-Bit4 are loaded to configurations that are selected by the user in PSDsoft Express. Bit0 and Bit7 are always cle ar ed on
reset. Bit0-Bit4 are active only when the device is c on figured in Philips 80C51XA mode.
Not e: Bit Definiti o ns:
SR_code 0 = PSEN cannot a ccess SRA M i n 80C5 1X A m odes.
1 = PSEN ca n access SR AM in 80C 51XA modes.
Boot_code 0 = PSEN ca nnot acc ess Secondary NVM in 80C51XA modes.
1 = PSEN ca n access Se condary NVM i n 80C51X A m odes.
FL_code 0 = PSEN cannot access Primary Flash memory in 80C51XA modes.
1 = PSEN ca n access Pr i mary Flash memory in 80C51XA m odes.
Boot_data 0 = RD cannot acc ess Secondary NVM in 8 0C51XA modes.
1 = RD can acce ss Secondary NVM i n 80C51XA modes.
FL_data 0 = RD cannot access Pri m ary Flash mem ory in 80 C51XA modes.
1 = RD can access Primary Flash m em ory in 80C51XA m odes.
Peripheral mode 0 = Periphe ral m ode of Po rt F is di sabled.
1 = Peripheral mode of Port F is enabled.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
not used
(set to 0) not used
(set to 0) PLD
MCells CLK PLD
Array CLK PLD
Turbo not used
(set to 0) APD
Enable not used
(set to 0)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
not used
(set to 0) PLD
Array WRH PLD
Array ALE PLD Array
CNTL2 PLD Array
CNTL1 PLD Array
CNTL0 not used
(set to 0) PLD
Array Addr
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Peripheral
mode not used
(set to 0) not used
(set to 0) FL_data Boot_data FL_code Boot_code SR_code
19/89
PSD4235G2
Table 26. Memo ry_I D0 Register
Not e: Bit Definiti o ns:
F_size[3:0] 0h = There is no Primary Flash memory
1h = Primary Flash memory size is 256 Kbit
2h = Primary Flash memory size is 512 Kbit
3h = Pr imary Fl ash memor y size is 1 M bi t
4h = Pr imary Fl ash memor y size is 2 M bi t
5h = Pr imary Fl ash memor y size is 4 M bi t
6h = Prim ary Flash m em ory size is 8 Mbit
S_size[3:0] 0h = There is no SRAM
1h = SRAM size is 16 Kbit
2h = SRAM size is 32 Kbit
3h = SRAM size is 64 Kbit
4h = SRAM size is 128 Kbit
5h = SRAM size is 256 Kbit
Table 27. Memo ry_I D1 Register
Not e: Bit Definiti o ns:
B_size[3:0] 0h = There is no Secondary NVM
1h = Seco ndary NV M size is 128 K bi t
2h = Secondary NVM size is 256 Kbit
3h = Seco ndary NV M size is 512 K bi t
B_type[1:0] 0h = Secondary NVM is Flash memory
1h = Secondary NVM is EEPROM
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
S_size 3 S_size 2 S_size 1 S_size 0 F_size 3 F_size 2 F_size 1 F_size 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
not used
(set to 0) not used
(set to 0) B_type 1 B_type 0 B_size 3 B_size 2 B_size 1 B_size 0
PSD4235G2
20/89
DETAIL ED OPERATIO N
As shown in Figure 4, t h e PSD consists of six ma-
jor types of functional blocks:
■Memory Blo c k s
■PLD Bloc ks
■MCU Bus Interface
■I/O P o rts
■Power Man agem ent Unit (PMU)
■JTAG-ISP Interface
The functions of each block are described in the
following sections. Many of the blocks perform
multiple functions, and are user configurable.
Memory Blocks
The PSD has the following m emory blocks:
– Primary Flash memory
– Secondary Flash memory
–SRAM
The Memory Select signals for these blocks origi-
nate from the De code PLD (DP LD) and are user-
defined in PSDsoft Express.
Table 28 sumamarizes the sizes and organisa-
tions o f the memory blocks.
Table 28. Memo ry Blo ck Size and Organi zati on
Primary Flash Memory Secondary Flash Memory SRAM
Sector
Number Sector Size
(x16) Sector Selec t
Signal Sector Size
(x16) Sector Select
Signal S RAM Size
(x16) SRAM Select
Signal
0 32K FS0 4K CSBOOT0 4K RS0
1 32K FS1 4K CSBOOT1
2 32K FS2 4K CSBOOT2
3 32K FS3 4K CSBOOT3
4 32K FS4
5 32K FS5
6 32K FS6
7 32K FS7
Totals 512KByte 8 Sectors 32KByte 4 Sectors 8KByte
21/89
PSD4235G2
Primary Flash Memory and Secondary Flash
memor y Descript ion . The primary Flash memo-
ry is divided evenly into 8 sectors. The sec ondary
Flash memory is divided evenly into 4 sectors.
Each sector of eithe r m emory block can be sepa-
rately protected from Program and Erase cycl es.
Flash memory may be erased on a sector-by-sec-
tor basis, and programmed word-by-word. Flash
sector erasure may be suspended while data is
read from other sectors of the block and th en re-
sumed after reading.
During a Program or Erase cycle in Flash memory,
the status can be output on the Ready/Busy pin
(PE4). Th is pin i s set up u sing PSDsoft Expres s.
Memory Block Select Signals. The DPLD gen-
erates t he Select signals for all the internal memo-
ry bl oc ks (see the section entitled “PLDs”, on page
31). Each of the sectors of the primary Flas h mem-
ory has a Select signal (FS0-FS7) which can c on-
tain up to t hree product terms. Each of the sectors
of the seco ndary Fl ash memo ry h as a Select s ig-
nal (CS BOOT0-CSB OOT3) whic h can contain up
to three product terms. Having three product terms
for each Select s ignal allows a gi ven sector to be
mapped in different areas of system memory.
When using a MCU with separate Program and
Data space (80C51XA), these flexi ble Select sig-
nals allow dynamic re-mapping of sectors from
one memory space to the other before and after
IAP. The SRAM block has a single Select signal
(RS0).
Ready/Busy (PE4). This signal can be used to
output the Ready/Busy stat us of the PSD. The out -
put is a 0 (Busy) when a Flash memory block is be-
ing written to,
or
when a Flash memory block is
being erase d. The out put is a 1 (Ready) whe n no
Write or Erase cycle is in progress .
Mem ory Op eration . The primary Flash memory
and secondary Flash memory are addressed
through the MCU Bus I nterface. T he MCU c an ac-
cess these memories in one of two ways:
■The MCU can execute a typical bus Write or
Read
operation
just as it would if accessing a
RAM or ROM device using standard bus cycles.
■The MCU can execute a s pecific instruction that
consists of several W rite and Read operations.
Th is involves writ ing specif ic d ata p at t e r ns to
special addresses within the Flash memory to
invoke an embedded algorithm. These
instructions are summarized in Table 29.
Typically, the MCU c an read F lash memory using
Read operations , just as it would read a ROM de-
vice. However, Flash m em ory can only be erased
and programmed using specific instructions. For
example, the MCU cannot write a single byte di-
rectly to Flash memory as one would write a byte
to RAM. To program a word into Flash memory,
the MCU must execute a Program instruction, then
test the status of the Programming event. This sta-
tus test is achieved by a Read operation or polling
Ready/Busy (PE4).
Flash memory can also be read by using special
instructions to retrieve particular Flash device in-
formation (sector protect status and ID).
PSD4235G2
22/89
Table 29. Instructions
Note: 1. All bus cycles are write bus cycles, except the ones with the “Read” label
2. All v al ues are in hexadec i m al :
X = Don’t Care . Addr esses of th e form XXXX h, in this t able, mu st be even address es
RA = Ad dress of the memor y l ocation t o be read
RD = Dat a read from loca tion RA during the Read cycle
PA = Address of the memory location to be programmed. Addresses are latched on the fal ling edge of Write Strobe (WR, CN T L0) .
PA is an even ad dress fo r PSD in word programming mod e .
PD = Dat a word to be programmed at locat i on PA. Dat a i s l atched on the ri si ng edge of Write S trobe (WR, CNTL0)
SA = Addres s of the sector to be er ased or verified. Th e Sector Selec t (FS0- FS7 or CSBOOT0- CSBOOT3) of the sector to be
era sed, or verified, must b e Active (High).
3. Sector Select (FS 0 to FS7 or CSBOOT 0 to CS BO OT 3) signal s are active High , an d are defined in PSD soft Ex press.
4. On l y address bits A11 -A0 ar e us ed in ins t ruct i on dec o di ng.
5. No Unlock or instructio n cy cles are requir ed when the devic e i s i n t he Read mo de
6. The Reset instruc tion is required to return to the Read mode after reading the Flash I D, or after reading the Sec tor Protection St at us,
or if the Error Flag (DQ5/DQ13) bit goes High.
7. Additional sectors to be eras ed must be written a t the end of t he S ector Erase inst ruction within 80 µs.
8. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and
(A1,A0)=(1,0)
9. The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction.
10. The U nl ock Bypass R eset Flash inst ruction is required to retu rn to reading m emory data whe n the dev i ce is in the Unlock Bypass
mode.
11. The system ma y perform Read and Pro gram cycles in non-erasing sect ors, read the F l ash ID or read t he Sector Pr otecti on Status
when in the Suspen d Sector E rase mo de. T he Suspe nd Sector E rase in st ruction i s valid onl y duri ng a S ector Erase cycl e.
12. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode.
1 3. The MCU can not inv oke the se i n stru ction s wh ile exe cutin g cod e from the sa me Fla sh me mory as that fo r whic h the ins truc tio n is
intended. The MCU must fetch, for example, t he code f rom the secondary Flash memory when reading the Sec tor Protection Status
of t h e prim a ry F lash m em o ry.
14. All write bus cycles in an instruction are byte write to an even address (XA4Ah or X554h). A Flash memory Program bus cycle writes
a word to an even address .
Instruction14 FS0-FS7 or
CSBOOT0-
CSBOOT3 Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7
Read51“Read”
RD @ RA
Read Main Flash ID61AAh@
XAAAh 55h@
X554h 90h@
XAAAh Read ID
@ XX02h
Read Sector
Protection6,8,13 1AAh@
XAAAh 55h@
X554h 90h@
XAAAh
Read 00h
or 01h @
XX04h
Program a Flash
Word13 1AAh@
XAAAh 55h@
X554h A0h@
XAAAh PD@ PA
Flash Sector Erase7,13 1AAh@
XAAAh 55h@
X554h 80h@
XAAAh AAh@
XAAAh 55h@
X554h 30h@
SA 30h7@
next SA
Flash Bulk Erase13 1AAh@
XAAAh 55h@
X554h 80h@
XAAAh AAh@
XAAAh 55h@
X554h 10h@
XAAAh
Suspend Sector
Erase11 1B0h@
XXXXh
Resume Sector
Erase12 130h@
XXXXh
Reset61F0h@
XXXXh
Unlock Bypass 1 AAh@
XAAAh 55h@
X554h 20h@
XAAAh
Unlock Bypass
Program91A0h@
XXXXh PD@ PA
Unlock Bypass
Reset10 190h@
XXXXh 00h@
XXXXh
23/89
PSD4235G2
Instructions
An instruction consists of a sequence of specific
operations. Each received byte is sequenti ally de-
coded by the PSD and not executed as a standard
Write operation. The instruction is e xecuted when
the correct num ber of byt es are properly rec eived
and the time between two consecutive bytes is
shorter than the time-out period. Some instruc-
tions are s tructured to include Read operations af-
ter the ini tial Write operations.
The instruction must be followed exactly. Any in-
valid combination of instruction bytes or time-out
between two consecutive bytes while addressing
Flash memory resets the device logic into Read
mode (Fl ash memory is read like a ROM device).
The P SD supports the instru ctions sum ma rized in
Table 29:
■Erase memory by chip or sector
■Suspend or resume sector erase
■Program a Word
■Reset to Read mode
■Read primary Flash Identifier value
■Read Secto r Protection Status
■Bypass
These instructions ar e detailed in Table 29. For ef-
ficient decoding of the instructions, the first two
bytes of an instruction are the coded cycles and
are followed by an instruction byte or confi rmation
byte. The coded cycles consist of writing the data
AAh to address XAAAh during the first cycle and
data 55h to address X554h during the s econd cy-
cle (u nless the Bypas s instruction featu re is used,
as described later). Address signals A15-A12 are
Don’t Care during the instruction Write cycles.
However, the appropriate Sector Select signal
(FS0-FS7, or CSBOOT0-CSBOOT3) must be se-
lected.
The primary and secondary Flash memorie s have
the same instruction set (exce pt for Read Primary
Flash Identifier ). The Sector Select signa ls de ter-
mine which Flash memory is to receive and exe-
cute the i ns truction. The primary Flash memory is
selected if any one of its Sector Select signals
(FS0-FS7) is High, and the secondary Flash mem-
ory is se lecte d if any one of its Sector Select sig-
nals (CSBOO T0-CSB OO T3) is High .
Power-up Condition. The PSD internal logic is
reset upon Power-up to the Read mode. Sector
Select (FS0-FS7 and CSBOOT0-CSBOOT3)
must be held Low, and Write Strobe (WR/WRL,
CNTL0) High, during Power-up for maximum se-
curity of t he data c ontents and to remove t he pos-
sibility of data being written on the first edge of
Write Strobe (WR /WRL, CNTL0). Any Write cycle
initiation is locked when VCC is below VLKO.
Reading Flash M emory
Under typical conditions, the MCU may read the
primary Flash memory, or se condary Flash mem-
ory, us ing Read operations just as it would a ROM
or RAM device. Alternately, the MCU may use
Read operations to obtain status information
about a Program or Erase cycle that is currently in
progress. Lastly, the MCU may use instructions to
read special data from these m em ory blocks. The
following sections describe these Read f uncti ons.
Read Memory Contents. P rim ary Fl ash memory
and secondary Flash memory are placed in the
Read mode after Power-up, chip reset, or a Reset
Flash instruction (see Table 29). The MCU can
read the memory contents of the primary Flash
memory, or the secondary Flash memory by using
Read operations any time the Read operation is
not part of an instruction.
Read Primary Flash I dentifier. The primary
Flash memory identi fier is read with an instruction
com posed of 4 operations: 3 specific Writ e opera-
tions and a Read operation (see Table 29). The
identifier for the primary Flash memory is E8h. The
secondary Flash memory does not support t his in-
struction.
Read Memory Sector Protection Statu s. The
Flash memory Sector Protection Status is read
with an instruction composed of four operations:
three specif ic Write operations and a Read opera-
tion (see Table 29). The Read operation produces
01h if the Flash memory sector is protected, or 00h
if the sector is not protected.
The sector protection status for all NVM blocks
(primary Fl ash memory, or secondary Flash mem-
ory) can be read by the MCU accessing the Flash
Protection and Flash Boot Protection registers in
PSD I/O space. See the section entitled “Flash
Memory Sector Protect”, on page 27, for register
definitions.
Reading the Erase/Pr ogram Status Bits. The
PSD provides several status bi ts to be used by the
MCU to confirm the completion of an Er ase or Pro-
gram cycle of Flash memory. These status bits
minimize the time that the MCU spends perform-
ing these tasks and are defined in Table 30. The
status byte resides in an even location, and can be
read as many times as needed. Also note that
DQ15-DQ8 is an even byte for Motorola MCUs
with a 16-bit data bus .
For Flash memory, the MCU can perform a Read
operation to obtain these status bits while an
Erase or Program instruction is being executed by
the embedded algo ri thm. See t he section entitled
“Programming Flash Memory”, on page 25, f or de-
tails.
PSD4235G2
24/89
Table 30. Statu s Bits
Table 31. Statu s Bits for Motoro la
Note: 1. X = Not guarante ed value, c an be read ei ther 1 or 0.
2. DQ 15-DQ0 represent the Data Bus bi ts , D15-D0.
3. FS0-FS7/CSBOOT0-CSBOOT3 are act ive High.
Data Polling (DQ7) – DQ15 for Motorola.
When erasing or programming in Flash memory,
the Data Polling (DQ7/ DQ15) bit ou tputs the com-
plement of the bit being entered fo r programm ing /
writing on the DQ7/DQ15 bit. Once the Program
instruction or the Write operation is completed, the
true logic value is re ad on the Data P olling (DQ7/
DQ15) bit (in a Read oper ation).
■Data Polling is effect ive after the fourth Write
pulse (for a Program in struction) or after the
sixth Write pulse (for an Erase instruction). It
must be performed at the address being
programmed or at an address within the Flash
memo ry sector being erased.
■Durin g an Erase cycle, th e Data Polli n g (DQ7/
DQ15) bit outputs a 0. After completion of the
cycle, the Data P oll ing (DQ7/DQ15 ) bit outputs
the last bit programmed (it is a 1 after eras i ng).
■If the loc ation to be programmed is in a
protected Flash memory sector, the instruction
is ignored.
■If all the Flash memory sectors to be erased are
protected, the Dat a Pollin g (DQ7/DQ 1 5) bit is
reset to 0 for about 100 µs, and then returns to
the value from the previously addressed
location. No erasure is performed.
Toggl e Fl ag (D Q6) – DQ14 for Moto rola. The
PSD offers anothe r way f or de termini ng whe n t he
Flash memory Program cycle is completed. During
the internal Write operation and when either F S 0-
FS7 or CSBOOT0-CSBOOT3 is true, the Toggle
Flag (DQ6 /DQ14) bit toggles fro m 0 to 1 and 1 t o
0 on subsequent attempts to read any wor d of the
memory.
When the internal cycle is complete, the toggling
stops and the data r ead on the Data Bus D0-D7 is
the value from the addressed memory location.
The device is now accessible for a new Read or
Write operation. The cycle is finished when two
successive Reads yield the same out put data.
■The Toggle Flag (DQ6/DQ14 ) bit is effective
after the fourth Write pulse (for a Program
instruction) or af ter t he sixth Write pulse (for an
Erase inst ruction).
■If the loc ation to be programmed belongs to a
protected Flash memory sector, the instruction
is ignored.
■If all the Flash memory sectors selected for
erasure are protected, the Toggle Flag (DQ6/
DQ14) bit toggles to 0 for about 100 µs and then
returns to the value from the previously
addressed location.
Error Flag (DQ5) – DQ13 for Motorola. During
a normal Program or Erase cycle, the Error Flag
(DQ5/DQ13) bit is reset to 0. This bit is set to 1
when there is a failure duri ng a Flash memory Pro-
gram, Sector Erase, or Bulk Erase cycle.
In the c as e of Flash memory programming, the Er-
ror Flag (DQ5/DQ13) bit indicates the attempt to
program a Flash memory bit, or bits, from the pro-
grammed state, 0, to the erased st ate, 1 , which is
not a valid operation. The Error Flag (DQ 5/DQ13 )
bit may also indicate a Time-out condition while at-
tempting to program a word.
In case of an error in a Flash memory Sector Erase
or Word Program cycle, the Flash memory sector
in which the error occurred or to which the pro-
grammed location belongs must no longer be
used. Other Flash memory sectors may still be
used. The Error Flag (DQ5/DQ13) bit i s res et af ter
a Reset instruction. A Reset i nstruction is required
after detecting an error on the Error Flag (DQ5/
DQ13) bit.
Erase T ime-out F lag (DQ3) – DQ11 for Motoro-
la. The Erase Time-out Flag (DQ3/DQ11) bit re-
flects the time-out period allowed between two
consecutive S ect or Er ase inst ructions. The Erase
Time-out Flag (DQ3/DQ11) bit is reset to 0 after a
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
Data Polling Toggle Flag Error Flag X Erase Time-
out XXX
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8
Data Polling Toggle Flag Error Flag X Erase Time-
out XXX
25/89
PSD4235G2
Sector Erase cycle for a period of 100 µs + 20%
unless an additional Sector Erase instruction is de-
coded. After this period, or when the additional
Sector Erase instruction is decoded, the Erase
Time-out Flag (DQ3/DQ11) bit is set to 1.
Programming Flash Memory
Flash memor y m ust be erased prior to being pro-
grammed . The M CU m ay erase Fl ash m emo ry a ll
at once or by-sector. Although erasing Flash mem-
ory occurs on a sector or device basis, program-
ming Flash memory occurs on a word basis.
The primary and secondary Flash memories re-
quire the MCU to send an inst ruction t o program a
word or to erase sectors (see Table 29).
Once the MCU issues a Flash m emory Program or
Erase i nstruction, it m ust check the status bits f or
completion. T he embedded algorit hms that are in-
voked inside the PSD support several means to
provide status to the MCU. Status may be checked
using any of three methods: Data Polling, Data
Toggle, or Ready/Busy (PE 4) signal.
Data Polling. Polling on the Data Polling (DQ7/
DQ15) bi t is a met hod of c heck ing whe ther a Pro-
gram or Erase cy cle i s in progress or has complet -
ed. Figure 6 sho ws the Data Polling algorithm.
When th e MCU issue s a Program i nstruction, t he
embedded algorithm within the PSD begins. The
MCU then reads the location of the word t o be pro-
grammed in Flash memory to check the status.
The Data Polling (DQ7/DQ15) bit becomes the
complement of the corresponding bit of the original
data word to be programmed. The MCU continues
to poll this location, comparin g data and monitor-
ing the Error Flag (DQ5/DQ13 ) bit. When the Data
Polling (DQ7/DQ15) bit matches the correspond-
ing bit of the original data, and the Error Flag
(DQ5/DQ13) bit remains 0, the embedded algo-
rithm is complete. If the Er ror Flag (DQ5/DQ13) bit
is 1, the MCU should test the Data Polli ng (DQ7/
DQ15) bit again since the Data Polling (DQ7/
DQ15) bit ma y ha ve changed s imultaneously with
the Error Flag (DQ5/DQ13) bit (see Figure 6).
The Error Flag (DQ5/DQ13) bit is set if either an in-
ternal time-out occurred while the embedded algo-
rithm attempted to program the location or if the
MCU attempted to program a 1 to a bit that was not
erased (not erased is logic 0).
It is suggest ed (as with all Flash memories) to read
the location again after the embedded program-
ming algorithm has completed, to compare the
word that was written t o the Flash memory with the
word that was intended to be written.
When using the Data Polling method during an
Erase cycle, Figure 6 still applies. However, the
Data Polling (DQ7/DQ15) bit is 0 until the Erase
cycle is complete. A 1 on the Error Flag (DQ5/
DQ13) bit indicates a time-out condition on the
Erase cycle , a 0 ind icates no error. The M CU c an
read any even location within the sector being
erased to get the Data Poll ing (DQ7/DQ15) bit and
the Error Fl ag (DQ5/DQ13) bit .
PSDsoft Express generates ANSI C code func-
tions that implement these Data Polling algo-
rithms.
Figu re 6. Da ta Po lli ng Flowchart
Da ta Toggle. Checking the Toggle Flag (DQ6/
DQ14) bit is another method of determining wheth-
er a Program or Erase cycle is in progress or has
completed. Fig ure 7 s hows t he Da ta Tog gle a lgo-
rithm.
When th e MCU issue s a Program i nstruction, t he
embedded algorithm within the PSD begins. The
MCU then reads the location to be programmed in
Flash memory to check the status. The Toggle
Flag (DQ6/DQ14) bit togg les each ti me the MCU
READ DQ5 and DQ7
(DQ13 and DQ15)
at Valid Even Address
START
READ DQ7
(DQ15)
Program
or Erase
Cycle failed
Program
or Erase
Cycle is
complete
AI04920
Yes
No
Yes
No
DQ5
(DQ13)
= 1
DQ7
(DQ15)
=
Data7
(Data15)
Yes
No
Issue RESET
instruction
DQ7
(DQ15)
=
Data7
(Data15)
PSD4235G2
26/89
reads this locati on unt il the embedded algorithm is
complete. The MCU continues to read this loca-
tion, checking the Toggle Flag (DQ6/DQ14) bit
and monitoring the Error Flag (DQ5/DQ13) bit.
When the T oggle Flag (DQ6 /DQ1 4) bit stops tog-
gling (two consecutive reads yield the same val-
ue), and the Error Flag (DQ5/DQ13) bit remains 0,
the embedded algorithm is complete. If the Error
Flag (DQ5/DQ13) bit is 1, the MCU should test the
Toggle Flag (DQ6/DQ14) bit again, since t he Tog-
gle Flag (DQ6/DQ14) bit may have changed simul-
taneously wit h the Error Flag (DQ5/DQ13) bi t (see
Figure 7).
Figu re 7. Da ta To ggl e Fl owchar t
The Error Flag (DQ5/DQ13) bit is set if either an in-
ternal time-out occurred while the embedded algo-
rithm attempted to program, or if the MCU
attempted to program a 1 to a bit that was not
erased (not erased is logic 0).
It is suggest ed (as with all Flash memories) to read
the location again after the embedded program-
ming algorithm has completed, to compare the
word that was written to Flash memory with the
word that was intended to be written.
When using the Data Toggle method after an
Erase cycle, Figure 7 st il l applies. the Toggle Flag
(DQ6/DQ14) bit toggles until the Erase cycle is
complete. A 1 on the Error Flag (DQ5/DQ13) bit in-
dicates a time-out condition on the Erase cycle, a
0 indicates no error. The MCU can rea d any ev en
location with in the sector being erased to get the
Toggle Flag (DQ6/DQ14) bit and the Error Flag
(DQ5/ DQ13) bit .
PSDsoft Express generates ANSI C code func-
tions which im plement these Data Toggling a lgo-
rithms.
Unlock Bypass. The Unlock Bypass instruction
allows the system to program words to the Flash
memories faster than using the standard Program
instruction. The Unlock Bypass mode is entered
by first ini tiating two Unlock cycles . This is followed
by a third Write cycle containing the Unlock By-
pass command , 20 h (as shown i n Table 29). The
Flash memory then enters the Unlock Bypass
mode.
A two-cycle Unlock Bypa ss Program i nstruction is
all that is required to program in this mode. The
first cycle in this instruction contains the Unlock
Bypass Program command , A0h. The second cy-
cle contain s the program address and dat a. A ddi-
tional data is programmed in the same manner.
This mode dispense wit h the initial two Unlock cy-
cles requ ired in the standard P rogram inst ruction,
resulting in faster total programming t ime.
During the unlock bypass mode, only the Unlock
Bypass Program and Unlock Bypass Reset in-
structions are valid.
To e xi t the Unlo ck Bypass mode, the system must
issue the two-cycle Unlock Bypass Reset instruc-
tion. The first cycle mus t contain the data 90h; the
second cycle the data 00h. Addresses are Don’t
Care for both cycles. The Fla sh mem ory then re-
turns to Read mode.
Erasing Flash Memory
Flash Bulk Erase. The Flash B ulk E rase instruc-
tion us es six Write operations followed by a Read
operation of the status register, as described in
Table 29 . If an y by te of t he Bul k E ras e i nstruct ion
is wrong, t he Bulk Erase instruction aborts and the
device is reset t o the Read M em ory mode.
During a Bulk Erase, the memory status may be
checked by reading the Error Flag (DQ5/DQ13)
bit, the Toggle Fl ag (DQ6/DQ14) bit, and the Data
Pollin g ( DQ 7/DQ 15 ) bit , as det ailed in the s ect ion
START
READ DQ6
(DQ14)
AI04921
No
No
Yes
Yes
No
Yes
Program
or Erase
Cycle failed
Program
or Erase
Cycle is
complete
Issue RESET
instruction
READ DQ5 and DQ6
(DQ13 and DQ14)
at Valid Even Address
DQ5
(DQ13)
= 1
DQ6
(DQ14)
=
Toggle
DQ6
(DQ14)
=
Toggle
27/89
PSD4235G2
entitled “Programming Flash Memory”, on page
25. The Error Flag (DQ5/DQ13) bit returns a 1 if
there has been an Erase F ailure (maximum num-
ber of Eras e cycles hav e been exec ut e d) .
It is not necessary to program the memory with
00h because the PSD auto matically does this be-
fore erasing to 0FFh.
During execut ion of the Bulk Erase instruction, the
Flash mem ory does not accept any i ns tructions.
Flash Sector Erase . The Sector Erase instruc-
tion uses six Write operations, as described in Ta-
ble 29. Additional Flash Sector Erase confirm
commands and Flash memory sector addresses
can be written subsequently to erase other F lash
memory sectors in parallel, without fu rther co ded
cycles, if the additional commands are transmit ted
in a shorter time than the tim e-out period of about
100 µs. The input of a new Sector Erase command
restarts the tim e-out period.
The status of the interna l timer can be monitored
through the level of the Erase Time-out Flag (DQ3/
DQ11) bit. If the Erase Time-out Flag (DQ3/DQ11)
bit is 0, the S ector Er ase instructio n has been re-
ceived and the time-out period is counting. If the
Erase Time-out Flag (DQ3/DQ11) bit is 1, the
time-out period has expired and the PSD is busy
erasing the Flash memory sector(s). Before and
during Erase time-out, any instruction other than
Suspend Sector Erase and Resume Sector Erase,
abort the cycle that is current ly in progress, and re-
set t he device to Read mode. It is not necessary to
program the Flash me mory sector with 00h as t he
PSD does this automatically bef ore erasing.
During a Sector Erase, the memory status may be
checked by reading the Error Flag (DQ5/DQ13)
bit, the Toggle Fl ag (DQ6/DQ14) bit, and the Data
Pollin g ( DQ 7/DQ 15) b it, as d etaile d in t he se ctio n
entitled “Programming Flash Memory”, on page
25.
During execution of the Erase cycle, the Flash
memory accepts only Reset and Susp end Se ctor
Erase in structi ons. Erasure of one Flash memory
sector may be suspended, in order to read data
from another Flash memory sector, and then re-
sumed.
Suspend Sector Erase. When a Sector Erase
cycle is in progress, the Suspend Sector Erase in-
struction can be used to suspend t he cycle by writ-
ing 0B0h to any even address when an
appropriate Sector Select (FS0-FS7 or
CSBOOT0-CSBOOT3) is High. (See Table 29).
This allows reading of data from another Flash
memory sector after the Erase cycle has been
suspended. Suspend Sector Erase is accepted
only during the Flash Secto r E ra se inst ruction ex-
ecution and defaults to Read mode. A Suspend
Sector Erase instruction executed during an Erase
time-out period, in addition to suspending the
Erase cycle, terminates the time out period.
The Toggle Flag (DQ6/DQ14) bit stops toggling
when the PSD internal logic is suspended. The
status of th is bit m ust be m onitored at an address
within the F lash memory sector bei ng erased. The
Toggle Flag (DQ6/DQ14) bit stops toggling be-
tween 0.1 µs and 15 µs after the Suspen d Sector
Erase in struction has been executed. The PSD is
then automatically set to Read mode.
If an Suspend Sector Erase instruction was exe-
cuted, the following rules apply:
– Attempting to read from a Flash memory se ctor
that was being erased outputs invalid data.
– Reading from a Flash memory sector that was
not
b eing erased is valid.
– The Flash memory
cannot
be program med, and
only responds to Resum e Sector Erase and Re-
set instructions (Read is a n operation an d is al-
lowed).
– If a Reset instruction is received, data in the
Flash memory sector that was being erased is
invalid.
Resume Sector Erase. If a Suspend Sector
Erase instruction was previously executed, the
Erase cycle may be resu med with th is instruction.
The Resume Sector Erase instruction consists of
writing 030h to any even address while an appro-
priate Sector Select (FS0-FS7 or CSBOOT0-
CSBOOT 3) is High. (See Table 29.)
Flash Memory Sector Protect
Ea ch sect o r o f P r i mar y or Seco nda ry Flash m e m-
ory ca n be separately protected aga inst Program
and Erase cycles. Sector Protection provides ad-
ditional data security because it disables all Pro-
gram or Erase cycles. This mode can be activated
(or deactivated) through the JTAG-ISP Port or a
Device Pro g ra mmer.
Sector protection c an be selected for each sector
using the PSDsoft Express program. This auto-
matically protects selected sectors when the de-
vice is programmed through the JTAG Port or a
Device Programmer. Flash memory sectors can
be unprote cted to allo w upda ting of their co ntents
using the JTA G Port or a Device Programmer. The
MCU can read (but cannot change) the sector pro-
tection bits.
Any att empt to progr am or erase a protected Flash
memory sector is ignored by the dev ice. The V erify
operation results in a read of the protected data.
This allows a guarantee of the r etention of the Pro-
tection status.
The sector protection status can be read by the
MCU through the Flash memory protection and
Secondary Flash memory protection registers (in
PSD4235G2
28/89
the CSIOP block) or use the Read Sector Protec-
tion instruction. See Table 19 t o T able 20.
Reset
The Reset instruction consists of one Write cycle
(see Table 29). It can also be opti onally p receded
by the standard two write dec oding cycles (writing
AAh to AAAh, and 55h to 554h).
The Reset ins truction must be executed after:
– Reading the Flash Pr ot ection Stat us or Fl ash ID
– An Error condition has occurred (and the devi ce
has set the Error Flag (DQ5/DQ13) bit to 1) dur-
ing a Flash memory Program or Erase cycle.
The R eset instruction immediately puts the Flash
memory back int o norm al Read mode. However, i f
there is an error condition (with the Error Flag
(DQ5/DQ13) bit set to 1) the F l ash memory will re-
turn to the Read mode in 25 µs after the Reset in-
struction is issued.
The Reset instruction is ignored when it is issued
during a Pro gr a m or Bu lk Erase cycle o f the Fl a sh
memory. Th e Reset instruction abo rts an y on-go-
ing Sector Erase cycle, and returns the Flash
memory t o the norm al Read mode in 25 µs.
Reset (R ESET) Pin. A pulse on the Reset (RE-
SET) pin aborts any cycle that is in progress, and
resets the Flash memory to the Read mode. When
the reset occurs during a Pr ogram or Erase cycle,
the Flash memory takes up to 25 µs to return to
the Read mode. It is recommended that the Reset
(RESET) pulse (except for Power On Reset, as
described on page 62) be at least 25 µs so that the
Flash memory is always ready for the MCU to
fetch the bootstrap i nst ructions after the Reset cy-
cle is complete.
SRAM
The SRAM is enabled when SRAM Sele ct (RS0)
from the DPLD is High. SRAM Select (RS0) can
contain up to three product terms, allowi ng flexibl e
mem o ry map p ing .
The SRAM can be backed up using an external
battery. The external battery should be connected
to the Voltage Stand-by (VSTBY, P E6) lin e. If you
have an external battery connected to the PSD,
the content s of the SRAM are retained in the event
of a power loss. T he contents of the S RAM are re-
tained so long as the battery voltage remains at
2 V or greater. If the supply voltage falls below the
battery voltage, an internal power switch-over to
the battery occurs.
PE7 can be configured as an output that indicates
when pow er is being drawn from the ex ternal ba t-
tery. This Battery-on Indicator (VBATON, PE7)
signal i s H igh whe n the supply v oltage falls below
the battery voltage and the battery on Voltage
Stand-by (VSTBY, P E6) is supplyi ng power to the
internal SRAM.
SRAM Select (RS0), Voltage Stand-by (VSTBY,
PE6) and Battery-on Indicator (VBATON, PE7)
are all configured using PSDsoft Express.
Memory Select Signals
The Primary Flash Memory Sector Select (FS0-
FS7), Secondary Flash Memory Sector Select
(CSBOOT0-CSBOOT3) and SRAM Select (RS0)
signals a re all output s of the DPLD. They are de-
fined using PSDsoft Express. The following rules
apply to the equations for these signals:
1. Primary Flash memory and secondary Flash
memory Sector Select signals must
not
be larg-
er than the physical se ctor size.
2. Any primary Flash memory sector must
not
be
mapped in the s ame memory space as anot her
Flash memory sector.
3. A sec ondary Flash memory sec tor must
not
be
mapped in the s ame memory space as anot her
secondary Flash mem ory sector.
4. SRAM, I /O, and P eripheral I/O spaces must
not
overlap.
5. A secondary Flash memory sector
may
overlap
a primary Flash m emory sect or. In case of over-
lap, priority is given to the secondary Flash
memory sector.
6. SRAM, I/O, and Peripheral I/O spaces
may
overlap any ot her mem ory sector. Priority is giv-
en to the SRAM, I/O, or Peripheral I/O.
Figure 8. Priority Level of Memory and I/O
Components
Example. FS0 is val id when the address is in the
range of 8000h to BFF Fh, CSBOOT 0 is valid from
8000h to 9FFFh, and RS0 is valid from 8000h to
87FFh. Any address in the range of RS0 always
accesses the SRAM . Any address in th e rang e of
CSBOOT0 greater than 87FFh (and less than
9FFFh) automa tically addre ss es secondary Flash
memory segment 0. Any address greater than
9FFFh accesses the primary Flash memory seg-
Level 1
SRAM, I/O, or
Peripheral I/O
Level 2
Secondary
Non-Volatile Memory
Highest Priority
Lowest Priority
Level 3
Primary Flash Memory
AI02867D
29/89
PSD4235G2
ment 0. You can see that half of the prim ary Flash
memory segment 0 and one-fourth of secondary
Flash memory segment 0 cannot be accessed in
this example. Also note tha t a n equation that de-
fined FS1 to anywhere in the range of 8000h to
BFFFh would
not
be valid.
Figure 8 shows the priority levels for all memory
components . Any component on a higher level can
overlap and has priority over any component on a
lower level. Components on the same level must
not
overlap. Level 1 has the highest priority and
level 3 has t he lowest.
Memory Select Configuration for MCUs with
Separa te Program an d Data Spaces. The
80C51XA and c ompatible fami ly of MCUs, c an be
configured to have separate address spaces for
Program memory (s ele cted using Program S ele ct
Enable (PSEN, CNTL2)) and Data memory (se-
lected using Read Strobe (RD, CNTL1)). Any of
the mem ories within the PSD can reside in either
space or both spaces. This is controlled through
manipulatio n of the VM registe r that resides i n the
CSIOP space.
The VM register is set using PSDsoft Express to
have an initial value. It can subsequently be
changed by the MCU so that memory mapping
can be changed on-t he-fly.
For example, you may wish to have SRAM and pri-
mary Flash memory in the Data spac e at Boot-up,
and secondary Flash memory in the Program
space at Boot-up, and later swap the secondary
Flash memory and prim ary F lash m emo ry. This is
easily done with the VM regist er by using PSDsof t
Express to configure it for Boot-up and having the
MCU change it when desired.
Table 25 de scribe s the VM Register.
Separate Sp ace Modes. Program space is sep-
arated from Data space. For example, Program
Select Enable (PSEN, CNTL2) is used to access
the program code from the primary Flash memory,
while Read S trobe (RD, CNTL1) is used to ac cess
data from the secondary Flash memory, SRAM
and I/O Port blocks. This configuration requires
the VM register to be set to 0Ch (see Figure 9).
Figure 9. 8031 Mem or y M od ul es – Separate S pac e
Combined Space Mo des. The Program and
Data spaces are combined into one memory
space that al lows the prim ary Flash memory, sec-
ondary Flash memory, and SRAM to be accessed
by either Progra m Select Enable (PSEN, CNTL2)
or Read Strobe (RD, CNTL1). For example, to
configure the primary F lash m em ory in Combi ned
space, bits 2 and 4 of the VM reg ister are set to 1
(see Figure 10).
80C51XA Mem ory Map Exam ple. See the Ap-
plication Notes for examp les.
Primary
Flash
Memory
DPLD Secondary
Flash
Memory
SRAM
RS0
CSBOOT0-3
FS0-FS7 CS CSCS
OE OE
RD
PSEN
OE
AI02869C
PSD4235G2
30/89
Figure 10. 8031 M em or y Mo dules – Combined S pace
Page Re gi st er
The 8-bit Page Register increas es the addressing
capability of the MCU by a fact or of up to 256. The
contents of the register can also be read by the
MCU. The outputs of the Page Register (PGR0-
PGR7) are inputs to the DPLD decoder and can be
included in the Sector Select (FS0-FS7,
CSBOOT0-CSBOOT3), and SRAM Select (RS0)
equations.
If memo ry paging is not needed, or if not all eight
page register bits are n eeded f or m em ory paging,
these bits may be used in the CPLD for general
logic. See Application Note
AN1154
.
Table 22 and Figure 11 show the Page Register.
The eight fli p-flops in the register are connected to
the internal data bus (D0-D7). The MCU c an write
to or read f rom the Page Register. The Page Reg-
ister can be acc essed at address location CSIOP
+ E0h.
Figure 11. Page Register
Primary
Flash
Memory
DPLD Secondary
Flash
Memory
SRAM
RS0
CSBOOT0-3
FS0-FS7
RD
CS CSCS
RD
OE OE
VM REG BIT 2
PSEN
VM REG BIT 0
VM REG BIT 1
VM REG BIT 3
VM REG BIT 4
OE
AI02870C
RESET
D0-D7
R/W
D0 Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D1
D2
D3
D4
D5
D6
D7
PAGE
REGISTER
PGR0
PGR1
PGR2
PGR3 DPLD
AND
CPLD
INTERNAL
SELECTS
AND LOGIC
PLD
PGR4
PGR5
PGR6
PGR7
AI02871B
31/89
PSD4235G2
M emory ID Registers
The 8-bit read-only Memory Status Registers are
included in the CSIOP space. The user can deter-
mine the memory confi guration of the PSD device
by reading the Memory ID0 and Memory ID1 reg-
isters. The content of the registers is defined as
shown in Table 26 and Tabl e 27.
PLDs
The PLDs bring programmable logic functionality
to the PSD. After spec ifying the logic for the PLDs
using PSDsoft Express, the logic is programmed
into the device and available upon Power-up.
Tab le 32. D PL D and C P LD I nputs
Note: 1. The ad dress inputs ar e A1 9-A4 in 80C51XA m ode.
The PSD contains two PLDs: the Decode PLD
(DPLD), and the Complex PLD (CPLD). The PLDs
are briefly di scu ssed in the next few paragraphs,
and in more detail i n the followin g secti ons. F igure
12 shows the configuration of the PLDs.
The DPLD performs address decoding for internal
components, such as memory, registers, and I/O
ports Select signal s.
The CPLD can be us ed for logic funct ions, such as
loadable counters and shift registers, state ma-
chines, and encoding and decoding logic. These
logic functions can be constructed using the 16
Output Macrocells (OMC), 24 Input Macrocells
(IMC), and the AND Array. The CPLD can also be
used to generate External Chip Select (ECS0-
ECS2) signals.
The AND Array is used to form product terms.
These produc t terms are specified u sing P SDsoft
Express. An Inp ut Bus consisting of 82 signals is
connected to the PLDs. T he signals are shown in
Table 32.
The Turb o B it i n PSD. The PLDs in the
PSD4235G2 can minimize power consumption by
switching to standby when inputs remain un-
changed for an extended time of about 70 ns. Re-
setting the Turbo bit to 0 (Bit 3 of the PMMR0
register) automat ically places the PLDs into stand-
by if no inputs are changing. Turning the Turbo
mode off increases propagation delays while re-
ducing power consumption. See the section enti-
tled “Power Management”, on page 59, on how to
set the Turbo bit.
Additionally, five bits are available in the PMMR2
register to block MCU control signals from entering
the PLDs. This reduces power consumption and
can be used only when these MCU control signals
are not used in PLD l ogic equat ions.
Each of the two PLDs has unique characteristics
suited for its applications. They are described in
the following sections.
Input Source Input Name Number
of
Signals
MCU Address Bus1A15-A0 16
MCU Control Signals CNTL0-CNTL2 3
Reset RST 1
Power-down PDN 1
Port A Input
Macrocells PA7-PA0 8
Port B Input
Macrocells PB7-PB0 8
Port C Input
Macrocells PC7-PC0 8
Port D Inputs PD3-PD0 4
Port F Inputs PF7- PF0 8
Page Register PGR7-PGR0 8
Macrocell A Feedback MCELLA.FB7-FB0 8
Macrocell B Feedback MCELLB.FB7-FB0 8
Flash memory
Program Status Bit Ready/Busy 1
PSD4235G2
32/89
Figure 12. PLD Diagram
PLD INPUT BUS
8
INPUT MACROCELL & INPUT PORTS
DIRECT MACROCELL INPUT TO MCU DATA BUS
CSIOP SELECT
SRAM SELECT
SECONDARY NON-VOLATILE MEMORY SELECTS
DECODE PLD
PAGE
REGISTER
PERIPHERAL SELECTS
JTAG SELECT
CPLD
PT
ALLOC.
MACROCELL
ALLOC.
MCELLA
MCELLB
DIRECT MACROCELL ACCESS FROM MCU DATA BUS
24 INPUT MACROCELL
(PORT A,B,C)
16 OUTPUT
MACROCELL
I/O PORTS
PRIMARY FLASH MEMORY SELECTS
12 PORT D and PORT F INPUTS
TO PORT A
TO PORT B
DATA
BUS
8
8
8
4
3
1
2
1
EXTERNAL CHIP SELECTS
TO PORT C or PORT F
8
82
16
82
24
OUTPUT MACROCELL FEEDBACK
AI05737
33/89
PSD4235G2
DECODE PLD (DPL D)
The DPLD, shown in Figure 13, is used for decod-
ing the address for internal and external compo-
nents. The DPLD can be used to generate the
following decode signals:
■8 Sector Select (FS0-FS7) signals for the
primary Flash memory (three product terms
each)
■4 Sector Select ( CS BOOT0-CSBOOT3) signals
for the secondary Flash memory (three product
terms each)
■1 internal SRAM Select (RS0) signal (three
product terms)
■1 internal CSIOP Select (PSD Co nfiguration
Register) signal
■1 JTAG Select signal (enables JTAG-ISP on
Port E)
■2 internal Peripheral Select signals
(Peripheral I/O mode).
Figure 13. DPLD Logic Array
Note: 1. The ad dress inputs ar e A1 9-A4 whe n i n 80C51XA mode
2. Additional address lines can be brought ino the PSD via Port A, B, C, D, or F.
(INPUTS)
(32)
(8)
(16)
(1)
PDN (APD OUTPUT)
I/O PORTS (PORT A,B,F)
(8)
PGR0 -PGR7
(8)
MCELLAB.FB [7:0] (FEEDBACKS)
MCELLBC.FB [7:0] (FEEDBACKS)
A[15:0]*
(4)
(3)
PD[3:0] (ALE,CLKIN,CSI)
CNTRL[2:0] (READ/WRITE CONTROL SIGNALS)
(1)
(1)
RESET
RD_BSY
RS0
CSIOP
PSEL0
PSEL1
8 PRIMARY FLASH
MEMORY SECTOR SELECTS
SRAM SELECT
I/O DECODER
SELECT
PERIPHERAL I/O MODE
SELECT
CSBOOT 0
CSBOOT 1
CSBOOT 2
CSBOOT 3
FS0
FS7
3
3
3
3
3
3
3
3
3
3
3
3
3
JTAGSEL
AI05738
FS1
FS2
FS3
FS6
FS5
FS4
1
1
1
1
PSD4235G2
34/89
COMPLEX PLD (CPLD )
The CPLD can be used to implement system logic
functions, such as loadable count ers and shift reg-
isters, system m ailboxes, ha ndshaking protocols,
state machines, and random logic. The CPLD can
also be used to generate e ight External Chip Se-
lect (E CS 0-ECS 7), routed to Port C or Port F.
Although External Chip Select (ECS0-ECS7) can
be produced by any Output Macrocell (OMC),
these eight Exter nal Chip Select (ECS0-ECS7) on
Port C or Port F do not consume any Output M ac-
roce l l s (O M C).
As shown in Figure 12, the CPLD has the following
blocks:
■24 Input Macroc ells (IMC)
■16 Output Macroc ells (OMC )
■Product Term Allocator
■AND Array capable of generating up to 196
product terms
■Four I/O Ports .
Each of the blocks are described in the sections
that follo w .
The Input Macrocells (IMC) and Output Macrocells
(OMC) are connected to the PSD internal data bus
and can be directly accessed by the MCU. This
enables the MCU software to load data into the
Output Macrocells (OMC) or read data from both
the Input and Output Macrocells (IMC and OMC) .
This feature allows efficient implementation of sys-
tem logic an d eliminates the need to connect the
data bus to the AND Array as required in most
standard PLD macrocell architectures.
Figure 14. Macrocell and I/O Port
I/O PORTS
CPLD MACROCELLS
INPUT MACROCELLS
LATCHED
ADDRESS OUT
MUX
MUX
MUX
MUX MUX
D
D
Q
Q
Q
G
D
QD
WR
WR
PDR
DATA
PRODUCT TERM
ALLOCATOR
DIR
REG.
SELECT
INPUT
PRODUCT TERMS
FROM OTHER
MACROCELLS
POLARITY
SELECT
UP TO 10
PRODUCT TERMS
CLOCK
SELECT
PR DI LD
D/T
CK
CL
Q
D/T/JK FF
SELECT
PT CLEAR
PT
CLOCK
GLOBAL
CLOCK
PT OUTPUT ENABLE (OE)
MACROCELL FEEDBACK
I/O PORT INPUT
ALE/AS
PT INPUT LATCH GATE/CLOCK
MCU LOAD
PT PRESET MCU DATA IN
COMB.
/REG
SELECT
PLD INPUT BUSPLD INPUT BUS
MCU ADDRESS / DATA BUS
MACROCELL
OUT TO
MCU
DATA
LOAD
CONTROL
AND ARRAY
CPLD OUTPUT
I/O PIN
AI04945
35/89
PSD4235G2
Output Macrocell (OMC). Eight of the Output
Macrocells (OMC) are connected to Ports A pins
and are named as McellA0-McellA7. The other
eight Macrocells are connected to Ports B pins
and are named as McellB0-McellB7.
The Output Macrocell (OMC) architecture is
shown in Figure 1 5. As shown in the figure, there
are native product terms available from the AND
Array, and borrowed product terms available (if
unused) from other Output Macrocells (OMC). The
polarity of the product term is controlled by the
XOR gate. The Output Macrocell (OMC) can im-
plement either sequential logic, using the fl ip-flop
element, or combinatorial logic. The multiplexer
selects between the sequential or combinatorial
logic outputs. The multiplexer output can drive a
port pin and has a feedback path t o the AND Array
inputs.
The flip-flop i n the Output Mac rocell (OM C) block
can be configured as a D, T, JK, or SR type in the
PSDsoft Express program. The flip-flop’s clock,
preset, and clear inputs may be driven from a
product term of the AND Array. Alternatively, the
external CLKIN (PD1) signal can be used for the
clock input to the flip-flop. The flip-flop is clocked
on the r ising edge of CLKIN (PD1). The preset and
clear are active High in puts. Each clear i nput can
use up to two product terms.
Table 33. Outp ut Macrocell Port and Data Bit Assignme nts
Output
Macrocell Port
Assignment Native Product
Terms
Maximum
Borrowed
Product Terms
Data Bit for
Loading or
Reading
Motorola 16-Bit
MCU for Loading or
Reading
McellA0 Port A0 3 6 D0 D8
McellA1 Port A1 3 6 D1 D9
McellA2 Port A2 3 6 D2 D10
McellA3 Port A3 3 6 D3 D11
McellA4 Port A4 3 6 D4 D12
McellA5 Port A5 3 6 D5 D13
McellA6 Port A6 3 6 D6 D14
McellA7 Port A7 3 6 D7 D15
McellB0 Port B0 4 5 D8 D0
McellB1 Port B1 4 5 D9 D1
McellB2 Port B2 4 5 D10 D2
McellB3 Port B3 4 5 D11 D3
McellB4 Port B4 4 6 D12 D4
McellB5 Port B5 4 6 D13 D5
McellB6 Port B6 4 6 D14 D6
McellB7 Port B7 4 6 D15 D7
PSD4235G2
36/89
Figure 15. CPLD Output Macrocell
Product Term A l lo ca tor. The CPLD has a Prod-
uct Term Allocator. PSDsoft Express, uses the
Product Term Alloc ator to b orrow and pl ace prod-
uct terms from one Macrocell to another. The fol-
lowing list summarizes how product terms are
allocated:
■McellA0-M ce llA7 all have three native product
terms and may borrow up to six more
■McellB0-M ce llB3 all have four native product
terms and may borrow up to five more
■McellB4-M ce llB7 all have four native product
terms and may borrow up to six m ore.
Each Macrocell may only borrow product terms
from certain other Macrocells. Product terms al-
ready in use by one Macrocell are not available for
another Macrocell.
If an equation requires more product terms than
are available to it, then “external” product terms
are required, which consum e other Output Macro-
cells (OMC). If external product terms are used,
extra delay is added for the equation that required
the extra product terms. This is called product term
expansion. PSDsoft Express performs thi s expan-
sion as needed.
Loading and Reading the Output Macrocells
(OMC). The Output Macrocells (OMC) block oc-
cupies a memory location in the MCU address
space, as defined by the CSIOP (see the section
entitled “I/O Ports”, on page 50). The flip-flops in
each of the 16 Output Macrocells (OMC) can be
loaded fr om the da ta bus b y a MCU. L oading the
Output Macrocells (OMC) with data from the MCU
takes priority ov er i nternal functions. As s uch, the
preset, clear, and clock inputs to the flip-flop can
be overridden by the MCU. The ability to load the
flip-flops and read t hem back is useful in such ap-
plications as loadable counters and shift regi sters,
mailboxes, and hands haking protoc ols.
Data is loaded to the Output Macrocells (OMC) on
the trailing edge of Write Strobe (WR/WRL,
CNTL0).
Th e OMC Mask Register. There is one Mask
Register for each of t he two groups of eight Output
Macrocells (OMC). The Mask Registers can be
used to block the loading of data to individual Out-
put Macrocells (OMC). The default value for the
Mask Registers is 00h, which allows loadi ng of the
Output Macrocells (OMC). When a given bit in a
Mask Register is set to a 1, the MCU is blocked
from writing to the associated Output Macrocells
PT
ALLOCATOR
MASK
REG.
PT CLK
PT
PT
PT
CLKIN
FEEDBACK (.FB)
PORT INPUT
AND ARRAY
PLD INPUT BUS
MUX
MUX
POLARITY
SELECT
LD
IN
CLR
Q
PRDIN
COMB/REG
SELECT
PORT
DRIVER
INPUT
MACROCELL
I/O PIN
INTERNAL DATA BUS
DIRECTION
REGISTER
CLEAR (.RE)
PROGRAMMABLE
FF (D/T/JK/SR)
WR
ENABLE (.OE)
PRESET(.PR)
RD
MACROCELL CS
AI04946
37/89
PSD4235G2
(OMC). For example, suppose McellA0-McellA3
are being used for a state machine. You would not
want a MCU write t o M cellA to o verwrite the state
machine registers. Therefore, you would want to
load the Mask Register for McellA (Mask Macro-
cell A) with the value 0Fh.
The Outp ut Enable of the OM C. The Output
Macrocells (OMC) can be connected to an I/O port
pin as a PLD output. The output enable of each
port pin driver is controlled by a single product
term from the AND Array, ORed with the Direction
Register output. The pin is enabled upon Power-
up if no output enable equation is defined and if
the pin is declared as a PLD output in PSDsoft E x-
press.
If the Output Macrocell (OMC) output is declared
as an internal node and not as a port p in output in
the PSDabel file, t hen the port pin can be used for
other I/O functions. The internal node feedback
can be routed as an input to the AND Array.
In put Macro cells (IMC). T he CPLD has 24 Input
Macrocells (IMC), one for each pin on Ports A, B,
and C. The architecture of the Input Macrocells
(IMC) is shown in Figure 16. The Input Macrocells
(IMC) are individually configurable, and can be
used as a latch, register, or to pass incoming Port
signals prior to driving them onto the PLD input
bus. The out puts of the Input Macrocells (IMC) can
be read by the MCU through the internal data bus.
The enable for t he latch a nd cloc k f or the regi ster
are driven by a multiplexer whose inputs are a
product term from the CPLD AND Array or the
MCU Address Strobe (ALE/AS). Each product
term output is used to latch or clock four Input
Macrocells (IMC). Port inputs 3-0 can be con-
trolled by one product term and 7-4 by another.
Configurations for the Input Macrocells (IMC) are
specified by PSDsoft Express (see Application
Note
AN1171
). Outputs of the Input Macrocells
(IMC) can be read by the MCU via the IMC buffer .
See the section entitled “I/O Ports”, on page 50.
Input Macrocells (IMC) can use Address Strobe
(ALE/AS, PD0) to latch address bits higher than
A15. Any latched addresses are routed to the
PLDs as inputs.
Input Macrocells (IMC) are particularly us eful with
handshaking communication applications where
two processors pass data back and fo rth th ro ugh
a common mailbox. Figure 18 shows a typical con-
figuration where the Master MCU writes to t he Port
A Data Out Register. This, in turn, can be read by
the Slave MCU via the activation of the “Slave-
Read” output enable product term.
The Slave can also write to t he Port A Input Mac-
rocells (IMC) and the Master can then read the In-
put Macrocell s (IMC) direct ly.
Note that the “Slave-Read” and “Slave-Wr” signals
are product terms that are derived from the Slave
MCU inputs Read Strobe (RD, CNTL1), Write
Strobe (WR /WRL, CNT L0), and Slave_CS.
PSD4235G2
38/89
Figure 16. Input Macrocell
External Chip Select. The CPLD also provides
eight External Chip Select (ECS0-ECS7) outputs
that can be used to select external devices. Each
External Chip Select (ECS0-ECS7) consists of
one product term that can be configured active
High or Low.
The output enable of the pin is controlled by either
the output enable product term or the Direction
Register. (See Figure 17.)
Figure 17. External Chip Select Signal
OUTPUT
MACROCELLS A
AND
MACROCELLS B
PT
PT
FEEDBACK
AND ARRAY
PLD INPUT BUS
PORT
DRIVER
I/O PIN
INTERNAL DATA BUS
DIRECTION
REGISTER
MUX
MUX
ALE/AS
PT
Q
Q
D
D
G
LATCH INPUT MACROCELL
ENABLE (.OE)
D FF
INPUT MACROCELL_ RD
AI04926
PLD INPUT BUS
POLARITY
BIT
PORT PIN
ECS PT ECS
To Port C or F
ENABLE (.OE) PT DIRECTION
REGISTER
CPLD AND ARRAY
Port C or Port F
AI04927
39/89
PSD4235G2
Figure 18. Handshaking Communication Using Input Macrocells
MASTER
MCU
MCU-RD
MCU-RD
MCU-WR
SLAVE–WR
SLAVE–CS
MCU-WR
D[7:0]
D[7:0]
CPLD DQ
QD
PORT A
DATA OUT
REGISTER
PORT A
INPUT
MACROCELL
PORT A
SLAVE–READ
SLAVE
MCU
RD
WR
AI02877C
PSD
PSD4235G2
40/89
MCU BUS INTERFACE
The “no-glue logic” MCU Bus Interface block can
be directly connected to most popular MCUs and
their control signals. Key 16-bit MCUs, with their
bus types and c ontrol signal s, are shown i n Tab le
34. T he M CU interface type i s specif ied using t he
PSDsoft Express.
PSD Interface to a Multiplexed Bus. Figure 19
shows an ex am ple of a system using a MCU with
a 16-bit multiplexed bus and a PSD4235G2. The
ADIO port on the P SD is connected directly to the
MCU address/data bus. A ddress Strobe (ALE/AS,
PD0) latches the address signals internally.
Latched addresses can be brought out to Port E, F
or G. The PSD drives the ADIO data bus only
when one of it s internal r esourc es is accessed and
Read Strobe (RD, CNTL1) is active. Should the
system addres s bus exceed s ixteen bits, Ports A,
B, C, or F may be used a s a dditional address in-
puts.
PSD Interface to a Non-Multiplexed 8-Bit Bus.
Figu re 20 shows an example of a system using a
MCU with a 16-bit non-multiplexed bus and a
PSD4235G2. The address bus is connected t o the
ADIO Port, and the data bus is c onnected to Ports
F and G. Ports F and G are in tri-state m ode when
the PS D is not acc essed by the MCU. S houl d the
system addres s bus exceed s ixteen bits, Ports A,
B, or C may be used for additional address inputs.
Table 34. MCUs an d their Control Signals
Not e: 1. Unused CNTL2 pin can be configured as CPLD input. Other unused pins (PD3-PD0, PF3-PF0) can be configured for other I/O func-
tions.
2. ALE /A S input is opti onal for MC Us with a non-m ul t iplexed bu s
MCU CNTL0 CNTL1 CNTL2 PD3 PD02ADIO0 PF3-PF0
68302, 68306, MMC2001 R/W LDS UDS (Note 1)AS —(Note 1)
68330, 68331, 68332, 68340 R/W DS SIZ0 (Note 1)AS A0 (Note 1)
68LC302, MMC2001 WEL OE —WEH AS — (Note 1)
68HC16 R/W DS SIZ0 (Note 1)AS A0 (Note 1)
68HC912 R/W E LSTRB DBE EA0
(Note 1)
68HC812 3 R/W E LSTRB (Note 1) (Note 1)A0 (Note 1)
80196 WR RD BHE (Note 1)ALE A0 (Note 1)
80196SP WRL RD (Note 1)WRH ALE A0 (Note 1)
80186 WR RD BHE (Note 1)ALE A0 (Note 1)
80C161, 80C164-80C167 WR RD BHE (Note 1)ALE A0 (Note 1)
80C51XA WRL RD PSEN WRH ALE A4/D0 A3-A1
H8/300 WRL RD (Note 1)WRH AS A0 —
M37702M2 R/W E BHE (Note 1)ALE A0 (Note 1)
41/89
PSD4235G2
Figure 19. An Exam p le of a Typical 16-bit Multiplexed Bus Interface
Figure 20. An Exam p le of a Typical 16-bit Non-Multiplexed Bus Interface
MCU
WR
RD
BHE
ALE
RESET
AD[7:0]
AD[15:8]
A[15:8]
A[7:0]
ADIO
PORT
PORT
F
PORT
G
PORT
A, B
or C
WR (CNTRL0)
RD (CNTRL1)
BHE (CNTRL2)
RST
ALE (PD0)
PORT D
(OPTIONAL)
(OPTIONAL)
PSD
AI04928
A[23:16]
(OPTIONAL)
MCU
WR
RD
BHE
ALE
RESET
D[15:0]
A[15:0]
D[15:8]
D[7:0]
ADIO
PORT
PORT
F
PORT
G
PORT
A, B
or C
WR (CNTRL0)
RD (CNTRL1)
BHE (CNTRL2)
RST
ALE (PD0)
PORT D
PSD
AI04929
A[23:16]
(OPTIONAL)
PSD4235G2
42/89
Data Byte Enable Reference. MCUs have differ-
ent data byte orientations. Table 35 to Table 38
show how the PSD4235G2 interprets byte/word
operations in different bus write configurations.
Even-byte refers to locations with address A0
equal to 0, and odd byte as locations with A0 equal
to 1.
Table 35. 16-Bit Data Bus with BHE
MCU Bus Interface Exa mples. Figure 21 to Fig-
ure 26 show examples of the basic connections
between the PSD4235G2 and some popular
MCUs. The PSD4235G2 Control input pins are la-
beled as to the MCU function for which they are
configured. The MCU bus interface is specified us-
ing PSDsoft Express. The Voltage Stand-by (VST-
BY, PE6) line should be held at Ground if not in
use.
Table 36. 16-Bit Data Bus with WRH and WRL
Table 37. 16-Bit Data Bus with SIZ0, A0
(Motorola MCU)
Table 38. 16-Bit Data Bus with LDS, UDS
(Motorola MCU)
BHE A0 D15-D8 D7-D0
0 0 Odd Byte Even Byte
0 1 Odd Byte —
1 0 — Even Byte
WRH WRL D15-D8 D7-D0
0 0 Odd Byte Even Byte
0 1 Odd Byte —
1 0 — Even Byte
SIZ0 A0 D15-D8 D7-D0
0 0 Even Byte Odd Byte
1 0 Even Byte —
1 1 — Odd Byte
WRH WRL D15-D8 D7-D0
0 0 Even Byte Odd Byte
1 0 Even Byte —
0 1 — Odd Byte
43/89
PSD4235G2
Figure 21. Interfacing the PSD with an 80C196
80C196 and 80C186 . In Figure 21, the Intel
80C196 MCU, which has a 16-bit multiplexed ad-
dress/data bus, is shown connected to a
PSD4235G2. The Read Strobe (RD, CNTL1), and
Write Strobe ( WR/WRL, C NTL0) signals are con-
nected to the CNTL pin s. Whe n BHE is not used,
the PSD can be configured to receive WRL and
Write Enable High-byte (WRH/DBE, PD3) fro m the
MCU. Higher address inputs (A16-A19) can be
routed to P orts A, B, or C as i nput ot the PLD.
The AMD 80186 family has the same bus connec-
tion to the P SD as the 80C196.
X1
X2
P1.0/EPA0/T2CLK
P1.1/EPA1
P1.2/EPA2/T2DIR
P1.3/EPA3
P1.4/EPA4
P1.5/EPA5
P1.6/EPA6
P1.7/EPA7
P3.0/AD0
P3.1/AD1
P3.2/AD2
P3.3/AD3
P3.4/AD4
P3.5/AD5
P3.6/AD6
P3.7/AD7
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PA0
PA2
PA1
PA3
PA4
PA5
PA6
PA7
P4.0/AD8
P4.1/AD9
P4.2/AD10
P4.3/AD11
P4.4/AD12
P4.5/AD13
P4.6/AD14
P4.7/AD15
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
CNTL0 (WR)
CNTL1 (RD)
CNTL2 (BHE)
PD0 (ALE)
PD1 (CLKIN)
PD2 (CSI)
RESET
RD/P5.3
WR/WRL/P5.2
BHE/WRH/P5.5
ALE/ADV/P5.0
INST/P5.1
SLPINT/P5.4
RESET
31
32
33
34
35
36
37
38
3
19
18
57
56
55
54
53
52
51
50
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
4
5
6
7
10
11
12
13
14
15
16
17
18
19
20
59
39
60
40
79
80
1
21
22
23
24
25
26
27
28
PSD80C196NT
A19-A16 A[19:16]
7
9
8
4
RD
WR
BHE
ALE
3
1
RESET
51
52
53
54
55
56
57
58
AI04930
AD15-AD0 AD[15:0]
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC2
PC1
PC3
PC4
PC5
PC6
PC7
61
62
63
64
65
66
67
68
41
42
43
44
45
46
47
48
PD3 (WRH)
2
PE0 (TMS)
PE1 (TCK/ST)
PE2 (TDI)
PE3 (TDO)
PE4 (TSTAT/RDY)
PE5 (TERR)
PE6 (VSTBY)
PE7 (VBATON)
71
72
73
74
75
76
77
78
8 30495070
GNDGNDGNDGNDGND
92969
VCC VCC VCC
VCC
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
3
4
5
6
7
10
11
12
13
14
15
16
17
18
19
20
EP.0/A16
EP.1/A17
EP.2/A18
EP.3/A19
14
13
12
11
31
BUSWIDTH/P5.7 10
EA 33
RESET
READY/P5.6 2
P2.0/TX/PVR
P2.1/RXD/PALE
P2.2/EXINT/PROG
P2.3/INTB
P2.4/INTINTOUT
P2.5/HLD
P2.6/HLDA/CPVER
P2.7/CLKOUT/PAC
36
37
38
39
40
41
42
43
P6.0/EPA8
P6.1/EPA9
P6.2/T1CLK
P6.3/T1DIR
P6.4/SC0
P6.5/SD0
P6.6/SC1
P6.7/SD1
58
59
60
61
62
63
64
65
NMI
VREF
VPP
ANGND
ACH4/P0.4/PMD.0
ACH5/P0.5/PMD.1
ACH6/P0.6/PMD.2
ACH7/P0.7/PMD.3
32
49
6
48
44
45
46
47 A16
A17
A18
A19
A16
A17
A18
A19
PSD4235G2
44/89
Figure 22. Interfacing the PSD with an MC68331
MC683xx and MC68H C16. Figure 22 shows a
MC68331 with a 16-bit non-multiplexed data bus
and 24-bit address bus. The data bus from the
MC68331 is connected to Port F (D0-D7) and P or t
G (D8-D15). The SIZ0 and A0 inputs determine
the high/low byte selection. The R/W, DS and SIZ0
signals are connected to the CNTL0-CNTL2 pins.
The MC68HC16, and other members of the
MC683x x f am ily, has the s ame bu s connection to
the PSD as the MC68331 shown in Figure 22.
VCC_BAR
D[15:0]
A16
A5
D1
D13
DS\
AS
A8
D12
A1
A18
A19
A23
D4
D12
D8
A22
D7
D3
A[23:0]
D3
D11
A16
A17
D14
D13
A3 D2
D5
A19
A0
A12
D2
A4
R/W\
D6
D5
RESET\
A7
A2
A13
A14
A15
D7
D9
D10
D15
D4
A17
A6
SIZ0
D10
D15
A18
A21
A11
D0
D1
D6
D11
D14
D9
D0
A20
D8 A9
A10
MC68331
A1 20
A2 21
A3 22
A4 23
A5 24
A6 25
A7 26
A8 27
A9 30
A10 31
A11 32
A12 33
A13 35
A14 36
A15 37
A16 38
A17 41
A18 42
A19_CS6/ 121
A20_CS7/ 122
A21_CS8/ 123
A22_CS9/ 124
A23_CS10/ 125
R_W 79
AS 82
D0
111
D1
110
D2
109
D4
105
D5
104
D6
103
D7
102
D8
100
D9
99
D10
98
D11
97
D13
93
D14
92
D15
91
A0 90
D3
108
D12
94
DS 85
SIZ0 81
SIZ1 80
CSBOOT/ 112
BR_CS0/ 113
BG_CS1/ 114
BGACK_CS2/ 115
FC0_CS3/ 118
FC1_CS4/ 119
FC2_CS5/ 120
RESET 68
DSACK0
89
DSACK1
88
CLKOUT 66
IRQ1
77
IRQ2
76
IRQ3
75
IRQ4
74
IRQ5
73
IRQ6
72
IRQ7
71
PSD
ADIO0
3
ADIO1
4
ADIO2
5
ADIO3
6
ADIO4
7
ADIO5
10
ADIO6
11
ADIO7
12
ADIO9
14
ADIO10
15
ADIO11
16
ADIO12
17
ADIO13
18
ADIO14
19
ADIO15
20
PF0 31
PF1 32
PF2 33
PF3 34
PF4 35
PF5 36
PF6 37
PF7 38
PG1 22
PG2 23
PG3 24
PG4 25
PG5 26
PG6 27
PG7 28
PA5 56
PA6 57
PA7 58
CNTL0(R/W)
59
CNTL1(DS)
60
CNTL2 (SIZ0)
40
PD0 (AS)
79
RESET
39
ADIO8
13 PG0 21
PA3 54
PA4 55
PA2 53
PA0 51
PA1 52
PB0 61
PB1 62
PB2 63
PB3 64
PB4 65
PB5 66
PB6 67
PB7 68
PC0 41
PC1 42
PC2 43
PC3 44
PC4 45
PC5 46
PC6 47
PC7 48
PE0 (TMS)
71
PE1 (TCK/ST)
72
PE2 (TDI)
73
PE3 (TDO)
74
PE4 (TSTAT/RDY)
75
PE5 (TERR)
76
PE7 (VBATON)
78
Vcc 29
Vcc 69
Vcc 9
GND
50 GND
49 GND
30 GND
8
GND
70
PD2 (CSI)
1PD1 (CLKIN)
80
PD3
2
PE6 (VSTBY)
77
RESET\
A[23:0]
D[15:0]
AI04951b
45/89
PSD4235G2
Figure 23. Interfacing the PSD with an 80C51XA-G3
80C51XA. The Philips 80C 51XA MCU h as a 16-
bit multiplexed bus with burst cycles. Address bits
(A3-A1) are not multiplexed, while (A19-A4) are
multiplexed with data bits (D15-D0).
The PSD4235G2 supports the 80C51XA burst
mod e. The WRH sig nal i s connected to P D3, and
WHL is connected to CNTL0. The RD and PSEN
signals are connected to the CNTL1 and CNTL2
pins. Figure 23 shows the schematic diagram.
The 80C51XA improves bus throughput and per-
formance by issuing burst cycles to fetch codes
fr om memory. In burst cycle s, address A19 -A4 are
latched internally by the PSD , whil e the 80C51XA
drives the A3-A1 signals to f etch sequentiall y up to
16 bytes of code. The PSD access time is then
measured from address A3-A1 valid to data in val-
id. The P SD bus t iming req uirem ent in a burs t cy-
cle is identical to the normal bus cycle, except the
address setup and hold time with respect to Ad-
dress Strobe (ALE/AS, PD0) is not requi red.
VCC_BAR
VCC_BAR
D[15:0]
WRL\
RD\
PSEN\
ALE
A4D0
A5D1
A6D2
A7D3
A8D4
A9D5
A10D6
A11D7
A12D8
A13D9
A14D10
A15D11
A16D12
A17D13
A18D14
A19D15
RESET\
RESET\
A3
A2
A1
WRH\
A[3:1]
A1
A2
A3
U3
CRYSTAL
PSD
ADIO0
3
ADIO1
4
ADIO2
5
ADIO3
6
ADIO4
7
ADIO5
10
ADIO6
11
ADIO7
12
ADIO9
14
ADIO10
15
ADIO11
16
ADIO12
17
ADIO13
18
ADIO14
19
ADIO15
20
PF0 31
PF1 32
PF2 33
PF3 34
PF4 35
PF5 36
PF6 37
PF7 38
PG1 22
PG2 23
PG3 24
PG4 25
PG5 26
PG6 27
PG7 28
PA5 56
PA6 57
PA7 58
CNTL0(WR)
59
CNTL1(RD)
60
CNTL2(PSEN)
40
PD0 (ALE)
79
RESET
39
ADIO8
13 PG0 21
PA3 54
PA4 55
PA2 53
PA0 51
PA1 52
PB0 61
PB1 62
PB2 63
PB3 64
PB4 65
PB5 66
PB6 67
PB7 68
PC0 41
PC1 42
PC2 43
PC3 44
PC4 45
PC5 46
PC6 47
PC7 48
PE0 (TMS)
71
PE1 (TCK/ST)
72
PE2 (TDI)
73
PE3 (TDO)
74
PE4 (TSTAT/RDY)
75
PE5 (TERR)
76
PE7 (VBATON)
78
Vcc 29
Vcc 69
Vcc 9
GND
50 GND
49 GND
30 GND
8
GND
70
PD2 (CSI)
1PD1 (CLKIN)
80
PD3 (WRH)
2
PE6 (VSTBY)
77
XA-G3
A0/WRH 2
A1 3
A2 4
A3 5
A4D0 43
A5D1 42
A6D2 41
A7D3 40
A8D4 39
A9D5 38
A10D6 37
A11D7 36
A12D8 24
A13D9 25
A14D10 26
A15D11 27
A16D12 28
A17D13 29
A18D14 30
A19D15 31
PSEN 32
RD 19
WRL 18
ALE 33
RST
10
INT0
14
INT1
15
EA/WAIT
35
BUSW
17
XTAL1
21
XTAL2
20
RXD0
11
TXD0
13
RXD1
6
TXD1
7
T2EX
9
T2
8
T0
16
D[15:0]
A[3:1]
AI04952b
PSD4235G2
46/89
Figure 24. Interfacing the PSD with an H83/2350
H8/300. Figure 24 shows an Hitachi H8/ 2350 with
a 16-bit non-multiplexed data bus, and a 24-bit ad-
dress bus. T he H8 dat a bus is connected to Port F
(D0-D7) and Port G (D8-D15).
The WRH signal is connected to PD3, and WHL is
connected to CNTL0. The RD signal is connect ed
to CNTL1. The connection to the Address Strobe
(AS) signal is optional, and is required if the ad-
dresses are to be latched.
VCC_BAR
AS
RESET\
RD\
RESET\
WRL\
A21
A3
A[23:0]
A11
A1
A9
A14
A15
A20
A5
A8
A13
A10
A7
A18
A19
A17
A2
A16
A4
A6
A12
A0
D4
D9
D10
D15
D8
D7
D[15:0]
D2
D5
D0
D11
D13
D3
D14
D1
D6
D12
WRH\
A22
A23
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A16
A17
A18
A19
U3
CRYSTAL
H8S/2655
PC0/A0 2
PC1/A1 3
PC2/A2 4
PC3/A3 5
PC4/A4 7
PC5/A5 8
PC6/A6 9
PC7/A7 10
PB0/A8 11
PB1/A9 12
PB2/A10 13
PB3/A11 14
PB4/A12 16
PB5/A13 17
PB6/A14 18
PB7/A15 19
PA0/A16 20
PA1/A17 21
PA2/A18 22
PA3/A19 23
PA4/A20/IRQ4 25
PA5/A21/IRQ5 26
PA6/A22/IRQ6 27
PA7/A23/IRQ7 28
CS7/IRQ3
29
CS6/IRQ2
30
IRQ1
31
IRQ0
32
RXD0
55
TXD0
53
SCK0
57
RXD1
56
TXD1
54
SCK1
58
RXD2
90
TXD2
89
SCK2
91
PF0/BREQ
88
PF1/BACK
87
PF2/LCAS/WAIT/B
86
NMI
74
PO0/TIOCA3
71
PO1/TIOCB3
70
PO2/TIOCC3/TMRI
69
PO3/TIOCD3/TMCI
68
PO4/TIOCA4/TMRI
67
PO5/TIOCB4/TMRC
66
PO6/TIOCA5/TMRO
65
PO7/TIOCB5/TMRO
64
DREQ/CS4
60
TEND0/CS5
61
DREQ1
62
TEND1
63
PE0/D0
34
PE0/D1
35
PE0/D2
36
PE0/D3
37
PE0/D4
39
PE0/D5
40
PE0/D6
41
PE0/D7
42
PD0/D8
43
PD1/D9
44
PD2/D10
45
PD3/D11
46
PD4/D12
48
PD5/D13
49
PD6/D14
50
PD7/D15
51
RD 83
LWR 85
HWR 84
AS 82
PF0/PHI0
80
RESET 73
WDTOVF 72
MOD0
113
MOD1
114
MOD2
115
STBY 75
EXTAL
78
XTAL
77
PG0/CAS/OE 116
PG1/CS3 117
PG2/CS2 118
PG3/CS1 119
PG4/CS0 120
PO8/TIOCA0/DACK 112
PO9/TIOCB0/DACK 111
PO10/TIOCC0/TCL 110
PO11/TIOCD0/TCL 109
PO12/TIOCA1 108
PO13/TIOCB1/TCL 107
PO14/TIOCA2 106
PO15/TIOCB2/TCL 105
AN0 95
AN1 96
AN2 97
AN3 98
AN4 99
AN5 100
AN6/DA0 101
AN7/DA1 102
ADTRG 92
PSD
ADIO0
3
ADIO1
4
ADIO2
5
ADIO3
6
ADIO4
7
ADIO5
10
ADIO6
11
ADIO7
12
ADIO9
14
ADIO10
15
ADIO11
16
ADIO12
17
ADIO13
18
ADIO14
19
ADIO15
20
PF0 31
PF1 32
PF2 33
PF3 34
PF4 35
PF5 36
PF6 37
PF7 38
PG1 22
PG2 23
PG3 24
PG4 25
PG5 26
PG6 27
PG7 28
PA5 56
PA6 57
PA7 58
CNTL0(WRL)
59
CNTL1(RD)
60
CNTL2
40
PD0 (AS)
79
RESET
39
ADIO8
13 PG0 21
PA3 54
PA4 55
PA2 53
PA0 51
PA1 52
PB0 61
PB1 62
PB2 63
PB3 64
PB4 65
PB5 66
PB6 67
PB7 68
PC0 41
PC1 42
PC2 43
PC3 44
PC4 45
PC5 46
PC6 47
PC7 48
PE0 (TMS)
71
PE1 (TCK/ST)
72
PE2 (TDI)
73
PE3 (TDO)
74
PE4 (TSTAT/RDY)
75
PE5 (TERR)
76
PE7 (VBATON)
78
Vcc 29
Vcc 69
Vcc 9
GND
50 GND
49 GND
30 GND
8
GND
70
PD2 (CSI)
1PD1 (CLKIN)
80
PD3 (WRH)
2
PE6 (VSTBY)
77
A[23:0]
D[15:0]
AI04953b
47/89
PSD4235G2
Figure 25. Interfacing the PSD with an MMC2001
MMC2001. The Motorola MCORE MMC2001
MCU has a MOD input pin that selects interal or
external boot ROM. The PSD can be configured
as the external flash boot ROM or as extension to
the internal ROM.
The MMC2001 has a 16-bit external data bus and
20 addres s lin es with external chip select signal s.
The Chip Select Control Registers allow the user
to customize the bus interface and timin g to fit the
individual system requirement. A typical interface
configuaration to the PSD is shown in Figure 25.
The MMC2001’s R/W signal is conneced to the
CNTL0 pin, while EB0 and EB1 (enable byte-0 and
enable byte-1) are connected t o the CNTL1 (UDS)
and CNTL2 (LDS) pins. The WEN bit in the C hip
Select Control Register should be set to 1 to termi-
nate the EB0-EB1 earlier to pr ovide the wrt i e data
hold tim e for the PSD. The WSC and WWS bits in
the Control Register are set to wait states that
meet the PSD access time requiremen t.
VCC_BAR VCC_BAR
A16
ALE
AD14
AD10
AD6
A17
A19
RD\
AD13
AD9
AD5
AD1
RESET\
A19
BHE\
AD7
A[19:16]
A17
AD[15:0]
AD12
AD4
AD2
A18
WR\
AD15
AD8
A18
AD11
A16
RESET\
AD3
AD0
U3
CRYSTAL
PSD
ADIO0
3
ADIO1
4
ADIO2
5
ADIO3
6
ADIO4
7
ADIO5
10
ADIO6
11
ADIO7
12
ADIO9
14
ADIO10
15
ADIO11
16
ADIO12
17
ADIO13
18
ADIO14
19
ADIO15
20
PF0 31
PF1 32
PF2 33
PF3 34
PF4 35
PF5 36
PF6 37
PF7 38
PG1 22
PG2 23
PG3 24
PG4 25
PG5 26
PG6 27
PG7 28
PA5 56
PA6 57
PA7 58
CNTL0(WR)
59
CNTL1(RD)
60
CNTL2(BHE)
40
PD0 (ALE)
79
RESET
39
ADIO8
13 PG0 21
PA3 54
PA4 55
PA2 53
PA0 51
PA1 52
PB0 61
PB1 62
PB2 63
PB3 64
PB4 65
PB5 66
PB6 67
PB7 68
PC0 41
PC1 42
PC2 43
PC3 44
PC4 45
PC5 46
PC6 47
PC7 48
PE0 (TMS)
71
PE1 (TCK/ST)
72
PE2 (TDI)
73
PE3 (TDO)
74
PE4 (TSTAT/RDY)
75
PE5 (TERR)
76
PE7 (VBATON)
78
Vcc 29
Vcc 69
Vcc 9
GND
50 GND
49 GND
30 GND
8
GND
70
PD2 (CSI)
1PD1 (CLKIN)
80
PD3 (WRH)
2
PE6 (VSTBY)
77
Infineon C167CR
AD0 100
AD1 101
Vcc 109
AD2 102
AD3 103
AD4 104
AD5 105
AD6 106
AD7 107
AD8 108
AD9 111
AD10 112
AD11 113
AD12 114
AD13 115
AD14 116
AD15 117
EA 99
ALE 98
READY
97
WR/WRL 96
RD 95
Vcc 93
XTAL1
138
XTAL2
137
RSTIN 140
RSTOUT 141
NMI 142
P4.0/A16 85
A17 86
A18 87
A19 88
A20 89
A21 90
A22 91
P4.7/A23 92
P3.0/T0IN
65
P3.1/T6OUT
66
P3.2/CAPIN
67
P3.3/T3OUT
68
P3.4/T3EUD
69
P3.5/T4IN
70
P3.6/T3IN
73
P3.7/T2IN
74
P3.8/MRST
75
P3.9/MTSR
76
P3.10/TXD0
77
P3.11/RXD0
78
P3.12/BHE/WRH 79
P3.13/SCLK
80
P3.15/CLKOUT
81
P1L0 118
P1L1 119
P1L2 120
P1L3 121
P1L4 122
P1L5 123
P1L6 124
P1L7 125
P1H0 128
P1H1 129
P1H2 130
P1H3 131
P1H4 132
P1H5 133
P1H6 134
P1H7 135
P2.0/CC0IO 47
P2.1/CC1IO 48
P2.2/CC2IO 49
P2.3/CC3IO 50
P2.4/CC4IO 51
P2.5/CC5IO 52
P2.6/CC6IO 53
P2.7/CC7IO 54
P2.8/CC8IO/EX0IN 57
P2.9/CC9IO/EX1IN 58
P2.10/CC10IO/EX2IN 59
P2.11/CC11IO/EX3IN 60
P2.12/CC12IO/EX4IN 61
P2.13/CC13IO/EX5IN 62
P2.14/CC14IO/EX6IN 63
P2.15/CC15IO/EX7IN 64
P5.0/AN0
27
P5.1/AN1
28
P5.2/AN2
29
P5.3/AN3
30
P5.4/AN4
31
P5.5/AN5
32
P5.6/AN6
33
P5.7/AN7
34
P5.8/AN8
35
P5.9/AN9
36
P5.10/AN10/T6UED
39
P5.11/AN11/T5UED
40
P5.12/AN12/T6IN
41
P5.13/AN13/T5IN
42
P5.14/AN14/T4UED
43
P5.15/AN15/T2UED
44
P6.0/!CS0
1
P6.1/!CS1
2
P6.2/!CS2
3
P6.3/!CS3
4
P6.4/!CS4
5
P6.5/!HOLD
6
P6.6/!HLDA
7
P6.7/!BREQ
8
P7.0/POUT0
19
P7.1/POUT1
20
P7.2/POUT2
21
P7.3/POUT3
22
P7.4/CC28IO
23
P7.5/CC29IO
24
P7.6/CC30IO
25
P7.7/CC31IO
26
P8.0/CC16IO
9
P8.1/CC17IO
10
P8.2/CC18IO
11
P8.3/CC19IO
12
P8.4/CC20IO
13
P8.5/CC21IO
14
P8.6/CC22IO
15
P8.7/CC23IO
16
Vss
143
Vss
139
Vss
127
Vss
110
Vss
94
Vss
83
Vss
71
Vss
55
Vss
45
Vss
18
Agnd
38
Vcc 144
Vcc 136
Vcc 126
Vcc 82
Vcc 72
Vcc 17
Vcc 56
Vcc 46
Vref
37
ADIO[15:0]
A[19:16]
AI04954b
PSD4235G2
48/89
Another option i s to configure the EB 0 and EB1 as
WRL and WRH signals. In this case, the PSD con-
trol setting will be: OE, WRL, WRH where OE is
the read signal f or the MMC2 001.
C16x Family. The PSD supports Infineon’ s C16X
family of MCUs (C161-C167) in both the multi-
plexed and non-multiplexed bus configuration. In
Figure 26, the C167CR is shown connected to the
PSD in a multiplexed bus config uration. The con-
trol signals from the MCU are WR, RD, BHE and
ALE, and are routed to the corresponding PSD
pins.
The C167 has an other contro l signal setting ( RD,
WRL, W RH, ALE) which is also supported by the
PSD.
49/89
PSD4235G2
Figure 26. Interfacing the PSD with a C167CR
XTAL1
XTAL2
P8.0/CC16IO
P8.1/CC17IO
P8.2/CC18IO
P8.3/CC19IO
P8.4/CC20IO
P8.5/CC21IO
P8.6/CC22IO
P8.7/CC23IO
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PA0
PA2
PA1
PA3
PA4
PA5
PA6
PA7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
CNTL0 (WR)
CNTL1 (RD)
CNTL2 (BHE)
PD0 (ALE)
PD1 (CLKIN)
PD2 (CSI)
RESET
RD
WR/WRL
P312/BHE/WRH
ALE
RESET
31
32
33
34
35
36
37
38
3
138
137
9
10
11
12
13
14
15
16
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
4
5
6
7
10
11
12
13
14
15
16
17
18
19
20
59
39
60
40
79
80
1
21
22
23
24
25
26
27
28
PSD
C167CR
A19-A16 A[19:16]
95
96
79
98
RD
WR
BHE
ALE
RESET
51
52
53
54
55
56
57
58
AI04955
AD15-AD0 AD[15:0]
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC2
PC1
PC3
PC4
PC5
PC6
PC7
61
62
63
64
65
66
67
68
41
42
43
44
45
46
47
48
PD3 (WRH)
2
PE0 (TMS)
PE1 (TCK/ST)
PE2 (TDI)
PE3 (TDO)
PE4 (TSTAT/RDY)
PE5 (TERR)
PE6 (VSTBY)
PE7 (VBATON)
71
72
73
74
75
76
77
78
8 30495070
GNDGNDGNDGNDGND
92969
VCC VCC VCC
VCC
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
100
101
102
103
104
105
106
107
108
111
112
113
114
115
116
117
P4.0/A16
P4.1/A17
P4.2/A18
P4.3/A19
85
86
87
88
140
EA 99
RSTIN
P7.0/POUT0
P7.1/POUT1
P7.2/POUT2
P7.3/POUT3
P7.4/CC28IO
P7.5/CC29IO
P7.6/CC30IO
P7.7/CC31IO
19
20
21
22
23
24
25
26
P6.0/!CS0
P6.1/!CS1
P6.2/!CS2
P6.3/!CS3
P6.4/!CS4
P6.5/!HOLD
P6.6/!HLDA
P6.7/!BREQ
1
2
3
4
5
6
7
8
A16
A17
A18
A19
A16
A17
A18
A19
P5.8/AN8
P5.9/AN9
P5.10/AN10/T6UED
P5.11/AN11/T5UED
P5.12/AN12/T6IN
P5.13/AN13
P5.14/AN14/T4UED
P5.15/AN15/T2UED
35
36
39
40
41
42
43
44
P5.0/AN0
P5.1/AN1
P5.2/AN2
P5.3/AN3
P5.4/AN4
P5.5/AN5
P5.6/AN6
P5.7/AN7
27
28
29
30
31
32
33
34
P3.8/MRST
P3.9/MTSR
P3.10/TXD0
P3.11/RXD0
P3.12
P3.13/SCLK
P3.15/CLKOUT
75
76
77
78
79
80
81
P3.0/T0IN
P3.1/T6OUT
P3.2/CAPIN
P3.3/T3OUT
P3.4/T3UED
P3.5/T4IN
P3.6/T3IN
P3.7/T2IN
65
66
67
68
69
70
73
74
Vref
READY
37
97
P1H7
P1H6
P1H5
P1H4
P1H3
P1H2
P1H1
P1H0
135
134
133
132
131
130
129
128
P1L7
P1L6
P1L5
P1L4
P1L3
P1L2
P1L1
P1L0
125
124
123
122
121
120
119
118
P2.0/CC0IO
P2.1/CC1IO
P2.2/CC2IO
P2.3/CC3IO
P2.4/CC4IO
P2.5/CC5IO
P2.6/CC6IO
P2.7/CC7IO
47
48
49
50
51
52
53
54
P2.8/CC8IO/EX0IN
P2.9/CC9IO/EX1IN
P2.10/CC10IO/EX2IN
P2.11/CC11IO/EX3IN
P2.12/CC12IO/EX4IN
P2.13/CC13IO/EX5IN
P2.14/CC14IO/EX6IN
P2.15/CC15IO/EX7IN
57
58
59
60
61
62
63
64
RSTOUT
NMI
141
142
P4.4/A20
P4.5/A21
P4.6/A22
P4.7/A23
89
90
91
92
143139127110 94 83 71 55 45 18
VssVssVssVssVssVssVssVssVssVss
AGND
38
144136129109 93 82 72 56 46 17
VccVccVccVccVccVccVccVccVccVcc
Vcc
PSD4235G2
50/89
I/O PORTS
There are seven programmable I /O ports: Ports A ,
B, C, D, E, F and G. Each port pin is individually
user configurable, thus allowing multiple funct ions
per port. Th e ports are configured using PSDsoft
Express or by the MCU writing to on-chip registers
in the CSIOP space.
The topics discussed in this section are:
■Gen e ra l Po rt a rch itecture
■Port operating modes
■Port Configuration Registers (P CR)
■Port Data Re gisters
■Individual Port functi onality.
General Port Architectu re. The general archi-
tecture of the I/O Port block is shown in Figure 27.
Individual Port architectures are shown in Figure
29 to Fi gure 31. In general, once the purpose for a
port pin has been defined, that pin is no longer
available for other purposes. Exceptions are not-
ed.
As shown in Figure 27, the ports cont ain an out put
multiplexer whose select signals are driven by the
configuration bits in the Control Registers (Ports E,
F and G only) and PSDsoft Express Configuration.
Inputs to the m ul tiplexer include the following:
■Output data from the Data Out register
■Latched address outputs
■CPLD M acrocell output
■External Chip Select from the CPLD.
The Port Data Buffer (PDB) is a tr i-state buffer that
allows only one source at a time to be read. The
Port Data Buffer (PDB) is connected to the Int ernal
Data Bus for feedback and can be read by the
MCU. The Data Out and Macrocel l outputs, Direc-
tion Register and Control Register, and port pin in-
put are all connected to the Port Data Buffer
(PDB).
Figu re 2 7. General I/O P ort A rchi t ect u re
INTERNAL DATA BUS
DATA OUT
REG.
DQ
D
G
Q
DQ
DQ
WR
WR
WR
ADDRESS
MACROCELL OUTPUTS
ENABLE PRODUCT TERM (.OE)
EXT CS
ALE
READ MUX
P
D
B
CPLD-INPUT
CONTROL REG.
DIR REG.
INPUT
MACROCELL
ENABLE OUT
DATA IN
OUTPUT
SELECT
OUTPUT
MUX
PORT PIN
DATA OUT
ADDRESS
AI02885
51/89
PSD4235G2
The Port pin’s tri-state output driver enable is con-
trolled by a two input OR gate whose inputs come
from the CPLD AND Array enable product term
and the Direction Register. If the enable product
term of any of the Array outputs are not defined
and that port pin is no t defined as a CPLD output
in the PSDabel file, the Direction Register has sole
control of the buffer that drives t he port pin.
The conten ts of these registers can be alt ered by
the MCU. The Port Data Buffer (PDB) feedback
path a llows the M CU to che ck the contents of t he
registers.
Ports A, B, and C have embedded Input Macro-
cells (IMC). The Input Macrocells (IMC) can be
configured as lat ches, registers, or direct inputs to
the PLDs. The latches and registers are clocked
by Address Strobe (ALE/AS, PD0) or a product
term from the PLD AND Array. The outputs from
the Input Macrocells (IMC) drive the PLD input bus
and can be read by the MCU. See the section en-
titled “Input Macrocell”, on page 38.
Port Operating Mode s
The I/O Ports have several modes of operation.
Some modes can be defined using PSDsoft Ex-
press, some by t he MCU writing to the registers in
CSIOP spac e, and some by both. The modes that
can only be defined using PSDsoft Express must
be programmed into the device and cannot be
changed unles s the device is reprogram m ed. The
modes that can be changed by the MCU can be
done so dynamically at run-time. The PLD I/O,
Data Port, Address I nput, Peripheral I/O and MCU
Reset modes are the only modes that must be de-
fined before programming the device. All other
modes can be changed by the MCU at run-time.
See Application Note
AN1171
for m ore detail.
Table 39 summarizes which modes a re available
on each port. Table 40 shows ho w and where t he
different modes are configured. Each of the port
operating modes are described in the following
sections.
MCU I/O Mode. In the MCU I/O mode, the MCU
uses the PSD Ports to expand its own I/O ports. By
setting up the CSIOP space, the ports on the PSD
are mapped into the MCU address space. The ad-
dresses of the ports are listed in Table 6.
A port pin can be put into MCU I/O mode by writing
a 0 to the corresponding bit in the Control Register
(for Ports E, F and G). The MCU I/O direction may
be changed by writing to the corresponding bit in
the Direction Register, or by the output enable
product term. S ee the section en titled “P ort Oper-
ating Modes”, on page 51. When the pi n is config-
ured as an output, the content of the Data Out
Register drives t he pin. When configured as an in-
put, the MCU can read the port input through the
Data In buffer. See Figure 27.
Ports A, B and C do not have Control Registers,
and are in MCU I/O mode by default. They can be
used for PLD I/O if they are specified in PSDsoft
Express.
PL D I/ O Mode. The PLD I/O Mode uses a port as
an input to the CPLD’s Input Macrocells (IMC),
and/or as an output from the CPLD’s Output Mac-
rocells (OMC). Th e out put c an be t ri-stated with a
control signal. This output enable control signal
can be defined by a product term from the PLD, or
by resetting the correspon ding bit in the Direction
Register to 0. T he correspondin g bit in the Direc-
tion Reg ister must not be set to 1 if the p in is de-
fined for a PLD input signal in PSDsoft Express.
The PLD I/O mode is specified in PSDsoft Express
by d eclaring t he port pins, a nd th en s pecifying an
equation in PSD soft Express .
Address Out Mode. For MCUs with a multi-
plexed address/data b us, Address Out mode can
be used to drive latched addresses onto the port
pins. These port pins can, in turn, drive external
devices. Either the output enable or the corre-
sponding bits of both the Direction Register and
Control Register must be set to a 1 for pins to use
Address Out mode. This must be done by the
MCU at run-time. See Table 41 for the address
output pin assignments on Ports E, F and G for
various MCUs.
Note: Do not drive address signals with Address
Out M ode t o an external memory device if it is in-
tended for the MCU to B oot from the external de-
vi ce . The M CU mu st firs t B oo t from P S D me m ory
so the Direction and Control register bits can be
set.
PSD4235G2
52/89
Table 39. Port Operating Modes
No te : 1. Can be mult i p l exed with othe r I/ O functions.
2. Available to Motorola 16-bit 683xx and H C16 f amilies of MCUs.
Table 40. Po rt Operating Mode S ettings
Not e: 1 . N/A = Not Appli ca b le
2. The direction of the Port A, B ,C , and F pins ar e controlled by the Direction Register ORed with the indivi dual out put enable product
term (.oe) from the CPLD AND Ar ray.
3. Any of these three methods enables the JTAG pins on Por t E.
4. Con tr ol Regis ter setti ng is not applica ble to Ports A, B and C.
Port Mode Port A Port B Port C Port D Port E Port F Port G
MCU I/O Yes Yes Yes Yes Yes Yes Yes
PLD I/O
McellA Outp uts
McellB Outp uts
Additional Ext. CS Outputs
PLD Inputs
Yes
No
No
Yes
Yes
Yes
No
Yes
No
No
Yes
Yes
No
No
No
Yes
No
No
No
No
No
No
Yes
Yes
No
No
No
No
Address Out No No No No Yes (A7 – 0) Yes (A7 – 0) Yes (A7 – 0)
or (A15 – 8)
Address In Yes Yes Yes Yes No Yes No
Data Port No No No No No Yes Yes
Peripheral I/O Yes No No Yes No Yes No
JTAG ISP No No No No Yes1 No No
MCU Reset Mode2No No No No No Yes Yes
Mode Defined in PSDsoft
Express
Control
Register
Setting
Direction
Register
Setting
VM Register
Setting JTAG Enable
MCU I/O Declare pins only 0 (Note 4)1 = output,
0 = input
(Note 2)N/A N/A
PLD I/O Declare pins and
Logic equations N/A (Note 2)N/A N/A
Data Port (Port F, G) Selected for MCU
with non-multiplexed
bus N/A N/A N/A N/A
Address Out
(Port E, F, G) Declare pins only 1 1 (Note 2)N/A N/A
Address In
(Port A, B, C, D, F)
Declare pins or Logic
equation for Input
Macrocells N/A N/A N/A N/A
Peripheral I/O
(Port F) Logic equations
(PSEL0 and PSEL1) N/A N/A PIO bit = 1 N/A
JTAG ISP 3Declare pins only N/A N/A N/A JTAG_Enable
MCU Reset Mode Specific pin logic le vel N/A N/A N/A N/A
53/89
PSD4235G2
Table 41. I/O Port Latched Address Outpu t Assignments
Not e: 1 . N/A = Not Appli ca b le.
Address In Mode. For MCUs that have more
than 16 address signals, the higher addresses can
be connect ed to Port A, B, C, D or F, and are rout-
ed as inputs to the PLDs. The address input can
be latched in the Input Macrocell (IMC) by Address
Strobe (ALE/AS, PD 0). Any input that is included
in the DPLD equat ions for the primary Flash mem-
ory, secondary F lash memory or SRAM is consid-
ered to be an address input .
Data Port Mode. Ports F and G can be used as a
data bus port for a MCU with a non-multiplexed
address/data bus. The Data Port is connected to
the data bus of the MCU. The general I/O func-
tions are disabl ed in Ports F and G if t he ports are
co nfigured as a Data P ort. Data Port mode is au-
tomatically configured in PSDsoft Express when a
non-multiplexed bus MCU is selected.
Peripheral I/ O M od e. Peripheral I/O mode can
be used to int erface with external 8-bit peri pherals.
In thi s mode, all of Port F s erves as a tri-state, bi-
directional data buffer for the MCU. Peripheral I/O
mode is enabled by set ting bit 7 of the V M Register
to a 1. Figure 28 shows how Port A acts as a bi-
directional buffer for the MCU data bus if Peripher-
al I/O mode is enabled. An equation for PSEL0
and/or PSEL1 must be specified in PSDsoft Ex-
press. The buffer is tri-stated when PSEL0 or
PSEL 1 is not active.
JTAG In-System Programmi ng (ISP). Port E is
JTAG compliant, and can be used for In-System
Programming (ISP). You can multiplex JTAG op-
erations wi th other functions on Port E b ecause In-
System Programming (ISP) is not performed dur-
ing normal system operation. For more information
on the JTAG Port, see the sec tion entitled “Reset
(RESET) Timin g”, on page 63.
MCU Reset Mode. Port s F a nd G can b e config-
ured to operat e in MCU Reset mode. This mode i s
available when PSD is configured for the Motorola
16-bit 683xx and HC16 family and is active only
during reset.
At the rising edge of the Reset input, the MCU
reads the logic level on the data bus (D15-D0)
pins. The MCU then configures some of its I/O pin
functions according to the logic level input on the
data bus lines. Tw o dedicated bu ffers are u sually
enabled during reset to drive th e data bus line s to
the desired logic level.
The PSD ca n repla ce th e tw o buff ers by c onfigur-
ing Ports F and G to operate in MCU Reset mode.
In this mode, the PSD will drive the pre-defined
logic level or data pattern on to the MCU data bus
when Reset is a ctive and there is no on going bus
cycle. After reset, Ports F an d G return to the nor-
mal Data Por t mode.
The MCU Reset mode is ena bled and configured
in PSDsoft Express. The user defines the logic lev-
el (data pa ttern) that will be drive out from Ports F
and G during reset.
Port Configuration Registers (PCR). Each Port
has a set of Port Configuration Registers (PCR)
used for configuration. The contents of the regis-
ters can be accessed by the MCU through normal
read/write bus cycles at the addresses given in Ta-
ble 6. The addres ses in Table 6 are t he offsets in
hexadecimal from the base of the CSIOP register.
The pins of a port are individually configurabl e and
each bit in the register controls its respective pin.
For example, bit 0 in a regis ter refers to bit 0 of i ts
port. The three Port Configuration Registers
(PCR), shown in Ta bl e 42, are us ed for setti ng the
Port configurations . The default Power-up state for
each register in Table 42 is 00 h.
Table 42. Port Configuration Registers (PCR)
No te : 1. Se e T able 46 for Drive Regis ter bit def i ni tion.
Control Register. Any bit reset t o 0 in t he Control
Register sets t he correspondi ng port pin to MCU I /
O mode, and a 1 sets it to Address Out mode. The
default mode is MCU I/O. Only Ports E, F and G
have an associated Control Register.
MCU Port E
(PE3-PE 0) Port E
(PE7-PE4) Port F
(PF3-PF0 ) Port F
(PF7-PF4) Port G
(PG3-P G0) Port G
(PG7-PG4)
80C51X A N/A1Address
a7-a4 N/A Address
a7-a4 Address
a11-a8 Address
a15-a12
All Other
MCU with Multiplexed Bus Address
a3-a0 Address
a7-a4 Address
a3-a0 Address
a7-a4 Address
a11-a8 Address
a15-a12
Register Name Port MCU Access
Control E, F, G Write/Read
Direction A, B, C, D, E, F, G Write/Read
Drive Select1A, B, C, D, E, F, G Write/Read
PSD4235G2
54/89
Figure 28. Peripheral I/O Mode
Direction Register. The Direction Register con-
trols t he direction of data flow in the I/O Ports. Any
bit set to 1 in the Direction Register causes the
corresponding pin to be an output, and any bit set
to 0 causes it to be an input . The def ault mode for
all port pins is input .
Table 43. Port Pin Direction Control, Output
Enable P.T. Not Defined
Table 44. Port Pin Direction Control, Output
Enable P.T. Defined
Table 45. Port Direction Assignment Example
Figure 29 and Figure 31 show the Port Architec-
ture diagrams for Ports A/B /C and E/F/G, respec-
tively. The direction of dat a flow for P orts A, B, C
and F are controlled not only by th e di rection reg-
ister, but also by the output enable product term
from the PLD AND Array. If the output enable
product term is not active, the Direction Register
has sole control of a given pi n’s direction.
An example of a configuration for a Port with the
three least significant bit s set to output and the re-
mainder set to input is shown in Table 45. Since
Port D only cont ains four pi ns, the Direction Reg-
ister for Port D has only the four least significant
bits active.
Drive Select Register. The Drive Select Register
configures the pi n driver as Open Drain or CM OS
for some port pins, and controls the slew rate for
the other port pins. An external pull-up resistor
should be used f or pi ns configured as Open Drain.
A pin can be configured as Open Drain if its corre-
sponding bit in the Drive Select Register is set to a
1. The default pin drive is CMOS.
(The slew rate is a measurement of the rise and
fall ti mes of an output. A higher slew rate means a
faster output response and may create more elec-
trical noise. A pin operates in a high slew rate
when the corresponding bit in the Drive Register is
set to 1. The default rate is slow slew.)
Table 46 shows the Drive Regist er for P ort s A , B,
C, D, E, F and G. It summari zes which pins c an be
configured a s Open Drain out puts and which pins
the slew rate can be s et for.
RD
PSEL0
PSEL1
PSEL
VM REGISTER BIT 7
WR
PA0-PA7
D0-D7
DATA BUS
AI02886
Direction Register Bit Port Pin Mode
0 Input
1 Output
Direction
Register Bit Ou tput Enable
P.T. Port Pin Mode
0 0 Input
0 1 Output
1 0 Output
1 1 Output
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 0 0 0 0 1 1 1
55/89
PSD4235G2
Table 46. Drive Register Pin Assig nment
Note: 1. NA = Not Applicable.
Table 47. Port Data Registers
Port Data Registers. The Port Data Registers,
shown in Tabl e 47, are used b y the MCU t o write
data to or read data from the ports. Table 47
shows the register name, the ports having each
register type, and MCU access for each register
type. The registers are described nex t.
Data In. Port pins are connected directly to the
Data In buf fer. In MCU I/O Input m ode, the pin in-
put is read through t he Dat a In buffer.
Data Out Register. S tores output data written by
the MCU in the MCU I/O Output mode. The con-
tents of the Register are driven out to the pins if the
Direction Register or the output enable product
term is set to 1. The contents of the register can
also be read bac k by the MCU.
Outp ut Macrocells (O MC). The CPLD Output
Macrocells (OMC) occupy a location in the MCU’s
address space. The MCU can read the output of
the Ou tput M acroc ell s (OM C). If the Mask M acro-
cell Register bits are not set, writing to the Macro-
cell loads data to the Ma crocell flip-flops. See the
section ent itl ed “Macroce ll and I/O Port”, on p age
34.
Mask Macrocell Register. Each Mask Macroce ll
Register bit corresponds to an Output Macrocell
(OMC) flip-flop. Wh en the Mask M acrocell Regis-
ter bit is set to a 1, loading data into the Output
Macrocell (OMC) flip-flop is blocked. The default
value is 0, or unblocked.
Input Macrocel ls (IMC). The Input Macrocells
(IMC) can be used to latch or store external inputs.
The outputs of the Input Macrocells (IMC) are rout-
ed to the PLD input bus, and can b e read by the
MCU. See the section entitled “Input Macrocells
(IMC)”, on page 37.
Drive
Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Port A Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain
Port B Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain
Port C Slew
Rate Slew
Rate Slew
Rate Slew
Rate Slew
Rate Slew
Rate Slew
Rate Slew
Rate
Port D NA1NA1NA1NA1Open
Drain Open
Drain Open
Drain Open
Drain
Port E Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain
Port F Slew
Rate Slew
Rate Slew
Rate Slew
Rate Slew
Rate Slew
Rate Slew
Rate Slew
Rate
Port G Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain
Register Name Port MCU Access
Data In A, B, C, D, E, F, G Read – input on pin
Data Out A, B, C, D, E, F, G Write/Read
Output Macrocell A, B Read – outputs of Macrocells
Write – loading Macrocells Flip-flop
Mask Macrocell A, B Write/Read – prevents loading into a given
Macrocell
Input Macrocell A, B, C Read – outputs of the Input Macrocells
Enable Out A, B, C, F Read – the output enable control of the port driver
PSD4235G2
56/89
Figu re 29 . Port A , B and C St ructure
Enable Out. The Enable Out register can be read
by the MCU. It contains the output enable values
for a given port . A 1 indicates the dri ver is in output
mode. A 0 indicates the driver is in tri-state and the
pin is in input mode.
Ports A, B an d C – Fu nct i on a lit y a nd S truc ture
Ports A, B and C have similar functionality and
s tr u ct ure, as s h own i n F i gure 2 9. T he po r t s c a n be
configured to perform one or more of the foll owing
functions:
■MCU I/ O Mode
■CPLD Output – Macrocells McellA7-McellA0
can be connecte d to Port A. Mcell B7 -Mcell B0
can be connecte d to Port B. Ext ernal Chip
Select (ECS7-E CS0) can be connected to Port
C or Port F .
■CPLD Input – Via the Input Macro cells (IMC).
■Address In – A ddi tional high add ress inputs
using the Input Mac rocells (IMC).
■Open Drain/Slew Rate – pins PC7- PC0 can be
configured to fast slew rate. Pins PA7-PA0 can
be configured to Open Drain mode.
INTERNAL DATA BUS
DATA OUT
Register
DQ
DQ
WR
WR
MCELL7-MCELL0 (Port A)
MCELLB7-MCELLB0 (Port B)
Ext.CS (Port C)
ENABLE PRODUCT TERM (.OE)
READ MUX
P
D
B
CPLD-INPUT
DIR Register
INPUT
MACROCELL
ENABLE OUT
DATA IN
OUTPUT
SELECT
OUTPUT
MUX
PORT Pin
DATA OUT
AI04936
57/89
PSD4235G2
Figure 30. Port D Structure
Port D – Function ality and Structure
Port D has four I/O pins. See Figure 30. Port D can
be configured t o perform one or more of the follow-
ing functions:
■MCU I/ O mode
■CPLD Input – direct input to the CPLD, no Input
Macroc ells ( IMC )
Port D pins can be configured in PSDsoft Ex-
press as input pins for other dedicated func-
tions:
■Address Strobe (ALE/AS, PD0)
■CLKIN (PD1) as input to the Macrocells Fli p-
flops and APD counter
■PSD Chip Select Input (CSI, PD2). Driv ing th is
signal High disables the Flash memory, SRAM
and CSIOP.
■Write Enable High-byte (WRH, PD3) input, or as
DBE input from a MC68HC912.
Por t E – Functionality and S t ruct u re
Port E can be configured to perform one or more
of the f ollowing f unctions (see Figure 31):
■MCU I/ O Mode
■In-S ystem Programming (ISP) – JTAG port can
be enabled for programm ing/erase of the PSD
device. (See the section entitled “Reset
(RESET) Timing”, on page 63, for more
information on JTAG pr ogramming.)
■Open Drain – pins can be configured in Open
Drain Mode
■Bat tery Backup features
– PE6 can be c onfigured for a battery input sup-
ply, Voltage Stand-by (VST BY).
– PE7 can be configu red as a Battery-o n Indi-
cator (VBATON), indicating when VCC is less
than VBAT.
■Latched Ad dress output – Provide latched
address output.
INTERNAL DATA BUS
DATA OUT
Register
DQ
DQ
WR
WR
READ MUX
P
D
B
CPLD-INPUT
DIR Register
DATA IN
OUTPUT
SELECT
OUTPUT
MUX
PORT D PIN
DATA OUT
AI04937
PSD4235G2
58/89
Figure 31. Port E, F and G Structure
Port F – Fun ctionality an d Structur e
Port F can be configured to perform one or more
of the following func tions:
■MCU I/O Mode
■CPLD Output – Ext ernal Chip Select (ECS7-
ECS0) can be connected to Port F or P ort C.
■CPLD Input – direct input to the CPLD, no Input
Macroc ells ( IMC )
■Latched Ad dress output – Provide latched
address output as per Table 41.
■Slew Rate – pins can be configured for fast Slew
Rate
■Data Port – connected to D7-D0 when P ort F is
configured as Data Port for a non-multiplex ed
bus
■Peripheral Mode
■MCU Reset Mode – for 16-bit Motorol a 683xx
and HC16 MCUs
Port G – Functi onality and Structure
Port G can be configured to perform on e or more
of the following func tions:
■MCU I/ O Mode
■Latched Ad dress output – Provide latched
address output as per Table 41.
■Open Drain – pins can be configured in Open
Drain Mode
■Data Port – connected t o D15-D8 when Port G
is configured as Data Port for a non-multiplexed
bus
■MCU Reset Mode – for 16-bit Motorol a 683xx
and HC16 MCUs
INTERNAL DATA BUS
DATA OUT
Register
DQ
D
G
Q
DQ
DQ
WR
WR
WR
ADDRESS
Ext. CS (Port F)
ENABLE PRODUCT TERM (.OE)
ALE
READ MUX
P
D
B
CPLD-INPUT (Port F)
CONTROL Register
DIR Register
ENABLE OUT
DATA IN
OUTPUT
SELECT
OUTPUT
MUX
PORT Pin
DATA OUT
ADDRESS
A[7:0] OR A[15:8]
AI04938
ISP or Battery Back-Up (Port E)
Configuration Bit
59/89
PSD4235G2
POWE R MANAGE MENT
The PSD device of fers configurab le pow er saving
options. These options may be used individually or
in combi nations, as follows:
■Al l memo ry blocks in a PSD (primary Flash
memor y, secondary Flash memory, and SRAM)
are built with power management technology. In
addition to using special silicon design
methodology, power management technology
puts the memories into standby mode when
address/data i nputs are not changing (zero DC
current). As soon as a tran sition occurs on an
input, the affected memory “wakes up”,
changes and latches its outputs, then goes back
to standby. The designer does
not
have to do
anything special to achieve m emory Stand-by
mode when no inputs are changing—it happens
automatically.
The PLD sections can also achieve Stand-by
mode when its inputs are not chan ging, as de-
scribed for the Power Managem ent Mode Reg-
isters (PMMR), later.
■The Automatic Power Down (APD) block allows
the PSD to reduce to stand-by current
automatical l y. The APD Unit als o blocks MCU
address/data signals from reaching t he
memories and PLDs. This feature is available
on all PSD devices. The APD Unit is descri bed
in more detail in the section entitled “APD Unit”,
on page 60.
Built in logic monitors the Address Strobe of the
MCU for activity. If there is no activity for a cer-
tain period (the MCU is asleep), the APD Unit
initiates Power-down mode (if enabled). Once in
Power-down mode, all address/data signals are
blocked from reaching the PSD memories and
PLDs, and the memories are deselected inter-
nally. This all ows the memories and PLDs to re-
main in Stand-by mode even if the address/data
signals are changing state externally (noise,
other devices on the MCU bus, etc.). Keep in
mind that any unbl oc ked PL D input s igna ls that
are changing states keeps the PLD out of
Stand-by mode, but not the memories.
■PSD Chip Select Input (CSI, PD2) can be used
to disable the int ernal memori es, placing them
in Stand-by mode even if inputs are changing .
This feature does not block any i nternal signals
or disable the PLDs. This is a good alternative
to using the APD Unit, especially if y our MCU
has a chip select output. There is a slight
penalty in memory access time when PSD Chip
Select Input (CSI, PD2) makes its initial
transition from deselected to selected.
■The Power Managem ent Mod e Registers
(PMMR) can be written by the MCU at run-time
to manage power. All PSD devices support
“blocking bit s” in these registers that are set to
block designated signals from reachi ng bot h
PLDs. Current consumption of the PLDs is
directly related to the composite frequency of
the changes on their inputs ( see Figure 35).
Significant power savings can be achieved by
blocking signals that are not used in DPLD or
CPLD l ogic equations at run-t ime. PS Dsoft Ex-
press creates a fuse map that automatically
blocks t he low address byt e (A7-A0) or the con-
trol signals (CNTL0-CNTL2, ALE and Write En-
able High-byte (WRH/DBE, PD3)) if none of
these signals are used in PLD logic equations.
PSD devices have a Turbo bit in PM MR0. This
bit can be set to turn the Turbo mode off (the de-
fault is with Turbo mode turned on). Whil e Turbo
mode is off, the PLDs can achieve Stand-by cur-
rent when no PLD inputs are changing (zero DC
current). Even when inputs do change, signifi-
cant power can be saved at lower frequencies
(AC current), compared to when Turbo mode is
on. When the Turbo mode is on, there is a s ig-
nificant DC current component, and the AC
component is higher.
PSD4235G2
60/89
Figure 32. APD Unit
Automatic Power-d own (APD) Unit and Power-
down Mode. The APD Unit, s hown i n Figure 32,
puts the P SD into Power-down mode by moni tor-
ing the acti vity of Address Strobe (ALE/AS, PD0).
If the AP D Unit is enab led, as soon as act ivity on
Address Strobe (ALE/AS, PD0) stops, a four bit
counter starts counting. If Address Strobe (ALE/
AS, PD0) remains i nac tive for fifteen c lock periods
of CLKIN (PD1), Power-down (PDN) goes High,
and the PSD enters Power-down mode, as dis-
cussed next.
Table 48. Effect of Power-down Mode on Ports
Po we r-down Mode . By def ault, if you enabl e the
APD Unit, Power-down mode is automatically en-
abled. The device enters P ower-down mode if Ad-
dress Strobe (ALE/AS, PD0) remains inactive for
fifteen periods of CLKIN (PD1).
The following should be kept in mind when the
PSD is in Power-down mode:
■If Address Strobe (ALE/AS, PD0) starts pul sing
again, the PSD returns to normal operation. The
PSD also returns to normal operation if either
PSD Chip Selec t Input ( CSI, PD2) is Low or the
Reset ( R ESET ) input is High.
■The MCU address/data bus is blocked from all
memory and PLDs.
■Various signal s can be blocked (prior to Power-
down mode) from entering the PLDs by setting
the appropriate bits in the P owe r Manage men t
Mode Registers (PMMR ). The blocked signals
include MCU control signals and the common
CLKIN (PD1). Note that blocking CLKIN (PD1)
fro m the PLDs does not block CLKIN (PD1)
from the APD Unit.
■All PSD memories enter Stand-by mode and are
drawing Stand-by current. However, the PLDs
and I/ O ports blocks do
not
go into Stand-by
mode becaus e you do not want to have to wait
for the logic and I/ O to “wake-up ” before their
outputs can change. See Table 48 for Power-
down mode effects on PSD ports.
■Typical Stand-by current i s or the order of µA.
This Stand-by current value assumes that there
are no transitions on any PLD input.
Table 49. P SD T i m ing and Stand-b y Curre nt dur ing Power-down Mode
Note: 1. Power-dow n does not a ffect the operation o f the PLD. Th e P LD operation in thi s m ode is based only on the Turbo bit.
2. Typ i cal current consump tion, see Tabl e 60, ass uming no PLD inputs are changing st ate and t he P LD Turb o bi t is 0.
APD EN
PMMR0 BIT 1=1
ALE
RESET
CSI
CLKIN
TRANSITION
DETECTION
EDGE
DETECT
APD
COUNTER
POWER DOWN
(PDN) Select
DISABLE BUS
INTERFACE
Secondary Flash
Memory Select
Primary Flash
Memory Select
SRAM Select
PD
CLR
PD
DISABLE Primary and Secondary
FLASH Memory and SRAM
PLD
AI04939
Port Function Pin Level
MCU I/O No Change
PLD Out No Change
Address Out Undefined
Data Port Tri-State
Peripheral I/O Tri-State
Mode PLD Propagation Delay Memory Access
Time Access Recovery Time to
Normal Access Typical Stand-by
Current
Power-down N or mal tPD (Note 1)No Access tLVDV ISB (Note 2)
61/89
PSD4235G2
Figure 33. Enable Power-down Flow Chart
Othe r Po wer S aving Options. The PSD offers
other reduced power saving opt ions that are inde-
pendent of the P ower-down mode . Except for the
SRAM Sta nd-by and P S D Chip Se lect Input ( CS I,
PD2) f eatures, they are enabled by setting b its in
PMMR0 and PMMR2 (as summ arised in Table 23
and Table 24).
PL D Po wer Mana gem ent
The power and spee d of the PLDs are con trolled
by the Turb o bit (bit 3) in PMMR0. By setting the
bit to 1, the Turbo mode is of f and the P LDs con-
sume the spe cified S tand-by current when the in-
puts are not switching for an extended time of
70 ns. The propagation delay time is increased af-
ter the Turbo bit is s et to 1 (turned off) when the in-
puts change at a composite frequency of less than
15 MHz. When the Turbo bit is reset to 0 (turned
on), the PLDs run at full power and speed. The
Turbo bit affects the PLD’s D C p ower, AC powe r,
and propagation de lay. S ee the AC and DC c har-
acteristics tables for PLD timing values (Table 67).
Blocking MCU control signals with the P MMR2 bits
can further reduce PLD AC power consumption.
SRAM Stand-b y Mode (Battery Backu p). The
PSD supports a battery backup mode in which the
contents of the SRAM are ret ained in the event of
a power loss. The SRAM has Voltage Stand-by
(VSTBY, P E6) th at ca n be co nnecte d to an exter-
nal battery. When VCC becomes lower than VSTBY
then the PSD automatically connects to Voltage
Stand-by (VSTBY , P E 6) as a power source to the
SRAM. The SRAM Stand-by current (ISTBY) is typ-
ically 0.5 µA. The S RAM data retention v oltage is
2 V minimum. The Batt ery-on Indic ator (VBATON)
can be routed to PE7. This signal indica tes when
the VCC has dropped below VSTBY, and that the
SRAM is running on battery power.
PSD Chip Select Input (CSI, PD 2 )
PD2 of Port D can be configured in PSDsoft Ex-
press as PSD Chip Select Input (CSI ). When Low,
the signal select s and enables the internal primary
Flash memory, secondary Flas h m emory, SRAM,
and I/O blocks for Read or Write operations involv-
ing the PSD. A High on PSD Chip Select Input
(CSI, PD2) disables the primary Flash memory,
secondary Flash mem ory , and S RA M, and reduc-
es the PSD power consumption. However, the
PLD and I/O signals remain operational when PSD
Chip Sel ect Input (CSI, PD2) is High.
There may be a timing penalty when using PSD
Chip Select Input (CSI, PD2) depending on the
speed grade of the PSD that you are using. See
the timing parameter tSLQV in Table 67.
Inpu t Cl oc k. The PSD provides the option to turn
off CLKIN (PD1) to the PLD to save AC power con-
sumption. CLKIN (PD1) is an input to the PLD
AND Array and the Output Macrocells (OMC).
During Power-down mode, or, if CLKIN (PD1) is
not being used a s part of the PLD logic equation,
the clock should be disabled to save AC power.
CLKIN (PD1) is disconnected from the PLD AND
Array or the Macrocel l s block by setting bits 4 or 5
to a 1 in PMMR0.
Table 50. A PD Counter Opera tion
Enable APD
Set PMMR0 Bit 1 = 1
PSD in Power
Down Mode
ALE/AS idle
for 15 CLKIN
clocks?
RESET
Yes
No
OPTIONAL
Disable desired inputs to PLD
by setting PMMR0 bits 4 and 5
and PMMR2 bits 0 to 6.
AI04940
APD Enable Bit ALE PD Polarity ALE Level APD Counter
0 X X Not Counting
1 X Pulsing Not Counting
1 1 1 Counting (Generates PDN after 15 Clocks)
1 0 0 Counting (Generates PDN after 15 Clocks)
PSD4235G2
62/89
Inpu t Control Si gn a l s. The PSD provides the
option to t urn off t he address input (A7-A0) and in -
put control signals (CNTL0, CNTL1, CNTL2, Ad-
dress Strobe (ALE/AS, PD0) and Write Enable
High-byte (WRH/DBE, PD3)) to the PLD to save
AC power consumption. These signals a re inputs
to the PLD A ND Arr ay. Dur ing Power -down mode,
or, if any of them are not being used as part of the
PLD logic equation, these control signals should
be disabled to save AC power. They are discon-
nected from t he PLD AND A rray by setting bits 0,
2, 3, 4, 5 and 6 to a 1 in PMMR2.
Power On Reset, Warm Reset and Power-down
Power On Reset. Upon Power-up, the PSD re-
quires a Reset (RESET) pulse of duration tNLNH-
PO (minimum 1 ms) after VCC is steady. During
this period, the device loads internal configura-
tions, clears some of the registers and sets the
Flash memo ry into O perating mode . After the ris-
ing edge of Reset (RESET), the PSD remains in
the Reset mode for an additional period, tOPR
(maximum 120 ns), before the first memory ac-
cess is a llow ed.
The PSD Flash memory is reset t o the Read mode
upon Power-up. Sector Select (FS0-FS7 and
CSBOOT0-CSBOOT3) must all be Low, Write
Strobe (WR/WRL, CNTL0) Hi gh, dur ing Power On
Reset for maximum security of the data contents
and to remove the possibility of data bein g written
on the first edge of Write Strobe (WR/WRL,
CNTL0). Any Flash memory Write cycle initiation
is prevented automatically when VCC is below VL-
KO.
W arm Reset. Once the device is up and ru nning,
the device can be reset with a pulse of a much
shorter duration, tNLNH (minimum 150 ns). The
same t OPR period is needed before the device is
operational after warm reset. Figure 34 shows the
timing of the Power-up and warm reset.
I/O Pin, Register and PLD Status at Reset. Ta-
ble 51 shows the I/O pin, register and PLD status
during Power On Reset, warm reset and Power-
down mod e. PLD output s are always valid during
warm reset, and t h ey are valid in Power On Reset
once the internal PSD Configurat ion bits are l oad-
ed. This loading of PSD is completed typically long
before the V CC ramp s up to operat ing leve l. Once
the PLD is active, the state of the outputs are de-
termined by equations specified in PSDsoft Ex-
press.
Reset of Flash Memory Erase and Program Cy-
cles. An external Reset (RESET) also resets the
internal Flash memory state machine. During a
Flash memory Program or Erase cycle, Reset
(RESET) terminates the cycle and returns the
Flash memory to the Read mode within a period of
tNLNH-A (minimum 25 µs).
Table 51. Status During Power-On Reset, Warm Reset and Power-down Mode
Note: 1. The SR_code and Peripheral Mode bits in the VM Register are always cleared to 0 on Power-On Reset or Warm Reset.
Port Configuration Power-On Reset Warm Reset Power-down Mode
MCU I/O Input mode Input mode Unchanged
PLD Output Valid after inter n al PSD
configuration bits are
loaded Valid Depends on inputs to PLD
(addresses are blocked in
PD mode)
Address Out Tri-stated Tri-stated Not defined
Data Port Tri-stated Tri-stated Tri-stated
Peripheral I/O Tri-stated Tri-stated Tri-stated
Register Power-On Reset Warm Reset Power-down Mode
PMMR0 and PMMR2 Cleared to 0 Unchanged Unchanged
Macrocells Flip-flop status Cleared to 0 by internal
Power-On Reset Depends on .re and .pr
equations Depends on .re and .pr
equations
VM Register1
Initialized, based on the
selection in PSDsoft
Express
Configuration menu
Initialized, based on the
selection in PSDsoft
Express
Configuration menu
Unchanged
All other registers Cleared to 0 Cleared to 0 Unchanged
63/89
PSD4235G2
Figure 34. Reset (RESET) Timing
Progr ammi ng In-Circu it using th e JTAG Serial
Interface
The JTAG Serial Interface on t he PSD can be en-
abled on Port E (see Table 52). All memory blocks
(primary Flash memory and secondary Flash
memory), PLD logic, and PSD Configuration bits
may be programmed through the JTAG-ISC Serial
Interface. A blank device can be mounted on a
printed circuit boar d and programmed using J TAG
In-Syst em Programming (IS P).
The standard JTAG signals (IEEE 1149.1) are
TMS, TCK, T DI, and TDO. Two addit i onal signals,
TSTA T an d TE R R , are opt ional JTAG ext ensions
used to speed up Program and Erase cycles.
By default, on a blank PSD (as shipped from the
factory, or after erasure), four pins on Port E are
enabled for the basic JTAG signals TMS, TCK,
TDI, and TDO
.
See Application Note
AN1153
for more details on
JTAG In-System Programm ing (ISP).
Standard JTAG Sign als. The standard JTAG
signals (TMS, TCK, TDI, and TDO) can be en-
abled by any of three different conditions that are
logically ORed. When enabled, TDI, TDO, TCK,
and TMS are inputs, waiting for a seria l command
from an ex ternal JTAG c ontroller device (such as
FlashLINK or Autom ated T est Equip ment). W hen
the enabling comm and is received from the exter-
nal JTAG controller devic e, TDO becomes an out-
put and the JTAG channel is fully functional inside
the PSD. The same command that enables the
JTAG channel may opti onally enable the two addi-
tional JTAG pins, TSTAT and TERR .
The following s ymbolic logic equat ion specifies the
conditions enabling the four basic JTAG pins
(TMS, TCK, TDI, and TDO) on their respective
Port E pins. For purpos es of di scussion , the logic
label JTAG_ON is used. When JTAG_ON is true,
the four pins are enabled for JTAG. When
JTAG_ON is false, the four pins can be used for
general P SD I/O.
JTAG_ON = PSDsoft Express_enabled +
/* An NVM configuration bit inside the
PSD is set by the designer in the
PSDsoft Express Configuration utilit y.
This ded icates the pins for JTA G at all
times (compliant with IEEE 1149.1 */
Microcontroller_enabled +
/* The microcontroller can set a bit at
run-time by writing to the PSD
register, JTAG Enable. This register
is located at address CSIOP + offset
C7h. Setting the JTAG_ENABLE bit in
this register will enable the pins for
JTAG use. This bit is cleared by a PSD
reset or the microcontroller. See
Table 21 for bit definition. */
PSD_product_term_enabled;
/* A dedicated product term (PT) inside
the PSD can be used to enable the JTAG
pins. This PT has the reserved name
JTAGSEL. Once defined as a node in
PSDabel, the designer can write an
equation for JTAGSEL. This method is
used when the Port E JTAG pins are
multiplexed with other I/O signal s. It
is recommended to tie logically the
node JTAGSEL to the JEN\ signal on the
Flashlink cable when multiplexing JTAG
signals. See Application Note 1153 f or
details. */
The state of the PSD Reset (RESET) signal does
not interrupt (or prevent) JTAG operations if the
JTAG pins are dedicated by an NVM c onf iguration
bit (via PSDsoft Express). However, Reset (RE-
SET) will prevent or interrupt JTAG operations if
the JTAG Enable Register (as shown in Table 21)
is used to enable the JTAG pins.
The PSD supports JTAG In-System-Programma-
bility (ISP) commands, but not Boundary Scan.
ST’s PSDsoft Express software tool and
FlashLINK JTAG programming cable implement
the JTAG In-System-Programmability (ISP) com-
mands.
Table 52. JTAG Port Signals
tNLNH-PO tOPR
AI02866b
RESET
tNLNH
tNLNH-A tOPR
VCC VCC(min)
Power-On Reset Warm Reset
Port E Pin JTAG Signals Description
PE0 TMS Mode Select
PE1 TCK Clock
PE2 TDI Serial Data In
PE3 TDO Serial Data Out
PSD4235G2
64/89
JTAG Extensions. TSTAT and TERR are two
JTAG e xtensio n s ign als ena bled by a JTA G com-
mand received over the four standard JTAG pins
(TMS, TCK, TDI, and TDO). They are used to
speed Program and Erase cycles by indicating
status on PSD pins instead of having to scan the
status out s eri ally u sing t he standa rd J TAG chan-
nel. See Application Not e
AN1153
.
TERR indicates if an error has occurred when
erasing a sec tor or programming in Flash memory .
This signal g oes Low (active) whe n an Error con-
dition occurs, and stays Low unt il a specific JTA G
comm and is executed or a Reset (RESET) pulse
is received after an “ISC_DISABLE” command.
TSTAT behaves the same as Ready/Busy (PE4)
described in the section entitled “Ready/Busy
(PE4)”, on page 21. TSTAT is High when the
PSD4235G2 device is in Read mode (primary
Flash memory and secondary Fl ash mem ory con-
tents can be read). TSTAT is Low when Flash
memory Program or Erase cycles are in progress,
and also when data is being wr itten to t he second-
ary Flash memory .
TSTAT and TERR can be configured as open-
drain type signals with a JTAG command.
Note: The state of Reset (Reset) does not interrupt
(or prevent) JTAG operations if the JTAG signals
are dedicated by an NVM Configuration bit (via
PSDsoft Express). However, Reset (Reset) pre-
vents or interrupts JTAG operations if the JTAG
Enable Register (as shown in Table 21) is used to
enable the JTAG signal s.
Security and Flash memory P ro tection. When
the security bit is set, the device cannot be read on
a Device Programmer or through the JTAG Port.
When usi ng t he JT AG Port, only a Full Chip Erase
command is allow ed.
All other Program, Erase and Verify commands
are blocked. Fu ll Chip Erase returns t he dev ice to
a non-sec ured blank state. The Security Bit can be
set in PSDsoft Express.
All primary Flash memory and secondary Flash
memory sectors can indi vidually be sector protect -
ed against erasure. The sector protect bits can be
set in PSDsoft Express.
INITIAL DELIVERY STATE
When delivered from ST, the PSD device has all
bits in the memory and PLDs set to 1. The PSD
Configuration Regist er bits are set to 0. The code,
configuration, and PLD logic are loaded using the
programming procedure. Information for program-
ming the device is available directly from ST.
Please contact you r local sales representative.
PE4 TSTAT Status
PE5 TERR Error Flag
Port E Pin JTAG Signals Description
65/89
PSD4235G2
AC/DC PARAMETERS
These tables describe the AD and DC parameters
of the PSD4235G2:
❏ DC Electrical Specification
❏ AC Timing Specification
■PLD Timing
– Combi nato rial Timing
– Synchronous Clock Mod e
– Async hronous Clock Mode
– Input Macrocell Timing
■MCU Timing
– Read Timing
–Write Timing
– Peripheral Mode Timing
– Power-dow n and Reset Timing
The following are issues concerning the parame-
ters presented:
■In the DC specifi cation the supply current is
given for different modes of oper ation. Befor e
calculatin g the total power consumpt ion,
determi ne the percentage of ti me that the PSD
is in each mode. Also, the supply power is
considerably different if t he Turbo bit is 0.
■The AC power component gives the PLD, Flash
memory, and SRAM mA/MHz specification.
Figure 35 show the PLD mA/MHz as a function
of the number of Product T erms (PT) used.
■In the PLD timing parameter s, add the required
delay when Turbo bit is 0.
Figure 35. PLD I CC /Frequency Consumption
AI05739
0
10
20
30
40
50
60
70
80
90
100
110
0 5 10 15 20 25
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
Icc - (mA)
PT 100% PT 25%
Vcc = 5V
TURBO ON (100%)
TURBO ON (25%)
TURBO OFF
TURBO OFF
PSD4235G2
66/89
Table 53. Example of PSD Typical Power Calculation at VCC = 5.0 V (with Turbo Mode On)
Conditions
Highest Composite PLD input frequency
(Freq PLD) = 8 MHz
MCU ALE frequency (Freq ALE) = 4 MHz
% Flash memory
Access = 80%
% SRAM access = 15%
% I/O access = 5% (no additional power above base)
Operational Modes
% Normal = 10%
% Power-down Mode = 90%
Number of product terms used
(from fitter report) = 45 PT
% of total product terms = 45/193 = 23.3%
Turbo Mode = ON
Calculation (using typical values)
ICC total = Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc))
= Ipwrdown x %pwrdown + % normal x (%flash x 2.5 mA/MHz x Freq ALE
+ %SRAM x 1.5 mA/MHz x Freq ALE
+ % PLD x 2 mA/MHz x Freq PLD
+ #PT x 400 µA/PT)
= 50 µA x 0.90 + 0.1 x (0.8 x 2.5 mA/MHz x 4 MHz
+ 0.15 x 1.5 mA/MHz x 4 MHz
+ 2 mA/MHz x 8 MHz
+ 45 x 0.4 mA/PT)
= 45 µA + 0.1 x (8 + 0.9 + 16 + 18 mA)
= 45 µA + 0.1 x 42.9
= 45 µA + 4.29 mA
= 4.34 mA
This is the operating power with no Flash memory Program or Erase cycles in progress. Calculation is based on IOUT
= 0 mA.
67/89
PSD4235G2
Table 54. Example of PSD Typical Power Calculation at VCC = 5.0 V (with Turbo M od e Off)
Conditions
Highest Composite PLD input frequency
(Freq PLD) = 8 MHz
MCU ALE frequency (Freq ALE) = 4 MHz
% Flash memory
Access = 80%
% SRAM access = 15%
% I/O access = 5% (no additional power above base)
Operational Modes
% Normal = 10%
% Power-down Mode = 90%
Number of product terms used
(from fitter report) = 45 PT
% of total product terms = 45/193 = 23.3%
Turbo Mode = Off
Calculation (using typical values)
ICC total = Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc))
= Ipwrdown x %pwrdown + % normal x (%flash x 2.5 mA/MHz x Freq ALE
+ %SRAM x 1.5 mA/MHz x Freq ALE
+ % PLD x (from graph using Freq PLD))
= 50 µA x 0.90 + 0.1 x (0.8 x 2.5 mA/MHz x 4 MHz
+ 0.15 x 1.5 mA/MHz x 4 MHz
+ 24 mA)
= 45 µA + 0.1 x (8 + 0.9 + 24)
= 45 µA + 0.1 x 32.9
= 45 µA + 3.29 mA
= 3.34 mA
This is the operating power with no Flash memory Program or Erase cycles in progress. Calculation is based on IOUT
= 0 mA.
PSD4235G2
68/89
MAX I MUM R AT I N G
Stressing the device ab ove t he rati ng l isted in t he
Absolute Maximum Ratings" table may caus e per-
manent damage to the device. These are stress
ratings only and operation of the device at t hes e or
any other con ditions ab ove those i ndicated i n the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 55. Absolut e Maximum Ratings
Not e: 1 . IPC/ JED EC J- ST D-02 0 A
2. JED EC St d JESD22-A11 4A (C1=100 pF , R1=1500 Ω, R2=500 Ω)
Symbol Parameter Min. Max. Unit
TSTG Storage Temperature –65 125 °C
TLEAD Lead Temperature during Soldering (20 seconds max.)1235 °C
VIO Input and Output Voltage (Q = VOH or Hi-Z) –0.6 7.0 V
VCC Supply Voltage –0.6 7.0 V
VPP Device Programmer Supply Voltage –0.6 14.0 V
VESD Electrostatic Discharge Voltage (Human Body model) 2–2000 2000 V
69/89
PSD4235G2
DC AND AC PARAME TERS
This section summarizes the operating and m ea-
surement conditions, and the DC and AC charac-
teristics of the device. The para meters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Des igners shoul d c heck that the operating
conditions i n their circuit match the meas urement
conditions when relying on the quoted parame-
ters.
Table 56. Oper ating Condi tions
Table 57. AC Symbols for PLD Timing
Example : tAVLX – Time from Address Valid to ALE Invalid.
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 4.5 5.5 V
TAAmbient Operating Temperature (industrial) –40 85 °C
Ambient Operating Temperature (commercial) 0 70 °C
Signal Lette rs Signal Behavior
A Address Input t Time
C CEout Output L Logic Level Low or ALE
D Input Data H Logic Level High
E E Input V Valid
G Internal WDOG_ON signal X No Longer a Valid Logic Level
I Interr upt Input Z F loat
L ALE Input PW Pulse Width
N Reset Input or Output
P Port Signal Output
Q Output Data
RWR
, UDS, LDS, DS, IORD, PSEN Inputs
S Chip Select Input
TR/W
Input
W Internal PDN Signal
BVSTBY Output
M Output Macrocell
PSD4235G2
70/89
Table 58. A C Measurem en t Condition s
Note: 1. Output Hi-Z i s defined as the poin t w here data o ut is no l onger driven.
Table 59. C apacitance
Not e: 1. Sampled only, not 100% tested.
2. Typ i cal value s are for TA = 2 5°C and nomi nal su ppl y volta ges.
Figure 36. AC Measurement I/O Wavef orm Figure 37. AC Measurement Load Circuit
Figure 38. S witching Waveforms – Key
Symbol Parameter Min. Max. Unit
CLLoad Capacitance 30 pF
Symbol Parameter Test Condition Typ.2Max.Unit
CIN Input Capacitance (for input pins) VIN = 0V 46pF
COUT Output Capacitance (for input/
output pins) VOUT = 0V 812pF
CVPP Capacitance (for CNTL2/VPP)V
PP = 0V 18 25 pF
3.0V
0V
Test Point 1.5V
AI03103b
Device
Under Test
2.01 V
195 Ω
CL = 30 pF
(Including Scope and
Jig Capacitance) AI03104b
WAVEFORMS INPUTS OUTPUTS
STEADY INPUT
MAY CHANGE FROM
HI TO LO
MAY CHANGE FROM
LO TO HI
DON'T CARE
OUTPUTS ONLY
STEADY OUTPUT
WILL BE CHANGING
FROM HI TO LO
WILL BE CHANGING
LO TO HI
CHANGING, STATE
UNKNOWN
CENTER LINE IS
TRI-STATE
AI03102
71/89
PSD4235G2
Table 60. DC Characteristics
No te : 1. Res et (R eset) has hy st eresis. VIL1 is valid at or belo w 0.2VCC –0. 1. VIH1 is valid at or ab ove 0.8VCC .
2. CSI deselected or in ternal Power-down mode is active.
3. PLD is in non-Turbo mode, and none of the inputs are switching.
4. Ple ase see Fi gure 35 for the PLD c urrent c al culati on.
Symbol Parameter Test Condition
(in addition to those in
Table 56) Min. Typ. Max. Unit
VIH Input High Volta ge 4.5 V < VCC < 5.5 V 2VCC +0.5 V
VIL Input Low Voltage 4.5 V < VCC < 5.5 V –0.5 0.8 V
VIH1 Reset High Level Input Voltage (Note 1)0.8VCC VCC +0.5 V
VIL1 Reset Low Level Input Voltage (Note 1)–0.5 0.2VCC –0.1 V
VHYS Reset Pin Hysteresis 0.3 V
VLKO VCC (min) for Flash Erase and
Program 2.5 4.2 V
VOL Output Low Voltage IOL = 20 µA, VCC = 4.5 V 0.01 0.1 V
IOL = 8 mA, VCC = 4.5 V 0.25 0.45 V
VOH Output High Voltage Except
VSTBY On IOH = –20 µA, VCC = 4.5 V 4.4 4.49 V
IOH = –2 mA, VCC = 4.5 V 2.4 3.9 V
VOH1 Output High Voltage VSTBY On IOH1 = 1 µA VSTBY – 0.8 V
VSTBY SRAM Stand-by Voltage 2.0 VCC V
ISTBY SRAM Stand-by Current VCC = 0 V 0.5 1 µA
IIDLE Idle Current (VSTBY input) VCC > VSTBY –0.1 0.1 µA
VDF SRAM Data Retention Voltage Only on VSTBY 2V
I
SB Stand -by Supply Current
for Power-down Mode CSI >VCC –0.3 V (No tes 2,3)100 200 µA
ILI Input Leakage Current VSS < VIN < VCC –1 ±0.1 1 µA
ILO Output Leakage Current 0.45 < VOUT < VCC –10 ±5 10 µA
ICC (DC)
(Note 5)
Operating
Supply
Current
PLD Only
PLD_TURBO = Off,
f = 0 MHz (Note 5)0 µA/PT
PLD_TURBO = On,
f = 0 MHz 400 700 µA/PT
Flash memory During Flash memory Write/
Erase Only 15 30 mA
Read Only, f = 0 MHz 0 0 mA
SRAM f = 0 MHz 0 0 mA
ICC (AC)
(Note 5)
PLD AC Adder note 4
Flash memory AC Adder 2.5 3.5 mA/
MHz
SRAM AC Adder 1.5 3.0 mA/
MHz
PSD4235G2
72/89
Table 61. CPLD Combinatorial Timing
No te : 1. Fast Slew Rate outp ut available on Port C an d Port F.
Table 62. CPLD Macrocell Synchrono us Clock Mode Timing
No te : 1. Fast Slew Rate outp ut available on Port C an d Port F.
2. CLK IN (PD1) tCLCL = tCH + tCL .
Symbol Parameter Conditions -70 -90 Fast
PT
Aloc
Turbo
Off Slew
rate1Unit
Min Max Min Max
tPD CPLD Input Pin/
Feedback to CP LD
Combinatorial Output 20 25 + 2 + 12 – 2 ns
tEA CPLD Input to CPLD
Output Enable 21 26 + 12 – 2 ns
tER CPLD Input to CPLD
Output Disable 21 26 + 12 – 2 ns
tARP CPLD Register Clear
or Preset Delay 21 26 + 12 – 2 ns
tARPW CPLD Register Clear
or Preset Pulse Width 10 20 + 12 ns
tARD CPLD Array Delay Any
Macrocell 11 16 + 2 ns
Symbol Parameter Conditions -70 -90 Fast
PT
Aloc
Turbo
Off Slew
rate1Unit
Min Max Min Max
fMAX
Maximum Frequency
External Feedback 1/(tS+tCO)34.4 30.30 MHz
Maximum Frequency
Internal Feedback
(fCNT)1/(tS+tCO–10) 52.6 43.48 MHz
Maximum Frequency
Pipelined Data 1/(tCH+tCL)83.3 50.00 MHz
tSInput Setup Time 14 15 + 2 + 12 ns
tHInput Hold Time 0 0 ns
tCH Clock High Time Clock Input 6 10 ns
tCL Clock Low Time Clock Input 6 10 ns
tCO Clock to Output
Delay Clock Input 15 18 – 2 ns
tARD CPLD Array Delay Any Macrocell 11 16 + 2 ns
tMIN Minimum Clock
Period 2 tCH+tCL 12 20 ns
73/89
PSD4235G2
Table 63. CPLD Macrocell Asynchron ou s Clock Mode Timing
Symbol Parameter Conditions -70 -90 PT
Aloc Turbo
Off Slew
Rate Unit
MinMaxMinMax
f
MAXA
Maximum
Frequency
External
Feedback
1/(tSA+tCOA)38.4 26.32 MHz
Maximum
Frequency
Internal
Feedback
(fCNTA)
1/(tSA+tCOA–10) 62.5 35.71 MHz
Maximum
Frequency
Pipelined Data 1/(tCHA+tCLA)47.6 37.03 MHz
tSA Input Setup
Time 6 8 + 2 + 12 ns
tHA Input Hold Time 7 1 2 ns
tCHA Clock Input
High Time 9 12 + 12 ns
tCLA Clock Input Low
Time 12 15 + 12 ns
tCOA Clock to Output
Delay 21 30 + 12 – 2 ns
tARDA CPLD Array
Delay Any Macrocell 11 16 + 2 ns
tMINA Minimum Clock
Period 1/fCNTA 16 28 ns
PSD4235G2
74/89
Figure 39. Input to Output Disable / Enable
Figure 40. Asynchronous Reset / Preset
Figure 41. Synch ronous C lo ck Mo de Ti m i ng – P LD
Figure 42. Asynchronous Clock Mode Timing (product term clock)
tER tEA
INPUT
INPUT TO
OUTPUT
ENABLE/DISABLE
AI02863
tARP
REGISTER
OUTPUT
tARPW
RESET/PRESET
INPUT
AI02864
tCH tCL
tCO
tH
tS
CLKIN
INPUT
REGISTERED
OUTPUT
AI02860
tCHA tCLA
tCOA
tHAtSA
CLOCK
INPUT
REGISTERED
OUTPUT
AI02859
75/89
PSD4235G2
Table 64. Inp ut Macrocell Timing
Note : 1. Inputs from Port A, B, and C relative to re gister/latch clock from the PLD. ALE latc h timings refer to tAVLX and tLXAX .
Figure 43. Input Macrocell Timing (product term clock)
Symbol Parameter Conditions -70 -90 PT
Aloc Turbo
Off Unit
Min Max Min Max
tIS Input Setup Time (Note 1)00 ns
t
IH Input Hold Time (Note 1)15 20 + 12 ns
tINH NIB Input High Time (Note 1)912 ns
t
INL NIB Input Low Time (Note 1)912 ns
t
INO NIB Input to Combinatorial
Delay (Note 1)34 46 + 2 + 12 ns
tINH tINL
tINO
tIH
tIS
PT CLOCK
INPUT
OUTPUT
AI03101
PSD4235G2
76/89
Table 65. R ead Tim ing
Note: 1. RD timing has th e sa me timi n g as DS, LD S, U DS , and PSEN signal s.
2. RD an d PSEN ha ve the same timing.
3. Any input used to select an internal PSD function.
4. In mu l tiplexed m ode, latc hed add resses generated from A DI O delay to addres s output on any Port.
5. RD timing has th e sam e timi n g as DS, LD S, an d UDS signals.
Symbol Parameter Conditions -70 -90 Turbo
Off Unit
Min Max Min Max
tLVLX ALE or AS Pulse Width 15 20 ns
tAVLX Address Setup Time (Note 3)46 ns
t
LXAX Address Hold Time (Note 3)78 ns
t
AVQV Address Valid to Data Valid (Note 3)70 9 0 + 12 ns
tSLQV CS Valid to Data Valid 75 100 ns
tRLQV
RD to Data Valid 8-Bit Bus (Note 5)24 32 ns
RD or PSEN to Data Valid
8-Bit Bus, 8031, 80251 (Note 2)31 38 ns
tRHQX RD Data Hold Time (Note 1)00 ns
t
RLRH RD Pulse Width (Note 1)27 32 ns
tRHQZ RD to Data High- Z (Note 1)20 25 ns
tEHEL E Pulse Width 27 32 ns
tTHEH R/W Setup Time to Enable 6 1 0 ns
tELTL R/W Hold Time After Enable 0 0 ns
tAVPV Address Input Valid to
Address Output Delay (Note 4)20 25 ns
77/89
PSD4235G2
Figure 44. Read Timing
Note: 1. tAVLX and tLXAX are not required for 80C251 in Page Mode or 80C51XA in Burst Mode.
tAVLX tLXAX
1
tLVLX
tAVQV
tSLQV
tRLQV tRHQX
tRHQZ
tELTL
tEHEL
tRLRH
tTHEH
tAVPV
ADDRESS
VALID
ADDRESS
VALID
DATA
VALID
DATA
VALID
ADDRESS OUT
ALE/AS
A/D
MULTIPLEXED
BUS
ADDRESS
NON-MULTIPLEXED
BUS
DATA
NON-MULTIPLEXED
BUS
CSI
RD
(PSEN, DS)
E
R/W
AI02895
PSD4235G2
78/89
Table 66. W rite Timing
Note: 1. Any input used to select an internal PSD function.
2. In mu l tiplexed m ode, latc hed add ress gen erated f rom A DIO delay to address output on an y port.
3. WR has the sam e ti m i ng as E, DS, LDS, U DS , WRL, and WRH signals.
4. Ass um i ng d at a i s s table before act i ve write signal .
5. Ass um i ng write i s active bef ore data becomes valid.
6. tWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory.
7. tWHA X is 6 ns when wri ting to th e Output Macroce l l Registers AB and B C.
Symbol Parameter Conditions -70 -90 Unit
Min Max Min Max
tLVLX ALE or AS Pulse Width 15 20 ns
tAVLX Address Setup Time (Note 1)46ns
t
LXAX Address Hold Time (Note 1)78ns
t
AVWL Address Valid to Leading
Edge of WR (Notes 1,3)815ns
t
SLWL CS Valid to Leading Edge of WR (Note 3)12 15 ns
tDVWH WR Data Setup Time (Note 3)25 35 ns
tWHDX WR Data Hold Time (Note 3,7)45ns
t
WLWH WR Pulse Width (Note 3)28 35 ns
tWHAX1 Trailing Edge of WR to Address Invalid (Note 3)68ns
t
WHAX2 Trailing Edge of WR to DPLD Address
Invalid (Note 3,6)00ns
t
WHPV Trailing Edge of WR to Po r t Outpu t
Valid Using I/O Port Data Register (Note 3)27 30 ns
tDVMV Data Valid to Port Output Valid
Using Macro cell Regist er
Preset/Clear (Notes 3,5)42 55 ns
tAVPV Address Input Valid to Address
Output Delay (Note 2)20 25 ns
tWLMV WR Valid to Port Output Valid Using
Macrocell Register Preset/Clear (Notes 3,4)48 55 ns
79/89
PSD4235G2
Figure 45. Write Timing
tAVLX tLXAX
tLVLX
tAVWL
tSLWL
tWHDX
tWHAX
tELTL
tEHEL
tWLMV
tWLWH
tDVWH
tTHEH
tAVPV
ADDRESS
VALID
ADDRESS
VALID
DATA
VALID
DATA
VALID
ADDRESS OUT
tWHPV
STANDARD
MCU I/O OUT
ALE/AS
A/D
MULTIPLEXED
BUS
ADDRESS
NON-MULTIPLEXED
BUS
DATA
NON-MULTIPLEXED
BUS
CSI
WR
(DS)
E
R/ W
AI02896
PSD4235G2
80/89
Table 67. Po rt F Perip heral Data Mo de Read Timing
Figure 46. P eripheral I/O Read Timing
Symbol Parameter Conditions -70 -90 Turbo
Off Unit
Min Max Min Max
tAVQV–PF Address Valid to Data
Valid (Note 3)30 35 + 12 ns
tSLQV–PF CSI Valid to Data Valid 25 35 + 12 ns
tRLQV–PF RD to Data Valid (Notes 1,4)21 32 ns
RD to Data Valid 8031 Mode 31 38 ns
tDVQV–PF Data In to Data Out Valid 22 30 ns
tQXRH–PF RD Data Hold Time 0 0 ns
tRLRH–PF RD Pulse Width (Note 1)27 32 ns
tRHQZ–PF RD to Data High-Z (Note 1)23 25 ns
tQXRH (PF)
tRLQV (PF)
tRLRH (PF)
tDVQV (PF)
tRHQZ (PF)
tSLQV (PF)
tAVQV (PF)
ADDRESS DATA VALID
ALE/AS
A/D BUS
RD
DATA ON PORT F
CSI
AI05740
81/89
PSD4235G2
Table 68. Po rt F Perip heral Data Mo de Write Tim ing
Note: 1. RD has the sam e t i mi ng as DS, LD S, U DS , and PSEN (in 8031 combined mode).
2. WR has the same timing as the E, LDS, U DS, W RL, and WRH signals.
3. Any input used to select Port F Data Peripheral mode.
4. Data i s alrea dy stab le on Port F.
5. Data stable on ADIO pins to d ata on Port F.
Figure 47. Peripheral I/O Wri te Timing
Symbol Parameter Conditions -70 -90 Unit
Min Max Min Max
tWLQV–PF WR to Data Propagation Delay (Note 2)25 35 ns
tDVQV–PF Data to Port F Data Propagation Delay (Note 5)22 30 ns
tWHQZ–PF WR Invalid to Port F Tri-state (Note 2)20 25 ns
tDVQV (PF)
tWLQV (PF) tWHQZ (PF)
ADDRESS DATA OUT
A/D BUS
WR
PORT F
DATA OUT
ALE/AS
AI05741
PSD4235G2
82/89
Table 69. Reset (Reset)Timing
No te : 1. Res et (R ESET) d oes not re set Flash m em ory Pr ogram or Er ase cycl es.
2. Warm reset abo rts Flash m emory Pr ogram or Erase cycles, an d puts the device in Read mod e.
Figure 48. Reset (RESET) Timing
Table 70. VSTBYON Tim in g
Note: 1. VSTBYON timing is measured at VCC ramp rate of 2 ms.
Table 71. Pro gr am, Write and Erase Times
Not e: 1. Programmed t o all zero before erase.
2. The po l ling sta tus, DQ7, i s valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for readi ng.
3. DQ7 is DQ15 for M otorola MCU w i th 16-bi t data bus.
Symbol Parameter Conditions Min Max Unit
tNLNH RESET Active Low Time 1150 ns
tNLNH–PO Power On Reset Active Low Time 1 ms
tNLNH–A Warm Reset 225 µs
tOPR RESET High to Operational Device 120 ns
Symbol Parameter Conditions Min Typ Max Unit
tBVBH VSTBY Detection to VSTBYON Output High (Note 1)20 µs
tBXBL VSTBY Off Detection to VSTBYON Output
Low (Note 1)20 µs
Symbol Parameter Min. Typ. Max. Unit
Flash Program 8.5 s
Flash Bulk Erase1 (pre-p rogramm ed) 330s
Flash Bulk Erase (not pre-pro grammed ) 10 s
tWHQV3 Sector Erase (pre-programmed) 1 30 s
tWHQV2 Sector Erase (not pre-programmed) 2.2 s
tWHQV1 Byte Program 14 1200 µs
Program / Erase Cycles (per Sector) 100,000 cycles
tWHWLO Sector Erase Time-Out 100 µs
tQ7VQV DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling)230 ns
tNLNH-PO tOPR
AI02866b
RESET
tNLNH
tNLNH-A tOPR
VCC VCC(min)
Power-On Reset Warm Reset
83/89
PSD4235G2
Table 72. ISC Timing
No te : 1. For non-PLD Pro grammi ng, Erase or in ISC b y-pass mode.
2. For Program or Erase PLD only.
Figure 49. ISC Timing
Symbol Parameter Conditions -70 -90 Unit
Min Max Min Max
tISCCF Clock (TCK, PC1) Frequency (except for
PLD) (Note 1)20 18 MHz
tISCCH Clock (TCK, PC1) High Time (except for
PLD) (Note 1)23 26 ns
tISCCL Clock (TCK, PC1) Low Time (except for
PLD) (Note 1)23 26 ns
tISCCFP Clock (TCK, PC1) Frequency (PLD only) (Note 2)2 2 MHz
tISCCHP Clock (TCK, PC1) High Time (PLD only) (Note 2)240 240 ns
tISCCLP Clock (TCK, PC1) Low Time (PLD only) (Note 2)240 240 ns
tISCPSU ISC Port Set Up Time 6 8 ns
tISCPH ISC Port Hold Up Time 5 5 ns
tISCPCO ISC Port Clock to Output 21 23 ns
tISCPZV ISC Port High-Impedance to Valid Output 21 23 ns
tISCPVZ ISC Port Valid Output to
High-Impedance 21 23 ns
ISCCH
TCK
TDI/TMS
ISC OUTPUTS/TDO
ISC OUTPUTS/TDO
t
ISCCL
t
ISCPH
t
ISCPSU
t
ISCPVZ
t
ISCPZV
tISCPCO
t
AI02865
PSD4235G2
84/89
Table 73. Power-down Timing
Note: 1. tCLCL i s t he period of CLKIN (PD 1).
Symbol Parameter Conditions -70 -90 Unit
Min Max Min Max
tLVDV ALE Access Time from Power-down 80 90 ns
tCLWH Maximum Delay from
APD Enable to Internal PDN Valid
Signal
Using CLKIN
(PD1) 15 * tCLCL1µs
85/89
PSD4235G2
PACKAGE MECHANICAL
TQFP80 - 80 lead Plastic Qu ad Flatpac k
Not e: Drawing is not to scale.
TQFP80 - 80 lead Plastic Qu ad Flatpac k
Symb. mm inches
Typ. Min. Max. Typ. Min. Max.
A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 0.950 1.050 0.0374 0.0413
α3.5° 0.0° 7.0° 3.5° 0.0° 7.0°
b 0.220 0.170 0.270 0.0087 0.0 067 0.0106
c 0.090 0.200 0.0035 0.0079
D 14.000 0.5512
D1 12.000 0.4724
D2 9.500 — — 0.3740 — —
E 14.000 0.5512
E1 12.000 0.4724
E2 9.500 — — 0.3740 — —
e 0.500 — — 0.0197 — —
L 0.600 0.450 0.750 0.0236 0.0 177 0.0295
L1 1.000 0.0394
CP 0.080 0.0031
N80 80
Nd 20 20
Ne 20 20
QFP-A
Nd
E1
CP
b
e
A2
A
N
LA1 α
D1
D
1
E
Ne
c
D2
E2
L1
PSD4235G2
86/89
Table 74. Pin Assignm ents – TQFP80
Pin No. Pin
Assign
ments Pin No. Pin
Assign
ments Pin No. Pin
Assign
ments Pin No. Pin
Assign
ments
1 PD2 21 PG0 41 PC0 61 PB0
2 PD3 22 PG1 42 PC1 62 PB1
3 AD0 23 PG2 43 PC2 63 PB2
4 AD1 24 PG3 44 PC3 64 PB3
5 AD2 25 PG4 45 PC4 65 PB4
6 AD3 26 PG5 46 PC5 66 PB5
7 AD4 27 PG6 47 PC6 67 PB6
8 GND 28 PG7 48 PC7 68 PB7
9VCC 29 VCC 49 GND 69 VCC
10 AD5 30 GND 50 GND 70 GND
11 AD6 31 PF0 51 PA0 71 PE0
12 AD7 32 PF1 52 PA1 72 PE1
13 AD8 33 PF2 53 PA2 73 PE2
14 AD9 34 PF3 54 PA3 74 PE3
15 AD10 35 PF4 55 PA4 75 PE4
16 AD11 36 PF5 56 PA5 76 PE5
17 AD12 37 PF6 57 PA6 77 PE6
18 AD13 38 PF7 58 PA7 78 PE7
19 AD14 39 RESET 59 CNTL0 79 PD0
20 AD15 40 CNTL2 60 CNTL1 80 PD1
87/89
PSD4235G2
PART NUMBERING
Table 75. Ordering Information Scheme
Note: 1. The 3.3V ±10% devices are not cov ered by thi s data she et, but by t he P SD4235G2V data sheet .
For a list of available options (speed, package,
etc.) or for further information on any aspect of this device, please c ontact your neares t ST Sales O f-
fice.
Example: PSD42 3 5 G 2 V –90U I T
Device Type
PSD42 = Flash PSD for 16-bit MCUs (with CPLD)
SRAM Siz e
0 = none 3 = 64 Kbit
1 = 16 Kbit 4 = 128 Kbit
2 = 32 Kbit 5 = 256 Kbit
Flash Memory Size
1 = 256 Kbit 4 = 2 Mbit
2 = 512 Kbit 5 = 4 Mbit
3 = 1 Mbit 6 = 8 Mbit
I/O Count
F = 27 I/O
G = 52 I/O
2nd Non Volatile
Memory
1 = 256 Kbit EEPROM
2 = 256 Kbit Flash memory
3 = none
6 = 512 Kbit Flash memory
Operating Voltage
blank = VCC = 4.5 to 5.5V
V1 = VCC = 3.0 to 3.6V
Speed
70 = 70 ns 12 = 120 ns
90 = 90 ns 15 = 150 ns
20 = 200 ns
Package
U = TQFP80
Temperature Range
blank = 0 to 70 °C (commercial)
I = –40 to 85 °C (industrial)
Option
T = Tape & Reel Packing
PSD4235G2
88/89
RE VISION HISTORY
Table 76. Document Revisio n History
Date Rev. Description of Revision
01-May-2001 1.0 Initial release as a WSI document
01-Aug-2001 1.1 Timing parameters updated
12-Sep-2001 2.0 Document rewritten using the ST template
14-Dec-2001 2.1 Information on the 3.3V±10% range removed to a separate data sheet
89/89
PSD4235G2
Info rm ation furnished i s believed to be accurate an d rel i able. However, STMicro el ectro ni cs assumes no responsibility for the cons equences
of use of such information nor for any inf ringement of patents or other rights of third parties which may result from its use. No license is grant ed
by i m pl i cation or oth erwise under any pat ent or paten t ri ghts of STMic roelec tr onics. Speci fications ment i oned in this publicati on are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical com ponents in lif e support devices or sy st ems wit hout exp ress writ t en approval of STMi croel ectronics.
The S T l ogo is re gi stered trade m ark of STMi croelectro nics
All other names are th e property of their respec tive owners
© 2001 STMicroelectronics - All Rights Reserved
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