Philips Semiconductors Product specification
N-channel TrenchMOS transistor PSMN015-100B, PSMN015-100P
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
EAS Non-repetitive avalanche Unclamped inductive load, IAS = 74 A; - 481 mJ
energy tp = 100 µs; Tj prior to avalanche = 25˚C;
VDD ≤ 50 V; RGS = 50 Ω; VGS = 10 V; refer
to fig:15
IAS Non-repetitive avalanche - 75 A
current
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
Rth j-mb Thermal resistance junction - 0.5 K/W
to mounting base
Rth j-a Thermal resistance junction SOT78 package, in free air 60 - K/W
to ambient SOT404 package, pcb mounted, minimum 50 - K/W
footprint
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V(BR)DSS Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 100 - - V
voltage Tj = -55˚C 89 - - V
VGS(TO) Gate threshold voltage VDS = VGS; ID = 1 mA 2.0 3.0 4.0 V
Tj = 175˚C 1.0 - - V
Tj = -55˚C - - 6 V
RDS(ON) Drain-source on-state VGS = 10 V; ID = 25 A - 12 15 mΩ
resistance Tj = 175˚C - - 41 mΩ
IGSS Gate source leakage current VGS = ±10 V; VDS = 0 V - 2 100 nA
IDSS Zero gate voltage drain VDS = 100 V; VGS = 0 V; - 0.05 10 µA
current Tj = 175˚C - - 500 µA
Qg(tot) Total gate charge ID = 75 A; VDD = 80 V; VGS = 10 V - 109 - nC
Qgs Gate-source charge - 20 - nC
Qgd Gate-drain (Miller) charge - 50 - nC
td on Turn-on delay time VDD = 50 V; RD = 1.8 Ω; - 30 - ns
trTurn-on rise time VGS = 10 V; RG = 5.6 Ω-80-ns
td off Turn-off delay time Resistive load - 150 - ns
tfTurn-off fall time - 95 - ns
LdInternal drain inductance Measured from tab to centre of die - 3.5 - nH
LdInternal drain inductance Measured from drain lead to centre of die - 4.5 - nH
LsInternal source inductance Measured from source lead to source - 7.5 - nH
bond pad
Ciss Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 4720 - pF
Coss Output capacitance - 650 - pF
Crss Feedback capacitance - 380 - pF
June 2003 2 Rev 1.200