[AK4104]
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GENERAL DESCRIPTION
The AK4104 is a digital audio interface transmitter (DIT) which sup ports data rate up to 192kHz sample rate
operation. The AK4104 encodes and transmits audio data ac cording to the AES3, IEC60958, S/PDIF & EIAJ
CP1201 interface stand ards. The AK4104 accepts audio and digital data, which is then encoded. The audi o
serial port supports four formats.
FEATURES
Sampling Rate up to 192kHz
Support AES3, IEC60958, S/PDIF & EIAJ CP1201 Consumer Formats
Generates Parity Bits
1-channel Transmission Output
42-bit Channel Status Buffer
Supports Multiple Clock Frequencies: 128/192/256/384/512/768/1024/1536fs
Supports Left/Right justified and I2S Audio Formats
Easy to use 4 wire/3 wire Serial Host Interface
CMOS Input Level
Power Supply: 2.7 to 3.6V
Small Package: 16pin TSSOP
Temperature Range of -20 to 85 °C
192kHz 24-Bit 3.3V DIT
AK4104
[AK4104]
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LRCK
BICK
Audio
Data
Interface
MCLK
PDN
Prescaler
Biphase
Encoder
SDTI1
TX
CDT O
CSN
CCLK
CDTI
µP
Interface VDD
VSS
Figure 1. AK4104 Block Diagram (Mode= “0”)
LRCK
BICK
Audio
Data
Interface
MCLK
PDN
Prescaler
Biphase
Encoder
SDTI1 TX
CSN
CCLK
CDTI
µP
Interface VDD
VSS
SDTI2
Figure 2. AK4104 Block Diagram (Mode= “1”)
[AK4104]
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■ Ordering Guide
AK4104ET −20 ∼ +85°C 16pin TSSOP (0.65mm pitch)
AKD4104 Evaluation Board for AK4104
■ Pin Layout
1
MCLK
LRC
K
BIC
K
CSN
CCL
K
CDTI
AK4104
Top
View
2
3
4
5
6
7
8
TX
VDD
CDTO/ SDTI2
VSS
TEST4
TEST3
TEST2
16
15
14
13
12
11
10
9
PDN
SDTI1
TEST1
[AK4104]
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PIN/FUNCTION
No. Pin Name I/O Function
1 MCLK I Master Clock Input Pin
2 BICK I Audio Serial Data Clock Pin
3 SDTI1 I Audio Serial Data Input 1 Pin
4 LRCK I Input Channel Clock Pin
5 PDN I Power Down and Reset Pin
“L”: Power down and Reset, “H”: Power up
6 CSN I Chip Select Pin
7 CCLK I Control Data Clock Pin
8 CDTI I Control Data Input Pin
9 TEST1 I TEST Pin
This pin should be connected to VDD.
10 TEST2 O TEST Pin
This pin should be OPEN.
11 TEST3 O TEST Pin
This pin should be OPEN.
12 TEST4 O TEST Pin
This pin should be OPEN.
13 VSS - Ground Pin
14 VDD - Power Supply Pin, 2.7 ∼ 3.6V
CDTO O Control Data Output Pin, The output is “Hi-Z” when PDN pin = “L”.
15 SDTI2 I Audio Serial Data Input 2 Pin
16 TX O Transmit Channel Output Pin, The output is “L” when PDN pin = “L” or RSTN bit
=“0” or PW bit = “0” or MCLK stops.
Note: All digital input pins should not be left floating.
[AK4104]
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ABSOLUTE MAXIMUM RATINGS
(VSS=0V; Note 1)
Parameter Symbol min max Units
Power Supply VDD −0.3 4.6 V
Input Current, Any Pin Except Supplies IIN - ±10 mA
Digital Input Voltage (Note 2) VIND −0.3 VDD+0.3 V
Ambient Temperature (Powered applied) Ta −20 85 °C
Storage Temperature Tstg −65 150 °C
Note 1. All voltages with respect to ground.
Note 2. MCLK, BICK, SDTI1, LRCK, PDN, CSN, CCLK, CDTI, SDTI2
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS=0V; Note 1)
Parameter Symbol min typ max Units
Power Supply VDD 2.7 3.3 3.6 V
Note 1. All voltages with respect to ground.
WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
DC CHARACTERISTICS
(Ta=25°C; VDD=2.7 ∼ 3.6V)
Parameter Symbol min typ max Units
Power Supply Current (Note 3)
Normal Operation (PDN pin = “H”, fs=44.1kHz) (Note 3)
Full power-down mode (PDN pin = “L”) (Note 4)
0.9
10
1.8
50
mA
μA
High-Level Input Voltage
Low-Level Input Voltage
VIH
VIL
70%VDD
-
-
-
-
30%VDD
V
V
High-Level Output Voltage (Iout=-80μA)
Low-Level Output Voltage (Iout=80µA)
VOH1
VOL1
VDD-0.4
-
-
-
-
0.4
V
V
Input Leakage Current Iin - - ± 10 µA
Note 3. TX pin: open . Power supply current (IDD@3.3V) is 1.0mA(typ)@fs=48kHz, 1.4mA(typ)@fs=96kHz and
2.6mA(typ)@fs=192kHz. IDD is 10µA(typ) if PDN= “L” and all other input pins are held to VSS(@3.3V).
(TX pin: 20pF, Power supply current (IDD@3.3V) is 3.3mA(typ)@fs=192kHz.)
Note 4. All digital input pins are fixed to VDD or VSS.
TX CHARACTERISTICS
(Ta=25°C; VDD=2.7 ∼ 3.6V)
Parameter Symbol min typ max Units
High-Level Output Voltage ( Iout=-400μA)
Low-Level Output Voltage ( Iout=400μA)
VOH2
VOL2
VDD-0.4
-
-
-
-
0.4
V
V
Load Capacitance CL - - 50 pF
[AK4104]
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SWITCHING CHARACTERISTICS
(Ta=25°C; VDD=2.7 ∼ 3.6V, CL=20pF)
Parameter Symbol min typ max Units
Master Clock Frequency
Frequency
Duty Cycle
fCLK
dCLK
2.048
40
36.864
60
MHz
%
LRCK Frequency
Frequency
Duty Cycle
fs
dCLK
8
45
192
55
kHz
%
Audio Interface Timing
BICK Period
BICK Pulse Width Low
Pulse Width High
BICK “↑” to LRCK Edge (Note 5)
LRCK Edge to BICK “↑” (Note 5)
SDTI Hold Time
SDTI Setup Time
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
81
30
30
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
CDTO Delay
CSN “↑” to CDTO Hi-Z
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tDCD
tCCZ
200
80
80
40
40
150
150
50
45
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Power-Down & Reset Timing
PDN Pulse Width (Note 6)
tPD
150
ns
Note 5. BICK rising edge must not occur at the same time as LRCK edge.
Note 6. The AK4104 can be reset by bringing PDN pin = “L”.
[AK4104]
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■ Timing Diagram
1/fCLK
tCLKL
VIH
tCLKH
MCLK VIL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK VIL
tBCK
tBCKL
VIH
tBCKH
BICK VIL
Figure 3. Clock Timing
tLRB
LRCK
VIH
BICK VIL
tSDS
VIH
SDTI VIL
tSDH
VIH
VIL
tBLR
Figure 4. Serial Interface Timing
[AK4104]
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tCCKL
CSN
CCLK
tCDS
CDTI
tCDH
tCSS
C0 A4
tCCKH
CDTO Hi-Z
R/W
C1
VIH
VIL
VIH
VIL
VIH
VIL
tCCK
Figure 5. WRITE/READ Command Input Timing in 3-wire/4-wire serial mode
tCSW
CSN
CCLK
CDTI D2 D0
tCSH
CDTO Hi-Z
D1D3
VIH
VIL
VIH
VIL
VIH
VIL
Figure 6. WRITE Data Input Timing in 3-wire/4-wire serial mode
CSN
CCLK
tDCD
CDTO D7 D6
CDTI A1 A0
D5
Hi-Z 50%VDD
VIH
VIL
VIH
VIL
VIH
VIL
Figure 7. READ Data Output Timing 1 in 4-wire serial mode
[AK4104]
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CSN
CCLK
tCCZ
CDTO D2 D1
CDTI
D0
D3
tCSW
tCSH
50%VDD
VIH
VIL
VIH
VIL
VIH
VIL
Hi-Z
Figure 8. READ Data Output Timing 2 in 4-wire serial mode
tPD
VIL
PDN
Figure 9. Power-Down & Reset Timing
[AK4104]
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OPERATION OVERVIEW
■ Reset and Initialization
The AK4104 should be reset once by bringing PDN = “L” upon power-up. It takes 8 bit clock cycles for the AK4104 to
initialize after PDN pin goes “H”.
■ MCLK and LRCK Relationship
For correct synchronization, MCLK and LRCK should be derived from the same clock signal either directly (as through a
frequency divider) or indirectly (for example, as through a DSP). The phase relationship between MCLK and LRCK
should be kept after power-up. The MCLK frequencies shown in Table 1 are supported. The internal clock frequency is
set depending on the external MCLK frequency automatically.
MCLK Fs
128fs 16k-192kHz
192fs 16k-192kHz
256fs 8k-128kHz
384fs 8k-96kHz
512fs 8k-48kHz
768fs 8k-48kHz
1024fs 8k-32kHz
1536fs 8k-24kHz
Table 1. MCLK Frequency
[AK4104]
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■ Audio Interface Format
Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF1-0 bits as shown in Table 2 can select four
serial data modes. In all modes the serial data is MSB-first, 2’s compliment format and is latched on the rising edge of
BICK. Mode 3 can be used for 16bit I2S Compatible format by zeroing the unused LSBs at BICK ≥ 48fs or BICK = 32fs.
Mode DIF1 DIF0 SDTI Format BICK Figure
0 0 0 16bit, LSB justified ≥ 32fs Figure 10
1 0 1 24bit, LSB justified ≥ 48fs Figure 11
2 1 0 24bit, MSB justified
≥ 48fs Figure 12
3 1 1 16/24bit, I2S Compatible ≥ 48fs or 32fs Figure 13
Table 2. Audio Interface Format
LRCK
BICK(32fs) 01102 3 9 1112131415 0 123 10109 1112131415
SDTI(i) Don't Care 1 0 15 14 13 21015 14 13 12 12Don't Care
SDTI-15:MSB, 0:LSB
SDTI(i) 15 14 13 7654321015 14 13 1576543210
BICK(64fs) 01182 3 19 20 31 0 1 2 3 1018 19 20 3117 17
Lch Data Rch Data
Figure 10. Mode 0 Timing
LRCK
BICK(64fs) 0 1 22431012 10312489 89
SDTI(i) Don't Care 0 8 10
23:MSB, 0:LSB
Lch Data Rch Data
23 8 Don't Care 231
Figure 11. Mode 1 Timing
LRCK
BICK(64fs) 0 1 220212431012 102220 21 312422 23 23
SDTI(i) Don't Care0 0
23:MSB, 0:LSB
Lch Data Rch Data
Don't Care
432123 22 23 22 231234
Figure 12. Mode 2 Timing
[AK4104]
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LRCK
BICK(64fs) 0122521 24 0 12 1022 2521 2422 23 233
SDTI(i) Don't Care0 0
23:MSB, 0:LSB
Lch Data Rch Data
Don't Care
432123 22 23 22 1234
Figure 13. Mode 3 Timing
■ DIT input select
The AK4104 can select 4-wire μP I/F mode (MODE bit = “0”) or 3-wire μP I/F mode (MODE bit = “1”). In 3-wire μP I/F
mode, the AK4104 can select the input data of DIT from SDTI1 or SDTI2 data.
MODE SEL1 SEL0 μP I/F DIT input
0 x x 4-wire SDTI1
1 0 0 3-wire SDTI1
1 0 1 3-wire SDTI2
1 1 0 3-wire SDTI2:DIT Bypass
1 1 1 Reserved
(x: Don’t care)
Table 3. DIT Input
[AK4104]
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■ Data Transmission Format
The Data transmitted on the TX outputs is formatted in blocks as shown in Figure 14. Each block consists of 192 frames.
A frame of data contains two sub-frames. A sub-frame consists of 32 bits of information. Each received data bit is coded
using a bi-phase mark encoding as a two binary state symbol. The preambles violate bi-phase encoding so they may be
differentiated from data. In bi-phase encoding, the first state of input symbol is always the inverse of the last state of the
previous data symbol. For a logic 0, the second state of the symbol is the same as the first state. For a logic 1, the second
state is opposite of the first. Figure 15 illustrates a sample stream of 8 data bits encoded in 16 symbol states.
Frame 191 Frame 0 Frame 1
Sub-frame Sub-frame
MChannel 1 WChannel 2 BChannel 1 WChannel 2 MChannel 1 WChannel 2
Figure 14. Block format
0 1 1 0 0 0 1 0
Figure 15. A biphase-encoded bit stream
The sub-frame is defined in Figure 16 below. Bits 0-3 of the sub-frame represent a preamble for synchronization. There
are three preambles. The block preamble, B, is contained in the first sub-frame of Frame 0. The channel 1 preamble, M, is
contained in the first sub-frame of all other frames. The channel 2 preamble, W, is contained in all of the second
sub-frames.
Table 4 below defines the symbol encoding for each of the preambles. Bits 4-27 of the sub-frame contain the 24 bit audio
sample in 2’s complement format with bit 27 as the most significant bit. For 16 bit mode, Bits 4-11 are all 0. Bit 28 is the
validity flag. It is “H” if the audio sample is unreliable. Bit 29 is a user data bit. Frame 0 contains the first bit of a 192 bit
user data word. Frame 191 contains the last bit of the user data word. Bit 30 is a channel status bit. Again frame 0 contains
the first bit of the 192 bit word with the last bit in frame 191. Bit 31 is an even parity bit for bits 4-31 of the sub-frame.
Sync P
C
UV
L M
S A u d io s a mp le S
B B
0 3 4 2 7 28 2 9 3 0 3 1
Figure 16. Sub-frame format
The block of data contains consecutive frames transmitted at a state-bit rate of 64 times the sample frequency, fs. For
stereophonic audio, the left or A channel data is in channel 1 while the right or B data is in channel 2. For monophonic
audio, channel 1 contains the audio data.
Preamble Preceding state = 0 Preceding state = 1
B 11101000 00010111
M 11100010 00011101
W 11100100 00011011
Table 4. Sub-frame preamble encoding
Channel Status bit
In the consumer mode (bit0 = “0”), bits20-23(audio channel) must be controlled by the CT20 bit. When the CT20 bit is
“1”, the AK4104 corresponds to “stereo mode”, bits20-23 are set to “1000”(left channel) in sub-frame 1, and is set to
“0100”(right channel) in sub-frame 2. When the CT20 bit is “0”, bits20-23 is set to “0000” in both sub-frame 1 and
sub-frame 2.
[AK4104]
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■ μP Control Interface
The AK4104 can select 4-wire μP I/F mode (MODE bit = “0”) or 3-wire μP I/F mode (MODE bit = “1”).
1.4-wire Serial mode (MODE bit = “0”, default)
The internal registers may be either written or read by the 4-wire μP interface pins: CSN, CCLK, CDTI and CDTO. The
data on this interface consists of Chip address (2bits, C1/0; fixed to “11”), Read/Write (1bit), Register address (MSB first,
5bits) and Control data (MSB first, 8bits). Address and data are clocked in on the rising edge of CCLK and data is clocked
out on the falling edge. For write operations, data is latched after the 16th rising edge of CCLK, after a high-to-low
transition of CSN. CSN should be set to “H” once after the 16th CCLK. For read operations, the CDTO output goes high
impedance after a low-to-high transition of CSN. The maximum speed of CCLK is 5MHz. PDN pin = “L” resets the
registers to their default values.
CDTI
CCLK
CSN
C1
0 1 2 345678 9 10 11 12 13 14 15
D4D5D6D7A1A2A3A4R/WC0 A0 D0 D1 D2 D3
CDTO Hi-Z
WRITE
CDTI C1 D4D5D6D7A1A2A3A4R/WC0 A0 D0 D1 D2 D3
CDTO Hi-Z
READ
D4D5D6D7 D0 D1 D2 D3 Hi-Z
C1-C0: Chip Address: (Fixed to “11”)
R/W: READ/WRITE (0:READ, 1:WRITE)
A4-A0: Register Address
D7-D0: Control Data
Figure 17. 4-wire μP I/F Timing
*When the AK4104 is in the power down mode (PDN pin = “L”) or the MCLK is not provided, writing into the control
register is inhibited.
[AK4104]
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2.3-wire μP I/F mode (MODE bit = “1”)
Internal registers may be written by 3-wire µP interface pins, CSN, CCLK and CDTI. The data on this interface consists
of Chip Address (2bits, C1/0; fixed to “11”), Read/Write (1bit; fixed to “1”, Write only), Register Address (MSB first,
5bits) and Control Data (MSB first, 8bits). The AK4104 latches the data on the rising edge of CCLK, so data should
clocked in on the falling edge. The writing of data becomes valid by 16th CCLK after a high to low transition of CSN.
CSN should be set to “H” once after the 16th CCLK. The clock speed of CCLK is 5MHz (max).
PDN pin = “L” resets the registers to their default values. The internal timing circuit is reset by RSTN bit, but the registers
are not initialized.
CDTI
CCLK
CSN
C1
012345678 9 10 11 12 13 14 15
D4D5D6D7A1A2A3A4R/WC0 A0 D0D1D2D3
C1-C0: Chip Address (Fixed to “11”)
R/W: READ/WRITE (Fixed to “1”, Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 18. 3-wire μP I/F Timing
*The AK4104 does not support the read command and chip address. C1/0 and R/W are fixed to “011”
*When the AK4104 is in the power down mode (PDN pin = “L”) or the MCLK is not provided, writing into the control
register is inhibited.
[AK4104]
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■ Register Map
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Control 1 1 0 0 0 DIF1 DIF0 PW RSTN
01H Reserved 0 1 0 1 1 0 1 1
02H Control 2 0 0 0 0 0 MODE SEL1 SEL0
03H TX 1 0 0 0 0 0 V TXE
04H Channel Status Byte0 CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0
05H Channel Status Byte1 CS15 CS14 CS13 CS12 CS11 CS10 CS9 CS8
06H Channel Status Byte2 CS23 CS22 CS21 CS20 CS19 CS18 CS17 CS16
07H Channel Status Byte3 CS31 CS30 CS29 CS28 CS27 CS26 CS25 CS24
08H Channel Status Byte4 CS39 CS38 CS37 CS36 CS35 CS34 CS33 CS32
09H Channel Status Byte5 0 0 0 0 0 0 CS41 CS40
Notes:
For addresses from 0AH to 1FH, data must not be written.
When PDN pin goes “L”, the registers are initialized to their default values.
When RSTN bit goes “0”, the only internal timing is reset and the registers are not initialized to their default
values. All data can be written to the register even if PW or RSTN bit is “0”.
The “0” register should be written “0”, the “1” register should be written “1” data.
■ Register Definitions
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Control 1 1 0 0 0 DIF1 DIF0 PW RSTN
R/W R/W
Default 1 0 0 0 1 1 1 1
RSTN: Internal timing reset control
0: Reset. All registers are not initialized.
1: Normal Operation
PW: Power down control
0: Power down. All registers are not initialized.
1: Normal Operation
DIF1-0: Audio data interface formats (Table 2)
Initial: “11”, Mode 3
[AK4104]
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Register Name D7 D6 D5 D4 D3 D2 D1 D0
02H Control 3 0 0 0 0 0 MODE SEL1 SEL0
R/W R/W
Default 0 0 0 0 0 0 0 0
MODE: Mode Control
0: 4 wire mode
1: 3 wire mode
SEL1-0: DIT input
00: SDTI1 input
01: SDTI2 input
10: SDTI2 input (DIT Bypass)
11: Reserved
(NOTE) SEL1-0 bits can not use in 4 wire mode (MODE=“0”).
Register Name D7 D6 D5 D4 D3 D2 D1 D0
03H TX 1 0 0 0 0 0 V TXE
R/W R/W
Default 1 0 0 0 0 0 0 1
V: Validity Flag
0: Valid
1: Invalid
TXE: TX output
0: “L”
1: normal operation
Register Name D7 D6 D5 D4 D3 D2 D1 D0
04H Channel Status Byte0 CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0
Default 0 0 0 0 0 1 0 0
05H Channel Status Byte1 CS15 CS14 CS13 CS12 CS11 CS10 CS9 CS8
Default 0 0 0 0 0 0 0 0
06H Channel Status Byte2 CS23 CS22 CS21 CS20 CS19 CS18 CS17 CS16
Default 0 0 0 0 0 0 0 0
07H Channel Status Byte3 CS31 CS30 CS29 CS28 CS27 CS26 CS25 CS24
Default 0 0 0 0 0 0 0 0
08H Channel Status Byte4 CS39 CS38 CS37 CS36 CS35 CS34 CS33 CS32
Default 0 0 0 0 0 0 0 0
09H Channel Status Byte5 0 0 0 0 0 0 CS41 CS40
Default 0 0 0 0 0 0 0 0
CS7-0: Transmitter Channel Status Byte 0
Default: “00000100”
CS39-8: Transmitter Channel Status Byte 4-1
Default: “00000000”
CS41-CS40: Transmitter Channel Status Byte 5
Default: “00000000”, D7-D2 bits should be written “1”.
[AK4104]
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SYSTEM DESIGN
Figure 19 and Figure 20 show the system connection diagram. The evaluation board AKD4104 demonstrates application
circuits, the optimum layout, power supply arrangements and measurement results.
MCLK
1
BICK
2
SDTI
3
LRCK
4
PDN
5
CSN
6
CCLK
7
CDTI 8
TX 16
CDTO 15
VDD 14
VSS 13
TEST4 12
TEST3 11
TEST2 10
TEST1 9
Master Clock
AK4104
fs
24bit Audio Data
Reset & Power down
64fs
0.1u +
A
nalog Suppl
y
2.7 to 3.6V
10u
Optic transmitting
module
Micro
Controller
Figure 19. Typical Connection Diagram (Mode= “0”, 4 wire mode )
MCLK
1
BICK
2
SDTI
3
LRCK
4
PDN
5
CSN
6
CCLK
7
CDTI 8
TX 16
SDTI2 15
VDD 14
VSS 13
TEST4 12
TEST3 11
TEST2 10
TEST1 9
Master Clock
AK4104
fs
24bit Audio Data1
Reset & Power down
64fs
0.1u +
A
nalog Suppl
y
2.7 to 3.6V
10u
Optic transmitting
module
Micro
Controller
24bit Audio Data2
Figure 20. Typical Connection Diagram (Mode= “1”, 3 wire mode )
[AK4104]
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PACKAGE
0-10°
Detail A
Seating Plane
0.10
0.17±0.05
0.22±0.1 0.65
*5.0±0.1 1.1 (max )
A
1 8
9 16
16pin TSSOP (Unit: mm)
*4.4±0.1
6.4±0.2
0.5±0.2
0.1±0.1
NOTE: Dimension "*" does not include mold flash.
0.13 M
■ Package & Lead frame material
Package molding compound: Epoxy
Lead frame material: Cu
Lead frame surface treatment: Solder (Pb free) plate
[AK4104]
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MARKING
AKM
4104ET
XX YYY
1) Pin #1 indication
2) Date Code : XXYYY (5 digits)
XX: Lot#
YYY: Date Code
3) Marketing Code : 4104ET
4) Asahi Kasei Logo
REVISION HISTORY
Date (YY/MM/DD) Revision Reason Page Contents
07/07/09 00 First Edition
10/09/28 01 Specification
Change
19 PACKAGE
The package dimension was changed.
[AK4104]
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IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
