BLOCK DIAGRAM
1
May 1997
ML2281, ML2282*,
ML2284#, ML2288#
Serial I/O 8-Bit A/D Converters with
Multiplexer Options
GENERAL DESCRIPTION
The ML2281 family are 8-bit successive approximation
A/D converters with serial I/O and configurable input
multiplexers with up to 8 input channels.
All errors of the sample-and-hold, incorporated on the
ML2281 family are accounted for in the analog-to-digital
converters accuracy specification.
The voltage reference can be externally set to any value
between GND and VCC, thus allowing a full conversion
over a relatively small voltage span if desired.
The ML2281 family is an enhanced double polysilicon
CMOS pin compatible second source for the ADC0831,
ADC0832, ADC0834, and ADC0838 A/D converters. The
ML2281 series enhancements are faster conversion time,
true sample-and-hold function, superior power supply
rejection, improved AC common mode rejection, faster
digital timing, and lower power dissipation. All parameters
are guaranteed over temperature with a power supply
voltage of 5V ±10%.
FEATURES
■Conversion time: 6µs
■Total unadjusted error: ±1/2LSB or ±1LSB
■Sample-and-hold: 375ns acquisition
■2, 4 or 8-input multiplexer options
■0 to 5V analog input range with single 5V
power supply
■Operates ratiometrically or with up to 5V
voltage reference
■No zero or full-scale adjust required
■ML2281 capable of digitizing a 5V, 40kHz sine wave
■Low power: 12.5mW MAX
■Superior pin compatible replacement for ADC0831,
ADC0832, ADC0834, and ADC0838
■Analog input protection: 25mA (min) per input
■Now in 8-Pin SOIC Package (ML2281, ML2282)
INPUT
SHIFT-REGISTER
OUTPUT
SHIFT-REGISTER
SHUNT
REGULATOR
CONTROL
AND
TIMING
DI
SARS
CLK
CS
DO
4-BIT
SE
DGND
V+
V
CC
V
REF
AGND
COMMON
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
A/D
CONVERTER
WITH
SAMPLE & HOLD
FUNCTION
MULTIPLEXER
(ML2288 SHOWN)
Σ
V
REF
CLK
CS
V
IN–
SUCCESSIVE
APPROXIMATION
REGISTER
D/A
CONVERTER
+
–
OUTPUT
SHIFT-REGISTER
CONTROL
AND
TIMING
COMP
A/D WITH SAMPLE & HOLD FUNCTION
8pF
8pF
–
+
V
IN+
V
CC
GND
DO
ML2281
ML2288
(8-Channel SE or 4-Channel Diff Multiplexer)
ML2284
(4-Channel SE or 2-Channel Diff Multiplexer)
ML2284
(2-Channel SE or 1-Channel Diff Multiplexer)
(* Indicates Part is Obsolete)
(# Indicates Part is End Of Life as Of July 1, 2000)
ML2281, ML2282, ML2284, ML2288
2
PIN CONFIGURATION
CS
V
IN+
V
IN–
GND
V
CC
CLK
DO
V
REF
1
2
3
4
8
7
6
5
TOP VIEW
TOP VIEW
CS
VIN+
VIN–
GND
VCC
CLK
DO
VREF
1
2
3
4
8
7
6
5
TOP VIEW
CS
CH0
CH1
GND
V
CC
(V
REF
)
CLK
DO
DI
1
2
3
4
8
7
6
5
TOP VIEW
V+
CS
CH0
CH1
CH2
CH3
DGND
V
CC
DI
CLK
SARS
DO
V
REF
AGND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
ML2281
Single Differential Input
8-Pin DIP
ML2282
2-Channel MUX
8-Pin DIP
ML2281
8-Pin SOIC ML2282
8-Pin SOIC
ML2284
14-Pin SOIC
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
DGND
V
CC
V+
CS
DI
CLK
SARS
DO
SE
V
REF
AGND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
TOP VIEW
ML2288
8-Channel MUX
20-Pin DIP
CS
DI
CLK
SARS
DO
CH3
CH4
CH5
CH6
CH7
910111213
CH2
CH1
CH0
V
CC
V+
COM
DGND
AGND
V
REF
SE
4
5
6
7
8
3212019
18
17
16
15
14
TOP VIEW
TOP VIEW
V+
CS
CH0
CH1
CH2
CH3
DGND
V
CC
DI
CLK
SARS
DO
V
REF
AGND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
ML2284
4-Channel MUX
14-Pin DIP
ML2288
8-Channel MUX
20-Pin PCC
CS
CH0
CH1
GND
V
CC
(V
REF
)
CLK
DO
DI
1
2
3
4
8
7
6
5
TOP VIEW
ML2281, ML2282, ML2284, ML2288
3
NAME FUNCTION
VCC Positive supply. 5V ± 10%
DGND Digital ground. 0 volts. All digital inputs and
outputs are referenced to this point.
AGND Analog ground. The negative reference voltage
for A/D converter.
CH0-7, Analog inputs. Digitally selected to be single
VIN+, VIN– ended (VIN) or; VIN+ or VIN– of a differential
input. Analog range = GND - VIN - VCC.
COM Common reference point for analog inputs.
A/D conversion is performed on voltage
difference between analog input and this
common reference point if single-end
conversion is specified.
VREF Reference. The positive reference voltage for
A/D converter.
SE Shift enable. Input controls whether LSB first
bit stream is shifted out on serial output DO.
If SE = 1, MSB first is shifted out only. If SE = 0,
an MSB first bit stream is shifted out, then a
second bit stream with LSB first is shifted out
after end of conversion.
V+ Input to the Shunt Regulator.
PIN DESCRIPTION
NAME FUNCTION
DO Data out. Digital output which contains result
of A/D conversion. The serial data is clocked
out on falling edges of CLK.
SARS Successive approximation register status.
Digital output which indicates that a
conversion is in progress. When SARS goes
to 1, the sampling window is closed and
conversion begins. When SARS goes to 0,
conversion is completed. When CS = 1, SARS
is in high impedance state.
CLK Clock. Digital input which clocks data in on
DI on rising edges and out on DO on falling
edges. Also used to generate clocks for A/D
conversion.
DI Data input. Digital input which contains serial
data to program the MUX and channel
assignments.
CS Chip select. Selects the chip for multiplexer
and channel assignment and A/D conversion.
When CS = 1, all digital outputs are in high
impedance state. When CS = 0, normal A./D
conversion takes place.
ML2281, ML2282, ML2284, ML2288
4
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, TA = TMIN to TMAX, VCC = VREF = 5V ±10%, and fCLK = 1.333MHz.
ML228XB ML228XC
TYP TYP
SYMBOL PARAMETER CONDITIONS MIN NOTE 3 MAX MIN NOTE 3 MAX UNITS
CONVERTER AND MULTIPLEXER CHARACTERISTICS
Total Unadjusted VREF = VCC (Notes 4, 6) ±1/2 ±1 LSB
Error
Reference Input (Notes 4, 7) 10 15 20 10 15 20 kW
Resistance
Common-Mode (Notes 4, 8) GND VCC GND VCC V
Input Range –0.05 +0.05 –0.05 +0.05
DC Common-Mode Common mode voltage ±1/16 ±1/4 ±1/16 ±1/4 LSB
Error voltage GND to VCC/2
(Note 5)
AC Common-Mode Common mode voltage ±1/4 ±1/4 LSB
Error GND to VCC/2,
0 to 50kHz (Note 5)
DC Power Supply VCC = 5V ±10% ±1/32 ±1/4 ±1/32 ±1/4 LSB
Sensitivity VREF - VCC +0.1V
(Note 5)
AC Power Supply 100mVP-P, 25kHz sine ±1/4 ±1/4 LSB
Sensitivity on VCC (Note 5)
Change in Zero 15mA into V+ ±1/2 ±1/2 LSB
Error from VCC=5V VCC = N.C. VREF = 5V
to Internal Zener (Note 5)
Operation
VZInternal Diode 15mA into V+ 6.9 6.9 V
Regulated Break-
down (at V+)
V+ Input Resistance (Note 4) 20 35 20 35 kW
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.
Current into V+ ...................................................... 15mA
Supply Voltage, VCC ................................................. 6.5V
Voltage
Logic Inputs ...........................................–7 to VCC +7V
Analog Inputs ................................ –0.3V to VCC +0.3V
Input Current per Pin (Note 1) ..............................±25mA
Storage Temperature ................................ –65°C to 150°C
Package Dissipation
at TA = 25°C (Board Mount) .............................800mW
Lead Temperature (Soldering 10 sec.)
Dual-In-Line Package (Molded) .......................... 260°C
Dual-In-Line Package (Ceramic) ......................... 300°C
Molded Chip Carrier Package
Vapor Phase (60 sec.) ..................................... 215°C
Infrared (15 sec.)............................................. 220°C
OPERATING CONDITIONS
Supply Voltage, VCC ............................ 4.5VDC to 6.3VDC
Temperature Range (Note 2) ................. TMIN - TA - TMAX
ML2281/2/4/8 BIX .................................. –40°C to 85°C
ML2281/2/4/8 CIX
ML2281/2/4/8 BCX ....................................0°C to 70°C
ML2281/2/4/8 CCX
ML2281, ML2282, ML2284, ML2288
5
ELECTRICAL CHARACTERISTICS
(Continued)
ML228XB ML228XC
TYP TYP
SYMBOL PARAMETER CONDITIONS MIN NOTE 3 MAX MIN NOTE 3 MAX UNITS
CONVERTER AND MULTIPLEXER CHARACTERISTICS (CONTINUED)
IOFF Off Channel On channel = VCC –1 –1 µA
Leakage Current Off channel = 0V
(Notes 4, 9)
On channel = 0V +1 +1 µA
Off channel = VCC
(Notes 4, 9)
ION On Channel On channel = 0V –1 –1 µA
Leakage Current Off channel = VCC
(Notes 4, 9)
On channel = VCC +1 +1 µA
Off channel = 0V
(Notes 4, 9)
DIGITAL AND DC CHARACTERISTICS
VIN(1) Logical “1” (Note 4) 2.0 2.0 V
Input Voltage
VIN(0) Logical “0” (Note 4) 0.8 0.8 V
Input Voltage
IIN(1) Logical “1” Input VIN = VCC (Note 4) 1 1 µA
Current
IIN(0) Logical “0” Input VIN = 0V (Note 4) –1 –1 µA
Current
VOUT(1) Logical “1” IOUT = –2mA (Note 4) 4.0 4.0 V
Output Voltage
VOUT(0) Logical “0” IOUT = 2mA (Note 4) 0.4 0.4 V
Output Voltage
IOUT HI-Z Output VOUT = 0V (Note 4) –1 –1 µA
Current VOUT = VCC 11µA
I
SOURCE Output Source VOUT = 0V (Note 4) –6.5 –6.5 mA
Current
ISINK Output Sink Current VOUT = VCC (Note 4) 8.0 8.0 mA
ICC Supply Current ML2281, ML2284 1.3 2.5 1.3 2.5 mA
ML2288 (Note 4)
ML2282 Includes ladder 1.8 3.5 1.8 3.5 mA
Current (Note 4)
ML2281, ML2282, ML2284, ML2288
6
ELECTRICAL CHARACTERISTICS
(Continued)
TYP LIMIT
SYMBOL PARAMETER CONDITIONS MIN NOTE 3 MAX UNITS
AC ELECTRICAL CHARACTERISTICS
fCLK Clock Frequency (Note 4) 10 1.333 kHz
tACQ Sample-and-Hold Acquisition 1/2 1/fCLK
tCConversion Time Not including MUX adddressing time 8 1/fCLK
SNR Signal to Noise Ratio VIN = 40kHz, 5V sine. fCLK = 1.333MHz 47 dB
ML2281 (fSAMPLING » 120kHz). Noise is sum of all
nonfundamental components up to 1/2
of fSAMPLING (Note 11)
THD Total Harmonic Distortion VIN = 40kHz, 5V sine. fCLK = 1.333MHz –60 dB
ML2281 (fSAMPLING » 120kHz). THD is sum of 2,
3, 4, 5 harmonics relative to fundamental
(Note 11)
IMD Intermodulation Distortion VIN = fA + fB. fA = 40kHz, 2.5V sine. –60 dB
ML2281 fB = 39.8kHz, 2.5V Sine, fCLK = 1.333MHz
(fSAMPLING » 120kHz). IMD is (fA + fB),
(fA – fB), (2fA + fB), (2fA – fB), (fA + 2fB),
(fA – 2fB) relative to fundamental (Note 11)
Clock Duty Cycle (Notes 4, 10) 40 60 %
tSET-UP CS Falling Edge or Data Input (Note 4) 130 ns
Valid to CLK Rising Edge
tHOLD Data Input Valid after (Note 4) 80 ns
CLK Rising Edge
tPD1, CLK Falling Edge to Output CL = 100pF (Note 4 & 12)
tPD0 Data Valid Data MSB first 90 200 ns
Data LSB first 50 110 ns
t1H, Rising Edge of CS to Data CL = 10pF, RL = 10k (see high impedance 40 90 ns
t0H Output and SARS Hi-Z test circuits) (Note 5)
CL = 100pF, RL = 2k (Note 4) 80 160 ns
CIN Capacitance of Logic Input 5 pF
COUT Capacitance of Logic Outputs 5 pF
Note 1: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < GND or VIN > VCC) the absolute value of current at that pin should be limited to 25mA
or less.
Note 2: 0°C to 70°C and –40°C to +85°C operating temperature range devices are 100% tested with temperature limits guaranteed by 100% testing, sampling, or by
correlation with worst-case test conditions.
Note 3: Typicals are parametric norm at 25°C.
Note 4: Parameter guaranteed and 100% production tested.
Note 5: Parameter guaranteed. Parameters not 100% tested are not in outgoing quality level calculation.
Note 6: Total unadjusted error includes offset, full-scale, linearity, multiplexer and sample-and-hold errors.
Note 7: Cannot be tested for ML2282.
Note 8: For VIN– ³ VIN+ the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward conduct for
analog input voltages one diode drop below ground or one diode drop greater than the VCC supply. Be careful, during testing at low VCC levels (4.5V), as high level
analog inputs (5V) can cause this input diode to conduct—especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows
50mV forward bias of either diode. This means that as long as the analog VIN or VREF does not exceed the supply voltage by more than 50mV, the output code will be
correct. To achieve an absolute 0V to 5V input voltage range will therefore require a minimum supply voltage of 4.950VDC over temperature variations, initial
tolerance and loading.
Note 9: Leakage current is measured with the clock not switching.
Note 10: A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits, the
minimum time the clock is high or the minimum time the clock is low must be at least 300ns. The maximum time the clock can be high or low is 60µs.
Note 11: Because of multiplexer addressing, test conditions for the ML2282 would be VIN = 34kHz, 5V sine (fSAMPLING » 102kHz); ML2284 VIN = 32kHz, 5V sine
(fSAMPLING » 95kHz); ML2288 VIN = 30kHz, 5V sine (fSAMPLING » 89kHz).
Note 12: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see Block Diagram) to allow for
comparator response time.
ML2281, ML2282, ML2284, ML2288
7
V
CC
DATA
OUTPUT
C
L
C
L
R
L
DATA
OUTPUT
t
1H
t
0H
t
1H
t
0H
CS
V
CC
GND
V
OH
GND
50%
10%
90%
t
1H
90%
DO AND
SARS OUTPUTS
CS
DO AND
SARS OUTPUTS
GND
V
CC
V
CC
V
OL
10%
t
0H
50%
10%
90%
t
r
t
r
R
L
Figure 1. High Impedance Test Circuits and Waveforms
CLK
CLK
CS
DO
t
SET-UP
t
PD0,
t
PD1
t
SET-UP
t
SET-UP
t
HOLD
t
HOLD
CS
DATA
IN (DI)
CLK
DATA
OUT (DO)
SE
t
SET-UP
START CONVERSION
BIT 7
(MSB) BIT 6
t
PD0,
t
PD1
Figure 2. Timing Diagrams
Data Input Timing Data Output Timing
ML2281 Start Conversion Timing
ML2281, ML2282, ML2284, ML2288
8
CLOCK (CLK)
CHIP SELECT (CS)
DATA OUT (DO)
CLOCK (CLK)
CHIP SELECT (CS)
DATA IN (DI)
DATA OUT (DO)
HI-Z
ADDRESS MUX
OUTPUT DATA
LSB FIRST DATAMSB FIRST DATA
START
BIT
SGL/DIF
ODD/
SIGN
*LSB FIRST OUTPUT NOT AVAILABLE ON ML2281
HI-Z
HI-Z HI-Z
SAMPLE & HOLD
ACQUISITION (t
ACQ
)
SAMPLE & HOLD
ACQUISITION (t
ACQ
)
1
76 543210
*
(MSB)
7654 321 123456
(MSB)
7
(MSB)
0
(LSB)
(LSB)
234567891011
1234567891011121314151617181920
t
C
t
SET-UP
t
SET-UP
DON’T CARE (DI DISABLED UNTIL NEXT CONVERSION CYCLE)
CLOCK (CLK)
CHIP SELECT (CS)
DATA IN (DI)
DATA OUT (DO)
SAR STATUS (SARS)
ADDRESS MUX
OUTPUT DATA
LSB FIRST DATAMSB FIRST DATA
START
BIT
SGL/DIF SELECT
BIT 1
ODD/SIGN
HI-Z HI-Z
HI-Z HI-Z
SAMPLE & HOLD
ACQUISITION (t
ACQ
)
765432 012345
(MSB)
67
(MSB)
1
(LSB)
1234567891011121314151617181920
A/D CONVERSION IN PROCESS
t
SET-UP
DON’T CARE (DI DISABLED UNTIL NEXT CONVERSION CYCLE)
ML2281 Timing
ML2282 Timing
ML2284 Timing
Figure 2. Timing Diagrams (Continued)
ML2281, ML2282, ML2284, ML2288
9
CLOCK (CLK)
CHIP SELECT (CS)
DATA IN (DI)
DO
USING SE
TO CONTROL
LSB FIRST
OUTPUT
SAR STATUS (SARS)
SE = “0”
DATA OUT (DO)
ADDRESS MUX
OUTPUT DATA
LSB FIRST DATAMSB FIRST DATA
START
BIT
SGL/DIF SELECT
BIT 1
ODD/
SIGN SELECT
BIT 0
HI-Z HI-Z
HI-ZHI-Z
HI-ZHI-Z
SAMPLE & HOLD
ACQUISITION (t
ACQ
)
765432 012345
(MSB) 67
(MSB)
1(LSB)
1234567891011121314151617181920212223242526
A/D CONVERSION IN PROCESS
DATA HELD LSB FIRST DATAMSB FIRST DATA
(LSB) (MSB)(MSB)
7654321 0 1234567
t
SET-UP
t
SET-UP
DON’T CARE (DI DISABLED UNTIL NEXT CONVERSION CYCLE)
SE
ML2288 Timing
Figure 2. Timing Diagrams (Continued)
1.0
0.75
0.5
0.25
0
LINEARITY ERROR (LSB)
CLOCK FREQUENCY (MHz)
0 0.01 0.1 1
V
CC
= 5V
V
REF
= 5V
125 C
–55 C
25 C
Figure 3. Linearity Error vs f
CLK
ML2281, ML2282, ML2284, ML2288
10
1
0.75
0.5
0.25
0
LINEARITY ERROR (LSB)
VREF (V
DC
)
0235
41
V
CC
= 5V
f
CLK
= 1.333MHz
125 C
–55 C 25 C
Figure 4. Linearity Error vs V
REF
Voltage
1
0.75
0.5
0.25
0
OFFSET ERROR (LSB)
VREF (V
DC
)
0235
41
V
CC
= 5V
V
IN
= 0V
f
CLK
= 1.333MHz
T
A
= 25 C
Figure 5. Unadjusted Offset Error vs V
REF
Voltage
ML2281, ML2282, ML2284, ML2288
11
*SOME OF THESE FUNCTIONS/PINS ARE NOT AVAILABLE WITH OTHER OPTIONS.
NOTE 1: FOR THE ML2284 DI IS INPUT DIRECTLY TO THE D INPUT OF SELECT 1. SELECT 0 IS FORCED TO A “1”. FOR THE ML2282, DI IS INPUT DIRECTLY TO THE D
INPUT OF ODD/SIGN. SELECT 0 IS FORCED TO A “1” AND SELECT 1 IS FORCED TO A “0”.
Figure 6. ML2288 Functional Block Diagram
C
Q
R
D
R
D
C
Q
D
C
Q
R
D
C
Q
R
+
–
–
+
ANALOG
MUX
(EQUIVALENT)
Σ
1
CH0*
16
CLK
17
DI*
18
CS
CH1*
CH6*
V
REF
V
CC
V+*
DGND*
AGND*
2
CH2 3
CH3 4
CH4* 5
CH5* 6
7
CH7* 8
COM* 9
12
20
TO INTERNAL
CIRCUITRY
7V SHUNT
REGULATOR
INPUT PROTECTION—ALL LOGIC INPUTS
C
C
R
LADDER
AND
DECODER
SAR
LOGIC
AND
LATCH
9-BIT
SHIFT
REGISTER
COMP B7
B6
B5
B4
14
DO
B2
B3
B1
B0
CS
CS
CS
COMP
PARALLEL XFR
TO SHIFT REGISTER
MSB FIRST
LSB FIRST
EOC
EOC
R
RC
CS
DEOC
CS
SE*
CS
CS
CS
T
D
V
CC
V
CC
TO
INTERNAL
CIRCUITS
INPUT
13
16
17
18
MUX
ADDRESS NOTE 1
13
SARS*
15
NOTE 1
SELECT 0SELECT 1START
RRRR R
D
C
SGL/DIF
5-BIT SHIFT-REGISTER
ODD/
SIGN
TIME
DELAY
DSTART 2
START
DSTART 1
ML2281, ML2282, ML2284, ML2288
12
FUNCTIONAL DESCRIPTION
MULTIPLEXER ADDRESSING
The design of these converters utilizes a sample data
comparator structure which provides for a differential
analog input to be converted by a successive
approximation routine.
The actual voltage converted is always the difference
between an assigned “+” input terminal and a “–” input
terminal. The polarity of each input terminal of the pair
being converted indicates which line the converter expects
to be the most positive. If the assigned “+” input is less than
the “–” input, the converter responds with an all zeros
output code.
A unique input multiplexing scheme has been utilized
to provide multiple analog channels with software
configurable single ended, differential, or pseudo
differential options. The pseudo differential option will
convert the difference between the voltage at any analog
input and a common terminal. One converter package
can now accommodate ground referenced inputs and
true differential inputs as well as signals with some
arbitrary reference voltage.
A particular input configuration is assigned during the MUX
addressing sequence, prior to the start of a conversion. The
MUX address selects which of the analog inputs are to be
enabled and whether this input is single ended or
differential. In the differential case, it also assigns the
polarity of the analog channels. Differential inputs are
restricted to adjacent channel pairs. For example, channel 0
and channel 1 may be selected as a different pair but
channel 0 or channel 1 cannot act differentially with any
other channel. In addition to selecting the differential mode,
the sign may also be selected. Channel 0 may be selected as
the positive input and channel 1 as the negative input or
vice versa. This programmability is illustrated by the MUX
addressing codes shown in Tables 1, 2, and 3.
The MUX address is shifted into the converter via the DI
input. Since the ML2281 contains only one differential
input channel with a fixed polarity assignment, it does
not require addressing.
The common input line on the ML2288 can be used as a
pseudo differential input. In this mode, the voltage on the
COM pin is treated as the “–” input for any of the other
input channels. This voltage does not have to be analog
ground; it can be any reference potential which is common
to all of the inputs. This feature is most useful in single
supply applications where the analog circuitry may be
biased at a potential other than ground and the output
signals are all referred to this potential.
Since the input configuration is under software control, it
can be modified, as required, at each conversion. A channel
can be treated as a single-ended, ground referenced input
for one conversion; then it can be reconfigured as part of a
differential channel for another conversion. Figure 7
illustrates these different input modes.
MUX ADDRESS ANALOG SINGLE-ENDED CHANNEL#
SGL/ ODD/ SELECT
DIF SIGN 1 001234567COM
1000+ –
1001 + –
1010 + –
1011 + –
1100+ –
1101 + –
1110 + –
1111 +–
SINGLE-ENDED MUX MODE
MUX ADDRESS ANALOG DIFFERENTIAL
CHANNEL-PAIR#
SGL/ ODD/ SELECT 0123
DIF SIGN 1 0 0 1234567
0000+–
0001 +–
0010 +–
0011 +–
0100–+
0101 –+
0110 –+
0111 –+
DIFFERENTIAL MUX MODE
Table 1. ML2288 MUX Addressing 8 Single-Ended
or 4 Differential Channels
MUX ADDRESS CHANNEL#
SGL/ ODD/ SELECT
DIF SIGN 1 0123
10 0 +
10 1 +
11 0 +
11 1 +
SINGLE-ENDED MUX MODE
MUX ADDRESS CHANNEL#
SGL/ ODD/ SELECT
DIF SIGN 1 0123
00 0 + –
00 1 + –
01 0 – +
01 1 – +
DIFFERENTIAL MUX MODE
COM is internally tied to AGND
Table 2. ML2284 MUX Addressing 4 Single-Ended
or 2 Differential Channel
ML2281, ML2282, ML2284, ML2288
13
DIGITAL INTERFACE
The block diagram and timing diagrams in Figures 2-5
illustrate how a conversion sequence is performed.
A conversion is initiated when CS is pulsed low. This line
must me held low for the entire conversion. The converter is
now waiting for a start bit and its MUX assignment word.
A clock is applied to the CLK input. On each rising edge
of the clock, the data on DI is clocked into the MUX
address shift register. The start bit is the first logic “1” that
appears on the DI input (all leading edge zeros are
ignored). After the start bit, the device clocks in the next 2
to 4 bits for the MUX assignment word.
When the start bit has been shifted into the start location
of the MUX register, the input channel has been assigned
and a conversion is about to begin. An interval of 1/2
clock period is used for sample & hold settling through the
selected MUX channels. The SAR status output goes high
at this time to signal that a conversion is now in progress
and the DI input is ignored.
The DO output comes out of High impedance and
provides a leading zero for this one clock period.
When the conversion begins, the output of the
comparator, which indicates whether the analog input is
greater than or less than each successive voltage from the
internal DAC, appears at the DO output on each falling
edge of the clock. This data is the result of the conversion
being shifted out (with MSB coming first) and can be read
by external logic or µP immediately.
After 8 clock periods, the conversion is completed. The SAR
status line returns low to indicate this 1/2 clock cycle later.
The serial data is always shifted out MSB first during the
conversion. After the conversion has been completed, the
data can be shifted out a second time with LSB first,
depending on level of SE input. For the case of ML2288, if
SE = 1, the data is shifted out MSB first during the
conversion only. If SE is brought low before the end of
conversion (which is signalled by the high to low transition
of SARS), the data is shifted out again immediately after the
end of conversion; this time LSB first. If SE is brought low
after end of conversion, the LSB first data is shifted out on
falling edges of clock after SE goes low. For ML2282 and
2284, SE is internally tied low, so data is shifted out MSB
first, then shifted out a second time LSB first at end of
conversion. For ML2281, SE is internally tied high, so data is
shifted out only once MSB first.
All internal registers are cleared when the CS input is
high. If another conversion is desired, CS must make a
high to low transition followed by address information.
The DI input and DO output can be tied together and
controlled through a bidirectional µP I/O bit with one
connection. This is possible because the DI input is only
latched in during the MUX addressing interval while the
DO output is still in the high impedance state.
MUX ADDRESS CHANNEL#
SGL/DIF ODD/SIGN 0 1
10 +
11 +
SINGLE-ENDED MUX MODE
Table 3. ML2282 MUX Addressing 2 Single-Ended
or 1 Differential Channel
MUX ADDRESS CHANNEL#
SGL/DIF ODD/SIGN 0 1
00 + –
01 – +
DIFFERENTIAL MUX MODE
0
1
2
3
4
5
6
7
+
+
+
+
+
+
+
+
COM (–)
8 Single-Ended
0
1
2
3
4
5
6
7
+
+
+
+
+
+
+
+
COM (–)
8 Pseudo-Differential
+
V
BIAS
0, 1
2, 3
4, 5
6, 7
+ (–)
– (+)
+ (–)
– (+)
+ (–)
– (+)
+ (–)
– (+)
4 Differential
0, 1
2, 3
+
–
–
+
+
+
+
+
COM (–)
Mixed Mode
+
V
BIAS
4
5
6
7
Figure 7. Analog Input Multiplexer Functional
Options for ML2288
ML2281, ML2282, ML2284, ML2288
14
REFERENCE
The voltage applied to the reference input to these
converters defines the voltage span of the analog input
(the difference between VIN MAX and VIN MIN) over which
the 256 possible output codes apply. The devices can be
used in either ratiometric applications or in systems
requiring absolute accuracy. The reference pin must be
connected
to a voltage source capable of driving the reference input
resistance, typically 10k. This pin is the top of a resistor
divider string used for the successive approximation
conversion.
In a ratiometric system, the analog input voltage is
proportional to the voltage used for the A/D reference.
This voltage is typically the system power supply, so the
VREF pin can be tied to VCC. This technique relaxes the
stability requirements of the system reference as the analog
input and A/D reference move together maintaining the
same output code for a given input condition.
For absolute accuracy, where the analog input varies
between specific voltage limits, the reference pin can be
biased with a time and temperature stable voltage source.
The maximum value of the reference is limited to the VCC
supply voltage. The minimum value, however, can be quire
small to allow direct conversion of inputs with less than 5V
of voltage span. Particular care must be taken with regard to
noise pickup, circuit layout and system error voltage sources
when operating with a reduced span due to the increased
sensitivity of the converter.
ANALOG INPUTS AND SAMPLE/HOLD
An important feature of the ML2281 family of devices is that
they can be located at the source of the analog signal and
then communicate with a controlling µP with just a few
wires. This avoids bussing the analog inputs long distances
and thus reduces noise pickup on these analog lines.
However, in some cases, the analog inputs have a large
common mode voltage or even some noise present along
with the valid analog signal.
The differential input of these converters reduces the effects
of common mode input noise. Thus, if a common mode
voltage is present on both “+” and “–” inputs, such as 60Hz,
the converter will reject this common mode voltage since it
only converts the difference between “+” and “–” inputs.
The ML2281 family have a true sample and hold circuit
which samples both “+” and “–” inputs simultaneously. This
simultaneous sampling with a true S/H will give common
mode rejection and AC linearity performance that is superior
to devices where the two input terminals are not sampled at
the same instant and where true sample and hold capability
does not exist. Thus, the ML2281 family of devices can
reject AC common mode signals from DC-50kHz as well as
maintain linearity for signals from DC-50kHz.
The signal at the analog input is sampled during the interval
when the sampling switch is closed prior to conversion
start. The sampling window (S/H acquisition time) is 1/2
CLK period wide and occurs 1/2 CLK period before DO
goes from high impedance to active low state. When the
sampling switch closes at the start of the S/H acquisition
time, 8pF of capacitance is thrown onto the analog input.
1/2 CLK period later, the sampling switch is opened and the
signal present at the analog input is stored. Any error on the
analog input at the end of the S/H acquisition time will
cause additional conversion error. Care should be taken to
allow adequate charging or settling time from the source.
If more charging or settling time is needed to reduce these
analog input errors, a longer CLK period can be used.
The ML2281X family has improved latchup immunity.
Each analog input has dual diodes to the supply rails, and
a minimum of ±25mA (±100mA typically) can be injected
into each analog input without causing latchup.
DYNAMIC PERFORMANCE
Signal-to-Noise-Ratio
Signal-to-noise ration (SNR) is the measured signal-to-noise
at the output of the converter. The signal is the RMS
magnitude of the fundamental. Noise is the RMS sum of all
the nonfundamental signals up to half the sampling
frequency. SNR is dependent on the number of quantization
levels used in the digitization process; the more levels, the
smaller the quantization noise. The theoretical SNR for a
sine wave is given by
SNR = (6.02N + 1.76)dB
where N is the number of bits. Thus for ideal 8-bit converter,
SNR = 49.92dB.
Harmonic Distortion
Harmonic distortion is the ratio of the RMS sum of
harmonics to the fundamental. Total harmonic distortion
(THD) of the ML2281 Series is defined as
THD
VVVV
V
=+++
20
22324252
1
log
where V1 is the RMS amplitude of the fundamental and V2,
V3, V4, V5 are the RMS amplitudes of the individual
harmonics.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fA
and fB, any active device with nonlinearities will create
distortion products, of order (m + n), at sum and difference
frequencies of mfA + nfB, where m, n = 0, 1, 2, 3… .
Intermodulation terms are those for which m or n is not
equal to zero. The (IMD) intermodulation distortion
specification includes the second order terms (fA + fB) and
(fA – fB) and the third order terms (2fA + fB), (2fA – fB),
(fA + 2fB) and (fA – 2fB) only.
ML2281, ML2282, ML2284, ML2288
15
ZERO ERROR ADJUSTMENT
The zero of the A/D does not require adjustment. If the
minimum analog input voltage value, VIN MIN is not ground,
a zero offset can be done. The converter can be made to
output 00000000 digital code for this minimum input
voltage by biasing any VIN– input at this VIN MIN value.
This utilizes the differential mode operation of the A/D.
The zero error of the A/D converter relates to the location
of the first riser of the transfer function and can be
measured by grounding the VIN– input and applying a
small magnitude positive voltage to the VIN+ input. Zero
error is the difference between the actual DC input
voltage which is necessary to just cause an output digital
code transition from 00000000 to 00000001 and the ideal
1/2 LSB value (1/2 LSB = 9.8mV for VREF = 5.000VDC).
FULL-SCALE ADJUSTMENT
The full-scale adjustment can be made by applying a
differential input voltage which is 1-1/2 LSB down from
the desired analog full-scale voltage range and then
adjusting the magnitude of the VREF input or VCC for a
digital output code which is just changing from 11111110
to 11111111.
ADJUSTMENT FOR AN ARBITRARY ANALOG
INPUT VOLTAGE RANGE
If the analog zero voltage of the A/D is shifted away from
ground (for example, to accommodate an analog input
signal which does not go to ground), this new zero
reference should be properly adjusted first. A VIN+ voltage
which equals this desired zero reference plus 1/2 LSB
CURRENT LIMITING
RESISTOR, I+ ≤15mA
12V V
CC
V+
GND
I + →28.8k
3.2k
3.2k
Figure 8. Shunt Regulator
I+
15mA
V+
5.5V
SLOPE =
6.9V
1
35k
Figure 9. I-V Characteristic of the Shunt Regulator
(where the LSB is calculated for the desired analog span,
1 LSB = analog span/256) is applied to selected “+” input
and the zero reference voltage at the corresponding “–”
input should then be adjusted to just obtain the 00000000
to 00000001 code transition.
The full-scale adjustment should be made by forcing a
voltage to the VIN+ input which is given be:
V fs adjust V VV
IN MAX MAX MIN
+=−×
−
15 256
.()
where VMAX = high end of the analog input range
VMIN = low end (offset zero) of the analog range
The VREF or VCC voltage is then adjusted to provide a
code change from 11111110 to 11111111.
SHUNT REGULATOR
A unique feature of ML2288 and ML2284 is the inclusion
of a shunt regulator connected from V+ terminal to
ground which also connects to the VCC terminal (which is
the actual converter supply) through a silicon diode as
shown in Figure 8. When the regulator is turned on, the
V+ voltage is clamped at 11VBE set by the internal resistor
ratio. The typical I-V of the shunt regulator is shown in
Figure 9. It should be noted that before V+ voltage is high
enough to turn on the shunt regulator (which occurs at
about 5.5V), 35kW resistance is observed between V+ and
GND. When the shunt regulator is not used, V+ pin
should be either left floating or tied to GND. The
temperature coefficient of the regulator is –22mV/°C.
ML2281, ML2282, ML2284, ML2288
16
APPLICATIONS
8051 Interface and Controlling Software
MNEMONIC INSTRUCTION
START ANL P1, #0F7H ;SELECT A/D (CS = 0)
MOV B, #5 ;BIT COUNTER ¬ 5
MOV A, #ADDR ;A ¬ MUX BIT
LOOP 1: RRC A ;CY ¬ ADDRESS BIT
JC ONE ;TEST BIT
;BIT = 0
ZERO: ANL P1, #0FEH ;DI ¬ 0
SJMP CONT ;CONTINUE
;BIT = 1
ONE: ORL P1, #1 ;D1 ¬ 1
CONT: ACALL PULSE ;PULSE SK 0 ® 1 ® 0
DJNZ B, LOOP 1 ;CONTINUE UNTIL DONE
ACALL PULSE ;EXTRA CLOCK FOR SYNC
MOV B, #8 ;BIT COUNTER ¬ 8
LOOP 2: ACALL PULSE ;PULSE SK 0 ® 1 ® 0
MOV A, P1 ;CY ¬ DO
RRC A
RRC A
MOV A, C ;A ¬ RESULT
RLC A ;A(0) BIT ¬ AND SHIFT
MOV C, A ;C ¬ RESULT
DJNZ B, LOOP 2 ;CONTINUE UNTIL DONE
RETI
;PULSE SUBROUTINE
PULSE: ORL P1, #04 ;SK ¬ 1
NOP ;DELAY
ANL P1, #0FBH ;SK ¬ 0
RET
CH0
ML2288 8051
P1
3
P1
2
P1
1
P1
0
CS
CLK
DI
DOCH7
ML2281, ML2282, ML2284, ML2288
17
APPLICATIONS
(Continued)
10kΩ
CLK
CLK
CLK
CLK
QD
CLOCK
GENERATOR
CLK
CLR
CLK
CLK
CLK INT
CLK
CS
SARS
GND SI A
SI B
CLK
Q
H
V
CC
V
CC
V
CC
SIN
SHIFT/
LOAD
V
REF
Q
A
10kΩ
5 V
DC
START
START
+
CLOSE TO
START THE
A/D CONVERSION
0.01µF
0.001µF
OUTPUT SHIFT REGISTER
74HC164
ANALOG INPUTS
PARALLEL INPUTS
MUX ADDRESS
GND
INPUT SHIFT REGISTER
74HC165
ML2288
114
1
14
2019101112
13
17
D1
COM
912345678
18
16
15
NC
0123
1kΩ (8) 1/8 V
CC
4567
DO
DO
DO
V+DGNDAGND
SE
+10µF
51kΩ
2
345610111213
7
8
1.3kΩ (8)
1/2 74HC74
MSB DATA DISPLAY LSB 5V
DC
5V
DC
5V
DC
5V
DC
5V
DC
(OR V
IN
)
14
NC
10
7
76543141312
51kΩ (4)
11
15
2
19
NC
SGL/DIF
START BIT
ML2288 “Stand-Alone” or Evaluation Circuit
ML2281, ML2282, ML2284, ML2288
18
3kΩ
+
10µF
ML2281
LM335
TA
VIN (–)
VIN (+) VCC
VCC
(5 VDC)
VREF
10kΩ
TA MIN
ADJ.
10kΩ
TA MAX
ADJ.
Low-Cost Remote Temperature Sensor
ML2281, ML2282, ML2284, ML2288
19
APPLICATIONS
(Continued)
10kΩ
FS
ADJ.
1kΩ
GAIN
10kΩ
OFFSET
DUAL
DUAL
5.1V
2.7kΩ
10kΩ
10V
10V
6.8kΩ
330Ω
VCC
(5VDC)
1kΩ
2VDC
ZERO ADJ.
+
+
10µF
1.2kΩ
2.7kΩ
330Ω
1kΩ
3V
VIN (+)
VIN
VCC
VCC
VREF
–IN
+IN DO
CLK
CS
ML2281
VREF
ML2281
+
1µF
SET
VOLTAGE SPAN
1MΩ
VIN (–)
SETS ZERO
CODE VOLTAGE
+
–
+
–
1MΩ
20kΩ
20kΩ
STRAIN GAUGE
LOAD CELL
300Ω/30mV FS
CH0
CH7 SERIAL I/O
COM
LM335
LM385
TL064
TL064 TL064
VREF
tREF
tREF
VCC
VCC
VCC
ML2288
+
–
+
–
+
–
+
–
+
–
910Ω
820Ω
1kΩ
1kΩ
TYPE J
TYPE J
T1
+
–
+
–
T8
1kΩ
22kΩ
88.2kΩ
88.2k
•
•
•
•
USES ONE MORE WIRE THAN LOAD CELL ITSELF
TWO MINI-DIPs COULD BE MOUNTED INSIDE LOAD CELL
FOR DIGITAL OUTPUT TRANSDUCER
ELECTRONIC OFFSET AND GAIN TRIMS RELAX MECHANICAL
SPECS FOR GAUGE FACTOR AND OFFSET
LOW LEVEL CELL OUTPUT IS CONVERTED IMMEDIATELY FOR
HIGH NOISE IMMUNITY
tREF
USES THE PSEUDO-DIFFERENTIAL MODE TO KEEP THE
DIFFERENTIAL INPUTS CONSTANT WITH CHANGES IN REFERENCE TEMPERATURE (TREF)
2kΩ
3kΩ20kΩ
1kΩ
Zero-Shift and Span Adjust: 2V - V
IN
- 5V Digital Load Cell
Convert 8 Thermocouples with only One Cold-Junction Compensator
ML2281, ML2282, ML2284, ML2288
20
APPLICATIONS
(Continued)
Obtaining 9-Bit Resolution
VCC
VIN VIN (+)
VIN (–)
VCC
VCC
(5VDC)
–15VDC
15VDC
VREF
+
–
+
–
+
–
ML2281
+
–
–
≤ 2.5V> 2.5V
+
R
R
(
(
ML2281
+
+
10µF
OP
AMP 600Ω
1µF
VIN (–)
VIN (+)
VCC
VREF
VCC
(5VDC)
VCC
(5VDC)
ML2281
LOAD
LM336
9.1kΩ
240kΩ
120kΩ
100Ω
0.1Ω(2A FULL-SCALE)
ILOAD
2kΩ
1kΩ
FS
ADJ.
10kΩ
FS
ADJ.
100Ω
ZERO
ADJ.
+10µF
→
+
–
VIN (+)
*VIN (–) = 0.15VCC
15% OF VCC ≤VXDR ≤85% OF VCC
VCC
VREF
VCC
(5VDC)
ML2281
0.7 VCC 1kΩ
FS
ADJ.
1kΩ
ZERO
ADJ.
24kΩ
+10µF
+
1µF
VCC
(5VDC)
+
+
10µF
10kΩ
2kΩ
20kΩ
3kΩ
VIN (–)*
XDR
VXDR
+
–
VIN (+)
VIN
VCC
VREF
ML2281
+
1µFSET FOR 3V
VIN (–)
CONTROLLER PERFORMS A ROUTINE TO DETERMINE WHICH
INPUT POLARITY PROVIDES A NON-ZERO OUTPUT CODE.
THIS INFORMATION PROVIDES THE EXTRA BITS.
DIODE CLAMPING IS NOT NEEDED
IF CURRENT IS LIMITED TO 25mA
3kΩ
1kΩ
Protecting the Input
Operating with Ratiometric Transducers Span Adjust: 0V - V
IN
- 3V
Digitizing a Current Flow
ML2281, ML2282, ML2284, ML2288
21
APPLICATIONS
(Continued)
4mA–20mA Current Loop Converter
V
CC
ML2281
GND
+IN
–IN
V
REF
DO
CS
CLK
GND
V
O
V
CC
V+
1000pF
100kΩ= 50kHZ
INP
CD4024
50pF
100kΩ
10kΩ
23
5
68
6N139
OPTO COUPLER
V
CC
V
O
5
200kΩ
6.2kΩ
3.9kΩ
300kΩ
47kΩ
10kΩ
5kΩ
24kΩ
47µF
10µF100Ω
+
LM385–2.5V
LM385–2.5V
4mA–20mA 1N4148 1/6 74HC14
→ →
• ALL POWER SUPPLIED BY LOOP
• 1500V ISOLATION AT OUTPUT
TRANSFORMER
TRW-TC-SSD-32 1N4148
1N4148
470Ω
6V
6V 1
5
3
7
2
6
6V
10kΩ
DI
470Ω
100µF
+
CLK
V
CC
V
CC
V
CC
V
CC
ML2288
100kΩ
2N2222
2N2222 2
3
8
6
5
2N2222
D1
DO
CS
V
CC
OUT
10kΩ
CS
10kΩ
CLK
6.8kΩ
8 ANALOG
CHANNELS
47kΩ
4N28
4N28
• NO POWER REQUIRED REMOTELY
• 1500V ISOLATION
6N139 HIGH GAIN
OPTOCOUPLER
100kΩ
Isolated Data Converter
ML2281, ML2282, ML2284, ML2288
22
APPLICATIONS
(Continued)
DQ
Q
DQ
Q
DQ
Q
S
R
Q
DSP
LS193
COUNT
DOWN
ML2281 FSR
START
CLK
V
IN
+
V
IN
–
LOAD
A
5V
BCD
B0
CLK
DRDO
CS
CLK
TMS320
SERIES
CLK 1
D7 D6 D5 D4 D3 D2 D1 D0
234567891011121314
START
CS
FSR
DO HI-Z HI-Z
Interfacing ML2281 to TMS320 Series
Sampling Rate 111kHz, Data Rate 1.33MHz
ML2281, ML2282, ML2284, ML2288
23
PHYSICAL DIMMENSIONS
inches (millimeters)
SEATING PLANE
0.240 - 0.260
(6.09 - 6.60)
PIN 1 ID 0.299 - 0.335
(7.59 - 8.50)
0.365 - 0.385
(9.27 - 9.77)
0.016 - 0.020
(0.40 - 0.51)
0.100 BSC
(2.54 BSC)
0.008 - 0.012
(0.20 - 0.31)
0.015 MIN
(0.38 MIN)
8
0º - 15º
1
0.055 - 0.065
(1.39 - 1.65)
0.170 MAX
(4.32 MAX)
0.125 MIN
(3.18 MIN)
0.020 MIN
(0.51 MIN)
(4 PLACES)
Package: P08
8-Pin PDIP
SEATING PLANE
0.148 - 0.158
(3.76 - 4.01)
PIN 1 ID 0.228 - 0.244
(5.79 - 6.20)
0.189 - 0.199
(4.80 - 5.06)
0.012 - 0.020
(0.30 - 0.51)
0.050 BSC
(1.27 BSC)
0.015 - 0.035
(0.38 - 0.89)
0.059 - 0.069
(1.49 - 1.75)
0.004 - 0.010
(0.10 - 0.26)
0.055 - 0.061
(1.40 - 1.55)
8
0.006 - 0.010
(0.15 - 0.26)
0º - 8º
1
0.017 - 0.027
(0.43 - 0.69)
(4 PLACES)
Package: S08
8-Pin SOIC
ML2281, ML2282, ML2284, ML2288
24
SEATING PLANE
0.148 - 0.158
(3.76 - 4.01)
PIN 1 ID 0.228 - 0.244
(5.79 - 6.20)
0.337 - 0.347
(8.56 - 8.81)
0.012 - 0.020
(0.30 - 0.51)
0.050 BSC
(1.27 BSC)
0.015 - 0.035
(0.38 - 0.89)
0.059 - 0.069
(1.49 - 1.75)
0.004 - 0.010
(0.10 - 0.26)
0.055 - 0.061
(1.40 - 1.55)
14
0.006 - 0.010
(0.15 - 0.26)
0º - 8º
1
0.017 - 0.027
(0.43 - 0.69)
(4 PLACES)
Package: S14
14-Pin SOIC
PHYSICAL DIMMENSIONS
inches (millimeters)
SEATING PLANE
0.240 - 0.260
(6.09 - 6.61)
PIN 1 ID 0.295 - 0.325
(7.49 - 8.25)
0.740 - 0.760
(18.79 - 19.31)
0.016 - 0.022
(0.40 - 0.56)
0.100 BSC
(2.54 BSC)
0.008 - 0.012
(0.20 - 0.31)
0.015 MIN
(0.38 MIN)
14
0º - 15º
1
0.050 - 0.065
(1.27 - 1.65)
0.170 MAX
(4.32 MAX)
0.125 MIN
(3.18 MIN)
0.070 MIN
(1.77 MIN)
(4 PLACES)
Package: P14
14-Pin PDIP
ML2281, ML2282, ML2284, ML2288
25
PHYSICAL DIMMENSIONS
inches (millimeters)
SEATING PLANE
0.240 - 0.260
(6.09 - 6.61)
PIN 1 ID 0.295 - 0.325
(7.49 - 8.26)
1.010 - 1.035
(25.65 - 26.29)
0.016 - 0.022
(0.40 - 0.56)
0.100 BSC
(2.54 BSC)
0.008 - 0.012
(0.20 - 0.31)
0.015 MIN
(0.38 MIN)
20
0º - 15º
1
0.055 - 0.065
(1.40 - 1.65)
0.170 MAX
(4.32 MAX)
0.125 MIN
(3.18 MIN)
0.060 MIN
(1.52 MIN)
(4 PLACES)
Package: P20
20-Pin PDIP
0.100 - 0.110
(2.54 - 2.79)
PIN 1 ID
SEATING PLANE
0.385 - 0.395
(9.78 - 10.03)
0.350 - 0.356
(8.89 - 9.04)
0.013 - 0.021
(0.33 - 0.53)
0.165 - 0.180
(4.19 - 4.57)
1
0.350 - 0.356
(8.89 - 9.04)
0.385 - 0.395
(9.78 - 10.03)
6
11
16 0.290 - 0.330
(7.36 - 8.38)
0.025 - 0.045
(0.63 - 1.14)
(RADIUS)
0.009 - 0.011
(0.23 - 0.28)
0.026 - 0.032
(0.66 - 0.81)
0.042 - 0.048
(1.07 - 1.22)
0.042 - 0.056
(1.07 - 1.42)
0.200 BSC
(5.08 BSC)
Package: Q20
20-Pin PLCC
0.146 - 0.156
(3.71 - 3.96)
0.050 BSC
(1.27 BSC)
ML2281, ML2282, ML2284, ML2288
26
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design.
Micro Linear does not assume any liability arising out of the application or use of any product described herein,
neither does it convey any license under its patent right nor the rights of others. The circuits contained in this
data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to
whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility
or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel
before deciding on a particular application.
5/5/97 Printed in U.S.A.
ORDERING INFORMATION
ALTERNATE TOTAL TEMPERATURE
PART NUMBER PART NUMBER UNADJUSTED ERROR RANGE PACKAGE
SINGLE ANALOG INPUT, 8-PIN PACKAGE
ML2281BIP (Obsolete) ADC0831CCN ±1/2 LSB –40°C to 85°C Plastic DIP (P08)
ML2281BCP ADC0831BCN 0°C to 70°C Molded DIP (P08)
ML2281BCS (Obsolete — 0°C to 70°C Plastic SOIC (S08)
ML2281CIP (End of Life) ADC0831BCN ±1 LSB –40°C to 85°C Plastic DIP (P08)
ML2281CCP (End of Life) ADC0831CCN 0°C to 70°C Molded DIP (P08)
ML2281CCS (End of Life) — 0°C to 70°C Plastic SOIC (S08)
TWO ANALOG INPUTS, 8-PIN PACKAGE
ML2282BIP (Obsolete) ADC0832CCN ±1/2 LSB –40°C to 85°C Plastic DIP (P08)
ML2282BCP (Obsolete) ADC0832BCN 0°C to 70°C Molded DIP (P08)
ML2282BCS (Obsolete) — 0°C to 70°C Plastic SOIC (S08)
ML2282CIP (Obsolete) ADC0832BCN ±1 LSB –40°C to 85°C Plastic DIP (P08)
ML2282CCP (Obsolete) ADC0832CCN 0°C to 70°C Molded DIP (P08)
ML2282CCS (Obsolete) — 0°C to 70°C Plastic SOIC (S08)
FOUR ANALOG INPUTS, 14-PIN PACKAGE
ML2284BIP (Obsolete) ADC0834CCN ±1/2 LSB –40°C to 85°C Plastic DIP (P14)
ML2284BCP (Obsolete) ADC0834BCN 0°C to 70°C Molded DIP (P14)
ML2284BCS (Obsolete) — 0°C to 70°C Plastic SOIC (S14)
ML2284CIP (Obsolete) ADC0834BCN ±1 LSB –40°C to 85°C Plastic DIP (P14)
ML2284CCP (End of Life) ADC0834CCN 0°C to 70°C Molded DIP (P14)
ML2284CCS (Obsolete) — 0°C to 70°C Plastic SOIC (S14)
EIGHT ANALOG INPUTS, 20-PIN PACKAGE
ML2288BIP (Obsolete) ADC0838CCN ±1/2 LSB –40°C to 85°C Plastic DIP (P20)
ML2288BCP (Obsolete) ADC0838BCN 0°C to 70°C Molded DIP (P20)
ML2288BCQ (Obsolete) ADC0838BCV 0°C to 70°C Molded PCC (Q20)
ML2288CIP (Obsolete) ADC0838CCN ±1 LSB –40°C to 85°C Plastic DIP (P20)
ML2288CCP (Obsolete) ADC0838CCN 0°C to 70°C Molded DIP (P20)
ML2288CCQ (End of Life) ADC0838CCV 0°C to 70°C Molded PCC (Q20)
2092 Concourse Drive
San Jose, CA 95131
Tel: 408/433-5200
Fax: 408/432-0295
© Micro Linear 1997 is a registered trademark of Micro Linear Corporation
Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940;
5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending.
DS2281_82_84_88-01
