19-1001; Rev 0; 8/04 12-Bit, 80Msps, 3.3V IF-Sampling ADC Applications Features Direct IF Sampling Up to 400MHz Excellent Dynamic Performance 68.0dB/66.5dB SNR at fIN = 70MHz/175MHz 85.1dBc/85.5dBc SFDR at fIN = 70MHz/175MHz 3.3V Low-Power Operation 366mW (Single-Ended Clock Mode) 393mW (Differential Clock Mode) 3W (Power-Down Mode) Differential or Single-Ended Clock Fully Differential or Single-Ended Analog Input Adjustable Full-Scale Analog Input Range: 0.35V to 1.15V Common-Mode Reference CMOS-Compatible Outputs in Two's Complement or Gray Code Data-Valid Indicator Simplifies Digital Design Data Out-of-Range Indicator Miniature, 40-Pin Thin QFN Package with Exposed Paddle Evaluation Kit Available (Order MAX1211EVKIT) Ordering Information PART MAX1209ETL TEMP RANGE PIN-PACKAGE PKG CODE -40C to +85C 40 Thin QFN (6mm x 6mm x 0.8mm) T4066-3 Pin-Compatible Versions PART SAMPLING RATE (Msps) RESOLUTION (BITS) TARGET APPLICATION MAX12553 65 14 IF/Baseband IF MAX1209 80 12 IF Communication Receivers Cellular, Point-to-Point Microwave, HFC, WLAN Ultrasound and Medical Imaging MAX1211 65 12 IF MAX1208 80 12 Baseband MAX1207 65 12 Baseband Portable Instrumentation Low-Power Data Acquisition MAX1206 40 12 Baseband Pin Configuration appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX1209 General Description The MAX1209 is a 3.3V, 12-bit, 80Msps analog-to-digital converter (ADC) featuring a fully differential wideband track-and-hold (T/H) input amplifier, driving a low-noise internal quantizer. The analog input stage accepts single-ended or differential signals. The MAX1209 is optimized for low power, small size, and high dynamic performance. Excellent dynamic performance is maintained from baseband to input frequencies of 175MHz and beyond, making the MAX1209 ideal for intermediatefrequency (IF) sampling applications. Powered from a single 3.0V to 3.6V supply, the MAX1209 consumes only 366mW while delivering a typical signal-to-noise (SNR) performance of 66.5dB at an input frequency of 175MHz. In addition to low operating power, the MAX1209 features a 3W power-down mode to conserve power during idle periods. A flexible reference structure allows the MAX1209 to use the internal 2.048V bandgap reference or accept an externally applied reference. The reference structure allows the full-scale analog input range to be adjusted from 0.35V to 1.15V. The MAX1209 provides a common-mode reference to simplify design and reduce external component count in differential analog input circuits. The MAX1209 supports both a single-ended and differential input clock drive. Wide variations in the clock duty cycle are compensated with the ADC's internal duty-cycle equalizer (DCE). ADC conversion results are available through a 12-bit, parallel, CMOS-compatible output bus. The digital output format is pin selectable to be either two's complement or Gray code. A data-valid indicator eliminates external components that are normally required for reliable digital interfacing. A separate digital power input accepts a wide 1.7V to 3.6V supply, allowing the MAX1209 to interface with various logic levels. The MAX1209 is available in a 6mm x 6mm x 0.8mm, 40-pin thin QFN package with exposed paddle (EP), and is specified for the extended industrial (-40C to +85C) temperature range. See the Pin-Compatible Versions table for a complete family of 14-bit and 12-bit high-speed ADCs. MAX1209 12-Bit, 80Msps, 3.3V IF-Sampling ADC ABSOLUTE MAXIMUM RATINGS VDD to GND ...........................................................-0.3V to +3.6V OVDD to GND........-0.3V to the lower of (VDD + 0.3V) and +3.6V INP, INN to GND ...-0.3V to the lower of (VDD + 0.3V) and +3.6V REFIN, REFOUT, REFP, REFN, COM to GND................-0.3V to the lower of (VDD + 0.3V) and +3.6V CLKP, CLKN, CLKTYP, G/T, DCE, PD to GND ........-0.3V to the lower of (VDD + 0.3V) and +3.6V D11 Through D0, I.C. DAV, DOR to GND ...-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70C) 40-Pin Thin QFN 6mm x 6mm x 0.8mm (derated 26.3mW/C above +70C)........................2105.3mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering 10s) ..................................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 80MHz (50% duty cycle), TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY (Note 2) Resolution 12 Integral Nonlinearity INL fIN = 3MHz Differential Nonlinearity DNL fIN = 3MHz, no missing codes over temperature -0.77 Bits 0.6 LSB 0.35 LSB Offset Error VREFIN = 2.048V 0.17 0.91 %FS Gain Error VREFIN = 2.048V 0.56 5.3 %FS ANALOG INPUT (INP, INN) Differential Input Voltage Range VDIFF Differential or single-ended inputs Common-Mode Input Voltage Input Capacitance (Figure 3) CPAR CSAMPLE Fixed capacitance to ground 1.024 V VDD / 2 V 2 Switched capacitance pF 1.9 CONVERSION RATE Maximum Clock Frequency fCLK 80 MHz Minimum Clock Frequency 5 Data Latency MHz 8.5 Clock cycles Input at less than -35dBFS -68.8 dBFS fIN = 70MHz at -0.5dBFS 68.0 fIN = 100MHz at -0.5dBFS 67.7 Figure 6 DYNAMIC CHARACTERISTICS (differential inputs, Note 2) Small-Signal Noise Floor Signal-to-Noise Ratio SSNF SNR fIN = 175MHz at -0.5dBFS (Note 6) Signal-to-Noise and Distortion SINAD 66.5 fIN = 70MHz at -0.5dBFS 67.8 fIN = 100MHz at -0.5dBFS 67.6 fIN = 175MHz at -0.5dBFS (Note 6) 2 64.5 64.3 dB 66.4 _______________________________________________________________________________________ dB 12-Bit, 80Msps, 3.3V IF-Sampling ADC (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 80MHz (50% duty cycle), TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN fIN = 70MHz at -0.5dBFS Spurious-Free Dynamic Range SFDR Total Harmonic Distortion Second Harmonic THD HD2 Third Harmonic HD3 Intermodulation Distortion Third-Order Intermodulation Two-Tone Spurious-Free Dynamic Range Full-Power Bandwidth IMD IM3 SFDRTT UNITS dBc 86.2 74.6 85.5 fIN = 70MHz at -0.5dBFS -81.2 fIN = 100MHz at -0.5dBFS -82.3 fIN = 175MHz at -0.5dBFS -82.7 fIN = 70MHz at -0.5dBFS -86.5 fIN = 100MHz at -0.5dBFS -89.6 fIN = 175MHz at -0.5dBFS -89 fIN = 70MHz at -0.5dBFS -85.1 fIN = 100MHz at -0.5dBFS -86.5 fIN = 175MHz at -0.5dBFS -88.6 fIN1 = 68.5MHz at -7dBFS, fIN2 = 71.5MHz at -7dBFS -82.4 fIN1 = 172.5MHz at -7dBFS, fIN2 = 177.5MHz at -7dBFS -74.2 fIN1 = 68.5MHz at -7dBFS, fIN2 = 71.5MHz at -7dBFS -86.4 fIN1 = 172.5MHz at -7dBFS, fIN2 = 177.5MHz at -7dBFS -86.1 fIN1 = 68.5MHz at -7dBFS, fIN2 = 71.5MHz at -7dBFS 85.1 fIN1 = 172.5MHz at -7dBFS, fIN2 = 177.5MHz at -7dBFS 74.2 dBc -73.9 dBc dBc dBc dBc dBc Input at -0.5dBFS, -3dB roll-off 700 Aperture Delay tAD Figure 4 0.9 ns Aperture Jitter tAJ Figure 4 <0.2 psRMS Output Noise nOUT INP = INN = COM 0.52 LSBRMS 1 Clock cycles Overdrive Recovery Time FPBW MAX 85.1 fIN = 100MHz at -0.5dBFS fIN = 175MHz at -0.5dBFS (Note 6) TYP 10% beyond full scale MHz _______________________________________________________________________________________ 3 MAX1209 ELECTRICAL CHARACTERISTICS (continued) MAX1209 12-Bit, 80Msps, 3.3V IF-Sampling ADC ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 80MHz (50% duty cycle), TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 2.048 2.070 V INTERNAL REFERENCE (REFIN = REFOUT; VREFP, VREFN, and VCOM are generated internally) REFOUT Output Voltage VREFOUT 1.984 COM Output Voltage VCOM VDD / 2 1.65 V Differential Reference Output Voltage VREF VREF = VREFP - VREFN 1.024 V REFOUT Load Regulation REFOUT Temperature Coefficient TCREF REFOUT Short-Circuit Current 35 mV/mA +50 ppm/C Short to VDD--sinking 0.24 Short to GND--sourcing 2.1 mA BUFFERED EXTERNAL REFERENCE (REFIN driven externally; VREFIN = 2.048V, VREFP, VREFN, and VCOM are generated internally) REFIN Input Voltage VREFIN 2.048 V REFP Output Voltage VREFP (VDD / 2) + (VREFIN / 4) 2.162 V REFN Output Voltage VREFN (VDD / 2) - (VREFIN / 4) 1.138 V COM Output Voltage VCOM VDD / 2 1.60 1.65 1.70 V Differential Reference Output Voltage VREF VREF = VREFP - VREFN 0.971 1.024 1.069 V Differential Reference Temperature Coefficient 25 ppm/C REFIN Input Resistance >50 M UNBUFFERED EXTERNAL REFERENCE (REFIN = GND; VREFP, VREFN, and VCOM are applied externally) COM Input Voltage VDD / 2 1.65 V REFP Input Voltage VREFP - VCOM 0.512 V REFN Input Voltage VREFN - VCOM -0.512 V VREF VREF = VREFP - VREFN 1.024 V REFP Sink Current IREFP VREFP = 2.162V 1.1 mA REFN Source Current IREFN VREFN = 1.138V 1.1 mA COM Sink Current ICOM 0.3 mA REFP, REFN Capacitance 13 pF COM Capacitance 6 pF Differential Reference Input Voltage VCOM CLOCK INPUTS (CLKP, CLKN) Single-Ended Input High Threshold VIH CLKTYP = GND, CLKN = GND Single-Ended Input Low Threshold VIL CLKTYP = GND, CLKN = GND 0.8 x VDD V 0.2 x VDD V Differential Input Voltage Swing CLKTYP = high 1.4 VP-P Differential Input Common-Mode Voltage CLKTYP = high VDD / 2 V 4 _______________________________________________________________________________________ 12-Bit, 80Msps, 3.3V IF-Sampling ADC (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 80MHz (50% duty cycle), TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER SYMBOL Input Resistance RCLK Input Capacitance CCLK CONDITIONS MIN Figure 5 TYP MAX UNITS 5 k 2 pF DIGITAL INPUTS (CLKTYP, G/T, PD) Input High Threshold VIH Input Low Threshold VIL Input Leakage Current Input Capacitance 0.8 x OVDD V 0.2 x OVDD VIH = OVDD 5 VIL = 0 5 CDIN 5 V A pF DIGITAL OUTPUTS (D11-D0, DAV, DOR) Output Voltage Low VOL Output Voltage High D11-D0, DOR, ISINK = 200A 0.2 DAV, ISINK = 600A 0.2 D11-D0, DOR, ISOURCE = 200A OVDD 0.2 DAV, ISOURCE = 600A OVDD 0.2 V V VOH Tri-State Leakage Current ILEAK (Note 3) 5 A D11-D0, DOR Tri-State Output Capacitance COUT (Note 3) 3 pF DAV Tri-State Output Capacitance CDAV (Note 3) 6 pF POWER REQUIREMENTS Analog Supply Voltage Digital Output Supply Voltage Analog Supply Current VDD 3.0 3.3 3.6 V OVDD 1.7 2.0 VDD + 0.3V V IVDD Normal operating mode, fIN = 175MHz at -0.5dBFS, CLKTYP = GND, single-ended clock 111 Normal operating mode, fIN = 175MHz at -0.5dBFS, CLKTYP = OVDD, differential clock 119 Power-down mode clock idle, PD = OVDD mA 132 0.001 _______________________________________________________________________________________ 5 MAX1209 ELECTRICAL CHARACTERISTICS (continued) MAX1209 12-Bit, 80Msps, 3.3V IF-Sampling ADC ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 80MHz (50% duty cycle), TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER Analog Power Dissipation Digital Output Supply Current SYMBOL PDISS IOVDD CONDITIONS MIN TYP Normal operating mode, fIN = 175MHz at -0.5dBFS, CLKTYP = GND, single-ended clock 366 Normal operating mode, fIN = 175MHz at -0.5dBFS, CLKTYP = OVDD, differential clock 393 MAX UNITS mW 436 Power-down mode clock idle, PD = OVDD 0.003 Normal operating mode, fIN = 175MHz at -0.5dBFS, OVDD = 2.0V, CL 5pF 9.2 mA Power-down mode clock idle, PD = OVDD 0.9 A TIMING CHARACTERISTICS (Figure 6) Clock Pulse Width High tCH 6.25 ns Clock Pulse Width Low tCL 6.25 ns 6.4 ns Data-Valid Delay tDAV CL = 5pF (Note 5) Data Setup Time Before Rising Edge of DAV tSETUP CL = 5pF (Notes 4, 5) 7.7 ns Data Hold Time After Rising Edge of DAV tHOLD CL = 5pF (Notes 4, 5) 4.2 ns Wake-Up Time from Power-Down tWAKE VREFIN = 2.048V Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: 6 10 ms Specifications +25C guaranteed by production test, <+25C guaranteed by design and characterization. See definitions in the Parameter Definitions section. During power-down, D11-D0, DOR, and DAV are high impedance. Guaranteed by design and characterization. Digital outputs settle to VIH or VIL. Due to test equipment jitter limitations at 175MHz, 0.15% of the spectrum on each side of the fundamental is excluded from the spectral analysis. _______________________________________________________________________________________ 12-Bit, 80Msps, 3.3V IF-Sampling ADC SINGLE-TONE FFT PLOT (4096-POINT DATA RECORD) -10 -20 -10 -50 HD3 HD2 -70 HD4 -40 -50 -60 HD4 -70 HD2 HD3 -80 -40 -50 -60 -90 -90 -100 -100 -110 4 8 12 16 20 24 28 32 36 40 FREQUENCY (MHz) -50 fIN2 - fIN1 -60 fIN2 + fIN1 -70 0.6 0.8 0.6 0.4 0.4 0.2 0.2 0 -0.2 0 -0.2 -0.4 -90 -0.6 -100 -0.8 -0.8 -110 -1.0 4 8 12 16 20 24 28 32 36 40 FREQUENCY (MHz) fCLK = 80MHz fIN1 = 172.4853516MHz AIN1 = -6.976dBFS fIN2 = 177.4853516MHz AIN2 = -7.046dBFS SFDRTT = 85.065dBc IMD = -82.255dBc IM3 = -86.378dBc DIFFERENTIAL NONLINEARITY -0.6 0 12 16 20 24 28 32 36 40 1.0 -0.4 -80 8 FREQUENCY (MHz) DNL (LSB) -40 0.8 4 fCLK = 80MHz fIN1 = 68.50098MHz AIN1 = -7.049dBFS fIN2 = 71.499MHz MAX1209 toc05 fIN2 -30 0 12 16 20 24 28 32 36 40 FREQUENCY (MHz) INTEGRAL NONLINEARITY INL (LSB) fIN1 -20 8 1.0 MAX1209 toc04 -10 4 fCLK = 80.00352MHz SINAD = 66.010dB fIN = 175.078125MHz THD = -82.976dBc AIN = -0.500dBFS SFDR = 84.718dBc SNR = 66.097dB TWO-TONE FFT PLOT (16,384-POINT DATA RECORD) 0 2 x fIN1 + fIN2 -110 0 fCLK = 80.00352MHz SINAD = 67.872dB fIN = 69.99331395MHz THD = -82.119dBc AIN = -0.506dBFS SFDR = 85.522dBc SNR = 68.039dB fIN2 + fIN1 -80 -90 0 fIN1 + 2 x fIN2 -70 -100 -110 fIN2 -30 MAX1209 toc06 -60 AMPLITUDE (dBFS) AMPLITUDE (dBFS) -40 fIN1 -20 -30 -30 -80 AMPLITUDE (dBFS) 0 MAX1209 toc02 -20 AMPLITUDE (dBFS) 0 MAX1209 toc01 0 -10 TWO-TONE FFT PLOT (16,384-POINT DATA RECORD) MAX1209 toc03 SINGLE-TONE FFT PLOT (8192-POINT DATA RECORD) -1.0 0 512 1024 1536 2048 2650 3072 3584 4096 DIGITAL OUTPUT CODE 0 512 1024 1536 2048 2650 3072 3584 4096 DIGITAL OUTPUT CODE AIN2 = -7.017dBFS SFDRTT = 74.205dBc IMD = -74.108dBc IM3 = -85.923dBc _______________________________________________________________________________________ 7 MAX1209 Typical Operating Characteristics (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 80MHz (50% duty cycle), TA = +25C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 80MHz (50% duty cycle), TA = +25C, unless otherwise noted.) 90 SFDR, -THD (dBc) 68 67 66 65 64 85 80 75 70 63 62 40 60 80 100 0 20 fCLK (MHz) 100 MAX1209 toc10 40 60 80 100 SFDR, -THD (dBc) 67 66 65 64 fIN 175MHz 85 80 75 70 SNR SINAD 63 80 450 MAX1209 toc09 400 350 ANALOG + DIGITAL POWER ANALOG POWER 250 0 20 40 60 80 0 100 20 40 60 80 fCLK (MHz) SNR, SINAD vs. ANALOG INPUT FREQUENCY SFDR, -THD vs. ANALOG INPUT FREQUENCY POWER DISSIPATION vs. ANALOG INPUT FREQUENCY fCLK 80MHz SFDR, -THD (dBc) 67 66 65 85 80 64 75 SNR SINAD 63 150 ANALOG INPUT FREQUENCY (MHz) 450 400 350 ANALOG + DIGITAL POWER ANALOG POWER 70 100 DIFFERENTIAL CLOCK fCLK 80MHz CL 5pF SFDR -THD 62 50 500 POWER DISSIPATION (mW) 90 200 100 MAX1209 toc15 MAX1209 toc13 95 68 120 DIFFERENTIAL CLOCK fIN 175MHz CL 5pF fCLK (MHz) fCLK 80MHz 0 100 fCLK (MHz) 70 69 100 80 300 60 60 60 500 SFDR -THD 65 62 40 40 POWER DISSIPATION vs. SAMPLING RATE 90 20 20 fCLK (MHz) 95 68 8 0 POWER DISSIPATION (mW) 69 SNR, SINAD (dB) ANALOG + DIGITAL POWER ANALOG POWER SFDR, -THD vs. SAMPLING RATE fIN 175MHz 0 300 fCLK (MHz) SNR, SINAD vs. SAMPLING RATE 70 350 200 MAX1209 toc11 20 400 SFDR -THD 60 0 DIFFERENTIAL CLOCK fIN 70MHz CL 5pF 250 65 SNR SINAD 450 MAX1209 toc14 SNR, SINAD (dB) fIN 70MHz 95 MAX1209 toc12 fIN 70MHz 69 POWER DISSIPATION vs. SAMPLING RATE POWEER DISSIPATION (mW) 100 MAX1209 toc07 70 SFDR, -THD vs. SAMPLING RATE MAX1209 toc08 SNR, SINAD vs. SAMPLING RATE SNR, SINAD (dB) MAX1209 12-Bit, 80Msps, 3.3V IF-Sampling ADC 300 0 50 100 150 ANALOG INPUT FREQUENCY (MHz) 200 0 50 100 150 ANALOG INPUT FREQUENCY (MHz) _______________________________________________________________________________________ 200 12-Bit, 80Msps, 3.3V IF-Sampling ADC SFDR, -THD vs. ANALOG INPUT AMPLITUDE 50 45 40 60 40 -40 -35 -30 -25 -20 -15 -10 -5 0 430 410 390 370 SFDR -THD 45 25 ANALOG + DIGITAL POWER ANALOG POWER 350 -40 -35 -30 -25 -20 -15 -10 -5 -40 0 -35 -30 -25 -20 -15 -10 -5 0 ANALOG INPUT AMPLITUDE (dBFS) ANALOG INPUT AMPLITUDE (dBFS) ANALOG INPUT AMPLITUDE (dBFS) SNR, SINAD vs. ANALOG POWER-INPUT VOLTAGE SFDR, -THD vs. ANALOG POWER-INPUT VOLTAGE POWER DISSIPATION vs. ANALOG POWER-INPUT VOLTAGE fCLK = 80.03584MHz fIN = 32.11399MHz 90 SFDR, -THD (dBc) 67 66 65 64 63 85 80 75 70 62 500 60 60 2.6 2.8 3.0 3.2 3.4 400 350 300 ANALOG + DIGITAL POWER ANALOG POWER 200 2.6 3.6 450 DIFFERENTIAL CLOCK fCLK = 80.03584MHz fIN = 32.11399MHz CL 5pF 250 SFDR -THD 65 SNR SINAD 61 550 MAX1209 toc21 68 95 POWER DISSIPATION (mW) fCLK = 80.03584MHz fIN = 32.11399MHz MAX1209 toc20 100 MAX1209 toc19 70 2.8 3.0 3.2 3.4 3.6 2.6 2.8 3.0 3.2 3.4 3.6 VDD (V) VDD (V) SNR, SINAD vs. OUTPUT-DRIVER POWER-INPUT VOLTAGE SFDR, -THD vs. OUTPUT-DRIVER POWER-INPUT VOLTAGE POWER DISSIPATION vs. OUTPUT-DRIVER POWER-INPUT VOLTAGE fCLK = 80.03584MHz fIN = 32.11399MHz 69 100 MAX1209 toc22 70 68 fCLK = 80.03584MHz fIN = 32.11399MHz 95 550 65 64 63 450 SFDR, -THD (dBc) SFDR, -THD (dBc) 66 85 80 75 70 62 SNR SINAD 61 1.8 2.2 2.6 OVDD (V) 3.0 3.4 3.8 350 300 ANALOG + DIGITAL POWER ANALOG POWER 225 60 1.4 400 250 SFDR -THD 65 60 DIFFERENTIAL CLOCK fCLK = 80.03584MHz fIN = 32.11399MHz CL 5pF 500 90 67 MAX1209 toc24 VDD (V) MAX1209 toc23 SNR, SINAD (dB) 65 50 SNR SINAD 30 SNR, SINAD (dB) 70 55 35 69 75 DIFFERENTIAL CLOCK fCLK = 79.95392MHz fIN = 175.0016MHz CL 5pF 450 POWER DISSIPATION (mW) 55 80 SFDR, -THD (dBc) SNR, SINAD (dB) 60 fCLK = 79.95392MHz fIN = 175.00168MHz 85 470 MAX1209 toc17 fCLK = 79.95392MHz fIN = 175.00168MHz 65 90 MAX1209 toc16 70 POWER DISSIPATION vs. ANALOG INPUT AMPLITUDE MAX1209 toc18 SNR, SINAD vs. ANALOG INPUT AMPLITUDE 200 1.4 1.8 2.2 2.6 OVDD (V) 3.0 3.4 3.8 1.4 1.8 2.2 2.6 3.0 3.4 3.8 OVDD (V) _______________________________________________________________________________________ 9 MAX1209 Typical Operating Characteristics (continued) (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 80MHz (50% duty cycle), TA = +25C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 80MHz (50% duty cycle), TA = +25C, unless otherwise noted.) 65 89 87 85 83 81 64 79 SNR SINAD 63 SFDR -THD 77 75 62 -40 -15 10 35 60 -15 10 35 60 85 MAX1209 toc27 350 300 250 -40 -15 0.3 35 GAIN ERROR vs. TEMPERATURE 3 MAX1209 toc28 VREFIN = 2.048V 10 TEMPERATURE (C) OFFSET ERROR vs. TEMPERATURE 0.5 0.2 VREFIN = 2.048V 2 GAIN ERROR (%FS) OFFSET ERROR (%FS) 400 TEMPERATURE (C) TEMPERATURE (C) 0.4 450 DIFFERENTIAL CLOCK fCLK 80MHz fIN 175MHz CL 5pF 200 -40 85 500 0.1 0 -0.1 -0.2 -0.3 MAX1209 toc29 SFDR, -THD (dBc) 66 ANALOG POWER DISSIPATION (C) 91 68 67 fCLK 80MHz fIN 175MHz 93 550 MAX1209 toc26 fCLK 80MHz fIN 175MHz 69 95 MAX1209 toc25 70 ANALOG POWER DISSIPATION vs. TEMPERATURE SFDR, -THD vs. TEMPERATURE SNR, SINAD vs. TEMPERATURE SNR, SINAD (dB) MAX1209 12-Bit, 80Msps, 3.3V IF-Sampling ADC 1 0 -1 -2 -0.4 -3 -0.5 -40 -15 10 35 TEMPERATURE (C) 10 60 85 -40 -15 10 35 TEMPERATURE (C) 60 ______________________________________________________________________________________ 85 60 85 12-Bit, 80Msps, 3.3V IF-Sampling ADC REFERENCE OUTPUT VOLTAGE LOAD REGULATION 2.03 3.0 2.5 1.99 1.97 1.95 -1.0 -0.5 0 -40C 2.029 0 0.5 -3.0 -2.0 IREFOUT SINK CURRENT (mA) -1.0 0 -40 1.0 -15 35 60 85 REFP, COM, REFN SHORT-CIRCUIT PERFORMANCE VREFP MAX1209 toc34 3.5 MAX1209 toc33 3.0 3.0 VCOM 2.5 VOLTAGE (V) 2.0 VCOM 1.5 -10 TEMPERATURE (C) IREFOUT SINK CURRENT (mA) REFP, COM, REFN LOAD REGULATION 2.5 2.033 2.031 0.5 1.96 -1.5 1.5 2.035 1.0 +25C -2.0 2.0 +25C -40C 1.98 2.037 +85C VREFOUT (V) VREFOUT (V) +85C 2.00 VOLTAGE (V) VREFOUT (V) 2.02 2.039 MAX1209 toc32 2.04 MAX1209 toc31 3.5 MAX1209 toc30 2.05 2.01 REFERENCE OUTPUT VOLTAGE vs. TEMPERATURE REFERENCE OUTPUT VOLTAGE SHORT-CIRCUIT PERFORMANCE VREFP 2.0 1.5 VREFN 1.0 1.0 VREFN 0.5 INTERNAL REFERENCE MODE AND BUFFERED EXTERNAL REFERENCE MODE 0.5 INTERNAL REFERENCE MODE AND BUFFERED EXTERNAL REFERENCE MODE 0 0 -2 -1 0 SINK CURRENT (mA) 1 2 -8 -4 0 4 8 12 SINK CURRENT (mA) ______________________________________________________________________________________ 11 MAX1209 Typical Operating Characteristics (continued) (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 80MHz (50% duty cycle), TA = +25C, unless otherwise noted.) MAX1209 12-Bit, 80Msps, 3.3V IF-Sampling ADC Pin Description PIN NAME FUNCTION REFP Positive Reference I/O. The full-scale analog input range is (VREFP - VREFN). Bypass REFP to GND with a 0.1F capacitor. Connect a 1F capacitor in parallel with a 10F capacitor between REFP and REFN. Place the 1F REFP to REFN capacitor as close to the device as possible on the same side of the printed circuit (PC) board. 2 REFN Negative Reference I/O. The full-scale analog input range is (VREFP - VREFN). Bypass REFN to GND with a 0.1F capacitor. Connect a 1F capacitor in parallel with a 10F capacitor between REFP and REFN. Place the 1F REFP to REFN capacitor as close to the device as possible on the same side of the PC board. 3 COM Common-Mode Voltage I/O. Bypass COM to GND with a 2.2F capacitor. Place the 2.2F COM to GND capacitor as close to the device as possible. This 2.2F capacitor can be placed on the opposite side of the PC board and connected to the MAX1209 through a via. 4, 7, 16, 35 GND Ground. Connect all ground pins and EP together. 1 5 INP Positive Analog Input 6 INN Negative Analog Input 8 DCE Duty-Cycle Equalizer Input. Connect DCE low (GND) to disable the internal duty-cycle equalizer. Connect DCE high (OVDD or VDD) to enable the internal duty-cycle equalizer. 9 CLKN Negative Clock Input. In differential clock input mode (CLKTYP = OVDD or VDD), connect the differential clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the singleended clock signal to CLKP and connect CLKN to GND. 10 CLKP Positive Clock Input. In differential clock input mode (CLKTYP = OVDD or VDD), connect the differential clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the singleended clock signal to CLKP and connect CLKN to GND. 11 CLKTYP Clock Type Definition Input. Connect CLKTYP to GND to define the single-ended clock input. Connect CLKTYP to OVDD or VDD to define the differential clock input. 12-15, 36 VDD Analog Power Input. Connect VDD to a 3.0V to 3.6V power supply. Bypass VDD to GND with a parallel capacitor combination of 2.2F and 0.1F. Connect all VDD pins to the same potential. 17, 34 OVDD Output-Driver Power Input. Connect OVDD to a 1.7V to VDD power supply. Bypass OVDD to GND with a parallel capacitor combination of 2.2F and 0.1F. 18 DOR Data Out-of-Range Indicator. The DOR digital output indicates when the analog input voltage is out of range. When DOR is high, the analog input is beyond its full-scale range. When DOR is low, the analog input is within its full-scale range (Figure 6). 19 D11 CMOS Digital Output, Bit 11 (MSB) 20 D10 CMOS Digital Output, Bit 10 21 D9 CMOS Digital Output, Bit 9 22 D8 CMOS Digital Output, Bit 8 23 D7 CMOS Digital Output, Bit 7 24 D6 CMOS Digital Output, Bit 6 25 D5 CMOS Digital Output, Bit 5 26 D4 CMOS Digital Output, Bit 4 27 D3 CMOS Digital Output, Bit 3 12 ______________________________________________________________________________________ 12-Bit, 80Msps, 3.3V IF-Sampling ADC PIN NAME 28 D2 CMOS Digital Output, Bit 2 FUNCTION 29 D1 CMOS Digital Output, Bit 1 30 D0 CMOS Digital Output, Bit 0 (LSB) 31, 32 I.C. Internally Connected. Leave I.C. unconnected. 33 DAV Data-Valid Output. DAV is a single-ended version of the input clock that is compensated to correct for any input clock duty-cycle variations. DAV is typically used to latch the MAX1209 output data into an external back-end digital circuit. 37 PD 38 REFOUT 39 REFIN 40 G/T Output Format Select Input. Connect G/T to GND for the two's complement digital output format. Connect G/T to OVDD or VDD for the Gray code digital output format. -- EP Exposed Paddle. The MAX1209 relies on the exposed paddle connection for a low-inductance ground connection. Connect EP to GND to achieve specified performance. Use multiple vias to connect the top-side PC board ground plane to the bottom-side PC board ground plane. Power-Down Input. Force PD high for power-down mode. Force PD low for normal operation. Internal Reference Voltage Output. For internal reference operation, connect REFOUT directly to REFIN or use a resistive divider from REFOUT to set the voltage at REFIN. Bypass REFOUT to GND with a 0.1F capacitor. Reference Input. In internal reference mode and buffered external reference mode, bypass REFIN to GND with a 0.1F capacitor. In these modes,VREFP - VREFN = VREFIN/2. For unbuffered external reference-mode operation, connect REFIN to GND. MAX1209 T/H + - FLASH ADC DAC INP T/H STAGE 1 STAGE 2 STAGE 9 INN STAGE 10 END OF PIPE DIGITAL ERROR CORRECTION D11-D0 OUTPUT DRIVERS D11-D0 Figure 1. Pipeline Architecture--Stage Blocks ______________________________________________________________________________________ 13 MAX1209 Pin Description (continued) MAX1209 12-Bit, 80Msps, 3.3V IF-Sampling ADC CLKP CLKN DCE CLKTYP CLOCK GENERATOR AND DUTY-CYCLE EQUALIZER MAX1209 VDD GND OVDD INP INN T/H 12-BIT PIPELINE ADC DEC OUTPUT DRIVERS MAX1209 CPAR 2pF *CSAMPLE 1.9pF CPAR 2pF *CSAMPLE 1.9pF D11-D0 DAV DOR BOND WIRE INDUCTANCE 1.5nH VDD INN REFIN COM VDD INP G/T REFOUT REFP BOND WIRE INDUCTANCE 1.5nH REFERENCE SYSTEM POWER CONTROL AND BIAS CIRCUITS PD REFN Figure 2. Simplified Functional Diagram Detailed Description The MAX1209 uses a 10-stage, fully differential, pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half-clock cycle. From input to output, the total clock-cycle latency is 8.5 clock cycles. Each pipeline converter stage converts its input voltage into a digital output code. At every stage, except the last, the error between the input voltage and the digital output code is multiplied and passed along to the next pipeline stage. Digital error correction compensates for ADC comparator offsets in each pipeline stage and ensures no missing codes. Figure 2 shows the MAX1209 functional diagram. Input Track-and-Hold (T/H) Circuit Figure 3 displays a simplified functional diagram of the input T/H circuit. This input T/H circuit allows for high analog input frequencies of 175MHz and beyond and supports a common-mode input voltage of V DD / 2 0.5V. The MAX1209 sampling clock controls the ADC's switched-capacitor T/H architecture (Figure 3), allowing the analog input signal to be stored as charge on the sampling capacitors. These switches are closed (track) when the sampling clock is high and open (hold) when the sampling clock is low (Figure 4). The analog input signal source must be capable of providing the dynamic current necessary to charge and discharge the sampling capacitors. To avoid signal degradation, these 14 SAMPLING CLOCK *THE EFFECTIVE RESISTANCE OF THE SWITCHED SAMPLING CAPACITORS IS: RSAMPLE = 1 fCLK x CSAMPLE Figure 3. Simplified Input Track-and-Hold Circuit capacitors must be charged to one-half LSB accuracy within one-half of a clock cycle. The analog input of the MAX1209 supports differential or single-ended input drive. For optimum performance with differential inputs, balance the input impedance of INP and INN and set the common-mode voltage to midsupply (VDD / 2). The MAX1209 provides the optimum common-mode voltage of V DD / 2 through the COM output when operating in internal reference mode and buffered external reference mode. This COM output voltage can be used to bias the input network as shown in Figures 10, 11, and 12. Reference Output (REFOUT) An internal bandgap reference is the basis for all the internal voltages and bias currents used in the MAX1209. The power-down logic input (PD) enables and disables the reference circuit. The reference circuit requires 10ms to power up and settle when power is applied to the MAX1209 or when PD transitions from high to low. REFOUT has approximately 17k to GND when the MAX1209 is in power-down. The internal bandgap reference and its buffer generate VREFOUT to be 2.048V. The reference temperature coefficient is typically +50ppm/C. Connect an external 0.1F bypass capacitor from REFOUT to GND for stability. ______________________________________________________________________________________ 12-Bit, 80Msps, 3.3V IF-Sampling ADC MAX1209 CLKP CLKN tAD ANALOG INPUT tAJ SAMPLED DATA T/H TRACK HOLD TRACK HOLD TRACK HOLD TRACK HOLD Figure 4. T/H Aperture Timing REFOUT sources up to 1.0mA and sinks up to 0.1mA for external circuits with a load regulation of 35mV/mA. Short-circuit protection limits I REFOUT to a 2.1mA source current when shorted to GND and a 0.24mA sink current when shorted to VDD. Analog Inputs and Reference Configurations The MAX1209 full-scale analog input range is adjustable from 0.35V to 1.15V with a commonmode input range of VDD / 2 0.5V. The MAX1209 provides three modes of reference operation. The voltage at REFIN (VREFIN) sets the reference operation mode (Table 1). To operate the MAX1209 with the internal reference, connect REFOUT to REFIN either with a direct short or through a resistive divider. In this mode, COM, REFP, and REFN are low-impedance outputs with V COM = VDD / 2, VREFP = VDD / 2 + VREFIN / 4, and VREFN = VDD / 2 - VREFIN / 4. The REFIN input impedance is very large (>50M). When driving REFIN through a resistive divider, use resistances 10k to avoid loading REFOUT. Buffered external reference mode is virtually identical to internal reference mode except that the reference source is derived from an external reference and not the MAX1209 REFOUT. In buffered external reference mode, apply a stable 0.7V to 2.3V source at REFIN. In this mode, COM, REFP, and REFN are low-impedance outputs with VCOM = VDD / 2, VREFP = VDD / 2 + VREFIN / 4, and VREFN = VDD / 2 - VREFIN / 4. To operate the MAX1209 in unbuffered external reference mode, connect REFIN to GND. Connecting REFIN to GND deactivates the on-chip reference buffers for COM, REFP, and REFN. With the respective buffers deactivated, COM, REFP, and REFN become highimpedance inputs and must be driven through separate, external reference sources. Drive VCOM to VDD / 2 5%, and drive REFP and REFN such that V COM = (VREFP + VREFN) / 2. The full-scale analog input range is (VREFP - VREFN). Table 1. Reference Modes VREFIN REFERENCE MODE 35% VREFOUT to 100% VREFOUT 0.7V to 2.3V <0.4V Internal Reference Mode. Drive REFIN with REFOUT either through a direct short or a resistive divider. The full-scale analog input range is VREFIN / 2: VCOM = VDD / 2 VREFP = VDD / 2 + VREFIN / 4 VREFN = VDD / 2 - VREFIN / 4 Buffered External Reference Mode. Apply an external 0.7V to 2.3V reference voltage to REFIN. The full-scale analog input range is VREFIN / 2: VCOM = VDD / 2 VREFP = VDD / 2 + VREFIN / 4 VREFN = VDD / 2 - VREFIN / 4 Unbuffered External Reference Mode. Drive REFP, REFN, and COM with external reference sources. The full-scale analog input range is (VREFP - VREFN). ______________________________________________________________________________________ 15 MAX1209 12-Bit, 80Msps, 3.3V IF-Sampling ADC All three modes of reference operation require the same bypass capacitor combinations. Bypass COM with a 2.2F capacitor to GND. Bypass REFP and REFN each with a 0.1F capacitor to GND. Bypass REFP to REFN with a 1F capacitor in parallel with a 10F capacitor. Place the 1F capacitor as close to the device as possible on the same side of the PC board. Bypass REFIN and REFOUT to GND with a 0.1F capacitor. For detailed circuit suggestions, see Figures 13 and 14. VDD S1H 10k CLKP 10k Clock Input and Clock Control Lines (CLKP, CLKN, CLKTYP) The MAX1209 accepts both differential and singleended clock inputs. For single-ended clock-input operation, connect CLKTYP to GND, CLKN to GND, and drive CLKP with the external single-ended clock signal. For differential clock-input operation, connect CLKTYP to OVDD or VDD, and drive CLKP and CLKN with the external differential clock signal. To reduce clock jitter, the external single-ended clock must have sharp falling edges. Consider the clock input as an analog input and route it away from any other analog inputs and digital signal lines. CLKP and CLKN are high impedance when the MAX1209 is powered down (Figure 5). Low clock jitter is required for the specified SNR performance of the MAX1209. Analog input sampling occurs on the falling edge of the clock signal, requiring this edge to have the lowest possible jitter. Jitter limits the maximum SNR performance of any ADC according to the following relationship: 1 SNR = 20 x log 2 x fIN x t J where fIN represents the analog input frequency and tJ is the total system clock jitter. Clock jitter is especially critical for undersampling applications. For example, assuming that clock jitter is the only noise source, to obtain the specified 66.5dB of SNR with an input frequency of 175MHz, the system must have less than 0.43ps of clock jitter. In actuality, there are other noise sources such as thermal noise and quantization noise that contribute to the system noise, requiring the clock jitter to be less than 0.24ps to obtain the specified 66.5dB of SNR at 175MHz. Clock Duty-Cycle Equalizer (DCE) Enable the MAX1209 clock duty-cycle equalizer by connecting DCE to OVDD or VDD. Disable the clock duty-cycle equalizer by connecting DCE to GND. 16 MAX1209 DUTY-CYCLE EQUALIZER S2H S1L 10k CLKN 10k S2L GND SWITCHES S1_ AND S2_ ARE OPEN DURING POWER-DOWN, MAKING CLKP AND CLKN HIGH IMPEDANCE. SWITCHES S2_ ARE OPEN IN SINGLE-ENDED CLOCK MODE. Figure 5. Simplified Clock Input Circuit The clock duty-cycle equalizer uses a delay-locked loop (DLL) to create internal timing signals that are duty-cycle independent. Due to this DLL, the MAX1209 requires approximately 100 clock cycles to acquire and lock to new clock frequencies. Disabling the clock duty-cycle equalizer reduces the analog supply current by 1.5mA. System Timing Requirements Figure 6 shows the relationship between the clock, analog inputs, DAV indicator, DOR indicator, and the resulting output data. The analog input is sampled on the falling edge of the clock signal and the resulting data appears at the digital outputs 8.5 clock cycles later. The DAV indicator is synchronized with the digital output and optimized for use in latching data into digital back-end circuitry. Alternatively, digital back-end circuitry can be latched with the rising edge of the conversion clock (CLKP-CLKN). Data-Valid Output (DAV) DAV is a single-ended version of the input clock (CLKP). Output data changes on the falling edge of DAV, and DAV rises once output data is valid (Figure 6). ______________________________________________________________________________________ 12-Bit, 80Msps, 3.3V IF-Sampling ADC (VREFP - VREFN) N+5 N+3 N-3 N-2 N-1 N N+1 MAX1209 N+4 DIFFERENTIAL ANALOG INPUT (INP-INN) N+6 N+2 N+7 N+9 N+8 (VREFN - VREFP) tAD CLKN CLKP tDAV tCL tCH DAV tSETUP D11-D0 tHOLD N-3 N-2 N-1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 tSETUP 8.5 CLOCK-CYCLE DATA LATENCY N+8 N+9 tHOLD DOR Figure 6. System Timing Diagram The state of the duty-cycle equalizer input (DCE) changes the waveform at DAV. With the duty-cycle equalizer disabled (DCE = low), the DAV signal is the inverse of the signal at CLKP delayed by 6.8ns. With the duty-cycle equalizer enabled (DCE = high), the DAV signal has a fixed pulse width that is independent of CLKP. In either case, with DCE high or low, output data at D11-D0 and DOR are valid from 7.7ns before the rising edge of DAV to 4.2ns after the rising edge of DAV, and the rising edge of DAV is synchronized to have a 6.4ns (tDAV) delay from the falling edge of CLKP. DAV is high impedance when the MAX1209 is in power-down (PD = high). DAV is capable of sinking and sourcing 600A and has three times the drive strength of D11-D0 and DOR. DAV is typically used to latch the MAX1209 output data into an external backend digital circuit. Keep the capacitive load on DAV as low as possible (<25pF) to avoid large digital currents feeding back into the analog portion of the MAX1209 and degrading its dynamic performance. An external buffer on DAV isolates it from heavy capacitive loads. Refer to the MAX1211 evaluation kit schematic for an example of DAV driving back-end digital circuitry through an external buffer. Data Out-of-Range Indicator (DOR) The DOR digital output indicates when the analog input voltage is out of range. When DOR is high, the analog input is out of range. When DOR is low, the analog input is within range. The valid differential input range is from (VREFP - VREFN) to (VREFN - VREFP). Signals outside this valid differential range cause DOR to assert high as shown in Table 2 and Figure 6. DOR is synchronized with DAV and transitions along with the output data D11-D0. There is an 8.5 clockcycle latency in the DOR function as with the output data (Figure 6). DOR is high impedance when the MAX1209 is in power-down (PD = high). DOR enters a high-impedance state within 10ns after the rising edge of PD and becomes active 10ns after PD's falling edge. Digital Output Data (D11-D0), Output Format (G/T) The MAX1209 provides a 12-bit, parallel, tri-state output bus. D11-D0 and DOR update on the falling edge of DAV and are valid on the rising edge of DAV. The MAX1209 output data format is either Gray code or two's complement, depending on the logic input G/T. With G/T high, the output data format is Gray code. With G/T low, the output data format is two's complement. See Figure 8 for a binary-to-Gray and Gray-tobinary code-conversion example. The following equations, Table 2, Figure 7, and Figure 8 define the relationship between the digital output and the analog input: VINP - VINN = (VREFP - VREFN ) x 2 x CODE10 - 2048 4096 for Gray code (G/T = 1) ______________________________________________________________________________________ 17 MAX1209 12-Bit, 80Msps, 3.3V IF-Sampling ADC VINP - VINN = (VREFP - VREFN ) x 2 x CODE10 4096 for two's complement (G/T = 0) where CODE10 is the decimal equivalent of the digital output code as shown in Table 2. Digital outputs D11-D0 are high impedance when the MAX1209 is in power-down (PD = high). D11-D0 transition high 10ns after the rising edge of PD and become active 10ns after PD's falling edge. Keep the capacitive load on the MAX1209 digital outputs D11-D0 as low as possible (<15pF) to avoid large digital currents feeding back into the analog portion of the MAX1209 and degrading its dynamic performance. The addition of external digital buffers on the digital outputs isolates the MAX1209 from heavy capacitive loading. To improve the dynamic performance of the MAX1209, add 220 resistors in series with the digital outputs close to the MAX1209. Refer to the MAX1211 evaluation kit schematic for an example of the digital outputs driving a digital buffer through 220 series resistors. Table 2. Output Codes vs. Input Voltage GRAY CODE OUTPUT CODE (G/T = 1) BINARY D11D0 DECIMAL HEXADECIMAL EQUIVALENT EQUIVALENT DOR OF OF D11D0 D11D0 (CODE10) TWO'S-COMPLEMENT OUTPUT CODE (G/T = 0) BINARY D11D0 DECIMAL HEXADECIMAL EQUIVALENT EQUIVALENT DOR OF OF D11D0 D11D0 (CODE10) VINP - VINN VREFP = 2.162V VREFN = 1.138V ) ( 1000 0000 0000 1 0x800 +4095 0111 1111 1111 1 0x7FF +2047 >+1.0235V (DATA OUT OF RANGE) 1000 0000 0000 0 0x800 +4095 0111 1111 1111 0 0x7FF +2047 +1.0235V 1000 0000 0001 0 0x801 +4094 0111 1111 1110 0 0x7FE +2046 +1.0230V 1100 0000 0011 0 0xC03 +2050 0000 0000 0010 0 0x002 +2 +0.0010V 1100 0000 0001 0 0xC01 +2049 0000 0000 0001 0 0x001 +1 +0.0005V 1100 0000 0000 0 0xC00 +2048 0000 0000 0000 0 0x000 0 +0.0000V 0100 0000 0000 0 0x400 +2047 1111 1111 1111 0 0xFFF -1 -0.0005V 0100 0000 0001 0 0x401 +2046 1111 1111 1110 0 0xFFE -2 -0.0010V 0000 0000 0001 0 0x001 +1 1000 0000 0001 0 0x801 -2047 -1.0235V 0000 0000 0000 0 0x000 0 1000 0000 0000 0 0x800 -2048 -1.0240V 0000 0000 0000 1 0x000 0 1000 0000 0000 1 0x800 -2048 <-1.0240V (DATA OUT OF RANGE) 18 ______________________________________________________________________________________ 12-Bit, 80Msps, 3.3V IF-Sampling ADC VREF = VREFP - VREFN 1 LSB = VREF 0x7FF 0x7FE 0x7FD 2 x VREF 4096 VREF VREF = VREFP - VREFN VREF 0x800 0x801 0x803 GRAY OUTPUT CODE (LSB) TWO'S COMPLEMENT OUTPUT CODE (LSB) 2 x VREF 4096 VREF MAX1209 1 LSB = 0x001 0x000 0xFFF 0x803 0x802 0x801 0x800 0xC01 0xC00 0x400 0x002 0x003 0x001 0x000 -2047 -2045 -1 0 +1 +2045 +2047 DIFFERENTIAL INPUT VOLTAGE (LSB) Figure 7. Two's Complement Transfer Function (G/T = 0) Power-Down Input (PD) The MAX1209 has two power modes that are controlled with the power-down digital input (PD). With PD low, the MAX1209 is in normal operating mode. With PD high, the MAX1209 is in power-down mode. The power-down mode allows the MAX1209 to efficiently use power by transitioning to a low-power state when conversions are not required. Additionally, the MAX1209 parallel output bus is high impedance in power-down mode, allowing other devices on the bus to be accessed. In power-down mode, all internal circuits are off, the analog supply current reduces to 1A, and the digital supply current reduces to 0.9A. The following list shows the state of the analog inputs and digital outputs in power-down mode: * INP, INN analog inputs are disconnected from the internal input amplifier (Figure 3). * REFOUT has approximately 17k to GND. * REFP, COM, and REFN go high impedance with respect to VDD and GND, but there is an internal 4k resistor between REFP and COM, as well as an internal 4k resistor between REFN and COM. * D11-D0, DOR, and DAV go high impedance. * CLKP and CLKN go high impedance (Figure 5). -2047 -2045 -1 0 +1 +2045 +2047 DIFFERENTIAL INPUT VOLTAGE (LSB) Figure 8. Gray Code Transfer Function (G/T = 1) The wake-up time from power-down mode is dominated by the time required to charge the capacitors at REFP, REFN, and COM. In internal reference mode and buffered external reference mode, the wake-up time is typically 10ms with the recommended capacitor array (Figure 13). When operating in unbuffered external reference mode, the wake-up time is dependent on the external reference drivers. Applications Information Using Transformer Coupling In general, the MAX1209 provides better SFDR and THD performance with fully differential input signals as opposed to single-ended input drive. In differential input mode, even-order harmonics are lower as both inputs are balanced, and each of the ADC inputs only requires half the signal swing compared to single-ended input mode. An RF transformer (Figure 10) provides an excellent solution to convert a single-ended input source signal to a fully differential signal, required by the MAX1209 for optimum performance. Connecting the center tap of the transformer to COM provides a VDD / 2 DC level shift to the input. Although a 1:1 transformer is shown, a step-up transformer can be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, can also improve the overall distortion. The configuration of Figure 10 is good for frequencies up to Nyquist (fCLK / 2). ______________________________________________________________________________________ 19 MAX1209 12-Bit, 80Msps, 3.3V IF-Sampling ADC BINARY-TO-GRAY CODE CONVERSION GRAY-TO-BINARY CODE CONVERSION 1) THE MOST SIGNIFICANT GRAY-CODE BIT IS THE SAME AS THE MOST SIGNIFICANT BINARY BIT. 1) THE MOST SIGNIFICANT BINARY BIT IS THE SAME AS THE MOST SIGNIFICANT GRAY-CODE BIT. D11 0 D7 1 1 1 0 D3 1 0 0 1 D0 1 0 0 0 BIT POSITION D11 BINARY 0 GRAY CODE 0 2) SUBSEQUENT GRAY-CODE BITS ARE FOUND ACCORDING TO THE FOLLOWING EQUATION: 0 0 1 D3 1 1 GRAY10 = 1 + 0 BINARY10 = 0 + 1 GRAY10 = 1 BINARY10 = 1 D7 1 1 0 D3 1 0 1 0 BIT POSITION GRAY CODE WHERE + IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH TABLE BELOW) AND X IS THE BIT POSITION: BINARY10 = BINARY11 + GRAY10 1 D0 0 BINARY GRAY10 = BINARY10 + BINARY11 + 1 BINARYX = BINARYX+1 + GRAYX WHERE + IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH TABLE BELOW) AND X IS THE BIT POSITION: D11 0 2) SUBSEQUENT BINARY BITS ARE FOUND ACCORDING TO THE FOLLOWING EQUATION: GRAYX = BINARYX + BINARYX + 1 0 D7 1 0 1 D0 1 0 0 D11 BIT POSITION BINARY 0 GRAY CODE 0 D7 1 0 0 1 D3 1 1 0 1 D0 0 1 0 BIT POSITION GRAY CODE + 0 1 3) REPEAT STEP 2 UNTIL COMPLETE: BINARY 1 3) REPEAT STEP 2 UNTIL COMPLETE: GRAY9 = BINARY9 + BINARY10 BINARY9 = BINARY10 + GRAY9 GRAY9 = 1 + 1 BINARY9 = 1 + 0 GRAY9 = 0 BINARY9 = 1 D11 0 1 0 1 D7 + 1 1 0 D3 1 0 0 1 D0 1 0 0 BIT POSITION D11 BINARY 0 1 GRAY CODE 0 1 D7 0 0 1 D3 1 1 0 1 D0 0 1 0 BIT POSITION GRAY CODE + 0 4) THE FINAL GRAY CODE CONVERSION IS: D11 D7 1 BINARY 4) THE FINAL BINARY CONVERSION IS: D3 D0 BIT POSITION D11 D7 D3 D0 0 1 1 1 0 1 0 0 1 1 0 0 BINARY 0 1 0 0 1 1 1 0 1 0 1 0 GRAY CODE 0 1 0 0 1 1 1 0 1 0 1 0 GRAY CODE 0 1 1 1 0 1 0 0 1 1 0 0 BINARY EXCLUSIVE OR TRUTH TABLE A B 0 0 1 1 0 1 0 1 Y = A + B 0 1 1 0 Figure 9. Binary-to-Gray and Gray-to-Binary Code Conversion 20 BIT POSITION ______________________________________________________________________________________ 12-Bit, 80Msps, 3.3V IF-Sampling ADC T1 N.C. 2 VIN 0.1F 12pF 6 1 VIN MAX4108 INP 0.1F INP MAX1209 5 5.6pF 100 COM 24.9 MAX1209 2.2F 3 4 MINICIRCUITS TT1-6 OR T1-1T MAX1209 24.9 COM 2.2F 24.9 100 INN 24.9 12pF INN 5.6pF Figure 10. Transformer-Coupled Input Drive for Input Frequencies Up to Nyquist Figure 12. Single-Ended, AC-Coupled Input Drive The circuit of Figure 11 converts a single-ended input signal to fully differential just as Figure 10. However, Figure 11 utilizes an additional transformer to improve the common-mode rejection, allowing high-frequency signals beyond the Nyquist frequency. The two sets of termination resistors provide an equivalent 75 termination to the signal source. The second set of termination resistors connects to COM, providing the correct input common-mode voltage. Two 0 resistors in series with the analog inputs allow high IF input frequencies. These 0 resistors can be replaced with low-value resistors to limit the input bandwidth. Single-Ended AC-Coupled Input Signal Figure 12 shows an AC-coupled, single-ended input application. The MAX4108 provides high speed, high bandwidth, low noise, and low distortion to maintain the input signal integrity. 0* INP 0.1F 6 1 VIN 75 0.5% T1 N.C. 2 5 75 0.5% 2 5 3 4 MINICIRCUITS ADT1-1WT 5.6pF 110 0.1% T2 N.C. 3 4 MINICIRCUITS ADT1-1WT 6 1 MAX1209 N.C. COM 110 0.1% 2.2F 0* INN 5.6pF *0 RESISTORS CAN BE REPLACED WITH LOW-VALUE RESISTORS TO LIMIT THE BANDWIDTH. Figure 11. Transformer-Coupled Input Drive for Input Frequencies Beyond Nyquist ______________________________________________________________________________________ 21 MAX1209 12-Bit, 80Msps, 3.3V IF-Sampling ADC +3.3V 0.1F 2.2F 0.1F +3.3V 1 2 VDD MAX6029EUK21 38 0.1F 5 REFP REFOUT 0.1F 1F* 2.048V 0.1F REFN 2 0.1F +3.3V 39 16.2k 1 10F MAX1209 NOTE: ONE FRONT-END REFERENCE CIRCUIT IS CAPABLE OF SOURCING 15mA AND SINKING 30mA OF OUTPUT CURRENT. 1F 1 5 MAX4230 4 3 3 REFIN GND COM 2.2F 2.048V 47 +3.3V 2 10F 6V 330F 6V 0.1F 2.2F 0.1F 1.47k VDD 38 *PLACE THE 1F REFP-to-REFN BYPASS CAPACITOR AS CLOSE TO THE DEVICE AS POSSIBLE. REFP 1 REFOUT 0.1F 1F* 10F MAX1209 REFN 2 0.1F 39 3 REFIN GND COM 2.2F Figure 13. External Buffered Reference Driving Multiple ADCs Buffered External Reference Drives Multiple ADCs The buffered external reference mode allows for more control over the MAX1209 reference voltage and allows multiple converters to use a common reference. The REFIN input impedance is >50M. 22 Figure 13 uses the MAX6029EUK21 precision 2.048V reference as a common reference for multiple converters. The 2.048V output of the MAX6029 passes through a one-pole, 10Hz lowpass filter to the MAX4230. The MAX4230 buffers the 2.048V reference and provides additional 10Hz lowpass filtering before its output is applied to the REFIN input of the MAX1209. ______________________________________________________________________________________ 12-Bit, 80Msps, 3.3V IF-Sampling ADC MAX1209 +3.3V 1 0.1F MAX6066 2 +3.3V 5 0.1F +3.3V 2.2F 3.000V 0.1F 0.1F 1 24.3k 1% 5 MAX4230 4 3 1 10F 6V 330F 6V 10F 0.1F MAX1209 2 0.1F +3.3V REFN 0.1F 26.7k 1% 1 26.7k 1% 5 10F 6V COM REFIN GND 39 2.2F +3.3V 330F 6V 2.2F 0.1F 20k 1% 20k 1% 1.649V 47 4 3 3 MAX4230 2 20k 1% 38 1F* 1.47k 0.47F VDD REFP REFOUT 2 20k 1% 2.157V 47 0.1F 1.47k 0.1F +3.3V 1 1 5 38 1.141V 10F 47 0.1F 1F* MAX1209 2 2 VDD REFOUT MAX4230 4 3 REFP 10F 6V 330F 6V 3 1.47k *PLACE THE 1F REFP-TO-REFN BYPASS CAPACITOR AS CLOSE TO THE DEVICE AS POSSIBLE. REFN 0.1F COM GND REFIN 39 2.2F Figure 14. External Unbuffered Reference Driving Multiple ADCs Unbuffered External Reference Drives Multiple ADCs The unbuffered external reference mode allows for precise control over the MAX1209 reference and allows multiple converters to use a common reference. Connecting REFIN to GND disables the internal reference, allowing REFP, REFN, and COM to be driven directly by a set of external reference sources. Figure 14 uses the MAX6029EUK30 precision 3.000V reference as a common reference for multiple converters. A five-component resistive divider chain follows the MAX6029 voltage reference. The 0.47F capacitor along this chain creates a 10Hz lowpass filter. Three MAX4230 operational amplifiers buffer taps along this resistor ______________________________________________________________________________________ 23 MAX1209 12-Bit, 80Msps, 3.3V IF-Sampling ADC chain providing 2.157V, 1.649V, and 1.141V to the MAX1209's REFP, COM, and REFN reference inputs, respectively. The feedback around the MAX4230 op amps provides additional 10Hz lowpass filtering. The 2.157V and 1.141V reference voltages set the full-scale analog input range to 1.016V. A common power source for all active components removes any concern regarding power-supply sequencing when powering up or down. Grounding, Bypassing, and Board Layout The MAX1209 requires high-speed board layout design techniques. Refer to the MAX1211 evaluation kit data sheet for a board layout reference. Locate all bypass capacitors as close to the device as possible, preferably on the same side of the board as the ADC, using surface-mount devices for minimum inductance. Bypass VDD to GND with a 0.1F ceramic capacitor in parallel with a 2.2F ceramic capacitor. Bypass OVDD to GND with a 0.1F ceramic capacitor in parallel with a 2.2F ceramic capacitor. Multilayer boards with ample ground and power planes produce the highest level of signal integrity. All MAX1209 GNDs and the exposed backside paddle must be connected to the same ground plane. The MAX1209 relies on the exposed backside paddle connection for a low-inductance ground connection. Use multiple vias to connect the top-side ground to the bottom-side ground. Isolate the ground plane from any noisy digital system ground planes such as a DSP or output buffer ground. Route high-speed digital signal traces away from the sensitive analog traces. Keep all signal lines short and free of 90 turns. Ensure that the differential analog input network layout is symmetric and that all parasitics are balanced equally. Refer to the MAX1211 evaluation kit data sheet for an example of symmetric input layout. Parameter Definitions Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. For the MAX1209, this straight line is between the end points of the transfer function, once offset and gain errors have been nullified. INL deviations are measured at every step of the transfer function and the worst-case deviation is reported in the Electrical Characteristics table. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function. For the MAX1209, DNL deviations are measured at every step of the transfer function and the worst-case deviation is reported in the Electrical Characteristics table. Offset Error Offset error is a figure of merit that indicates how well the actual transfer function matches the ideal transfer function at a single point. Ideally the midscale MAX1209 transition occurs at 0.5 LSB above midscale. The offset error is the amount of deviation between the measured midscale transition point and the ideal midscale transition point. Gain Error Gain error is a figure of merit that indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. The slope of the actual transfer function is measured between two data points: positive full scale and negative full scale. Ideally, the positive full-scale MAX1209 transition occurs at 1.5 LSBs below positive full scale, and the negative fullscale transition occurs at 0.5 LSB above negative full scale. The gain error is the difference of the measured transition points minus the difference of the ideal transition points. Small-Signal Noise Floor (SSNF) Small-signal noise floor is the integrated noise and distortion power in the Nyquist band for small-signal inputs. The DC offset is excluded from this noise calculation. For this converter, a small signal is defined as a single tone with an amplitude less than -35dBFS. This parameter captures the thermal and quantization noise characteristics of the converter and can be used to help calculate the overall noise figure of a receive channel. Go to www.maxim-ic.com for application notes on thermal + quantization noise floor. Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC's resolution (N bits): SNR[max] = 6.02 x N + 1.76 In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, 24 ______________________________________________________________________________________ 12-Bit, 80Msps, 3.3V IF-Sampling ADC Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus distortion. RMS noise plus distortion includes all spectral components to the Nyquist frequency excluding the fundamental and the DC offset. Effective Number of Bits (ENOB) ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quantization noise only. ENOB for a full-scale sinusoidal input waveform is computed from: Single-Tone Spurious-Free Dynamic Range (SFDR) SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS amplitude of the next-largest spurious component, excluding DC offset. Total Harmonic Distortion (THD) THD is the ratio of the RMS sum of the first six harmonics of the input signal to the fundamental itself. This is expressed as: * Third-order intermodulation products: 2 x fIN1 - fIN2, 2 x fIN2 - fIN1, 2 x fIN1 + fIN2, 2 x fIN2 + fIN1 * Fourth-order intermodulation products: 3 x fIN1 - fIN2, 3 x fIN2 - fIN1, 3 x fIN1 + fIN2, 3 x fIN2 + fIN1 * Fifth-order intermodulation products: 3 x fIN1 - 2 x fIN2, 3 x fIN2 - 2 x fIN1, 3 x fIN1 + 2 x fIN2, 3 x fIN2 + 2 x fIN1 IM3 is the total power of the third-order intermodulation products to the Nyquist frequency relative to the total input power of the two input tones fIN1 and fIN2. The individual input tone levels are at -7dBFS. The thirdorder intermodulation products are 2 x fIN1 - fIN2, 2 x fIN2 - fIN1, 2 x fIN1 + fIN2, 2 x fIN2 + fIN1. Two-Tone Spurious-Free Dynamic Range (SFDRTT) SFDRTT represents the ratio, expressed in decibels, of the RMS amplitude of either input tone to the RMS amplitude of the next-largest spurious component in the spectrum, excluding DC offset. This spurious component can occur anywhere in the spectrum up to Nyquist and is usually an intermodulation product or a harmonic. Full-Power Bandwidth where V1 is the fundamental amplitude, and V2 through V7 are the amplitudes of the 2nd- through 7th-order harmonics (HD2-HD7). Intermodulation Distortion (IMD) IMD is the ratio of the RMS sum of the intermodulation products to the RMS sum of the two fundamental input tones. This is expressed as: VIM12 + VIM 2 2 + ....... + VIM13 2 + VIM14 2 IMD = 20 x log V12 + V2 2 fIN1 + fIN2, fIN2 - fIN1 Third-Order Intermodulation (IM3) SINAD - 1.76 ENOB = 6.02 2 2 2 2 2 2 V2 + V3 + V4 + V5 + V6 + V7 THD = 20 x log V1 are used in the MAX1209 IMD calculation. The intermodulation products are the amplitudes of the output spectrum at the following frequencies, where fIN1 and fIN2 are the fundamental input tone frequencies: * Second-order intermodulation products: The fundamental input tone amplitudes (V1 and V2) are at -7dBFS. Fourteen intermodulation products (VIM_) A large -0.5dBFS analog input signal is applied to an ADC, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. This point is defined as fullpower input bandwidth frequency. In practical laboratory measurements, full-power bandwidth is limited by the analog input circuitry and not the ADC itself. For the MAX1209, the full-power bandwidth is tested using the MAX1211 evaluation kit input circuitry. Aperture Delay The MAX1209 samples data on the falling edge of its sampling clock. In actuality, there is a small delay between the falling edge of the sampling clock and the actual sampling instant. Aperture delay (tAD) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken (Figure 4). ______________________________________________________________________________________ 25 MAX1209 etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first six harmonics (HD2-HD7), and the DC offset. Aperture Jitter Overdrive Recovery Time Overdrive recovery time is the time required for the ADC to recover from an input transient that exceeds the full-scale limits. The MAX1209 specifies overdrive recovery time using an input transient that exceeds the full-scale limits by 10%. I.C. I.C. DAV OVDD GND PD REFOUT REFIN TOP VIEW G/T Output Noise (nOUT) The output noise (nOUT) parameter is similar to the thermal + quantization noise parameter and is an indication of the ADC's overall noise performance. No fundamental input tone is used to test for nOUT; INP, INN, and COM are connected together and 1024k data points collected. nOUT is computed by taking the RMS value of the collected data points. VDD Pin Configuration Figure 4 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay. 40 39 38 37 36 35 34 33 32 31 REFP 1 30 D0 REFN 2 29 D1 COM 3 28 D2 GND 4 27 D3 INP 5 26 D4 INN 6 25 D5 GND 7 24 D6 DCE 8 23 D7 CLKN 9 22 D8 CLKP 10 21 D9 MAX1209 EXPOSED PADDLE (GND) THIN QFN 6mm x 6mm x 0.8mm 26 ______________________________________________________________________________________ D10 D11 DOR OVDD GND VDD VDD VDD VDD 11 12 13 14 15 16 17 18 19 20 CLKTYP MAX1209 12-Bit, 80Msps, 3.3V IF-Sampling ADC 12-Bit, 80Msps, 3.3V IF-Sampling ADC QFN THIN.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 27 (c) 2004 Maxim Integrated Products is a registered trademark of Maxim Integrated Products. MAX1209 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)