General Description
The MAX1209 is a 3.3V, 12-bit, 80Msps analog-to-digital
converter (ADC) featuring a fully differential wideband
track-and-hold (T/H) input amplifier, driving a low-noise
internal quantizer. The analog input stage accepts sin-
gle-ended or differential signals. The MAX1209 is opti-
mized for low power, small size, and high dynamic
performance. Excellent dynamic performance is main-
tained from baseband to input frequencies of 175MHz
and beyond, making the MAX1209 ideal for intermediate-
frequency (IF) sampling applications.
Powered from a single 3.0V to 3.6V supply, the
MAX1209 consumes only 366mW while delivering a
typical signal-to-noise (SNR) performance of 66.5dB at
an input frequency of 175MHz. In addition to low oper-
ating power, the MAX1209 features a 3µW power-down
mode to conserve power during idle periods.
A flexible reference structure allows the MAX1209 to use
the internal 2.048V bandgap reference or accept an
externally applied reference. The reference structure
allows the full-scale analog input range to be adjusted
from ±0.35V to ±1.15V. The MAX1209 provides a com-
mon-mode reference to simplify design and reduce exter-
nal component count in differential analog input circuits.
The MAX1209 supports both a single-ended and differ-
ential input clock drive. Wide variations in the clock
duty cycle are compensated with the ADC’s internal
duty-cycle equalizer (DCE).
ADC conversion results are available through a 12-bit,
parallel, CMOS-compatible output bus. The digital out-
put format is pin selectable to be either two’s comple-
ment or Gray code. A data-valid indicator eliminates
external components that are normally required for reli-
able digital interfacing. A separate digital power input
accepts a wide 1.7V to 3.6V supply, allowing the
MAX1209 to interface with various logic levels.
The MAX1209 is available in a 6mm x 6mm x 0.8mm,
40-pin thin QFN package with exposed paddle (EP),
and is specified for the extended industrial (-40°C to
+85°C) temperature range.
See the Pin-Compatible Versions table for a complete
family of 14-bit and 12-bit high-speed ADCs.
Applications
IF Communication Receivers
Cellular, Point-to-Point Microwave, HFC, WLAN
Ultrasound and Medical Imaging
Portable Instrumentation
Low-Power Data Acquisition
Features
♦Direct IF Sampling Up to 400MHz
♦Excellent Dynamic Performance
68.0dB/66.5dB SNR at fIN = 70MHz/175MHz
85.1dBc/85.5dBc SFDR at fIN = 70MHz/175MHz
♦3.3V Low-Power Operation
366mW (Single-Ended Clock Mode)
393mW (Differential Clock Mode)
3µW (Power-Down Mode)
♦Differential or Single-Ended Clock
♦Fully Differential or Single-Ended Analog Input
♦Adjustable Full-Scale Analog Input Range: ±0.35V
to ±1.15V
♦Common-Mode Reference
♦CMOS-Compatible Outputs in Two’s Complement
or Gray Code
♦Data-Valid Indicator Simplifies Digital Design
♦Data Out-of-Range Indicator
♦Miniature, 40-Pin Thin QFN Package with Exposed
Paddle
♦Evaluation Kit Available (Order MAX1211EVKIT)
MAX1209
12-Bit, 80Msps, 3.3V IF-Sampling ADC
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-1001; Rev 0; 8/04
PART TEMP
RANGE
PIN-PACKAGE PKG
CODE
MAX1209ETL
-40°C to
+85°C
40 Thin QFN
(6mm x 6mm x 0.8mm)
T4066-3
Pin-Compatible Versions
PART SAMPLING
RATE (Msps)
RESOLUTION
(BITS)
TARGET
APPLICATION
MAX12553
65 14
IF/Baseband
MAX1209
80 12 IF
MAX1211
65 12 IF
MAX1208
80 12 Baseband
MAX1207
65 12 Baseband
MAX1206
40 12 Baseband
Pin Configuration appears at end of data sheet.
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim's website at www.maxim-ic.com.
MAX1209
12-Bit, 80Msps, 3.3V IF-Sampling ADC
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK = 80MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to GND...........................................................-0.3V to +3.6V
OVDD to GND........-0.3V to the lower of (VDD + 0.3V) and +3.6V
INP, INN to GND ...-0.3V to the lower of (VDD + 0.3V) and +3.6V
REFIN, REFOUT, REFP, REFN, COM
to GND................-0.3V to the lower of (VDD + 0.3V) and +3.6V
CLKP, CLKN, CLKTYP, G/T, DCE,
PD to GND ........-0.3V to the lower of (VDD + 0.3V) and +3.6V
D11 Through D0, I.C. DAV, DOR to GND ...-0.3V to (OVDD + 0.3V)
Continuous Power Dissipation (TA= +70°C)
40-Pin Thin QFN 6mm x 6mm x 0.8mm
(derated 26.3mW/°C above +70°C)........................2105.3mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering 10s) ..................................+300°C
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
DC ACCURACY (Note 2)
Resolution 12 Bits
Integral Nonlinearity INL fIN = 3MHz
±0.6
LSB
Differential Nonlinearity DNL fIN = 3MHz, no missing codes over
temperature
-0.77 ±0.35
LSB
Offset Error VREFIN = 2.048V
±0.17 ±0.91
Gain Error VREFIN = 2.048V
±0.56 ±5.3
ANALOG INPUT (INP, INN)
Differential Input Voltage Range VDIFF Differential or single-ended inputs
±1.024
V
Common-Mode Input Voltage
VDD / 2
V
CPAR Fixed capacitance to ground 2
Input Capacitance
(Figure 3)
CSAMPLE
Switched capacitance 1.9 pF
CONVERSION RATE
Maximum Clock Frequency fCLK 80
Minimum Clock Frequency 5
Data Latency Figure 6 8.5
DYNAMIC CHARACTERISTICS (differential inputs, Note 2)
Small-Signal Noise Floor SSNF Input at less than -35dBFS
-68.8
fIN = 70MHz at -0.5dBFS 68.0
fIN = 100MHz at -0.5dBFS 67.7Signal-to-Noise Ratio SNR
fIN = 175MHz at -0.5dBFS (Note 6)
64.5
66.5
dB
fIN = 70MHz at -0.5dBFS 67.8
fIN = 100MHz at -0.5dBFS 67.6
Signal-to-Noise and Distortion SINAD
fIN = 175MHz at -0.5dBFS (Note 6)
64.3
66.4
dB
MAX1209
12-Bit, 80Msps, 3.3V IF-Sampling ADC
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK = 80MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
fIN = 70MHz at -0.5dBFS 85.1
fIN = 100MHz at -0.5dBFS 86.2
Spurious-Free Dynamic Range SFDR
fIN = 175MHz at -0.5dBFS (Note 6)
74.6
85.5
dBc
fIN = 70MHz at -0.5dBFS
-81.2
fIN = 100MHz at -0.5dBFS
-82.3
Total Harmonic Distortion THD
fIN = 175MHz at -0.5dBFS
-82.7 -73.9
dBc
fIN = 70MHz at -0.5dBFS
-86.5
fIN = 100MHz at -0.5dBFS
-89.6
Second Harmonic HD2
fIN = 175MHz at -0.5dBFS -89
dBc
fIN = 70MHz at -0.5dBFS
-85.1
fIN = 100MHz at -0.5dBFS
-86.5
Third Harmonic HD3
fIN = 175MHz at -0.5dBFS
-88.6
dBc
fIN1 = 68.5MHz at -7dBFS,
fIN2 = 71.5MHz at -7dBFS
-82.4
Intermodulation Distortion IMD
fIN1 = 172.5MHz at -7dBFS,
fIN2 = 177.5MHz at -7dBFS
-74.2
dBc
fIN1 = 68.5MHz at -7dBFS,
fIN2 = 71.5MHz at -7dBFS
-86.4
Third-Order Intermodulation IM3
fIN1 = 172.5MHz at -7dBFS,
fIN2 = 177.5MHz at -7dBFS
-86.1
dBc
fIN1 = 68.5MHz at -7dBFS,
fIN2 = 71.5MHz at -7dBFS 85.1
Two-Tone Spurious-Free
Dynamic Range
SFDRTT
fIN1 = 172.5MHz at -7dBFS,
fIN2 = 177.5MHz at -7dBFS 74.2
dBc
Full-Power Bandwidth FPBW Input at -0.5dBFS, -3dB roll-off 700
MHz
Aperture Delay tAD Figure 4 0.9 ns
Aperture Jitter tAJ Figure 4 <0.2
psRMS
Output Noise nOUT INP = INN = COM 0.52
LSBRMS
Overdrive Recovery Time ±10% beyond full scale 1 Clock
cycles
MAX1209
12-Bit, 80Msps, 3.3V IF-Sampling ADC
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK = 80MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INTERNAL REFERENCE (REFIN = REFOUT; VREFP, VREFN, and VCOM are generated internally)
REFOUT Output Voltage
VREFOUT 1.984 2.048 2.070
V
COM Output Voltage VCOM VDD / 2
1.65
V
Differential Reference Output
Voltage VREF VREF = VREFP - VREFN
1.024
V
REFOUT Load Regulation 35
mV/mA
REFOUT Temperature Coefficient
TCREF
+50
ppm/°C
Short to VDD—sinking
0.24
REFOUT Short-Circuit Current Short to GND—sourcing 2.1 mA
BUF F ERED EXTERNAL REF ERENCE (REF IN d ri ven extern al ly; VR EF IN
= 2.048V, VR EF P, VR EF N
, an d VC OM
are g en erated in tern ally)
REFIN Input Voltage VREFIN
2.048
V
REFP Output Voltage VREFP (VDD / 2) + (VREFIN / 4)
2.162
V
REFN Output Voltage VREFN (VDD / 2) - (VREFIN / 4)
1.138
V
COM Output Voltage VCOM VDD / 2
1.60 1.65 1.70
V
Differential Reference Output
Voltage VREF VREF = VREFP - VREFN
0.971 1.024 1.069
V
Differential Reference
Temperature Coefficient
±25
ppm/°C
REFIN Input Resistance
>50
MΩ
UNBUFFERED EXTERNAL REFERENCE (REFIN = GND; VREFP, VREFN, and VCOM are applied externally)
COM Input Voltage VCOM VDD / 2
1.65
V
REFP Input Voltage VREFP - VCOM
0.512
V
REFN Input Voltage VREFN - VCOM
-0.512
V
Differential Reference Input
Voltage VREF VREF = VREFP - VREFN
1.024
V
REFP Sink Current IREFP VREFP = 2.162V 1.1 mA
REFN Source Current IREFN VREFN = 1.138V 1.1 mA
COM Sink Current ICOM 0.3 mA
REFP, REFN Capacitance 13 pF
COM Capacitance 6pF
CLOCK INPUTS (CLKP, CLKN)
Single-Ended Input High
Threshold VIH CLKTYP = GND, CLKN = GND 0.8 x
VDD
V
Single-Ended Input Low
Threshold VIL CLKTYP = GND, CLKN = GND 0.2 x
VDD
V
Differential Input Voltage Swing CLKTYP = high 1.4
VP-P
Differential Input Common-Mode
Voltage CLKTYP = high
VDD / 2
V
MAX1209
12-Bit, 80Msps, 3.3V IF-Sampling ADC
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK = 80MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Resistance RCLK Figure 5 5 kΩ
Input Capacitance CCLK 2pF
DIGITAL INPUTS (CLKTYP, G/T, PD)
Input High Threshold VIH 0.8 x
OVDD
V
Input Low Threshold VIL 0.2 x
OVDD
V
VIH = OVDD ±5
Input Leakage Current VIL = 0 ±5µA
Input Capacitance CDIN 5pF
DIGITAL OUTPUTS (D11–D0, DAV, DOR)
D11–D0, DOR, ISINK = 200µA 0.2
Output Voltage Low VOL DAV, ISINK = 600µA 0.2 V
D11–D0, DOR, ISOURCE = 200µA
OVDD -
0.2
Output Voltage High VOH
DAV, ISOURCE = 600µA OVDD -
0.2
V
Tri-State Leakage Current ILEAK (Note 3) ±5 µA
D11–D0, DOR Tri-State Output
Capacitance COUT (Note 3) 3 pF
DAV Tri-State Output
Capacitance CDAV (Note 3) 6 pF
POWER REQUIREMENTS
Analog Supply Voltage VDD 3.0 3.3 3.6 V
Digital Output Supply Voltage OVDD 1.7 2.0
VDD +
0.3V
V
Normal operating mode,
fIN = 175MHz at -0.5dBFS, CLKTYP = GND,
single-ended clock
111
Normal operating mode,
fIN = 175MHz at -0.5dBFS,
CLKTYP = OVDD, differential clock
119
132
Analog Supply Current IVDD
Power-down mode clock idle, PD = OVDD
0.001
mA
MAX1209
12-Bit, 80Msps, 3.3V IF-Sampling ADC
6 _______________________________________________________________________________________
Note 1: Specifications ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization.
Note 2: See definitions in the Parameter Definitions section.
Note 3: During power-down, D11–D0, DOR, and DAV are high impedance.
Note 4: Guaranteed by design and characterization.
Note 5: Digital outputs settle to VIH or VIL.
Note 6: Due to test equipment jitter limitations at 175MHz, 0.15% of the spectrum on each side of the fundamental is excluded from
the spectral analysis.
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK = 80MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
Normal operating mode,
fIN = 175MHz at -0.5dBFS, CLKTYP = GND,
single-ended clock
366
Normal operating mode,
fIN = 175MHz at -0.5dBFS,
CLKTYP = OVDD, differential clock
393
436
Analog Power Dissipation PDISS
Power-down mode clock idle, PD = OVDD
0.003
mW
Normal operating mode,
fIN = 175MHz at -0.5dBFS, OVDD = 2.0V,
CL ≈ 5pF
9.2 mA
Digital Output Supply Current IOVDD
Power-down mode clock idle, PD = OVDD 0.9 µA
TIMING CHARACTERISTICS (Figure 6)
Clock Pulse Width High tCH
6.25
ns
Clock Pulse Width Low tCL
6.25
ns
Data-Valid Delay tDAV CL = 5pF (Note 5) 6.4 ns
Data Setup Time Before Rising
Edge of DAV tSETUP CL = 5pF (Notes 4, 5) 7.7 ns
Data Hold Time After Rising Edge
of DAV tHOLD CL = 5pF (Notes 4, 5) 4.2 ns
Wake-Up Time from Power-Down
tWAKE VREFIN = 2.048V 10 ms
MAX1209
12-Bit, 80Msps, 3.3V IF-Sampling ADC
_______________________________________________________________________________________ 7
-100
-30
-40
-10
-20
-70
-80
-90
-50
-60
0
0 4 8 1216202428323640
SINGLE-TONE FFT PLOT
(8192-POINT DATA RECORD)
MAX1209 toc01
FREQUENCY (MHz)
AMPLITUDE (dBFS)
fCLK = 80.00352MHz SINAD = 67.872dB
fIN = 69.99331395MHz THD = -82.119dBc
AIN = -0.506dBFS SFDR = 85.522dBc
SNR = 68.039dB
-110
HD2 HD3
HD4
SINGLE-TONE FFT PLOT
(4096-POINT DATA RECORD)
MAX1209 toc02
FREQUENCY (MHz)
AMPLITUDE (dBFS)
fCLK = 80.00352MHz SINAD = 66.010dB
fIN = 175.078125MHz THD = -82.976dBc
AIN = -0.500dBFS SFDR = 84.718dBc
SNR = 66.097dB
0 4 8 1216202428323640
HD4 HD2 HD3
-100
-30
-40
-10
-20
-70
-80
-90
-50
-60
0
-110
TWO-TONE FFT PLOT
(16,384-POINT DATA RECORD)
MAX1209 toc03
FREQUENCY (MHz)
AMPLITUDE (dBFS)
fCLK = 80MHz AIN2 = -7.046dBFS
fIN1 = 68.50098MHz SFDRTT = 85.065dBc
AIN1 = -7.049dBFS IMD = -82.255dBc
fIN2 = 71.499MHz IM3 = -86.378dBc
0 4 8 1216202428323640
-100
-30
-40
-10
-20
-70
-80
-90
-50
-60
0
-110
fIN1
fIN2
2 x fIN1 + fIN2
fIN1 + 2 x fIN2
fIN2 + fIN1
TWO-TONE FFT PLOT
(16,384-POINT DATA RECORD)
MAX1209 toc04
FREQUENCY (MHz)
AMPLITUDE (dBFS)
fCLK = 80MHz AIN2 = -7.017dBFS
fIN1 = 172.4853516MHz SFDRTT = 74.205dBc
AIN1 = -6.976dBFS IMD = -74.108dBc
fIN2 = 177.4853516MHz IM3 = -85.923dBc
0 4 8 1216202428323640
-100
-30
-40
-10
-20
-70
-80
-90
-50
-60
0
-110
fIN1
fIN2
fIN2 - fIN1 fIN2 + fIN1
-1.0
-0.6
-0.8
-0.2
-0.4
0.2
0
0.4
0.8
0.6
1.0
0 1024 1536512 2048 2650 3072 3584 4096
INTEGRAL NONLINEARITY
MAX1209 toc05
DIGITAL OUTPUT CODE
INL (LSB)
-1.0
-0.6
-0.8
-0.2
-0.4
0.2
0
0.4
0.8
0.6
1.0
0 1024 1536512 2048 2650 3072 3584 4096
DIFFERENTIAL NONLINEARITY
MAX1209 toc06
DIGITAL OUTPUT CODE
DNL (LSB)
Typical Operating Characteristics
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK = 80MHz (50% duty cycle), TA = +25°C, unless otherwise noted.)
MAX1209
12-Bit, 80Msps, 3.3V IF-Sampling ADC
8 _______________________________________________________________________________________
SNR, SINAD
vs. SAMPLING RATE
MAX1209 toc07
fCLK (MHz)
SNR, SINAD (dB)
806020 40
63
64
65
66
67
68
69
70
62
0 100
fIN ≈ 70MHz
SNR
SINAD
SFDR, -THD
vs. SAMPLING RATE
MAX1209 toc08
fCLK (MHz)
SFDR, -THD (dBc)
806020 40
65
70
75
80
85
90
95
100
60
0 100
fIN ≈ 70MHz
SFDR
-THD
POWER DISSIPATION
vs. SAMPLING RATE
MAX1209 toc09
fCLK (MHz)
POWEER DISSIPATION (mW)
806020 40
250
300
350
400
450
200
0 120100
DIFFERENTIAL CLOCK
fIN ≈ 70MHz
CL ≈ 5pF
ANALOG + DIGITAL POWER
ANALOG POWER
62
64
63
65
66
67
68
69
70
04020 60 80 100
SNR, SINAD vs. SAMPLING RATE
MAX1209 toc10
fCLK (MHz)
SNR, SINAD (dB)
SNR
SINAD
fIN ≈ 175MHz
60
70
65
75
80
85
90
95
100
04020 60 80 100
SFDR, -THD vs. SAMPLING RATE
MAX1209 toc11
fCLK (MHz)
SFDR, -THD (dBc)
SFDR
-THD
fIN ≈ 175MHz
250
300
350
400
450
500
04020 60 80 100
POWER DISSIPATION
vs. SAMPLING RATE
MAX1209 toc12
fCLK (MHz)
POWER DISSIPATION (mW)
ANALOG + DIGITAL POWER
ANALOG POWER
DIFFERENTIAL CLOCK
fIN ≈ 175MHz
CL ≈ 5pF
62
64
63
65
66
67
68
69
70
0 50 100 150 200
SNR, SINAD
vs. ANALOG INPUT FREQUENCY
MAX1209 toc13
ANALOG INPUT FREQUENCY (MHz)
SNR, SINAD (dB)
SNR
SINAD
fCLK ≈ 80MHz
70
75
80
85
90
95
0 50 100 150 200
SFDR, -THD
vs. ANALOG INPUT FREQUENCY
MAX1209 toc14
ANALOG INPUT FREQUENCY (MHz)
SFDR, -THD (dBc)
fCLK ≈ 80MHz
SFDR
-THD
300
350
400
450
500
0 50 100 150 200
POWER DISSIPATION
vs. ANALOG INPUT FREQUENCY
MAX1209 toc15
ANALOG INPUT FREQUENCY (MHz)
POWER DISSIPATION (mW)
ANALOG + DIGITAL POWER
ANALOG POWER
DIFFERENTIAL CLOCK
fCLK ≈ 80MHz
CL ≈ 5pF
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK = 80MHz (50% duty cycle), TA = +25°C, unless otherwise noted.)
MAX1209
12-Bit, 80Msps, 3.3V IF-Sampling ADC
_______________________________________________________________________________________ 9
25
35
30
40
45
50
55
60
65
70
-40 -30-35 -25 -15 -5-20 -10 0
SNR, SINAD
vs. ANALOG INPUT AMPLITUDE
MAX1209 toc16
ANALOG INPUT AMPLITUDE (dBFS)
SNR, SINAD (dB)
SNR
SINAD
fCLK = 79.95392MHz
fIN = 175.00168MHz
40
50
45
55
60
65
75
70
80
85
90
-40 -30-35 -25 -15 -5-20 -10 0
SFDR, -THD
vs. ANALOG INPUT AMPLITUDE
MAX1209 toc17
ANALOG INPUT AMPLITUDE (dBFS)
SFDR, -THD (dBc)
SFDR
-THD
fCLK = 79.95392MHz
fIN = 175.00168MHz
350
370
390
410
430
450
470
-40 -30-35 -25 -15 -5-20 -10 0
POWER DISSIPATION
vs. ANALOG INPUT AMPLITUDE
MAX1209 toc18
ANALOG INPUT AMPLITUDE (dBFS)
POWER DISSIPATION (mW)
ANALOG + DIGITAL POWER
ANALOG POWER
DIFFERENTIAL CLOCK
fCLK = 79.95392MHz
fIN = 175.0016MHz
CL ≈ 5pF
SNR, SINAD
vs. ANALOG POWER-INPUT VOLTAGE
MAX1209 toc19
VDD (V)
SNR, SINAD (dB)
3.43.23.02.8
61
62
63
64
65
66
67
68
69
70
60
2.6 3.6
fCLK = 80.03584MHz
fIN = 32.11399MHz
SNR
SINAD
SFDR, -THD
vs. ANALOG POWER-INPUT VOLTAGE
MAX1209 toc20
VDD (V)
SFDR, -THD (dBc)
3.43.23.02.8
65
70
75
80
85
90
95
100
60
2.6 3.6
fCLK = 80.03584MHz
fIN = 32.11399MHz
SFDR
-THD
POWER DISSIPATION
vs. ANALOG POWER-INPUT VOLTAGE
MAX1209 toc21
VDD (V)
POWER DISSIPATION (mW)
3.43.23.02.8
250
300
350
400
450
500
550
200
2.6 3.6
DIFFERENTIAL CLOCK
fCLK = 80.03584MHz
fIN = 32.11399MHz
CL ≈ 5pF
ANALOG + DIGITAL POWER
ANALOG POWER
SNR, SINAD
vs. OUTPUT-DRIVER POWER-INPUT VOLTAGE
MAX1209 toc22
OVDD (V)
SNR, SINAD (dB)
3.43.02.62.21.8
61
62
63
64
65
66
67
68
69
70
60
1.4 3.8
fCLK = 80.03584MHz
fIN = 32.11399MHz
SNR
SINAD
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK = 80MHz (50% duty cycle), TA = +25°C, unless otherwise noted.)
SFDR, -THD
vs. OUTPUT-DRIVER POWER-INPUT VOLTAGE
MAX1209 toc23
OVDD (V)
SFDR, -THD (dBc)
3.43.02.62.21.8
65
70
75
80
85
90
95
100
60
1.4 3.8
fCLK = 80.03584MHz
fIN = 32.11399MHz
SFDR
-THD
POWER DISSIPATION
vs. OUTPUT-DRIVER POWER-INPUT VOLTAGE
MAX1209 toc24
OVDD (V)
SFDR, -THD (dBc)
3.43.02.62.21.8
250
225
300
350
400
450
500
550
200
1.4 3.8
DIFFERENTIAL CLOCK
fCLK = 80.03584MHz
fIN = 32.11399MHz
CL ≈ 5pF
ANALOG + DIGITAL POWER
ANALOG POWER
MAX1209
12-Bit, 80Msps, 3.3V IF-Sampling ADC
10 ______________________________________________________________________________________
62
64
63
65
66
67
68
69
70
-40 10-15 35 60 85
SNR, SINAD vs. TEMPERATURE
MAX1209 toc25
TEMPERATURE (°C)
SNR, SINAD (dB)
fCLK ≈ 80MHz
fIN ≈ 175MHz
SNR
SINAD
75
81
79
77
83
85
87
89
91
93
95
-40 10-15 35 60 85
SFDR, -THD vs. TEMPERATURE
MAX1209 toc26
TEMPERATURE (°C)
SFDR, -THD (dBc)
fCLK ≈ 80MHz
fIN ≈ 175MHz
SFDR
-THD
200
300
250
350
450
400
500
550
-40 10-15 35 60 85
ANALOG POWER DISSIPATION
vs. TEMPERATURE
MAX1209 toc27
TEMPERATURE (°C)
ANALOG POWER DISSIPATION (°C)
DIFFERENTIAL CLOCK
fCLK ≈ 80MHz
fIN ≈ 175MHz
CL ≈ 5pF
-0.5
-0.2
-0.3
-0.4
-0.1
0
0.1
0.2
0.3
0.4
0.5
-40 10-15 35 60 85
OFFSET ERROR vs. TEMPERATURE
MAX1209 toc28
TEMPERATURE (°C)
OFFSET ERROR (%FS)
VREFIN = 2.048V
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK = 80MHz (50% duty cycle), TA = +25°C, unless otherwise noted.)
-3
-1
-2
0
1
2
3
-40 10-15 35 60 85
GAIN ERROR vs. TEMPERATURE
MAX1209 toc29
TEMPERATURE (°C)
GAIN ERROR (%FS)
VREFIN = 2.048V
MAX1209
12-Bit, 80Msps, 3.3V IF-Sampling ADC
______________________________________________________________________________________ 11
0
1.5
1.0
0.5
2.5
2.0
3.0
3.5
-8 -4 0 4 8 12
REFP, COM, REFN
SHORT-CIRCUIT PERFORMANCE
MAX1209 toc34
SINK CURRENT (mA)
VOLTAGE (V)
VREFP
VCOM
VREFN
INTERNAL REFERENCE MODE
AND BUFFERED EXTERNAL
REFERENCE MODE
0
1.0
0.5
2.0
1.5
2.5
3.0
-2 0-1 1 2
REFP, COM, REFN
LOAD REGULATION
MAX1209 toc33
SINK CURRENT (mA)
VOLTAGE (V)
VREFP
VCOM
VREFN
INTERNAL REFERENCE MODE AND
BUFFERED EXTERNAL REFERENCE MODE
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK = 80MHz (50% duty cycle), TA = +25°C, unless otherwise noted.)
1.95
1.97
1.96
1.98
1.99
2.00
2.02
2.01
2.03
2.04
2.05
-2.0 0.5-1.5 -1.0 -0.5 0
REFERENCE OUTPUT VOLTAGE
LOAD REGULATION
MAX1209 toc30
IREFOUT SINK CURRENT (mA)
VREFOUT (V)
+85°C
+25°C
-40°C
0
0.5
1.0
1.5
2.5
2.0
3.0
3.5
-3.0 -2.0 -1.0 0 1.0
REFERENCE OUTPUT VOLTAGE
SHORT-CIRCUIT PERFORMANCE
MAX1209 toc31
IREFOUT SINK CURRENT (mA)
VREFOUT (V)
+85°C
+25°C
-40°C
2.029
2.031
2.033
2.035
2.037
2.039
-40 85-15 -10 35 60
REFERENCE OUTPUT VOLTAGE
vs. TEMPERATURE
MAX1209 toc32
TEMPERATURE (°C)
VREFOUT (V)
MAX1209
12-Bit, 80Msps, 3.3V IF-Sampling ADC
12 ______________________________________________________________________________________
PIN NAME FUNCTION
1 REFP
Positive Reference I/O. The full-scale analog input range is ±(VREFP - VREFN). Bypass REFP to GND with
a 0.1µF capacitor. Connect a 1µF capacitor in parallel with a 10µF capacitor between REFP and REFN.
Place the 1µF REFP to REFN capacitor as close to the device as possible on the same side of the
printed circuit (PC) board.
2 REFN
Negative Reference I/O. The full-scale analog input range is ±(VREFP - VREFN). Bypass REFN to GND
with a 0.1µF capacitor. Connect a 1µF capacitor in parallel with a 10µF capacitor between REFP and
REFN. Place the 1µF REFP to REFN capacitor as close to the device as possible on the same side
of the PC board.
3 COM
Common-Mode Voltage I/O. Bypass COM to GND with a 2.2µF capacitor. Place the 2.2µF COM to
GND capacitor as close to the device as possible. This 2.2µF capacitor can be placed on the
opposite side of the PC board and connected to the MAX1209 through a via.
4, 7, 16,
35 GND Ground. Connect all ground pins and EP together.
5 INP Positive Analog Input
6 INN Negative Analog Input
8 DCE Duty-Cycle Equalizer Input. Connect DCE low (GND) to disable the internal duty-cycle equalizer.
Connect DCE high (OVDD or VDD) to enable the internal duty-cycle equalizer.
9 CLKN
Negative Clock Input. In differential clock input mode (CLKTYP = OVDD or VDD), connect the differential
clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the single-
ended clock signal to CLKP and connect CLKN to GND.
10 CLKP
Positive Clock Input. In differential clock input mode (CLKTYP = OVDD or VDD), connect the differential
clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the single-
ended clock signal to CLKP and connect CLKN to GND.
11 CLKTYP Clock Type Definition Input. Connect CLKTYP to GND to define the single-ended clock input. Connect
CLKTYP to OVDD or VDD to define the differential clock input.
12–15, 36
VDD Analog Power Input. Connect VDD to a 3.0V to 3.6V power supply. Bypass VDD to GND with a parallel
capacitor combination of ≥2.2µF and 0.1µF. Connect all VDD pins to the same potential.
17, 34 OVDD Output-Driver Power Input. Connect OVDD to a 1.7V to VDD power supply. Bypass OVDD to GND with a
parallel capacitor combination of ≥2.2µF and 0.1µF.
18 DOR
Data Out-of-Range Indicator. The DOR digital output indicates when the analog input voltage is out of
range. When DOR is high, the analog input is beyond its full-scale range. When DOR is low, the analog
input is within its full-scale range (Figure 6).
19 D11 CMOS Digital Output, Bit 11 (MSB)
20 D10 CMOS Digital Output, Bit 10
21 D9 CMOS Digital Output, Bit 9
22 D8 CMOS Digital Output, Bit 8
23 D7 CMOS Digital Output, Bit 7
24 D6 CMOS Digital Output, Bit 6
25 D5 CMOS Digital Output, Bit 5
26 D4 CMOS Digital Output, Bit 4
27 D3 CMOS Digital Output, Bit 3
Pin Description
MAX1209
12-Bit, 80Msps, 3.3V IF-Sampling ADC
______________________________________________________________________________________ 13
PIN NAME FUNCTION
28 D2 CMOS Digital Output, Bit 2
29 D1 CMOS Digital Output, Bit 1
30 D0 CMOS Digital Output, Bit 0 (LSB)
31, 32 I.C. Internally Connected. Leave I.C. unconnected.
33 DAV
Data-Valid Output. DAV is a single-ended version of the input clock that is compensated to correct for
any input clock duty-cycle variations. DAV is typically used to latch the MAX1209 output data into an
external back-end digital circuit.
37 PD Power-Down Input. Force PD high for power-down mode. Force PD low for normal operation.
38 REFOUT
Internal Reference Voltage Output. For internal reference operation, connect REFOUT directly to REFIN
or use a resistive divider from REFOUT to set the voltage at REFIN. Bypass REFOUT to GND with a
≥0.1µF capacitor.
39 REFIN
Reference Input. In internal reference mode and buffered external reference mode, bypass REFIN to
GND with a ≥0.1µF capacitor. In these modes,VREFP - VREFN = VREFIN/2. For unbuffered external
reference-mode operation, connect REFIN to GND.
40 G/TOutput Format Select Input. Connect G/T to GND for the two’s complement digital output format.
Connect G/T to OVDD or VDD for the Gray code digital output format.
—EP
Exposed Paddle. The MAX1209 relies on the exposed paddle connection for a low-inductance ground
connection. Connect EP to GND to achieve specified performance. Use multiple vias to connect the
top-side PC board ground plane to the bottom-side PC board ground plane.
Pin Description (continued)
MAX1209 Σ
+
−
DIGITAL ERROR CORRECTION
FLASH
ADC
T/H
DAC
STAGE 2
D11–D0
INP
INN
STAGE 1
T/H STAGE 9 STAGE 10
END OF PIPE
OUTPUT
DRIVERS
D11–D0
Figure 1. Pipeline Architecture—Stage Blocks
MAX1209
Detailed Description
The MAX1209 uses a 10-stage, fully differential,
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consump-
tion. Samples taken at the inputs move progressively
through the pipeline stages every half-clock cycle.
From input to output, the total clock-cycle latency is 8.5
clock cycles.
Each pipeline converter stage converts its input voltage
into a digital output code. At every stage, except the
last, the error between the input voltage and the digital
output code is multiplied and passed along to the next
pipeline stage. Digital error correction compensates for
ADC comparator offsets in each pipeline stage and
ensures no missing codes. Figure 2 shows the
MAX1209 functional diagram.
Input Track-and-Hold (T/H) Circuit
Figure 3 displays a simplified functional diagram of the
input T/H circuit. This input T/H circuit allows for high
analog input frequencies of 175MHz and beyond and
supports a common-mode input voltage of VDD / 2
±0.5V.
The MAX1209 sampling clock controls the ADC’s
switched-capacitor T/H architecture (Figure 3), allowing
the analog input signal to be stored as charge on the
sampling capacitors. These switches are closed (track)
when the sampling clock is high and open (hold) when
the sampling clock is low (Figure 4). The analog input
signal source must be capable of providing the dynam-
ic current necessary to charge and discharge the sam-
pling capacitors. To avoid signal degradation, these
capacitors must be charged to one-half LSB accuracy
within one-half of a clock cycle.
The analog input of the MAX1209 supports differential
or single-ended input drive. For optimum performance
with differential inputs, balance the input impedance of
INP and INN and set the common-mode voltage to mid-
supply (VDD / 2). The MAX1209 provides the optimum
common-mode voltage of VDD / 2 through the COM
output when operating in internal reference mode and
buffered external reference mode. This COM output
voltage can be used to bias the input network as shown
in Figures 10, 11, and 12.
Reference Output (REFOUT)
An internal bandgap reference is the basis for all the
internal voltages and bias currents used in the
MAX1209. The power-down logic input (PD) enables
and disables the reference circuit. The reference circuit
requires 10ms to power up and settle when power is
applied to the MAX1209 or when PD transitions from
high to low. REFOUT has approximately 17kΩto GND
when the MAX1209 is in power-down.
The internal bandgap reference and its buffer generate
VREFOUT to be 2.048V. The reference temperature coeffi-
cient is typically +50ppm/°C. Connect an external ≥0.1µF
bypass capacitor from REFOUT to GND for stability.
12-Bit, 80Msps, 3.3V IF-Sampling ADC
14 ______________________________________________________________________________________
MAX1209
INP
INN
12-BIT
PIPELINE
ADC
DEC
REFERENCE
SYSTEM
COM
REFOUT
REFN
REFP
OVDD
DAV
OUTPUT
DRIVERS
D11–D0
DOR
REFIN
T/H
POWER CONTROL
AND
BIAS CIRCUITS
CLKP CLOCK
GENERATOR
AND
DUTY-CYCLE
EQUALIZER
CLKN
CLKTYP
PD
VDD
GND
DCE
G/T
Figure 2. Simplified Functional Diagram
MAX1209
CPAR
2pF
VDD
BOND WIRE
INDUCTANCE
1.5nH
INP
SAMPLING
CLOCK
*THE EFFECTIVE RESISTANCE OF THE
SWITCHED SAMPLING CAPACITORS IS:
*CSAMPLE
1.9pF
CPAR
2pF
VDD
BOND WIRE
INDUCTANCE
1.5nH
INN
*CSAMPLE
1.9pF
RSAMPLE = 1
fCLK x CSAMPLE
Figure 3. Simplified Input Track-and-Hold Circuit
REFOUT sources up to 1.0mA and sinks up to 0.1mA
for external circuits with a load regulation of 35mV/mA.
Short-circuit protection limits IREFOUT to a 2.1mA
source current when shorted to GND and a 0.24mA
sink current when shorted to VDD.
Analog Inputs and Reference
Configurations
The MAX1209 full-scale analog input range is
adjustable from ±0.35V to ±1.15V with a common-
mode input range of VDD / 2 ±0.5V. The MAX1209 pro-
vides three modes of reference operation. The voltage
at REFIN (VREFIN) sets the reference operation mode
(Table 1).
To operate the MAX1209 with the internal reference,
connect REFOUT to REFIN either with a direct short or
through a resistive divider. In this mode, COM, REFP,
and REFN are low-impedance outputs with VCOM =
VDD / 2, VREFP = VDD / 2 + VREFIN / 4, and VREFN =
VDD / 2 - VREFIN / 4. The REFIN input impedance is very
large (>50MΩ). When driving REFIN through a resistive
divider, use resistances ≥10kΩto avoid loading
REFOUT.
Buffered external reference mode is virtually identical to
internal reference mode except that the reference source
is derived from an external reference and not the
MAX1209 REFOUT. In buffered external reference mode,
apply a stable 0.7V to 2.3V source at REFIN. In this
mode, COM, REFP, and REFN are low-impedance out-
puts with VCOM = VDD / 2, VREFP = VDD / 2 + VREFIN / 4,
and VREFN = VDD / 2 - VREFIN / 4.
To operate the MAX1209 in unbuffered external refer-
ence mode, connect REFIN to GND. Connecting REFIN
to GND deactivates the on-chip reference buffers for
COM, REFP, and REFN. With the respective buffers
deactivated, COM, REFP, and REFN become high-
impedance inputs and must be driven through sepa-
rate, external reference sources. Drive VCOM to VDD / 2
±5%, and drive REFP and REFN such that VCOM =
(VREFP + VREFN) / 2. The full-scale analog input range
is ±(VREFP - VREFN).
MAX1209
12-Bit, 80Msps, 3.3V IF-Sampling ADC
______________________________________________________________________________________ 15
tAD
T/H
CLKN
CLKP
tAJ
TRACK HOLDTRACK HOLDTRACK HOLDTRACKHOLD
ANALOG
INPUT
SAMPLED
DATA
Figure 4. T/H Aperture Timing
VREFIN REFERENCE MODE
35% VREFOUT to 100%
VREFOUT
Internal Reference Mode. Drive REFIN with REFOUT either through a direct short or a resistive divider.
The full-scale analog input range is ±VREFIN / 2:
VCOM = VDD / 2
VREFP = VDD / 2 + VREFIN / 4
VREFN = VDD / 2 – VREFIN / 4
0.7V to 2.3V
Buffered External Reference Mode. Apply an external 0.7V to 2.3V reference voltage to REFIN.
The full-scale analog input range is ±VREFIN / 2:
VCOM = VDD / 2
VREFP = VDD / 2 + VREFIN / 4
VREFN = VDD / 2 – VREFIN / 4
<0.4V Unbuffered External Reference Mode. Drive REFP, REFN, and COM with external reference sources.
The full-scale analog input range is ±(VREFP – VREFN).
Table 1. Reference Modes
MAX1209
All three modes of reference operation require the
same bypass capacitor combinations. Bypass COM
with a 2.2µF capacitor to GND. Bypass REFP and
REFN each with a 0.1µF capacitor to GND. Bypass
REFP to REFN with a 1µF capacitor in parallel with a
10µF capacitor. Place the 1µF capacitor as close to
the device as possible on the same side of the PC
board. Bypass REFIN and REFOUT to GND with a
0.1µF capacitor.
For detailed circuit suggestions, see Figures 13 and 14.
Clock Input and Clock Control Lines
(CLKP, CLKN, CLKTYP)
The MAX1209 accepts both differential and single-
ended clock inputs. For single-ended clock-input oper-
ation, connect CLKTYP to GND, CLKN to GND, and
drive CLKP with the external single-ended clock signal.
For differential clock-input operation, connect CLKTYP
to OVDD or VDD, and drive CLKP and CLKN with the
external differential clock signal. To reduce clock jitter,
the external single-ended clock must have sharp falling
edges. Consider the clock input as an analog input and
route it away from any other analog inputs and digital
signal lines.
CLKP and CLKN are high impedance when the
MAX1209 is powered down (Figure 5).
Low clock jitter is required for the specified SNR perfor-
mance of the MAX1209. Analog input sampling occurs
on the falling edge of the clock signal, requiring this
edge to have the lowest possible jitter. Jitter limits the
maximum SNR performance of any ADC according to
the following relationship:
where fIN represents the analog input frequency and tJ
is the total system clock jitter. Clock jitter is especially
critical for undersampling applications. For example,
assuming that clock jitter is the only noise source, to
obtain the specified 66.5dB of SNR with an input fre-
quency of 175MHz, the system must have less than
0.43ps of clock jitter. In actuality, there are other noise
sources such as thermal noise and quantization noise
that contribute to the system noise, requiring the clock
jitter to be less than 0.24ps to obtain the specified
66.5dB of SNR at 175MHz.
Clock Duty-Cycle Equalizer (DCE)
Enable the MAX1209 clock duty-cycle equalizer by
connecting DCE to OVDD or VDD. Disable the clock
duty-cycle equalizer by connecting DCE to GND.
The clock duty-cycle equalizer uses a delay-locked
loop (DLL) to create internal timing signals that are
duty-cycle independent. Due to this DLL, the MAX1209
requires approximately 100 clock cycles to acquire and
lock to new clock frequencies.
Disabling the clock duty-cycle equalizer reduces the
analog supply current by 1.5mA.
System Timing Requirements
Figure 6 shows the relationship between the clock, ana-
log inputs, DAV indicator, DOR indicator, and the result-
ing output data. The analog input is sampled on the
falling edge of the clock signal and the resulting data
appears at the digital outputs 8.5 clock cycles later.
The DAV indicator is synchronized with the digital out-
put and optimized for use in latching data into digital
back-end circuitry. Alternatively, digital back-end cir-
cuitry can be latched with the rising edge of the con-
version clock (CLKP-CLKN).
Data-Valid Output (DAV)
DAV is a single-ended version of the input clock (CLKP).
Output data changes on the falling edge of DAV, and
DAV rises once output data is valid (Figure 6).
SNR
ft
IN J
log
=× ×π ×
⎛
⎝
⎜⎞
⎠
⎟
20 1
2
12-Bit, 80Msps, 3.3V IF-Sampling ADC
16 ______________________________________________________________________________________
MAX1209
CLKP
CLKN
VDD
GND
10kΩ
10kΩ
10kΩ
10kΩ
DUTY-CYCLE
EQUALIZER
SWITCHES S1_ AND S2_ ARE OPEN
DURING POWER-DOWN, MAKING
CLKP AND CLKN HIGH IMPEDANCE.
SWITCHES S2_ ARE OPEN IN
SINGLE-ENDED CLOCK MODE.
S1H
S2H
S1L
S2L
Figure 5. Simplified Clock Input Circuit
The state of the duty-cycle equalizer input (DCE)
changes the waveform at DAV. With the duty-cycle
equalizer disabled (DCE = low), the DAV signal is the
inverse of the signal at CLKP delayed by 6.8ns. With the
duty-cycle equalizer enabled (DCE = high), the DAV sig-
nal has a fixed pulse width that is independent of CLKP.
In either case, with DCE high or low, output data at
D11–D0 and DOR are valid from 7.7ns before the rising
edge of DAV to 4.2ns after the rising edge of DAV, and
the rising edge of DAV is synchronized to have a 6.4ns
(tDAV) delay from the falling edge of CLKP.
DAV is high impedance when the MAX1209 is in
power-down (PD = high). DAV is capable of sinking
and sourcing 600µA and has three times the drive
strength of D11–D0 and DOR. DAV is typically used to
latch the MAX1209 output data into an external back-
end digital circuit.
Keep the capacitive load on DAV as low as possible
(<25pF) to avoid large digital currents feeding back
into the analog portion of the MAX1209 and degrading
its dynamic performance. An external buffer on DAV
isolates it from heavy capacitive loads. Refer to the
MAX1211 evaluation kit schematic for an example of
DAV driving back-end digital circuitry through an exter-
nal buffer.
Data Out-of-Range Indicator (DOR)
The DOR digital output indicates when the analog input
voltage is out of range. When DOR is high, the analog
input is out of range. When DOR is low, the analog
input is within range. The valid differential input range is
from (VREFP - VREFN) to (VREFN - VREFP). Signals out-
side this valid differential range cause DOR to assert
high as shown in Table 2 and Figure 6.
DOR is synchronized with DAV and transitions along
with the output data D11–D0. There is an 8.5 clock-
cycle latency in the DOR function as with the output
data (Figure 6).
DOR is high impedance when the MAX1209 is in
power-down (PD = high). DOR enters a high-imped-
ance state within 10ns after the rising edge of PD and
becomes active 10ns after PD’s falling edge.
Digital Output Data (D11–D0), Output Format (G/
T
)
The MAX1209 provides a 12-bit, parallel, tri-state out-
put bus. D11–D0 and DOR update on the falling edge
of DAV and are valid on the rising edge of DAV.
The MAX1209 output data format is either Gray code or
two’s complement, depending on the logic input G/T.
With G/Thigh, the output data format is Gray code.
With G/Tlow, the output data format is two’s comple-
ment. See Figure 8 for a binary-to-Gray and Gray-to-
binary code-conversion example.
The following equations, Table 2, Figure 7, and Figure 8
define the relationship between the digital output and
the analog input:
for Gray code (G/T= 1)
VV V V CODE
INP INN REFP REFN
( )
−= − ×× −
22048
4096
10
MAX1209
12-Bit, 80Msps, 3.3V IF-Sampling ADC
______________________________________________________________________________________ 17
DAV
D11–D0
NN+1 N+2
N+3
N+4 N+5
N+6
N+7
N+8
N+9
tDAV
tSETUP
tAD
N-1
N-2
N-3
tHOLD
tCL tCH
DOR
8.5 CLOCK-CYCLE DATA LATENCY
DIFFERENTIAL ANALOG INPUT (INP–INN)
tSETUP tHOLD
N N+1 N+2 N+3 N+5 N+6 N+7N-1N-2N-3 N+9N+4 N+8
CLKN
CLKP
(VREFP - VREFN)
(VREFN - VREFP)
Figure 6. System Timing Diagram
MAX1209
for two’s complement (G/T= 0)
where CODE10 is the decimal equivalent of the digital
output code as shown in Table 2.
Digital outputs D11–D0 are high impedance when the
MAX1209 is in power-down (PD = high). D11–D0 transi-
tion high 10ns after the rising edge of PD and become
active 10ns after PD’s falling edge.
Keep the capacitive load on the MAX1209 digital out-
puts D11–D0 as low as possible (<15pF) to avoid large
digital currents feeding back into the analog portion of
the MAX1209 and degrading its dynamic performance.
The addition of external digital buffers on the digital
outputs isolates the MAX1209 from heavy capacitive
loading. To improve the dynamic performance of the
MAX1209, add 220Ωresistors in series with the digital
outputs close to the MAX1209. Refer to the MAX1211
evaluation kit schematic for an example of the digital
outputs driving a digital buffer through 220Ωseries
resistors.
VV V V CODE
INP INN REFP REFN
( ) −= − ××24096
10
12-Bit, 80Msps, 3.3V IF-Sampling ADC
18 ______________________________________________________________________________________
GRAY CODE OUTPUT CODE (G/T = 1) TWO’S-COMPLEMENT OUTPUT CODE (G/T = 0)
BINARY
D11➝D0
DOR
HEXADECIMAL
EQUIVALENT
OF
D11➝D0
DECIMAL
EQUIVALENT
OF
D11➝D0
(CODE10)
BINARY
D11➝D0
DOR
HEXADECIMAL
EQUIVALENT
OF
D11➝D0
DECIMAL
EQUIVALENT
OF
D11➝D0
(CODE10)
VINP - VINN
VREFP = 2.162V
VREFN = 1.138V
1000 0000 0000
1
0x800 +4095
0111 1111 1111 1
0x7FF +2047
>+1.0235V
(DATA OUT OF
RANGE)
1000 0000 0000
0
0x800 +4095
0111 1111 1111 0
0x7FF +2047 +1.0235V
1000 0000 0001
0
0x801 +4094
0111 1111 1110 0
0x7FE +2046 +1.0230V
1100 0000 0011
0
0xC03 +2050
0000 0000 0010 0
0x002 +2 +0.0010V
1100 0000 0001
0
0xC01 +2049
0000 0000 0001 0
0x001 +1 +0.0005V
1100 0000 0000
0
0xC00 +2048
0000 0000 0000 0
0x000 0 +0.0000V
0100 0000 0000
0
0x400 +2047
1111 1111 1111 0
0xFFF -1 -0.0005V
0100 0000 0001
0
0x401 +2046
1111 1111 1110 0
0xFFE -2 -0.0010V
0000 0000 0001
0
0x001 +1
1000 0000 0001 0
0x801 -2047 -1.0235V
0000 0000 0000
0
0x000 0
1000 0000 0000 0
0x800 -2048 -1.0240V
0000 0000 0000
1
0x000 0
1000 0000 0000 1
0x800 -2048
<-1.0240V
(DATA OUT OF
RANGE)
Table 2. Output Codes vs. Input Voltage
()
Power-Down Input (PD)
The MAX1209 has two power modes that are controlled
with the power-down digital input (PD). With PD low, the
MAX1209 is in normal operating mode. With PD high,
the MAX1209 is in power-down mode.
The power-down mode allows the MAX1209 to efficient-
ly use power by transitioning to a low-power state when
conversions are not required. Additionally, the
MAX1209 parallel output bus is high impedance in
power-down mode, allowing other devices on the bus
to be accessed.
In power-down mode, all internal circuits are off, the
analog supply current reduces to 1µA, and the digital
supply current reduces to 0.9µA. The following list
shows the state of the analog inputs and digital outputs
in power-down mode:
• INP, INN analog inputs are disconnected from the
internal input amplifier (Figure 3).
• REFOUT has approximately 17kΩto GND.
• REFP, COM, and REFN go high impedance with
respect to VDD and GND, but there is an internal 4kΩ
resistor between REFP and COM, as well as an inter-
nal 4kΩresistor between REFN and COM.
• D11–D0, DOR, and DAV go high impedance.
• CLKP and CLKN go high impedance (Figure 5).
The wake-up time from power-down mode is dominat-
ed by the time required to charge the capacitors at
REFP, REFN, and COM. In internal reference mode and
buffered external reference mode, the wake-up time is
typically 10ms with the recommended capacitor array
(Figure 13). When operating in unbuffered external ref-
erence mode, the wake-up time is dependent on the
external reference drivers.
Applications Information
Using Transformer Coupling
In general, the MAX1209 provides better SFDR and THD
performance with fully differential input signals as
opposed to single-ended input drive. In differential input
mode, even-order harmonics are lower as both inputs are
balanced, and each of the ADC inputs only requires half
the signal swing compared to single-ended input mode.
An RF transformer (Figure 10) provides an excellent
solution to convert a single-ended input source signal
to a fully differential signal, required by the MAX1209
for optimum performance. Connecting the center tap of
the transformer to COM provides a VDD / 2 DC level
shift to the input. Although a 1:1 transformer is shown, a
step-up transformer can be selected to reduce the
drive requirements. A reduced signal swing from the
input driver, such as an op amp, can also improve the
overall distortion. The configuration of Figure 10 is good
for frequencies up to Nyquist (fCLK / 2).
MAX1209
12-Bit, 80Msps, 3.3V IF-Sampling ADC
______________________________________________________________________________________ 19
DIFFERENTIAL INPUT VOLTAGE (LSB)
-1-2045
4096
2 x VREF
1 LSB = VREF = VREFP - VREFN
VREF VREF
0+1-2047 +2047+2045
TWO'S COMPLEMENT OUTPUT CODE (LSB)
0x800
0x801
0x802
0x803
0x7FF
0x7FE
0x7FD
0xFFF
0x000
0x001
Figure 7. Two’s Complement Transfer Function (G/
T
= 0)
DIFFERENTIAL INPUT VOLTAGE (LSB)
-1-2045
4096
2 x VREF
1 LSB = VREF = VREFP - VREFN
VREF VREF
0+1-2047 +2047+2045
GRAY OUTPUT CODE (LSB)
0x000
0x001
0x003
0x002
0x800
0x801
0x803
0x400
0xC00
0xC01
Figure 8. Gray Code Transfer Function (G/
T
= 1)
MAX1209
12-Bit, 80Msps, 3.3V IF-Sampling ADC
20 ______________________________________________________________________________________
BINARY-TO-GRAY CODE CONVERSION
1) THE MOST SIGNIFICANT GRAY-CODE BIT IS THE SAME
AS THE MOST SIGNIFICANT BINARY BIT.
0111 0100 1100 BINARY
GRAY CODE0
2) SUBSEQUENT GRAY-CODE BITS ARE FOUND ACCORDING
TO THE FOLLOWING EQUATION:
D11 D7 D3 D0
GRAYX = BINARYX +BINARYX + 1
BIT POSITION
0 111 0100 1100 BINARY
GRAY CODE0
D11 D7 D3 D0 BIT POSITION
GRAY10 = BINARY10 BINARY11
GRAY10 = 1 0
GRAY10 = 1
1
3) REPEAT STEP 2 UNTIL COMPLETE:
01 11 0100 1100 BINARY
GRAY CODE0
D11 D7 D3 D0 BIT POSITION
GRAY9 = BINARY9BINARY10
GRAY9 = 1 1
GRAY9 = 0
10
4) THE FINAL GRAY CODE CONVERSION IS:
0111 0100 1100 BINARY
GRAY CODE0
D11 D7 D3 D0 BIT POSITION
1001101 1010
GRAY-TO-BINARY CODE CONVERSION
1) THE MOST SIGNIFICANT BINARY BIT IS THE SAME AS THE
MOST SIGNIFICANT GRAY-CODE BIT.
2) SUBSEQUENT BINARY BITS ARE FOUND ACCORDING TO
THE FOLLOWING EQUATION:
D11 D7 D3 D0
BINARYX = BINARYX+1
BIT POSITION
BINARY10 = BINARY11 GRAY10
BINARY10 = 0 1
BINARY10 = 1
3) REPEAT STEP 2 UNTIL COMPLETE:
4) THE FINAL BINARY CONVERSION IS:
0100 1110 1010
BINARY
GRAY CODE
D11 D7 D3 D0 BIT POSITION
0 BINARY
GRAY CODE0100 11 011010
BINARY9 = BINARY10 GRAY9
BINARY9 = 1 0
BINARY9 = 1
GRAYX
0 100 1110 1010
BINARY
GRAY CODE
0
D11 D7 D3 D0 BIT POSITION
1
01 00 1110 1010
BINARY
GRAY CODE
0
D11 D7 D3 D0 BIT POSITION
11
0111 0100 1100
AB Y=AB
00
01
10
11
0
1
1
0
EXCLUSIVE OR TRUTH TABLE
WHERE IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH
TABLE BELOW) AND X IS THE BIT POSITION:
+WHERE IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH
TABLE BELOW) AND X IS THE BIT POSITION:
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Figure 9. Binary-to-Gray and Gray-to-Binary Code Conversion
The circuit of Figure 11 converts a single-ended input
signal to fully differential just as Figure 10. However,
Figure 11 utilizes an additional transformer to improve
the common-mode rejection, allowing high-frequency
signals beyond the Nyquist frequency. The two sets of
termination resistors provide an equivalent 75Ωtermi-
nation to the signal source. The second set of termina-
tion resistors connects to COM, providing the correct
input common-mode voltage. Two 0Ωresistors in series
with the analog inputs allow high IF input frequencies.
These 0Ωresistors can be replaced with low-value
resistors to limit the input bandwidth.
Single-Ended AC-Coupled Input Signal
Figure 12 shows an AC-coupled, single-ended input
application. The MAX4108 provides high speed, high
bandwidth, low noise, and low distortion to maintain the
input signal integrity.
MAX1209
12-Bit, 80Msps, 3.3V IF-Sampling ADC
______________________________________________________________________________________ 21
MAX1209
1
2
3
6
5
4
N.C.
VIN
0.1μF
T1
MINICIRCUITS
TT1-6 OR T1-1T
24.9Ω
24.9Ω
12pF
12pF
2.2μF
INP
COM
INN
Figure 10. Transformer-Coupled Input Drive for Input
Frequencies Up to Nyquist
MAX1209
1
2
3
6
5
4
N.C. N.C.
T2
MINICIRCUITS
ADT1-1WT
1
2
3
6
5
4
N.C.
VIN
0.1μF
T1
MINICIRCUITS
ADT1-1WT
0Ω*
0Ω*
5.6pF
5.6pF
2.2μF
INP
COM
INN
110Ω
0.1%
110Ω
0.1%
75Ω
0.5%
75Ω
0.5%
*0Ω RESISTORS CAN BE REPLACED WITH LOW-VALUE
RESISTORS TO LIMIT THE BANDWIDTH.
Figure 11. Transformer-Coupled Input Drive for Input Frequencies Beyond Nyquist
MAX1209
5.6pF
5.6pF
2.2μF
INP
COM
INN
24.9Ω
24.9Ω
100Ω
100Ω
0.1μF
MAX4108
VIN
Figure 12. Single-Ended, AC-Coupled Input Drive
MAX1209
Buffered External Reference
Drives Multiple ADCs
The buffered external reference mode allows for more
control over the MAX1209 reference voltage and allows
multiple converters to use a common reference. The
REFIN input impedance is >50MΩ.
Figure 13 uses the MAX6029EUK21 precision 2.048V
reference as a common reference for multiple convert-
ers. The 2.048V output of the MAX6029 passes through
a one-pole, 10Hz lowpass filter to the MAX4230. The
MAX4230 buffers the 2.048V reference and provides
additional 10Hz lowpass filtering before its output is
applied to the REFIN input of the MAX1209.
12-Bit, 80Msps, 3.3V IF-Sampling ADC
22 ______________________________________________________________________________________
MAX1209
NOTE: ONE FRONT-END REFERENCE
CIRCUIT IS CAPABLE OF SOURCING 15mA
AND SINKING 30mA OF OUTPUT CURRENT.
*PLACE THE 1μF REFP-to-REFN BYPASS CAPACITOR AS CLOSE TO THE DEVICE AS POSSIBLE.
16.2kΩ
0.1μF
0.1μF
1μF
2
5
2.048V
2.048V
+3.3V
1
2
4
1
3
5
47Ω
1.47kΩ
+3.3V
10μF
6V
330μF
6V
+3.3V
2.2μF
2.2μF
0.1μF
1μF* 10μF
0.1μF
0.1μF
0.1μF
REFP
REFN
COM
3
2
1
VDD
GND
REFIN
39
REFOUT
38
MAX1209
+3.3V
2.2μF
2.2μF
0.1μF
1μF* 10μF
0.1μF
0.1μF
0.1μF
REFP
REFN
COM
3
2
1
VDD
GND
REFIN
39
REFOUT
38
MAX6029EUK21
MAX4230
Figure 13. External Buffered Reference Driving Multiple ADCs
Unbuffered External
Reference Drives Multiple ADCs
The unbuffered external reference mode allows for pre-
cise control over the MAX1209 reference and allows
multiple converters to use a common reference.
Connecting REFIN to GND disables the internal refer-
ence, allowing REFP, REFN, and COM to be driven
directly by a set of external reference sources.
Figure 14 uses the MAX6029EUK30 precision 3.000V
reference as a common reference for multiple convert-
ers. A five-component resistive divider chain follows the
MAX6029 voltage reference. The 0.47µF capacitor along
this chain creates a 10Hz lowpass filter. Three MAX4230
operational amplifiers buffer taps along this resistor
MAX1209
12-Bit, 80Msps, 3.3V IF-Sampling ADC
______________________________________________________________________________________ 23
MAX1209
*PLACE THE 1μF REFP-TO-REFN BYPASS CAPACITOR AS CLOSE TO THE DEVICE AS POSSIBLE.
0.1μF
0.1μF
5
2.157V
+3.3V
1
2
2
4
1
3
5
47Ω
1.47kΩ
+3.3V
10μF
6V
330μF
6V
+3.3V
2.2μF
0.1μF
1μF*
10μF
0.1μF
0.1μF
0.1μF
REFOUT
REFN
REFIN 39
1
2
3
VDD
GND
COM
REFP 38
MAX6066
MAX4230
0.1μF
0.47μF
1.649V
2
4
1
3
5
47Ω
1.47kΩ
+3.3V
10μF
6V
330μF
6V
MAX4230
0.1μF
1.141V
2
4
1
3
5
47Ω
1.47kΩ
+3.3V
10μF
6V
330μF
6V
MAX4230
MAX1209
+3.3V
2.2μF
0.1μF
1μF*
10μF
0.1μF
0.1μF
0.1μF
REFOUT
REFN
REFIN 39
1
2
3
VDD
GND
COM
REFP 38
3.000V
24.3kΩ
1%
20kΩ
1%
26.7kΩ
1%
26.7kΩ
1%
20kΩ
1%
20kΩ
1%
20kΩ
1%
2.2μF
2.2μF
Figure 14. External Unbuffered Reference Driving Multiple ADCs
MAX1209
chain providing 2.157V, 1.649V, and 1.141V to the
MAX1209’s REFP, COM, and REFN reference inputs,
respectively. The feedback around the MAX4230 op
amps provides additional 10Hz lowpass filtering. The
2.157V and 1.141V reference voltages set the full-scale
analog input range to ±1.016V.
A common power source for all active components
removes any concern regarding power-supply
sequencing when powering up or down.
Grounding, Bypassing, and
Board Layout
The MAX1209 requires high-speed board layout design
techniques. Refer to the MAX1211 evaluation kit data
sheet for a board layout reference. Locate all bypass
capacitors as close to the device as possible, prefer-
ably on the same side of the board as the ADC, using
surface-mount devices for minimum inductance.
Bypass VDD to GND with a 0.1µF ceramic capacitor in
parallel with a 2.2µF ceramic capacitor. Bypass OVDD
to GND with a 0.1µF ceramic capacitor in parallel with a
2.2µF ceramic capacitor.
Multilayer boards with ample ground and power planes
produce the highest level of signal integrity. All
MAX1209 GNDs and the exposed backside paddle
must be connected to the same ground plane. The
MAX1209 relies on the exposed backside paddle con-
nection for a low-inductance ground connection. Use
multiple vias to connect the top-side ground to the bot-
tom-side ground. Isolate the ground plane from any
noisy digital system ground planes such as a DSP or
output buffer ground.
Route high-speed digital signal traces away from the
sensitive analog traces. Keep all signal lines short and
free of 90°turns.
Ensure that the differential analog input network layout
is symmetric and that all parasitics are balanced equal-
ly. Refer to the MAX1211 evaluation kit data sheet for
an example of symmetric input layout.
Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. For the
MAX1209, this straight line is between the end points of
the transfer function, once offset and gain errors have
been nullified. INL deviations are measured at every
step of the transfer function and the worst-case devia-
tion is reported in the Electrical Characteristics table.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes and a monotonic transfer function. For
the MAX1209, DNL deviations are measured at every
step of the transfer function and the worst-case devia-
tion is reported in the Electrical Characteristics table.
Offset Error
Offset error is a figure of merit that indicates how well
the actual transfer function matches the ideal transfer
function at a single point. Ideally the midscale
MAX1209 transition occurs at 0.5 LSB above midscale.
The offset error is the amount of deviation between the
measured midscale transition point and the ideal mid-
scale transition point.
Gain Error
Gain error is a figure of merit that indicates how well the
slope of the actual transfer function matches the slope
of the ideal transfer function. The slope of the actual
transfer function is measured between two data points:
positive full scale and negative full scale. Ideally, the
positive full-scale MAX1209 transition occurs at 1.5
LSBs below positive full scale, and the negative full-
scale transition occurs at 0.5 LSB above negative full
scale. The gain error is the difference of the measured
transition points minus the difference of the ideal transi-
tion points.
Small-Signal Noise Floor (SSNF)
Small-signal noise floor is the integrated noise and dis-
tortion power in the Nyquist band for small-signal
inputs. The DC offset is excluded from this noise calcu-
lation. For this converter, a small signal is defined as a
single tone with an amplitude less than -35dBFS. This
parameter captures the thermal and quantization noise
characteristics of the converter and can be used to
help calculate the overall noise figure of a receive
channel. Go to www.maxim-ic.com for application
notes on thermal + quantization noise floor.
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantiza-
tion error only and results directly from the ADC’s reso-
lution (N bits):
SNR[max] = 6.02 ×N + 1.76
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
12-Bit, 80Msps, 3.3V IF-Sampling ADC
24 ______________________________________________________________________________________
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise. RMS noise includes all spec-
tral components to the Nyquist frequency excluding the
fundamental, the first six harmonics (HD2–HD7), and
the DC offset.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal
to the RMS noise plus distortion. RMS noise plus distor-
tion includes all spectral components to the Nyquist fre-
quency excluding the fundamental and the DC offset.
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at
a specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. ENOB for
a full-scale sinusoidal input waveform is computed from:
Single-Tone Spurious-Free Dynamic Range
(SFDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS amplitude of the next-largest spurious
component, excluding DC offset.
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first six harmon-
ics of the input signal to the fundamental itself. This is
expressed as:
where V1is the fundamental amplitude, and V2through
V7are the amplitudes of the 2nd- through 7th-order
harmonics (HD2–HD7).
Intermodulation Distortion (IMD)
IMD is the ratio of the RMS sum of the intermodulation
products to the RMS sum of the two fundamental input
tones. This is expressed as:
The fundamental input tone amplitudes (V1and V2) are
at -7dBFS. Fourteen intermodulation products (VIM_)
are used in the MAX1209 IMD calculation. The inter-
modulation products are the amplitudes of the output
spectrum at the following frequencies, where fIN1 and
fIN2 are the fundamental input tone frequencies:
• Second-order intermodulation products:
fIN1 + fIN2, fIN2 - fIN1
• Third-order intermodulation products:
2 x fIN1 - fIN2, 2 x fIN2 - fIN1, 2 x fIN1 + fIN2, 2 x fIN2 + fIN1
• Fourth-order intermodulation products:
3 x fIN1 - fIN2, 3 x fIN2 - fIN1, 3 x fIN1 + fIN2, 3 x fIN2 + fIN1
• Fifth-order intermodulation products:
3 x fIN1 - 2 x fIN2, 3 x fIN2 - 2 x fIN1,
3 x fIN1 + 2 x fIN2, 3 x fIN2 + 2 x fIN1
Third-Order Intermodulation (IM3)
IM3 is the total power of the third-order intermodulation
products to the Nyquist frequency relative to the total
input power of the two input tones fIN1 and fIN2. The
individual input tone levels are at -7dBFS. The third-
order intermodulation products are 2 x fIN1 - fIN2, 2 x
fIN2 - fIN1, 2 x fIN1 + fIN2, 2 x fIN2 + fIN1.
Two-Tone Spurious-Free Dynamic Range
(SFDRTT)
SFDRTT represents the ratio, expressed in decibels, of
the RMS amplitude of either input tone to the RMS
amplitude of the next-largest spurious component in
the spectrum, excluding DC offset. This spurious com-
ponent can occur anywhere in the spectrum up to
Nyquist and is usually an intermodulation product or a
harmonic.
Full-Power Bandwidth
A large -0.5dBFS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by -3dB. This point is defined as full-
power input bandwidth frequency.
In practical laboratory measurements, full-power band-
width is limited by the analog input circuitry and not the
ADC itself. For the MAX1209, the full-power bandwidth is
tested using the MAX1211 evaluation kit input circuitry.
Aperture Delay
The MAX1209 samples data on the falling edge of its
sampling clock. In actuality, there is a small delay
between the falling edge of the sampling clock and the
actual sampling instant. Aperture delay (tAD) is the time
defined between the falling edge of the sampling clock
and the instant when an actual sample is taken (Figure 4).
IMD VV V V
VV
IM IM IM IM
log .......
=× +++ +
+
⎛
⎝
⎜
⎜
⎞
⎠
20 1222132142
1222
THD VVVVVV
V
log
=× +++++
⎛
⎝
⎜
⎜
⎜
⎜
⎞
⎠
⎟
⎟
⎟
⎟
20 2
2
3
2
4
2
5
2
6
2
7
2
1
ENOB SINAD
.
.
=−
⎛
⎝
⎜⎞
⎠
⎟
176
602
MAX1209
12-Bit, 80Msps, 3.3V IF-Sampling ADC
______________________________________________________________________________________ 25
MAX1209
Aperture Jitter
Figure 4 depicts the aperture jitter (tAJ), which is the
sample-to-sample variation in the aperture delay.
Output Noise (nOUT)
The output noise (nOUT) parameter is similar to the ther-
mal + quantization noise parameter and is an indication
of the ADC’s overall noise performance.
No fundamental input tone is used to test for nOUT; INP,
INN, and COM are connected together and 1024k data
points collected. nOUT is computed by taking the RMS
value of the collected data points.
Overdrive Recovery Time
Overdrive recovery time is the time required for the
ADC to recover from an input transient that exceeds the
full-scale limits. The MAX1209 specifies overdrive
recovery time using an input transient that exceeds the
full-scale limits by ±10%.
12-Bit, 80Msps, 3.3V IF-Sampling ADC
26 ______________________________________________________________________________________
REFP 1
REFN 2
COM 3
GND 4
INP 5
INN 6
GND 7
DCE 8
CLKN 9
CLKP 10
D030
D129
D228
D327
D426
D525
D624
D723
D822
D921
40
REFIN
39
REFOUT
38
PD
37
VDD
36
GND
35
OVDD
34
DAV
33
I.C.
32
I.C.
31
CLKTYP
11
VDD
12
VDD
13
VDD
14
VDD
15
GND
16
OVDD
17
DOR
18
D11
19
D10
20
G/T
TOP VIEW
MAX1209
EXPOSED PADDLE (GND)
THIN QFN
6mm x 6mm x 0.8mm
Pin Configuration
MAX1209
12-Bit, 80Msps, 3.3V IF-Sampling ADC
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 27
© 2004 Maxim Integrated Products is a registered trademark of Maxim Integrated Products.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
QFN THIN.EPS