1
Copyright
Cirrus Logic, Inc. 2002
(All Rights Reserved)
Cirrus Logic, Inc.
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
CDB4340A/41A
Evaluation Board for CS4340A and CS4341A
Features
Demonstrates recommended layout and
grounding arrangements
CS8414 Receives AES/EBU, S/PDIF, &
EIAJ-340 Compatible Digital Audio
Digital and Analog Patch Areas
Requires only a digital signal source and
power supplies for a complete Digital-to-
Analog-Converter system
Description
The CDB4340A/41A evaluation board is an excellent
means for quickly evaluating the CS4340A/41A family of
24-bit, stereo D/A converters. Evaluation requires an an-
alog signal analyzer, a digital signal source, a PC for
controlling the CS4341A and a power supply. Analog
outputs are provided via RCA phono jacks for both
channels.
The CS8414 digital audio receiver I.C. provides the sys-
tem timing necessary to operate the Digital-to-Analog
converters and will accept AES/EBU, S/PDIF, and EIAJ-
340 compatible audio data. The evaluation board may
also be configured to accept external timing signals for
operation in a user application during system
development.
ORDERING INFORMATION
CDB4340A, CDB4341A Evaluation Board
Analog
CS4340A/41A
CS8414
Digital
Audio
Interface
I/O for
Clocks
and Data
Filter
Control
Port
Mute
Circuit
JUN ‘02
DS590DB1
CDB4340A/41A
2DS590DB1
TABLE OF CONTENTS
1. CDB4340A/41A SYSTEM OVERVIEW .......................................................... 4
2. CDB4340A/41A ERRATA .............................................................................. 4
3. CS4340A/41A DIGITAL TO ANALOG CONVERTER .................................... 4
4. CS8414 DIGITAL AUDIO RECEIVER ............................................................ 4
5. CS8414 DATA FORMAT ................................................................................ 4
6. ANALOG OUTPUT FILTER ........................................................................... 5
7. INPUT/OUTPUT FOR CLOCKS AND DATA ................................................. 5
8. POWER SUPPLY CIRCUITRY ....................................................................... 5
9. GROUNDING AND POWER SUPPLY DECOUPLING .................................. 5
10. CDB4341A CONTROL PORT SOFTWARE ................................................. 5
LIST OF FIGURES
Figure 1. System Block Diagram and Signal Flow .............................................. 9
Figure 2. CS4340A/41A .................................................................................... 10
Figure 3. Analog Output Passive Filter .............................................................. 11
Figure 4. External Mute Circuit .......................................................................... 12
Figure 5. CS8414 Digital Audio Receiver Connections ..................................... 13
Figure 6. Digital Audio Inputs ............................................................................ 14
Figure 7. MCLK Divider and Voltage Level Converter ...................................... 15
Figure 8. Control Port Interface ......................................................................... 16
Figure 9. Reset Circuitry .................................................................................... 17
Figure 10. Power Supply ................................................................................... 18
Figure 11. I/O for Clocks and Data .................................................................... 19
Figure 12. Silkscreen Top ................................................................................. 20
Figure 13. Top Side ........................................................................................... 21
Figure 14. Bottom Side ...................................................................................... 22
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/sales.cfm
IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product infor-
mation describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the infor-
mation contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty
of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being
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terial and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be
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CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE
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Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade-
marks or service marks of their respective owners.
CDB4340A/41A
DS590DB1 3
LIST OF TABLES
Table 1. CS8414 Supported Formats ................................................................... 4
Table 2. System Connections ............................................................................... 6
Table 3. CDB4340A Jumper Selectable Options .................................................. 6
Table 4. CDB4341A (I2C Mode) Jumper Selectable Options .............................. 7
Table 5. CDB4341A (SPI Mode) Jumper Selectable Options............................... 8
CDB4340A/41A
4DS590DB1
1. CDB4340A/41A SYSTEM OVERVIEW
The CDB4340A/41A evaluation board is an excel-
lent means of quickly evaluating the
CS4340A/41A. The CS8414 digital audio interface
receiver provides an easy interface to digital audio
signal sources including the majority of digital au-
dio test equipment. The evaluation board also al-
lows the user to supply clocks and data through a
10-pin header for system development.
The CDB4340A/41A schematic has been parti-
tioned into 10 schematics shown in Figures 2
through 11. Each partitioned schematic is repre-
sented in the system diagram shown in Figure 1.
Notice that the system diagram also includes
the interconnections between the partitioned sche-
matics.
2. CDB4340A/41A ERRATA
The CS4340A is mounted on the same PCB used to
evaluate the CS4340. Please see tables 3 to 5 for
jumper settings that are not applicable to the
CDB4340A/41A. These jumpers should retain the
default setting from the factory. Also, all SDATA
net names for the CS4340A shall be interpreted as
SDIN,asseeninthepindescriptionofthe
CS4340A datasheet.
3. CS4340A/41A DIGITAL TO ANALOG
CONVERTER
A description of the CS4340A is included in the
CS4340A data sheet. A description of the
CS4341A is included in the CS4341A data sheet.
4. CS8414 DIGITAL AUDIO RECEIVER
The system receives and decodes the standard
S/PDIF data format using a CS8414 Digital Audio
Receiver, Figure 5. The outputs of the CS8414 in-
clude a serial bit clock, serial data, left-right clock
(FSYNC), and a 256 Fs master clock. The opera-
tion of the CS8414 and a discussion of the digital
audio interface are included in the CS8414
Datasheet.
During normal operation, the CS8414 operates in
the Channel Status mode where the LED's display
channel status information for the channel selected
by the CSLR/FCK jumper.
When the Error & Frequency button is enabled, the
CS8414 operates in the Error and Frequency infor-
mation mode. The information displayed by the
LED's can be decoded by consulting the CS8414
data sheet.
Encoded sample frequency information can be dis-
played provided a proper clock is being applied to
the FCK pin of the CS8414. When an LED is lit,
this indicates a "1" on the corresponding pin locat-
ed on the CS8414. When an LED is off, this indi-
cates a "0" on the corresponding pin. Neither the L
or R option of CSLR/FCK should be selected if the
FCK pin is being driven by a clock signal.
5. CS8414 DATA FORMAT
The CS8414 data format can be set with jumpers
M0, M1, M2, and M3, as described the CS8414
datasheet. The format selected must be compatible
with the data format of the CS4340A or CS4341A,
shown in the CS4340A and CS4341A datasheets.
Please note that the CS8414 does not support all the
possible modes of the CS4340A or CS4341A, see
Table 1 for details. The default settings for M0-M3
on the evaluation board are given in Tables 3-5.
CS4341A
Format
CS4340A
Format
CS8414
Format
External
SCLK
Internal
SCLK
0- 2YesYes
10 2YesNo
21 0NoYes
3 2 Unsupported - -
4 - Unsupported - -
53 5YesNo
6- 6YesYes
70 2YesNo
Table 1. CS8414 Supported Formats
CDB4340A/41A
DS590DB1 5
6. ANALOG OUTPUT FILTER
The evaluation board includes a pair of single pole
passive filters. The passive filters, Fig. 3, have a
corner frequency of approximately 95 kHz with
JP3 and JP6 installed and 190 kHz without JP3 and
JP6.
7. INPUT/OUTPUT FOR CLOCKS AND
DATA
The evaluation board has been designed to allow
the interface to external systems via the 10-pin
header, J9. This header allows the evaluation board
to accept externally generated clocks and data. The
schematic for the clock/data I/O is shown in
Figure 11. The 74HC243 transceiver functions as
an I/O buffer where jumpers HDR1-HDR6 deter-
mine if the transceiver operates as a transmitter or
receiver. A transmit function is implemented with
the HDR1-HDR6 jumpers in the 8414 position.
LRCK, SDATA, and SCLK from the CS8414 will
be outputs on J9. The transceiver operates as a re-
ceiver with jumpers HDR1-HDR6 in the EXTER-
NAL position. MCLK, LRCK, SDATA and SCLK
on J9 become inputs.
8. POWER SUPPLY CIRCUITRY
Power is supplied to the evaluation board by three
binding posts (GND, +5V, +3V/+5V) (see
Figure 10). The +5V input supplies power to the
+5 Volt digital circuitry (VA+5, VD+5, VDPC+5),
while the +3V/+5V input supplies power to the
Voltage Level Converter and the CS4340A/41A
for evaluation in either +3 or +5 Volt mode.
9. GROUNDING AND POWER SUPPLY
DECOUPLING
The CS4340A/41A requires careful attention to
power supply and grounding arrangements to opti-
mize performance. Figure 10 details the power dis-
tribution used on this board. The CDB4340A/41A
ground plane is split to control the digital return
currents in order to minimize digital interference.
The decoupling capacitors are located as close to
the CS4340A/41A as possible. Extensive use of
ground plane fill on both the analog and digital sec-
tions of the evaluation board yields large reduc-
tions in radiated noise.
10. CDB4341A CONTROL PORT
SOFTWARE
The CDB4341A is shipped with Windows based
software for interfacing with the CS4341A control
port via the DB25 connector, P1. The software can
be used to communicate with the CS4341A in ei-
ther SPI or I2C mode; however, in SPI mode the
CS4341A registers are write-only.
Run SETUP.EXE from the distribution diskette to
install the software. Further documentation for the
software is available on the distribution diskette.
The documentation is available in the plain text for-
mat file, README.TXT.
CDB4340A/41A
6DS590DB1
Table 2. System Connections
Table 3. CDB4340A Jumper Selectable Options
*Default setting from factory
CONNECTOR INPUT/OUTPUT SIGNAL PRESENT
+5 V input + 5 Volt power
+3V/+5V input + 3 Volt or + 5 Volt power for the CS4340A/41A and the Volt-
age Level Converter
GND input ground connection from power supply
Digital input input digital audio interface input via coax
Optical input input digital audio interface input via optical
J9 input/output I/O for master, serial, left/right clocks and serial data
Parallel Port input/output parallel connection to PC for SPI/I2C control port signals
Control I/O input/output I/O for SPI/I2C control port signals
AOUTA output channel A analog output with single-pole passive filter
AOUTB output channel B analog output with single-pole passive filter
JUMPER PURPOSE POSITION FUNCTION SELECTED
CSLR/FCK Selects channel for CS8414
channel status information
HI
*LO
See CS8414 Datasheet for details
M0
M1
M2
M3
CS8414 mode selection *Low
*High
*Low
*Low
See CS8414 Datasheet for details
SCLK N/A INT
*EXT
N/A
DEM_8414 N/A *8414
DEM
N/A
HDR1-6 Selects source of clocks and
audio data
*8414
EXT
Selects CS8414 as source
Digital I/O header becomes an source
HDR 7 Enables the external mute for
AOUTA
*ON
OFF
Mute Enabled
Mute Disabled
HDR 8 Enables the external mute for
AOUTB
*ON
OFF
Mute Enabled
Mute Disabled
MCLK Selects Single-Speed or Double-
Speed Modes
*x1
÷2
Selects Single-Speed Mode
Selects Double-Speed Mode
HDR15 DIF1 HI
*LOW
See CS4340A Datasheet for details
HDR16 DIF0 HI
*LOW
See CS4340A Datasheet for details
HDR17 DEM0 HI
*LOW
See CS4340A Datasheet for details
ENCTRL Enables/Disables parallel port Enable
*Disable
Invalid for CS4340A
Disables parallel port
CDB4340A/41A
DS590DB1 7
Table 4. CDB4341A (I2C Mode) Jumper Selectable Options
*Default setting from factory
Notes: The CDB4341A evaluation board is shipped from the factory configured for I2C mode.
JUMPER PURPOSE POSITION FUNCTION SELECTED
CSLR/FCK Selects channel for CS8414
channel status information
HI
*LO
See CS8414 Datasheet for details
M0
M1
M2
M3
CS8414 mode selection *Low
*High
*Low
*Low
See CS8414 Datasheet for details
SCLK N/A INT
*EXT
N/A
DEM_8414 N/A *8414
DEM
“Don’t Care” for CS4341A
HDR1-6 Selects source of clocks and
audio data
*8414
EXT
Selects CS8414 as source
Digital I/O header becomes an source
HDR 7 Enables the external mute for
AOUTA
*ON
OFF
Mute Enabled
Mute Disabled
HDR 8 Enables the external mute for
AOUTB
*ON
OFF
Mute Enabled
Mute Disabled
MCLK Selects Single-Speed or Double-
Speed Modes
*x1
÷2
Selects Single-Speed Mode
Selects Double-Speed Mode
HDR15 SCL Pull-Up *HI
LOW
SCL pulled high
Invalid for I2Cmode
HDR16 SDA Pull-Up *HI
LOW
SDA pulled high
Invalid for I2Cmode
HDR17 AD0 HI
*LOW
“Don’t Care” for Control Port Mode
ENCTRL Enables/Disables parallel port *Enable
Disable
Enables parallel port
Disables parallel port (must use HDR14)
CDB4340A/41A
8DS590DB1
Table 5. CDB4341A (SPI Mode) Jumper Selectable Options
*Default setting from factory
Notes: When in SPI mode, it is not possible to read the control registers of the CS4341A. The CDB4341A
evaluation board is shipped from the factory configured for I2C mode.
JUMPER PURPOSE POSITION FUNCTION SELECTED
CSLR/FCK Selects channel for CS8414
channel status information
HI
*LO
See CS8414 Datasheet for details
M0
M1
M2
M3
CS8414 mode selection *Low
*High
*Low
*Low
See CS8414 Datasheet for details
SCLK N/A INT
*EXT
N/A
DEM_8414 N/A *8414
DEM
“Don’t Care” for CS4341A
HDR1-6 Selects source of clocks and
audio data
*8414
EXT
Selects CS8414 as source
Digital I/O header becomes an source
HDR 7 Enables the external mute for
AOUTA
*ON
OFF
Mute Enabled
Mute Disabled
HDR 8 Enables the external mute for
AOUTB
*ON
OFF
Mute Enabled
Mute Disabled
MCLK Selects Single-Speed or Double-
Speed Modes
*x1
÷2
Selects Single-Speed Mode
Selects Double-Speed Mode
HDR15 CCLK Pull-up or Pull-down *HI
LOW
“Don’t Care” for SPI mode
HDR16 CDIN Pull-up or Pull-down *HI
LOW
“Don’t Care” for SPI mode
HDR17 CS Pull-up HI
*LOW
“Don’t Care” for Control Port Mode
ENCTRL Enables/Disables parallel port *Enable
Disable
Enables parallel port
Disables parallel port (must use HDR14)
CDB4340A/41A
DS590DB1 9
Digital
Audio
Input
CS4340A/41A
CS8414
Digital
Audio
Receiver
I/O for
Clocks
and Data
Filter
RXN
RXP
Fig 6
Fig 5
Fig 11
Voltage
Fig 7
Level
Reset
Circuit
MCLK
LRCK
SCLK
SDATA Fig 2 Fig 3
Fig 9
MCLK
LRCK
SCLK
SDATA
Figure 1. System Block Diagram and Signal Flow
External
Fig 4
Passive
Analog
Mute
Fig 8
Control
Port
Converter
Circuit
Connections
Interface
CDB4340A/41A
10 DS590DB1
ARP
X7R
C35
.1UF
R40
200
499
R13
X7R
.1UF
C17
TP5
MUTEC
FERRITE_BEAD
L1
TP4
AGND
R10
499
R39
200
499
R14
R41
49.9
SDATA-A
DEM1/SCLK-A
LRCK-A
MCLK-A
DIF0/SDA/CDIN
10UF
C23
C43
3.3UF
ALP
C44
3.3UF
X7R
C34
.1UF
AGND
VA+3/+5
MUTEC
C21
1UF
C20
1UF
RST
1
2
3
4
5
6
7
8
/RST
SDIN
SCLK
LRCK
MCLK
DIF0
DEM
MUTEC
AOUTA
VA
AGND
AOUTB
DIF1 REF_GND
VQ
FILT+
16
15
14
13
12
11
10
98
7
6
5
4
3
2
1
CS4340A_KS
U7
CS4340A
DIF1/SCL/CCLK-A
DEM0/AD0/CS-A
Figure 2. CS4340A/41A
CDB4340A/41A
DS590DB1 11
B
A
JP6
AGND
AGND
COG
1500PF
C5
COG
1500PF
C22
560
R18
NC
1
2
3
4
J4
CON_RCA_RA
NC
4
3
2
1
CON_RCA_RA
J3
R17 560
AGND
AGND
AOUTLP
AOUTRP
COG
1500PF
C18
COG
1500PF
C6
JP3
R28
10K
R29
10K
AGND
AGND
21
HDR7
HDR1X2
12
HDR8
HDR1X2
MUTEA
ALP
ARP
MUTEB
Figure 3. Analog Output Passive Filter
CDB4340A/41A
12 DS590DB1
AGND
R31 2K
1
3
2
Q2
2SC2878
2
3
1
Q1
2SC2878
R25 2K
AGND
MUTEA MUTEB
AGND
VA+3/+5
MUTEC
3
1
2
MMUN2211LT1
Q4
3
1
2
MMUN2111LT1
Q3
Figure 4. External Mute Circuit
CDB4340A/41A
DS590DB1 13
RXP
RXN
CSLR/FCK
INT/EXT SCLK
VD+5
ERROR & FREQ
SCLK
DEM1/SCLK
8414_DEM
TP10
INT
EXT
DEM
M0
M1
M2
CSLR/FCK
D1
LED_RECT
560
RN3
CSLR/FCK
VCC
GND
7
14
12 13
10 11
89
65
43
21
U8
SN74HC04N
D2
LED_RECT
LED_RECT
D4
LED_RECT
D6
LED_RECT
D5
LED_RECT
D3
VD+5
VERF
CE/F2
SDATA
ERF
M1
M0
VA+
AGND
FILT
MCK
M2
M3
CBL
SEL
U
CS12/FCK
SCK
FSYNC
RXN
RXP
DGND
VD+
/C0/E0
CA/E1
CB/E2
CC/F0
CD/F1
C
28
27
26
25
24
23
22
21
20
19
18
17
16
1514
13
12
11
10
9
8
7
6
5
4
3
2
1
CS8414
U2
1
2
3
HDR2
HDR1X3
LRCK
1
2
3
HDR1X3
HDR1
SDATA
SCLK
1
2
3
HDR1X3
HDR3
10
R11
VD1
1
2
3
HDR4
HDR1X3
1
2
3
HDR5
HDR1X3
MCLK
VA
GND
VD1
GND
GND
GND
S4
SW_B3W_1100
CS8414_M0
CS8414_M1
8414_M
8414
GND
VA+5
C16
.1UF
10UF
C1
X7R
C27 .1UF
X7R
.1UF
C26
1
2
3
HDR1X3
M0
1
2
3
M1
HDR1X3
1
2
3
HDR1X3
M2
1
2
3
M3
HDR1X3
1
2
3
HDR1X3
CSLR/FCK
1
2
3
8414_DEM
HDR1X3
1
2
3
EXT_INT_SCLK
HDR1X3
VA
470
R9
CS8414_M2
X7R
.068UFC33
47.5K
R7
VD1
47.5K
R6
1UF
C32
1UFC31
GND
8414_DEM
Figure 5. CS8414 Digital Audio Receiver Connections
CDB4340A/41A
14 DS590DB1
75
R30
GND
6
5
4
3
2
1
TORX173
OPT1
47UH
L4
VD+5
.01UF
C9
.01UF
C10
RXP
GND
NC
4
3
2
1
J5
CON_RCA_RA
C11
.01UF
RXN
OPTICAL INPUTDIGITAL INPUT
Figure 6. Digital Audio Inputs
CDB4340A/41A
DS590DB1 15
VA+3/+5
AGND
VD+5
VD+5
GND
/SET1
CLOCK1
DATA1
/RST1
/SET2
CLOCK2
DATA2
/RST2
VCC
GND
Q1
/Q1
Q2
/Q2
14
13
12
11
10 9
8
7
6
5
4
3
2
1
MC74HC74AN
U1
MCLK
GND
1
2
3
J20
HDR1X3
VD+5
VD+5
GND
VD+5
VD+5
MCLK
HRM BRM
C15
.1UF
GND
SDATA-A
DEM1/SCLK-A
LRCK-A
MCLK-A
DIF1/SCL/CCLK-A
DEM0/AD0/CS-A
SDATA
DEM1/SCLK
LRCK
DIF1/SCL/CCLK
DEM0/AD0/CS
MCLK-B
.1UF
C14
B8
B7
B6
B5
B4
B3
B2
B1
GND
VCC
A8
A7
A6
A5
A4
A3
A2
A1
DIR
/G
2019
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
SN74VHC245DW
U5
Figure 7. MCLK Divider and Voltage Level Converter
CDB4340A/41A
16 DS590DB1
VDPC+5
DIF0/SDA/CDIN
GND
1
2
3
HDR18
HDR1X3
87
65
43
21
HDR4X2
HDR14
R22 2K
1
2
3
HDR17
HDR1X3
R23 2K
R20 2K
1
2
3
HDR1X3
HDR16
R21 2K
2K
R19
R12 1K
R8 1K
R4 1K
1K
R3
R2 1K
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DB25M_RA
P1
8Q
7Q
8D
7D
GND
VCC
1Q
2Q
3Q
4Q
5Q
6Q6D
5D
4D
3D
2D
1D
CLK
/OC
19
18
17
16
15
14
13
12
20
10
9
8
7
6
5
4
3
2
11
1
SN74HC574N
U3
LATCH
ENCTRL
VDPC+5
C4
.1UF
C7
.1UF
GND
1
2
3
HDR15
HDR1X3
R16 2K
ENCTRL
GND
VDPC+5
PC0
GND
GND
DIF0/SDA/CDIN
VDPC+5
VA+3/+5
DIF1/SCL/CCLK
DEM0/AD0/CS
VDPC+5
LATCH
GND
GND
VCC
7
14
32
1
SN74HCT125N
U6
1112
13
U6
SN74HCT125N
65
4
U6
SN74HCT125N
10
98
SN74HCT125N
U6
DIF1/SCL/CCLK
DEM0/AD0/CS
GND
GND
GND
1K
R5
Figure 8. Control Port Interface
CDB4340A/41A
DS590DB1 17
RST
100
R27
SW_B3W_1100
S1
AGND
AGND
BAT85
D7
VA+3/+5
3.3UF
C29
200K
R1
Figure 9. Reset Circuitry
CDB4340A/41A
18 DS590DB1
GND
+3V/+5V
J6
CON_BANANA
+5V
P6KE6V8P
Z1
VA+5
47UF
C13
C12
47UF
J7
CON_BANANA
AGND
C3 .1UF
C2
47UF
P6KE6V8P
Z2
J1
CON_BANANA
GND
VA+3/+5
C25 .1UF
L3
FB
L2
FB
C8 .1UF
VD+5VDPC+5
GND
10UF
C19
Figure 10. Power Supply
CDB4340A/41A
DS590DB1 19
SDATA
GND
109
87
65
43
21
HDR5X2
J9
SCLK
LRCK
SDATA
VD+5
MCLK
LRCK
SCLK
DIGITAL I/O
GND
MCLK
GND
C24
.1UF
EXTERNAL
CLK SOURCE
GND
VD+5
1
2
3
HDR6
HDR1X3
B4
B3
B2
B1
GND
VCC
A4
A3
A2
A1
GBA
/GAB
14
11
10
9
8
7
6
5
4
3
13
1
74HC243
U4
8414
Figure 11. I/O for Clocks and Data
CDB4340A/41A
20 DS590DB1
Figure 12. Silkscreen Top
CDB4340A/41A
DS590DB1 21
Figure 13. Top Side
CDB4340A/41A
22 DS590DB1
Figure 14. Bottom Side
• Notes •
