November 2001 Rev 1.1 PC87413, PC87414, PC87416, PC87417 LPC ServerI/O for Servers and Workstations General Description (R) The National Semiconductor PC8741x family of LPC ServerI/O devices ("PC8741x") comprises highly integrated Advanced I/O products. The PC8741x is targeted for a wide range of servers and workstations that use the Low Pin Count (LPC) bus for the host interface and the serial ACCESS.bus or SMBus(R) for the embedded controller interface. The PC8741x features an X-Bus extension for read and write operations over the X-Bus for both LPC and ACCESS.bus cycles. Boot Flash and I/O devices can be accessed over this X-Bus. Embedded controllers can access the PC8741x and its X-Bus via the ACCESS.bus or SMBus serial interface when VSB exists, regardless of the LPC bus state. Some of the PC8741x logical devices can be disabled, or their pins can be floated, under control of the VSB-powered serial bus. The PC8741x provides a VSB-powered high-frequency clock for on-chip peripherals and for other VSB-powered platform components. The PC8741x's extended wake-up support complements the chipset's ACPI controller and the platform embedded controllers. The PC8741x can monitor the Power and Sleep buttons and control the power supply of simple platforms that lack an embedded controller. The System Wake-Up Control (SWC) module is powered by VSB and VBAT power supplies. It sup- ports flexible wake-up and power-off request mechanisms in any sleep state. It features Main and Standby power-on elapsed-time counters. The PC8741x also incorporates a Floppy Disk Controller (FDC), two serial ports (UARTs), a Keyboard and Mouse Controller (KBC), a Real-Time Clock (RTC), a fully compliant IEEE 1284 Parallel Port, General-Purpose Input/Output (GPIO) for a total of 51 ports and an Interrupt Serializer for Parallel IRQs. Outstanding Features LPC Interface, based on Intel's LPC Interface Specification, Revision 1.0, September 29th, 1997 VSB-powered access to modules through ACCESS.bus or SMBus (PC87413 and PC87417) X-Bus Extension for memory and I/O (PC87416 and PC87417) PC01 Revision 0.5 and ACPI Revision 1.0b compliant ServerI/O modules: Parallel Port, FDC, two Serial Ports (UARTs) and a Keyboard and Mouse Controller (KBC) Y2K-compliant RTC with 242 bytes of RAM 51 GPIO ports with a variety of wake-up events Extremely low current consumption in Battery Backup mode 128-pin PQFP package Block Diagram PC87417 (See page 5 for other PC8741x diagrams.) Serial Serial Interface Interface ServerI/O Clock VDD Serial Port 1 Serial Port 2 Parallel Port Interface Floppy Drive Interface IEEE 1284 Parallel Port Floppy Disk Controller LPC Serial Keyboard Mouse Interface Interface Interface IRQ Keyboard & Mouse Controller LPC Bus Interface Device Configuration Internal Clocks VBAT VSB Power System On Wake-Up Control Timers Wake-Up Power SCI & Events Control SMI RTC Clock Generator Low-F High-F 32.768 KHz Clock Clock GPIO Ports X-Bus Extension X-Bus XIRQ I/O Ports Interface ACCESS.bus Interface Clock Serial Data National Semiconductor is a registered trademark of National Semiconductor Corporation. All other brand or product names are trademarks or registered trademarks of their respective holders. (c) 2001 National Semiconductor Corporation PC87413, PC87414, PC87416, PC87417 LPC ServerI/O for Servers and Workstations Preliminary Features * Bus Interfaces * -- Compliant with PC01 Specification Revision 0.5, November 2, 1999 -- Plug and Play (PnP) Configuration register structure -- Base Address strap to setup the address of the Index-Data register pair -- Flexible resource allocation for all logical devices: Relocatable base address LPC Bus Interface -- Based on Intel's LPC Interface Specification Revision 1.0, September 29, 1997 -- Synchronous cycles using up to 33 MHz bus clock -- 8-bit I/O and Memory read and write cycles -- Up to four 8-bit DMA channels -- Serial IRQ -- Supports bootable memory -- Reset input -- CLKRUN support -- FWH Transaction support * * ACCESS.bus X-Bus memory device * Programmable through the LPC bus VBAT backed-up -- Concurrent access with the LPC bus -- VSB powered -- Optional internal pull-up on the ACBDAT and ACBCLK pins * X-Bus Extension (PC87416 and PC87417) -- Supports I/O and Memory read/write operations -- 8-bit data bus, 28-bit address -- Multiplexed address-data lines: Four direct address lines * -- Boot configuration selected by straps -- Four chip-select outputs, each supporting multiple zones: Up to 32 MByte BIOS memory zones Up to 32 MByte user-defined memory zones Four user-defined I/O zones Test port and other I/O ports -- -- -- -- -- Optional indirect addressing of memory XRD-XEN or XWR-XR/W mode support Supports both slow and fast devices Accessible from both LPC and ACB buses Programmable protection control over access from the LPC bus and the ACCESS.bus -- VSB powered -- External Interrupt support via XIRQ pin www.national.com Serial Ports 1 and 2 IEEE 1284-compliant Parallel Port Floppy Disk Controller (FDC) -- Programmable write protect -- Supports FM and MFM modes -- Supports Enhanced mode command for three-mode Floppy Disk Drive (FDD) -- Perpendicular recording drive support for 2.88 MB -- Burst and Non-Burst modes -- Full support for IBM Tape Drive Register (TDR) implementation of AT and PS/2 drive types -- 16-byte FIFO -- Error-free handling of data overrun and underrun conditions during DMA transactions (i.e., does not lose data or status bytes and is free of the NEC765A bug) -- Software compatible with the PC8477, which contains a superset of the FDC functions in the DP8473, NEC PD765A/B and N82077 -- High-performance digital separator -- Supports standard 5.25" and 3.5" FDDs Partial non-multiplexed option Up to four optional 8-bit DMA channels -- ECP, with Level 2 (14 mA sink and source output buffers) -- Software or hardware control -- Enhanced Parallel Port (EPP) compatible with EPP 1.7 and EPP 1.9 -- Supports EPP as mode 4 of the Extended Control Register (ECR) -- Selection of internal pull-up or pull-down resistor for Paper End (PE) pin -- Supports a demand DMA mode mechanism and a DMA fairness mechanism for improved bus utilization -- Protection circuit that prevents damage to the parallel port when a printer connected to it powers up or is operated at high voltages, even if the device is in power-down state -- Optional outputs TRI-STATE by external pin -- Slave address: Two values selected by strap -- Software compatible with the 16550A and the 16450 -- Supports shadow register for write-only bit monitoring -- UART data rates up to 1.5 Mbaud -- Proprietary commands for read/write byte from/to: Internal register X-Bus I/O device 15 IRQ routing options to serial IRQ Legacy Modules -- Enables a system controller to access the internal functions and the X-Bus extension -- Supports slave operation compatible with: Intel SMBus -- ACCESS.bus control over pin multiplexing, module disable and output TRI-STATE for all Legacy modules (PC87413 and PC87417) ACCESS.bus (ACB) Interface (PC87413 and PC87417) Configuration Control (via LPC bus) 2 Features (Continued) Power Management -- Supports up to four FDDs -- Supports fast tape drives (2 Mbps) and standard tape drives (1 Mbps, 500 Kbps and 250 Kbps) * Keyboard and Mouse Controller (KBC) -- 8-bit microcontroller, software compatible with 8042AH and PC87911 -- Standard interface (60h, 64h, IRQ1 and IRQ12) -- Supports two external swapable PS/2 interfaces for keyboard and mouse -- Five programmable, dedicated, open-drain I/O lines (Fast GA20/P21, KBRST/P20, P12, P16, P17) * Supports ACPI Specification Revision 1.0b, Feb. 2, 1999 * System Wake-Up Control (SWC) -- Wake-up request on detection of: Preprogrammed Keyboard or Mouse sequence External modem ring from RI1 or RI2 on serial ports Predetermined RTC date and time alarm General-Purpose Input Events from up to 16 GPIO pins IRQs of internal logical devices General-Purpose Modules * General-Purpose I/O (GPIO) Ports -- Optional routing of power-up request to SERIRQ, SIOSMI, SIOSCI, PWBTOUT and ONCTL -- Routing control per input/output event combination -- Outputs enable/disable per event and system state combination (ACPI Sx states) -- Implements bank "b" of the ACPI registers -- Suspend modes via software emulation (control) -- Battery-backed event-logic configuration -- Power button support, featuring: On/Off control -- 51 GPIO Ports: Individually assigned to either LPC or ACB control (PC87413 and PC87417) 46 individually configured as input or output Five output-only -- Programmable features for each output pin: Drive type (open-drain, push-pull or TRI-STATE) TRI-STATE on VDD-fall detection for pins driving VDD-supplied devices -- Programmable option for internal pull-up resistor on each input pin -- Lock option for the configuration and data of each output pin -- 16 GPIO ports generate IRQ/SIOSMI/SIOSCI for wake-up events, with individual: Enable control Polarity and edge/level selection Debounce mechanism * * Real-Time Clock (RTC) Time-of-day alarm Once-per-second to once-per-day Power button output Power Supply On/Off control Enhanced Power Management (PM), including: -- -- -- -- -- DS1287, MC146818 and PC87911 compatible -- 242-byte battery backed-up CMOS RAM in two banks (accessed through 70-71h and 72-73h) -- Selective lock mechanisms for the RTC RAM -- Y2K-compliant calendar, including century and automatic leap-year adjustment -- Time of day in seconds, minutes and hours that allows a 12-hour or 24-hour format with optional adjustment for daylight saving time -- BCD or binary format for timekeeping -- Four individually maskable interrupt event flags: Periodic rates from 122 s to 500 ms Day-of-month alarm -- Supports Legacy- and ACPI-compatible Power button -- Direct power supply control in response to wake-up events -- Programmable Crowbar time-out for On request -- On/Off control via software emulation -- Power-fail recovery -- Low-cost external GPIO port expansion via X-Bus (PC87416 and PC87417) Power-off, 4-second override -- Sleep Button support -- VSB powered * * Special configuration registers for power down Reduced current leakage from pins Low-power CMOS technology Ability to disable all modules Keyboard Events -- Wake-up on any key -- Supports programmable 8-byte sequence "password" for Power Management -- Simultaneous recognition of three programmable keys (sequences): "Power", "Sleep" and "Resume" * Power Active Timers -- Two power-on, elapsed-time counters for the main (VDD) and standby (VSB) power supplies -- 32-bit counters with 1 second LSB -- VBAT backed-up counters -- Double-buffer time registers 3 www.national.com Features (Continued) * -- On-chip low-frequency clock generator: 32.768 KHz for RTC, System Wake-Up Control (SWC), Power Active timers and the high-frequency clock generator WATCHDOG -- WATCHDOG counter reset by: Serial Ports Interrupts Keyboard and Mouse Interrupts Software control -- 8-bit counter with 1 minute LSB -- Generates a 250 ms pulse at WDO pin -- Programmable SIOSMI or SIOSCI events VBAT powered VSB powered -- Clock outputs: LFCKOUT: 32.768 KHz or 1 Hz Strap Input Controlled Operating Modes -- Base Address (BADDR) for the PnP Index-Data register pair -- Input clock presence (CKIN48) select -- X-Bus configuration (XCNF2-0) select (PC87413 and PC87417) -- ACCESS.bus slave address (ACBSA) select (PC87416 and PC87417) -- TRI-STATE device pins (TRIS) * Very low power consumption -- On-chip high-frequency clock generator: Based on the 32.768 KHz clock Clocking, Supply and Package Information * * HFCKOUT: 48 MHz or 40 MHz (or divided) Protection -- All pins are 5V tolerant and back-drive protected (except the LPC bus pins) -- Separate battery pin that includes an internal UL protection resistor -- GPIO multiplexing configuration lock * Clocks Power Supply -- 3.3V supply operation -- Separate pins for main (VDD) and standby (VSB) power supplies -- Backup battery input for RTC, SWC and Power Active timers -- Reduced standby power consumption -- Very low power consumption for RTC and timers (0.9 A typical) from backup battery -- LPC clock input (up to 33 MHz) -- ServerI/O modules clock input: 48 MHz or no clock -- Single 32.768 KHz crystal * Package -- 128-pin PQFP Device-Specific Information The following table shows the main features for each device in the PC8741x family. Function1 PC87413 LPC Bus Interface X-Bus Extension PC87414 YES NO PC87416 YES NO PC87417 YES YES YES YES ACCESS.bus Interface YES General-Purpose Input/Output Ports (GPIO) YES YES YES YES Real Time Clock (RTC) YES YES YES YES System Wake-Up Control (SWC) YES YES YES YES Legacy Functional Blocks YES YES YES YES 1. This datasheet contains notes that are device specific. www.national.com 4 NO NO YES Features (Continued) Block Diagrams These are the block diagrams for the remaining PC8741x devices (see page 1 for the PC87417): PC87413 Serial Serial Interface Interface ServerI/O Clock VDD Serial Port 1 Serial Port 2 Parallel Port Interface Floppy Drive Interface IEEE 1284 Parallel Port Floppy Disk Controller LPC Serial Keyboard Mouse Interface Interface Interface IRQ Keyboard & Mouse Controller LPC Bus Interface Device Configuration Internal Clocks VBAT Power System On Wake-Up Control Timers VSB Wake-Up Power SCI & Events Control SMI RTC Clock Generator Low-F High-F 32.768 KHz Clock Clock GPIO Ports ACCESS.bus Interface I/O Ports Clock Serial Data PC87414 Serial Serial Interface Interface ServerI/O Clock VDD Serial Port 1 Serial Port 2 Parallel Port Interface Floppy Drive Interface IEEE 1284 Parallel Port Floppy Disk Controller LPC Serial Keyboard Mouse Interface Interface Interface IRQ Keyboard & Mouse Controller LPC Bus Interface Device Configuration Internal Clocks VBAT System Wake-Up Control VSB Power On Timers Wake-Up Power SCI & Events Control SMI RTC GPIO Ports Clock Generator Low-F High-F 32.768 KHz Clock Clock I/O Ports PC87416 Serial Serial Interface Interface ServerI/O Clock VDD Serial Port 1 Serial Port 2 Parallel Port Interface Floppy Drive Interface IEEE 1284 Parallel Port Floppy Disk Controller LPC Serial Keyboard Mouse Interface Interface Interface IRQ Keyboard & Mouse Controller LPC Bus Interface Device Configuration Internal Clocks VBAT VSB Power System On Wake-Up Control Timers Wake-Up Power SCI & Events Control SMI RTC Clock Generator Low-F High-F 32.768 KHz Clock Clock 5 GPIO Ports X-Bus Extension X-Bus XIRQ I/O Ports Interface www.national.com Datasheet Revision Record Revision Date July 2000 October 2000 March 2001 Status Comments Preliminary Datasheet First issue - Rev 0.12 Preliminary Datasheet Second issue - Rev 0.13 Preliminary Datasheet Third issue - Rev 1.0 November 2001 Preliminary Datasheet Fourth issue - Rev 1.1 www.national.com 6 Table of Contents 1.0 2.0 3.0 Signal/Pin Connection and Description 1.1 CONNECTION DIAGRAMS ...................................................................................................... 15 1.2 BUFFER TYPES AND SIGNAL/PIN DIRECTORY .................................................................... 19 1.3 PIN MULTIPLEXING ................................................................................................................. 20 1.4 DETAILED SIGNAL/PIN DESCRIPTIONS ................................................................................ 22 1.4.1 LPC Interface .............................................................................................................. 22 1.4.2 ACCESS.bus (ACB) Interface (PC87413 and PC87417) ........................................... 22 1.4.3 X-Bus Extension (PC87416 and PC87417) ................................................................ 22 1.4.4 Serial Port 1 and Serial Port 2 (UART1 and UART2) ................................................. 23 1.4.5 Parallel Port ................................................................................................................ 24 1.4.6 Floppy Disk Controller (FDC) ..................................................................................... 25 1.4.7 Keyboard and Mouse Controller (KBC) ...................................................................... 26 1.4.8 General-Purpose I/O (GPIO) ...................................................................................... 26 1.4.9 System Wake-Up Control (SWC) ............................................................................... 27 1.4.10 Clocks .......................................................................................................................... 28 1.4.11 Configuration Straps ................................................................................................... 28 1.4.12 Power and Ground ...................................................................................................... 29 1.5 INTERNAL PULL-UP AND PULL-DOWN RESISTORS ............................................................ 29 Power, Reset and Clocks 2.1 POWER ..................................................................................................................................... 31 2.1.1 Power Planes .............................................................................................................. 31 2.1.2 Power States ............................................................................................................... 31 2.1.3 Power Connection and Layout Guidelines .................................................................. 32 2.2 RESET SOURCES AND TYPES ............................................................................................... 33 2.2.1 VPP Power-Up Reset ................................................................................................... 33 2.2.2 VSB Power-Up Reset .................................................................................................. 33 2.2.3 Controller Software Reset (PC87413 and PC87417) .................................................. 34 2.2.4 VDD Power-Up Reset .................................................................................................. 34 2.2.5 Hardware Reset ........................................................................................................... 34 2.2.6 Host Software Reset .................................................................................................... 34 2.3 CLOCK GENERATION .............................................................................................................. 35 2.3.1 Clock Domains ............................................................................................................ 35 2.3.2 Clock Generator .......................................................................................................... 35 2.3.3 Low Frequency Clock .................................................................................................. 36 Device Architecture and Configuration 3.1 OVERVIEW ............................................................................................................................... 37 3.2 CONFIGURATION STRUCTURE AND ACCESS ..................................................................... 37 3.2.1 The Index-Data Register Pair ...................................................................................... 37 3.2.2 Banked Logical Device Registers Structure ................................................................ 38 3.2.3 Standard Configuration Register Definitions ............................................................... 39 3.2.4 Standard Configuration Registers ............................................................................... 41 3.2.5 Default Configuration Setup ........................................................................................ 42 3.3 MODULE CONTROL ................................................................................................................. 42 7 www.national.com Table of Contents 3.3.1 3.3.2 (Continued) Module Enable/Disable ................................................................................................ 42 Module Lock by ACCESS.bus (PC87413 and PC87417) ........................................... 43 3.4 INTERNAL ADDRESS DECODING .......................................................................................... 44 3.5 PROTECTION ........................................................................................................................... 45 3.5.1 Multiplexed Pins Configuration Lock ........................................................................... 45 3.5.2 GPIO Ports Configuration Lock ................................................................................... 45 3.5.3 Fast Disable Configuration Lock .................................................................................. 45 3.5.4 Clock Generator Configuration Lock ........................................................................... 45 3.5.5 GPIO Ports Lock .......................................................................................................... 45 3.5.6 X-Bus I/O Map Lock (PC87416 and PC87417) ........................................................... 46 3.5.7 X-Bus Memory Map Lock (PC87416 and PC87417) ................................................... 46 3.5.8 X-Bus Chip Select Configuration Lock (PC87416 and PC87417) ............................... 46 3.5.9 X-Bus Host Protection Lock (PC87416 and PC87417) ............................................... 46 3.5.10 SWC Timers Protection Lock ...................................................................................... 46 3.5.11 SWC Sleep State Configuration Lock .......................................................................... 46 3.5.12 CMOS RAM Access Lock ............................................................................................ 46 3.6 REGISTER TYPE ABBREVIATIONS ........................................................................................ 47 3.7 SERVERI/O CONFIGURATION REGISTERS .......................................................................... 47 3.7.1 ServerI/O ID Register (SID) ......................................................................................... 48 3.7.2 ServerI/O Configuration 1 Register (SIOCF1) ............................................................. 48 3.7.3 ServerI/O Configuration 2 Register (SIOCF2) ............................................................. 49 3.7.4 ServerI/O Configuration 3 Register (SIOCF3) ............................................................. 50 3.7.5 ServerI/O Configuration 4 Register (SIOCF4) ............................................................. 51 3.7.6 ServerI/O Configuration 5 Register (SIOCF5) ............................................................. 52 3.7.7 ServerI/O Configuration 6 Register (SIOCF6) ............................................................. 53 3.7.8 ServerI/O Revision ID Register (SRID) ....................................................................... 54 3.7.9 ServerI/O Configuration 8 Register (SIOCF8) ............................................................. 54 3.7.10 Clock Generator Configuration Register (CLOCKCF) ................................................. 55 3.7.11 ACCESS.bus Configuration (ACBCF) Register ........................................................... 56 3.8 FLOPPY DISK CONTROLLER (FDC) CONFIGURATION ........................................................ 57 3.8.1 General Description ..................................................................................................... 57 3.8.2 Logical Device 0 (FDC) Configuration ......................................................................... 57 3.8.3 FDC Configuration Register ........................................................................................ 58 3.8.4 Drive ID Register ......................................................................................................... 59 3.9 PARALLEL PORT (PP) CONFIGURATION ............................................................................. 60 3.9.1 General Description ..................................................................................................... 60 3.9.2 Logical Device 1 (PP) Configuration ............................................................................ 60 3.9.3 Parallel Port Configuration Register ............................................................................ 61 3.10 SERIAL PORT 2 CONFIGURATION ........................................................................................ 62 3.10.1 General Description ..................................................................................................... 62 3.10.2 Logical Device 2 (SP2) Configuration .......................................................................... 62 3.10.3 Serial Port 2 Configuration Register ............................................................................ 63 3.11 SERIAL PORT 1 CONFIGURATION ........................................................................................ 64 3.11.1 General Description ..................................................................................................... 64 3.11.2 Logical Device 3 (SP1) Configuration .......................................................................... 64 www.national.com 8 Table of Contents 3.11.3 4.0 (Continued) Serial Port 1 Configuration Register ............................................................................ 65 3.12 SYSTEM WAKE-UP CONTROL (SWC) CONFIGURATION .................................................... 66 3.12.1 General Description ..................................................................................................... 66 3.12.2 Logical Device 4 (SWC) Configuration ........................................................................ 66 3.13 KEYBOARD AND MOUSE CONTROLLER (KBC) CONFIGURATION .................................... 67 3.13.1 General Description ..................................................................................................... 67 3.13.2 Logical Devices 5 and 6 (Mouse and Keyboard) Configuration .................................. 67 3.13.3 KBC Configuration Register ........................................................................................ 68 3.14 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS CONFIGURATION ......................... 69 3.14.1 General Description ..................................................................................................... 69 3.14.2 Logical Device 7 (GPIO) Configuration ....................................................................... 70 3.14.3 GPIO Pin Select Register (GPSEL) ............................................................................. 71 3.14.4 GPIO Pin Configuration Register 1 (GPCFG1) ........................................................... 71 3.14.5 GPIO Event Routing Register (GPEVR) ...................................................................... 73 3.14.6 GPIO Pin Configuration Register 2 (GPCFG2) ........................................................... 73 3.15 X-BUS CONFIGURATION ........................................................................................................ 74 3.15.1 Logical Device F (X-Bus) Configuration ...................................................................... 74 3.15.2 X-Bus I/O Range Programming ................................................................................... 74 3.15.3 X-Bus Memory Range Programming ........................................................................... 75 3.15.4 X-Bus I/O Configuration Register (XIOCNF) ............................................................... 77 3.15.5 X-Bus I/O Base Address 1 High Byte Register (XIOBA1H) ......................................... 78 3.15.6 X-Bus I/O Base Address 1 Low Byte Register (XIOBA1L) .......................................... 79 3.15.7 X-Bus I/O Size 1 Configuration Register (XIOSIZE1) .................................................. 79 3.15.8 X-Bus I/O Base Address 2 High Byte Register (XIOBA2H) ......................................... 80 3.15.9 X-Bus I/O Base Address 2 Low Byte Register (XIOBA2L) .......................................... 80 3.15.10 X-Bus I/O Size 2 Configuration Register (XIOSIZE2) ................................................. 81 3.15.11 X-Bus Memory Configuration Register 1 (XMEMCNF1) ............................................ 82 3.15.12 X-Bus Memory Configuration Register 2 (XMEMCNF2) ............................................ 83 3.15.13 X-Bus Memory Base Address High Byte Register (XMEMBAH) ................................ 84 3.15.14 X-Bus Memory Base Address Low Byte Register (XMEMBAL) ................................. 84 3.15.15 X-Bus Memory Size Configuration Register (XMEMSIZE) ......................................... 85 3.15.16 X-Bus IRQ Mapping Register (XIRQMAP) ................................................................. 85 3.16 REAL TIME CLOCK (RTC) CONFIGURATION ....................................................................... 86 3.16.1 General Description ..................................................................................................... 86 3.16.2 Logical Device 10 (RTC) Configuration ....................................................................... 86 3.16.3 RAM Lock Register (RLR) ........................................................................................... 87 3.16.4 Date-of-Month Alarm Register Offset (DOMAO) ......................................................... 88 3.16.5 Month Alarm Register Offset (MONAO) ...................................................................... 88 3.16.6 Century Register Offset (CENO) ................................................................................. 88 LPC Bus Interface 4.1 OVERVIEW ............................................................................................................................... 89 4.2 LPC TRANSACTIONS ............................................................................................................... 89 4.3 CLKRUN FUNCTIONALITY ...................................................................................................... 90 4.4 INTERRUPT SERIALIZER ........................................................................................................ 90 9 www.national.com Table of Contents 5.0 6.0 (Continued) X-Bus Extension 5.1 OVERVIEW ............................................................................................................................... 91 5.2 X-BUS TRANSACTIONS ........................................................................................................... 91 5.2.1 Transaction Clock ........................................................................................................ 92 5.2.2 Programmable Range Chip Select .............................................................................. 92 5.2.3 LPC and FWH Address-to-X-Bus Address Translation ............................................... 92 5.2.4 Indirect Memory Read and Write Transactions ........................................................... 94 5.2.5 Mode 0, Normal Address X-Bus Transactions ............................................................ 94 5.2.6 Mode 0, Normal Address, Fast X-Bus Transactions ................................................... 96 5.2.7 Mode 0, Normal Address, Turbo X-Bus Transactions ................................................. 98 5.2.8 Mode 1, Normal Address Transactions ....................................................................... 99 5.2.9 Latched Address Mode X-Bus Transactions ............................................................. 100 5.3 X-BUS PROTECTION ............................................................................................................. 104 5.4 X-BUS REGISTERS ................................................................................................................ 106 5.4.1 X-Bus Register Map .................................................................................................. 106 5.4.2 X-Bus Configuration Register (XBCNF) .................................................................... 107 5.4.3 X-Bus Select Configuration Registers (XZCNF0 to XZCNF3) ................................... 107 5.4.4 X-Bus IRQ Configuration Register (XIRQC) .............................................................. 109 5.4.5 X-Bus Indirect Memory Address Register 0 (XIMA0) ................................................ 110 5.4.6 X-Bus Indirect Memory Address Register 1 (XIMA1) ................................................ 110 5.4.7 X-Bus Indirect Memory Address Register 2 (XIMA2) ................................................ 111 5.4.8 X-Bus Indirect Memory Address Register 3 (XIMA3) ................................................ 111 5.4.9 X-Bus Indirect Memory Data Register (XIMD) ........................................................... 111 5.4.10 X-Bus Select Mode Register (XZM0 to XZM3) .......................................................... 112 5.4.11 Host Access Protect Register (HAP0 to HAP1) ......................................................... 113 5.5 USAGE HINTS ........................................................................................................................ 114 5.6 X-BUS EXTENSION REGISTER BITMAP ............................................................................. 115 ACCESS.bus Interface 6.1 OVERVIEW ............................................................................................................................. 116 6.2 FUNCTIONAL DESCRIPTION ................................................................................................ 116 6.2.1 Bus Signals ................................................................................................................ 116 6.2.2 Data Transactions ..................................................................................................... 116 6.2.3 Start and Stop Conditions .......................................................................................... 117 6.2.4 Acknowledge (ACK) Cycle ........................................................................................ 117 6.2.5 Acknowledge after Every Byte Rule .......................................................................... 118 6.2.6 Addressing Transfer Formats .................................................................................... 118 6.2.7 Arbitration on the Bus ................................................................................................ 119 6.2.8 Packet Error Check (PEC) ......................................................................................... 119 6.2.9 ACCESS.bus Protocol ............................................................................................... 120 6.2.10 Transaction Execution ............................................................................................... 124 6.3 ACB REGISTERS (ON ACCESS.BUS ONLY) ........................................................................ 125 6.3.1 ACB Register Map (on ACCESS.bus Only) .............................................................. 125 6.3.2 ACCESS.bus Control/Status Register (ACBCST) ..................................................... 126 6.3.3 ACCESS.bus Configuration Register (ACBCFG) ...................................................... 127 www.national.com 10 Table of Contents 6.3.4 6.3.5 6.3.6 6.3.7 6.3.8 6.4 7.0 8.0 (Continued) ACCESS.bus Lock Control Register (ACBLKCTL) ................................................... 127 ACCESS.bus Fast Disable Register (ACBFDIS) ....................................................... 129 ACCESS.bus TRI-STATE Register (ACBTRIS) ........................................................ 130 Access Lock Configuration 1 Register (ACCLCF1) ................................................... 131 Access Lock Configuration 2 Register (ACCLCF2) ................................................... 132 ACB REGISTER BITMAP ........................................................................................................ 133 General-Purpose Input/Output (GPIO) Ports 7.1 OVERVIEW ............................................................................................................................. 134 7.2 BASIC FUNCTIONALITY ........................................................................................................ 135 7.2.1 Configuration Options ................................................................................................ 135 7.2.2 Operation ................................................................................................................... 136 7.3 EVENT HANDLING AND SYSTEM NOTIFICATION .............................................................. 136 7.3.1 Event Configuration ................................................................................................... 136 7.3.2 System Notification .................................................................................................... 137 7.4 GPIO PORT REGISTERS ....................................................................................................... 138 7.4.1 GPIO Pin Configuration Registers Structure ............................................................. 138 7.4.2 GPIO Port Runtime Register Map ............................................................................. 139 7.4.3 GPIO Data Out Register (GPDO) .............................................................................. 139 7.4.4 GPIO Data In Register (GPDI) .................................................................................. 139 7.4.5 GPIO Event Enable Register (GPEVEN) .................................................................. 140 7.4.6 GPIO Event Status Register (GPEVST) .................................................................... 140 Real-Time Clock (RTC) 8.1 OVERVIEW ............................................................................................................................. 141 8.2 FUNCTIONAL DESCRIPTION ................................................................................................ 141 8.2.1 Bus Interface ............................................................................................................. 141 8.2.2 RTC Clock Generation .............................................................................................. 141 8.2.3 Internal Oscillator ....................................................................................................... 141 8.2.4 External Oscillator ..................................................................................................... 142 8.2.5 Timing Generation ..................................................................................................... 143 8.2.6 Timekeeping .............................................................................................................. 143 8.2.7 Updating .................................................................................................................... 144 8.2.8 Alarms ....................................................................................................................... 144 8.2.9 Power Supply ............................................................................................................ 145 8.2.10 System Bus Lockout .................................................................................................. 146 8.2.11 Power-Up Detection .................................................................................................. 146 8.2.12 Oscillator Activity ....................................................................................................... 146 8.2.13 Interrupt Handling ...................................................................................................... 147 8.2.14 Battery-Backed RAMs and Registers ........................................................................ 147 8.3 RTC REGISTERS .................................................................................................................... 148 8.3.1 RTC Configuration Registers Structure ..................................................................... 148 8.3.2 RTC Runtime Register Map ...................................................................................... 149 8.3.3 Seconds Register (SEC) ........................................................................................... 149 8.3.4 Seconds Alarm Register (SECA) ............................................................................... 150 8.3.5 Minutes Register (MIN) .............................................................................................. 150 11 www.national.com Table of Contents 8.3.6 8.3.7 8.3.8 8.3.9 8.3.10 8.3.11 8.3.12 8.3.13 8.3.14 8.3.15 8.3.16 8.3.17 8.3.18 8.3.19 8.3.20 9.0 (Continued) Minutes Alarm Register (MINA) ................................................................................. 150 Hours Register (HOR) ............................................................................................... 151 Hours Alarm Register (HORA) .................................................................................. 151 Day-of-Week Register (DOW) ................................................................................... 151 Date-of-Month Register (DOM) ................................................................................. 152 Month Register (MON) .............................................................................................. 152 Year Register (YER) .................................................................................................. 152 RTC Control Register A (CRA) .................................................................................. 153 RTC Control Register B (CRB) .................................................................................. 155 RTC Control Register C (CRC) ................................................................................. 156 RTC Control Register D (CRD) ................................................................................. 156 Date-of-Month Alarm Register (DOMA) ..................................................................... 157 Month Alarm Register (MONA) .................................................................................. 157 Century Register (CEN) ............................................................................................. 157 BCD and Binary Formats ........................................................................................... 158 8.4 USAGE HINTS ........................................................................................................................ 158 8.5 RTC REGISTER BITMAP ........................................................................................................ 159 8.6 RTC GENERAL-PURPOSE RAM MAP ................................................................................... 159 System Wake-Up Control (SWC) 9.1 OVERVIEW ............................................................................................................................. 160 9.2 FUNCTIONAL DESCRIPTION ................................................................................................ 161 9.2.1 External Events ......................................................................................................... 161 9.2.2 Internal Events ........................................................................................................... 165 9.2.3 Sleep States .............................................................................................................. 166 9.2.4 Interrupt Signals ........................................................................................................ 166 9.2.5 Power Management Signals ...................................................................................... 168 9.2.6 Special Power Management Functions ..................................................................... 170 9.2.7 LED Control ............................................................................................................... 172 9.2.8 Power Active Timers .................................................................................................. 173 9.2.9 WATCHDOG Function .............................................................................................. 173 9.2.10 Miscellaneous Functions ........................................................................................... 173 9.3 SWC REGISTERS ................................................................................................................... 175 9.3.1 SWC Register Map .................................................................................................... 175 9.3.2 Wake-Up Event Select Register (WK_EVT_SEL) ..................................................... 177 9.3.3 Wake-Up State Enable Register (WK_ST_EN) ......................................................... 179 9.3.4 GPE1_STS Events to IRQ Enable Low Register (GPE1_2IRQ_LOW) ..................... 180 9.3.5 GPE1_STS Events to IRQ Enable High Register (GPE1_2IRQ_HIGH) ................... 181 9.3.6 GPE1_STS Events to SMI Enable Low Register (GPE1_2SMI_LOW) ..................... 182 9.3.7 GPE1_STS Events to SMI Enable High Register (GPE1_2SMI_HIGH) ................... 183 9.3.8 SWC Fast Disable Register (SWCFDIS) ................................................................... 184 9.3.9 SWC TRI-STATE Register (SWCTRIS) .................................................................... 185 9.3.10 SWC Miscellaneous Control Register (SWC_CTL) ................................................... 186 9.3.11 Power ON Control Register (PWONCTL) .................................................................. 187 9.3.12 LED Control Register (LEDCTL) ............................................................................... 189 9.3.13 LED Blink Control Register (LEDBLNK) .................................................................... 190 www.national.com 12 Table of Contents 9.3.14 9.3.15 9.3.16 9.3.17 9.3.18 9.3.19 9.3.20 9.3.21 9.3.22 9.3.23 9.3.24 9.3.25 9.3.26 9.3.27 9.3.28 9.3.29 9.3.30 9.3.31 9.3.32 9.3.33 9.3.34 9.3.35 10.0 (Continued) BIOS General-Purpose Scratch Register (BIOSGPR) .............................................. 190 Bank Select Register (BANKSEL) ............................................................................. 191 Keyboard Wake-Up Control Register (KBDWKCTL) ................................................. 192 PS2 Protocol Control Register (PS2CTL) .................................................................. 193 Keyboard Data Shift Register (KDSR) ....................................................................... 194 Mouse Data Shift Register (MDSR) ........................................................................... 194 PS2 Keyboard Key Data 0 to 7 Registers (PS2KEY0 to PS2KEY7) ......................... 194 VDD Active Timer 0 Register (VDD_ON_TMR_0) .................................................... 195 VDD Active Timer 1 Register (VDD_ON_TMR_1) .................................................... 195 VDD Active Timer 2 Register (VDD_ON_TMR_2) .................................................... 195 VDD Active Timer 3 Register (VDD_ON_TMR_3) .................................................... 196 VSB Active Timer 0 Register (VSB_ON_TMR_0) ..................................................... 196 VSB Active Timer 1 Register (VSB_ON_TMR_1) ..................................................... 196 VSB Active Timer 2 Register (VSB_ON_TMR_2) ..................................................... 197 VSB Active Timer 3 Register (VSB_ON_TMR_3) ..................................................... 197 Power Active Timers Control Register (PWTMRCTL) ............................................... 198 S0 to S5 Sleep Type Encoding Registers (S0_SLP_TYP to S5_SLP_TYP) ............. 198 Sleep State Configuration Register (SLP_ST_CFG) ................................................. 199 ACPI Configuration Register (ACPI_CFG) ................................................................ 200 WATCHDOG Control Register (WDCTL) .................................................................. 201 WATCHDOG Time-Out Register (WDTO) ................................................................ 201 WATCHDOG Configuration Register (WDCFG) ....................................................... 202 9.4 ACPI REGISTERS ................................................................................................................... 203 9.4.1 ACPI Register Map .................................................................................................... 203 9.4.2 PM1 Status Low Register (PM1b_STS_LOW) .......................................................... 204 9.4.3 PM1 Status High Register (PM1b_STS_HIGH) ........................................................ 204 9.4.4 PM1 Enable Low Register (PM1b_EN_LOW) ........................................................... 205 9.4.5 PM1 Enable High Register (PM1b_EN_HIGH) ......................................................... 206 9.4.6 PM1 Control Low Register (PM1b_CNT_LOW) ........................................................ 207 9.4.7 PM1 Control High Register (PM1b_CNT_HIGH) ....................................................... 207 9.4.8 General-Purpose Status 1 Register 0 (GPE1_STS_0) .............................................. 208 9.4.9 General-Purpose Status 1 Register 1 (GPE1_STS_1) .............................................. 208 9.4.10 General-Purpose Status 1 Register 2 (GPE1_STS_2) .............................................. 209 9.4.11 General-Purpose Status 1 Register 3 (GPE1_STS_3) .............................................. 210 9.4.12 General-Purpose Enable 1 Register 0 (GPE1_EN_0) ............................................... 212 9.4.13 General-Purpose Enable 1 Register 1 (GPE1_EN_1) ............................................... 212 9.4.14 General-Purpose Enable 1 Register 2 (GPE1_EN_2) ............................................... 213 9.4.15 General-Purpose Enable 1 Register 3 (GPE1_EN_3) ............................................... 214 9.5 SYSTEM WAKE-UP CONTROL REGISTERS BITMAP ......................................................... 215 Legacy Functional Blocks 10.1 FLOPPY DISK CONTROLLER (FDC) .................................................................................... 219 10.1.1 General Description ................................................................................................... 219 10.1.2 FDC Bitmap Summary ............................................................................................... 220 10.2 PARALLEL PORT ................................................................................................................... 221 10.2.1 General Description ................................................................................................... 221 13 www.national.com Table of Contents 10.2.2 10.2.3 11.0 (Continued) Parallel Port Register Map ......................................................................................... 221 Parallel Port Bitmap Summary .................................................................................. 222 10.3 UART FUNCTIONALITY (SP1 AND SP2) .............................................................................. 224 10.3.1 General Description ................................................................................................... 224 10.3.2 UART Mode Register Bank Overview ....................................................................... 224 10.3.3 SP1 and SP2 Register Maps for UART Functionality ................................................ 224 10.3.4 SP1 and SP2 Bitmap Summary for UART Functionality ........................................... 226 10.4 KEYBOARD AND MOUSE CONTROLLER (KBC) ................................................................. 228 10.4.1 General Description ................................................................................................... 228 10.4.2 KBC Register Map ..................................................................................................... 229 10.4.3 KBC Bitmap Summary ............................................................................................... 229 Device Characteristics 11.1 GENERAL DC ELECTRICAL CHARACTERISTICS .............................................................. 230 11.1.1 Recommended Operating Conditions ....................................................................... 230 11.1.2 Absolute Maximum Ratings ....................................................................................... 230 11.1.3 Capacitance .............................................................................................................. 230 11.1.4 Power Consumption under Recommended Operating Conditions ............................ 231 11.1.5 Voltage Thresholds .................................................................................................... 231 11.2 DC CHARACTERISTICS OF PINS, BY I/O BUFFER TYPES ............................................... 232 11.2.1 Input, CMOS Compatible with Schmitt Trigger .......................................................... 232 11.2.2 Input, PCI 3.3V .......................................................................................................... 232 11.2.3 Input, SMBus Compatible .......................................................................................... 232 11.2.4 Input, TTL Compatible ............................................................................................... 233 11.2.5 Input, TTL Compatible with Schmitt Trigger .............................................................. 233 11.2.6 Output, TTL Compatible Push-Pull Buffer ................................................................. 233 11.2.7 Output, Open-Drain Buffer ......................................................................................... 234 11.2.8 Output, PCI 3.3V ....................................................................................................... 234 11.2.9 Exceptions ................................................................................................................. 234 11.3 INTERNAL RESISTORS ........................................................................................................ 235 11.3.1 Pull-Up Resistor ......................................................................................................... 236 11.3.2 Pull-Down Resistor .................................................................................................... 236 11.4 AC ELECTRICAL CHARACTERISTICS ................................................................................. 237 11.4.1 AC Test Conditions .................................................................................................... 237 11.4.2 Reset Timing ............................................................................................................. 238 11.4.3 Clock Timing .............................................................................................................. 240 11.4.4 LPC Interface Timing ................................................................................................ 242 11.4.5 X-Bus Extension Timing (PC87416 and PC87417) ................................................. 244 11.4.6 ACCESS.bus Timing (PC87413 and PC87417) ........................................................ 245 11.4.7 FDC Timing ............................................................................................................... 247 11.4.8 Parallel Port Timing ................................................................................................... 249 11.4.9 Serial Ports 1 and 2 Timing ...................................................................................... 251 11.4.10 SWC Timing ............................................................................................................. 252 www.national.com 14 1.0 Signal/Pin Connection and Description 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 STEP WDATA WGATE TRK0 WP RDATA HDSEL DSKCHG GPIO55/CLKIN GPO64/WDO/CKIN48 GPIO54/VDDFELL GPIOE47/SLPS5 GPIOE46/SLPS3 GPIOE45/LED2 GPIOE44/LED1 GPIOE43/PWBTOUT GPO63/ACBSA ACBCLK ACBDAT GPIO53/LFCKOUT/MSEN0 32KX2 VSS 32KX1_32KCLKIN VBAT VSB ONCTL 1.1 CONNECTION DIAGRAMS MTR0 INDEX DRATE0 DENSEL SLCT PE BUSY_WAIT ACK PD7 PD6 PD5 PD4 PD3 SLIN_ASTRB PD2 INIT PD1 ERR PD0 AFD_DSTRB STB_WRITE VDD 38 37 36 35 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 34 33 32 PC87413-xxx/VLA 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GPIO52/SIOSCI GPIO51/SIOSMI GPIO50/PWBTIN GPIOE42/SLBTIN GPO62 GPO61 GPO60 GPIO37 GPIO36 GPIO35 GPIO34 GPIO33 GPIO32 GPIO31 GPIO30 GPIO27 GPIO26 GPIOE41 GPIOE40 GPIO25 GPIO24 GPIO23 GPIO22 GPIO21 GPIO20 GPIO07/HFCKOUT VSB VSS GPIO06 GPIO05 GPIOE17 GPIOE16 GPIOE15 GPIOE14 GPIOE13 GPIOE12 GPIOE11 GPIOE10 DSR2 SIN2 RTS2 SOUT2 CTS2 DTR2_BOUT2 RI2 LAD3 LAD2 LAD1 LAD0 LCLK VSS VDD LFRAME LDRQ SERIRQ LRESET P12/PPDIS KBRST GA20 GPIO00/CLKRUN GPIO01/KBCLK GPIO02/KBDAT GPIO03/MCLK GPIO04/MDAT VSS DCD1 DSR1 SIN1 RTS1/TRIS SOUT1 CTS1 DTR1_BOUT1/BADDR RI1 DCD2 65 66 67 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 DIR MTR1/P17 DR0 VSS VDD DR1/P16 Plastic Quad Flatpack (PQFP), JEDEC Order Number PC87413-xxx/VLA See NS Package Number VLA128A xxx = Three-character identifier for National data, keyboard ROM and/or customer identification code. 15 www.national.com (Continued) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 STEP WDATA WGATE TRK0 WP RDATA HDSEL DSKCHG GPIO55/CLKIN GPO64/WDO/CKIN48 GPIO54/VDDFELL GPIOE47/SLPS5 GPIOE46/SLPS3 GPIOE45/LED2 GPIOE44/LED1 GPIOE43/PWBTOUT GPO63 NC NC GPIO53/LFCKOUT/MSEN0 32KX2 VSS 32KX1_32KCLKIN VBAT VSB ONCTL 1.0 Signal/Pin Connection and Description MTR0 INDEX DRATE0 DENSEL SLCT PE BUSY_WAIT ACK PD7 PD6 PD5 PD4 PD3 SLIN_ASTRB PD2 INIT PD1 ERR PD0 AFD_DSTRB STB_WRITE VDD 38 37 36 35 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 34 33 32 PC87414-xxx/VLA 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GPIO52/SIOSCI GPIO51/SIOSMI GPIO50/PWBTIN GPIOE42/SLBTIN GPO62 GPO61 GPO60 GPIO37 GPIO36 GPIO35 GPIO34 GPIO33 GPIO32 GPIO31 GPIO30 GPIO27 GPIO26 GPIOE41 GPIOE40 GPIO25 GPIO24 GPIO23 GPIO22 GPIO21 GPIO20 GPIO07/HFCKOUT VSB VSS GPIO06 GPIO05 GPIOE17 GPIOE16 GPIOE15 GPIOE14 GPIOE13 GPIOE12 GPIOE11 GPIOE10 DSR2 SIN2 RTS2 SOUT2 CTS2 DTR2_BOUT2 RI2 LAD3 LAD2 LAD1 LAD0 LCLK VSS VDD LFRAME LDRQ SERIRQ LRESET P12/PPDIS KBRST GA20 GPIO00/CLKRUN GPIO01/KBCLK GPIO02/KBDAT GPIO03/MCLK GPIO04/MDAT VSS DCD1 DSR1 SIN1 RTS1/TRIS SOUT1 CTS1 DTR1_BOUT1/BADDR RI1 DCD2 65 66 67 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 DIR MTR1/P17 DR0 VSS VDD DR1/P16 NC - Not Connected (these pins should be left unconnected) Plastic Quad Flatpack (PQFP), JEDEC Order Number PC87414-xxx/VLA See NS Package Number VLA128A xxx = Three-character identifier for National data, keyboard ROM and/or customer identification code. www.national.com 16 (Continued) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 STEP WDATA WGATE TRK0 WP RDATA HDSEL DSKCHG GPIO55/CLKIN GPO64/WDO/CKIN48 GPIO54/VDDFELL GPIOE47/SLPS5 GPIOE46/SLPS3 GPIOE45/LED2 GPIOE44/LED1 GPIOE43/PWBTOUT GPO63 NC NC GPIO53/LFCKOUT/MSEN0 32KX2 VSS 32KX1_32KCLKIN VBAT VSB ONCTL 1.0 Signal/Pin Connection and Description MTR0 INDEX DRATE0 DENSEL SLCT PE BUSY_WAIT ACK PD7 PD6 PD5 PD4 PD3 SLIN_ASTRB PD2 INIT PD1 ERR PD0 AFD_DSTRB STB_WRITE VDD 38 37 36 35 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 34 33 32 PC87416-xxx/VLA 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GPIO52/SIOSCI GPIO51/SIOSMI GPIO50/PWBTIN GPIOE42/SLBTIN GPO62/XSTB0/XCNF0 GPO61/XSTB1/XCNF1 GPO60/XSTB2/XCNF2 GPIO37/XD0 GPIO36/XD1 GPIO35/XD2 GPIO34/XD3 GPIO33/XD4 GPIO32/XD5 GPIO31/XD6 GPIO30/XD7 GPIO27/XCS0 GPIO26/XCS1 GPIOE41/XCS2 GPIOE40/XCS3 GPIO25/XA0 GPIO24/XA1 GPIO23/XA2 GPIO22/XA3 GPIO21/XWR_XRW GPIO20/XRD_XEN GPIO07/HFCKOUT VSB VSS GPIO06/XIRQ GPIO05/XRDY GPIOE17/XA4 GPIOE16/XA5 GPIOE15/XA6 GPIOE14/XA7 GPIOE13/XA8 GPIOE12/XA9 GPIOE11/XA10 GPIOE10/XA11 DSR2 SIN2 RTS2 SOUT2 CTS2 DTR2_BOUT2 RI2 LAD3 LAD2 LAD1 LAD0 LCLK VSS VDD LFRAME LDRQ SERIRQ LRESET P12/PPDIS KBRST GA20 GPIO00/CLKRUN GPIO01/KBCLK GPIO02/KBDAT GPIO03/MCLK GPIO04/MDAT VSS DCD1 DSR1 SIN1 RTS1/TRIS SOUT1 CTS1 DTR1_BOUT1/BADDR RI1 DCD2 65 66 67 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 DIR MTR1/P17 DR0 VSS VDD DR1/P16 NC - Not Connected (these pins should be left unconnected) Plastic Quad Flatpack (PQFP), JEDEC Order Number PC87416-xxx/VLA See NS Package Number VLA128A xxx = Three-character identifier for National data, keyboard ROM and/or customer identification code. 17 www.national.com (Continued) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 STEP WDATA WGATE TRK0 WP RDATA HDSEL DSKCHG GPIO55/CLKIN GPO64/WDO/CKIN48 GPIO54/VDDFELL GPIOE47/SLPS5 GPIOE46/SLPS3 GPIOE45/LED2 GPIOE44/LED1 GPIOE43/PWBTOUT GPO63/ACBSA ACBCLK ACBDAT GPIO53/LFCKOUT/MSEN0 32KX2 VSS 32KX1_32KCLKIN VBAT VSB ONCTL 1.0 Signal/Pin Connection and Description MTR0 INDEX DRATE0 DENSEL SLCT PE BUSY_WAIT ACK PD7 PD6 PD5 PD4 PD3 SLIN_ASTRB PD2 INIT PD1 ERR PD0 AFD_DSTRB STB_WRITE VDD 38 37 36 35 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 34 33 32 PC87417-xxx/VLA 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GPIO52/SIOSCI GPIO51/SIOSMI GPIO50/PWBTIN GPIOE42/SLBTIN GPO62/XSTB0/XCNF0 GPO61/XSTB1/XCNF1 GPO60/XSTB2/XCNF2 GPIO37/XD0 GPIO36/XD1 GPIO35/XD2 GPIO34/XD3 GPIO33/XD4 GPIO32/XD5 GPIO31/XD6 GPIO30/XD7 GPIO27/XCS0 GPIO26/XCS1 GPIOE41/XCS2 GPIOE40/XCS3 GPIO25/XA0 GPIO24/XA1 GPIO23/XA2 GPIO22/XA3 GPIO21/XWR_XRW GPIO20/XRD_XEN GPIO07/HFCKOUT VSB VSS GPIO06/XIRQ GPIO05/XRDY GPIOE17/XA4 GPIOE16/XA5 GPIOE15/XA6 GPIOE14/XA7 GPIOE13/XA8 GPIOE12/XA9 GPIOE11/XA10 GPIOE10/XA11 DSR2 SIN2 RTS2 SOUT2 CTS2 DTR2_BOUT2 RI2 LAD3 LAD2 LAD1 LAD0 LCLK VSS VDD LFRAME LDRQ SERIRQ LRESET P12/PPDIS KBRST GA20 GPIO00/CLKRUN GPIO01/KBCLK GPIO02/KBDAT GPIO03/MCLK GPIO04/MDAT VSS DCD1 DSR1 SIN1 RTS1/TRIS SOUT1 CTS1 DTR1_BOUT1/BADDR RI1 DCD2 65 66 67 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 DIR MTR1/P17 DR0 VSS VDD DR1/P16 Plastic Quad Flatpack (PQFP), JEDEC Order Number PC87417-xxx/VLA See NS Package Number VLA128A xxx = Three-character identifier for National data, keyboard ROM and/or customer identification code. www.national.com 18 1.0 Signal/Pin Connection and Description (Continued) 1.2 BUFFER TYPES AND SIGNAL/PIN DIRECTORY The signal DC characteristics of the pins described in Section 1.4 are denoted by buffer type symbols, which are defined in Table 1 and described in further detail in Section 11.2. The pin multiplexing information refers to two different types of multiplexing: Multiplexed, denoted by a slash (/) between pins in the diagrams in Section 1.1. Pins are shared between two different functions. Each function is associated with different board connectivity. Normally, the function selection is determined by the board design and cannot be changed dynamically. The multiplexing options must be configured by the BIOS upon power-up in order to comply with the board implementation. Multiple Mode, denoted by an underscore (_) between pins in the diagrams in Section 1.1. Pins have two or more modes of operation within the same function. These modes are associated with the same external (board) connectivity. Mode selection may be controlled by the device driver through the registers of the functional block and do not require a special BIOS setup upon power-up. These pins are not considered multiplexed pins from the ServerI/O configuration perspective. The mode selection method (registers and bits), as well as the signal specification in each mode, are described within the functional description of the relevant functional block. Table 1. Buffer Types Symbol Description INCS Input, CMOS compatible, with Schmitt Trigger INOSC Input, from crystal oscillator (not characterized) INPCI Input, PCI 3.3V INSM Input, ACCESS.bus and SMBus compatible INT Input, TTL compatible INTS Input, TTL compatible, with Schmitt Trigger INULR Input, power, resistor protected (not characterized) Op/n Output, push-pull output buffer capable of sourcing p mA and sinking n mA ODn Output, open-drain output buffer capable of sinking n mA OOSC Output, to crystal oscillator (not characterized) OPCI Output, PCI 3.3V PWR Power pin GND Ground pin 19 www.national.com 1.0 Signal/Pin Connection and Description (Continued) 1.3 PIN MULTIPLEXING The table below shows only multiplexed pins, their associated functional blocks and the configuration bits for the selection of the multiplexed options used in the PC8741x. Some PC8741x devices implement a subset of these signals. Refer to Device-Specific Information on page 4 to identify the functions relevant to a specific device. Table 2. Pin Multiplexing Configuration Pin Functional Block Signal Functional Block Signal Functional Strap/Wake-up Configuration Select Block 1 GPIOE10 XA11 GPIOE10 2 GPIOE11 XA10 GPIOE11 3 GPIOE12 XA9 GPIOE12 4 GPIOE13 XA8 GPIOE13 SWC 5 GPIOE14 6 SIOCF4.NOADDIR XA7 GPIOE14 GPIOE15 XA6 GPIOE15 7 GPIOE16 XA5 GPIOE16 8 GPIOE17 XA4 GPIOE17 9 GPIO05 XRDY SIOCF4.XRDYMUX 10 GPIO06 XIRQ SIOCF5.XIRQMUX 13 GPIO07 HFCKOUT SIOCF4.HFCKMUX 14 GPIO20 XRD_XEN 15 GPIO21 XWR_XRW 16 GPIO22 XA3 17 GPIO23 XA2 GPIO24 XA1 19 GPIO25 XA0 22 GPIO26 XCS1 SIOCF5.XCS1MUX 23 GPIO27 XCS0 SIOCF5.XCS0MUX 20 GPIOE40 XCS3 X-Bus CLKGEN SIOCF4.NOXBUS 18 GPIO GPIOE40 SIOCF5.XCS3MUX GPIOE41 SIOCF5.XCS2MUX SWC XCS2 21 GPIOE41 24 GPIO30 25 GPIO31 XD6 26 GPIO32 XD5 27 GPIO33 XD4 28 GPIO34 XD3 29 GPIO35 XD2 30 GPIO36 XD1 31 GPIO37 XD0 32 GPO60 XSTB2 33 GPO61 XSTB1 34 GPO62 XSTB0 X-Bus XD7 SIOCF4.NOXBUS www.national.com Straps 20 XCNF2 SIOCF5.XSTB2MUX XCNF1 SIOCF5.XSTB1MUX XCNF0 SIOCF5.XSTB0MUX 1.0 Signal/Pin Connection and Description (Continued) Table 2. Pin Multiplexing Configuration (Continued) Pin Functional Block Signal 35 GPIOE42 36 GPIO50 Functional Block Signal SLBTIN Functional Strap/Wake-up Configuration Select Block SWC GPIOE42 SIOCF3.SLBTIMUX PWBTIN SIOCF3.PWBTIMUX SWC 37 GPIO51 SIOSMI SIOCF3.SMIMUX 38 GPIO52 SIOSCI SIOCF3.SCIMUX 45 GPIO53 48 49 CLKGEN LFCKOUT FDC MSEN0 SIOCF4.LFCKMUX GPO63 Straps ACBSA GPIOE43 PWBTOUT GPIOE43 SIOCF3.PWBTOMUX 50 GPIOE44 LED1 GPIOE44 SIOCF3.LED1MUX 51 GPIOE45 LED2 GPIOE45 SIOCF3.LED2MUX 52 GPIOE46 SLPS3 GPIOE46 SIOCF3.EXTSTMUX 53 GPIOE47 SLPS5 GPIOE47 SIOCF3.EXTSTMUX 54 GPIO54 VDDFELL 55 GPO64 WDO 56 GPIO55 GPIO SWC CLKGEN MTR1 66 SWC SIOCF2.VDDFLMUX Straps CKIN48 SIOCF2.WDOMUX CLKIN CLOCKCF.CKIN48 P17 SIOCF2.P17MUX P16 SIOCF2.P16MUX KBC FDC 70 DR1 97 RTS1 TRIS Straps 100 Serial Port 1 DTR1_BOUT1 101 BADDR RI1 RI1 SWC 109 Serial Port 2 RI2 RI2 121 Parallel Port PPDIS KBC P12 SIOCF2.P12MUX 124 GPIO00 LPC I/F CLKRUN SIOCF2.CLKRNMUX 125 GPIO01 126 GPIO GPIO02 KBCLK KBCLK KBDAT KBDAT KBC SWC SIOCF2.NOKBC 127 GPIO03 MCLK MCLK 128 GPIO04 MDAT MDAT 21 www.national.com 1.0 Signal/Pin Connection and Description (Continued) 1.4 DETAILED SIGNAL/PIN DESCRIPTIONS This section describes all the signals of the PC8741x devices. Some PC8741x devices implement a subset of these signals. Refer to Device-Specific Information on page 4 to identify the functions relevant to a specific device. Device signals are organized by functional group. 1.4.1 LPC Interface Signal Pin(s) I/O Buffer Type Power Well Description LAD3-0 110-113 I/O INPCI/OPCI VDD LPC Address-Data. Multiplexed command, address bi-directional data and cycle status. LCLK 114 I INPCI VDD LPC Clock. Derived from the PCI clock (up to 33 MHz). LFRAME 117 I INPCI VDD LPC Frame. Low pulse indicates the beginning of a new LPC cycle or termination of a broken cycle. LDRQ 118 O OPCI VDD LPC DMA Request. Encoded DMA request for LPC Interface. LRESET 120 I INPCI VDD LPC Reset. Derived from the PCI system reset. SERIRQ 119 I/O INPCI/OPCI VDD Serial IRQ. The interrupt requests are serialized over a single pin, where each IRQ level is delivered during a designated time slot. CLKRUN 124 I/OD INPCI/OD6 VDD Clock Run. Indicates that LCLK is going to be stopped and requests full-speed LCLK (same behavior as PCI CLKRUN). 1.4.2 ACCESS.bus (ACB) Interface (PC87413 and PC87417) Signal Pin(s) I/O Buffer Type Power Well Description ACBCLK 47 I/O INSM/OD6 VSB ACCESS.bus Clock. An internal pull-up for this pin is optional. ACBDAT 46 I/O INSM/OD6 VSB ACCESS.bus Serial Data. An internal pull-up for this pin is optional. 1.4.3 X-Bus Extension (PC87416 and PC87417) Signal XRD_XEN Pin/s I/O Buffer Type Power Well Description 14 O O3/6 VSB Read. Active (low) level indicates read cycle on the X-Bus. Enable. Active (high) level indicates valid data on the X-Bus. XWR_XRW 15 O O3/6 VSB Write. Active (low) level indicates a write cycle on the X-Bus. Read/Write. A high level indicates a read cycle on the X-Bus; a low level indicates a write cycle on the X-Bus. XD7-0 24-31 I/O INTS/O3/6 VSB Data Bus. 8-bit data multiplexed with the address lines XA27-4. XA11-4, XA3-0 1-8 16-19 O O3/6 VSB Address Bus. The XA27-12 address lines are always multiplexed with the data lines. XSTB2-0 32-34 O O3/6 VSB Address Strobes. Control the strobe of up to three external latches for the multiplexed address lines. XCS3-0 20-23 O O3/6 VSB Chip Selects. Control the selection of up to four devices residing on the X-Bus. XRDY 9 I INTS VSB I/O Ready. Instructs the PC8741x to extend the access cycle. XIRQ 10 I INTS VSB X-Bus Interrupt. Converted into serial interrupt by the Interrupt Serializer. The system configuration includes the interrupt number associated with this signal. www.national.com 22 1.0 Signal/Pin Connection and Description 1.4.4 (Continued) Serial Port 1 and Serial Port 2 (UART1 and UART2) Signal Pin/s I/O Buffer Type Power Well Description CTS1 CTS2 99 107 I INTS VDD Clear to Send. When low, indicates that the modem or other data transfer device is ready to exchange data. DCD1 DCD2 94 102 I INTS VDD Data Carrier Detected. When low, indicates that the modem or other data transfer device has detected the data carrier. DSR1 DSR2 95 103 I INTS VDD Data Set Ready. When low, indicates that the data transfer device, e.g., modem, is ready to establish a communications link. DTR1_ BOUT1 100 O O3/6 VDD DTR2_ BOUT2 108 Data Terminal Ready. When low, indicates to the modem or other data transfer device that the UART is ready to establish a communications link. After a system reset, these pins provide the DTR function and set these signals to inactive high. Loopback operation holds them inactive. Baud Output. Provides the associated serial channel baud rate generator output signal if Test mode is selected, i.e., bit 7 of the EXCR1 register is set. RI1 RI2 101 109 I INTS VDD Ring Indicator. When low, indicates that a telephone ring signal has been received by the modem. These pins are monitored during VDD power-off for wake-up event detection. RTS1 RTS2 97 105 O O3/6 VDD Request to Send. When low, indicates to the modem or other data transfer device that the corresponding UART is ready to exchange data. A system reset sets these signals to inactive high, and loopback operation holds them inactive. SIN1 SIN2 96 104 I INTS VDD Serial Input. Receives composite serial data from the communications link (peripheral device, modem or other data transfer device). SOUT1 SOUT2 98 106 O O3/6 VDD Serial Output. Sends composite serial data to the communications link (peripheral device, modem or other data transfer device). These signals are set active high after a system reset. 23 www.national.com 1.0 Signal/Pin Connection and Description 1.4.5 (Continued) Parallel Port Signal ACK Pin/s I/O Buffer Type Power Well Description 78 I INT VDD Acknowledge. Pulsed low by the printer to indicate that it has received data from the parallel port. AFD_DSTRB 90 O OD14, O14/14 VDD AFD - Automatic Feed. When low, instructs the printer to automatically feed a line after printing each line. This pin is in TRI-STATE after a 0 is loaded into the corresponding control register bit. An external 4.7 K pull-up resistor must be connected to this pin. DSTRB - Data Strobe (EPP). Active low, used in EPP mode to denote a data cycle. When the cycle is aborted, DSTRB becomes inactive (high). BUSY_WAIT 77 I INT VDD Busy. Set high by the printer when it cannot accept another character. Wait. In EPP mode, the parallel port device uses this active low signal to extend its access cycle. ERR 88 I INT VDD Error. Set active low by the printer when it detects an error. INIT 86 O OD14, O14/14 VDD Initialize. When low, initializes the printer. This signal is in TRI-STATE after a 1 is loaded into the corresponding control register bit. An external 4.7 K pull-up resistor must be connected to this pin. PD7-3 PD2 PD1 PD0 79-83 85 87 89 I/O INT/O14/14 VDD Parallel Port Data. Transfers data to and from the peripheral data bus and the appropriate parallel port data register. These signals have a high current drive capability. PE 76 I INT VDD Paper End. Set high by the printer when it is out of paper. This pin has an internal weak pull-up or pull-down resistor. SLCT 75 I INT VDD Select. Set active high by the printer when the printer is selected. SLIN_ASTRB 84 O OD14, O14/14 VDD SLIN - Select Input. When low, selects the printer. This signal is in TRI-STATE after a 0 is loaded into the corresponding control register bit. An external 4.7 K pull-up resistor must be connected to this pin. ASTRB - Address Strobe (EPP). Active low, used in EPP mode to denote an address or data cycle. When the cycle is aborted, ASTRB becomes inactive (high). STB_WRITE 91 O OD14, O14/14 VDD STB - Data Strobe. When low, Indicates to the printer that valid data is available at the printer port. This signal is in TRI-STATE after a 0 is loaded into the corresponding control register bit. An external 4.7 K pull-up resistor must be connected to this pin. WRITE - Write Strobe. Active low, used in EPP mode to denote an address or data cycle. When the cycle is aborted, WRITE becomes inactive (high). PPDIS I INT VDD Parallel Port Disable. When high, this input disables (TRISTATEs) all the output signals of the parallel port.1 121 1. If this feature is not used, either select the alternate function (P12 port) at the pin multiplexer (see Section 3.7.3 on page 49) or connect an external 3.3 K pull-down resistor to this pin. If the function connected to the pin is PPDIS and the pin is left unconnected, the output signals of the parallel port will float. www.national.com 24 1.0 Signal/Pin Connection and Description 1.4.6 (Continued) Floppy Disk Controller (FDC) Signal Pin(s) I/O Buffer Type Power Well Description DENSEL 74 O O2/12 VDD Density Select. Indicates that a high FDC density data rate (500 Kbps, 1 Mbps or 2 Mbps) or a low density data rate (250 or 300 Kbps) is selected. DIR 65 O OD12, O2/12 VDD Direction. Determines the direction of the Floppy Disk Drive (FDD) head movement (active = step in; inactive = step out) during a seek operation. DR1 70 O OD12, O2/12 VDD DR0 67 Drive Select. Decoded output signals in Two-Drive mode or encoded signals in Four-Drive mode. Controlled by bits 1 and 0 of the Digital Output Register (DOR). DRATE0 73 O O3/6 VDD Data Rate. Reflects the value of bit 0 of the Configuration Control Register (CCR) or the Data Rate Select Register (DSR), whichever was written to last. DSKCHG 57 I INT VDD Disk Change. Indicates if the drive door has been opened. HDSEL 58 O OD12, O2/12 VDD Head Select. Determines which side of the FDD is accessed. Active low selects side 1; inactive selects side 0. INDEX 72 I INT VDD Index. Indicates the beginning of an FDD track. MSEN0 45 I INT VDD Automatic Media Sense. Identifies the media type of the floppy disk in drives 1 and 0 (if the drives support this protocol). MTR1 66 O OD12, O2/12 VDD MTR0 71 Motor Select. Active low, motor enable lines for drives 1 and 0, controlled by bits D7-4 of the Digital Output Register (DOR). MTR0 is used to decode DR1 and DR0 in Four-Drive mode. RDATA 59 I INT VDD Read Data. Raw serial input data stream read from the FDD. STEP 64 O OD12, O2/12 VDD Step. Issues pulses to the disk drive at a software programmable rate to move the head during a seek operation. TRK0 61 I INT VDD Track 0. Indicates to the controller that the head of the selected floppy disk drive is at track 0. WDATA 63 O OD12, O2/12 VDD Write Data. Carries out the pre-compensated serial data that is written to the FDD. Pre-compensation is software selectable. WGATE 62 O OD12, O2/12 VDD Write Gate. Enables the write circuitry of the selected FDD. WGATE is designed to prevent glitches during power-up and power-down. This prevents writing to the disk when power is cycled. WP 60 I INT VDD Write Protected. Indicates that the disk in the selected drive is write protected. 25 www.national.com 1.0 Signal/Pin Connection and Description 1.4.7 (Continued) Keyboard and Mouse Controller (KBC) Signal Pin/s I/O Buffer Type Power Well Description KBCLK 125 I/O INTS/OD14 VDD Keyboard Clock. Keyboard clock signal. External pull-up resistor is required for PS/2 compliance. This pin is monitored during VDD power-off for wake-up event detection. KBDAT 126 I/O INTS/OD14 VDD Keyboard Data. Keyboard data signal. External pull-up resistor is required for PS/2 compliance. This pin is monitored during VDD power-off for wake-up event detection. MCLK 127 I/O INTS/OD14 VDD Mouse Clock. Mouse clock signal. External pull-up resistor is required for PS/2 compliance. This pin is monitored during VDD power-off for wake-up event detection. MDAT 128 I/O INTS/OD14 VDD Mouse Data. Mouse data signal. External pull-up resistor is required for PS/2 compliance. This pin is monitored during VDD power-off for wake-up event detection. KBRST 122 I/O INT/OD2 VDD KBD Reset. Keyboard reset (P20) open-drain output. GA20 123 I/O INT/OD2 VDD Gate A20. KBC gate A20 (P21) open-drain output. P12, P16, P17 121, 70, 66 I/O INT/OD2, O2/2 VDD I/O Port. KBC quasi-bidirectional signal for general-purpose input and output (controlled by KBC firmware). 1.4.8 General-Purpose I/O (GPIO) Signal Pin(s) I/O Buffer Type Power Well I/O INTS/ OD14, O3/14 VSB GPIOE44, 45 50, 51 I/O INTS/ OD12, O12/12 VSB GPIO07 13 I/O INTS/ OD4, O2/4 VSB GPIO53 45 I/O INTS/ OD2, O1/2 VSB GPIO00, GPIO05-06, GPIOE10-17, GPIO20-25, GPIO26-27, GPIO30-37, GPIOE40-41, GPIOE42, 43, GPIOE46, 47, GPIO50-52, GPIO54, 55 124 9-10 1-8 14-19 22-23 24-31 2-21 35, 49 52, 53 36-38 54, 56 I/O INTS/ OD6, O3/6 VSB GPO60-62, 63, 64 32-34, 48, 55 O OD6, O3/6 VSB GPIO01-04 www.national.com 125-128 Description General-Purpose I/O Ports. Each pin is configured independently as input or I/O with or without static pull-up and with either open-drain or push-pull output type. The GPIOEnn pins have event detection capability. General-Purpose Output Ports. Each pin is configured independently for either open-drain or push-pull output type. 26 1.0 Signal/Pin Connection and Description 1.4.9 (Continued) System Wake-Up Control (SWC) Signal Pin(s) I/O Buffer Type GPIOE10-17, GPIOE40-41, GPIOE42, GPIOE43-47, 1-8 2-21 35 49-53 I RI1 RI2 101 109 KBCLK Power Well Description INTS VSB I INTS VSB Ring Indicator Wake-up. When low, generates a wake-up event or an interrupt, indicating that a telephone ring signal was received by the modem. 125 I/O INTS/OD14 VSB Keyboard Clock Wake-up. Generates a wake-up event or an interrupt, indicating a change in the keyboard clock signal. KBDAT 126 I/O INTS/OD14 VSB Keyboard Data Wake-up. Generates a wake-up event or an interrupt, indicating a change in the keyboard data signal. MCLK 127 I/O INTS/OD14 VSB Mouse Clock Wake-up. Generates a wake-up event or an interrupt, indicating a change in the mouse clock signal. MDAT 128 I/O INTS/OD14 VSB Mouse Data Wake-up. Generates a wake-up event or an interrupt, indicating a change in the mouse data signal. PWBTIN 36 I INTS VSB Power Button In. Active (low) level indicates a user request to turn the power on or off. This pin has debounce protection. PWBTOUT 49 O OD6 VSB Power Button Out. Output for the chip-set Power button input. SLBTIN 35 I INTS VSB Sleep Button In. Active (low) level indicates a user request to enter or exit Sleep mode. This pin has debounce protection. SLPS3, SLPS5 52, 53 I INTS VSB Sleep State 3 to 5. Active (low) level indicates the system is in one of the sleep states S3, S4 or S5. These signals are generated by an external ACPI controller. Wake-up Inputs. Generate a wake-up event or an interrupt. These pins have programmable debounce protection. Pins SLPS3 SLPS5 1 0 0 1 1 1 0 0 Functionality Working state (S0) or sleep states S1 or S2 Sleep state S3 Sleep states S4 or S5 Illegal combination SIOSCI 38 O OD6 VSB System Control Interrupt. Active (low) level indicates that a wake-up event occurred, causing the system to exit its current sleep state. External pull-up resistor to VSB is required. SIOSMI 37 O OD6 VSB System Management Interrupt. Active (low) level indicates that an SMI occurred. External pull-up resistor to VSB is required. ONCTL 39 O OD6 VSB LED1, LED2 50, 51 O O12/12 VSB LED Drive. These outputs can be connected directly to LED devices. They can be configured as one dual-colored LED or two single-colored LEDs with programmable blink rate for all LEDs. VDDFELL 54 O O3/6 VSB VDD Power Fell. Active pulse (high) indicates that the VDD power supply has been turned off. Optionally, this pin can be used to drive an external circuit that pulses the VSB power to the Keyboard and Mouse, thus resetting them. WDO 55 O O3/6 VSB WATCHDOG Out. An active pulse (low) of a fixed width; it is generated when a WATCHDOG time-out occurs. Power Supply On/Off Control. Active level (low) indicates that the power should be turned on. External pull-up resistor is required 27 www.national.com 1.0 Signal/Pin Connection and Description (Continued) 1.4.10 Clocks Signal Pin(s) I/O Buffer Type Power Well Description 32KX1_32KCLKIN 42 I INOSC VPP 32.768 KHz Crystal Input. Input from external crystal oscillator circuitry. 32.768 KHz Clock Oscillator Input. Input from external clock oscillator device. 32KX2 44 O OOSC VPP 32.768 KHz Crystal Oscillator Output. Output to external crystal oscillator circuitry. LFCKOUT 45 O O1/2 VSB Low Frequency Clock Output. The Real-Time Clock frequency (32.768 KHz) or a 1 Hz clock output. CLKIN 56 I INTS VSB1 Clock Input. 48 MHz for the Legacy functions or no input clock. HFCKOUT 13 O O2/4 VSB High Frequency Clock Output. Clock output for system use. 1. The CLKIN signal source can be VDD powered. 1.4.11 Configuration Straps Signal Pin(s) I/O Buffer Type Power Well Description BADDR 100 I INCS VDD Base Address. Sampled at VDD Power-Up reset to determine the base address of the configuration Index-Data register pair, as follows: No pull-up resistor: 2Eh-2Fh 10 K external pull-up resistor: 4Eh-4Fh TRIS 97 I INCS VDD TRI-STATE Device. Sampled at VDD Power-Up reset to force the device to float all its output and I/O pins, as follows: No pull-up resistor: pins active 4.7 K external pull-up resistor: pins floating CKIN48 55 I INCS VSB CLKIN 48 MHz. Sampled at VSB Power-Up reset to determine the presence of the 48 MHz input clock at the CLKIN pin, as follows: No pull-up resistor: no clock 10 K external pull-up resistor: 48 MHz clock XCNF2-0 (PC87416, PC87417) 32-34 I INCS VSB X-Bus Default Configuration. Sampled at VSB Power-Up reset to set the configuration of the X-Bus transactions. Pins 2 1 0 Functionality 0 1 1 1 1 No BIOS With BIOS, XA11-4 multiplexed, XRDY disabled With BIOS, XA11-4 multiplexed, XRDY enabled With BIOS, XA11-4 direct, XRDY disabled With BIOS, XA11-4 direct, XRDY enabled x 0 0 1 1 x 0 1 0 1 Pulled to 0 by internal resistor or set to 1 by external 10 K pullup resistor. ACBSA (PC87413, PC87417) www.national.com 48 I INCS VSB ACCESS.bus Slave Address. Sampled at VSB Power-Up reset to determine the slave address of the device on the ACCESS.bus, as follows No pull-up resistor: D8h, D9h 10 K external pull-up resistor: 60h, 61h 28 1.0 Signal/Pin Connection and Description (Continued) 1.4.12 Power and Ground Signal Pin(s) I/O Buffer Type Power Well Description VSS 11, 43, 68, 93, 115 I GND Ground. Serves for both on-chip logic, output drivers and backup battery circuit. VDD 69, 92, 116 I PWR Digital 3.3V Power Supply. Serves as power supply for the legacy peripherals and the LPC Interface. VSB 12, 40 I PWR Standby Digital 3.3V Power Supply. Used for the ACB and X-Bus Interfaces, the GPIO ports and the clock generator. When active, it also powers the RTC and the SWC. VBAT 41 I INULR Battery Power Supply. When VSB is off, this supply provides battery back-up to the SWC registers, to the RTC and to the 32 KHz crystal oscillator. The pin is connected to the internal logic through a series resistor for UL-compliant protection. 1.5 INTERNAL PULL-UP AND PULL-DOWN RESISTORS The signals listed in Table 3 have internal pull-up (PU) and/or pull-down (PD) resistors. The internal resistors are optional for those signals indicated as "Programmable". See Section 11.3 on page 235 for the values of each resistor type. Table 3. Internal Pull-Up and Pull-Down Resistors Signal Pin/s Type Comments Parallel Port ACK 78 PU220 AFD_DSTRB 90 PU440 BUSY_WAIT 77 PD120 ERR 88 PU220 INIT 86 PU440 PE 76 PU220/ PD110 SLCT 75 PD110 SLIN_ASTRB 84 PU440 STB_WRITE 91 PU440 PPDIS 121 PU25 Programmable Keyboard and Mouse Controller (KBC) P12, P16, P17 PU25 121, 70, 66 ACCESS.bus (ACB) Interface (PC87413 and PC87417) ACBCLK 47 PU25 Programmable1 ACBDAT 46 PU25 Programmable1 29 www.national.com 1.0 Signal/Pin Connection and Description (Continued) Table 3. Internal Pull-Up and Pull-Down Resistors (Continued) Signal Pin/s Type Comments System Wake-Up Control (SWC) PWBTIN 36 PU25 SLBTIN 35 PU25 PWBTOUT 49 PU25 Note 2 General-Purpose Input/Output (GPIO) Ports GPIO00-04, 05-06, 07 124-128, 9-10, 13 PU25 Programmable3 GPIOE10-17 1-8 PU25 Programmable3 GPIO20-25, 26-27 14-19, 22-23 PU25 Programmable3 GPIO30-37 24-31 PU25 Programmable3 GPIOE40-41, 42, 43-47 20-21, 35, 49-53 PU25 Programmable3 GPIO50-52, 53, 54, 55 36-38, 45, 54, 56 PU25 Programmable3 GPO60-62, 63, 64 PU50 Programmable3,4 32-34, 48, 55 Strap Configuration BADDR 100 PD110 Strap5 TRIS 97 PD60 Strap5 CKIN48 55 PD110 Strap6 XCNF2-0 (PC87416, PC87417) 32-34 PD110 Strap6 ACBSA (PC87413, PC87417) 48 PD110 Strap6 1. Default at reset: disabled. 2. Disabled when VDD is off. 3. See Table 26 on page 72 for default value at reset (0 = PU disabled, 1 = PU enabled). 4. Disabled during VSB Power-Up reset. 5. Active only during VDD Power-Up reset. 6. Active only during VSB Power-Up reset. www.national.com 30 2.0 Power, Reset and Clocks 2.1 POWER 2.1.1 Power Planes The PC8741x devices have three power planes (wells), as shown in the table below: Table 4. Power Planes Power Plane Description Power Pins Ground Pins Main Powers the Legacy modules (Serial Ports, Parallel Port, FDC, KBC), the LPC Interface, part of the Configuration Control and some external signals1 VDD VSS Standby Powers the ACCESS.bus and X-Bus Interfaces, the GPIO ports, the Clock Generator, part of the SWC, part of the Configuration Control and some external related signals1 VSB VSS Backup Powers the RTC, the 32.768 KHz clock/crystal oscillator, part of the SWC and some functions that must be preserved at all times1 VPP2 VSS 1. See the tables in Section 1.4 (pages 22-29), specifically the Power Well column. 2. VPP is an internal power signal derived from VSB or VBAT. VPP is taken from VSB if it is greater than the minimum value defined in Section 11.1.5; otherwise it is taken from VBAT. For more details on switching between them, refer to Section 8.2.9. For correct operation, either VSB or VBAT must be applied whenever VDD is applied. 2.1.2 Power States The PC8741x devices have four power states: * * Battery Fail - the Main, Standby and Backup power planes are all powered off (VDD, VSB and VBAT are inactive). * Power Off - the Main power plane is powered off; the Standby power plane is on; the Backup power plane is on (VDD is inactive; VSB is active; VBAT is irrelevant). * Power On - the Main and Standby power planes are powered on; the Backup power plane may is on (VDD and VSB are active; VBAT is irrelevant). Power Fail - the Main and Standby power planes are powered off; the Backup power plane is on (VDD and VSB are inactive; VBAT is active). The following power state is illegal: * The Main power plane is powered on, the Standby power plane is off and the Backup power plane is on or off (i.e., VDD is active, VSB is inactive and VBAT is irrelevant). The following table summarizes the power states described above. Table 5. Power States and Related Power Planes Power State Main (VDD) Standby (VSB) Backup (VPP) OFF Battery Fail OFF OFF Power Fail OFF OFF Power Off OFF Power On ON Illegal1 ON ON OFF OFF ON ON ON or OFF VBAT ON ON ON or OFF ON ON or OFF ON or OFF 1. Operation is not guaranteed and register data may be corrupted. 31 www.national.com 2.0 Power, Reset and Clocks (Continued) Figure 1 shows the power state transitions: Battery Fail VDD, VSB and VBAT Off VBAT Off VBAT On, VPP Power-Up Reset Cold Reset + VPP Power-Up Reset Power Fail VDD and VSB Off, VBAT On VSB Off VSB On (VBAT Off), VSB On, VSB Power-Up Reset VSB Off (VBAT Off) Power Off VDD Off, VSB On VBAT On VBAT Off VDD Off VDD On, VDD Power-Up Reset Power On VDD and VSB On VBAT On VBAT Off Figure 1. Power State Transitions 2.1.3 Power Connection and Layout Guidelines The PC8741x requires a power supply voltage of 3.3V 10% for both the VDD and the VSB supplies. The device is designed to operate with a Lithium backup battery supplying up to 3.6V. Therefore, it includes an internal current-limiting resistor on the VBAT input to prevent the battery from shorting, as required by the UL regulations. VDD, VSB and VBAT use a common ground return marked VSS. To obtain the best performance, bear in mind the following recommendations. Ground Connection. The following items must be connected to the ground layer (VSS) as close to the device as possible: * * * * The five ground return (VSS) pins. The decoupling capacitors of the Main power supply (VDD) pins. The decoupling capacitors of the Standby power supply (VSB) pins. The decoupling capacitor of the Backup battery (VBAT) pin. Note that a low-impedance ground layer also improves noise isolation. Decoupling Capacitors. The following decoupling capacitors must be used in order to reduce EMI and ground bounce: * Main power supply (VDD): Place one capacitor of 0.1 F on each VDD-VSS pin pair as close to the pin as possible. In addition, place one 10-47 F tantalum capacitor on the common net as close to the chip as possible. * Standby power supply (VSB): Place one capacitor of 0.1 F on each VSB-VSS pin pair as close to the pin as possible. In addition, place one 10-47 F tantalum capacitor on the common net as close to the chip as possible. * Backup battery (VBAT): Place one capacitor of 0.1 F on the VBAT pin as close to the pin as possible. In addition, place one 4.7-10 F ceramic capacitor on the common net as close to the chip as possible. www.national.com 32 2.0 Power, Reset and Clocks (Continued) 2.2 RESET SOURCES AND TYPES The PC8741x devices have up to six reset sources: * * * * * VPP Power-Up Reset - activated when either VSB or VBAT is powered up after both have been off. * Controller Software Reset (PC87413 and PC87417) - triggered by the CSWRST bit of the ACBCFG register (see Section 6.3.3 on page 127); the CSWRST bit is set by the system controller through the ACCESS.bus Interface. VSB Power-Up Reset - activated when VSB is powered up. VDD Power-Up Reset - activated when VDD is powered up. Hardware Reset - activated when the LRESET input is asserted (low). Host Software Reset - triggered by the HSWRST bit of the SIOCF1 register (see Section 3.7.2 on page 48); the HSWRST bit is set by the host through the LPC Interface. Unless otherwise noted, reset references throughout the modules of the PC8741x devices default to the following resets: For VPP-retained functions (RTC, part of SWC and some other functions): VPP Power-Up reset. For VSB-powered functions (ACCESS.bus, X-Bus, GPIO ports, Clock Generator, part of SWC and part of Configuration Control): VSB Power-Up reset or Controller Software Reset (within the limitations described in Section 2.2.3). For VDD-powered functions (Legacy modules, LPC and part of Configuration Control): VDD Power-Up reset, Hardware Reset or Host Software Reset (within the limitations described in Section 2.2.6). The following sections detail the sources and effects of the various resets on the PC8741x devices per reset source. 2.2.1 VPP Power-Up Reset VPP is an internal power signal derived from VSB and VBAT. VPP Power-Up reset is generated by an internal circuit that detects the status of the VPP power. An active VPP Power-Up reset signal is generated following a rise in the VPP until the VPP power within the accepted range is detected (see Section 11.1.5 on page 231). When VPP Power-Up reset is active, it resets the modules and registers whose values are retained by VPP (RTC, part of SWC and some other functions). The VPP PowerUp reset also activates the 32 KHz internal crystal oscillator. 2.2.2 VSB Power-Up Reset VSB Power-Up reset is generated by an internal circuit when VSB power is applied. This reset is completed after 8,192 cycles of the 32 KHz clock (t32KOSC). However, if the 32 KHz on-chip crystal oscillator was disabled before VSB power-up, a delay of t32KW (see Low Frequency Clock Timing on page 241) is added to tIRST (see VSB Power-Up Reset on page 238) to account for the time required by the 32 KHz oscillator to stabilize. In addition, if the Hardware reset (LRESET) is de-asserted in an early stage, only 1,280 clock cycles are required to complete the VSB Power-Up reset. External devices should wait at least tIRST before accessing the PC8741x device. However, if the system controller accesses the PC8741x device (through the ACCESS.bus) before tIRST ends, both the ACBDAT and the ACBCLK signals will float until the end of VSB Power-Up reset, which is when the ACCESS.bus Interface becomes operational. Since these signals are pulled-up by external resistors, this situation is equivalent to generating a NACK condition in response to the system controller access (see Section 6.2.4 on page 117). VSB Power-Up reset performs the following actions and all the actions performed by VDD Power-Up reset (if the VDD power is already active): * * * * * * * * * * Activates the Clock Generator and sets its output to the default frequency. Puts pins with VSB strap options into TRI-STATE and enables their internal pull-down resistors. Samples the logic levels of the VSB strap pins. Sets up the PC8741x device slave address on the ACCESS.bus (PC87413 and PC87417). Resets the VSB-powered lock bits in the Configuration Control and X-Bus (PC87416 and PC87417). Loads default values to the GPIO Configuration bits: VDDLOAD and BUSCTL. Loads default values to the VSB-powered bits in SWC. Loads default values to the bits in ACCESS.bus Interface (PC87413 and PC87417). Sets up the pull-up option and the default source for the VSB-powered multiplexed output pins. Executes all the actions performed by the Controller Software reset (see Section 2.2.3 on page 34) in all PC8741x devices. 33 www.national.com 2.0 Power, Reset and Clocks 2.2.3 (Continued) Controller Software Reset (PC87413 and PC87417) The Controller Software reset is initiated by the system controller through the ACCESS.bus Interface. The system controller can trigger this reset by setting the CSWRST bit of the ACBCFG register (see Section 6.3.3 on page 127). The Controller Software reset performs the following actions: * * * Updates the VSB-powered strap configuration bits with the strap levels sampled during the VSB Power-Up reset. * Loads default values to the bits in the ACBCST, ACBDIS and ACBTRIS registers of the ACCESS.bus Interface (PC87413 and PC87417). * Terminates any transaction involving the internal modules of the PC8741x device that were initiated by the ACCESS.bus Interface. Loads default values to the VSB-powered unlocked bits in the Configuration Control and X-Bus (PC87416 and PC87417). Loads default values to the unlocked GPIO Configuration and Data bits for those GPIO ports with VDDLOAD = 0. The VDDLOAD and BUSCTL bits are not affected. 2.2.4 VDD Power-Up Reset VDD Power-Up reset is generated by an internal circuit when VDD power is turned on. This reset is completed after 8,192 cycles of the 32 KHz clock (t32KOSC; see Low Frequency Clock Timing on page 241). However, if the Hardware reset (LRESET) is de-asserted in an early stage, tIRST (see VSB Power-Up Reset on page 238) is shortened to only 1,280 clock cycles. In any condition, the VDD Power-Up reset ends after the VSB Power-Up reset. External devices must wait at least tIRST before accessing the PC8741x device. If the host processor accesses the device during this time, the PC8741x device ignores the transaction (that is, it does not return SYNC response). VDD Power-Up reset performs the following actions: * * * Puts pins with VDD strap options into TRI-STATE and enables their internal pull-down resistors. Samples the logic levels of the VDD strap pins. Executes all the actions performed by the Hardware reset (see Section 2.2.5 on page 34). 2.2.5 Hardware Reset Hardware reset is activated by the assertion (low) of the LRESET input while VDD is "good". When the VDD power is OFF, the PC8741x device ignores the level of the LRESET input. Hardware reset performs the following actions: * Resets the VSB-powered lock bits in the Configuration Control and X-Bus (PC87416 and PC87417), if VSBLOCK = 0 in the ACBLKCTL register (in PC87414 and PC87416, VSBLOCK is always `0'). * * Sets up the pull-up option and the default source for the VDD-powered multiplexed output pins. Executes all the actions performed by the Host Software reset (see Section 2.2.6 on page 34). 2.2.6 Host Software Reset The Host Software reset is triggered by the host setting the HSWRST bit of the SIOCF1 register (see Section 3.7.2 on page 48) through the LPC Interface. The Host Software reset performs the following actions: * * * * * * Updates the VDD-powered strap configuration bits with the strap levels sampled during the VDD Power-Up reset. Loads default values to the VDD-powered unlocked bits in the Configuration Control. Loads default values to the VSB-powered unlocked GPIO Configuration and Data bits for those GPIO ports with VDDLOAD = 1. The VDDLOAD and BUSCTL bits are not affected. Resets all the VDD-powered Legacy logical devices. Loads default values to all the VDD-powered Legacy module registers. Terminates any transaction involving the internal modules of the PC8741x device that were initiated by the LPC bus Interface. www.national.com 34 2.0 Power, Reset and Clocks (Continued) 2.3 CLOCK GENERATION 2.3.1 Clock Domains The PC8741x devices have five clock domains, as shown in Table 6. Table 6. Clock Domains of the PC8741x Clock Domain Frequency Source Usage LPC Up to 33 MHz LPC clock input (LCLK) LPC bus Interface Legacy 48 MHz Clock input (CLKIN) or Clock Generator Legacy functions (Serial Ports, Parallel Port, FDC, KBC) Output Clock Up to 40 or 48 MHz Clock Generator External Devices Standby 20 or 24 MHz Clock Generator VSB-powered functions (ACCESS.bus and X-Bus Interfaces) RTC 32.768 KHz Clock input or on-chip oscillator (32KX1, 32KX2)1 RTC, Clock Generator, SWC, GPIO 1. See Section 8.2 on page 141. The LPC and Legacy clock domains, and the modules using them, are powered by the Main power plane. Therefore, these two clock domains are only active when the VDD power supply is on; however, if the Legacy clock domain is sourced by the Clock Generator, it is active also during the time VDD power supply is off. The Standby and Output clock domains are sourced by the Clock Generator, which is supplied by the Standby power plane. These two clock domains are active while the VSB power supply is on. Both clock domains require a certain amount of time to stabilize after VSB becomes active. Moreover, if the 32 KHz on-chip crystal oscillator was disabled before VSB power-up, the time required for the clocks to stabilize is t32KOSC (see Section 11.4.3 on page 240). The selection of 40 MHz (or its divisions) or 48 MHz (or its divisions) is set by the CKIN48 strap. The RTC clock domain is sourced either by a clock input or by the on-chip crystal oscillator, which are supplied by the Backup power plane. This clock domain is active while either the VBAT or VSB power supply is on. At VBAT or VSB power-up, the clock requires t32KOSC to stabilize. 2.3.2 Clock Generator The Clock Generator is the source of the Standby and Output clock domains; it is also the source of the Legacy clock domain if the 48 MHz clock input is not available. The Clock Generator is fed by the 32.768 KHz from the on-chip crystal oscillator and supplied by the Standby power plane. It starts generating clock output either after the VSB power supply is turned on (if the 32.768 KHz clock is already stable) or after the 32.768 KHz clock stabilizes (if VBAT was inactive previous to VSB poweron), whichever occurs last. Operation Figure 2 shows a simplified diagram of the Clock Generator. CLKIN 48 MHz or no clock 1 48 MHz 0 CKIN48(strap) Divide by 2 20/24 MHz Legacy Modules ACCESS.bus Interface X-Bus Extension Frequency On-chip Crystal Oscillator 32.768 KHz Multiplier 40/48 MHz 32.768 KHz RTC 1 Hz 0 Programmable Divider 32.768 KHz / 1 Hz HFCKOUT LFCKOUT 1 LFCKSEL Figure 2. Clock Generator - Simplified Diagram 35 www.national.com 2.0 Power, Reset and Clocks (Continued) The Frequency Multiplier generates either a 40 MHz or a 48 MHz clock out of the 32.768 KHz clock from the on-chip crystal oscillator (which is a part of the RTC module; see Section 8.2.2 on page 141). The frequency is selected by the value read at VSB Power-Up reset from the CKIN48 strap input pin (available for read in the CKIN48 bit of the CLOCKCF register; see Section 3.7.10 on page 55): * A strap value of `0' configures the PC8741x device to work without a clock signal that is connected to the CLKIN pin and to generate a 48 MHz internal clock. This clock is used for the Standby and Output clock domains and is also selected for the Legacy modules. * A strap value of `1' configures the PC8741x device to work with a 48 MHz clock signal connected to the CLKIN pin and to generate a 40 MHz internal clock. This clock is used only for the Standby and Output clock domains. The 48 MHz input clock is selected for the Legacy modules. The internal clock generated by the Frequency Multiplier is divided by two and used as the basic clock for the ACCESS.bus Interface and X-Bus Extension modules. In addition, it is scaled-down by a programmable divider and generates the HFCKOUT signal. On power-up, when VSB is applied, the Frequency Multiplier waits for the 32.768 KHz clock to stabilize before it starts generating the internal clock. The multiplier output clock is frozen to a low level until the multiplier provides a stable clock signal that meets all requirements. Then the multiplier output clock starts toggling. The status of the internal clock is indicated by the CKVALID bit of the CLOCKCF register. While either the on-chip crystal oscillator or the Frequency Multiplier is stabilizing, this bit is 0, indicating an internal clock frozen at low level. When the internal clock starts toggling, this bit is set to 1. The software must activate (enable) the Legacy modules (Serial Ports, Parallel Port, FDC, KBC) only after the CKVALID bit is set. The programmable divider scales down the frequency of the internal clock according to the CKIN48 strap and the HFCKDV field of the CLOCKCF register (see Section 3.7.10 on page 55), as shown in Table 7. . Table 7. HFCKOUT Frequency Selection HFCKOUT Frequency HFCKDIV Field Divisor Default 0 1 40 MHz at CKIN48=1 0 1 22 24 MHz at CKIN48=0 0 1 0 3 10 MHz 0 1 1 4 8 MHz 6.667 MHz 1 0 0 6 6 MHz 5 MHz 1 0 1 8 4 MHz 3.333 MHz 1 1 0 12 3 MHz 2.5 MHz 1 1 1 16 CKIN48 = 0 CKIN48 = 1 Bit 2 Bit 1 Bit 0 48 MHz 40 MHz1 0 0 24 MHz 20 MHz 0 16 MHz 13.333 MHz 12 MHz 1. The actual value is 40.004 MHz. 2. The output signal, generated using all the division ratios (divisors), has an accurate 50% duty cycle. During frequency transitions caused by software changing the HFCKDIV field value, the output clock is guaranteed to be glitch free. The high or low level of the clock signal is stable for at least half of the shortest cycle between the previous and the new frequency. When the alternate function (GPIO07) is selected for the device pin (see Section 3.7.3 on page 49) or if the HFCKDIS bit in the CLOCKCF register is set, the programmable divider is disabled to save power. When the programmable divider is disabled by setting the HFCKDIS bit, HFCKOUT is stopped at low level. Specifications Frequency Multiplier wake-up time is 33 msec (maximum). This is measured from a valid VSB or a valid 32.768 KHz clock until the internal clock is stable. Tolerance (long term deviation) of the multiplier output clock, relative to the 32.768 KHz clock, is 110 ppm. Total tolerance is therefore (input clock tolerance + 110 ppm). Cycle-by-cycle variance is 0.4 nsec (maximum). 2.3.3 Low Frequency Clock This clock output is obtained by selecting to the LFCKOUT pin either the 32.768 KHz clock or a 1 Hz signal (generated by the RTC). The LFCKSEL bit in the CLOCKCF register (see Section 3.7.10 on page 55) is responsible for the selection. The transition from one clock source to the other is not guaranteed to be glitch free. www.national.com 36 3.0 Device Architecture and Configuration The PC8741x devices comprise a collection of legacy and proprietary functional blocks. Each functional block is described in a separate chapter in this document. However, some parameters in the implementation of each functional block may vary per ServerI/O device. This chapter describes the structure of the PC8741x devices and provides all logical device specific information, including special implementation of generic blocks, system interface and device configuration. 3.1 OVERVIEW The PC8741x consists of the following: up to 10 logical devices, the host interface, the system controller interface and a central set of configuration registers. All these components are built around a central, internal bus. The internal bus is similar to an 8-bit ISA bus protocol. See the Block Diagram on page 1, which illustrates the blocks and the internal bus. The host, via the LPC Interface, can access the modules connected to the Internal bus. This interface supports 8-bit I/O Read/Write, 8-bit Memory Read/Write and 8-bit DMA transactions of the LPC bus (see Section 4.2 on page 89). The system controller can access these modules via the ACB Interface (PC87413 and PC87417). This interface supports slave operation for 8-bit I/O Read/Write and 8-bit Memory Read/Write transactions of the ACCESS.bus (see Section 6.2 on page 116). Both the host and system controller accesses occur concurrently via the Internal bus. The central configuration register set is ACPI compliant and supports PnP configuration. The configuration registers are structured as a subset of the Plug and Play Standard registers, defined in Appendix A of the Plug and Play ISA Specification, Revision 1.0a by Intel and Microsoft(R). All system resources assigned to the functional blocks (I/O address space, IRQ numbers and DMA channels) are configured in and managed by the central configuration register set. In addition, some function-specific parameters are configurable through the configuration registers and distributed to the functional blocks through special control signals. Access through the ACB Interface (PC87413 and PC87417) ignores the PnP configuration registers and thus the system resources assigned through them. 3.2 CONFIGURATION STRUCTURE AND ACCESS The configuration structure is comprised of a set of banked registers that are accessed via a pair of specialized registers. 3.2.1 The Index-Data Register Pair Access to the ServerI/O configuration registers is via an Index-Data register pair, using only two system I/O byte locations. The base address of this register pair is determined during reset, according to the state of the hardware strapping option on the BADDR pin. Table 8 shows the selected base addresses as a function of BADDR. The I/O location of the Index-Data register pair is irrelevant when the configuration is accessed through the ACB Interface. Table 8. BADDR Strapping Options I/O Address BADDR Index Register Data Register 0 2Eh 2Fh 1 4Eh 4Fh The Index register is an 8-bit read/write register located at the selected base address (Base+0). It is used as a pointer to the configuration register file and holds the index of the configuration register that is currently accessible via the Data register. Reading the Index register returns the last value written to it (or the default of 00h after reset). The Data register is an 8-bit register (Base+1) used as a data path to any configuration register. Accessing the Data register actually accesses the configuration register that is currently pointed to by the Index register. The Index, Data and Logical Device Number registers are duplicated to enable concurrent access to the configuration registers from the LPC bus and ACCESS.bus, without contention (PC87413 and PC87417). Each bus has its own set of registers (Index/Data/LDN) powered from the VSB well (ACCESS.bus set) or the VDD well (LPC bus set). This power scheme allows access to the configuration registers of the VSB-powered modules while in Power Off state (VDD off). In this case, access is possible only through the ACCESS.bus. 37 www.national.com 3.0 Device Architecture and Configuration 3.2.2 (Continued) Banked Logical Device Registers Structure Each functional block is associated with a Logical Device Number (LDN). The configuration registers are grouped into banks, where each bank holds the standard configuration registers of the corresponding logical device. Table 9 shows the LDN values of the PC8741x functional blocks. Any value not listed is reserved. Figure 3 shows the structure of the standard configuration register file. The LDN and ServerI/O Configuration registers are not banked and are accessed by the Index-Data register pair only, as described above. However, the device control and device configuration registers are duplicated over 10 banks for the 10 logical devices. Therefore, accessing a specific register in a specific bank is performed by two-dimensional indexing, where the LDN register selects the bank (or logical device) and the Index register selects the register within the bank. Accessing the Data register while the Index register holds a value of 30h or higher actually accesses the configuration registers of the logical device selected by the LDN register and pointed to by the Index register. 07h Logical Device Number Register 20h 2Fh ServerI/O Configuration Registers 30h Logical Device Control Register 60h 63h 70h 71h 74h 75h F0h FEh Standard Logical Device Configuration Registers Special (Vendor-defined) Logical Device Configuration Registers Bank Select Banks (One per Logical Device) Figure 3. Structure of Standard Configuration Register File Table 9. Logical Device Number (LDN) Assignments LDN Functional Block 00h Floppy Disk Controller (FDC) 01h Parallel Port (PP) 02h Serial Port 2 (SP2) 03h Serial Port 1 (SP1) 04h System Wake-Up Control (SWC) 05h Keyboard and Mouse Controller (KBC) - Mouse Interface 06h Keyboard and Mouse Controller (KBC) - Keyboard Interface 07h General-Purpose I/O (GPIO) Ports 0Fh X-Bus Extension (PC87416 and PC87417) 10h Real Time Clock (RTC) Write accesses to unimplemented registers (i.e., accessing the Data register while the Index register points to a non-existing register) are ignored. Read accesses return 00h on all addresses, except for 74h and 75h (DMA configuration registers), which returns 04h (indicating no DMA channel). The configuration registers are accessible immediately after reset. www.national.com 38 3.0 Device Architecture and Configuration 3.2.3 (Continued) Standard Configuration Register Definitions In the registers below, any undefined bit is reserved. Unless otherwise noted, the following definitions also hold true: * * All registers are read/write. * Write-only registers must not use read-modify-write during updates. All reserved bits return 0 on reads, except where noted otherwise. To prevent unpredictable results, do not modify these bits. Use read-modify-write to prevent the values of reserved bits from being changed during write. Table 10. Standard General Configuration Registers Index Register Name 07h Logical Device Number 20h - 2Fh ServerI/O Configuration Description This register selects the current logical device. See Table 9 for valid numbers. All other values are reserved. ServerI/O configuration registers and ID registers. Table 11. Logical Device Activate Register Index Register Name 30h Activate Description Bit 0 - Logical device activation control (see Section 3.3 on page 42) 0: Disabled 1: Enabled Bits 7-1 - Reserved Table 12. I/O Space Configuration Registers Index Register Name Description 60h I/O Port Base Indicates selected I/O lower limit address bits 15-8 for I/O Descriptor 0. Address Bits (15-8) Descriptor 0 61h I/O Port Base Indicates selected I/O lower limit address bits 7-0 for I/O Descriptor 0. Address Bits (7-0) Descriptor 0 62h I/O Port Base Address Bits (15-8) Indicates selected I/O lower limit address bits 15-8 for I/O Descriptor 1. Descriptor 1 63h I/O Port Base Address Bits (7-0) Indicates selected I/O lower limit address bits 7-0 for I/O Descriptor 1. Descriptor 1 39 www.national.com 3.0 Device Architecture and Configuration (Continued) Table 13. Interrupt Configuration Registers Index Register Name Description 70h Interrupt Number Indicates selected interrupt number. and Wake-Up on Bits 7-5 - Reserved. IRQ Enable Bit 4 - Enables a Power Management event (SCI or wake-up) from the IRQ of the logical device. When enabled, IRQ assertion sets the respective XXX_IRQ_STS bit (XXX is MOD, MS or KBD) in the GPE1_STS_3 register (see Section 9.4.11 on page 210). 0: Disabled (default) 1: Enabled Note: If the BIOS routine that sets IRQ does not use a Read-Modify-Write sequence, it might reset bit 4. To ensure that the system wakes up, the BIOS must set bit 4 before the system goes to sleep. Bits 3-0 select the interrupt number. A value of 1 selects IRQ1. A value of 15 selects IRQ15. IRQ0 is not a valid interrupt selection and represents no interrupt selection. Note: Avoid selecting the same interrupt number (except 0) for different Logical Devices, as it causes the PC8741x device to behave unpredictably. 71h Interrupt Request Indicates the type and polarity of the interrupt request number selected in the Type Select previous register. If a logical device supports only one type of interrupt, the corresponding bit is read-only. Bits 7-2 - Reserved. Bit 0 - Type of interrupt request selected in previous register 0: Edge 1: Level Bit 1 - Polarity of interrupt request selected in previous register 0: Low polarity 1: High polarity Table 14. DMA Configuration Registers Index Register Name Description 74h DMA Channel Select 0 Indicates selected DMA channel for DMA 0 of the logical device (0 - The first DMA channel in case of using more than one DMA channel). Bits 7-3 - Reserved. Bits 2-0 select the DMA channel for DMA 0. The valid choices are 0-3, where: - A value of 0 selects DMA channel 0, 1 selects channel 1, etc. - A value of 4 indicates that no DMA channel is active. - The values 5-7 are reserved. Note: Avoid selecting the same DMA channel (except 4) for different Logical Devices, as it causes the PC8741x device to behave unpredictably. 75h DMA Channel Select 1 Indicates selected DMA channel for DMA 1 of the logical device (1 - The second DMA channel in case of using more than one DMA channel). Bits 7-3 - Reserved. Bits 2-0 select the DMA channel for DMA 1. The valid choices are 0-3, where: - A value of 0 selects DMA channel 0, 1 selects channel 1, etc. - A value of 4 indicates that no DMA channel is active. - The values 5-7 are reserved. Note: Avoid selecting the same DMA channel (except 4) for different Logical Devices, as it causes the PC8741x device to behave unpredictably. www.national.com 40 3.0 Device Architecture and Configuration (Continued) Table 15. Special Logical Device Configuration Registers Index Register Name F0h-FEh Logical Device Configuration 3.2.4 Description Special (vendor-defined) configuration options. Standard Configuration Registers Index ServerI/O Control and Configuration Registers Logical Device Control and Configuration Registers one per Logical Device (some are optional) Register Name 07h Logical Device Number 20h ServerI/O ID 21h ServerI/O Configuration 1 22h ServerI/O Configuration 2 23h ServerI/O Configuration 3 24h ServerI/O Configuration 4 25h ServerI/O Configuration 5 26h ServerI/O Configuration 6 27h ServerI/O Revision ID 28h ServerI/O Configuration 8 29h Clock Generator Configuration 2Ah ACCESS.bus Configuration 2Bh - 2Fh Reserved for National use 30h Logical Device Control (Activate) 60h I/O Base Address Descriptor 0 Bits 15-8 61h I/O Base Address Descriptor 0 Bits 7-0 62h I/O Base Address Descriptor 1 Bits 15-8 63h I/O Base Address Descriptor 1 Bits 7-0 70h Interrupt Number and Wake-Up on IRQ Enable 71h IRQ Type Select 74h DMA Channel Select 0 75h DMA Channel Select 1 F0h - FFh Device Specific Logical Device Configuration Figure 4. Configuration Register Map ServerI/O Control and Configuration Registers The ServerI/O configuration registers at indexes 20h (ServerI/O ID) and 27h (ServerI/O Revision ID) are used for part identification. The other configuration registers are used for global power management and selecting pin multiplexing options. For details, see Section 3.7 on page 47. Logical Device Control and Configuration Registers A subset of these registers is implemented for each logical device. See functional block descriptions in the following sections. 41 www.national.com 3.0 Device Architecture and Configuration (Continued) Control The only implemented control register for each logical device is the Activate register at index 30h. Bit 0 of the Activate register controls the activation of the associated functional block. Activation enables access to the functional block's runtime registers and attaches its system resources, which are unassigned as long as it is not activated. Other effects may apply on a function-specific basis (such as clock enable and active pinout signaling). Access to the configuration register of the logical device is enabled even when the logical device is not activated. Standard Configuration The standard configuration registers manage the PnP resource allocation to the functional blocks. The I/O port base address descriptor 0 is a pair of registers at Index 60-61h that hold the first 16-bit base address for the register set of the functional block. An optional 16-bit second base-address (descriptor 1) at index 62-63h is used for logical devices with more than one continuous register set. Interrupt Number and Wake-Up on IRQ Enable (index 70h) and IRQ Type Select (index 71h) allocate an IRQ line to the block and control its type. DMA Channel Select 0 (index 74h) allocates a DMA channel to the block, where applicable. DMA Channel Select 1 (index 75h) allocates a second DMA channel, where applicable. Special Configuration The vendor-defined registers, starting at index F0h, control function-specific parameters such as operation modes, power saving modes, pin TRI-STATE, clock rate selection and non-standard extensions to generic functions. 3.2.5 Default Configuration Setup The default configuration setup of the PC8741x device is determined by the six reset types described in Section 2.2 on page 33. See the specific register descriptions for the bits affected by each reset source. In the event of a VDD Power-Up (also induced by VSB Power-Up reset) or Hardware reset, the PC8741x device wakes up with the following default configuration setup: * * * The configuration base address is 2Eh or 4Eh, according to the BADDR strap pin value, as shown in Table 8 on page 37. If the VSBLOCK bit in the ACBLKCTL register is `0' (see Section 6.3.4 on page 127; in PC87414 and PC87416, VSBLOCK is always `0'), all lock bits in the Configuration Control registers are reset (the protected bits are unlocked). All the actions performed by the Host Software reset are executed. If a Host software reset occurs, the PC8741x device wakes up with the following default configuration setup: * All logical devices are disabled (the Activation bit is reset) and the VSB-powered logical devices (X-Bus, GPIO, RTC and SWC) remain functional but their registers cannot be accessed by the Host. * * Standard configuration registers of all logical devices are set to their default values. * All Legacy devices are reset. Default values are loaded into the Legacy module runtime registers. National proprietary functions are not assigned with any default resources and the default values of their base addresses are all 00h. 3.3 MODULE CONTROL Module control is performed primarily through the Activation bit (bit 0 of index 30h) of each logical device. The operation of each module can be controlled either by the host through the LPC bus or by the Embedded Controller through the ACCESS.bus (PC87413 and PC87417). This dual control is supported by two interacting mechanisms: a dual enable/disable and an access lock (the access lock is available only through the ACCESS.bus). 3.3.1 Module Enable/Disable LPC Control. Module enable/disable by the host through the LPC bus is controlled by the following bits (see Figure 5 on page 44): Activation bit (bit 0) in index 30h of the Standard configuration registers (see Section 3.2.3 on page 39). Fast Disable bit in the SIOCF6 register (see Section 3.7.7 on page 53) - only for the FDC, Parallel Port and Serial Port 1 and 2 modules. Fast Disable bit in the SWCFDIS register (see Section 9.3.8 on page 184) - only for the KBC, FDC, Parallel Port and Serial Port 1 and 2 modules. Global Enable bit (GLOBEN) in the SIOCF1 register (see Section 3.7.2 on page 48). www.national.com 42 3.0 Device Architecture and Configuration (Continued) A module is enabled only if all these bits are set to their "enable" value and the module's enable/disable is not controlled by the Embedded Controller as described in the next paragraph. Although possible, changing the above bits by the Embedded Controller through the ACCESS.bus (PC87413 and PC87417) is not recommended. ACCESS.bus Control. Module enable/disable by the Embedded Controller through the ACCESS.bus (PC87413 and PC87417) is controlled by the following bits: Access lock bit (xxxALOK) in the ACCLCF1 and ACCLCF2 registers (see Sections 6.3.7 and 6.3.8 on pages 131ff.) - for the FDC, Parallel Port, Serial Port 1 and 2, KBC, X-Bus, RTC and SWC modules. Fast Disable bit in the ACBFDIS register (see Section 6.3.5 on page 129) - only for the KBC, FDC, Parallel Port and Serial Port 1 and 2 modules. A module is enabled if both the Access lock bit is set to "lock" and the Fast Disable bit is set to "enable". When the module enable/disable is controlled by the Embedded Controller, the setting of the Activation, Fast Disable (in both SIOCF6 and SWCFDIS) or Global Enable bits is ignored (see Figure 5 on page 44). When a VDD-powered module (FDC, Parallel Port and Serial Port 1 and 2 and KBC) is disabled, the following takes place: The host system resources of the logical device (IRQ, DMA and runtime address range) are unassigned. Access to the standard- and device-specific Logical Device configuration registers, through LPC bus or ACCESS.bus, remains enabled. Access to the module's runtime registers through the LPC bus is disabled (transactions are ignored; SYNC cycle is not generated). Access to the module's runtime registers through the ACCESS.bus causes unpredictable results, and therefore is not allowed. * The module's internal clock is disabled (the module is not functional) to lower power consumption. When a VSB-powered module (X-Bus, GPIO, RTC and SWC) is disabled, the following takes place: The host system resources of the logical device (IRQ, DMA and runtime address range)) are unassigned, with the exception of the XIRQ interrupt, which is not a resource of the X-Bus Extension and therefore remains operational. Access to the standard- and device specific Logical Device configuration registers, through the LPC bus or ACCESS.bus, remains enabled. Access to the module's runtime registers through the LPC bus is disabled (transactions are ignored; SYNC cycle is not generated). Access to the module's runtime registers through the ACCESS.bus causes unpredictable results, and therefore is not allowed. * The module is functional. 3.3.2 Module Lock by ACCESS.bus (PC87413 and PC87417) A module can be locked to allow only ACCESS.bus control over its registers. In this case, only the setting of the Fast Disable bit in the ACBFDIS register controls the enable/disable of the module (see Figure 5 on page 44). The setting of the Activation, Fast Disable (in both SIOCF6 and SWCFDIS) or Global Enable bits is ignored. Module locking is controlled by the bits of the ACCLCF1 and ACCLCF2 registers (see Sections 6.3.7 and 6.3.8 on pages 131ff.). When a module is locked for sole use by ACCESS.bus, the following takes place: The system resources of the logical device (IRQ, DMA) are forced to their inactive level, with the exception of the XIRQ interrupt, which is not a resource of the X-Bus Extension and therefore remains operational. Host read access to the Logical Device Standard and Device Specific configuration registers (through the LPC bus) remains enabled. Host write access to these registers is ignored. Host access to the module's runtime registers (through the LPC bus) is disabled and the transaction is performed according to the setting of the ACCLMD field, as described in the next paragraph. * The module is functional. If, the host tries to access the runtime registers of a locked module, the LPC transaction is performed according to the value of the ACCLMD field in the ACBCFG register (see Section 6.3.3 on page 127). In addition, the ACCLVIOL bit in the ACBCST register (see Section 6.3.2 on page 126) is set, indicating a lock violation attempt. Since a locked module and a disabled module behave similarly, the ACTSTAT bit in the ACBCFG register (see Section 6.3.3 on page 127) allows the software to control the behavior of the Activation bit when read through the LPC bus. When a module is locked or disabled by the Fast Disable bit in the ACBFDIS register, the ACTSTAT bit selects the value the host reads from the Activation bit. This value is either the actual value of the Activation bit or `0' (module disabled). 43 www.national.com 3.0 Device Architecture and Configuration ACCLCF1, ACCLCF2 Registers Device Configuration Access Lock xxxALOK (Continued) ACBFDIS Register Fast Disable xxxDIS ACCESS.bus Interface (PC87413, PC87417) Index 30h Activation Register Bit Module SIOCF1 Register Global Enable GLOBEN SIOCF6 Register Fast Disable xxxDIS Module Enable Runtime Registers 0 1 SWC Module SWCFDIS Register Fast Disable xxxDIS LPC Bus ACCESS.bus (PC87413, PC87417) Figure 5. Module Enable and Access Control 3.4 INTERNAL ADDRESS DECODING A full 16-bit address decoding is applied when accessing the configuration I/O space as well as the registers of the functional blocks. However, the number of configurable bits in the base address registers varies for each logical device. The lower 1, 2, 3, 4 or 5 address bits are decoded in the functional block to determine the offset of the accessed register within the logical device's I/O range of 2, 4, 8, 16 or 32 bytes, respectively. The rest of the bits are matched with the base address register to decode the entire I/O range allocated to the logical device. Therefore, the lower bits of the base address register are forced to 0 (read only), and the base address is forced to be 2, 4, 8, 16 or 32 byte-aligned, according to the size of the I/O range. The base address of the FDC, Serial Port 1, Serial Port 2, KBC and RTC are limited to the I/O address range of 00h to 7FXh only (bits 11-15 are forced to 0). The Parallel Port base address is limited to the I/O address range of 00h to 3F8h. The addresses of the non-legacy logical devices, including the SWC, GPIO and X-Bus, are configurable within the full 16-bit address range (up to FFFXh). In some special cases, other address bits are used for internal decoding (such as bit 2 in the KBC and bit 10 in the Parallel Port). The KBC has two I/O base addresses with some implied dependency between them. For more details, see the description of the base address register for each logical device. The X-Bus extension (PC87416 and PC87417) serves as a bridge from the LPC to the X-Bus. For module control and security function registers, the 16-bit base address is applied through the configuration address space. The lower five address bits are decoded in the X-Bus to access each register. The address ranges in the LPC I/O space and the LPC or FWH memory space that are bridged to the X-Bus are defined in the configuration section of the X-Bus bridge. The number of address bits used for this bridge decoding varies according to the specified zones and their sizes. See Sections 3.15.2 and 3.15.3 on pages 74ff. for details of the address range specifications. www.national.com 44 3.0 Device Architecture and Configuration (Continued) 3.5 PROTECTION The PC8741x devices provide features to protect the hardware configuration from changes made by application software running on the host. The protection is activated by the software setting a "sticky" lock bit. Each lock bit protects a group of configuration bits located either in the same register or in different registers. When the lock bit is set, the lock bit and all the protected bits become read only and cannot be further modified by the host through the LPC bus. However, for each lock bit there is an unlock bit in the ACCESS.bus Interface (ACBLKCTL register; see Section 6.3.4 on page 127). Setting an unlock bit through the ACCESS.bus resets the corresponding lock bit, thus releasing the locked configuration bits, which again become read/write bits (PC87413 and PC87417). In addition, all the lock bits are reset by power-up reset, thus unlocking the protected configuration bits. The VSBLOCK bit in the ACBLKCTL register (see Section 6.3.4 on page 127; in PC87414 and PC87416, VSBLOCK is always `0') selects which power-up reset clears the lock bits: VDD Power-Up reset (or Hardware reset) or VSB Power-Up reset. Note that the locked configuration bits are not reset by the selected power-up reset, unless the selected power-up reset corresponds with the default reset defined for the power well of the locked configuration bits (see Section 2.2 on page 33). The bit locking protection mechanism can be used optionally. The protected groups of configuration bits are described below. 3.5.1 Multiplexed Pins Configuration Lock Protects the configuration of all the multiplexed device pins. Lock bit: LOCKMCF in SIOCF1 register (Device Configuration). Unlock bit: UNLOCKM in ACBLKCTL register (ACCESS.bus Interface - PC87413 and PC87417). Protected bits: DMAWAIT, IOWAIT in SIOCF1 register and all bits of the SIOCF2, SIOCF3, SIOCF4 and SIOCF5 registers (Device Configuration). 3.5.2 GPIO Ports Configuration Lock Protects the configuration (but not the data) of all the GPIO Ports. Lock bit: LOCKGCF in SIOCF1 register (Device Configuration). Unlock bit: UNLOCKG in ACBLKCTL register (ACCESS.bus Interface - PC87413 and PC87417). Protected bits for each GPIO Port: All bits of the GPCFG1, GPEVR and GPCFG2 registers except the LOCKCFP bit (Device Configuration). 3.5.3 Fast Disable Configuration Lock Protects the Fast Disable bits for all the Legacy modules. Lock bit: LOCKFDS in SIOCF6 register (Device Configuration). Unlock bit: UNLOCKF in ACBLKCTL register (ACCESS.bus Interface - PC87413 and PC87417). Protected bits: All bits of the SIOCF6 register, except the General-Purpose Scratch bits (Device Configuration). 3.5.4 Clock Generator Configuration Lock Protects the Clock Generator configuration bits. Lock bit: LOCKCCF in CLOCKCF register (Device Configuration). Unlock bit: UNLOCKC in ACBLKCTL register (ACCESS.bus Interface). Protected bits: All bits of the CLOCKCF register (Device Configuration). 3.5.5 GPIO Ports Lock Protects the configuration and data of all the GPIO Ports. Lock bit: LOCKCFP in GPCFG1 register, for each GPIO Port (Device Configuration). Unlock bit: UNLOCKG in ACBLKCTL register (ACCESS.bus Interface - PC87413 and PC87417). Protected bits for each GPIO Port: PUPCTL, OUTTYPE and OUTENA in GPCFG1 register; all bits of the GPCFG2 register (Device Configuration); the corresponding bit (to the port pin) in the GPDO register (GPIO Ports). 45 www.national.com 3.0 Device Architecture and Configuration 3.5.6 (Continued) X-Bus I/O Map Lock (PC87416 and PC87417) Protects the configuration of the X-Bus I/O address mapping. Lock bit: LOCKIOMP in XIOCNF register (Device Configuration). Unlock bit: UNLOCKX in ACBLKCTL register (ACCESS.bus Interface - PC87417). Protected bits: All bits of the XIOCNF, XIOBA1H, XIOBA1L, XIOSIZE1, XIOBA2H, XIOBA2L and XIOSIZE2 registers (Device Configuration). 3.5.7 X-Bus Memory Map Lock (PC87416 and PC87417) Protects the configuration of the X-Bus memory address mapping. Lock bit: LOCKMMP in XMEMCNF2 register (Device Configuration). Unlock bit: UNLOCKX in ACBLKCTL register (ACCESS.bus Interface - PC87417). Protected bits: All bits of the XMEMCNF1, XMEMCNF2, XMEMBAH, XMEMBAL and XMEMSIZE registers (Device Configuration). 3.5.8 X-Bus Chip Select Configuration Lock (PC87416 and PC87417) Protects the configuration of the four X-Bus chip selects. Lock bit: LOCKXSCF in XZM0 to XZM3 register (X-Bus Extension). Unlock bit: UNLOCKX in ACBLKCTL register (ACCESS.bus Interface - PC87417). Protected bits: All bits of the XBCNF, XZCNF0 to XZCNF3 and XZM0 to XZM3 registers, except the WRSTAT bit of the XZM0-XZM3 registers (X-Bus Extension). 3.5.9 X-Bus Host Protection Lock (PC87416 and PC87417) Protects the Host Protection configuration bits for each memory block of XCS0 and XCS1 chip selects. Lock bit: LOCKXHP in all 16 indexes of the HAP0 and HAP1 registers (X-Bus Extension). Unlock bit: UNLOCKX in ACBLKCTL register (ACCESS.bus Interface - PC87417). Protected bits: HWRP and HRDP bits of all 16 indexes of the HAP0 and HAP1 registers (X-Bus Extension). 3.5.10 SWC Timers Protection Lock Protects the access to the reset of the Power Active timers in the SWC module. Lock bit: LOCK_TMRRST in PWTMRCTL register (System Wake-Up Control). Unlock bit: UNLOCKS in ACBLKCTL register (ACCESS.bus Interface - PC87413 and PC87417). Protected bits: All bits of the PWTMRCTL register (System Wake-Up Control). 3.5.11 SWC Sleep State Configuration Lock Protects the Sleep Type encoding configuration in the SWC module. Lock bit: LOCK_SLP_ENC in SLP_ST_CFG register (System Wake-Up Control). Unlock bit: UNLOCKS in ACBLKCTL register (ACCESS.bus Interface - PC87413 and PC87417). Protected bits: All bits of the SLP_ST_CFG and S0_SLP_TYP to S5_SLP_TYP registers (System Wake-Up Control). 3.5.12 CMOS RAM Access Lock Protects access lock configuration bits of the CMOS Standard and Extended RAM. Lock bits: BLSTR, BLRWR, BLEXRWR, BLEXRRD and BLEXR in RLR register (Real-Time Clock). Unlock bit: UNLOCKR in ACBLKCTL register (ACCESS.bus Interface - PC87413 and PC87417). Protected bits: Standard and Extended CMOS RAM bits for read and/or write access by the host (Real-Time Clock; see Section 3.16.3 on page 87). www.national.com 46 3.0 Device Architecture and Configuration (Continued) 3.6 REGISTER TYPE ABBREVIATIONS The following abbreviations are used to indicate the Register Type: R/W = Read/Write. R = Read from a specific register (write to the same address is to a different register). W = Write (see above). RO = Read Only. WO = Write Only. Reading from the bit returns 0. R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect. R/W1S = Read/Write 1 to Set. Writing 1 to a bit sets its value to 1. Writing 0 has no effect. In the registers below, use one of the following methods to handle the Reserved bits: Write 0 to reserved bits, unless another "required value" is specified. This method can be used for registers containing bits of all types. Use read-modify-write to preserve the values of the reserved bits. This method can be used only for registers containing bits of R/W, RO, R/W1C and R/W1S types. 3.7 SERVERI/O CONFIGURATION REGISTERS This section describes the ServerI/O configuration and ID registers (those registers with first level indexes in the range of 20h - 2Eh). See Table 16 for a summary and directory of these registers. Table 16. ServerI/O Configuration Registers Index Mnemonic Register Name Power Well Type Section 20h SID ServerI/O ID VSB RO 3.7.1 21h SIOCF1 ServerI/O Configuration 1 VSB Varies per bit 3.7.2 22h SIOCF2 ServerI/O Configuration 2 VSB R/W or RO 3.7.3 23h SIOCF3 ServerI/O Configuration 3 VSB R/W or RO 3.7.4 24h SIOCF4 ServerI/O Configuration 4 VSB R/W or RO 3.7.5 25h SIOCF5 ServerI/O Configuration 5 VSB R/W or RO 3.7.6 26h SIOCF6 ServerI/O Configuration 6 VSB Varies per bit 3.7.7 27h SRID ServerI/O Revision ID VSB RO 3.7.8 28h SIOCF8 ServerI/O Configuration 8 VSB R/W 3.7.9 29h CLOCKCF Clock Generator Configuration VSB Varies per bit 3.7.10 VPP R/W or RO 3.7.11 2Ah ACBCF ACCESS.bus Configuration 2Bh - Reserved for National use 2Fh 47 www.national.com 3.0 Device Architecture and Configuration 3.7.1 (Continued) ServerI/O ID Register (SID) This register contains the identity number of the device family. The PC8741x family is identified by the value EEh. Power Well: VSB Location: Index 20h Type: RO Bit 7 6 5 4 3 Name Family ID Reset EEh Bit 7-0 3.7.2 2 1 0 Description Family ID. These bits identify a family of devices with similar functionality but with different implemented options. ServerI/O Configuration 1 Register (SIOCF1) Power Well: VSB Location: Index 21h Type: Varies per bit Bit 7 6 Name LOCKMCF LOCKGCF Reset 0 0 Bit 5 4 3 1 0 Reserved 0 2 IOWAIT Type 0 1 0 HSWRST GLOBEN 0 1 Description 7 R/W1S LOCKMCF (Lock Multiplexing Configuration). When set to 1, this bit locks the configuration of registers SIOCF1, SIOCF2, SIOCF3, SIOCF4 and SIOCF5 by disabling writing to all bits in these registers (including the LOCKMCF bit itself), except for the LOCKGCF, HSWRST and GLOBEN bits of SIOCF1. Once set, this bit can be cleared either by VDD Power-Up reset (or Hardware reset) or by VSB Power-Up reset, according to the VSBLOCK bit in the ACBLKCTL register (see Section 6.3.4 on page 127). In addition, this bit is cleared by setting the UNLOCKM bit in the ACBLKCTL register (PC87413 and PC787417). 0: R/W bits are enabled for write (default) 1: All bits are RO 6 R/W1S LOCKGCF (Lock GPIO Pins Configuration). When set to 1, this bit locks the configuration registers of all the GPIO pins (see Section 3.14.2 on page 70) by disabling writing to all their bits (including the LOCKGCF bit itself). Once set, this bit can be cleared either by VDD Power-Up reset (or Hardware reset) or by VSB Power-Up reset, according to the VSBLOCK bit in the ACBLKCTL register (see Section 6.3.4 on page 127). In addition, this bit is cleared by setting the UNLOCKG bit in the ACBLKCTL register (PC87416 and PC87417). 0: R/W bits are enabled for write (default) 1: All bits are RO 5-4 3-2 Reserved (must be `01') R/W or IOWAIT (Number of I/O Wait States). These bits set the number of wait states for I/O transactions RO through the LPC bus. www.national.com Bits 5 4 Number of wait states 0 0 1 1 0 (Zero - default) 2 6 12 0 1 0 1 48 3.0 Device Architecture and Configuration Bit Type 1 R/W 0 (Continued) Description HSWRST (Host Software Reset). When set to 1, this bit triggers the Host Software reset sequence (see Section 2.2.6 on page 34), after which it returns to 0. Read always returns 0. This bit is not influenced by the value of LOCKMCF. 0: Inactive (default) 1: Trigger the Host Software reset sequence R/W or GLOBEN (Global Device Enable). When set to 1, this bit allows the operation of all the logical devices RO of the PC8741x device (see Table 9 on page 38). The behavior of the different devices is explained in Section 3.3. When cleared, this bit forces all logical devices to be disabled simultaneously by writing to a single bit. 0: All logical devices in the PC8741x device are forced to be disabled and their resources are released 1: Each logical device may be enabled; see Section 3.3.1 on page 42 (default) 3.7.3 ServerI/O Configuration 2 Register (SIOCF2) Power Well: VSB Location: Index 22h Type: R/W or RO Bit 7 6 5 4 3 2 1 0 Name WDOMUX Reserved NOKBC VDDFLMUX P17MUX P16MUX P12MUX CLKRNMUX Reset 0 0 1 0 0 0 0 0 Bit Description 7 WDOMUX (WATCHDOG Out Multiplex Control). Selects the function connected to pin 55. 0: GPO64 port - GPIO (default) 1: WDO - SWC 6 Reserved. 5 NOKBC (Keyboard and Mouse Multiplex Control). Selects the function connected to pins 125-128. 0: GPIO01-GPIO04 ports - GPIO 1: KBCLK, KBDAT, MCLK, MDAT - KBC (default) 4 VDDFLMUX (VDDFELL Multiplex Control). Selects the function connected to pin 54. 0: GPIO54 - GPIO (default) 1: VDDFELL - SWC 3 P17MUX (P17 Multiplex Control). Selects the function connected to pin 66. 0: MTR1 - FDC (default) 1: P17 port - KBC 2 P16MUX (P16 Multiplex Control). Selects the function connected to pin 70. 0: DR1 - FDC (default) 1: P16 port - KBC 1 P12MUX (P12 Multiplex Control). Selects the function connected to pin 121. 0: PPDIS - Parallel Port (default)1 1: P12 port - KBC (internally, PPDIS is set to 0; Parallel Port enabled) 0 CLKRNMUX (CLKRUN Multiplex Control). Selects the function connected to pin 124. 0: GPIO00 port - GPIO (default) 1: CLKRUN - LPC Interface 1. If this feature is not used, either select the P12 port or connect an external 3.3 K pull-down resistor to pin 121. If the function connected to the pin is PPDIS and the pin is left unconnected, the output signals of the parallel port will float. 49 www.national.com 3.0 Device Architecture and Configuration 3.7.4 (Continued) ServerI/O Configuration 3 Register (SIOCF3) Power Well: VSB Location: Index 23h Type: R/W or RO Bit 7 6 5 Name EXTSTMUX SCIMUX SMIMUX Reset EXT_ST _SELECT1 0 0 4 3 2 PWBTOMUX PWBTIMUX SLBTIMUX 0 0 1 0 LED2MUX LED1MUX 0 0 0 1. The reset value is the same as the value set to the EXT_ST_SELECT bit in the SLP_ST_CFG register (see Section 9.3.31 on page 199). Bit Description 7 EXTSTMUX (External PM State Multiplex Control). Selects the function connected to pins 52 and 53. 0: GPIOE46, GPIOE47 ports - GPIO (internally, SLPS3 and SLPS5 are both set to 1; not in S3-S5 states) 1: SLPS3, SLPS5 - SWC 6 SCIMUX (SIOSCI Multiplex Control). Selects the function connected to pin 38. 0: GPIO52 port - GPIO (default) 1: SIOSCI - SWC 5 SMIMUX (SIOSMI Multiplex Control). Selects the function connected to pin 37. 0: GPIO51 port - GPIO (default) 1: SIOSMI - SWC 4 PWBTOMUX (PWBTOUT Multiplex Control). Selects the function connected to pin 49. 0: PWBTOUT - SWC (default) 1: GPIOE43 port - GPIO 3 PWBTIMUX (PWBTIN Multiplex Control). Selects the function connected to pin 36. 0: PWBTIN - SWC (default) 1: GPIO50 port - GPIO (internally, PWBTIN is set to 1; Power button not active) 2 SLBTIMUX (SLBTIN Multiplex Control). Selects the function connected to pin 35. 0: GPIOE42 port - GPIO (default; internally, SLBTIN is set to 1; Sleep button not active) 1: SLBTIN - SWC 1 LED2MUX (LED2 Multiplex Control). Selects the function connected to pin 51. 0: GPIOE45 port - GPIO (default) 1: LED2 - SWC 0 LED1MUX (LED1 Multiplex Control). Selects the function connected to pin 50. 0: GPIOE44 port - GPIO (default) 1: LED1 - SWC www.national.com 50 3.0 Device Architecture and Configuration 3.7.5 (Continued) ServerI/O Configuration 4 Register (SIOCF4) Power Well: VSB Location: Index 24h Type: R/W or RO Bit 7 Name HFCKMUX Reset 0 Bit 6 5 LFCKMUX 0 0 4 3 2 1 0 Reserved SMI2IRQ2 NOXBUS NOADDIR XRDYMUX 0 0 Strap Strap Strap Description 7 HFCKMUX (HFCKOUT Multiplex Control). Selects the function connected to pin 13. 0: HFCKOUT - Clock Generator (default) 1: GPIO07 port - GPIO 6-5 LFCKMUX (LFCKOUT Multiplex Control). Selects the function connected to pin 45. Bits 6 5 Function 0 0 1 1 GPIO53 port - GPIO (default; internally, MSEN0 is set to 1) LFCKOUT - Clock Generator (internally, MSEN0 is set to 1) MSEN0 - FDC Reserved 0 1 0 1 4 Reserved. 3 SMI2IRQ2 (SMI to IRQ2 Enable). This bit enables the SMI interrupt to the IRQ2 slot of the SERIRQ. 0: Disabled (default) 1: Enabled (the SMI interrupt is shared with the interrupt source selected to IRQ2 - see Table 13 on page 40) 2 NOXBUS (Basic X-Bus Multiplex Control). Selects the function connected to pins 14-19 and 24-31. The default value is set according to the XCNF2 strap, sampled at VSB Power-Up reset. 0: GPIO20-GPIO25, GPIO30-GPIO37 ports - GPIO 1: XRD_XEN, XWR_XRW, XA3-XA0, XD7-XD0 - X-Bus (PC87416 and PC87417) 1 NOADDIR (XA11-4 Multiplex Control). Selects the function connected to pins 1-8. The default value is set by the XCNF1 strap if XCNF2 = 1 or to 0 if XCNF2 = 0. The XCNF2 and XCNF1 straps are sampled at VSB Power-Up reset. 0: GPIOE10-GPIOE17 ports - GPIO 1: XA11-XA4 - X-Bus (PC87416 and PC87417) 0 XRDYMUX (XRDY Multiplex Control). Selects the function connected to pin 9. The default value is set by the XCNF0 strap if XCNF2 = 1 or to 0 if XCNF2 = 0. The XCNF2 and XCNF0 straps are sampled at VSB PowerUp reset. 0: GPIO05 port - GPIO (internally, XRDY is set to 1; device ready) 1: XRDY - X-Bus (PC87416 and PC87417) 51 www.national.com 3.0 Device Architecture and Configuration 3.7.6 (Continued) ServerI/O Configuration 5 Register (SIOCF5) Power Well: VSB Location: Index 25h Type: R/W or RO Bit 7 Name 6 5 4 3 XIRQMUX XSTB2MUX XSTB1MUX XSTB0MUX XCS3MUX Reset 0 Strap Strap Bit Strap 0 2 1 0 XCS2MUX XCS1MUX XCS0MUX 0 0 Strap Description 7 XIRQMUX (XIRQ Multiplex Control). Selects the function connected to pin 10. 0: GPIO06 port - GPIO (default; internally, XIRQ is set to 0; Interrupt not active) 1: XIRQ - X-Bus (PC87416 and PC87417) 6 XSTB2MUX (XSTB2 Multiplex Control). Selects the function connected to pin 32. The default value is set to 0 if XCNF2 = 1 or to 1 if XCNF2 = 0. The XCNF2 strap is sampled at VSB Power-Up reset. 0: XSTB2 - X-Bus (PC87416 and PC87417) 1: GPO60 port - GPIO 5 XSTB1MUX (XSTB1 Multiplex Control). Selects the function connected to pin 33. The default value is set to 0 if XCNF2 = 1 or to 1 if XCNF2 = 0. The XCNF2 strap is sampled at VSB Power-Up reset. 0: XSTB1 - X-Bus (PC87416 and PC87417) 1: GPO61 port - GPIO 4 XSTB0MUX (XSTB0 Multiplex Control). Selects the function connected to pin 34. The default value is set to 0 if XCNF2 = 1 or to 1 if XCNF2 = 0. The XCNF2 strap is sampled at VSB Power-Up reset. 0: XSTB0 - X-Bus (PC87416 and PC87417) 1: GPO62 port - GPIO 3 XCS3MUX (XCS3 Multiplex Control). Selects the function connected to pin 20. 0: GPIOE40 port - GPIO (default) 1: XCS3 - X-Bus (PC87416 and PC87417) 2 XCS2MUX (XCS2 Multiplex Control). Selects the function connected to pin 21. 0: GPIOE41 port - GPIO (default) 1: XCS2 - X-Bus (PC87416 and PC87417) 1 XCS1MUX (XCS1 Multiplex Control). Selects the function connected to pin 22. 0: GPIO26 port - GPIO (default) 1: XCS1 - X-Bus (PC87416 and PC87417) 0 XCS0MUX (XCS0 Multiplex Control). Selects the function connected to pin 23. The default value is set to 0 if XCNF2 = 1 or to 1 if XCNF2 = 0. The XCNF2 strap is sampled at VSB Power-Up reset. 0: XCS0 - X-Bus (PC87416 and PC87417) 1: GPIO27 port - GPIO www.national.com 52 3.0 Device Architecture and Configuration 3.7.7 (Continued) ServerI/O Configuration 6 Register (SIOCF6) This register provides a fast way to disable one or more modules, without having to access the Activate register of each (see Section 3.3.1 on page 42). Power Well: VSB Location: Index 26h Type: Varies per bit Bit 7 Name LOCKFDS Reset Bit 7 0 6 5 General-Purpose Scratch 0 0 4 3 2 1 0 Reserved SER1DIS SER2DIS PARPDIS FDCDIS 0 0 0 0 0 Type Description R/W1S LOCKFDS (Lock Fast Disable Configuration). When set to 1, this bit locks itself, the SER1DIS, SER2DIS, PARPDIS and FDCDIS bits in this register and the GLOBEN bit in the SIOCF1 register by disabling writing to all these bits. Once set, this bit can be cleared either by VDD Power-Up reset (or Hardware reset) or by VSB Power-Up reset, according to the VSBLOCK bit in the ACBLKCTL register (see Section 6.3.4 on page 127). In addition, this bit is cleared by setting the UNLOCKF bit in the ACBLKCTL register (PC87413 and PC87417). 0: R/W bits are enabled for write (default) 1: All bits are RO 6-5 R/W 4 - General-Purpose Scratch. Reserved. 3 R/W or SER1DIS (Serial Port 1 Disable). When set to 1, this bit forces the Serial Port 1 module to be disabled RO (and its resources released) regardless of the actual setting of its Activation bit (index 30). 0: Enabled or Disabled, according to Activation bit (default) 1: Disabled 2 R/W or SER2DIS (Serial Port 2 Disable). When set to 1, this bit forces the Serial Port 2 module to be disabled RO (and its resources released) regardless of the actual setting of its Activation bit (index 30). 0: Enabled or Disabled, according to Activation bit (default) 1: Disabled 1 R/W or PARPDIS (Parallel Port Disable). When set to 1, this bit forces the Parallel Port module to be disabled RO (and its resources released) regardless of the actual setting of its Activation bit (index 30). 0: Enabled or Disabled, according to Activation bit (default) 1: Disabled 0 R/W or FDCDIS (Floppy Disk Controller Disable). When set to 1, this bit forces the Floppy Disk Controller RO module to be disabled (and its resources released) regardless of the actual setting of its Activation bit (index 30). 0: Enabled or Disabled, according to Activation bit (default) 1: Disabled 53 www.national.com 3.0 Device Architecture and Configuration 3.7.8 (Continued) ServerI/O Revision ID Register (SRID) This register contains the ID number of the specific family member (Chip ID) and the chip revision number (Chip Rev). Power Well: VSB Location: Index 27h Type: RO Bit 7 Name 6 5 4 3 Chip ID (N/A) Reset X X 2 1 0 X X Chip Rev X Bit X X X Description 7-5 Chip ID (N/A). These bits identify a specific device of a family. Note: Not applicable for the PC8741x family 4-0 Chip Rev. These bits identify the device revision. The value is incremented on each revision. 3.7.9 ServerI/O Configuration 8 Register (SIOCF8) Power Well: VSB Location: Index 28h Type: R/W Bit 7 Name Reset 0 Bit 7-5 6 5 Reserved 0 4 MIRQ2SMI 0 3 2 1 KIRQ2SMI KBCP12SMI GPIO2SMI 0 0 0 0 0 Reserved 0 Description Reserved. 4 MIRQ2SMI (Mouse IRQ to SMI Enable). Controls the routing of the Mouse interrupt to the SIOSMI pin. 0: Disabled (default) 1: Enabled 3 KIRQ2SMI (Keyboard IRQ to SMI Enable). Controls the routing of the Keyboard interrupt to the SIOSMI pin. 0: Disabled (default) 1: Enabled 2 KBCP12SMI (KBC P12 to SMI Enable). Controls the routing of the P12 port of the KBC to the SIOSMI pin. 0: Disabled (default) 1: Enabled 1 GPIO2SMI (GPIO IRQ to SMI Enable). Controls the routing of the GPIO event (see Section 7.3.2 on page 137) to the SIOSMI pin. 0: Disabled (default) 1: Enabled 0 Reserved. www.national.com 54 3.0 Device Architecture and Configuration (Continued) 3.7.10 Clock Generator Configuration Register (CLOCKCF) Power Well: VSB Location: Index 29h Type: Varies per bit Bit 7 6 5 4 3 Name LOCKCCF LFCKSEL HFCKDIS CKVALID CKIN48 Reset 0 0 0 0 Strap Bit Type 2 1 0 HFCKDIV 0 0 See Table Description 7 R/W1S LOCKCCF (Lock Clock Configuration). When set to 1, this bit locks the configuration register CLOCKCF by disabling writing to all its bits (including to the LOCKCCF bit itself). Once set, this bit can be cleared either by VDD Power-Up reset (or Hardware reset) or by VSB Power-Up reset, according to the VSBLOCK bit in the ACBLKCTL register (see Section 6.3.4 on page 127). In addition, this bit is cleared by setting the UNLOCKC bit in the ACBLKCTL register (PC87413 and PC87417). 0: R/W bits are enabled for write (default) 1: All bits are RO 6 R/W or LFCKSEL (Low Frequency Clock Select). Selects the frequency generated at the LFCKOUT pin. RO 0: 32.768 KHz (default) 1: 1 Hz 5 R/W or HFCKDIS (High Frequency Clock Disable). Disables both the HFCKOUT output and the RO programmable divider to save power. 0: Enabled (default) 1: Disabled (set low) 4 RO CKVALID (Valid Multiplier Clock Status). This bit indicates the status of output from the Frequency Multiplier (the internal clock signal). 0: Internal clock frozen (default) 1: Internal clock active (stable and toggling) 3 RO CKIN48 (Clock Input Available). This bit indicates the value of the CKIN48 strap input, sampled at VSB Power-Up reset. 0: No clock is available at the CLKIN pin (pin 56 connected to GPIO55 ) 1: A 48 MHz clock is available at the CLKIN pin (pin 56 connected to CLKIN) 2-0 R/W or HFCKDIV (High Frequency Clock Divisor). These bits define the value by which the 48 MHz or 40 RO MHz internal clock frequency is divided to generate the HFCKOUT signal. The resulting frequency depends on the value of the CKIN48 bit (see Table 7 on page 36). Bits 2 1 0 Function 0 0 0 0 1 1 1 1 Divide by 1 (default for CKIN48 = 1) Divide by 2 (default for CKIN48 = 0) Divide by 3 Divide by 4 Divide by 6 Divide by 8 Divide by 12 Divide by 16 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 55 www.national.com 3.0 Device Architecture and Configuration (Continued) 3.7.11 ACCESS.bus Configuration (ACBCF) Register This register is relevant only for the PC87413 and PC87417. In the PC87414 and PC87416, all bits are held at their default value. This register may be written only once. All eight bits must be updated in a single write operation, after which the data in the register becomes read only. The register is cleared and the write-lock released only by VPP Power-Up reset. Power Well: VPP Location: Index 2Ah Type: R/W or RO Bit 7 Name ACBPUEN Reset 0 6 5 4 3 2 1 0 0 0 0 ACBSADD 0 0 0 0 Bit Description 7 ACBPUEN (ACCESS.bus Signals Pull-Up Enable). This bit controls the internal pull-up resistors connected to the ACBCLK and ACBDAT signals (see Section 1.5 on page 29). 0: Disconnected (default) 1: Connected 6-0 ACBSADD (ACCESS.bus Slave Address). This field defines the slave address on the ACCESS.bus for the PC8741x devices. This address, once programmed by the host, is preserved as long as the VPP power is active (VSB or VBAT). The 7-bit slave address is used to access the PC8741x devices (see Section 6.2.6 on page 118). A non-zero value read from this field indicates that ACBSADD contains a valid slave address. www.national.com 56 3.0 Device Architecture and Configuration (Continued) 3.8 FLOPPY DISK CONTROLLER (FDC) CONFIGURATION 3.8.1 General Description The generic FDC is a standard FDC with a digital data separator and is DP8473 and N82077 software compatible. The PC8741x FDC supports 14 of the 17 standard FDC signals described in the generic Floppy Disk Controller (FDC) chapter, including (see Section 10.1 on page 219): * FM and MFM modes are supported. To select either mode, set bit 6 of the first command byte when writing to/reading from a diskette, where: 0 = FM mode 1 = MFM mode * A logic 1 is returned during LPC I/O read cycles by all register bits reflecting the state of floating (TRI-STATE) FDC pins. Exceptions to standard FDC are: * * Automatic media sense using the MSEN1 signal is not supported DRATE1 is not supported. The FDC functional block registers are shown in Section 10.1 on page 219. All these registers are VDD powered. 3.8.2 Logical Device 0 (FDC) Configuration Table 17 lists the configuration registers that affect the FDC. Only the last two registers (F0h and F1h) are described here. See Section 3.2.3 on page 39 for descriptions of the other configuration registers. All these registers are VDD powered. Table 17. FDC Configuration Registers Index Configuration Register or Action Type Power Well Reset 30h Activate (see Section 3.3.1 on page 42). R/W VDD 00h 60h Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b. R/W VDD 03h 61h Base Address LSB register. Bits 2 and 0 (for A2 and A0) are read only, 00b. R/W VDD F2h 70h Interrupt Number and Wake-Up on IRQ Enable register. R/W VDD 06h 71h Interrupt Type. Bit 1 is read/write; other bits are read only. R/W VDD 03h 74h DMA Channel Select. R/W VDD 02h 75h Report no second DMA assignment. RO VDD 04h F0h FDC Configuration register. R/W VDD 24h F1h Drive ID register. R/W VDD 00h 57 www.national.com 3.0 Device Architecture and Configuration 3.8.3 (Continued) FDC Configuration Register This register is reset by hardware to 24h. Power Well: VDD Location: Index F0h Type: R/W Bit 7 6 5 4 3 Name Four-Drive Encode Enable TDR Register Mode DENSEL Polarity Control FDC 2Mbps Enable Write Protect Reset 0 0 1 0 0 Bit 2 1 PC-AT or PS/2 Drive Reserved Mode Select 1 0 0 TRI-STATE Control 0 Description 7 Four-Drive Encode Enable. 0: Two floppy drives are directly controlled by DR1-0, MTR1-0 (default) 1: Four floppy drives are controlled with the aid of an external decoder 6 TDR Register Mode. 0: PC-AT-Compatible Drive mode; i.e., bits 7-2 of the TDR are 111111b (default) 1: Enhanced Drive mode 5 DENSEL Polarity Control. 0: Active low for 500 Kbps or 1 or 2 Mbps data rates 1: Active high for 500 Kbps or 1 or 2 Mbps data rates (default) 4 FDC 2Mbps Enable. This bit is set only when a 2 Mbps drive is used. 0: 2 Mbps disabled and the FDC clock is 24 MHz (default) 1: 2 Mbps enabled and the FDC clock is 48 MHz 3 Write Protect. This bit enables forcing of write protect functionality by software. When set, writes to the floppy disk drive are disabled. This effect is identical to an active WP signal. 0: Write protected according to WP signal (default) 1: Write protected regardless of value of WP signal 2 PC-AT or PS/2 Drive Mode Select. 0: PS/2 Drive mode 1: PC-AT Drive mode (default) 1 Reserved. 0 TRI-STATE Control. When enabled and the device is inactive (see Section 3.3.1 on page 42), the logical device output pins are in TRI-STATE. 0: Disabled (default) 1: Enabled www.national.com 58 3.0 Device Architecture and Configuration 3.8.4 (Continued) Drive ID Register This register is reset by hardware to 00h. This register controls bits 5 and 4 of the TDR register in Enhanced mode. Power Well: VDD Location: Index F1h Type: R/W Bit 7 6 0 0 Name 5 4 3 0 0 0 Reserved Reset Bit 2 1 0 0 Drive 1 ID 0 Drive 0 ID 0 Description 7-4 Reserved. 3-2 Drive 1 ID. When drive 1 is accessed, these bits are reflected on bits 5-4 of the TDR register, respectively. 1-0 Drive 0 ID. When drive 0 is accessed, these bits are reflected on bits 5-4 of the TDR register, respectively. Usage Hints: Some BIOS implementations support automatic media sense FDDs, in which case bit 5 of the TDR register in the Enhanced mode is interpreted as valid media sense when it is cleared to 0. If drive 0 and/or drive 1 do not support automatic media sense, bits 1 and/or 3 of the Drive ID register must be set to 1 (to indicate non-valid media sense). When Drive 0 or Drive 1 is selected, the Drive ID bit is reflected on bit 5 of the TDR register in Enhanced mode. 59 www.national.com 3.0 Device Architecture and Configuration (Continued) 3.9 PARALLEL PORT (PP) CONFIGURATION 3.9.1 General Description The PC8741x Parallel Port supports all IEEE1284 standard communication modes: Compatibility (also known as Standard or SPP), Bi-directional (known also as PS/2), FIFO, EPP (also known as mode 4) and ECP (with an optional Extended ECP mode). The Parallel Port includes two groups of runtime registers, as follows (see Section 10.2 on page 221): * A group of 21 registers at first level offset, sharing 14 entries. Three of this registers (at offsets 403h, 404h and 405h) are used only in the Extended ECP mode. * A group of four registers, used only in the Extended ECP mode, accessed by a second level offset. The desired mode is selected by the ECR runtime register (offset 402h). The selected mode determines which runtime registers are used and which address bits are used for the base address. The FDC functional block registers are shown in Section 10.2 on page 221. All these registers are VDD powered. 3.9.2 Logical Device 1 (PP) Configuration Table 18 lists the configuration registers that affect the Parallel Port. Only the last register (F0h) is described here. See Section 3.2.3 on page 39 for descriptions of the other configuration registers. All these registers are VDD powered. Table 18. Parallel Port Configuration Registers Index Configuration Register or Action Type Power Well Reset 30h Activate (see Section 3.3.1 on page 42). R/W VDD 00h 60h Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b. Bit 2 (for A10) must be 0b. R/W VDD 02h 61h Base Address LSB register. Bits 1 and 0 (A1 and A0) are read only, 00b. For ECP mode 4 (EPP) or when using the Extended registers, bit 2 (A2) must also be 0b. R/W VDD 78h 70h Interrupt Number and Wake-Up on IRQ Enable register. R/W VDD 07h 71h Interrupt Type: Bits 7-2 are read only. Bit 1 is a read/write bit. Bit 0 is read only. It reflects the interrupt type dictated by the Parallel Port operation mode. This bit is set to 1 (level interrupt) in Extended mode and cleared (edge interrupt) in all other modes. R/W VDD 02h 74h DMA Channel Select. R/W VDD 04h 75h Report no second DMA assignment. RO VDD 04h F0h Parallel Port Configuration register. R/W VDD F2h www.national.com 60 3.0 Device Architecture and Configuration 3.9.3 (Continued) Parallel Port Configuration Register This register is reset by hardware to F2h. Power Well: VDD Location: Index F0h Type: R/W Bit 7 6 5 Name Parallel Port Mode Select Reset 1 Bit 7-5 4 3-2 1 1 4 3 Extended Register Access 1 2 Reserved 0 0 1 0 Power Mode Control TRI-STATE Control 1 0 Description Parallel Port Mode Select. 000: SPP-Compatible mode. PD7-0 are always output signals 001: SPP Extended mode. PD7-0 direction is controlled by software 010: EPP 1.7 mode 011: EPP 1.9 mode 100: ECP mode (IEEE1284 register set), with no support for EPP mode 101: Reserved 110: Reserved 111: ECP mode (IEEE1284 register set), with EPP mode selectable as mode 4 (default) Selection of EPP 1.7 or 1.9 in ECP mode 4 is controlled by bit 4 of the Control2 configuration register of the parallel port at offset 02h. Note: Before setting bits 7-5, enable the parallel port and set CTR/DCR (at base address + 2) to C4h. Extended Register Access. 0: Registers at base (address) + 403h, base + 404h and base + 405h are not accessible (reads and writes are ignored) 1: Registers at base (address) + 403h, base + 404h and base + 405h are accessible. This option supports runtime configuration within the Parallel Port address space (default). Reserved. 1 Power Mode Control. When the logical device is active: 0: Parallel port clock disabled. ECP modes and EPP time-out are not functional when the logical device is active. Registers are maintained. 1: Parallel port clock enabled. All operation modes are functional when the logical device is active (default). 0 TRI-STATE Control. When enabled and the device is inactive (see Section 3.3.1 on page 42), the logical device output pins are in TRI-STATE. 0: Disabled (default) 1: Enabled 61 www.national.com 3.0 Device Architecture and Configuration (Continued) 3.10 SERIAL PORT 2 CONFIGURATION 3.10.1 General Description Serial Port 2 provides UART functionality by supporting serial data communication with remote peripheral device or modem. The functional blocks can function as a standard 16450 or 16550 or as an Extended UART. Serial Port 2 includes four register banks, each containing eight runtime registers, as shown in Section 10.3 on page 224. All these registers are VDD powered. 3.10.2 Logical Device 2 (SP2) Configuration Table 19 lists the configuration registers that affect Serial Port 2. Only the last register (F0h) is described here. See Section 3.2.3 on page 39 for descriptions of the other configuration registers. All these registers are VDD powered. Table 19. Serial Port 2 Configuration Registers Index Configuration Register or Action Type Power Well Reset 30h Activate (see Section 3.3.1 on page 42). R/W VDD 00h 60h Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b. R/W VDD 02h 61h Base Address LSB register. Bit 2-0 (for A2-0) are read only, 000b. R/W VDD F8h 70h Interrupt Number and Wake-Up on IRQ Enable register. R/W VDD 03h 71h Interrupt Type. Bit 1 is R/W; other bits are read only. R/W VDD 03h 74h Report no DMA Assignment. RO VDD 04h 75h Report no DMA Assignment. RO VDD 04h F0h Serial Port 2 Configuration register. R/W VDD 02h www.national.com 62 3.0 Device Architecture and Configuration (Continued) 3.10.3 Serial Port 2 Configuration Register This register is reset by hardware to 02h. Power Well: VDD Location: Index F0h Type: R/W Bit Name 7 6 Bank Select Enable Fast TRI-STATE 0 0 Reset Bit 5 4 3 Reserved 0 0 0 2 1 0 Busy Indicator Power Mode Control TRI-STATE Control 0 1 0 Description 7 Bank Select Enable. Enables bank switching for Serial Port 2. 0: All attempts to access the extended registers in Serial Port 2 are ignored (default) 1: Enables bank switching for Serial Port 2 6 Fast TRI-STATE. When set, the logical device output pins are in TRI-STATE and the input pins are internally held at inactive level (high), regardless of the device activation (Activation bit - Section 3.3.1 on page 42; SER2DIS - Section 3.7.7 on page 53; GLOBEN - Section 3.7.2 on page 48; SER2DIS - Section 9.3.8 on page 184; SER2ALOK - Section 6.3.7 on page 131; SER2DIS - Section 6.3.5 on page 129). 0: Device pins active (default) 1: Device pins disabled 5-3 Reserved. 2 Busy Indicator. This read only bit can be used by power management software to decide when to power-down the Serial Port 2 logical device. 0: No transfer in progress (default) 1: Transfer in progress 1 Power Mode Control. When the logical device is active in: 0: Low-Power mode Serial Port 2 clock disabled. The output signals are set to their default states. The RI input signal can be programmed to generate an interrupt. Registers are maintained (unlike Active bit in index 30 that also prevents access to Serial Port 2 registers). 1: Normal Power mode Serial Port 2 clock enabled. Serial Port 2 is functional when the logical device is active (default). 0 TRI-STATE Control. When enabled and the device is inactive (see Section 3.3.1 on page 42), the logical device output pins are in TRI-STATE. 0: Disabled (default) 1: Enabled 63 www.national.com 3.0 Device Architecture and Configuration (Continued) 3.11 SERIAL PORT 1 CONFIGURATION 3.11.1 General Description Serial Port 1 provides UART functionality by supporting serial data communication with remote peripheral device or modem. The functional blocks can function as a standard 16450 or 16550 or as an Extended UART. Serial Port 1 includes the same register banks and runtime registers as Serial Port 2 (see Section 10.3 on page 224). All the registers are VDD powered. 3.11.2 Logical Device 3 (SP1) Configuration Table 20 lists the configuration registers that affect Serial Port 1. Only the last register (F0h) is described here. See Section 3.2.3 on page 39 for descriptions of the other configuration registers. All these registers are VDD powered. Table 20. Serial Port 1 Configuration Registers Index Configuration Register or Action Type Power Well Reset 30h Activate (see Section 3.3.1 on page 42). R/W VDD 00h 60h Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b. R/W VDD 03h 61h Base Address LSB register. Bit 2-0 (for A2-0) are read only, 000b. R/W VDD F8h 70h Interrupt Number and Wake-Up on IRQ Enable register. R/W VDD 04h 71h Interrupt Type. Bit 1 is R/W; other bits are read only. R/W VDD 03h 74h Report no DMA Assignment. RO VDD 04h 75h Report no DMA Assignment. RO VDD 04h F0h Serial Port 1 Configuration register. R/W VDD 02h www.national.com 64 3.0 Device Architecture and Configuration (Continued) 3.11.3 Serial Port 1 Configuration Register This register is reset by hardware to 02h. Power Well: VDD Location: Index F0h Type: R/W Bit 7 Name Bank Select Enable Reset 0 Bit 6 5 Fast TRI-STATE 0 4 3 Reserved 0 0 0 2 1 0 Busy Indicator Power Mode Control TRI-STATE Control 0 1 0 Description 7 Bank Select Enable. Enables bank switching for Serial Port 1. 0: All attempts to access the extended registers in Serial Port 1 are ignored (default) 1: Enables bank switching for Serial Port 1 6 Fast TRI-STATE. When set, the logical device output pins are in TRI-STATE and the input pins are internally held at inactive level (high), regardless of the device activation (Activation bit - Section 3.3.1 on page 42; SER1DIS - Section 3.7.7 on page 53; GLOBEN - Section 3.7.2 on page 48; SER1DIS - Section 9.3.8 on page 184; SER1ALOK - Section 6.3.7 on page 131; SER1DIS - Section 6.3.5 on page 129). 0: Device pins active (default) 1: Device pins disabled 5-3 Reserved. 2 Busy Indicator. This read only bit can be used by power management software to decide when to power-down the Serial Port 1 logical device. 0: No transfer in progress (default) 1: Transfer in progress 1 Power Mode Control. When the logical device is active in: 0: Low-Power mode Serial Port 1 clock disabled. The output signals are set to their default states. The RI input signal can be programmed to generate an interrupt. Registers are maintained (unlike Active bit in Index 30;s which also prevents access to Serial Port 1 registers). 1: Normal Power mode Serial Port 1 clock enabled. Serial Port 1 is functional when the logical device is active (default). 0 TRI-STATE Control. When enabled and the device is inactive (see Section 3.3.1 on page 42), the logical device output pins are in TRI-STATE. 0: Disabled (default) 1: Enabled 65 www.national.com 3.0 Device Architecture and Configuration (Continued) 3.12 SYSTEM WAKE-UP CONTROL (SWC) CONFIGURATION 3.12.1 General Description System Wake-up Control provides wake-up and power management functionality according to ACPI specification (see Section 9.1 on page 160). Its registers are VPP or VSB powered. 3.12.2 Logical Device 4 (SWC) Configuration Table 21 lists the configuration registers that affect the SWC. See Section 3.2.3 on page 39 for a detailed description of these registers. All these registers are VDD powered. Table 21. System Wake-Up Control (SWC) Configuration Registers Index Configuration Register or Action Type Power Well Reset 30h Activate. When bit 0 is cleared, the runtime registers of this logical device are not accessible (see Section 3.3.1 on page 42).1 R/W VDD 00h 60h SWC Base Address MSB register. R/W VDD 00h 61h SWC Base Address LSB register. Bits 4-0 (for A4-0) are read only, 00000b. R/W VDD 00h 62h PM1b_EVT_BLK Base Address MSB register. R/W VDD 00h 63h PM1b_EVT_BLK Base Address LSB register. Bits 1-0 (for A1-0) are read only, 00b. R/W VDD 00h 64h PM1b_CNT_BLK Base Address MSB register. R/W VDD 00h 65h PM1b_CNT_BLK Base Address LSB register. Bits 1-0 (for A1-0) are read only, 00b. R/W VDD 00h 66h GPE1_BLK Base Address MSB register. R/W VDD 00h 67h GPE1_BLK Base Address LSB register. Bits 2-0 (for A2-0) are read only, 000b. R/W VDD 00h 70h Interrupt Number. R/W VDD 00h 71h Interrupt Type. Bit 1 is read/write. Other bits are read only. R/W VDD 03h 74h Report no DMA assignment. RO VDD 04h 75h Report no DMA assignment. RO VDD 04h 1. The logical device runtime registers are maintained and all wake-up detection mechanisms are functional. www.national.com 66 3.0 Device Architecture and Configuration (Continued) 3.13 KEYBOARD AND MOUSE CONTROLLER (KBC) CONFIGURATION 3.13.1 General Description The KBC is implemented physically as a single hardware module and houses two separate logical devices: a Mouse controller (Logical Device 5) and a Keyboard controller (Logical Device 6). The KBC is functionally equivalent to the industry standard 8042A Keyboard controller. Technical references for the standard 8042A Keyboard Controller may serve as detailed technical references for the KBC. The Keyboard and Mouse Controller runtime registers are described in Section 10.4 on page 228. All the registers are VDD powered. 3.13.2 Logical Devices 5 and 6 (Mouse and Keyboard) Configuration Tables 22 and 23 list the configuration registers that affect the Mouse and the Keyboard logical devices, respectively. Only the last register (F0h) is described here. See Section 3.2.3 on page 39 for descriptions of the other configuration registers. All these registers are VDD powered. Table 22. Mouse Configuration Registers Index Mouse Configuration Register or Action Type Power Well Reset 30h Activate (see Section 3.2.3 on page 39). When the Mouse of the KBC is inactive, the IRQ selected by the Mouse Interrupt Number and Wake-Up on IRQ Enable register (index 70h) are not asserted. This register has no effect on host KBC commands handling the PS/2 Mouse. R/W VDD 00h 70h Mouse Interrupt Number and Wake-Up on IRQ Enable register. R/W VDD 0Ch 71h Mouse Interrupt Type. Bits 1,0 are read/write; other bits are read only. R/W VDD 02h 74h Report no DMA assignment. RO VDD 04h 75h Report no DMA assignment. RO VDD 04h Table 23. Keyboard Configuration Registers Index Keyboard Configuration Register or Action Type 30h Activate (see Section 3.2.3 on page 39). When the Keyboard of the KBC is inactive, the IRQ selected by the Keyboard Interrupt Number and Wake-Up on IRQ Enable register (index 70h) are not asserted. R/W VDD 00h 60h Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b. R/W VDD 00h 61h Base Address LSB register. Bits 2-0 (for A2-0) are read-only 000b. R/W VDD 60h 62h Command Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b. R/W VDD 00h 63h Command Base Address LSB. Bits 2-0 (for A2-0) are read-only 100b. R/W VDD 64h 70h KBD Interrupt Number and Wake-Up on IRQ Enable register. R/W VDD 01h 71h KBD Interrupt Type. Bits 1,0 are read/write; others are read only. R/W VDD 02h 74h Report no DMA assignment. RO VDD 04h 75h Report no DMA assignment. RO VDD 04h F0h KBC Configuration register. R/W VDD 40h 67 Power Well Reset www.national.com 3.0 Device Architecture and Configuration (Continued) 3.13.3 KBC Configuration Register This register is reset by hardware to 40h. Power Well: VDD Location: Index F0h Type: R/W Bit 7 Name 6 KBC Clock Source Reset Required 0 1 Bit 7-6 5-4 3 2-1 0 5 4 Reserved 0 3 2 Swap 0 0 1 Reserved 0 0 0 0 TRI-STATE Control 0 Description KBC Clock Source. The clock source can be changed only when the KBC is inactive (disabled). Bits 7 6 Source 0 0 1 1 8 MHz 12 MHz (default) 16 MHz Reserved 0 1 0 1 Reserved. Swap. This bit swaps between the Keyboard and Mouse Interface pins. 0: KBCLK and KBDAT are Keyboard Interface; MCLK and MDAT are Mouse Interface (default) 1: KBCLK and KBDAT are Mouse Interface; MCLK and MDAT are Keyboard Interface Reserved. TRI-STATE Control. If the keyboard is inactive (see Section 3.3.1 on page 42) when this bit is set, the KBD pins (KBCLK and KBDAT) are in TRI-STATE. If the mouse is inactive (see Section 3.3.1 on page 42) when this bit is set, the mouse pins (MCLK and MDAT) are in TRI-STATE. 0: Disabled (default) 1: Enabled Usage Hints: 1. To change the clock frequency of the KBC: a. Disable the KBC logical devices. b. Change the frequency setting. c. Enable the KBC logical devices. 2. Before swapping between the Keyboard and Mouse Interface pins, disable the KBC logical devices and both pin sets. After swapping, the software must issue a synchronization command to the Keyboard and Mouse through the KBC to regain synchronization with these devices. www.national.com 68 3.0 Device Architecture and Configuration (Continued) 3.14 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS CONFIGURATION 3.14.1 General Description The GPIO functional block includes 51 pins arranged in seven ports: Ports 1 and 4 contain eight GPIOE pins each. Ports 0, 2 and 3 contain eight GPIO pins each. Port 5 contains six GPIO pins. Port 6 contains five GPO pins (see Section 1.4.8 on page 26). All the pins of Ports 1 and 4 and have full event detection capability (see Section 1.3 on page 20), enabling them to trigger the assertion of IRQ or SIOSMI signals. In addition, through the SWC functional block, the pins of Ports 1 and 4 can trigger the SIOSCI, control the ONCTL signal or enable the generation of a pulse in the PWBTOUT signal. The pins of Ports 0-5 are I/O, however the five pins of Port 6 are output only. All 51 GPIO pins are powered from the VSB well. The 17 runtime registers associated with the seven ports are arranged in the GPIO address space as shown in Table 24. The GPIO ports with wake-up event detection capability (such as Ports 1 and 4) have four runtime registers; the other ports have only 2. Port 6 contains only GPO pins and therefore has only one runtime register. The GPIO base address is 32-byte aligned. Address bits 4-0 are used to indicate the register offset. The specific runtime registers implemented in the PC8741x devices are shown in Table 24. All these registers are VSB powered. Table 24. Runtime Registers in GPIO Address Space Offset Mnemonic Register Name 00h GPDO0 GPIO Data Out 0 01h GPDI0 GPIO Data In 0 02h GPDO1 GPIO Data Out 1 03h GPDI1 GPIO Data In 1 Port Power Well 0 1 Type VSB R/W VSB RO VSB R/W VSB RO 04h GPEVEN1 GPIO Event Enable 1 VSB R/W 05h GPEVST1 GPIO Event Status 1 VSB R/W1C VSB R/W VSB RO VSB R/W VSB RO VSB R/W VSB RO 06h GPDO2 GPIO Data Out 2 07h GPDI2 GPIO Data In 2 08h GPDO3 GPIO Data Out 3 09h GPDI3 GPIO Data In 3 0Ah GPDO4 GPIO Data Out 4 0Bh GPDI4 GPIO Data In 4 2 3 4 0Ch GPEVEN4 GPIO Event Enable 4 VSB R/W 0Dh GPEVST4 GPIO Event Status 4 VSB R/W1C VSB R/W VSB RO VSB R/W 0Eh GPDO5 GPIO Data Out 5 0Fh GPDI5 GPIO Data In 5 10h GPDO6 GPIO Data Out 6 5 6 69 www.national.com 3.0 Device Architecture and Configuration (Continued) 3.14.2 Logical Device 7 (GPIO) Configuration Table 25 lists the configuration registers that affect the GPIO. Only the last three registers (F0h - F2h) are described here. See Section 3.2.3 on page 39 for a detailed description of the other configuration registers. The standard configuration registers are powered by VDD, however the specific configuration registers are powered by VSB. Table 25. GPIO Configuration Register Index Configuration Register or Action Type Power Well Reset 30h Activate (see Section 3.2.3 on page 39). R/W VDD 00h 60h Base Address MSB register. R/W VDD 00h 61h Base Address LSB register. Bits 4-0 (for A4-0) are read-only 00000b. R/W VDD 00h 70h Interrupt Number and Wake-Up on IRQ Enable register. R/W VDD 00h 71h Interrupt Type. Bit 1 is read/write. Other bits are read only. R/W VDD 03h 74h Report no DMA assignment. RO VDD 04h 75h Report no DMA assignment. RO VDD 04h F0h GPIO Pin Select register (GPSEL). R/W VSB 00h F1h GPIO Pin Configuration register 1 (GPCFG1). R/W VSB See text F2h GPIO Pin Event Routing register (GPEVR). R/W VSB 01h F3h GPIO Pin Configuration register 2 (GPCFG2). R/W VSB 00h Figure 6 shows the organization of these registers: GPIO Pin Select Register (Index F0h) Port Select Port 0 Pin Select Pin 0 Port 6, Pin 0 Port 5, Pin 0 Port 4, Pin 0 Port 3, Pin 0 Port 2, Pin 0 Port 1, Pin 0 Port 0, Pin 0 GPIO Pin Configuration Registers (Index F1h) (Index F3h) Port 6 Port 0, Pin 7 Pin 7 Pin 0 Port 4, Pin 0 Port 1, Pin 0 Port 1 GPIO Pin Event Routing Register (Index F2h) Port 4 Pin 7 Port 1, Pin 7 Figure 6. Organization of GPIO Pin Registers www.national.com 70 3.0 Device Architecture and Configuration (Continued) 3.14.3 GPIO Pin Select Register (GPSEL) This register selects the GPIO pin (port number and bit number) to be configured (i.e., which register is accessed via the GPIO configuration registers). Since access to the pin configuration requires two transactions (first to GPSEL, then to the configuration register) and since the LPC bus and ACCESS.bus concurrently access the module (PC87413 and PC87417), the GPSEL register is duplicated (one GPSEL register is accessed by the host and one by the ACCESS.bus). This register is reset by hardware to 00h. Power Well: VSB Location: Index F0h Type: R/W Bit 7 Name Reserved Reset 0 6 5 PORTSEL 0 5-4 3 2-0 3 2 Reserved 0 Bit 7 4 0 0 1 0 PINSEL 0 0 0 Description Reserved. PORTSEL (Port Select). These bits select the GPIO port to be configured: 000: Port 0 (default) 001 to 110: Binary value of port numbers 1-6, respectively (all other values are reserved) Reserved. PINSEL (Pin Select). These bits select the GPIO pin of the selected port, to be configured: 000: Pin 0 (default) 001 to 111: Binary value of pin number 1-7, respectively 3.14.4 GPIO Pin Configuration Register 1 (GPCFG1) This register reflects, for both read and write, the register currently selected by the GPIO Pin Select register. All the GPIO Pin Configuration registers have a common bit structure, as shown below. Ports 1 and 4 are reset by hardware to 01000X00b. Ports 0, 2, 3, 5 and 6 are reset to 00000X00b (see Table 26 on page 72 for the value of `X'). Power Well: VSB Location: Type: Index F1h Varies per bit Ports 1 and 4 (With Wake-Up Event Detection Capability) Bit 7 6 5 4 3 2 1 0 Name Reserved EVDBNC EVPOL EVTYPE Reset 0 1 0 0 LOCKCFP PUPCTL OUTTYPE OUTENA 0 see Table 26 0 0 3 2 1 0 LOCKCFP PUPCTL OUTTYPE OUTENA 0 see Table 26 0 0 Ports 0, 2, 3, 5 and 6 (Without Wake-Up Event Detection Capability) Bit 7 6 0 0 Name Reset 5 4 0 0 Reserved 71 www.national.com 3.0 Device Architecture and Configuration (Continued) Bit Type Description 7 - 6 R/W Reserved for Ports 0, 2, 3, 5, and 6. For Ports 1 and 4: EVDBNC (Event Debounce Enable). This bit enables the debounce circuit in the event input path of the selected GPIO pin. The event is detected after a predetermined debouncing period of time (see Section 7.3 on page 136). 0: Disabled 1: Enabled (default) 5 R/W Reserved for Ports 0, 2, 3, 5, and 6. For Ports 1 and 4: EVPOL (Event Polarity). This bit defines the polarity of the wake-up signal that issues an event from the selected GPIO pin (see Section 7.3 on page 136). 0: Falling edge or low level input (default) 1: Rising edge or high level input 4 R/W Reserved for Ports 0, 2, 3, 5, and 6. For Ports 1 and 4: EVTYPE (Event Type). This bit defines the type of the wake-up signal that issues an event from the selected GPIO pin (see Section 7.3 on page 136). 0: Edge input (default) 1: Level input Reserved (note that for Ports 0, 2, 3, 5, and 6, bits 7-4 are reserved). 3 R/W1S LOCKCFP (Lock Configuration of Pin). When set to 1, this bit locks the GPIO pin configuration and data (see also Section 7.4 on page 138) by disabling writing to itself, to GPCFG1 register bits PUPCTL, OUTTYPE and OUTENA, to all the bits of the GPCFG2 register and to the corresponding bit in the GPDO register. Once set, this bit can be cleared by VDD Power-Up reset (or Hardware reset) or by VSB Power-Up reset, according to the VSBLOCK bit in the ACBLKCTL register (see Section 6.3.4 on page 127). In addition, this bit is cleared by setting the UNLOCKG bit in the ACBLKCTL register (PC87413 and PC87417). 0: R/W bits are enabled for write (default) 1: All bits are RO 2 R/W or PUPCTL (Pull-Up Control). This bit controls the internal pull-up resistor of the selected GPIO pin (see RO Section 7.2 on page 135). 0: Disabled (for default value, see Table 26) 1: Enabled (for default value, see Table 26) 1 R/W or OUTTYPE (Output Type). This bit controls the output buffer type of the selected GPIO pin (see Section RO 7.2 on page 135). 0: Open-drain (default) 1: Push-pull 0 R/W or OUTENA (Output Enable). This bit controls the output buffer of the selected GPIO pin (see Section 7.2 RO on page 135). 0: TRI-STATE (default) 1: Output buffer enabled Table 26. Reset Values for PUPCTL Bit GP(I)O(E)nn PUPCTL 00-07,10-17 20,21 0 1 22-25 26,27,30-37,40-42 43-47,50 51-53 54,55,60-63 641 0 1 0 1 0 1 1. The pull-up resistor is disabled during VSB Power-Up reset. www.national.com 72 3.0 Device Architecture and Configuration (Continued) 3.14.5 GPIO Event Routing Register (GPEVR) This register enables the routing of the GPIO event (see Section 7.3.2 on page 137) to IRQ and/or SIOSMI signals. It is implemented only for Ports 1 and 4, which have wake-up event detection capability. This register is reset by hardware to 01h. Power Well: VSB Location: Index F2h Type: R/W Bit 7 6 5 Name Reset 0 0 0 Bit 7-2 4 3 2 Reserved 0 0 1 0 EV2SMI EV2IRQ 0 1 0 Description Reserved. 1 EV2SMI (Event to SMI Routing). Controls the routing of the event from the selected GPIO pin to SIOSMI (see Section 7.3 on page 136). 0: Disabled (default) 1: Enabled 0 EV2IRQ (Event to IRQ Routing). Controls the routing of the event from the selected GPIO pin to IRQ (see Section 7.3 on page 136). 0: Disabled 1: Enabled (default) 3.14.6 GPIO Pin Configuration Register 2 (GPCFG2) This register controls the access to the GPIO pin from one of the two buses. This register is reset by hardware to 00h. Power Well: VSB Location: Type: Index F3h R/W or RO Bit 7 Name Reserved Reset 0 Bit 7 6-5 4 6 5 BUSCTL 0 4 3 2 0 0 VDDLOAD 0 0 1 0 0 0 Reserved Description Reserved. BUSCTL (Bus Control). These bits select the bus (ACCESS.bus or LPC bus) that controls the configuration and data of the selected GPIO pin. The bus not selected has read-only access to the GPCFG1, GPCFG2 and GPEVR registers and to the corresponding bit in the GPDO, GPEVEN and GPEVST registers (see Section 7.4.2 on page 139). In the PC87414 and PC87416, these bits are irrelevant because only the LPC bus is available. Bits 1 0 Function 0 0 1 1 Access from ACCESS.bus and LPC bus (default) Access from ACCESS.bus only Access from LPC bus only Reserved 0 1 0 1 VDDLOAD (VDD-Powered Load). This bit indicates that the selected GPIO pin is connected to a device powered by VDD. The input and output (including the internal pull-up) of such a GPIO pin are disabled whenever VDD power to the PC8741x device falls below a certain value (see Section 11.1.5 on page 231). 0: GPIO pin connected to a VSB-powered load (default) 1: GPIO pin connected to a VDD-powered load 3-0 Reserved. 73 www.national.com 3.0 Device Architecture and Configuration (Continued) 3.15 X-BUS CONFIGURATION This section is relevant only for the PC87416 and PC87417. 3.15.1 Logical Device F (X-Bus) Configuration Table 27 lists the configuration registers that affect the X-Bus functional block. The X-Bus base address registers point to the X-Bus runtime registers described in Section 5.4 on page 106. The memory space to which the X-Bus responds is defined by the configuration registers described in the sections below. See Section 3.2.3 on page 39 for a detailed description of the other configuration registers. The standard configuration registers are powered by VDD, however the specific configuration registers are powered by VSB. Table 27. X-Bus Configuration Registers Index Configuration Register or Action Type Power Well Reset 30h Activate (see Section 3.3.1 on page 42). When bit 0 is cleared, the registers of this logical device are not accessible. R/W VDD 00h 60h Base Address MSB register. R/W VDD 00h 61h Base Address LSB register. Bits 4-0 (for A4-A0) are read only, 00000b. Varies per bit VDD 00h 70h Interrupt Number and wake-up on IRQ enable. RO VDD 00h 71h Interrupt Type. RO VDD 00h 74h Report no DMA assignment. RO VDD 04h 75h Report no DMA assignment. RO VDD 04h F0h X-Bus I/O Configuration register (XIOCNF). Varies per bit VSB 00h F1h X-Bus I/O Base Address 1 High Byte register (XIOBA1H). R/W or RO VSB 00h F2h X-Bus I/O Base Address 1 Low Byte register (XIOBA1L). R/W or RO VSB 00h F3h X-Bus I/O Size 1 Configuration register (XIOSIZE1). R/W or RO VSB 00h F4h X-Bus I/O Base Address 2 High Byte register (XIOBA2H). R/W or RO VSB 00h F5h X-Bus I/O Base Address 2 Low Byte register (XIOBA2L). R/W or RO VSB 00h F6h X-Bus I/O Size 2 Configuration register (XIOSIZE2). R/W or RO VSB 00h F7h X-Bus Memory Configuration register 1 (XMEMCNF1). R/W or RO VSB 00h F8h X-Bus Memory Configuration register 2 (XMEMCNF2). Varies per bit VSB 00h F9h X-Bus Memory Base Address High Byte register (XMEMBAH). R/W or RO VSB 00h FAh X-Bus Memory Base Address Low Byte register (XMEMBAL). R/W or RO VSB 00h FBh X-Bus Memory Size Configuration register (XMEMSIZE). R/W or RO VSB 00h FCh X-Bus IRQ Mapping register (XIRQMAP). R/W VSB 00h 3.15.2 X-Bus I/O Range Programming LPC I/O transactions can be forwarded to the X-Bus of the PC8741x device. The X-Bus I/O configuration registers define the map of I/O addresses to be forwarded. The PC8741x provides five individually enabled I/O zones. Each zone generates an internal select signal that is sent to the X-Bus functional block. The mapping of the internal select signals to the XCS0-3 signals of the PC8741x device is controlled by the X-Bus functional block. See Section 5.2 on page 91 for further details. The supported I/O zones are: User-Defined I/O Zone 0 through 3 (UDIZ0-3) - specified using the zone size (2n where n is 0 through 8) and start address (must be aligned with the zone size). Debug Port Address (TST) - This zone is for debug use only. www.national.com 74 3.0 Device Architecture and Configuration (Continued) These decoded I/O zones are determined by the following seven registers: X-Bus I/O Configuration, X-Bus I/O Zone Base Address 1/2 High and Low Byte and X-Bus I/O Size 1/2 Configuration. When a zone is enabled but is not associated with any XCS0-3 select signal in the X-Bus Interface, the X-Bus does not respond to LPC transactions accessing that zone. The I/O Address Map Lock bit (LOCKIOMP) in XIOCNF register enables protecting the contents of the I/O mapping by preventing modifications to them that would cause access rights violation through aliasing. Figure 7 illustrates the mapping of the User-Defined I/O zones to the host I/O space. The order between Base Address 1 and 2 is an example only and may be reversed. Host I/O Space FFFFh Zone Size 2 User-Defined I/O Zone 3 (UDIZ3) Zone Size 2 Base Address 2 (High, Low) User-Defined I/O Zone 2 (UDIZ2) Zone Size 1 User-Defined I/O Zone 1 (UDIZ1) Zone Size 1 Base Address 1 (High, Low) User-Defined I/O Zone 0 (UDIZ0) 0000h Figure 7. User-Defined I/O Block Mapping 3.15.3 X-Bus Memory Range Programming LPC memory transactions or LPC-FWH transactions can be forwarded to the X-Bus Extension of the PC8741x device. X-Bus Memory Configuration Register 1 defines the address space to which the device responds. The XCNF2 strap input controls the default setting of the XMEMCNF1 register to enable booting from memories connected on the X-Bus. Two memory areas may be individually enabled: a user-defined zone and a BIOS memory zone (either BIOS-LPC, or BIOS-FWH spaces). To enable BIOS support, set the XCNF2 strap input to select the BIOS mode (see Section 1.4.11 on page 28 for details). The PC8741x devices respond to LPC memory read and write transactions to/from the BIOS address spaces (see Table 28) as long as the BIOLPCEN bit of XMEMCNF1 register is set (see Section 3.15.11 on page 82). Table 28. BIOS-LPC Memory Space Definition Memory Address Range 000E 0000h - 000E FFFFh 000F 0000h - 000F FFFFh FFFC 0000h - FFFF FFFFh FFF8 0000h - FFFF FFFFh FFF0 0000h - FFFF FFFFh FFE0 0000h - FFFF FFFFh FFC0 0000h - FFFF FFFFh FF80 0000h - FFFF FFFFh FF00 0000h - FFFF FFFFh FE00 0000h - FFFF FFFFh Description Extended BIOS Range (Legacy) Only when BIOEXTEN = 1 in XMEMCNF1 register BIOS Range (Legacy) 386 mode BIOS Range. This is the upper 256 Kbytes to 32 Mbytes of the memory space, depending on the setting of BIOSIZE and SEL2BIOS in XMEMCNF2 (see Section 3.15.12 on page 83). The PC8741x devices respond to LPC-FWH read transactions from the high memory address range ('386' mode BIOS range), shown in Table 28, as long as BIOFWHEN = 1 in the XMEMCNF1 register. 75 www.national.com 3.0 Device Architecture and Configuration (Continued) Table 29. BIOS-FWH Memory Space Definition Memory Address Range FFFC 0000h - FFFF FFFFh FFF8 0000h - FFFF FFFFh FFF0 0000h - FFFF FFFFh FFE0 0000h - FFFF FFFFh FFC0 0000h - FFFF FFFFh FF80 0000h - FFFF FFFFh FF00 0000h - FFFF FFFFh FE00 0000h - FFFF FFFFh Description 386 mode BIOS Range. This is the upper 256 Kbytes to 32 Mbytes of the memory space, depending on the setting of BIOSIZE and SEL2BIOS in XMEMCNF2 (see Section 3.15.12 on page 83). The PC8741x devices use the ID field and address bits A18-A27 to A25-A27, respectively, to identify FWH access to the BIOS memory. Upon reset in BIOS mode, both the BIOLPCEN and the BIOFWHEN bits in the XMEMCNF1 register are set. The PC8741x device automatically detects the type of host boot protocol in use via the first completed BIOS read transaction after reset. If the first read is an LPC memory read, the BIOFWHEN bit is cleared. If the first read is an LPC-FWH read, the BIOLPCEN bit is cleared. The succeeding LPC or LPC-FWH transactions do not influence the BIOLPCEN and BIOFWHEN bits. The software can later enable the response to both address spaces by setting the cleared bit. Figure 8 illustrates this behavior. VSB Power-Up Reset XCNF2 = Disable BIOS XC NF 2= Ena ble BIO S BIOFWHEN = 0 BIOLPCEN = 0 BIOFWHEN = 1 BIOLPCEN = 1 First Memory Read is LPC Note: Only hardware controlled transitions are shown. Other transitions are possible via software writing to the bits. BIOFWHEN = 0 BIOLPCEN = 1 First Memory Read is FWH BIOFWHEN = 1 BIOLPCEN = 0 Figure 8. BIOS Mapping Enable Scheme The two User-Defined Memory Zones (MEM0 and MEM1) are specified via a 32-bit base address. This address is formed by eight bits of the XMEMBAL register, eight bits of the XMEMBAH register and 16 least significant bits of 0. The size of each zone is specified through the XMEMSIZE register. The base address must be aligned to the block size. Figure 9 and Figure 10 illustrate the mapping of the LPC and FWH spaces to the different memory zones. The Memory Address Map Lock bit in X-Bus Memory Configuration Register 2 enables protection of the contents of the memory mapping, thus preventing modifications to them that may cause access rights violation through aliasing. The address used for the X-Bus transaction is the 28 least significant bits of the address bus. In read transactions, the data read from the X-Bus is passed to the LPC bus. In write transactions, the data from the LPC is passed to the X-Bus. www.national.com 76 3.0 Device Architecture and Configuration (Continued) Host Memory Space FFFF FFFFh BIOS Size BIOS Zone 0 (BIOS 0) BIOS Size BIOS Zone 1 (BIOS 1) Memory Zone Size User-Defined Memory Zone 1 (MEM 1) Memory Zone Size User-Defined Memory Zone 0 (MEM 0) Memory Base Address (High, Low) Legacy BIOS Address space 0000 0000h Figure 9. Memory Block Mapping FFFF FFFFh FWH Space BIOS Size FWH ID Match BIOS Zone 0 (BIOS 0) BIOS Size BIOS Zone 1 (BIOS 1) 0000 0000h Figure 10. FWH Memory Mapping 3.15.4 X-Bus I/O Configuration Register (XIOCNF) This register is reset by hardware to 00h. Power Well: VSB Location: Index F0h Type: Varies per bit Bit 7 Name LOCKIOMP Reset 0 6 5 Reserved 0 4 TSTADEN 0 0 77 3 2 1 0 UDIOZEN3 UDIOZEN2 UDIOZEN1 UDIOZEN0 0 0 0 0 www.national.com 3.0 Device Architecture and Configuration Bit 7 (Continued) Type Description RW1L LOCKIOMP (Lock I/O Address Map). When set to 1, this bit locks the configuration of registers XIOCNF, XIOBA1H, XIOBA1L, XIOSIZE1, XIOBA2H, XIOBA2L and XIOSIZE2 by disabling writing to all their bits (including to the LOCKIOMP bit itself). Once set, this bit can be cleared either by VDD PowerUp reset (or Hardware reset) or by VSB Power-Up reset, according to the VSBLOCK bit in the ACBLKCTL register (see Section 6.3.4 on page 127). In addition, this bit is cleared by setting the UNLOCKX bit in the ACBLKCTL register (PC87417). 0: R/W bits are enabled for write (default) 1: All bits are RO 6-5 - Reserved. 4 R/W or TSTADEN (TST Debug Port Address Enable). When set, enables the mapping of I/O address 80h to RO the X-Bus space. 0: Disabled (default) 1: Enabled 3 R/W or UDIOZEN3 (User-Defined I/O Zone Enable 3). This bit enables the mapping of the User-Defined I/O RO zone 3 to the X-Bus space. The zone base address and size are defined by the XIOBA2H/XIOBA2L and XIOSIZE2 registers, respectively. The base address for this Zone is: (Base Address 2) + (Size 2) 0: Disabled (default) 1: Enabled 2 R/W or UDIOZEN2 (User-Defined I/O Zone Enable 2). This bit enables the mapping of the User-Defined I/O RO zone 2 to the X-Bus space. The zone base address and size are defined by the XIOBA2H/XIOBA2L and XIOSIZE2 registers, respectively. The base address for this Zone is: (Base Address 2) 0: Disabled (default) 1: Enabled 1 R/W or UDIOZEN1 (User-Defined I/O Zone Enable 1). This bit enables the mapping of the User-Defined I/O RO zone 1 to the X-Bus space. The zone base address and size are defined by the XIOBA1H/XIOBA1L and XIOSIZE1 registers, respectively. The base address for this Zone is: (Base Address 1) + (Size 1) 0: Disabled (default) 1: Enabled 0 R/W or UDIOZEN0 (User-Defined I/O Zone Enable 0). This bit enables the mapping of the User-Defined I/O RO zone 0 to the X-Bus space. The zone base address and size are defined by the XIOBA1H/XIOBA1L and XIOSIZE1 registers, respectively. The base address for this Zone is: (Base Address 1) 0: Disabled (default) 1: Enabled 3.15.5 X-Bus I/O Base Address 1 High Byte Register (XIOBA1H) This register describes the high byte of the Base Address for user-defined I/O zone blocks 0 and 1, which are mapped to the X-Bus. This register is reset by hardware to 00h. Power Well: VSB Location: Index F1 Type: R/W or RO Bit 7 6 5 4 Name Reset www.national.com 3 2 1 0 0 0 0 0 IOBA1H 0 0 0 0 78 3.0 Device Architecture and Configuration (Continued) Bit Description 7-0 IOBA1H (I/O User-Defined Zone Base Address 1 High). Defines the upper eight bits of the user-defined I/O blocks 0 and 1 base address. The base address must be aligned on the selected block size. 3.15.6 X-Bus I/O Base Address 1 Low Byte Register (XIOBA1L) This register describes the low byte of the Base Address for User-Defined I/O zone blocks 0 and 1, which are mapped to the X-Bus. This register is reset by hardware to 00h. Power Well: VSB Location: Index F2h Type: R/W or RO Bit 7 6 5 4 Name Reset 0 0 0 Bit 7-0 3 2 1 0 0 0 0 0 IOBA1L 0 Description IOBA1L (I/O User-Defined Zone Base Address 1 Low). Defines the lower eight bits of the user-defined I/O blocks 0 and 1 base address. The base address must be aligned on the selected block size. 3.15.7 X-Bus I/O Size 1 Configuration Register (XIOSIZE1) This register defines the size of User-Defined I/O zone blocks 0 and 1, which are mapped to the X-Bus. The two blocks are contiguous and both have the same size. The User-Defined I/O Zone 1 address does not depend on Zone 0 being enabled. This register is reset by hardware to 00h. Power Well: VSB Location: Index F3h Type: R/W or RO Bit 7 6 Name 5 4 3 2 Reserved Reset 0 0 Bit 1 0 0 0 IOSIZE1 0 0 0 0 Description 7-4 Reserved. 3-0 IOSIZE1 (User-Defined I/O Zone Size 1). Defines the size in bytes of the zone window. The size is defined as a power of two using the equation: NumOfBytes = 2n (where n = the value of the IOSIZE1 field). The zone must always be aligned to the window size (i.e., for a 128-byte window, the seven LSBs of the base address are zero). Bits 3210 Size (Bytes) 0000 1 (20 - default) ... 1000 Other 256 (28) Reserved 79 www.national.com 3.0 Device Architecture and Configuration (Continued) 3.15.8 X-Bus I/O Base Address 2 High Byte Register (XIOBA2H) This register describes the high byte of the Base Address for User-Defined I/O zone blocks 2 and 3, which are mapped to the X-Bus. This register is reset by hardware to 00h. Power Well: VSB Location: Index F4 Type: R/W or RO Bit 7 6 5 4 Name 3 2 1 0 0 0 0 0 IOBA2H Reset 0 0 0 0 Bit Description 7-0 IOBA2H (I/O User-Defined Zone Base Address 2 High). Defines the upper eight bits of the User-Defined I/O blocks 2 and 3 base address. The base address must be aligned on the selected block size. 3.15.9 X-Bus I/O Base Address 2 Low Byte Register (XIOBA2L) This register describes the low byte of the Base Address for User-Defined I/O zone blocks 2 and 3, which are mapped to the X-Bus. This register is reset by hardware to 00h. Power Well: VSB Location: Index F5h Type: R/W or RO Bit 7 6 5 4 0 0 0 0 Name 2 1 0 0 0 0 0 IOBA2L Reset Bit 7-0 3 Description IOBA2L (I/O User-Defined Zone Base Address 2 Low). Defines the lower eight bits of the user-defined I/O blocks 2 and 3 base address. The base address must be aligned on the selected block size. www.national.com 80 3.0 Device Architecture and Configuration (Continued) 3.15.10 X-Bus I/O Size 2 Configuration Register (XIOSIZE2) This register defines the size of User-Defined I/O zone blocks 2 and 3, which are mapped to the X-Bus. The two blocks are contiguous and have the same size. The User-Defined I/O Zone 3 address does not depend on Zone 2 being enabled. This register is reset by hardware to 00h. Power Well: VSB Location: Index F6h Type: R/W or RO Bit 7 6 0 0 Name 5 4 3 2 0 0 0 0 Reserved Reset Bit 1 0 0 0 IOSIZE2 Description 7-4 Reserved. 3-0 IOSIZE2 (User-Defined I/O Zone Size 2). Defines the size in bytes of the zone window. The size is defined as a power of two using the equation: NumOfBytes = 2n (where n = the value of bits 3-0). The zone must always be aligned to the window size (i.e., for a 128-byte window, the seven LSBs of the base address are zero). Bits 3210 Size (Bytes) 0000 1 (20 - default) ... 1000 Other 256 (28) Reserved 81 www.national.com 3.0 Device Architecture and Configuration (Continued) 3.15.11 X-Bus Memory Configuration Register 1 (XMEMCNF1) This register is reset by hardware to 00h. Power Well: VSB Location: Index F7h Type: R/W or RO Bit 7 6 0 0 Name 5 4 0 0 FWHID Reset 3 2 1 0 BIOFWHEN UDMEMEN BIOEXTEN BIOLPCEN Strap 0 0 Strap Bit Description 7-4 FWHID (BIOS FWH ID). These four bits correspond to the Device Select nibble that is part of a FWH transaction (see Section 4.2 on page 89 for details). 3 BIOFWHEN (BIOS FWH Enable). When set, this bit enables the PC8741x device to respond to LPC-FWH transactions to the BIOS-FWH space. The default value is set according to the XCNF2 strap, sampled at VSB Power-Up reset. The value of this bit is later updated based on the detected host BIOS scheme (see Section 3.15.3 on page 75 for details). 0: Disabled (default when XCNF2 = 0 - disables BIOS configuration) 1: Enabled (default when XCNF2 = 1 - enables BIOS configuration) 2 UDMEMEN (User-Defined Memory Space Enable). When set, this bit enables the PC8741x device to respond to LPC memory read and write transactions in the user-defined memory range. The base address and size of the user-defined range is specified by the XMEMBAH/XMEMBAL and XMEMSIZE registers, respectively. 0: Disabled (default) 1: Enabled 1 BIOEXTEN (BIOS Extended Space Enable). Expands the BIOS address space to which the PC8741x device responds, to include the Extended BIOS address range. 0: Disabled (default) 1: Enabled 0 BIOLPCEN (BIOS LPC Enable). Enables the PC8741x device to respond to LPC memory transactions to the BIOS-LPC space. The default value is set according to the XCNF2 strap, sampled at VSB Power-Up reset. The value of this bit is later updated, based on the detected host BIOS scheme (see Section 3.15.3 on page 75 for details). 0: Disabled (default when XCNF2 = 0 - disables BIOS configuration) 1: Enabled (default when XCNF2 = 1 - enables BIOS configuration) www.national.com 82 3.0 Device Architecture and Configuration (Continued) 3.15.12 X-Bus Memory Configuration Register 2 (XMEMCNF2) This register is reset by hardware to 00h. Power Well: VSB Location: Index F8h Type: Varies per bit Bit 7 Name LOCKMMP Reset 0 6 5 Reserved 0 0 4 3 SEL2UDM SEL2BIOS 0 0 2 1 0 BIOSIZE 0 0 0 Bit Description 7 LOCKMMP (Lock Memory Address Map). When set to 1, this bit locks the configuration of registers XMEMCNF1, XMEMCNF2, XMEMBAH, XMEMBAL and XMEMSIZE by disabling writing to all their bits (including to the LOCKMAP bit itself). Once set, this bit can be cleared either by VDD Power-Up reset (or Hardware reset) or by VSB Power-Up reset, according to the VSBLOCK bit in the ACBLKCTL register (see Section 6.3.4 on page 127). In addition, this bit is cleared by setting the UNLOCKX bit in the ACBLKCTL register (PC87417). 0: R/W bits are enabled for write (default) 1: All bits are RO 6-5 Reserved. 4 SEL2UDM (Dual User-Defined Memory Select Enable). Enables the PC8741x device to control two memory devices for data storage. The second zone (MEM Zone 1) is mapped on top of the first zone (MEM Zone 0). Both zones are the same size. The base address of MEM Zone 0 is specified by the XMEMBAH and XMEMBAL registers. The size of both memory zones is specified by the XMEMSIZE register. The base address of MEM Zone 1 is: (Base Address Memory Zone) + (Size Memory Zone). 0: Disabled - Use only MEM Zone 0, if enabled (default) 1: Enabled - If the user-defined memory is enabled, use both MEM Zone 0 and MEM Zone 1 3 SEL2BIOS (Dual BIOS Select Enable). Enables the PC8741x device to control two flash devices for BIOS storage. The first device (BIOS Zone 0) is used for legacy and the upper 386 zone. BIOS zone 1 is on the next "BIOS Size" block in the 386 address range (addresses lower than these of Block 1). When FWH is enabled, BIOS Zone 0 responds to the upper addresses and BIOS Zone 1, if enabled, responds to the group below Zone 0, as defined by BIOS Size. Both zones use the same FWHID value. 0: Disabled - Use BIOS Zone 0 only, if enabled (default) 1: Enabled - If either the LPC BIOS or the FWH BIOS is enabled, use both BIOS Zone 0 and BIOS Zone 1 2-0 BIOSIZE (BIOS Size). Define the Size of one BIOS Zone in the 386 range. Note that by setting the Dual BIOS Select Enable, two equal-sized BIOS Zones are available. 2 0 0 0 0 1 1 1 1 Bits 1 0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 Size (Bytes) 256 Kbytes (default) 512 Kbytes 1 Mbyte 2 Mbytes 4 Mbytes 8 Mbytes 16 Mbytes Reserved 83 www.national.com 3.0 Device Architecture and Configuration (Continued) 3.15.13 X-Bus Memory Base Address High Byte Register (XMEMBAH) This register describes the high byte for the user-defined memory zones mapped to the X-Bus (decoded as bits 31 to 24 of the 32-bit address range; bits 15-0 are 0). This register is reset by hardware to 00h. Power Well: VSB Location: Index F9h Type: R/W or RO Bit 7 6 5 4 Name Reset 0 0 0 Bit 7-0 3 2 1 0 0 0 0 0 MEMBAH 0 Description MEMBAH (User-Defined Memory Zone Address High). Defines the upper eight bits of the user-defined memory block base address. The base address must be aligned on the selected block size. 3.15.14 X-Bus Memory Base Address Low Byte Register (XMEMBAL) This register describes the low byte for the user-defined memory zones mapped to the X-Bus (decoded as bits 23 to 16 of the 32-bit address range; bits 15 to 0 are 0). This register is reset by hardware to 00h. Power Well: VSB Location: Index FAh Type: R/W or RO Bit 7 6 5 4 0 0 0 0 Name 2 1 0 0 0 0 0 MEMBAL Reset Bit 7-0 3 Description MEMBAL (User-Defined Memory Zone Address Low). Defines the lower eight bits of the user-defined memory block base address. The base address must be aligned on the selected block size. www.national.com 84 3.0 Device Architecture and Configuration (Continued) 3.15.15 X-Bus Memory Size Configuration Register (XMEMSIZE) This register defines the size of each user-defined memory zone mapped to the X-Bus. This register is reset by hardware to 00h. Power Well: VSB Location: Index FBh Type: R/W or RO Bit 7 6 Name 5 4 3 2 Reserved Reset 0 0 1 0 0 0 MEMSIZE 0 Bit 0 0 0 Description 7-4 Reserved. 3-0 MEMSIZE (User-Defined Memory Zone Size). Defines the size of one zone window (in bytes). The size is defined as a power of two using the equation: NumOfBytes = 2n (where n = the value of the MEMSIZE field +16). The zone must always be aligned to the window size (i.e., for a 128 Kbyte window, the 17 LSBs of the address must be zero). Bits 3 210 Size (Bytes) 0000 64K (216 - default) ... 1000 Other 16M (224) Reserved 3.15.16 X-Bus IRQ Mapping Register (XIRQMAP) This register defines the mapping of the XIRQ signal. Power Well: VSB Location: Index FCh Type: R/W Bit 7 6 Name 5 4 3 2 Reserved Reset 0 0 Bit 1 0 0 0 IRQMAP 0 0 0 0 Description 7-4 Reserved. 3-0 IRQMAP (XIRQ Mapping). Defines to which host IRQ the XIRQ input is routed. Bits 3 2 1 0 Function 0 0 0 0 0 0 0 1 IRQ Disabled (default) IRQ1 ... 1 1 1 1 IRQ 15 85 www.national.com 3.0 Device Architecture and Configuration (Continued) 3.16 REAL TIME CLOCK (RTC) CONFIGURATION 3.16.1 General Description The RTC provides timekeeping and calendar management capabilities. It uses a 32.768 KHz signal as the basic clock for timekeeping. The RTC also includes 242 bytes of battery-backed RAM for general-purpose use. The RTC runtime registers are shown in Section 8.3.2 on page 149. These registers are VPP powered. 3.16.2 Logical Device 10 (RTC) Configuration Table 30 lists the configuration registers that affect the Real Time Clock. The standard configuration registers (see Section 3.2.3 on page 39) are powered by VDD. The specific configuration registers are powered by VSB. Table 30. RTC Configuration Registers Index RTC Configuration Register or Action Type Power Well Reset 30h Activate (see Section 3.3.1 on page 42). When bit 0 is cleared, the runtime registers of this logical device are not accessible. R/W VDD 00h 60h Standard Base Address MSB register. R/W VDD 00h 61h Standard Base Address LSB register. Bit 0 (for A0) is read only 0b. R/W VDD 70h 62h Extended RAM Base Address MSB register. R/W VDD 00h 63h Extended RAM Base Address LSB register. Bit 0 (for A0) is read only 0b. R/W VDD 72h 70h RTC Interrupt Number and Wake-Up on IRQ Enable register. R/W VDD 08h 71h RTC Interrupt Type. Bit 1 is read/write; other bits are read only. R/W VDD 00h 74h Report no DMA assignment. RO VDD 04h 75h Report no DMA assignment. RO VDD 04h F0h RAM Lock Register (RLR). R/W1S VSB 00h F1h Date-of-Month Alarm Register Offset (DOMAO). R/W VSB 00h F2h Month Alarm Register Offset (MONAO). R/W VSB 00h F3h Century Register Offset (CENO). R/W VSB 00h www.national.com 86 3.0 Device Architecture and Configuration (Continued) 3.16.3 RAM Lock Register (RLR) Once a non-reserved bit is set to 1, it can be cleared either by VDD Power-Up reset (or Hardware reset) or by VSB Power-Up reset, according to the VSBLOCK bit in the ACBLKCTL register (see Section 6.3.4 on page 127). In addition, all the bits are cleared by setting the UNLOCKR bit in the ACBLKCTL register (see Section 6.3.4 on page 127 - PC87413 and PC87417). Power Well: VSB Location: Index F0h Type: R/W1S Bit 7 6 5 4 3 Name BLSTR BLRWR BLEXRWR BLEXRRD BLEXR Reset 0 0 0 0 0 2 1 0 Reserved 0 0 0 Bit Description 7 BLSTR (Block Standard RAM). Disables both read and write access to locations 38h-3Fh of the Standard RAM (writes are ignored; reads return FFh). 0: Normal access (default) 1: Read and write to locations 38h-3Fh of the Standard RAM are blocked 6 BLRWR (Block RAM Write). Disables write access to both the Standard and Extended RAM (writes are ignored). 0: Normal access (default) 1: Writes to RAM (Standard and Extended) are blocked 5 BLEXRWR (Block Extended RAM Write). Disables write access to bytes 00h-1Fh of the Extended RAM (writes are ignored). 0: Normal access (default) 1: Writes to bytes 00h-1Fh of the Extended RAM are blocked 4 BLEXRRD (Block Extended RAM Read). Disables read access from bytes 00h-1Fh of the Extended RAM (reads return FFh). 0: Normal access (default) 1: Reads from bytes 00h-1Fh of the Extended RAM are blocked 3 BLEXR (Block Extended RAM). Disables both read and write access to the Extended RAM (writes are ignored; reads return FFh). 0: Normal access (default) 1: Read and write to the Extended RAM are blocked 2-0 Reserved. 87 www.national.com 3.0 Device Architecture and Configuration (Continued) 3.16.4 Date-of-Month Alarm Register Offset (DOMAO) Power Well: VSB Location: Index F1h Type: R/W Bit 7 Name Reserved Reset 0 6 5 6-0 3 2 1 0 0 0 0 DOMAO 0 0 Bit 7 4 0 0 Description Reserved. DOMAO (Date of Month Alarm Register Offset Value). Sets the offset value of the Date-of-Month Alarm (DOMA) runtime register. 3.16.5 Month Alarm Register Offset (MONAO) Power Well:VSB Location:Index F2h Type: R/W Bit 7 Name Reserved Reset 0 6 5 6-0 3 2 1 0 0 0 0 MONAO 0 0 Bit 7 4 0 0 Description Reserved. MONAO (Month Alarm Register Offset Value). Sets the offset value of the Month Alarm (MONA) runtime register. 3.16.6 Century Register Offset (CENO) Power Well: VSB Location: Index F3h Type: R/W Bit 7 Name Reserved Reset 0 Bit 7 6-0 6 5 4 3 2 1 0 0 0 0 CENO 0 0 0 0 Description Reserved. CENO (Century Register Offset Value). Sets the offset value of the Century (CEN) runtime register. www.national.com 88 4.0 LPC Bus Interface With the exception of the ACCESS.bus Interface, the host can access all the functional blocks of the PC8741x device through the LPC bus. 4.1 OVERVIEW The LPC host Interface supports 8-bit I/O Read, 8-bit I/O Write and 8-bit DMA transactions, as defined in Intel's LPC Interface Specification, Revision 1.0. 4.2 LPC TRANSACTIONS The LPC Interface of the PC8741x devices can respond to the following LPC transactions as part of the standard ServerI/O implementation: * * * 8-bit I/O read and write cycles. 8-bit DMA read and write cycles. DMA request cycles. In addition, the X-Bus bridge uses the following transactions (PC87416 and PC87417): * * * 8-bit I/O read and write cycles. 8-bit memory read and write. 8-bit FWH read LPC-FWH Cycles: The LPC bus and the ACCESS.bus (PC87413 and PC87417) use the internal bus of the PC8741x device to access the internal modules or to bridge transactions to the X-Bus (see the Block Diagrams on pages 1 and 5). In case both the LPC and the ACCESS.bus try to access targets (same or different) through the internal bus simultaneously, the LPC transaction is deferred until the end of the ACCESS.bus transaction. This is achieved by generating Long Wait SYNC cycles on the LPC bus. The amount of time the LPC bus waits depends on the duration of the ACCESS.bus transaction (see Section 6.2.10 on page 124). An LPC transaction that starts before an ACCESS.bus transaction is performed normally (i.e., without interference). The LPC-FWH read cycle is similar to the LPC memory read cycle, as shown below. The DATA, TAR and SYNC fields are as specified for LPC memory read cycle. The START field is similar to the equivalent field in the LPC memory read cycle but differs in the data placed on the LAD signals (see details in the cycle description). The Address field contains only seven nibbles (A27-A0), starting with the most significant. The IDSEL and MSIZE fields are specific to LPC-FWH transactions. FWH Read Cycle 1. START FWH Memory Read cycle type = 1101 (0Dh). 2. IDSEL FWH Device Select ID nibble (compared with the FWHID field in the XMEMCNF1 register, Section 3.15.11 on page 82). 3. MADDR Memory Address: seven address nibbles, MS nibble first (see LPC-FWH Address Translation:, below). 4. MSIZE Memory Size, single byte = 0000 (00h). 5. TAR (two cycles). 6. SYNC. 7. DATA Data: two nibbles, LS nibble first (D3-D0, D7-D4). 8. TAR (two cycles). The IDSEL field is compared with the FWHID field in the XMEMCNF1 register, described in Section 3.15.11 on page 82. If the two match, the PC8741x device continues handling the transaction; if not, the current LPC-FWH transaction is ignored. The MSIZE field is ignored by the PC8741x devices. LPC-FWH Address Translation: The address field in the LPC-FWH transaction is constructed of seven nibbles, containing the 28 LS address bits (A27-A0), as follows: the first incoming nibble corresponds to addresses A27-A24, the second to A23A20, and so forth, until the seventh nibble, which corresponds to A3-A0. The MS bits of the 32-bit addresses (A31-A28) are assumed to be `1111'. 89 www.national.com 4.0 LPC Bus Interface (Continued) 4.3 CLKRUN FUNCTIONALITY The PC8741x devices support the CLKRUN I/O signal, which is implemented according to the specification in PCI Mobile Design Guide, Revision 1.1, December 18, 1998. The PC8741x devices support operation with both a slow and stopped clock in ACPI state S0 (the system is active but is not being accessed). In the following cases, the PC8741x device drives the CLKRUN signal low to force the LPC bus clock into full speed operation: An IRQ is pending internally, waiting to be sent through the serial IRQ. A DMA request is pending internally, waiting to be sent through the serial DMA. Note: When the CLKRUN signal is not in use, the PC8741x devices assume a valid clock on the LCLK pin. 4.4 INTERRUPT SERIALIZER The Interrupt Serializer translates parallel interrupt request (PIRQ) signals received from external devices, via the XIRQ pin (PC87416 and PC87417) and from internal IRQ sources, into serial interrupt request data transmitted over the SERIRQ bus. This enables devices that support only parallel IRQs to be integrated into a system that supports only serial IRQs. The external XIRQ signal and the internal IRQs are fed into a Mapping, Enable and Polarity Control block, which maps them to their associated IRQ slots. The IRQs are then fed into the Interrupt Serializer, where they are translated into serial data and transmitted over the SERIRQ bus. The XIRQ input value is routed to the Interrupt Serializer as the IRQn value to be driven onto IRQ slot n. The same slot cannot be shared among different interrupt sources in the device. When a transition is sensed on an IRQ source, the new value of the IRQ source is transmitted over the SERIRQ bus during the corresponding IRQ slot. For example, when a transition on XIRQ is sensed, the new value of XIRQ is transmitted during slot n of the SERIRQ bus. Figure 11 shows the mechanism for both interrupt serialization and wake-up. Bus Interface Internal IRQ Sources IRQ1 IRQ Mapping and Polarity Control XIRQ Interrupt Serializer IRQ15 (PC87416 and PC87417) Control Signals Wake-Up Enable Control SWC Figure 11. Interrupt Serialization and Wake-Up Mechanism www.national.com 90 SERIRQ 5.0 X-Bus Extension This section is relevant only for the PC87416 and PC87417. In the PC87413 and PC87414, all X-Bus Extension bits and signals that influence other modules are at their default value. 5.1 OVERVIEW The PC8741x provides an X-Bus extension to the LPC bus or ACCESS.bus to enable the connection of external 8-bit memories or peripherals through the X-Bus's ISA-like interface. A single read/write line and an enable pin replace the ISAlike protocol. The decode logic, described in Section 3.15 on page 74, defines the addresses for which the X-Bus generates transactions that occur in the I/O address space and memory address space or in the FWH memory address space. Using the X-Bus Interface, the PC8741x serves as a bridge for such transactions over the X-Bus. Figure 12 is a block diagram of the X-Bus bridging function. For details on the decoder functions, see Section 3.15 on page 74. All other functions are described in detail in this section. IRQ Serializer XA11-0 X-Bus Configuration XD7-0 Device Architecture Module X-Bus Interface MUX ACCESS.bus ACCESS.bus Interface I/O Address Decoder XCS0 MUX Memory Address Decoder XRD_XEN XWR_XRW XSTB2-0 XRDY XCS1 MUX Bus Cycle Generator XCS2 MUX LPC Interface LPC Bus XIRQ IRQ Router Internal Bus SERIRQ XCS3 XCNF2-0 Figure 12. X-Bus Extension Block Diagram The PC8741x supports one IRQ input: XIRQ. This pin may be used to support external legacy devices that are connected on the X-Bus. The interrupt from this pin can be routed to any one of 15 host IRQs. The IRQ input is mapped by the X-Bus XIRQ Mapping register at FCh. The XIRQC register enables the user to define the interrupt as active high or low and to route it to a wake-up event. 5.2 X-BUS TRANSACTIONS The X-Bus extension supports 8-bit I/O or Memory read/write cycles. The zone mapping of the chip-select signals determines how X-Bus read and write cycles correspond to memory and I/O LPC bus cycles. The zone mapping to a select signal (XCS3-0) must be enabled in order for the zone to respond to LPC transactions. However, when the chip-select signal is not required by an off-chip device, multiplexing the chip select to a pin is not necessary. 91 www.national.com 5.0 X-Bus Extension (Continued) There are two X-Bus address modes: Normal Address mode - A signal is assigned for each address line (only XA11-XA0 are available at the device pins) and a non-multiplexed address data bus is used. In this mode, only address signals 0 through 19 are generated. Latched Address mode - The number of pins used for outputting the address is reduced. The address lines are multiplexed with the data bus. External latches may be used to generate address signals from the multiplexed bus. These address signals are required to access memory and I/O devices. In this mode address, signals 0 through 27 are generated, allowing access to memory in excess of 1 Mbyte. There are two X-Bus transaction modes: Mode 0 - The X-Bus transactions are ISA-like, using separate read and write signals. XWR_XRW functions as the write signal (XWR); XRD_XEN functions as the read signal (XRD). The following speed levels are available for Mode 0, X-Bus transactions: -- Normal -- Fast -- Turbo Mode 1 - The X-Bus transactions are read/write and enable controlled transactions, using XWR_XRW as the read and write signal (XRW) and XRD_XEN as the enable signal (XEN). When XWR_XRW is high, it identifies a read transaction; when low, it identifies a write transaction. 5.2.1 Transaction Clock X-Bus access timing is referenced to an internal clock referred to as CLK or "the clock". Transactions are described in terms of this clock and the AC specifications are also defined relative to it. This provides an easy way for calculating the timing during system design. Note that the system interface is optimized for an asynchronous interface. For hints on how to use the asynchronous interface, refer to the usage hints in Section 5.5 on page 114. X-Bus Clock: For transactions triggered by the LPC bus, the clock is an internal version of the LPC clock (i.e., it has the same frequency but may have some phase delay). For transactions driven by the ACCESS.bus (PC87417), the clock is the Standby clock as defined in Section 2.3.1 on page 35. 5.2.2 Programmable Range Chip Select The PC8741x has four chip-select signals (XCS3-0) to control the X-Bus accesses to off-chip devices. The PC8741x X-Bus functional block enables flexible association of these chip selects with I/O and memory address ranges in the LPC address space. The Zone Mapping field of the X-Bus Select Configuration registers defines the decoded address range(s) to which the specific XCSn signal responds. In addition, the X-Bus Configuration register enables specifying the access time for each select signal via bits that control the fixed wait and variable wait cycles (using the XRDY input). If the chip-select signal setting results in a conflict in which one or more selects are configured for the same zone, XCS0 has the highest priority and XCS3 has the lowest. The XCSn signal with the lower priority remain inactive and their Select Configuration register setting is ignored. For zones that are not associated with one of the chip-select signals, the X-Bus does not respond to LPC transactions. In addition, X-Bus transactions may be generated in response to a request from the ACCESS.bus (PC87417). In such a case, the target select signal (XCS3) and the offset address are specified in the ACCESS.bus protocol. See Section 6.2.9 on page 120 for the specification of ACCESS.bus operation. 5.2.3 LPC and FWH Address-to-X-Bus Address Translation The BIOS memory on the LPC bus can occupy one of three regions in the memory space (see Table 28 on page 75). Address translation between the LPC bus address and the X-Bus is performed as follows: I/O Transactions. The 16-bit address received from the LPC bus is used to decode the different I/O zones described in Section 3.15.2 on page 74. The address is then left-padded with zeroes (address lines 16 through 27) to create the 28-line input address to the X-Bus Extension functional block. www.national.com 92 5.0 X-Bus Extension (Continued) Memory Transactions. The 32-bit address received from the LPC bus is used to decode the different memory zones described in Section 3.15.3 on page 75. The address is then translated to the X-Bus address, using the following rules: User-Defined Memory Zones (MEM 0 and MEM 1) and 386 Mode-Compatible BIOS Range: The 28 least significant address lines of the LPC address are used as the X-Bus input address. Figure 13 illustrates the mapping for this zone. Legacy and Extended Legacy BIOS Range: The 17 least significant address lines (A16-0) of the LPC address are routed as the 17 least significant address signals of the X-Bus (XA16-0). The upper 11 X-Bus address lines are driven to `1'. This shifts the addresses to the top of the X-Bus memory space (see Figure 14). X-Bus Address LPC Bus Address xFFF FFFFh FFFC 0000h xFFC 0000h ******* FFFF FFFFh 0000 0000h Figure 13. LPC-to-X-Bus Address Translation: 386 Mode-Compatible BIOS Range X-Bus Address LPC Bus Address FFFF FFFFh xFFF FFFFh 000F FFFFh Legacy BIOS xFFE 0000h 000F 0000h 000E FFFFh Extended Legacy BIOS ******* 000E 0000h 0000 0000h Figure 14. LPC-to-X-Bus Address Translation: Legacy and Extended Legacy BIOS Ranges 93 www.national.com 5.0 X-Bus Extension 5.2.4 (Continued) Indirect Memory Read and Write Transactions I/O mapped registers accessed through an LPC I/O transaction may be used to perform an X-Bus memory transaction. This mechanism uses the following X-Bus Extension module registers: Four Indirect Memory Address registers (XIMA3-0), representing address bits 31 to 0. One Indirect Memory Data register (XIMD), representing data bits 7 to 0. Four enable bits, one for each Select Configuration register, XZCNF0, XZCNF1, XZCNF2 and XZCNF3. Following an LPC I/O write to the XIMD register, a Memory write cycle is initiated on the X-Bus using the addresses from the previously written XIMA3-0 registers and data from the XIMD register. Following an LPC I/O read from the XIMD register, a Memory read cycle is initiated on the X-Bus using the address from the XIMA3-0 registers. The returned data from the XBus cycle is used to finish the read cycle from the XIMD register. Indirect memory transactions may be enabled for one chip-select signal only. If more than one enable bit in the Select Configuration registers is set, the indirect memory access will be available only for the XCSn with the highest priority. The setting of the enable bit for the chip selects with lower priority will be ignored. XCS0 has the highest priority and XCS3 has the lowest priority. 5.2.5 Mode 0, Normal Address X-Bus Transactions The read and write transactions in Normal Address mode are similar to those used in the X-Bus or ISA bus. At least two idle cycles are inserted at the end of each X-Bus transaction cycle before the next transaction starts (there may be more idle cycles due to the LPC transactions). This mode is selected for transactions accessing XCSn by setting TRANSMD = 0 in the corresponding XZMn register. Read Transactions. When a read cycle on the LPC falls within an enabled decoded address range of the X-Bus functional block (or an indirect read is started or an X-Bus read through the ACCESS.bus is started) and the relevant XCSn is set to mode 0, a Mode 0 read cycle begins. A read cycle (see Figure 15) starts by outputting the address on address signals XA110 on the rising edge of the clock. During this time, the PC8741x device does not drive the data bus signals XD7-0. One CLK cycle later, a chip-select signal XCSn is asserted, where n is a chip-select number from 0 to 3, based on the address accessed and the select signal mapping. Three CLK cycles later, on the rising edge of the clock, the XRD signal is asserted (set low), indicating a read cycle and enabling the accessed device to drive the data bus. After 16 CLK cycles plus the internally programmed wait state period, if XRDY use is enabled for this zone, its value is then sampled on the rising edge of the clock. The transaction is extended until XRDY is detected to be high. Four CLK cycles later, the input data XD7-0 is sampled on the rising edge of the clock. One CLK cycle later, XRD is de-asserted (set high) and one CLK cycle after that, the transaction is completed by de-asserting XCSn. The address is retained for two more CLK cycles after which the address lines are driven to 0. www.national.com 94 5.0 X-Bus Extension (Continued) CLK (Internal; for Reference Only) XD7-0 XD7-0 (Data In) (Data Read) XA11-0 XCSn XWR_XRW XRD_XEN XRDY Insert: 12 + "Programmed Wait States" CLK cycles here. During this time, non-clock signals do not change. Figure 15. Mode 0, Normal Address X-Bus Transaction - Read Access Cycle Write Transactions. When a write cycle on the LPC falls within any of the enabled decoded address ranges of the X-Bus functional block (or an indirect write is started or an X-Bus write through the ACCESS.bus is started) and the relevant XCSn is set to mode 0, a Mode 0 write cycle begins. A write cycle (see Figure 16) starts by outputting the address on address signals XA11-0 and the data signals on data pins XD7-0 on the rising edge of the clock. One CLK cycle later, a chip-select signal XCSn is asserted, where n is a chip-select number from 0 to 3, based on the address accessed and the select signal mapping. Three CLK cycles later, on the rising edge of the clock, the XWR signal is asserted (set low), indicating a write cycle and enabling the accessed device to be written. After 16 CLK cycles plus the internally programmed wait state period, if XRDY use is enabled for this zone, its value is then sampled on the rising edge of the clock. The transaction is extended until XRDY is detected to be high. Five CLK cycles later, XWR is de-asserted (set high) and one CLK cycle later, the transaction is completed by de-asserting XCSn and floating the data bus signals XD7-0. Two CLK cycles later, the address lines are driven to 0. 95 www.national.com 5.0 X-Bus Extension (Continued) CLK (Internal; for Reference Only) XD7-0 XA11-0 XCSn XWR_XRW XRD_XEN XRDY Insert: 12 + "Programmed Wait States" CLK cycles here. During this time, non-clock signals do not change. Figure 16. Mode 0, Normal Address X-Bus Transaction - Write Access Cycle 5.2.6 Mode 0, Normal Address, Fast X-Bus Transactions The read and write transactions in Normal Address, Fast X-Bus transactions are similar to those in Mode 0, Normal Address X-Bus Transactions on page 94, differing only in the delay for valid data. Because Normal Address, Fast X-Bus transactions have 14 to 20 fewer cycles than Normal Address transactions, they can be used to speed up access to fast devices. The gray areas in Figures Figure 15 and Figure 16 (+ 2 CLK cycles) represent the additional cycles that Fast transactions (Figures Figure 17 and Figure 18) do not perform. This mode is selected for transactions accessing XCSn by setting TRANSMD = 0 and TRANSPD = 1 in the corresponding XZMn register. www.national.com 96 5.0 X-Bus Extension (Continued) CLK (Internal; for Reference Only) XD7-0 XD7-0 (Data In) (Data Read) XA11-0 XCSn XWR_XRW XRD_XEN XRDY Figure 17. Mode 0, Normal Address, Fast X-Bus Transaction - Read Access Cycle CLK (Internal; for Reference Only) XD7-0 XA11-0 XCSn XWR_XRW XRD_XEN XRDY Figure 18. Mode 0, Normal Address, Fast X-Bus Transaction - Write Access Cycle 97 www.national.com 5.0 X-Bus Extension 5.2.7 (Continued) Mode 0, Normal Address, Turbo X-Bus Transactions The read and write transactions in Normal Address, Turbo X-Bus transactions provide a lower access time than those in Mode 0, Normal Address, Fast X-Bus transactions. Because Normal Address, Turbo X-Bus transactions have seven fewer cycles than Normal Address, Fast X-Bus transactions, they efficiently access very fast devices. This mode is selected for transactions accessing XCSn by setting TRANSMD = 0 in the corresponding XZMn register and TBXCSn = 1 in the XBCNF register. Read Transactions. When a read cycle on the LPC starts and the relevant XCSn is set to Turbo mode, a Mode 0, Normal Address, Turbo X-Bus Transaction read cycle begins. A read cycle (Figure 21, below) starts by outputting the address on address signals XA11-0 on the rising edge of the clock. During this time, the PC8741x device does not drive the data bus signals XD7-0. One CLK cycle later, a chip-select signal XCSn is asserted. One CLK cycle after that, the XRD signal is asserted (set low), indicating a read cycle and enabling the accessed device to drive the data bus. In Turbo X-Bus transactions, XRDY is ignored. Two CLK cycles later, the input data XD7-0 is sampled on the rising edge of the clock. One CLK cycle after that, XRD is de-asserted (set high) and one CLK cycle later, the transaction is completed by de-asserting XCSn. The address is retained for one more CLK cycle, after which the address lines are driven to 0. CLK (Internal; for Reference Only) XD7-0 XD7-0 (Data Read) XA11-0 XCSn XWR_XRW XRD_XEN Figure 19. Mode 0, Normal Address, Turbo X-Bus Transaction - Read Access Cycle Write Transactions. When a write cycle on the LPC starts and the relevant XCSn is set to Turbo mode, a Mode 0, Normal Address, Turbo X-Bus Transaction write cycle begins. A write cycle (Figure 22, below) starts by outputting the address on address signals XA11-0 and the data signals on data pins XD7-0 on the rising edge of the clock. One CLK cycle later, a chipselect signal XCSn is asserted. One CLK cycle after that, the XWR signal is asserted (set low), indicating a write cycle and enabling the accessed device to be written. In Turbo X-Bus transactions, XRDY is ignored. Three CLK cycles later, XWR is de-asserted (set high) and one CLK cycle after that, the transaction is completed by de-asserting XCSn and floating the data bus signals XD7-0. One CLK cycle later, the address lines are driven to 0. CLK (Internal; for Reference Only) XD7-0 XA11-0 XCSn XWR_XRW XRD_XEN Figure 20. Mode 0, Normal Address, Turbo X-Bus Transaction - Write Access Cycle www.national.com 98 5.0 X-Bus Extension 5.2.8 (Continued) Mode 1, Normal Address Transactions Read and write transactions in mode 1 use an Enable signal and a R/W signal controlled protocol. At least two idle cycles are inserted at the end of each X-Bus transaction cycle (though there may be more idle cycles due to the LPC transactions). This mode is selected for transactions accessing XCSn by setting TRANSMD = 1 in the corresponding XZMn register. Read Transactions. When a read cycle on the LPC falls within any of the enabled decoded address ranges of the X-Bus functional block (or an indirect read is started or an X-Bus read through the ACCESS.bus is started) and the relevant XCSn is set to mode 1, a Mode 1 read cycle begins. A Mode 1 read cycle (see Figure 21) begins with the de-assertion of XRD_XEN (set low). At the same time, the address is driven on the XA11-0. Ten CLK cycles later, XCSn is asserted (set low). After five CLK cycles, XRD_XEN is asserted (set high) and remains asserted for 18 cycles plus the internally programmed wait state period. During the period that XRD_XEN is asserted, the data must be driven on XD7-0 by the target device. XRD_XEN is then de-asserted for two CLK cycles. The data from XD7-0 is sampled at the rising edge of the clock one CLK cycle before XRD_XEN is de-asserted. At the end of these two CLK cycles, XCSn is set high, and after one CLK cycle, XRD_XEN is also set high. One CLK cycle later, the address lines XA11-0 are driven low. CLK (Internal; for Reference Only) XD7-0 Data In XA11-0 XCSn XWR_XRW XRD_XEN Insert: 8 CLK cycles. Insert: 16 + "Programmed Wait States" CLK cycles. During this time, non-clock signals do not change. Figure 21. Mode 1, Normal Address X-Bus Transaction - Read Access Cycle Write Transactions. When a write cycle on the LPC falls within any of the enabled decoded address ranges of the X-Bus functional block (or an indirect write is started or an X-Bus write through the ACCESS.bus is started) and the relevant XCSn is set to mode 1, a Mode 1 write cycle begins. A mode 1 write cycle (see Figure 22) begins with a de-assertion of XRD_XEN (set low). At the same time, the address is driven on the XA11-0 and the data is driven on XD7-0. After ten CLK cycles, XCSn and XWR_XRW are asserted (set low). After five CLK cycles, XRD_XEN is asserted (set high) and remains asserted for 18 cycles plus the internally programmed wait state period. XRD_XEN is then de-asserted for two CLK cycles. At the end of these two CLK cycles, XCSn is set high. After another CLK cycle, XWR_XRW and XRD_XEN are set high. Address lines XA11-0 are driven low one CLK cycle later (at the end of the transaction). 99 www.national.com 5.0 X-Bus Extension (Continued) CLK (Internal; for Reference Only) XD7-0 XA11-0 XCSn XWR_XRW XRD_XEN Insert: 16 + "Programmed Wait States" CLK cycles. During this time, non-clock signals do not change. Insert: 8 CLK cycles. Figure 22. Mode 1, Normal Address X-Bus Transaction - Write Access Cycle 5.2.9 Latched Address Mode X-Bus Transactions The read and write transactions in Latched Address mode are similar to those used in Normal Address mode except for the way the addresses are placed on the X-Bus. In Latched Address mode, address signals 27-0 are output using the XA signals via multiplexing over the data bus (XD7-0). The purpose of Latch control signals XSTB2-0 is to separate the XA signals from the XD7-0 data bus. The XSTB2-0 signals are active from the time the address signals are valid (and until the end of a transaction). Latched address X-Bus transactions are available at two levels: Standard - standard access time transactions available in mode 0, mode 0 fast, and mode 1. Turbo - low access time transactions available in mode 0 turbo. Standard Read Transactions. When a read cycle on the LPC falls within any of the enabled X-Bus decoded address ranges (or an indirect read is started or an X-Bus read through the ACCESS.bus is started), a read cycle begins. A read cycle starts by outputting the lower 12 address signals on address signals XA11-0 and by outputting address lines 27-20 on data signals XD7-0 on the rising edge of the clock. Two CLK cycles later, a strobe signal (XSTB2) is asserted to latch the address in an external latch. Two CLK cycles later, a second set of address lines (19-12) is placed on data pins XD7-0. These can be latched by the strobe signal XSTB1 asserted two cycles later on the rising edge of the clock. Two CLK cycles later, the last group of address lines (11-4) is placed on data signals XD7-0. The XSTB0, asserted two cycles later on the rising edge of the clock, can be used to latch this part of the address. Two CLK cycles later on the rising edge of the clock, the PC8741x stops driving the data bus. At this point, all addresses are available either at the address outputs of the PC8741x (XA11-0) or in the three latches. The system may require only part of these addresses, depending on the size of the memory or peripheral address space. One CLK cycle later, either a chip-select signal XCSn or the enable signal XRD_XEN is asserted, based on the XCSn mode setting (where n is a chip-select number from 0 to 3, based on the address accessed and the select signal mapping). From this point, the read continues as described for the Normal Address mode. XSTB2-0 are deasserted one CLK cycle after the de-assertion of XCSn. At this time, the latched address becomes invalid. www.national.com 100 5.0 X-Bus Extension (Continued) CLK (Internal; for Reference Only) A [27-20] XD7-0 A [19-12] A [11-4] XSTB2 XSTB1 XSTB0 XA11-0 (Availability on Device Pins Depends on Multiplexing) XA27-0 (After Latching) XCSn Starting point for mode 0 XRD_XEN Starting point for mode 1 XWR_XRW XRDY Transaction Continues as for Non-Latched Address Mode 0 and Mode 1 Read Figure 23. Standard Latched Address Mode - X-Bus Read Access Cycle Standard Write Transactions. When a write cycle on the LPC falls within any of the enabled decoded address ranges of the X-Bus functional block (or an indirect write is started or an X-Bus write through the ACCESS.bus is started), a write cycle begins. A write cycle starts by outputting the lower 12 address signals on address signals XA11-0 and address lines 27-20 on data signals XD7-0 on the rising edge of the clock. Two CLK cycles later, a strobe signal (XSTB2) is asserted to latch the address in an external latch. Two CLK cycles after that, a second set of address lines (19-12) is placed on data pins XD7-0. These can be latched by the strobe signal XSTB1 asserted two cycles later on the rising edge of the clock. Two CLK cycles later, the last group of address lines (11-4) is output on the data signals XD7-0. The XSTB0, asserted two CLK cycles later on the rising edge of the clock, can be used to latch this part of the address. Two CLK cycles later on the rising edge of the clock, the PC8741x outputs the data signals on data pins XD7-0. At this point, all the addresses are available either at the address outputs of the PC8741x (XA11-0) or at the outputs of the three latches. The system may require only part of these addresses, depending on the size of the memory or peripheral address space. One CLK cycle later, either a chip-select signal XCSn or the enable signal XRD_XEN is asserted, based on the XCSn mode setting (where n is a chip-select number from 0 to 3, based on the address accessed and the select signal mapping). From this point, the write continues as described for the Normal Address mode. XSTB2-0 are de-asserted one CLK cycle after the de-assertion of XCSn. At this time, the latched address becomes invalid. 101 www.national.com 5.0 X-Bus Extension (Continued) CLK (Internal; for Reference Only) A [27-20] XD7-0 A [19-12] A [11-4] D [7-0] XSTB2 XSTB1 XSTB0 XA11-0 (Availability on Device Pins Depends on Multiplexing) XA27-0 (After Latching) XCSn Starting point for mode 0 XRD_XEN Starting point for mode 1 XWR_XRW XRDY Transaction Continues as for Non-Latched Address Mode 0 and Mode 1 Write Figure 24. Standard Latched Address Mode - X-Bus Write Access Cycle Turbo Read Transactions. A Turbo read cycle starts by outputting the lower 12 address signals on address signals XA11-0 and by outputting address lines 27-20 on data signals XD7-0 on the rising edge of the clock. One CLK cycle later, a strobe signal (XSTB2) is asserted to latch the address in an external latch. One CLK cycle after that, a second set of address lines (19-12) is placed on data pins XD7-0. These can be latched by the strobe signal XSTB1, asserted one cycle later on the rising edge of the clock. One CLK cycle later, the last group of address lines (11-4) is placed on data signals XD7-0. The XSTB0, asserted one cycle later on the rising edge of the clock, can be used to latch this part of the address. One CLK cycle later on the rising edge of the clock, the PC8741x stops driving the data bus. At this point, all addresses are available either at the address outputs of the PC8741x (XA11-0) or in the three latches. The system may require only part of these addresses, depending on the size of the memory or peripheral address space. One CLK cycle later, the chip-select signal XCSn is asserted, based on the XCSn Turbo mode setting. From this point, the read continues as described for the Normal Address Turbo transaction, Mode 0. XSTB2-0 are de-asserted one CLK cycle after the de-assertion of XCSn. At this time, the latched address becomes invalid. At the same time, the address signals XA11-0 are driven to low level. www.national.com 102 5.0 X-Bus Extension (Continued) CLK (Internal; for Reference Only) A A [27-20] [19-12] XD7-0 A [11-4] XSTB2 XSTB1 XSTB0 XA11-0 (Availability on Device Pins Depends on Multiplexing) XA27-0 (After Latching) Starting point XCSn XRD_XEN XWR_XRW Transaction Continues as for Non-Latched, Turbo X-Bus Address Mode 0 Read Figure 25. Turbo Latched Address Mode - X-Bus Read Access Cycle Turbo Write Transactions. A Turbo write cycle starts by outputting the lower 12 address signals on address signals XA11-0 and by outputting address lines 27-20 on data signals XD7-0 on the rising edge of the clock. One CLK cycle later, a strobe signal (XSTB2) is asserted to latch the address in an external latch. One CLK cycle after that, a second set of address lines (19-12) is placed on data pins XD7-0. These can be latched by the strobe signal XSTB1, asserted one cycle later on the rising edge of the clock. One CLK cycle later, the last group of address lines (11-4) is output on the data signals XD70. The XSTB0, asserted one CLK cycle later on the rising edge of the clock, can be used to latch this part of the address. One CLK cycle later on the rising edge of the clock, the PC8741x outputs the data signals on data pins XD7-0. At this point, all the addresses are available either at the address outputs of the PC8741x (XA11-0) or at the outputs of the three latches. The system may require only part of these addresses, depending on the size of the memory or peripheral address space. One CLK cycle later, the chip-select signal XCSn is asserted, based on the XCSn Turbo mode setting. From this point, the write continues as described for the Normal Address Turbo transaction, Mode 0. XSTB2-0 are de-asserted one CLK cycle after the de-assertion of XCSn. At this time, the latched address becomes invalid. At the same time, the address signals XA11-0 are driven to low level. 103 www.national.com 5.0 X-Bus Extension (Continued) CLK (Internal; for Reference Only) A A [27-20] [19-12] XD7-0 A [11-4] D [7-0] XSTB2 XSTB1 XSTB0 XA11-0 (Availability on Device Pins Depends on Multiplexing) XA27-0 (After Latching) Starting point XCSn XRD_XEN XWR_XRW Transaction Continues as for Non-Latched, Turbo X-Bus Address Mode 0 Write Figure 26. Turbo Latched Address Mode - X-Bus Write Access Cycle 5.3 X-BUS PROTECTION The PC8741x devices include a mechanism to protect the settings of the X-Bus mapping functions and the contents of the memories mapped to it. This mechanism consists of three separate lock mechanisms, which must all be in use to obtain the most comprehensive protection: Lock the memory mapping by the host, using the lock bit in the X-Bus Memory Configuration register and X-Bus I/O Configuration register. Lock the bits of the X-Bus Select n Configuration register and X-Bus Mode n register, using the lock bit in the respective X-Bus Mode register. A Memory protection mechanism is available for XCS0 and XCS1. This protects the contents of up to two memory devices (one for each chip-select) for read and/or write with a granularity of 16 blocks each. This is done using the Host Access Protect registers 0 and 1 for XCS0 and XCS1, respectively. Note that access protection is provided only for XCS0 and XCS1. Absolute access protection is only enabled by using all three lock levels. The Memory protection mechanism pertains to the X-Bus address and the chip-select (XCS0 or XCS1) involved in the transaction. The size of a protected block is determined by dividing the size of each BIOS Zone by 16 (see Section 3.15.12 on page 83). Table 31 on page 105 shows the protected block size for different BIOS Zone sizes. www.national.com 104 5.0 X-Bus Extension (Continued) Table 31. Protected Block Size BIOS Zone Size BIOSIZE2-BIOSIZE0 Protected Block Size Address Lines Used for Block Selection1,2 256 Kbyte 000 16 Kbyte XA17-XA14 512 Kbyte 001 32 Kbyte XA18-XA15 1 Mbyte 010 64 Kbyte XA19-XA16 2 Mbyte 011 128 Kbyte XA20-XA17 4 Mbyte 100 256 Kbyte XA21-XA18 8 Mbyte 101 512 Kbyte XA22-XA19 16 Mbyte 110 1 Mbyte XA23-XA20 1. Selects the block according to the HAPINDX3-HAPINDX0 setting in the HAP0-HAP1 registers. 2. All the other address lines are ignored. A read/write transaction to/from a protected block is not allowed to take place if, for the respective block number, the HWRP/HRDP bit is set in the HAP0 or HAP1 register (see Section 5.4.11 on page 113). This includes both memory and I/O transactions. To prevent bypassing the protection by selecting additional non-BIOS zones to XCS0 or XCS1, the upper lines of the address are not used for block selection. This results in the aliasing of a protected block in each area of X-Bus memory space that has the same size as the BIOS Zone (see Figure 27). X-Bus Memory Space FFF FFFFh BIOS Zone Size Protected Block n BIOS Zone Size Protected Block n .... BIOS Zone Size Protected Block n BIOS Zone Size Protected Block n 000 0000h Figure 27. Protected Block Aliasing The SMI interrupt generated on access to XCS0 and XCS1 may be used to allow flash updates under System Management protection. 105 www.national.com 5.0 X-Bus Extension (Continued) 5.4 X-BUS REGISTERS The following abbreviations are used to indicate the Register Type: R/W = Read/Write. R = Read from a specific register (write to the same address is to a different register). W = Write (see above). RO = Read Only. WO = Write Only. Reading from the bit returns 0. R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect. R/W1S = Read/Write 1 to Set. Writing 1 to a bit sets its value to 1. Writing 0 has no effect. 5.4.1 X-Bus Register Map The following table lists the X-Bus registers. All these registers are VSB powered. Offset Mnemonic 00h XBCNF 01h Type Power Well Section X-Bus Configuration Register. R/W or RO VSB 5.4.2 XZCNF0 X-Bus Select 0 Configuration Register. R/W or RO VSB 5.4.3 02h XZCNF1 X-Bus Select 1 Configuration Register. R/W or RO VSB 5.4.3 04h XIRQC X-Bus IRQ Configuration Register. R/W VSB 5.4.4 08h XIMA0 X-Bus Indirect Memory Address Register 0. R/W VSB 5.4.5 09h XIMA1 X-Bus Indirect Memory Address Register 1. R/W VSB 5.4.6 0Ah XIMA2 X-Bus Indirect Memory Address Register 2. R/W VSB 5.4.7 0Bh XIMA3 X-Bus Indirect Memory Address Register 3. R/W VSB 5.4.8 0Ch XIMD X-Bus Indirect Memory Data Register. R/W VSB 5.4.9 0Dh XZCNF2 X-Bus Select 2 Configuration Register. R/W or RO VSB 5.4.3 0Eh XZCNF3 X-Bus Select 3 Configuration Register. R/W or RO VSB 5.4.3 0Fh XZM0 X-Bus Select 0 Mode Register. Varies per bit VSB 5.4.10 10h XZM1 X-Bus Select 1 Mode Register. Varies per bit VSB 5.4.10 11h XZM2 X-Bus Select 2 Mode Register. Varies per bit VSB 5.4.10 12h XZM3 X-Bus Select 3 Mode Register. Varies per bit VSB 5.4.10 13h HAP0 Host Access Protect Register 0. Varies per bit VSB 5.4.11 14h HAP1 Host Access Protect Register 1. Varies per bit VSB 5.4.11 Other www.national.com Register Name Reserved for National use. 106 5.0 X-Bus Extension 5.4.2 (Continued) X-Bus Configuration Register (XBCNF) This register affects the functionality mode of the X-Bus. Power Well: VSB Location: Offset 00h Type: R/W or RO Bit 7 6 5 4 Name TBXCS3 TBXCS2 TBXCS1 TBXCS0 Reset 0 0 0 0 3 2 1 Reserved 0 0 0 LADEN 0 Strap Bit Description 7 TBXCS3 (Turbo Transactions on XCS3). When set to 1 and mode 0 is selected (TRANSMD = 0 in the XZM3 register), enables Turbo X-Bus transactions (see Section 5.2.7 on page 98) when XCS3 is accessed. The Turbo transactions are Normal Address or Latched Address (see Section 5.2.9 on page 100), according to the setting of the LADEN bit. This bit is locked by setting at least one of the LOCKXSCF bits in the XZM0-XZM3 registers. 0: Disabled (default) 1: Enabled 6 TBXCS2 (Turbo Transactions on XCS2). When set to 1 and mode 0 is selected (TRANSMD = 0 in the XZM2 register), enables Turbo X-Bus transactions (see Section 5.2.7 on page 98) when XCS2 is accessed. The Turbo transactions are Normal Address or Latched Address (see Section 5.2.9 on page 100), according to the setting of the LADEN bit. This bit is locked by setting at least one of the LOCKXSCF bits in the XZM0-XZM3 registers. 0: Disabled (default) 1: Enabled 5 TBXCS1 (Turbo Transactions on XCS1). When set to 1 and mode 0 is selected (TRANSMD = 0 in the XZM1 register), enables Turbo X-Bus transactions (see Section 5.2.7 on page 98) when XCS1 is accessed. The Turbo transactions are Normal Address or Latched Address (see Section 5.2.9 on page 100), according to the setting of the LADEN bit. This bit is locked by setting at least one of the LOCKXSCF bits in the XZM0-XZM3 registers. 0: Disabled (default) 1: Enabled 4 TBXCS0 (Turbo Transactions on XCS0). When set to 1 and mode 0 is selected (TRANSMD = 0 in the XZM0 register), enables Turbo X-Bus transactions (see Section 5.2.7 on page 98) when XCS0 is accessed. The Turbo transactions are Normal Address or Latched Address (see Section 5.2.9 on page 100), according to the setting of the LADEN bit. This bit is locked by setting at least one of the LOCKXSCF bits in the XZM0-XZM3 registers. 0: Disabled (default) 1: Enabled 3-1 0 5.4.3 Reserved. LADEN (Latch Address Mode Enabled). When set to 1, enables addresses XA27-XA4 to be multiplexed with the data pins in three phases. Reset value of this bit is set according to the XCNF2 strap, sampled at VSB Power-Up reset. See Section 1.4.11 on page 28 for the definition of strap setting. This bit is locked by setting at least one of the LOCKXSCF bits in the XZM0-XZM3 registers. 0: Disabled (default if XCNF2 = 0 - No BIOS) 1: Enabled (default if XCNF2 = 1 - With BIOS) X-Bus Select Configuration Registers (XZCNF0 to XZCNF3) These registers control the mapping of I/O and Memory Zones to XCSn, where n is from 0 to 3. Power Well: VSB Location: Offset 01h (XZCNF0) Location: Offset 02h (XZCNF1) Location: Offset 0Dh (XZCNF2) Location: Offset 0Eh (XZCNF3) Type: R/W or RO 107 www.national.com 5.0 X-Bus Extension Bit (Continued) 7 6 5 Name 4 XRDYEN WAITSEN INDIRMEN ZSELMAP Reset Strap 1 0 Strap Bit 7 3 2 1 0 Description XRDYEN (XRDY Enable). Enables the use of XRDY input for the zones mapped to XCSn. The reset value of this bit depends on the setting of XCNF2 and XCNF0 straps, sampled at VSB Power-Up reset. 0: Disabled (default for XZCNF1-3; default for XZCNF0 if XCNF0 = 0 or XCNF2 = 0) 1: Enabled (default for XZCNF0 if XCNF0 = 1 and XCNF2 = 1) 6 WAITSEN (Wait States Enable). This bit controls the number of wait states added to an X-Bus transaction. If the TRANSPD bit in the XZM0 to XZM3 registers is set, the setting of WAITSEN is ignored (wait states are disabled). 0: Wait states disabled 1: Eight wait states (CLK cycles) enabled (default) 5 INDIRMEN (Indirect Memory Access Enable). Enables indirect memory access mechanism to generate memory transactions through XCSn. 0: Disabled (default) 1: Enabled 4-0 ZSELMAP (Zone Select Mapping). UDIZ = User-Defined I/O Zone. MEM = User-Defined Memory Zone. = XCSn does not respond to this zone decode. + = XCSn responds to this zone decode and is influenced by its setting. Bits Function 4 3 2 1 0 UDIZ0 UDIZ1 UDIZ2 UDIZ3 TST BIOS0 BIOS1 MEM0 MEM1 00000 - 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 Others + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Reserved www.national.com - - - - - - - - + + + + + + + + + + + - + + + + + + + - + + + + + + + + + - + + + + + + + + + - + + + - + + + + + + + + + + + + + + 108 (default for XZCNF1-3; default for XZCNF0 if XCNF2 = 0) (default for XZCNF0 if XCNF2 = 1) 5.0 X-Bus Extension 5.4.4 (Continued) X-Bus IRQ Configuration Register (XIRQC) This register defines the functionality of the XIRQ signal. Power Well: VSB Location: Offset 04h Type: R/W Bit 7 6 Name 5 4 Reserved Reset 0 0 0 2 1 0 IRQPOLINV IRQEN IRQPOL PWUREN 0 0 0 0 0 Bit 7-4 3 Description Reserved. 3 IRQPOLINV (IRQ Polarity Inversion). This bit controls the polarity of the IRQ signal sent through the IRQ Serializer (see Table 32). This bit is reset to `0'. 2 IRQEN (IRQ Enable). When this bit is set, it enables the interrupt. The bit is ignored when the IRQ is mapped to zero (see Section 3.2.3 on page 39). 0: Disabled (default) 1: Enabled 1 IRQPOL (IRQ Polarity). This bit specifies the active level of the incoming IRQ signal. 0: Active low (default) 1: Active high 0 PWUREN (Power-Up Request Enable). When this bit is set, an XIRQ event is routed to the Modules IRQ Wake-Up Event (bit MOD_IRQ_STS in the GPE1_STS_3 register; see Section 9.4.11 on page 210). 0: Disabled (default) 1: Enabled Table 32. Serial IRQ vs. XIRQ Polarity IRQPOLINV IRQPOL 0 0 XIRQ 0 1 XIRQ 1 0 XIRQ 1 1 XIRQ 109 Serial IRQ www.national.com 5.0 X-Bus Extension (Continued) Bit Name 0 1 Power-Up IRQ Request Polarity Enable 2 IRQ Enable 3 IRQ Polarity Inversion 0 0 IRQ Serializer 1 1 XIRQ Modules IRQ Wake-Up Event IRQ from Legacy Modules Figure 28. Functional Illustration of X-Bus IRQ Configuration Register 5.4.5 X-Bus Indirect Memory Address Register 0 (XIMA0) This register holds addresses 7-0 for indirect read or write transactions to memory or I/O. Power Well: VSB Location: Offset 08h Type: R/W Bit 7 6 Name 5 0 0 0 Bit 5.4.6 3 2 1 0 0 0 1 0 0 0 X-Bus Indirect Memory or I/O Address 7-0 Reset 7-0 4 0 0 0 Description X-Bus Indirect Memory or I/O Address 7-0 X-Bus Indirect Memory Address Register 1 (XIMA1) This register holds addresses 15-8 for indirect read or write transactions to memory or I/O. Power Well: VSB Location: Offset 09h Type: R/W Bit 7 6 Name 5 3 2 X-Bus Indirect Memory or I/O Address 15-8 Reset 0 0 0 Bit 7-0 4 0 Description X-Bus Indirect Memory or I/O Address 15-8 www.national.com 110 0 0 5.0 X-Bus Extension 5.4.7 (Continued) X-Bus Indirect Memory Address Register 2 (XIMA2) This register holds addresses 23-16 for indirect read or write transactions to the memory. Power Well: VSB Location: Offset 0Ah Type: R/W Bit 7 6 Name 5 0 0 0 Bit 5.4.8 3 2 1 0 0 0 1 0 0 0 0 2 1 0 0 0 X-Bus Indirect Memory Address 23-16 Reset 7-0 4 0 0 0 Description X-Bus Indirect Memory Address 23-16 X-Bus Indirect Memory Address Register 3 (XIMA3) This register holds addresses 31-24 for indirect read or write transactions to the memory. Power Well: VSB Location: Offset 0Bh Type: R/W Bit 7 6 Name 5 0 0 0 Bit 5.4.9 3 2 X-Bus Indirect Memory Address 31-24 Reset 7-0 4 0 0 Description X-Bus Indirect Memory Address 31-24. X-Bus Indirect Memory Data Register (XIMD) This register holds data bits 7-0 for indirect read or write transactions to memory or I/O. Power Well: VSB Location: Offset 0Ch Type: R/W Bit 7 6 Name Reset 5 3 X-Bus Indirect Memory or I/O Data 7-0 0 0 0 Bit 7-0 4 0 0 0 Description X-Bus Indirect Memory or I/O Data 7-0. 111 www.national.com 5.0 X-Bus Extension (Continued) 5.4.10 X-Bus Select Mode Register (XZM0 to XZM3) These registers control the operation mode of chip select XCSn, where n is from 0 to 3. Power Well: VSB Location: Offset 0Fh (XZM0) Location: Offset 10h (XZM1) Location: Offset 11h (XZM2) Location: Offset 12h (XZM3) Type: Varies per bit Bit 7 6 5 4 Name LOCKXSCF WRSTAT SMIWREN XCSPOL Reset 0 0 0 0 Bit Type 3 2 XCSTIM 0 0 1 0 TRANSMD TRANSPD 0 0 Description 7 R/W1S LOCKXSCF (X-Bus Select Configuration Lock). Locks the configuration registers of the respective XCSn signal (both XZCNFn register and XZMn register) by disabling writing to all their bits (including to itself). An exception to this is the WRSTAT bit of the XZMn register. In addition, it locks the bits in the XBCNF register. Once set, this bit can be cleared either by the VDD Power-Up reset (or Hardware reset) or by the VSB Power-Up reset, according to the VSBLOCK bit in the ACBLKCTL register (see Section 6.3.4 on page 127). In addition, this bit is cleared by setting the UNLOCKX bit in the ACBLKCTL register (PC87417). 0: Lock Disabled (default) 1: Lock Enabled, protecting the configuration for this chip select 6 R/W1C WRSTAT (Write Status). This bit is set if a write to the chip select occurred. Writing 1 to this bit clears it to 0. WRSTAT is not locked by the LOCKXSCK bit. 0: No write detected (default) 1: Write to the chip select detected 5 R/W or SMIWREN (SMI-on-Write Enable). Enables the generation of an SMI, if the WRSTAT bit is set by the RO occurrence of a write to the chip select. 0: SMI Disabled (default) 1: SMI Enabled 4 R/W or XCSPOL (XCS Polarity Control). Selects the polarity of the XCSn signal. RO 0: Active low - idle = 1, select = 0 (default) 1: Active high - idle = 0, select = 1 3-2 R/W or XCSTIM (XCS Timing Control). Selects the timing of the XCSn signal during read and write RO transactions in mode 0. If TRANSMD bit is set to mode 1, the value of these bits is ignored and they are treated as `00'. Bits 3 2 00 01 10 11 1 Function Normal XCSn timing Normal XCSn timing Normal XCSn timing XRD_XEN timing for for both read and write cycles (default) during write cycles; XRD_XEN timing for XCSn during read cycles during read cycles; XWR_XRW timing for XCSn during write cycles XCSn during read cycles; XWR_XRW timing for XCSn during write cycles R/W or TRANSMD (X-Bus Transaction Mode). Selects the X-Bus transaction mode pertaining to the behavior RO of the XWR_XRW and XRD_XEN signals during a transaction. 0: Mode 0 - This is an ISA-like mode. When accessing the XCSn, XWR_XRW functions as an active low write signal and XRD_XEN functions as an active low read signal (default) 1: Mode 1 - In this mode, when accessing the XCSn, XWR_XRW functions as a read/write signal (high for a read transaction and low for a write transaction) and XRD_XEN functions as an active high enable signal www.national.com 112 5.0 X-Bus Extension Bit 0 (Continued) Type Description R/W or TRANSPD (X-Bus Transaction Speed). When set to 1, removes the additional cycles from mode 0 RO read and write transactions. In this situation, the setting of WAITSEN bit in the XZCNF0 to XZCNF3 registers is ignored (wait states are disabled). 0: Sixteen additional CLK cycles (apart from the programmed number of wait states) are inserted into mode 0 read and write transactions when accessing the XCSn (default) 1: No CLK cycles are inserted 5.4.11 Host Access Protect Register (HAP0 to HAP1) HAP0 and HAP1 registers hold the read/write protection and lock control bits for access control to XCS0 and XCS1, respectively. Each register defines the access rights for a group of 16 blocks of the related chip select (see Section 5.3 on page 104 for more information on how to define these blocks). Each block is protected by three bits, which are accessed through the block number written into the Host Access Protection Index field. The lock bit for each block is cleared either by reset or by writing a `0' through the ACCESS.bus (PC87417). When a lock bit is cleared, the related write-protect flag is set and the read-protect flag is cleared. Power Well: VSB Location: Offset 13h and 14h Type: Varies per bit Bit 7 6 Name 5 4 HAPINDX Reset 0 0 0 0 3 2 1 0 INDXWR LOCKXHP HWRP HRDP 0 0 1 0 Bit Type Description 7-4 R/W HAPINDX (Host Access Protection Index). Holds the index for the block number to be accessed by the other fields in this register. All blocks are 16 KByte up to 1 MByte in size (see Section 5.3 on page 104). 0000b - 1111b - index for block numbers of 0-15, respectively (0000b = default). 3 WO INDXWR (Index Write). Indicates an index write transaction for which the value of bits 2-0 are ignored (not written). This bit always returns `0' when read. 0: Index and Data write transaction (writes bits 2-0 according to the newly written index); (default) 1: Index update write transaction (bits 2-0 are not updated by this write) 2 R/W1S LOCKXHP (Lock Host Protection). When set to `1' through the LPC bus, this bit locks itself and the two HWRP and HRDP protection bits by disabling writing to them. The block number these three bits relate to is pointed to by the Index field. Once set, this bit can be cleared either by the VDD Power-Up reset (or Hardware reset) or by the VSB Power-Up reset, according to the VSBLOCK bit in the ACBLKCTL register (see Section 6.3.4 on page 127). In addition, this bit is cleared by setting the UNLOCKX bit in the ACBLKCTL register (PC87417). This bit may be set or reset through the ACCESS.bus (PC87417), regardless of its value (it is not selflocking). 0: Changes to protection bits (2-0) for this block are enabled (default) 1: Protection bits (2-0) for this block are locked and their values cannot be changed 1 R/W or HWRP (Host Write Protection). This bit prevents writes to a block, thus preventing programming or RO erasing of the flash memory connected to the XCSn. The block number affected by this field is the one pointed to by the Index field. 0: Host writes to this block are allowed 1: Host writes to this block are inhibited (default) 0 R/W or HRDP (Host Read Protection). This bit prevents reads from a block, thus protecting the contents of the RO flash memory connected to the XCSn. The block number affected by this field is the one pointed to by the Index field. 0: Host reads from this block are allowed (default) 1: Host reads from this block are inhibited 113 www.national.com 5.0 X-Bus Extension (Continued) 5.5 USAGE HINTS 1. Bear in mind the following system design hints for asynchronous X-Bus use: -- The chip-select signal must be used as a qualifier with the address when partial address decoding is in use for multiple device access control. -- In read cycles, the system may drive the data until the read signal XRD_XEN is de-asserted to guarantee the proper PC8741x sampling. -- In write cycles, use either the falling or rising edge of the write control signal (XWR_XRW) to latch the data in the device. 2. Address multiplexing on XD7-0 and strobe signals XSTB2-0 are designed for glueless interface with off-chip latch components (see the example in Figure 29). XD7-0 D7-0 XSTB2 PC8741x XSTB1 XSTB0 Latch (74HC373*) A27-20 Latch (74HC373*) A19-12 Latch (74HC373*) A11-4 XA3-0 A3-0 * - For mode 0, mode 0 fast, and mode 1, use 74HC373 - For mode 0 turbo, use 74VHC373 - For 5V-powered X-Bus devices, use 74HCT/VHCT373, which is also powered by the 5V supply. Figure 29. Latched Mode X-Bus Transaction External Logic www.national.com 114 5.0 X-Bus Extension (Continued) 5.6 X-BUS EXTENSION REGISTER BITMAP Register Bits Offset Mnemonic 7 6 5 4 00h XBCNF TBXCS3 TBXCS2 TBXCS1 TBXCS0 01h XZCNF0 XRDYEN WAITSEN INDIRMEN ZSELMAP 02h XZCNF1 XRDYEN WAITSEN INDIRMEN ZSELMAP 04h XIRQC 08h XIMA0 X-Bus Indirect Memory Address 7-0 09h XIMA1 X-Bus Indirect Memory Address 15-8 0Ah XIMA2 X-Bus Indirect Memory Address 23-16 0Bh XIMA3 X-Bus Indirect Memory Address 31-24 0Ch XIMD X-Bus Indirect Memory or I/O Data 7-0 0Dh XZCNF2 XRDYEN WAITSEN INDIRMEN ZSELMAP 0Eh XZCNF3 XRDYEN WAITSEN INDIRMEN ZSELMAP 0Fh XZM0 LOCKXSCF WRSTAT SMIWREN XCSPOL XCSTIM TRANSMD TRANSPD 10h XZM1 LOCKXSCF WRSTAT SMIWREN XCSPOL XCSTIM TRANSMD TRANSPD 11h XZM2 LOCKXSCF WRSTAT SMIWREN XCSPOL XCSTIM TRANSMD TRANSPD 12h XZM3 LOCKXSCF WRSTAT SMIWREN XCSPOL XCSTIM TRANSMD TRANSPD 13h HAP0 HAPINDX INDXWR LOCKXHP HWRP HRDP 14h HAP1 HAPINDX INDXWR LOCKXHP HWRP HRDP Other Reserved 3 2 1 Reserved IRQPOLINV IRQEN 0 LADEN IRQPOL PWUREN Reserved for National use 115 www.national.com 6.0 ACCESS.bus Interface This section is relevant only for the PC87413 and PC87417. In the PC87414 and PC87416, all ACCESS.bus Interface bits and signals that influence other modules are at their default value. The ACCESS.bus Interface is a two-wire synchronous serial interface compatible with the ACCESS.bus (Specification Rev. 3.0 Sep. 1995) and with Intel's SMBus (Specification Rev 1.1 Dec. 11, 1998). The ACCESS.bus Interface acts as a slave device controlled by a bus master. The ACCESS.bus Interface uses proprietary commands for AdvancedI/O access, compatible with the Physical, Data Link and Transport layers defined by the above specifications. This chapter describes the ACCESS.bus Interface functional block. 6.1 OVERVIEW The ACCESS.bus protocol uses a two-wire interface for bi-directional communication between the devices connected to the bus. The two interface lines are the Serial Data Line (ACBDAT) and the Serial Clock Line (ACBCLK). These open-drain lines must be connected to a positive supply via an internal or an external pull-up resistor and remain high when the bus is idle. Each device connected to the bus has a unique address and can operate as a transmitter or a receiver (though some peripherals are only receivers). During data transactions, the master device initiates the transaction with an attached peripheral, generates the clock signal and terminates the transaction. When the master sends a slave address or data, the peripheral behaves as a receiver. When the slave responds and sends data to the master, the peripheral behaves as a transmitter. 6.2 FUNCTIONAL DESCRIPTION 6.2.1 Bus Signals ACBDAT and ACBCLK Signals The ACBDAT and ACBCLK are open-drain signals. The device permits the user to define whether to enable or disable the internal pull-up of these two signals (at reset, the internal pull-up is disabled). Clock Frequency The PC8741x device is a slave device that synchronizes to the clock frequency of the ACCESS.bus clock. The maximum clock frequency is 100 kHz and the minimum is 10 kHz (limited by the 50 sec maximum high time required by the standards to detect a Bus Idle condition). However, since the PC8741x device is a slave device, the minimum clock frequency limitation is ignored. The clock low period may be extended by stall periods initiated by the ACCESS.bus Interface (see Section 11.4.6 on page 245). 6.2.2 Data Transactions One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock (ACBCLK). Consequently, throughout the high period of the clock, the data must remain stable (see Figure 30). Any change in midtransaction on the ACBDAT line during the high period of the ACBCLK aborts the transaction and releases the ACBDAT signal (to high level), thus generating Negative Acknowledge (NACK) cycles (see Section 6.2.4 on page 117). In addition, the PC8741x device sets the BUSERR bit in the ACBCST register (see Section 6.3.2 on page 126). Data must be driven onto the bus only during the low ACBCLK period. This protocol permits a single data line to transfer both command/control information and data, using the synchronous serial clock. During each clock cycle, while the slave handles the received data or prepares the data to be sent, it can stall the master. The slave can do this for each bit transferred or on a byte boundary by holding ACBCLK low to extend the clock-low period. Typically, slaves extend the first clock cycle of a transfer if a byte written has not yet been stored or if the byte to be read is not yet ready. Some microcontroller-based masters with limited hardware support for ACCESS.bus extend the access after each bit, thus allowing the software to handle the bit. www.national.com 116 6.0 ACCESS.bus Interface (Continued) Each data transaction is composed of a Start Condition, a number of byte transfers (defined by the protocol) and a Stop Condition to terminate the transaction. Each byte (eight bits) is transferred with the most significant bit first. After each byte, an Acknowledge signal must follow. The following sections provide further details of this process. ACBDAT ACBCLK Data Line Stable: Data Valid Change of Data Allowed Figure 30. Data Bit Transfer 6.2.3 Start and Stop Conditions The ACCESS.bus master generates Start and Stop Conditions (control codes). After a Start Condition is generated, the bus remains busy until after a Stop Condition is generated. A high-to-low transition of the data line (ACBDAT) while the clock (ACBCLK) is high indicates a Start Condition. A low-to-high transition of the ACBDAT line while the ACBCLK is high indicates a Stop Condition (Figure 31). A transaction begins with a Start Condition and ends with a Stop Condition. However, a Restart Condition can be generated in the middle of a transaction (without the need for a Stop Condition) in order to change the direction of data transfer (from address/data write to data read). Before a Start condition, any changes of the ACBDAT line outside the high period of the ACBCLK are ignored. A Stop condition encountered in mid-transaction on the ACBDAT line aborts the transaction. The PC8741x device releases the ACBDAT signal (to high level), thus generating Negative Acknowledge (NACK) cycles (see Section 6.2.4). In addition, the PC8741x device sets the BUSERR bit in the ACBCST register (see Section 6.3.2 on page 126). ACBDAT ACBCLK S or R P Start or Restart Condition Stop Condition Figure 31. Start, Restart and Stop Conditions 6.2.4 Acknowledge (ACK) Cycle The ACK cycle involves two signals: the ACK clock pulse, sent by the master after each byte transferred, and the ACK data signal, sent by the receiving device (see Figure 32). The master generates the ACK clock pulse on the ninth clock pulse of the byte transfer. The transmitter (master or slave) releases the ACBDAT line (allows it to go high) to allow the receiver to send the ACK signal. The receiver must pull down the ACBDAT line during the ACK clock pulse, signalling that it correctly received the previous data byte and is ready to receive the next byte. If the receiver does not pull the ACBDAT line (leaves it high), the transmitter identifies it as a NACK condition (see Section 6.2.5). Figure 33 illustrates the ACK cycle. 117 www.national.com 6.0 ACCESS.bus Interface (Continued) Acknowledge Signal From Receiver ACBDAT MSB ACBCLK 1 S LSB 2 3-6 7 8 1 9 ACK 2 3-8 9 ACK Start Condition P Stop Condition Clock Line Held Low by Receiver While Interrupt is Serviced Byte Complete Interrupt Within Receiver Figure 32. ACCESS.bus Data Transaction with Acknowledge Data Output by Transmitter Transmitter Stays Off Bus During Acknowledge Clock Data Output by Receiver Acknowledge Signal From Receiver ACBCLK S 1 2 3-6 7 8 9 Start Condition Figure 33. ACCESS.bus Acknowledge Cycle 6.2.5 Acknowledge after Every Byte Rule According to this rule, the master generates an acknowledge clock pulse after each byte transfer and the receiver (master or slave) sends an acknowledge signal after every byte received. There are two exceptions to this rule: * When the master is the receiver, it must indicate to the slave transmitter the end of the expected data by not acknowledging (NACK) the last byte clocked out of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master), but the ACBDAT line is not pulled down. * When a problem has occurred in the slave receiver, it sends a NACK to indicate that it did not accept the previous data byte or cannot accept additional data bytes. The NACK indicates an error in data reception (by slave or master) and a request to repeat the ACCESS.bus transaction. 6.2.6 Addressing Transfer Formats Each device on the bus has a unique address. The PC8741x device starts a slave address set-up process if one of the following occurs: * A VSB Power-Up reset is activated by VSB going up: in this case, the ACBSA strap value is also sampled (see Section 2.2.2 on page 33). * A broadcast transaction to the General Call address with a "Reset and write programmable part of slave address by hardware" command is received over the ACCESS.bus (see below). During the slave address set-up process, the PC8741x device performs the following actions in the order listed: 1. Checks the value of the ACBSADD field in the ACBCF register (see Section 3.7.11 on page 56); if the value of the bits is valid (not zero), the value is adopted and the other two actions are ignored. 2. Checks the value of the ACBSA strap sampled at the VSB Power-Up reset. 3. Adopts one of the two fixed values (see Section 1.4.11 on page 28) for its slave address, according to the ACBSA value. www.national.com 118 6.0 ACCESS.bus Interface (Continued) Before any data is transmitted, the master transmits the address of the target slave. The slave must send an acknowledge signal on the ACBDAT line once it recognizes its address. The address consists of the first seven bits after a Start Condition. The direction of the data transfer (R/W) depends on the eighth bit (which is sent after the address). When the address is sent, each device in the system compares this address with its own. If there is a match, the device considers itself addressed and sends an acknowledge signal. Depending on the state of the R/W bit (1=read, 0=write), the device acts either as a transmitter or a receiver. The combination of the 7-bit address and the R/W bit is used in this document to define the slave address as a write address (even) and a read address (odd) pair. A low-to-high transition during a ACBCLK high period indicates the Stop Condition and ends the transaction of ACBDAT (see Figure 34). The ACCESS.bus protocol allows a General Call address to be sent to all slaves connected to the bus. The first byte sent specifies the General Call address (00h) and the second byte specifies the meaning of the general call ("Reset and write programmable part of slave address by hardware"--06h). When a 00h-followed-by-a-06h transaction is detected, the PC8741x device resets the ACCESS.bus Interface logic and the data registers (except for the configuration registers) and reloads the default slave address. ACBDAT ACBCLK 1-7 S 8 9 Start Slave Condition Address R/W ACK 1-7 Data 8 9 1-7 ACK Data 9 8 ACK P Stop Condition Figure 34. A Complete ACCESS.bus Data Transaction 6.2.7 Arbitration on the Bus Multiple master devices on the bus require arbitration between their conflicting bus access demands. Control of the bus is initially determined according to address bits and clock cycle. If more than one master try to address the same slave, data comparisons determine the outcome of this arbitration. A master device immediately aborts a transaction if the value sampled on the ACBDAT line differs from the value internally driven by the device. (An exception to this rule is ACBDAT while the master is receiving data. The lines may be held low by the slave without causing an abort.) The ACBCLK signal is monitored by the master for clock synchronization and to allow the slave to stall the bus. The actual clock period is set either by the master with the longest clock period or by the slave stall period. The maximum allowed "cumulative clock low extend time" of a slave device (per transaction) is defined in Section 11.4.6. The clock high period is determined by the master with the shortest clock high period; however, it must not be longer than the value defined in Section 11.4.6. When an abort occurs during the address transmission, the master that identifies the conflict must release the bus, switch to Slave mode and continue to sample ACBDAT to check if it is being addressed by the winning master on the bus. If the PC8741x device detects that ACBCLK is held low longer than the maximum allowed time, it aborts the current transaction and sets the LOWCKTO bit in the ACBCST register (see Section 6.3.2 on page 126). 6.2.8 Packet Error Check (PEC) The Packet Error Checking mechanism complies with Revision 1.1 of the SMBus Specification. It consists of appending an error check byte to the end of each transaction (before the Stop condition). The PC8741x devices are capable of communicating with all masters, whether or not they implement the PEC. Master PEC Assessment After reset, a master supporting the PEC feature performs the following sequence: 1. Read (without PEC) the ACBCST register of the PC8741x slave device. 2. Check the PECAVAIL bit (bit 0 of the register), which indicates the PEC slave support (for the PC8741x devices, this bit is always `1'). 3. Read (with PEC) the ACBCST register and check for its correctness. 4. Register the PC8741x slave device as PEC compliant. 119 www.national.com 6.0 ACCESS.bus Interface (Continued) All subsequent transactions between the master and the PEC-compliant slave include the PEC byte. During write transactions, the master provides the PEC of the transmitted data. During read transactions, the master checks the received data using the PEC supplied by the slave. In both cases, the master supplies the number of ACBCLK cycles required for PEC support. If the master does not supply these clock cycles, the PC8741x device considers that PEC is not supported during the current transaction (i.e., there is no error condition). Slave PEC Support The PC8741x device provides PEC support when the master also requires it. However, the PC8741x device always calculates the PEC value of the incoming or outgoing data. After the last bytes of a write transaction, if the master supplies additional ACBCLK cycles, the PC8741x device receives the PEC byte and compare it with the calculated PEC value. Otherwise, it just ignores the calculated PEC. If the comparison fails, the PC8741x device generates a NACK bit at the end of the PEC byte and sets the PECERR bit in the ACBCST register (see Section 6.3.2 on page 126) but does not execute the write transaction. At the end of the last byte of a read transaction, if the master generates an ACK for the last byte (instead of a NACK), the PC8741x device sends the calculated PEC value during the following byte. Otherwise, it discards the calculated PEC. PEC Implementation The PEC is an 8-bit cyclic redundancy check (CRC-8) value attached at the end of an ACCESS.bus transaction as the last byte transmitted before the Stop condition. The PC8741x device calculates the PEC value by hardware (bit-by-bit), using all the bytes in the transaction (except the PEC byte itself). PEC calculation does not include Start, Restart, Stop, ACK or NACK, which are bus control bits and not data bits. The PEC value is generated using the polynomial C(x) = x8 + x2 + x1 + 1, which is specified in Intel's SMBus Specification (Rev 1.1 Dec. 11, 1998). During a read transaction, the PEC value is generated by the PC8741x device and checked by the master; during a write transaction, it is generated by the master and checked by the slave. 6.2.9 ACCESS.bus Protocol The protocol is based on five basic byte types: Save Address, Command, Offset Address, Data and PEC; these are described below. An error is flagged in the following cases: If the number of bytes in the transaction differs from the number of bytes required by the Command byte. For Command byte type, if the reserved bit is not zero. When an error is flagged, a NACK is generated at the end of the current byte (the current transaction is aborted) and the ILGCOM bit in the ACBCST register is set (see Section 6.3.2 on page 126). Slave Address Byte Type Bit 7 Name 6 5 4 3 2 1 SLAVEAD 0 ACBRW Bit Description 7-1 SLAVEAD (Slave Address). This seven-bit field indicates the slave address of the accessed device. If its value is the same as the one selected during the set-up process (see Section 6.2.6), the PC8741x device responds to the present transaction. 0 ACBRW (ACCESS.bus Read/Write Mode). Selects the transfer direction for the current transaction. 0: Write ACCESS.bus transaction (from master to slave) - equivalent to an even 8-bit slave address 1: Read ACCESS.bus transaction (from slave to master) - equivalent to an odd 8-bit slave address www.national.com 120 6.0 ACCESS.bus Interface (Continued) Command Byte Type This type has two variations, according to the value of the INEX bit. Bit Name 7 6 INEX=0 RDWR 7 6 5 INEX=1 RDWR Reserved Bit Name Bit 5 4 3 2 1 0 2 1 0 LOGDEV 4 3 XBCSN XA26-XA24 Description 7 INEX (Internal/External Access). Selects the access type for the current transaction. 0: Internal access - to modules within the PC8741x device 1: External access - to devices connected to the X-Bus (PC87417) 6 RDWR (Read/Write Access). Selects the access direction for the current transaction. 0: Write access - data sent by the master is written into the selected address 1: Read access - data read from the selected address is stored in the Read Buffer 5-0 5 4-3 LOGDEV (Logical Device Number). This field indicates the Logical Device Number (LDN) of the accessed internal functional block. Table 33 defines the LDN assignment for each functional block of the PC8741x device; other table values are not allowed. These LDNs are equivalent but not identical to those assigned by the plugand-play configuration. Only those Logical Devices that can be accessed both through the ACCESS.bus and the LPC bus are assigned the same LDN. Reserved. XBCSN (X-Bus Chip-Select Number). These two bits select one of the four X-Bus chip-selects to be accessed during the current transaction (PC87417). Bits 1 0 00 01 10 11 2-0 Chip-Select XCS0 XCS1 XCS2 XCS3 XA26-XA24 (X-Bus Offset Address). These bits set the value of the X-Bus address lines XA26-XA24, which are used as offset for the X-Bus access during the current transaction (PC87417). The XA27 address line is set to `0'. 121 www.national.com 6.0 ACCESS.bus Interface (Continued) Table 33. Logical Device Number (LDN) Assignment for ACCESS.bus LDN Functional Block 00h Floppy Disk Controller (FDC) 01h Parallel Port (PP) 02h Serial Port 2 (SP2) 03h Serial Port 1 (SP1) 04h System Wake-Up Control (SWC) 06h Keyboard and Mouse Controller (KBC)1 07h General-Purpose I/O (GPIO) Ports 0Fh X-Bus Extension (PC87417) 10h Real Time Clock (RTC)2 30h PM1b_EVT_BLK (SWC-ACPI) 31h PM1b_CNT_BLK (SWC-ACPI) 32h GPE1_BLK (SWC-ACPI) 3Eh Device Configuration (CONFIG)3,4 3Fh ACCESS.bus Interface (ACB)3 1. This Logical Device has two chip selects for the Index/Data registers, each pointed to by a different Base Address in the configuration. The A2 bit of the Offset Address Byte differentiates between the two chip selects: A2 = 0: the Index/Data registers pointed to by the Base Address at 60h and 61h A2 = 1: the Index/Data registers pointed to by the Base Address at 62h and 63h. 2. This Logical Device has two chip selects for the Index/Data registers, each pointed to by a different Base Address in the configuration. The A1 bit of the Offset Address Byte differentiates between the two chip selects (see Note 1 above). 3. This Logical Device is accessible only through the ACCESS.bus. 4. Access to this Logical Device is through the Index register located at offset 00h and data register located at offset 01h. Offset Address Byte Type This is an 8-bit value representing either of the following: * * Internal access - the offset address from the base of the functional block. External access - eight bits of the offset address from the base of the X-Bus chip-select (PC87417). The offset address value must be within the defined range for the selected Logical Device or X-Bus chip-select. Offset values outside this range are reserved. Data Byte Type This is an 8-bit value representing either the written or read data. PEC Byte Type This is an 8-bit value representing the 8-bit cyclic redundancy check of all the transferred bytes (see Section 6.2.8 on page 119). www.national.com 122 6.0 ACCESS.bus Interface (Continued) Reset Slave Transaction This is a broadcast transaction to the General Call address (00h) that resets the ACCESS.bus Interface logic and the data registers (the configuration registers are not affected) and reloads the current slave address by starting a slave address setup process (see Section 6.2.6 on page 118). PEC is not supported for this transaction. Since this is a broadcast transaction, all slave devices connected to the ACCESS.bus respond to it. S General Call Address A Reset & Reload Slave Address A P (00h) (06h) S = Start condition P = Stop condition A = ACK by slave Write Internal Transaction This transaction writes a byte of data to a register of a functional block of the PC8741x device. The functional block is selected by the Logical Device Number for the ACCESS.bus (see Table 33 on page 122). The specific register is accessed using the 8-bit offset address (from the base of the functional block). If PEC is supported, the master sends a PEC byte at the end of the transaction. If the selected Logical Device is not powered (the VDD supply is off), the PC8741x device generates a NACK bit at the end of the Command byte, sets the OFFLDN bit in the ACBCST register (see Section 6.3.2 on page 126) and aborts the transaction. S Slave Address A Command A Offset Address A (S.A, Write) (Int, Write, LDN) (OA7-OA0) S = Start condition P = Stop condition Data A A PEC A P = ACK by slave Read Internal Transaction This transaction reads a byte of data from a register of a functional block of the PC8741x device. The functional block is selected by the Logical Device Number for the ACCESS.bus (see Table 33 on page 122). The specific register is accessed using the 8-bit offset address (from the base of the functional block). This transaction is executed in two phases: The master executes an ACCESS.bus write transaction, which conveys the Command (Read) and Offset Address information to the PC8741x device. During this phase, the data is read from the specific register into the Read Buffer. This phase has no Stop Condition. Following a Restart condition, the master executes an ACCESS.bus read transaction. During this phase the data is transferred from the Read Buffer to the master. At the end of this phase, the PC8741x device returns a PEC byte if required by the master. The calculated PEC value is based on the bytes transferred during both phases. If the selected Logical Device is not powered (the VDD supply is off), the PC8741x device generates a NACK bit at the end of the Command byte, sets the OFFLDN bit in the ACBCST register (see Section 6.3.2 on page 126) and aborts the transaction. S Slave Address A Command A Offset Address A (S.A, Write) (Int, Read, LDN) (OA7-OA0) R Slave Address A Data A PEC N P (S.A, Read) S = Start condition R = Restart condition N = NACK by master P = Stop condition A = ACK by master A = ACK by slave 123 www.national.com 6.0 ACCESS.bus Interface (Continued) Write External Transaction (PC87417) This transaction writes a byte of data to a memory device or to an I/O port connected to the X-Bus. The chip-select for the device is selected by the XBCSN field in the command byte. The specific memory location or I/O port register is accessed using a 27-bit offset address (from the base of the chip-select). The 27-bit offset address is broken into four bytes: XA26XA24 in the Command byte and XA23-XA16, XA15-XA8 and XA7-XA0 in three successive Offset Address bytes. If PEC is supported, the master sends a PEC byte at the end of the transaction. S Slave Address A (S.A, Write) Command A Offset Address A Offset Address A Offset Address A (Ext, Write, XA26-24) (XA23-XA16) (XA15-XA8) (XA7-XA0) Data S = Start condition P = Stop condition A A PEC A P = ACK by slave Read External Transaction (PC87417) This transaction reads a byte of data from a memory device or from an I/O port connected to the X-Bus. The chip-select for the device is selected by the XBCSN field in the command byte. The specific memory location or I/O port register is accessed using a 27-bit offset address (from the base of the chip-select). The 27-bit offset address is broken in four bytes: XA26-XA24 in the Command byte and XA23-XA16, XA15-XA8 and XA7-XA0 in three successive Offset Address bytes. This transaction is executed in two phases: The master executes an ACCESS.bus write transaction, which conveys the Command (Read), chip-select and Offset Address information to the PC8741x device. During this phase, the data is read from the specific memory location or I/O port register into the Read Buffer. This phase has no Stop Condition. Following a Restart condition, the master executes an ACCESS.bus read transaction. During this phase the data is transferred from the Read Buffer to the master. At the end of this phase, the PC8741x device returns a PEC byte if required by the master. The calculated PEC value is based on the bytes transferred during both phases. S Slave Address A (S.A, Write) Command A Offset Address A Offset Address A Offset Address A (Ext, Read, XA26-24) (XA23-XA16) (XA15-XA8) R Slave Address A Data (XA7-XA0) A PEC N P (S.A, Read) S = Start condition R = Restart condition N = NACK by master P = Stop condition A = ACK by master A = ACK by slave 6.2.10 Transaction Execution The ACCESS.bus uses the internal bus of the PC8741x device to access the internal modules (except its own registers) or to bridge transactions to the X-Bus (see "Block Diagram" on page 1). Since the same internal bus is also used independently by the LPC bus, the duration of the ACCESS.bus use of the internal bus is held to a minimum. At the highest ACBCLK frequency (100 KHz), the longest ACCESS.bus transaction (Read External) takes at least 750 s to complete. In order not to stall the internal bus for such a long time, the ACCESS.bus transactions are executed as follows: Write - data is written through the internal bus at the end of the transaction after the Stop condition is detected; the next ACCESS.bus transaction can start immediately while the present data is written through the internal bus. Read - data is read through the internal bus during the second part of the transaction (beginning with Restart), after the Slave Address is received and before it is acknowledged (ACK); while the data is read through the internal bus, the ACBCLK signal is held low, indicating to the ACCESS.bus master that PC8741x device is not ready (see Section 6.2.7 on page 119). The duration of the ACCESS.bus transaction through the internal bus is longer for external access (X-Bus devices PC87417) than for internal access (internal modules of the PC8741x device). If wait states are configured for the module or X-Bus access, their duration must be added to the internal bus transaction time. When the XRDY signal is in use, its delay must also be accounted for. If an LPC transaction started before an ACCESS.bus transaction, the execution of the ACCESS.bus transaction through the internal bus is withheld until the end of the LPC transaction. www.national.com 124 6.0 ACCESS.bus Interface (Continued) 6.3 ACB REGISTERS (ON ACCESS.BUS ONLY) All these registers are accessible only through the ACCESS.bus. The following abbreviations are used to indicate the Register Type: R/W = Read/Write. R = Read from a specific register (write to the same address is to a different register). W = Write (see above). RO = Read Only. WO = Write Only. Reading from the bit returns 0. R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect. R/W1S = Read/Write 1 to Set. Writing 1 to a bit sets its value to 1. Writing 0 has no effect. 6.3.1 ACB Register Map (on ACCESS.bus Only) Offset Mnemonic Register Name Type Power Well Section 00h ACBCST ACCESS.bus Control/Status Varies per bit VSB 6.3.2 01h ACBCFG ACCESS.bus Configuration Varies per bit VSB 6.3.3 02h ACBLKCTL ACCESS.bus Lock Control Varies per bit VSB 6.3.4 03h ACBFDIS ACCESS.bus Fast Disable R/W VSB 6.3.5 04h ACBTRIS ACCESS.bus TRI-State R/W VSB 6.3.6 05h ACCLCF1 Access Lock Configuration 1 R/W VSB 6.3.7 06h ACCLCF2 Access Lock Configuration 2 R/W VSB 6.3.8 125 www.national.com 6.0 ACCESS.bus Interface 6.3.2 (Continued) ACCESS.bus Control/Status Register (ACBCST) This register controls the ACCESS.bus interface and holds the status of the last transactions. On reset, it is cleared (01h). Power Well: VSB Location: Offset 00h Type: Varies per bit Bit 7 6 5 4 Name OFFLDN ILGCOM PECERR BUSERR Reset 0 0 0 0 Bit 7 Type 3 2 LOWCKTO ACCLVIOL 0 0 1 0 VDDSTAT PECAVAIL 0 1 Description R/W1C OFFLDN (Accessed LDN Powered-off Flag). Indicates that the Logical Device accessed through the command byte (only for Internal Access mode, i.e., when INEX = 0) is powered-off (relevant for the Legacy functional blocks powered from the VDD plane). Writing `1' clears this bit; writing `0' is ignored. 0: Powered Logical Device accessed (default) 1: Unpowered Logical Device accessed 6 R/W1C ILGCOM (Illegal Command Flag). Indicates that an illegal command code or an incorrect number of address/data bytes was received or requested for transmission (by last byte NACK or Stop control). Writing `1' clears this bit; writing `0' is ignored. 0: Correct protocol (default) 1: Illegal command or number of bytes 5 R/W1C PECERR (PEC Error Flag). Indicates that a PEC error was detected in the write transaction bytes that were received from the master. This bit is not updated if the master does not send a PEC byte. Writing `1' clears this bit; writing `0' is ignored. 0: Correct PEC (default) 1: CRC of the received bytes differs from the received PEC 4 R/W1C BUSERR (Bus Error Flag). Indicates that an unexpected Start, Restart or Stop Condition was detected during a read or write transaction. Writing `1' clears this bit; writing `0' is ignored. 0: Correct transaction (default) 1: Illegal Start, Restart or Stop Condition 3 R/W1C LOWCKTO (Low Clock Timeout Flag). Indicates that the ACBCLK signal was detected low for longer than the maximum allowed "cumulative clock low extend time" during a transaction, as defined in Section 11.4.6. Writing `1' clears this bit; writing `0' is ignored. 0: Correct clock low timing (default) 1: Clock low timeout 2 R/W1C ACCLVIOL (Access Lock Violation Flag). Indicates that an LPC access to a functional module locked for sole use by ACCESS.bus was detected. Writing `1' clears this bit; writing `0' is ignored. 0: Correct LPC access (default) 1: LPC access to a locked functional module 1 RO VDDSTAT (VDD Power Status). Indicates the actual status of the VDD power supply to the PC8741x device. 0: VDD power OFF 1: VDD power ON 0 RO PECAVAIL (PEC Feature Available). Enables the master to detect the availability of the PEC implementation in the slave. 0: Peripheral does not support PEC 1: Peripheral supports PEC (default and fixed value for PC8741x devices) www.national.com 126 6.0 ACCESS.bus Interface 6.3.3 (Continued) ACCESS.bus Configuration Register (ACBCFG) This register controls the configuration of the ACCESS.bus Interface. On reset, it is cleared (00h). Power Well: VSB Location: Offset 01h Type: Varies per bit Bit 7 6 Name CSWRST Reserved Reset 0 0 Bit Type 7 R/W 6 4 3 ACCLMD 0 2 1 Reserved 0 0 0 0 ACTSTAT 0 0 Description CSWRST (Controller Software Reset). When set to `1', this bit triggers a Controller Software reset sequence (see Section 2.2.3 on page 34) and then returns to `0'. It always returns `0' when read. 0: Normal operation (default) 1: Enable the Controller Software Reset Reserved. 5-4 R/W ACCLMD (Locked Module Access Mode). These bits control the behavior of the LPC Interface whenever a locked module is accessed. Bits 1 0 00 01 10 11 3-1 Function Complete cycle and generate Error SYNC; read 00h; ignore write (default). Complete cycle; read 00h; ignore write. Ignore cycle (do not generate SYNC). - Locked X-Bus chip-select (XCS3-XCS0): Generate Long Wait SYNC for read and write until access lock is removed; then complete transaction normally. - Any other locked module: Complete cycle; read 00h; ignore write. Reserved. 0 6.3.4 5 R/W ACTSTAT (Module Activation Status Configuration). This bit configures the behavior of the Activation bit (for the Legacy modules) when read through the LPC bus (index 30 - see Section 3.2.3 on page 39). When this bit is set to `1' and a specific module is disabled by the bits in the ACBFDIS register (see Section 6.3.5 on page 129), or when the module is locked by the bits in the ACCLCF1 register (see Section 6.3.7 on page 131), the module Activation status that is read through the LPC returns a `0' value, ignoring the actual setting of the Activation bit. 0: Activation status reflects the value of the Activation bit (default) 1: Activation status reflects the value of the Activation bit, or returns `0' if either the module is locked, or disabled by the bits in the ACBFDIS register ACCESS.bus Lock Control Register (ACBLKCTL) This register controls the configuration lock of the PC8741x device. On reset, it is cleared (00h). Power Well: VSB Location: Offset 02h Type: Varies per bit Bit 7 Name VSBLOCK Reset 0 6 5 UNLOCKM UNLOCKG 0 0 4 3 2 1 0 UNLOCKF UNLOCKC UNLOCKX UNLOCKR UNLOCKS 0 0 0 0 0 127 www.national.com 6.0 ACCESS.bus Interface Bit 7 (Continued) Type Description R/W1S VSBLOCK (Configuration Lock Until VSB Reset). Controls the reset source of the following lock bits: LOCKMCF and LOCKGCF in the SIOCF1 register, LOCKFDS in the SIOCF6 register, LOCKCCF in the CLOCKCF register, LOCKCFP in all GPCFG1 registers (for each GPIO pin), LOCKIOMP in the XIOCNF register (PC87417), LOCKMMP in the XMEMCNF2 register (PC87417), all bits of the RLR register, LOCKXSCF in the XZM0-XZM3 registers (PC87417), LOCKXHP in the HAP0 and HAP1 registers (PC87417), LOCK_TMRRST in the PWTMRCTL register and LOCK_SLP_ENC in the SLP_ST_CFG register. When set to `1', this bit is cleared only by the VSB Power-Up reset. 0: Lock bits cleared by VDD Power-Up reset, by Hardware reset or by VSB Power-Up reset (default) 1: Lock bits cleared only by VSB Power-Up reset 6 R/W UNLOCKM (Unlock Multiplexing Configuration). When set to `1', this bit resets the LOCKMCF bit in the SIOCF1 register, ignoring the setting of the VSBLOCK bit. It always returns `0' when read. 0: Normal operation (default) 1: Reset the LOCKMCF bit 5 R/W UNLOCKG (Unlock GPIO Configuration). When set to `1', this bit resets the LOCKGCF bit in the SIOCF1 register and the LOCKCFP bit in all the GPCFG1 registers (for each GPIO pin), ignoring the setting of the VSBLOCK bit. It always returns `0' when read. 0: Normal operation (default) 1: Reset the LOCKGCF and all the LOCKCFP bits 4 R/W UNLOCKF (Unlock Fast Disable Configuration). When set to `1', this bit resets the LOCKFDS bit in the SIOCF6 register, ignoring the setting of the VSBLOCK bit. It always returns `0' when read. 0: Normal operation (default) 1: Reset the LOCKFDS bit 3 R/W UNLOCKC (Unlock Clock Configuration). When set to `1', this bit resets the LOCKCCF bit in the CLOCKCF register, ignoring the setting of the VSBLOCK bit. It always returns `0' when read. 0: Normal operation (default) 1: Reset the LOCKCCF bit 2 R/W UNLOCKX (Unlock X-Bus Configuration). When set to `1', this bit resets the LOCKIOMP bit in the XIOCNF register, the LOCKMMP bit in the XMEMCNF2 register, the LOCKXSCF bit in the XZM0-XZM3 registers and the LOCKXHP bit in the HAP0 and HAP1 registers, ignoring the setting of the VSBLOCK bit (PC87417). It always returns `0' when read. 0: Normal operation (default) 1: Reset the LOCKIOMP, LOCKMMP, LOCKXSCF and LOCKXHP bits 1 R/W UNLOCKR (Unlock RAM Lock Configuration). When set to `1', this bit resets all the bits of the RLR register (see Section 3.16.3 on page 87), ignoring the setting of the VSBLOCK bit. It always returns `0' when read. 0: Normal operation (default) 1: Reset all the bits of the RLR register 0 R/W UNLOCKS (Unlock SWC Configuration). When set to `1', this bit resets the LOCK_TMRRST bit in the PWTMRCTL register and the LOCK_SLP_ENC bit in the SLP_ST_CFG register, ignoring the setting of the VSBLOCK bit. It always returns `0' when read. 0: Normal operation (default) 1: Reset the LOCK_TMRRST and LOCK_SLP_ENC bits www.national.com 128 6.0 ACCESS.bus Interface 6.3.5 (Continued) ACCESS.bus Fast Disable Register (ACBFDIS) This register provides a fast way to disable one or more modules through the ACCESS.bus without having to access the Activate register of each module (see Section 3.2.3 on page 39). It is reset by hardware to 00h. Power Well: VSB Location: Offset 03h Type: R/W Bit 7 Name Reset 0 Bit 7-6 6 Reserved 0 5 4 3 2 1 0 KBDDIS MSDIS SER1DIS SER2DIS PARPDIS FDCDIS 0 0 0 0 0 0 Description Reserved. 5 KBDDIS (Keyboard Controller Disable). When set to 1, this bit forces the Keyboard Controller module (Logical Device 6) to be disabled (and its resources released) regardless of the actual setting of its Activation bit (index 30). 0: Enabled or Disabled, according to Activation bit (default) 1: Disabled 4 MSDIS (Mouse Controller Disable). When set to 1, this bit forces the Mouse Controller module (Logical Device 5) to be disabled (and its resources released) regardless of the actual setting of its Activation bit (index 30). 0: Enabled or Disabled, according to Activation bit (default) 1: Disabled 3 SER1DIS (Serial Port 1 Disable). When set to 1, this bit forces the Serial Port 1 module to be disabled (and its resources released) regardless of the actual setting of its Activation bit (index 30). 0: Enabled or Disabled, according to Activation bit (default) 1: Disabled 2 SER2DIS (Serial Port 2 Disable). When set to 1, this bit forces the Serial Port 2 module to be disabled (and its resources released) regardless of the actual setting of its Activation bit (index 30). 0: Enabled or Disabled, according to Activation bit (default) 1: Disabled 1 PARPDIS (Parallel Port Disable). When set to 1, this bit forces the Parallel Port module to be disabled (and its resources released) regardless of the actual setting of its Activation bit (index 30). 0: Enabled or Disabled, according to Activation bit (default) 1: Disabled 0 FDCDIS (Floppy Disk Controller Disable). When set to 1, this bit forces the Floppy Disk Controller module to be disabled (and its resources released) regardless of the actual setting of its Activation bit (index 30). 0: Enabled or Disabled, according to Activation bit (default) 1: Disabled 129 www.national.com 6.0 ACCESS.bus Interface 6.3.6 (Continued) ACCESS.bus TRI-STATE Register (ACBTRIS) This register provides a fast way to float the outputs of one or more modules through the ACCESS.bus without having to access their TRI-STATE Control bit in the Special Configuration register at index F0h. The module outputs enter TRI-STATE only when the module is disabled (see Section 6.3.5 on page 129). The register is reset by hardware to 00h. Power Well: VSB Location: Offset 04h Type: R/W Bit 7 Name 5 Reserved Reset 0 Bit 7-5 6 0 4 3 KBMSTRIS SER1TRIS 0 0 0 2 1 0 SER2TRIS PARPTRIS FDCTRIS 0 0 0 Description Reserved. 4 KBMSTRIS (Keyboard and Mouse Outputs TRI-STATE). When set to 1 and the module is disabled, this bit forces the outputs of the Keyboard and Mouse Controller to be in TRI-STATE regardless of bit 0 in the Keyboard Configuration register (see Section 3.13.3 on page 68). 0: Enabled or Disabled, according to bit 0 in the Keyboard Configuration register (default) 1: Outputs in TRI-STATE 3 SER1TRIS (Serial Port 1 Outputs TRI-STATE). When set to 1 and the module is disabled, this bit forces the outputs of the Serial Port 1 module to be in TRI-STATE regardless of bits 6 and 0 in the Serial Port 1 Configuration register (see Section 3.11.3 on page 65). 0: Enabled or Disabled, according to bits 6 and 0 in the Serial Port 1 Configuration register (default) 1: Outputs in TRI-STATE 2 SER2TRIS (Serial Port 2 Outputs TRI-STATE). When set to 1 and the module is disabled, this bit forces the outputs of the Serial Port 2 module to be in TRI-STATE regardless of bits 6 and 0 in the Serial Port 2 Configuration register (see Section 3.10.3 on page 63). 0: Enabled or Disabled, according to bits 6 and 0 in the Serial Port 2 Configuration register (default) 1: Outputs in TRI-STATE 1 PARPTRIS (Parallel Port Outputs TRI-STATE). When set to 1 and the module is disabled, this bit forces the outputs of the Parallel Port module to be in TRI-STATE regardless of bit 0 in the Parallel Port Configuration register (see Section 3.9.3 on page 61). 0: Enabled or Disabled, according to bit 0 in the Parallel Port Configuration register (default) 1: Outputs in TRI-STATE 0 FDCTRIS (Floppy Disk Controller Outputs TRI-STATE). When set to 1 and the module is disabled, this bit forces the outputs of the Floppy Disk Controller module to be in TRI-STATE regardless of bit 0 in the FDC Configuration register (see Section 3.8.3 on page 58). 0: Enabled or Disabled, according to bit 0 in the FDC Configuration register (default) 1: Outputs in TRI-STATE www.national.com 130 6.0 ACCESS.bus Interface 6.3.7 (Continued) Access Lock Configuration 1 Register (ACCLCF1) This register controls the locking of the device functional blocks to LPC bus access. On reset, it is cleared (00h). Power Well: VSB Location: Offset 05h Type: Bit R/W 7 Name CONFALOK Reset 0 Bit 7 6-5 6 5 Reserved 0 4 3 2 1 0 KBCALOK SER1ALOK SER2ALOK PARPALOK FDCALOK 0 0 0 0 0 0 Description CONFALOK (Configuration Access Lock). When set to 1, this bit disables LPC bus access to the Device Configuration module and locks the module for use by ACCESS.bus only. If the module is accessed through the LPC bus, it responds according to the setting of the ACCLMD field in the ACBCFG register (see Section 6.3.3 on page 127); in addition, the ACCLVIOL bit in ACBCST is set (see Section 6.3.2 on page 126). 0: Module opened for LPC access (default) 1: Module locked for LPC access and opened for use by ACCESS.bus only Reserved. 4 KBCALOK (Keyboard/Mouse Controller Access Lock). When set to 1, this bit disables LPC bus access to the Keyboard/Mouse Controller module and locks the module for use by ACCESS.bus only. If the module is accessed through the LPC bus, it responds according to the setting of the ACCLMD field and the ACCLVIOL bit (see CONFALOK bit). The setting of this bit also forces module activation regardless of the actual setting of its Activation bit (index 30 - see Section 3.2.3 on page 39) and of the setting of the global enable bit (GLOBEN bit in the SIOCF1 register). 0: Module opened for LPC access (default) 1: Module locked for LPC access and opened for use by ACCESS.bus only (see Section 3.3.2 on page 43) 3 SER1ALOK (Serial Port 1 Access Lock). When set to 1, this bit disables LPC bus access to the Serial Port 1 module and locks the module for use by ACCESS.bus only. If the module is accessed through the LPC bus, it responds according to the setting of the ACCLMD field and the ACCLVIOL bit (see CONFALOK bit). The setting of this bit also forces module activation regardless of the actual setting of its Activation bit (index 30 see Section 3.2.3 on page 39), of its fast-enable bit (SER1DIS bit in the SIOCF6 register) and of the setting of the global enable bit (GLOBEN bit in the SIOCF1 register). 0: Module opened for LPC access (default) 1: Module locked for LPC access and opened for use by ACCESS.bus only (see Section 3.3.2 on page 43) 2 SER2ALOK (Serial Port 2 Access Lock). When set to 1, this bit disables LPC bus access to the Serial Port 2 module and locks the module for use by ACCESS.bus only. This bit behaves like the SER1ALOK bit. 0: Module opened for LPC access (default) 1: Module locked for LPC access and opened for use by ACCESS.bus only (see Section 3.3.2 on page 43) 1 PARPALOK (Parallel Port Access Lock). When set to 1, this bit disables LPC bus access to the Parallel Port module and locks the module for use by ACCESS.bus only. This bit behaves like the SER1ALOK bit. 0: Module opened for LPC access (default) 1: Module locked for LPC access and opened for use by ACCESS.bus only (see Section 3.3.2 on page 43) 0 FDCALOK (Floppy Disk Controller Access Lock). When set to 1, this bit disables LPC bus access to the Floppy Disk Controller module and locks the module for use by ACCESS.bus only. This bit behaves like the SER1ALOK bit. 0: Module opened for LPC access (default) 1: Module locked for LPC access and opened for use by ACCESS.bus only (see Section 3.3.2 on page 43) 131 www.national.com 6.0 ACCESS.bus Interface 6.3.8 (Continued) Access Lock Configuration 2 Register (ACCLCF2) This register controls the locking to LPC bus access of the device functional blocks. On reset, it is cleared (00h). Power Well: VSB Location: Offset 06h Type: R/W Bit 7 Name 6 SWCALOK RTCALOK Reset 0 0 5 4 XBSALOK Reserved 0 0 3 2 1 0 XCS3ALOK XCS2ALOK XCS1ALOK XCS0ALOK 0 0 0 0 Bit Description 7 SWCALOK (System Wake-up Controller Access Lock). When set to 1, this bit disables the LPC bus access to the System Wake-up Controller module and locks the module for use by ACCESS.bus only. If the module is accessed through the LPC bus (the SWC registers), it responds according to the setting of the ACCLMD field in the ACBCFG register (see Section 6.3.3 on page 127), and the ACCLVIOL bit in ACBCST is set (see Section 6.3.2 on page 126). This bit does not affect LPC access to the ACPI registers. The setting of this bit also forces module activation regardless of the actual setting of its Activation bit (index 30 - see Section 3.2.3 on page 39) and of the setting of the global enable bit (GLOBEN bit in the SIOCF1 register). 0: Module opened for LPC access (default) 1: Module locked for LPC access and opened for use by ACCESS.bus only (see Section 3.3.2 on page 43) 6 RTCALOK (Real-Time Clock Access Lock). When set to 1, this bit disables the LPC bus access to the RealTime Clock module and locks the module for use by ACCESS.bus only. This bit behaves like the SWCALOK bit. 0: Module opened for LPC access (default) 1: Module locked for LPC access and opened for use by ACCESS.bus only (see Section 3.3.2 on page 43) 5 XBSALOK (X-Bus Module Access Lock). When set to 1, this bit disables the LPC bus access to the X-Bus module and locks the module for use by ACCESS.bus only (PC87417). This bit behaves like the SWCALOK bit. 0: Module opened for LPC access (default) 1: Module locked for LPC access and opened for use by ACCESS.bus only (see Section 3.3.2 on page 43) 4 Reserved. 3 XCS3ALOK (X-Bus XCS3 Access Lock). When set to 1, this bit disables the LPC bus access to the X-Bus devices connected to XCS3 and locks them for use by ACCESS.bus only (PC87417). This bit behaves like the SWCALOK bit. 0: XCS3-connected devices opened for LPC access (default) 1: XCS3-connected devices locked for LPC access and opened for use by ACCESS.bus only (see Section 3.3.2 on page 43) 2 XCS2ALOK (X-Bus XCS2 Access Lock). Same as XCS3ALOK bit for X-Bus devices connected to XCS2 (PC87417) 1 XCS1ALOK (X-Bus XCS1 Access Lock). Same as XCS3ALOK bit for X-Bus devices connected to XCS1 (PC87417) 0 XCS0ALOK (X-Bus XCS0 Access Lock). Same as XCS3ALOK bit for X-Bus devices connected to XCS0 (PC87417) www.national.com 132 6.0 ACCESS.bus Interface (Continued) 6.4 ACB REGISTER BITMAP Register Offset Mnemonic Bits 7 6 5 4 PECERR BUSERR 00h ACBCST OFFLDN ILGCOM 01h ACBCFG CSWRST Reserved 02h 3 2 1 0 LOWCKTO ACCLVIOL VDDSTAT PECAVAIL Reserved ACTSTAT ACCLMD ACBLKCTL VSBLOCK UNLOCKM UNLOCKG UNLOCKF UNLOCKC UNLOCKX UNLOCKR UNLOCKS 03h ACBFDIS Reserved KBDDIS 04h ACBTRIS 05h ACCLCF1 CONFALOK 06h ACCLCF2 SWCALOK RTCALOK Reserved Reserved MSDIS SER1DIS SER2DIS PARPDIS FDCDIS KBMSTRIS SER1TRIS SER2TRIS PARPTRIS FDCTRIS KBCALOK SER1ALOK SER2ALOK PARPALOK FDCALOK Reserved 133 XCS3ALOK XCS2ALOK XCS1ALOK XCS0ALOK www.national.com 7.0 General-Purpose Input/Output (GPIO) Ports This chapter describes one 8-bit port. A device may include a combination of several ports with different implementations. For device specific implementation, see Section 3.14 on page 69. 7.1 OVERVIEW The GPIO port is an 8-bit port, connected to eight pins. It features: * * * * Software capability to control and read pin levels. Flexible system notification by several means, based on the pin level or level transition. Ability to capture and route events and their associated status. Back-drive protected pins. GPIO port operation is associated with two sets of registers: * Pin Configuration registers mapped in the Device Configuration space. These registers are used to set up the logical behavior of each pin. There are three registers for each GPIO pin: GPIO Pin Configuration registers 1 and 2 (GPCFG1, GPCFG2) and the GPIO Pin Event Routing register (GPEVR). * Four 8-bit runtime registers: GPIO Data Out (GPDO), GPIO Data In (GPDI), GPIO Event Enable (GPEVEN) and GPIO Event Status (GPEVST). These registers are mapped in the GPIO device IO space (which is determined by the base address registers in the GPIO Device Configuration). They are used to control and/or read the pin values and to handle system notification. Each runtime register corresponds to the 8-pin port, such that bit `n' in each one of the four registers is associated with GPIOXn pin, where `X' is the port number. Each GPIO pin is associated with configuration bits and the corresponding bit slice of the four runtime registers, as shown in Figure 35. The functionality of the GPIO port is divided into basic functionality, which includes the control and reading of the GPIO pins and enhanced functionality, which includes wake-up event detection and system notification. Basic functionality is described in Section 7.2; enhanced functionality is described in Section 7.3. Bit n GPDOX GPIOX Base Address GPDIX 8 GPCFG Registers X = port number n = pin number (0 to 7) GPIO Pin Configuration 1 and 2 (GPCFG1 and GPCFG2) Registers GPEVENX Runtime Registers GPEVSTX GPIOXn Pin GPIOXn CNFG GPIOXn Port Logic GPIO Pin Select (GPSEL) Register GPIO Pin Event Routing (GPEVR) Register Port and Pin Select x8 8 GPEVR Registers x8 GPIO Event x8 Pending Indication Event Routing Control GPIOXn ROUTE Interrupt Request SIOSMI Power Button Pulse Enable SWC SIOSCI ONCTL Figure 35. GPIO Port Architecture www.national.com 134 7.0 General-Purpose Input/Output (GPIO) Ports (Continued) 7.2 BASIC FUNCTIONALITY The basic functionality of each GPIO pin is based on four configuration bits and a bit slice of runtime registers GPDO and GPDI. The configuration and operation of a single pin GPIOXn (pin `n' in port `X') is shown in Figure 36. ACCESS.bus LPC Bus (GPDI) Read Only Data In Static Pull-Up Push-Pull =1 (GPDO) Pin Read/Write Data Out Pull-Up Enable Lock (GPCFG1) Lock Bus Control (Bits 6,5) Pin Lock (Bit 3) Lock Output Type (Bit 1) Pull-Up Control (Bit 2) Lock Output Enable (Bit 0) No_Vdd Lock V DD-powered (GPCFG2) Load (Bit 4) GPIO Pin Configuration Registers 1 and 2 Figure 36. GPIO Basic Functionality 7.2.1 Configuration Options The GPCFG1 register controls the following basic configuration options: * * Port Direction - Controlled by the Output Enable bit (bit 0). * * Static Pull-Up - May be added to any type of port (input, open-drain or push-pull). It is controlled by Pull-Up Control (bit 2). Output Type - Push-pull vs. open-drain. It is controlled by Output Buffer Type (bit 1) by enabling/disabling the upper transistor of the output buffer. Pin Lock - GPIO pin may be locked to prevent any changes in the output value and/or the output configuration. The lock is controlled by bit 3. It disables writes to the GPDO register bits, to bits 0-3 of the GPCFG1 register (including the Lock bit itself) and to bits 4-6 of the GPCFG2 register. Once locked, it can be released by reset or by the UNLOCKG bit in the ACBLKCTL register (see Section 6.3.4 on page 127 - PC87413 and PC87417). The GPCFG2 register controls the following basic configuration options: * Load Protection - Disables the Output Buffer (if enabled), the Static Pull-Up (if enabled) and the Input Buffer (if the Port is not a GPO type) if the specific GPIO pin is connected to a VDD-powered device and the VDD power is not present (No_Vdd). This function is controlled by the VDD-powered Load bit (bit 4). 135 www.national.com 7.0 General-Purpose Input/Output (GPIO) Ports * (Continued) Access Control - Limits access to the specific pin from only one of the buses (ACCESS.bus or LPC bus). When access from a bus is disabled, attempted writes to the Basic Functionality configuration registers (GPCFG1 bits 3-0 and GPCFG2 bits 6-4, none of which are shown in Figure 36) and to the corresponding bit in the GPDO register are ignored. Reads from the bits above and from the corresponding bit in the GPDI register are allowed and return the actual bit value. Bus access is controlled by Bus Control bits (bits 6 and 5). After reset, both bits are `0' and access is allowed from both ACCESS.bus and LPC bus. In the PC87414 and PC87416, this feature is irrelevant because only the LPC bus is available. 7.2.2 Operation If the output is enabled, the value that is written to the GPDO register is driven to the pin. Reading from the GPDO register returns its contents regardless of the actual pin value or the port configuration. The GPDI register is a read-only register. Reading from the GPDI register returns the actual pin value regardless of its source (the port itself or an external device). Writing to this register is ignored. Activation of the GPIO module is controlled by device-specific configuration bits. When this module is inactive, access through the LPC bus to the runtime registers (GPDI and GPDO) is disabled; however, there is no change in the GPDO value and therefore there is no effect on the outputs of the pins. 7.3 EVENT HANDLING AND SYSTEM NOTIFICATION The enhanced GPIO port (GPIOE) supports system notification based on event detection. This functionality is based on configuration bits and a bit slice of runtime registers GPEVEN and GPEVST. The configuration and operation of the event detection capability is shown in Figure 37. System notification is described in Section 7.3.2. GPIO Event Indication to SWC 1 Set 0 GPIO Event Pending Indication GPIO Status Read Reset R/W Write 1 to Clear Event Enable 0 Input Debouncer Rising Edge Detector 1 Pin Rising Edge or High Level =1 Level =1 Event Debounce Enable Event Polarity Event Type Bit 6 Bit 5 Bit 4 Internal Bus GPIO Pin Configuration Register 1 (GPCFG1) Figure 37. Event Detection 7.3.1 Event Configuration Each pin in the GPIO port is a potential input event source. The event detection can trigger a system notification upon predetermined behavior of the source pin. The GPCFG1 register determines the event detection trigger type for the system notification. www.national.com 136 7.0 General-Purpose Input/Output (GPIO) Ports (Continued) Event Debounce Enable The input signal can be debounced for about 15 msec before entering the detector. To ensure that the signal is stable, the signal state is transferred to the event detector only after a debouncing period during which the signal has no transitions. The debouncer adds a 16 msec delay to both assertion and de-assertion of the event pending indicator (IRQ, SMI, SCI). The debounce is controlled by Event Debounce Enable (bit 6 of the GPCFG1 register). Event Type and Polarity Two trigger types of event detection are supported: edge and level. An edge event may be detected upon a source pin transition either from high to low or low to high. A level event may be detected when the source pin is either at high or low level. The trigger type is determined by Event Type (bit 4 of the GPCFG1 register). The direction of the transition (for edge) or the polarity of the active level (for level) is determined by Event Polarity (bit 5 of the GPCFG1 register). The term active edge refers to a change in a GPIO pin level that matches the Event Polarity bit (1 for rising edge and 0 for falling edge). Active level refers to the GPIO pin level that matches the Event Polarity bit (1 for high level and 0 for low level). The corresponding bit of the GPEVST register is set by hardware whenever an active edge or an active level is detected regardless of the GPEVEN register setting. Writing 1 to the Status bit clears it to 0. Writing 0 is ignored. A GPIO pin is in event pending state if an active event occurred (the corresponding bit of the GPEVST register is set) and the corresponding bit of the GPEVEN register is set. 7.3.2 System Notification System notification on GPIO-triggered events is achieved by asserting at least one of the following output pins: * * Interrupt Request (via the Interrupt Serializer in the LPC Bus Interface). System Management Interrupt (SIOSMI, via the System Wake-Up Control). The system notification for each GPIO pin is controlled by the corresponding bit in the GPEVEN register and the bits of the GPEVR register. System notification by a GPIO pin is enabled if the corresponding bit of the GPEVEN register is set to 1. The bits of the GPEVR register select the means of system notification (IRQ or SMI) that the detected GPIO event is routed to. The event routing mechanism is described in Figure 38. GPIO Event Pending Indication GPIO Event to SIOSMI GPIO Event to IRQ Event Routing Logic Enable SMI Routing Enable IRQ Routing Bit 1 Bit 0 GPIO Pin Event Routing Register (GPEVR) Routed Events from other GPIO Pins Figure 38. GPIO Event Routing Mechanism for System Notification The system notification to the target is asserted if at least one GPIO pin is in event pending state. The selection of the target (the means of system notification) is determined by the GPEVR register. If IRQ is selected as one of the means for the system notification, the specific IRQ number is determined by the IRQ selection procedure of the device configuration. The assertion of IRQ (as a means of system notification) is disabled either when the GPIO functional block is deactivated or when the VDD power is OFF. The assertion of SMI is independent of the activation of the GPIO functional block. SMI from GPIO pins connected to a device powered by VDD (VDDLOAD = 1 in the GPCFG2 register) is disabled when the VDD power is OFF. However, SMI from GPIO pins connected to a device powered by VSB (VDDLOAD = 0) is not affected by the status of the VDD power. 137 www.national.com 7.0 General-Purpose Input/Output (GPIO) Ports (Continued) System notification through IRQ, SMI or SCI (see Section 9.2.1 on page 161) can be initiated by software by writing to the Data Out bit (in the GPDO register) of a GPIO pin. This is possible only if the output of the corresponding GPIO pin is enabled, pin multiplexing is selected for the GPIO function (see Section 1.3 on page 20) and the GPIO event is routed to IRQ, SMI or SCI. System notification is asserted according to the actual level at the GPIO pin driven by the GPIO output and/or by external circuitry. The level driven by the GPIO output should not cause a contention with the level driven by the external circuitry. A pending edge event may be cleared by clearing the corresponding GPEVST bit. However, a level event source may not be released by software (except for disabling the source) as long as the pin is at active level. When level event is used, it is also recommended to disable the input debouncer. Upon deactivation of the GPIO functional block and while the VDD power is OFF, access through the LPC bus to the runtime registers (GPEVST and GPEVEN) is disabled. All means of system notification that include the target IRQ number are detached from the GPIO and de-asserted. When the VDD power is OFF, the status bits of the GPIO pins connected to a VDD-powered device (VDDLOAD = 1) are cleared, however the status bits of the GPIO pins connected to a VSB-powered device (VDDLOAD = 0) is not affected. Before enabling any system notification, it is recommended to set the desired event configuration and then verify that the status registers are cleared. 7.4 GPIO PORT REGISTERS The following abbreviations are used to indicate the Register Type: R/W = Read/Write. R = Read from a specific register (write to the same address is to a different register). W = Write (see above). RO = Read Only. WO = Write Only. Reading from the bit returns 0. R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect. R/W1S = Read/Write 1 to Set. Writing 1 to a bit sets its value to 1. Writing 0 has no effect. 7.4.1 GPIO Pin Configuration Registers Structure For each Port, there is a group of eight identical sets of configuration registers. Each set is associated with one GPIO pin. The entire group is mapped to the PnP configuration space. The mapping scheme is based on the GPSEL register (see Section 3.14.3 on page 71), which functions as an index register, and the specific GPCFG1, GPEVR and GPCFG2 registers that reflect the configuration of the currently selected pin (see Table 34). All these registers are VSB powered. Table 34. GPIO Configuration Registers Index Configuration Register or Action Type Power Well Reset F0h GPIO Pin Select register (GPSEL). R/W VSB 00h F1h GPIO Pin Configuration register 1 (GPCFG1). R/W VSB Note1 F2h GPIO Pin Event Routing register (GPEVR). R/W VSB 01h F3h GPIO Pin Configuration register 2 (GPCFG2). R/W VSB 00h 1. See Section 3.14.3 on page 71. www.national.com 138 7.0 General-Purpose Input/Output (GPIO) Ports 7.4.2 (Continued) GPIO Port Runtime Register Map All these registers are VSB powered. Offset Mnemonic Register Name Type Power Well Reset Section Device specific1 GPDO GPIO Data Out R/W VSB FFh 7.4.3 Device specific1 GPDI GPIO Data In RO VSB - 7.4.4 Device specific1 GPEVEN GPIO Event Enable R/W VSB 00h 7.4.5 Device specific1 GPEVST GPIO Event Status R/W1C VSB 00h 7.4.6 1. The location of this register is defined in Section 3.14.1 on page 69. 7.4.3 GPIO Data Out Register (GPDO) Power Well: VSB Location: Device specific Type: R/W Bit 7 6 5 4 Name 3 2 1 0 1 1 1 1 DATAOUT Reset 1 1 1 1 Bit Description 7-0 DATAOUT (Data Out). Bits 7-0 correspond to pins 7-0 of the specific Port. The value of each bit determines the value driven on the corresponding GPIO pin when its output buffer is enabled. Writing to the bit latches the written data unless the bit is locked by the GPCFG register Lock bit. Reading the bit returns its value regardless of the pin value and configuration. 0: Corresponding pin driven to low 1: Corresponding pin driven or released (according to buffer type selection) to high (default) 7.4.4 GPIO Data In Register (GPDI) Power Well: VSB Location: Device specific Type: RO Bit 7 6 5 4 Name Reset 3 2 1 0 X X X X DATAIN X X X X Bit Description 7-0 DATAIN (Data In). Bits 7-0 correspond to pins 7-0 of the specific Port. Reading each bit returns the value of the corresponding GPIO pin. Pin configuration and the GPDO register value may influence the pin value. Write is ignored. 0: Corresponding pin level low 1: Corresponding pin level high 139 www.national.com 7.0 General-Purpose Input/Output (GPIO) Ports 7.4.5 (Continued) GPIO Event Enable Register (GPEVEN) Power Well: VSB Location: Device specific Type: R/W Bit 7 6 5 4 Name 3 2 1 0 0 0 0 0 EVTENA Reset 0 0 0 0 Bit Description 7-0 EVTENA (Event Enable). Bits 7-0 correspond to pins 7-0 of the specific Port. Each bit enables system notification by the corresponding GPIO pin. The bit has no effect on the corresponding Status bit in the GPEVST register. 0: Event Pending by corresponding GPIO pin masked 1: Event Pending by corresponding GPIO pin enabled 7.4.6 GPIO Event Status Register (GPEVST) Power Well: VSB Location: Device specific Type: R/W1C Bit 7 6 5 4 Name 3 2 1 0 0 0 0 0 EVTSTAT Reset 0 0 0 0 Bit Description 7-0 EVTSTAT (Event Status). Bits 7-0 correspond to pins 7-0 of the specific Port. The setting of each bit is independent of the Event Enable bit in the GPEVEN register. An active event sets the Status bit, which may be cleared only by software writing 1 to the bit. 0: No active edge or level detected since last cleared 1: Active edge or level detected www.national.com 140 8.0 Real-Time Clock (RTC) 8.1 OVERVIEW The RTC provides timekeeping and calendar management capabilities. It uses a 32.768 KHz signal as the basic clock for timekeeping. The RTC also includes 242 bytes of battery-backed RAM for general-purpose use. The RTC provides the following functions: Accurate timekeeping and calendar management. Alarm at a predetermined time and/or date. Three programmable interrupt sources. Valid timekeeping during power-down by utilizing external battery backup. 242 bytes of battery-backed RAM. RAM lock schemes to protect its content. Internal oscillator circuit (the crystal itself is off-chip) or external clock supply for the 32.768 KHz clock. A century counter. PnP support: -- Relocatable index and data registers -- Module access enable/disable option -- Host interrupt enable/disable option Additional low-power features such as: -- Automatic switching from VBAT to VSB -- Internal power monitoring on the VRT bit -- Oscillator disabling to conserve battery power during storage Software compatible with the DS1287 and MC146818. 8.2 FUNCTIONAL DESCRIPTION 8.2.1 Bus Interface The RTC function is initially mapped to the default ServerI/O locations at indexes 70h to 73h (two Index/Data pairs). These locations may be reassigned in compliance with Plug and Play requirements. 8.2.2 RTC Clock Generation The RTC uses a 32.768 KHz clock signal as the basic clock for timekeeping. The 32.768 KHz clock is supplied by either the internal oscillator circuit or by an external oscillator (see Sections 8.2.3 and 8.2.4). 8.2.3 Internal Oscillator The internal oscillator employs an external crystal connected to the on-chip amplifier. The on-chip amplifier is accessible on the 32KX1 input pin and 32KX2 output pin. See Figure 39 for the recommended external circuit; see Table 35 on page 142 for a listing of the circuit components. The oscillator may be disabled in certain conditions. See Section 8.2.12 on page 146 for more details. To other modules VBAT CF 32KX1 / 32KCLKIN B1 32KX2 R1 C1 Y Battery Internal External R2 C2 CF = 0.1F Figure 39. Recommended Oscillator External Circuitry 141 www.national.com 8.0 Real-Time Clock (RTC) (Continued) Table 35. Crystal Oscillator Circuit Components Component Crystal Parameters Resonance Frequency Values Tolerance 32.768 KHz Parallel mode User defined Type N-Cut or XY-bar Serial Resistance 40 K Max Quality Factor, Q 35000 Min 2 pF Max Shunt Capacitance 9-13 pF Load Capacitance, CL Temperature Coefficient User-defined Resistor R1 Resistance 20 M 5% Resistor R2 Resistance 510 K 5% Capacitor C1 Capacitance 10 pF 5% Capacitor C2 Capacitance 10 pF 5% External Elements Choose C1 and C2 capacitors (see Figure 39) to match the crystal's load capacitance. The load capacitance CL "seen" by crystal Y is comprised of C1 in series with C2 and in parallel with the parasitic capacitance of the circuit. The parasitic capacitance is caused by the chip package, board layout and socket (if any) and can vary from 0 to 8 pF. The rule of thumb in choosing these capacitors is: CL = (C1 * C2) / (C1 + C2) + CPARASITIC Oscillator Start-Up The oscillator starts to generate 32.768 KHz pulses to the RTC after about t32KW from when VBAT is higher than VBATMIN (2.4V) or VSB is higher than VSBON (2.5V). The oscillation amplitude on the X2C pin stabilizes to its final value (approximately 0.4V peak-to-peak around 0.7V DC) in about 1 sec. C1 can be trimmed to achieve precisely 32.768 KHz. For highly accurate timekeeping, use crystal and capacitors with low tolerance and temperature coefficients. 8.2.4 External Oscillator 32.768 KHz can be applied from an external clock source, as shown in Figure 40. VBAT To other modules Internal CF 32KCLKIN / 32KX1 32KX2 External NC OUT PWR 32.768 KHz Clock Generator CF B1 Battery CF = 0.1F Figure 40. External Oscillator Connections Connections Connect the clock to the 32KCLKIN pin, leaving the oscillator output, 32KX2, unconnected. www.national.com 142 8.0 Real-Time Clock (RTC) (Continued) Signal Parameters The signal levels must conform to the voltage level requirements for 32KCLKIN/32KX1 stated in Section 11.2 on page 232. The signal must have a duty cycle of approximately 50%. To oscillate during power-down, the signal must be sourced from a battery-backed source. This assures that the RTC delivers updated time/calendar information. 8.2.5 Timing Generation The timing generation function divides the 32.768 KHz clock by 215 to derive a 1 Hz signal, which serves as the input for the seconds counter. This is performed by a divider chain composed of 15 divide-by-two latches, as shown in Figure 41. Divider Chain 1 2 2 2 3 2 13 14 15 2 2 2 1 Hz Reset DV2 DV1 DV0 6 5 4 CRA Register 32.768 KHz To other modules 32KX1 / 32KCLKIN Oscillator Enable 32KX2 Figure 41. Divider Chain Control Bits 6-4 (DV2-0) of the CRA register control the following functions: Normal operation of the divider chain (counting). Divider chain reset to 0. Oscillator activity when only VBAT power is present (backup state). The divider chain can be activated by setting Normal Operation mode (bits 6-4 of CRA = 010b). The first update occurs 500 ms after divider chain activation. Bits 3-0 of the CRA register select one the of 15 taps from the divider chain to be used as a periodic interrupt. The periodic flag becomes active after half of the programmed period has elapsed, following divider chain activation. See Section 8.3.13 on page 153 for more details. 8.2.6 Timekeeping Data Format Time is kept in BCD or binary format, as determined by bit 2 (DM) of Control Register B (CRB), and in either 12 or 24-hour format, as determined by bit 1 of this register. Note: When changing the above formats, re-initialize all the time registers. Daylight Saving Daylight saving time exceptions are handled automatically, as described in the RTC Control Register B (CRB) in Section 8.3.2 on page 149. Leap Years Leap year exceptions are handled automatically by the internal calendar function (every four years, February is extended to 29 days). 143 www.national.com 8.0 Real-Time Clock (RTC) 8.2.7 (Continued) Updating The time and calendar registers are updated once per second regardless of bit 7 (SET) of the CRB register. Since the time and calendar registers are updated serially, unpredictable results may occur if they are accessed during the update. Therefore, it is essential to ensure that reading or writing to the time storage locations does not coincide with a system update of these locations. There are four methods to avoid this contention. Method 1 1. Set bit 7 of the CRB register to 1. This takes a "snapshot" of the internal time registers and loads them into the user copy registers. The user copy registers are seen when accessing the RTC from outside and are part of the double buffering mechanism. This bit may be kept set for up to 1 second, since the time/calendar chain continues to be updated once per second. 2. Read or write the required registers (since bit 7 is set, the access is to the user copy registers). If a read operation is performed, the information read is correct from the time bit 7 was set. If a write operation is performed, the write is only to the user copy registers. 3. Reset bit 7 to 0. During the transition, the user copy registers update the internal registers, using the double buffering mechanism to ensure that the update is performed between two time updates. This mechanism enables new time parameters to be loaded in the RTC. Method 2 1. Access the RTC registers after detection of an Update Ended interrupt. The detection interrupt implies that an update has just been completed and 999 ms remain until the next update. 2. To detect an Update Ended interrupt, either: -- Poll bit 4 of the CRC register. -- Use the following interrupt routine: a) Set bit 4 of the CRB register. b) Wait for an interrupt from interrupt pin. c) Clear the IRQF flag of the CRC register before exiting the interrupt routine. Method 3 Poll bit 7 of the CRA register. The update occurs 244 s after this bit goes high. Therefore, if a 0 is read, the time registers remain stable for at least 244 s. Method 4 Use a periodic interrupt routine to determine if an update cycle is in progress, as follows: 1. Set the periodic interrupt to the desired period. 2. Set bit 6 of the CRB register to enable the interrupt from periodic interrupt. 3. Wait for the appearance of a periodic interrupt, which indicates that the period represented by the following expression remains until another update occurs: [(Period of periodic interrupt / 2) + 244 s] 8.2.8 Alarms The timekeeping function can be set to generate an alarm when the current time reaches a stored alarm time. After each RTC time update (every 1 second), the seconds, minutes, hours, date-of-month and month counters are compared with their corresponding registers in the alarm settings. If they are equal, bit 5 of the CRC register is set to 1 and sent to the SWC as an alarm signal. If the Alarm Interrupt Enable bit was previously set (bit 5 of the CRB register), the interrupt request pin is also active. Any alarm register may be set to Unconditional Match by setting bits 7 and 6 to binary `11'. This combination, not used by any BCD or binary time codes, results in a periodic alarm. The rate of this periodic alarm is determined by the registers that were set to Unconditional Match. For example, if all but the seconds and minutes alarm registers are set to Unconditional Match, an interrupt is generated every hour at the specified minute and second. If all but the seconds, minutes and hours alarm registers are set to Unconditional Match, an interrupt is generated every day at the specified hour, minute and second. www.national.com 144 8.0 Real-Time Clock (RTC) 8.2.9 (Continued) Power Supply The device is supplied from three supply voltages, as shown in Figure 42: System power supply voltage, VDD. System standby power supply voltage, VSB. Backup voltage, from low-capacity Lithium battery VBAT. A standby voltage (VSB) from the external AC/DC power supply powers the RTC under normal conditions. External AC Power Power Management VDD Sense Power Supply VDD VDD ONCTL ONCTL RTC VDD VSB VSB VBAT VBAT VSB ON/OFF Control VSB VBAT VBAT Backup Battery Figure 42. Power Supply Connections Figure 43 shows a typical battery configuration. No external diode is required to meet the UL standard due to the internal switch and internal serial resistor RUL. RTC VPP VSB CF 0.1 F VREF VBAT RUL CE 22 F VSB BT1 CF 0.1 F 1. Place a 0.1 F capacitor on each VSB power supply pin and on VBAT as close to the pin as possible. 2. Place a 10-47 F capacitor on the common VSB power supply net as close to the device as possible. Figure 43. Typical Battery Configuration The RTC is supplied from one of two power supplies, VSB or VBAT, depending on their voltage levels. An internal voltage comparator delivers the control signals to a pair of switches. Battery backup voltage VBAT maintains the correct time and saves the CMOS memory when the VSB voltage is absent due to power failure or disconnection of the external AC/DC input power supply or VSB main battery. To ensure that the module uses power from VSB and not from VBAT, the VSB voltage must be maintained above its minimum, as detailed in Section 11.1.5 on page 231. The actual voltage point where the module switches from VBAT to VSB is lower than the minimum workable battery voltage but high enough to guarantee the correct functionality of the oscillator and the CMOS RAM. Figure 44 shows typical battery current consumption during battery-backed operation; Figure 45 shows the same during normal operation. 145 www.national.com 8.0 Real-Time Clock (RTC) (Continued) IBAT (A) 1.0 0.9 0.8 0.7 2.4 3.0 3.6 VBAT (V) Figure 44. Typical Battery Current During Battery-Backed Power Mode IBAT (A) 0.20 0.15 0.10 0.05 VSB (V) 3.0 3.3 3.6 Note: Battery voltage in this test is 3.0V. Figure 45. Typical Battery Current During Normal Operation Mode 8.2.10 System Bus Lockout During power on or power off, spurious bus transactions from the host may occur. To protect the data in the RTC internal registers from being corrupted, all inputs are automatically locked out. The lockout condition is asserted when VSB is lower than VSBON at VSB power-on or VSBOFF at VSB power-off. 8.2.11 Power-Up Detection When system power is restored after a power failure or power off state (VSB=0), the lockout condition continues for a delay of 62 ms (minimum) to 125 ms (maximum) after the RTC switches from battery to system power. The lockout condition is switched off immediately in the following situations: * If the Divider Chain Control bits, DV0-2 (bits 6-4 in the CRA register), specify a normal operation mode (010), all input signals are enabled immediately on detection of system voltage above VSBON. * When battery voltage is below VBATDCT and LRESET is 0, all input signals are enabled immediately on detection of system voltage above VSBON. This also initializes registers at offsets 00h through 0Dh. * If bit 7 (VRT) of the CRD register is 0, all input signals are enabled immediately on detection of system voltage above VSBON. 8.2.12 Oscillator Activity The RTC oscillator is active if: VSB power supply is higher than VSBON regardless of the battery voltage, VBAT. VBAT power supply is higher than VBATMIN whether or not VSB is present. The RTC oscillator is disabled if: During power-down (VBAT only), if the battery voltage drops below VBATMIN, Battery Fail state may be entered. In this case, the oscillator may stop oscillating and memory contents may be corrupted or lost. Software writes 00h to DV2-0 bits of the CRA register and VSB is removed. This disables the oscillator and decreases the power consumption from the battery connected to the VBAT pin. When disabling the oscillator, the CMOS RAM is not affected as long as the battery is present at a correct voltage level. www.national.com 146 8.0 Real-Time Clock (RTC) (Continued) If the RTC oscillator becomes inactive, the following features are dysfunctional/disabled: Timekeeping. Periodic interrupt. Alarm. 8.2.13 Interrupt Handling The RTC has a single Interrupt Request line which handles the following three interrupt conditions: Periodic interrupt. Alarm interrupt. Update end interrupt. The interrupts are generated if the respective enable bits in the CRB register are set prior to an interrupt event occurrence. Reading the CRC register clears all interrupt flags. Thus, when multiple interrupts are enabled, the interrupt service routine must first read and store the CRC register and then deal with all pending interrupts by referring to this stored status. If an interrupt is not serviced before a second occurrence of the same interrupt condition, the second interrupt event is lost. Figure 46 illustrates the interrupt and status timing in the RTC. Bit 7 of CRA A (244 s) Bit 4 of CRC P P/2 Bit 6 of CRC P/2 B C (30.5 s) Bit 5 of CRC Flags (and IRQ) are reset at the conclusion of CRC read or by reset. A: B: C: P: Update In Progress bit high before update occurs = 244 s Periodic interrupt to update = (P/2 + A) Update to Alarm Interrupt = 30.5 s Periodic interrupt cycle (programmed by RS3-0 of CRA) Figure 46. Interrupt/Status Timing 8.2.14 Battery-Backed RAMs and Registers The RTC has two battery-backed RAMs and 17 registers used by the logical units themselves. Battery-backup power enables information retention during system power down. The RAMs are: Standard RAM. Extended RAM. The memory maps and register content of the RAMs are illustrated in Section 8.6 on page 159. The first 14 bytes and three programmable bytes of the Standard RAM are overlaid by time, alarm data and control registers. The remaining 111 bytes are general-purpose memory. Registers with reserved bits must be written using the "Read-Modify-Write" method. All register locations within the device are accessed by the RTC Index and Data registers (at base address and base address+1). The Index register points to the register location being accessed. The Data register contains the data to be transferred to or from the location. An additional 128 bytes of battery-backed RAM (also called Extended RAM) may be accessed via a second pair of Index and Data registers pointed at by the secondary base address and base address+1. Access to the two RAMs may be locked. For details see the RAM Lock Register (RLR) in Section 3.16.3 on page 87. 147 www.national.com 8.0 Real-Time Clock (RTC) (Continued) 8.3 RTC REGISTERS The RTC configuration registers can be accessed at any time during normal or standby operation; i.e., when VSB and/or VDD are within the recommended operation range. Access to the RTC configuration registers is disabled during battery-backed operation. The register maps in this chapter use the following abbreviations for Type: R/W = Read/Write. R = Read from a specific register (write to the same address is to a different register). W = Write (see above). RO = Read Only. WO = Write Only. Reading from the bit returns 0. R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect. R/W1S = Read/Write 1 to Set. Writing 1 to a bit sets its value to 1. Writing 0 has no effect. 8.3.1 RTC Configuration Registers Structure The RTC configuration registers can be accessed at any time during normal or standby operation; i.e., when VSB and/or VDD are within the recommended operation range. Access to the RTC configuration registers is disabled during battery-backed operation. See Section 3.16 on page 86 for a description of the Configuration registers. Table 36. RTC Configuration Register Map Index RTC Configuration Register or Action Type Power Well Reset R/W1S VSB 00h Date-of-Month Alarm Register Offset (DOMAO). R/W VSB 00h F2h Month Alarm Register Offset (MONAO). R/W VSB 00h F3h Century Register Offset (CENO). R/W VSB 00h F0h RAM Lock Register (RLR). F1h www.national.com 148 8.0 Real-Time Clock (RTC) 8.3.2 (Continued) RTC Runtime Register Map The RTC runtime registers can be accessed at any time during normal or standby operation; i.e., when VSB and/or VDD are within the recommended operation range. The access is disabled during battery-backed operation. Write operation to these registers is also disabled if bit 7 of the CRD register is 0 (see Section 8.3.16 on page 156). Note: Before attempting to perform any start-up procedures, read the explanation of bit 7 (VRT) of the CRD register (see Section 8.3.16 on page 156). See Section 8.6 on page 159 for a detailed description of the memory map for the RTC registers. This section describes the RTC Timing and Control registers that control basic RTC functionality. All registers are VPP powered. Index Mnemonic Name Type Power Well Reset Section 00h SEC Seconds Register R/W VPP VPP PUR 8.3.3 01h SECA Seconds Alarm Register R/W VPP VPP PUR 8.3.4 02h MIN Minutes Register R/W VPP VPP PUR 8.3.5 03h MINA Minutes Alarm Register R/W VPP VPP PUR 8.3.6 04h HOR Hours Register R/W VPP VPP PUR 8.3.7 05h HORA Hours Alarm Register R/W VPP VPP PUR 8.3.8 06h DOW Day-of-Week Register R/W VPP VPP PUR 8.3.9 07h DOM Date-of-Month Register R/W VPP VPP PUR 8.3.10 08h MON Month Register R/W VPP VPP PUR 8.3.11 09h YER Year Register R/W VPP VPP PUR 8.3.12 0Ah CRA RTC Control Register A Varies per bit VPP Bit specific 8.3.13 0Bh CRB RTC Control Register B R/W VPP Bit specific 8.3.14 0Ch CRC RTC Control Register C R/O VPP Bit specific 8.3.15 0Dh CRD RTC Control Register D R/O VPP VPP PUR 8.3.16 Programmable1 by DOMAO DOMA Date-of-Month Alarm Register R/W VPP VPP PUR 8.3.17 Programmable1 by MONAO MONA Month Alarm Register R/W VPP VPP PUR 8.3.18 Century Register R/W VPP VPP PUR 8.3.19 Programmable1 by CENO CEN 1. Overlaid on RAM bytes in range 0Eh-7Fh. 8.3.3 Seconds Register (SEC) Power Well: VPP Location: Index 00h Type: R/W Bit 7 6 5 Name Reset Bit 7-0 4 3 2 1 0 0 0 0 Seconds Data 0 0 0 0 0 Description Seconds Data. Values may be 00 to 59 in BCD format or 00 to 3B in Binary format. 149 www.national.com 8.0 Real-Time Clock (RTC) 8.3.4 (Continued) Seconds Alarm Register (SECA) Power Well: VPP Location: Index 01h Type: R/W Bit 7 6 5 Name 0 0 0 Bit 8.3.5 3 2 1 0 0 0 0 Seconds Alarm Data Reset 7-0 4 0 0 Description Seconds Alarm Data. Values may be 00 to 59 in BCD format or 00 to 3B in Binary format. When bits 7 and 6 are both set to one (`11'), unconditional match is selected. Minutes Register (MIN) Power Well: VPP Location: Index 02h Type: R/W Bit 7 6 5 Name 0 0 0 Bit 8.3.6 3 2 1 0 0 0 0 2 1 0 0 0 0 Minutes Data Reset 7-0 4 0 0 Description Minutes Data. Values may be 00 to 59 in BCD format or 00 to 3B in Binary format. Minutes Alarm Register (MINA) Power Well: VPP Location: Index 03h Type: R/W Bit 7 6 5 Name 3 Minutes Alarm Data Reset 0 Bit 7-0 4 0 0 0 0 Description Minutes Alarm Data. Values may be 00 to 59 in BCD format or 00 to 3B in Binary format. When bits 7 and 6 are both set to one (`11'), unconditional match is selected. www.national.com 150 8.0 Real-Time Clock (RTC) 8.3.7 (Continued) Hours Register (HOR) Power Well: VPP Location: Index 04h Type: R/W Bit 7 6 5 4 Name 3 2 1 0 0 0 0 0 Hours Data Reset 0 0 0 0 Bit Description 7-0 Hours Data. For 12-Hour mode, values may be 01 to 12 (AM) and 81 to 92 (PM) in BCD format or 01 to 0C (AM) and 81 to 8C (PM) in Binary format. For 24-Hour mode, values may be 0 to 23 in BCD format or 00 to 17 in Binary format. 8.3.8 Hours Alarm Register (HORA) Power Well: VPP Location: 05h Type: R/W Bit 7 6 5 Name 4 3 2 1 0 0 0 0 Hours Alarm Data Reset 0 0 0 0 0 Bit Description 7-0 Hours Alarm Data. For 12-Hour mode, values may be 01 to 12 (AM) and 81 to 92 (PM) in BCD format or 01 to 0C (AM) and 81 to 8C (PM) in Binary format. For 24-Hour mode, values may be 0 to 23 in BCD format or 00 to 17 in Binary format. When bits 7 and 6 are both set to one (`11'), unconditional match is selected. 8.3.9 Day-of-Week Register (DOW) Power Well: VPP Location: Index 06h Type: R/W Bit 7 6 5 Name Reset Bit 7-0 4 3 2 1 0 0 0 0 Day-of-Week Data 0 0 0 0 0 Description Day-of-Week Data. Values may be 01 to 07 in BCD format or 01 to 07 in Binary format. 151 www.national.com 8.0 Real-Time Clock (RTC) (Continued) 8.3.10 Date-of-Month Register (DOM) Power Well: VPP Location: Index 07h Type: R/W Bit 7 6 5 Name 3 2 1 0 0 0 0 2 1 0 0 0 0 Date-of-Month Data Reset 0 0 0 Bit 7-0 4 0 0 Description Date-of-Month Data. Values may be 01 to 31 in BCD format or 01 to 1F in Binary format. 8.3.11 Month Register (MON) Power Well: VPP Location: Index 08h Type: R/W Bit 7 6 5 Name 3 Month Data Reset 0 0 0 Bit 7-0 4 0 0 Description Month Data. Values may be 01 to 12 in BCD format or 01 to 0C in Binary format. 8.3.12 Year Register (YER) Power Well: VPP Location: Index 09h Type: R/W Bit 7 6 5 4 Name 2 1 0 0 0 0 0 Year Data Reset 0 Bit 7-0 3 0 0 0 Description Year Data. Values may be 00 to 99 in BCD format or 00 to 63 in Binary format. www.national.com 152 8.0 Real-Time Clock (RTC) (Continued) 8.3.13 RTC Control Register A (CRA) This register controls test selection in addition to other functions. This register cannot be written before reading bit 7 of the CRD register. Power Well: VPP Location: Index 0Ah Type: Varies per bit Bit 7 6 Name Update in Progress Reset 0 5 4 3 Divider Chain Control 0 1 2 1 0 Periodic Interrupt Rate Select 0 0 0 0 0 Bit Type Description 7 RO Update in Progress. This bit is not affected by reset. It reads 0 when bit 7 of the CRB register is 1. 0: Timing registers not updated within 244 s 1: Timing registers updated within 244 s 6-4 R/W Divider Chain Control. These bits control the configuration of the divider chain for timing generation (see Table 37). They are cleared to 000 as long as bit 7 of the CRD register reads 0. 3-0 R/W Periodic Interrupt Rate Select. These bits select one of 15 output taps from the clock divider chain to control the rate of the periodic interrupt (see Table 38 and Figure 41 on page 143). They are cleared to 000 as long as bit 7 of the CRD register reads 0. Table 37. Divider Chain Control and Test Selection DV2 (CRA6) DV1 (CRA5) DV0 (CRA4) 0 0 X Oscillator Disabled 0 1 0 Normal Operation 0 1 1 1 0 X 1 1 X Configuration Reserved Divider Chain Reset 153 www.national.com 8.0 Real-Time Clock (RTC) (Continued) Table 38. Periodic Interrupt Rate Encoding www.national.com Rate Select 3210 Periodic Interrupt Rate (ms) 0000 No interrupts 0001 3.906250 7 0010 7.812500 8 0011 0.122070 2 0100 0.244141 3 0101 0.488281 4 0110 0.976562 5 0111 1.953125 6 1000 3.906250 7 1001 7.812500 8 1010 15.625000 9 1011 31.250000 10 1100 62.500000 11 1101 125.000000 12 1110 250.000000 13 1111 500.000000 14 154 Divider Chain Output 8.0 Real-Time Clock (RTC) (Continued) 8.3.14 RTC Control Register B (CRB) Power Well: VPP Location: Index 0Bh Type: R/W Bit 7 6 5 4 3 2 1 0 Name SETMODE PIE AIE UIE Reserved DATMODE HRMODE DSVMODE Reset 0 0 0 0 0 0 0 0 . Bit 7 Description SETMODE (Set Mode). This bit is reset at VPP power-up reset only. 0: Timing updates occur normally 1: User copy of time is frozen, allowing the time registers to be accessed whether or not an update occurs 6 PIE (Periodic Interrupt Enable). Bits 3-0 of the CRA register determine the rate at which this interrupt is generated. It is cleared to 0 on RTC reset (i.e., hardware or software reset) or when RTC is disabled. 0: Disabled 1: Enabled 5 AIE (Alarm Interrupt Enable). This interrupt is generated immediately after a time update in which the seconds, minutes, hours, date and month time equal their respective alarm counterparts. It is cleared to 0 as long as bit 7 of the CRD register reads 0. 0: Disabled 1: Enabled 4 UIE (Update Ended Interrupt Enable). This interrupt is generated when an update occurs. It is cleared to 0 on RTC reset (i.e., hardware or software reset) or when the RTC is disabled. 0: Disabled 1: Enabled 3 Reserved. This bit is defined as "Square Wave Enable" by MC146818 and is not supported by the RTC. It is always read as 0. 2 DATMODE (Data Mode). This bit is reset at VPP power-up reset only. 0: BCD format enabled 1: Binary format enabled 1 HRMODE (Hour Mode). This bit is reset at VPP power-up reset only. 0: 12-hour format enabled 1: 24-hour format enabled 0 DSVMODE (Daylight Saving). This bit is reset at VPP power-up reset only. 0: Disabled 1: Enabled: In the spring, time advances from 1:59:59 AM to 3:00:00 AM on the first Sunday in April. In the fall, time returns from 1:59:59 AM to 1:00:00 AM on the last Sunday in October. 155 www.national.com 8.0 Real-Time Clock (RTC) (Continued) 8.3.15 RTC Control Register C (CRC) Power Well: VPP Location: Index 0Ch Type: RO Bit 7 6 5 4 Name IRQF PIF AF UF Reset 0 0 0 0 3 2 1 0 0 0 Reserved 0 0 Bit Description 7 IRQF (IRQ Flag). This bit mirrors the value on the interrupt output signal. When interrupt is active, this bit is 1. To clear this bit (and deactivate the interrupt pin), perform a read on the CRC register. This read also clears flag bits UF, AF and PF. 0: IRQ inactive 1: IRQ active, according to the equation: ((UIE and UF) or (AIE and AF) or (PIE and PF)); see Section 8.3.14 on page 155 6 PIF (Periodic Interrupt Flag). This bit is cleared to 0 on RTC reset (i.e., hardware or software reset) or when the RTC is disabled. In addition, this bit is cleared to 0 when this register is read. 0: No transition occurred on the selected tap since the last read 1: Transition occurred on the selected tap of the divider chain 5 AIF (Alarm Interrupt Flag). This bit is cleared to 0 as long as bit 7 of the CRD register is reads 0. In addition, this bit is cleared to 0 when this register is read. 0: No alarm detected since the last read 1: Alarm condition detected 4 UIF (Update Ended Interrupt Flag). This bit is cleared to 0 on RTC reset (i.e., hardware or software reset) or the RTC disabled. In addition, this bit is cleared to 0 when this register is read. 0: No update occurred since the last read 1: Time registers updated 3-0 Reserved. 8.3.16 RTC Control Register D (CRD) Power Well: VPP Location: Index 0Dh Type: RO Bit 7 Name Valid RAM and Time Reset 0 6 5 4 3 2 1 0 0 0 0 Reserved 0 0 0 0 Bit Description 7 Valid RAM and Time. This bit senses the voltage that feeds the RTC (VSB or VBAT) and indicates if the voltage dropped below the specified minimum value VBATMIN. If the voltage is too low, the RTC contents (time/calendar registers and CMOS RAM) are not valid. 0: RTC contents not valid 1: RTC contents (time/calendar registers and CMOS RAM) are valid 6-0 Reserved. www.national.com 156 8.0 Real-Time Clock (RTC) (Continued) 8.3.17 Date-of-Month Alarm Register (DOMA) Power Well: VPP Location: Programmable Index through DOMAO register Type: R/W Bit 7 6 5 Name 4 2 1 0 0 0 0 Date-of-Month Alarm Data Reset 1 1 0 Bit 7-0 3 0 0 Description Date-of-Month Alarm Data. Values may be 01 to 31 in BCD format or 01 to 1F in Binary format. When bits 7 and 6 are both set to one (`11'), unconditional match is selected (default). 8.3.18 Month Alarm Register (MONA) Power Well: VPP Location: Programmable Index through MONAO register Type: R/W Bit 7 6 5 Name 3 2 1 0 0 0 0 2 1 0 0 0 0 Month Alarm Data Reset 1 1 0 Bit 7-0 4 0 0 Description Month Alarm Data. Values may be 01 to 12 in BCD format or 01 to 0C in Binary format. When bits 7 and 6 are both set to one (`11'), unconditional match is selected (default). 8.3.19 Century Register (CEN) Power Well: VPP Location: Programmable Index through CENO register Type: R/W Bit 7 6 5 Name Reset Bit 7-0 4 3 Century Data 0 0 0 0 0 Description Century Data. Values may be 00 to 99 in BCD format or 00 to 63 in Binary format. 157 www.national.com 8.0 Real-Time Clock (RTC) (Continued) 8.3.20 BCD and Binary Formats Parameter BCD Format Binary Format Seconds 00 to 59 00 to 3B Minutes 00 to 59 00 to 3B Hours 12-Hour mode: 01 to 12 (AM) 81 to 92 (PM) 24-Hour mode: 00 to 23 12-Hour mode: 01 to 0C (AM) 81 to 8C (PM) 24-Hour mode: 00 to 17 Day 01 to 07 (Sunday = 01) 01 to 07 Date 01 to 31 01 to 1F Month 01 to 12 (January = 01) 01 to 0C Year 00 to 99 00 to 63 Century 00 to 99 00 to 63 8.4 USAGE HINTS 1. Read bit 7 of the CRD register at each system power-up to validate the contents of the RTC registers and the CMOS RAM. When this bit is 0, the contents of these registers and the CMOS RAM are questionable. This bit is reset when the backup battery voltage is below the minimum specified battery voltage, VBATMIN. Although the RTC oscillator may function properly and the register contents may be correct at lower voltages than VBATMIN, this bit is reset because correct functionality cannot be guaranteed. System BIOS may use a checksum method to revalidate the contents of the CMOSRAM. The checksum byte must be stored in the CMOS RAM. 2. To maintain valid time and register information, change the backup battery while normal operating power is on and not while in Backup mode; however, if a low leakage capacitor is connected to VBAT, the battery can also be changed in Backup mode. 3. A rechargeable NiCd battery may be used instead of a non-rechargeable Lithium battery. This is the preferred solution for portable systems, where small size components is essential. 4. A supercap capacitor may be used instead of the normal Lithium battery. In a portable system, the VSB voltage is usually present because the power management stops the system before its voltage falls. The supercap capacitor in the range of 0.047-0.47F will supply the power during the battery replacement. www.national.com 158 8.0 Real-Time Clock (RTC) (Continued) 8.5 RTC REGISTER BITMAP Bits Register Offset Mnemonic 7 6 5 4 3 2 00h SEC Seconds Data 01h SECA Seconds Alarm Data 02h MIN Minutes Data 03h MINA Minutes Alarm Data 04h HOR Hours Data 05h HORA Hours Alarm Data 06h DOW Day-of-Week Data 07h DOM Date-of-Month Data 08h MON Month Data 09h YER Year Data 0Ah CRA Update in Progress 0Bh CRB SETMODE PIE AIE UIE 0Ch CRC IRQF PIF AIF UIF 0Dh CRD Valid RAM and Time Prog. DOMA Date-of-Month Alarm Data Prog. MONA Month Alarm Data Prog. CEN Century Data Divider Chain Control 1 0 Periodic Interrupt Rate Select Reserved DATMODE HRMODE DSVMODE Reserved Reserved 8.6 RTC GENERAL-PURPOSE RAM MAP Table 39. Standard RAM Map Index 0Eh - 7Fh1 Description Battery-backed General-purpose 111-byte RAM. 1. Battery-backed 111-byte RAM (114-3 overlaid registers). Table 40. Extended RAM Map Index 00h - 7Fh Description Battery-backed General-purpose 128-byte RAM. 159 www.national.com 9.0 System Wake-Up Control (SWC) 9.1 OVERVIEW The System Wake-Up Control supports the ACPI Specification, Revision 1.0b, Feb. 2, 1999. The SWC functional block receives external events from the system and internal events from the functional blocks of the PC8741x device. Using these events together with the ACPI sleep state information supplied by the software or by external signals, the SWC generates system interrupts (IRQ, SIOSMI) and Power Management signals (SIOSCI, ONCTL, PWBTOUT). In addition, it controls two LED indicators and contains two Power Active timers and a WATCHDOG Timer. The SWC receives the following external events: * * * * * Sixteen VSB-powered General-Purpose Input/Output events (GPIOE10-17 and GPIOE40-47). Two Modem Ring events (RI1 and RI2). Mouse movement and button pressing events (via MCLK and MDAT). Advanced key pressing events from the Keyboard (via KBCLK and KBDAT). Power and Sleep buttons pressing events (PWBTIN and SLBTIN). The SWC receives the following internal events: * * * RTC alarm event. * * WATCHDOG time-out event. Keyboard and Mouse interrupt event (IRQ). Module interrupt (IRQ) event from the Legacy functional blocks (FDC, Parallel Port and Serial Ports 1 and 2) and from the XIRQ pin (mapped to IRQ). Software VDD ON and VDD OFF requests. The SWC receives sleep state information either by software (writing the ACPI, SLP_TYPx and SLP_EN bits) or via the SLPS3 and SLPS5 pins from an external ACPI controller. In Legacy Power Button mode, the Power button can generate an S5 sleep state. The SWC implements three ACPI fixed register groups: PM1 Event Group (block b), PM1 Control Group (block b) and General-Purpose Event 1 Group. The unimplemented functions in the first two groups (block b) are supported by returning zero. The SWC generates the system interrupts, IRQ (via SERIRQ) and SMI (via SIOSMI), based on the external and internal events (except GPIOE events) and on the routing information written into its registers. GPIOE events, the exception, are routed to the IRQ and SMI by the GPIO functional block. The IRQ and SMI interrupts are independent of the sleep state. The SWC generates the Power Management signals (the ACPI interrupt--SIOSCI, the ONCTL signal for the VDD power supply control and the PWBTOUT signal, which is used by an external ACPI controller) based on the same external and internal events, on routing information and on the current sleep state. The ONCTL and PWBTOUT signals are enabled according to the current sleep state, based on information written into the SWC registers. In Legacy Power Button mode, ONCTL is controlled by the Power button external event. The ACPI-compatible SCI interrupt is independent of the current sleep state. Two functions bypass event routing by the sleep state mechanism and directly affect the ONCTL and PWBTOUT signals. These are: Power Button Override, which forces the VDD power supply off if the Power button is continuously pressed for more than four seconds. Crowbar, which releases the VDD Power On request if the VDD power supply refuses to turn on. In addition, the SWC controls two LED indicators. Control is based on the current sleep state information or on the status of the VSB and VDD power. The SWC also includes two Power Active timers that measure the time the VSB and VDD power supplies are active (ON). Another function included in the SWC is the WATCHDOG Timer. If the WATCHDOG is not retriggered by one of its event sources and reaches time-out, it generates an SMI (via SIOSMI) or an SCI (via SIOSCI) interrupt. In addition, the WATCHDOG generates a pulse at the WDO pin. The SWC contains two Power Management registers that allow the software to disable each Legacy module and to TRISTATE its outputs in a centralized manner. The SWC module is powered by the VPP plane (see Section 2.1 on page 31). However, during Power Fail state (i.e., when only VBAT is present), the module functions (event detection, output generation and time counting) are disabled and only the VPP-powered registers retain their data. Figure 47 shows the simplified block diagram of the SWC functional block. www.national.com 160 9.0 System Wake-Up Control (SWC) 1 Min. Clock (Continued) WATCHDOG WDO Interrupt Routing Control 31 Internal Events 7 External Events 24 SWC Event Status Debounce and Detection SCI Interrupt Enable Legacy Power Button SLP_TYPx SLP_EN 4 SPLS3 SLPS5 2 Power Button VDD, VSB Status SIOSMI SIOSCI Power Button S5 Sleep State Converter IRQ Current Sleep State Power Management Signals Enable 4 Sec. Override and Crowbar LED Control 2 ONCTL PWBTOUT LED1 LED2 Power Active Timers 1 Hz Clock Figure 47. SWC Block Diagram 9.2 FUNCTIONAL DESCRIPTION 9.2.1 External Events General-Purpose Input/Output Events The PC8741x devices support 16 VSB-powered General-Purpose Input/Output events through ports GPIOE10-17 and GPIOE40-47. VDD- and VSB-powered signals can be connected to the GPIO pins to become sources of external events. A VDD-powered signal used to generate an event is internally disabled (for event generation) while VDD power is off and also for 1 second after VDD power is restored. This prevents the detection of false events during power transitions and while the signal driver is unpowered. For the same reasons, a VSB-powered signal used to generate an event is enabled only 1 second after the VSB power is on. (When VSB is off, the whole SWC module is disabled.) Each GPIOE pin has programmable polarity and an optional 16 ms debouncer (see Figure 48). The debouncer is enabled after the reset but can be disabled by software. A GPIO event can generate the system interrupts (IRQ and SMI) if the event is enabled and routed to the specific interrupt. The status, event enable and pending event routing bits to IRQ and SMI are implemented in the GPIO Ports module (see Section 7.3 on page 136). The status bit is set when an event of the programmed type (edge or level) is detected. A GPIO event can also generate the Power Management signals (the SCI interrupt, the ONCTL power supply control and the PWBTOUT signal). The status, event enable and wake-up state enable bits are implemented in the SWC module (see Figures 48 and 50). 161 www.national.com 9.0 System Wake-Up Control (SWC) (Continued) An active level-type event sets the status bit in registers GPE1_STS_0 for ports GPIOE10-17 and GPE1_STS_1 for ports GPIOE40-47 (see Sections 9.4.8 and 9.4.9 on pages 208ff.). The status bit remains set even when the event becomes inactive. The status bit is cleared only when the software writes `1' to the bit. If the event is still active when software writes `1', the status bit remains set. After changing the GPIOExx pin multiplexing, clear the relevant bits in the GPE1_STS_0 and GPE1_STS_1 registers, to prevent false events (caused by the pin multiplexing switch) from generating a wake-up event. GPIO Status Routing Control IRQ SIOSMI Event Enable GPIO Ports Module GPIO Ports Module 0 Input Debouncer Set 1 SWC GPIO Status SWC GPIO Event Status Read Reset Pin Write 1 to Clear Bit 6 Event Debounce Enable Bit 5 Event Polarity Internal Bus GPIO Pin Configuration Register 1 (GPCFG1) Figure 48. GPIO Events Modem Ring Events High-to-low transitions on RI1 or RI2 indicate the detection of a ring signal by an external modem connected to Serial Port 1 or Serial Port 2, respectively. The transitions on RI1 and RI2 are detected by the RI Wake-up Detector powered by VSB, which works independently of the Serial Port 1 or Serial Port 2 modules (powered by VDD). A detected RI1 or RI2 transition sets the RI1_EVT_STS or RI2_EVT_STS status bits in the GPE1_STS_2 register (see Section 9.4.10 on page 209). A status bit is cleared only when the software writes `1' to it. The transition detection from RI1 and RI2 is enabled (for event generation) 1 second after the VSB power is on. This prevents the detection of false events during VSB power-On transitions. Mouse Wake-Up Event The mouse wake-up event is detected by the Keyboard/Mouse Wake-up Detector, which monitors the MCLK and MDAT signals. Since the detection mechanisms for keyboard and mouse events are independent, they can be operated simultaneously. Moreover, the Keyboard signals may be swapped with the Mouse signals by setting the SWAP_KBMS bit in the SWC_CTL register (see Section 9.3.10 on page 186). This bit must be set to the same value as the Swap bit in the KBC Configuration register (see Section 3.13.3 on page 68). The Keyboard/Mouse Wake-up Detector is powered by VSB and works independently of the Keyboard Controller module (powered by VDD). The mouse event detection mechanism can be programmed to detect either a mouse click or movement, a specific mouse click (left or right) or a double-click. To program which mouse action causes an event detection, set the MSEVCFG field in the PS2CTL register (see Section 9.3.17 on page 193) to the required value. A detected mouse event sets the MS_EVT_STS status bit in the GPE1_STS_2 register (see Section 9.4.10 on page 209). The status bit is cleared only when the software writes `1' to it. www.national.com 162 9.0 System Wake-Up Control (SWC) (Continued) The mouse event detection from MCLK and MDAT is enabled (for event generation) 1 second after the VSB power is on. This prevents the detection of false events during Mouse VSB power-On transitions. In addition, if the Keyboard/Mouse Power Control feature (see Section 9.2.10 on page 173) is enabled by setting the VDDFLMUX bit to `1' (in the SIOCF2 register - see Section 3.7.3 on page 49), mouse event detection is disabled for 2 seconds from the moment the VDD power is turned off. If this feature is disabled (VDDFLMUX = `0' in SIOCF2) mouse event detection is enabled regardless of the VDD power status; however, the wake-up becomes effective (VDD power is turned on) only 1 second after the VDD power was turned off. Keyboard Wake-Up Events Keyboard wake-up events are also detected by the Keyboard/Mouse Wake-up Detector, which monitors the KBCLK and KBDAT signals. Since the detection mechanisms for keyboard and mouse events are independent, they can be operated simultaneously. Moreover, the Keyboard signals may be swapped with the Mouse signals, as explained in the Mouse WakeUp Event section (page 162). The Keyboard/Mouse Wake-up Detector is powered by VSB and works independently of the Keyboard Controller module (powered by VDD). The keyboard event detection mechanism can be programmed to detect: Any keystroke (Special Key Sequence mode). A specific programmable sequence of up to eight alphanumeric keystrokes (Password mode). Any programmable sequence of up to eight bytes of data received from the keyboard (Special Key Sequence mode). Up to three programmable, Power Management keys concurrently available, each including a sequence of up to three bytes of data received from the keyboard (Power Management Key mode). The Keyboard/Mouse Wake-up Detector has three operation modes: Password mode. Special Key Sequence mode. Power Management Key mode. Up to eight Keyboard Data registers (PS2KEY0 to PS2KEY7) are used to define which keyboard data string generates an event. Since the same set of registers is used by each operation mode, only one mode can be selected at a time. In the modes involving more than one keystroke, the maximum delay allowed between pressing two consecutive keys is 4 seconds. A longer delay is interpreted by the Wake-up Detector as the beginning of a new sequence of keystrokes, which causes the present sequence to be discarded. In all operation modes, pressing a wrong key requires a recovery time of 4 seconds, before a new (correct) sequence may be recognized. Password Mode. In Password mode, the Make and Break bytes transmitted by the keyboard are discarded, and only the keystroke data bytes are compared with those programmed in the PS2KEY0 to PS2KEY7 registers. If the two sets are equal, a keyboard event that sets the KBD_EVT1_STS bit in the GPE1_STS_2 register is detected (see Section 9.4.10 on page 209). The status bit is cleared only when the software writes `1' to it. To simplify the detection mechanism, only keys with a keystroke data of one byte can be included in the sequence to be detected. To program the Keyboard/Mouse Wakeup Detector to operate in Password mode, proceed as follows: 1. Set KBDMODE bit in the KBDWKCTL register to `0' (see Section 9.3.16 on page 192). 2. Set KBEVCFG field in the PS2CTL register to a value that indicates the desired number of alphanumeric keystrokes in the sequence. The programmed value = the number of keystrokes + 7. For example, to detect a sequence of two keys, set KBEVCFG to 9h. 3. Program the appropriate subset of the PS2KEY0-PS2KEY7 registers in sequential order with the data bytes of the keys in the sequence. For example, if there are three keys in the sequence and the keystroke data of these keys are 05h (first), 50h (second) and 44h (third), program PS2KEY0 to 05h, PS2KEY1 to 50h and PS2KEY2 to 44h (the scan codes are only examples). Special Key Sequence Mode. In Special Key Sequence mode, all the bytes transmitted by the keyboard are compared with those programmed in the PS2KEY0 to PS2KEY7 registers. These include also the Make and Break bytes. If the two sets are equal, a keyboard event is detected, as explained in Password Mode, above. This mode enables the detection of any sequence of keystrokes, including keys as "Shift" and "Alt". To program the Keyboard/Mouse Wake-up Detector to operate in Special Key Sequence mode, proceed as follows: 1. Set KBDMODE bit in the KBDWKCTL register to `0' (see Section 9.3.16 on page 192). 2. Set KBEVCFG field in the PS2CTL register to a value that indicates the desired number of keystrokes in the sequence. The programmed value = the number of keystrokes + 1. For example, to detect a sequence of three received bytes (i.e., one keystroke), set KBEVCFG to 2h. 3. Program the appropriate subset of the PS2KEY0-PS2KEY7 registers in sequential order with the data bytes that comprise the sequence. For example, if the number of bytes in the sequence is four, and the values of these bytes are E0h (first), 5Bh (second), E0h (third) and DBh (fourth), program PS2KEY0 to E0h, PS2KEY1 to 5Bh, PS2KEY2 to E0h and PS2KEY3 to DBh (the byte values are only examples). 163 www.national.com 9.0 System Wake-Up Control (SWC) (Continued) Special Key Sequence mode also enables detection of a specific single keystroke. To program the Keyboard/Mouse Wakeup Detector to wake-up on a single keystroke, perform the following sequence: 1. Set KBDMODE bit in the KBDWKCTL register to `0' (see Section 9.3.16 on page 192). 2. Set KBEVCFG field in the PS2CTL register to 0001b. 3. Program the PS2KEY0 and PS2KEY1 registers to 00h. This forces the detector to ignore the values of incoming data, thus causing it to detect a keyboard event on the single keystroke. Power Management Mode. In Power Management Key mode, the PS2KEY0 to PS2KEY7 register bank is divided into three groups of registers: PS2KEY0 to PS2KEY2, PS2KEY3 to PS2KEY5 and PS2KEY6 to PS2KEY7. Each group can be programmed with different data bytes, allowing the bytes transmitted by the keyboard to be compared simultaneously with three keystroke sequences. If the bytes transmitted by the keyboard (including Make and Break) are equal to the data bytes in one register group, the related keyboard event is detected. The detection of Keyboard Event 1 (data in PS2KEY0PS2KEY2) sets the KBD_EVT1_STS bit, the detection of Keyboard Event 2 (data in PS2KEY3-PS2KEY5) sets the KBD_EVT2_STS bit and the detection of Keyboard Event 3 (data in PS2KEY6-PS2KEY7) sets the KBD_EVT3_STS bit. All three status bits are in the GPE1_STS_2 register (see Section 9.4.10 on page 209). Each status bit is cleared only when the software writes `1' to the bit. This mode enables the detection of any sequence of keys. Note: Do not use a byte sequence that is a "subset" of the byte sequence of another ("superset") Power Management key event. (The subset sequence has fewer bytes (set by the EVTxCFG fields in the KBDWKCTL register) than the superset sequence; the bytes contained in the subset sequence (as programed in the PS2KEY0 to PS2KEY7 registers) are identical to the respective bytes of the superset sequence.) To program the Keyboard/Mouse Wake-up Detector to operate in Power Management Key mode, proceed as follows: 1. Set KBDMODE bit in the KBDWKCTL register to `1' (see Section 9.3.16 on page 192). 2. Set each event configuration field (EVT1CFG, EVT2CFG and EVT3CFG) in the KBDWKCTL register to a value that indicates the desired number of keystroke data bytes in the sequence, for each event. For example, to detect a sequence of two received bytes, set EVTxCFG to 2h. 3. Program each group of the PS2KEY0-PS2KEY7 registers in sequential order with the data bytes of the keys in the sequence for each event. Event Generation. Keyboard event detection from KBCLK and KBDAT is enabled (for event generation) 1 second after the VSB power is on. This prevents the detection of false events during Keyboard VSB power-On transitions. In addition, if the Keyboard/Mouse Power Control feature (see Section 9.2.10 on page 173) is enabled by setting the VDDFLMUX bit to `1' (in the SIOCF2 register; see Section 3.7.3 on page 49), keyboard event detection is disabled for 2 seconds from the moment the VDD power is turned off. If this feature is disabled (VDDFLMUX = `0' in SIOCF2) keyboard event detection is enabled regardless of the VDD power status; however, the wake-up becomes effective (VDD power is turned on) only 1 second after the VDD power was turned off. Power Button Event A low level signal at PWBTIN indicates that the Power button was pressed. This input, filtered by a 16 ms debouncer, is bridged to the PWBTOUT output to synchronize an external ACPI controller (which is optional). A detected low level signal sets the PWRBTN_STS status bit in the PM1b_STS_HIGH register (see Section 9.4.3 on page 204) and the PWBT_EVT_STS status bit in the GPE1_STS_2 register (see Section 9.4.10 on page 209). Note, however, that the PWRBTN_STS status bit is not set if the PWRBTN_EV_DIS bit in the ACPI_CFG register is reset (see Section 9.3.32 on page 200). This functionality is required for ACPI compatibility in case the Power button event is implemented in an (optional) external ACPI controller. Both status bits are cleared when the software writes `1' to any of them. If a low level is present at the input when software writes `1' to the status bit, the status bit remains set. The low level detection from PWBTIN is enabled (for event generation) 1 second after the VSB power is on. This prevents the detection of false events during VSB power-On transitions. The Power button event is always enabled for wake-up in any sleep state. In addition, the Power button event is the only wake-up event available after a Power Button Override or a Crowbar condition (see Section 9.2.6 on page 170). In Legacy Power Button mode (LEGACY_PWBT = 1 in the PWONCTL register - see Section 9.3.11 on page 187), a lowlevel signal at PWBTIN, when the VDD power is on, generates an S45 current sleep state (see Section 9.2.3 on page 166), which sets ONCTL to Off. In addition, the PWRBTN_STS and the PWBT_EVT_STS status bits are reset in this situation. In this mode, the Power button event is the only wake-up event available after ONCTL is turned off. Sleep Button Event A low level on SLBTIN indicates the Sleep button was pressed. This input is also filtered by a 16 ms debouncer. A detected low level sets the SLPBTN_STS status bit in the PM1b_STS_HIGH register (see Section 9.4.3 on page 204) and the SLBT_EVT_STS status bit in the GPE1_STS_2 register (see Section 9.4.10 on page 209). Note, however, that the SLPBTN_STS status bit is not set if the SLPBTN_EV_DIS bit in the ACPI_CFG register is reset (see Section 9.3.32 on page 200). This functionality is required for ACPI compatibility in case the Sleep Button event is implemented in an (optional) external ACPI controller. Both status bits are cleared when the software writes `1' to either of them. If a low level is present at the input when software writes `1' to the status bit, the status bit remains set. www.national.com 164 9.0 System Wake-Up Control (SWC) (Continued) The low level detection from SLBTIN is enabled (for event generation) 1 second after the VSB power is on. This prevents the detection of false events during VSB power-On transitions. 9.2.2 Internal Events RTC Alarm Event An RTC Alarm event is generated by the RTC functional block. An asserted RTC Alarm sets the RTC_STS status bit in the PM1b_STS_HIGH register (see Section 9.4.3 on page 204) and the RTC_EVT_STS status bit in the GPE1_STS_3 register (see Section 9.4.11 on page 210). Note, however, that the RTC_STS status bit is not set if the RTC_EV_DIS bit in the ACPI_CFG register (see Section 9.3.32 on page 200) is reset. This functionality is required for ACPI compatibility in case the RTC Alarm event is implemented in an (optional) external ACPI controller. Both status bits are cleared when the software writes `1' to any of them. If the RTC Alarm is asserted when software writes `1' to the status bit, the status bit remains set. KBC P12 Event A KBC P12 event is detected when the P12 port of the Keyboard Controller (KBC) functional block is set to `1'. For this to happen, the KBC module must be enabled (see Section 3.3.1 on page 42). Since the Keyboard Controller functional block is powered by VDD, a P12 event can occur only when VDD is present. A high level at the P12 port of the KBC sets the P12_EVT_STS status bit in the GPE1_STS_3 register (see Section 9.4.11 on page 210). The status bit is cleared only when the software writes `1' to it. If the P12 port is at high level when software writes `1' to the status bit, the status bit remains set. Keyboard and Mouse IRQ Events Keyboard and Mouse IRQ events are detected when either the Keyboard IRQ or Mouse IRQ is asserted. To enable the IRQ of a logical device to generate an IRQ event, the associated Enable bit (bit 4 of the configuration register at index 70h; see Section 3.2.3 on page 39) must be set to `1'. Since the Keyboard Controller (KBC) functional block is powered by VDD, a Keyboard or Mouse IRQ event can occur only when VDD is present. An active (level-type) Keyboard IRQ event sets the KBD_IRQ_STS status bit and an active Mouse IRQ event sets the MS_IRQ_STS status bit. Both status bits are in the GPE1_STS_3 register (see Section 9.4.11 on page 210). A status bit is cleared only when the software writes `1' to it. If the IRQ event is active when software writes `1' to the status bit, the status bit remains set. The ROM code used for the Keyboard Controller generates active high Keyboard and Mouse interrupts, used by the SWC module. Module IRQ Event A Module IRQ event is detected when one of the Legacy modules (FDC, Parallel Port, Serial Port 1 or 2) asserts its IRQ or when an active level is detected at the XIRQ pin (PC87416 and PC87417). To enable the IRQ of a logical device to generate an IRQ event, the associated Enable bit (bit 4 of the configuration register at index 70h - see Section 3.2.3 on page 39) must be set to `1'. Since the Legacy modules are powered by VDD, they can assert IRQ only when VDD is present. To enable an active level at the XIRQ pin (PC87416 and PC87417) to generate an event, both the IRQEN and the PWUREN bits in the XIRQC register (see Section 5.4.4 on page 109) must be set to `1'. Since the XIRQ interrupt belongs to the X-Bus Extension functional block powered by VSB, an active level at the XIRQ pin can also generate a Module IRQ event when VDD is off. The XIRQ detection enabled (for event generation) 1 second after the VSB power is on. This prevents the detection of false events during VSB power-On transitions. The MOD_IRQ_STS status bit in the GPE1_STS_3 register is set by an IRQ that is asserted by one of the Legacy modules or by an active level at the XIRQ pin (see Section 9.4.11 on page 210). The status bit is cleared only when the software writes `1' to it. If the Module IRQ event is active when software writes `1' to the status bit, the status bit remains set. WATCHDOG Time-Out Event A WATCHDOG time-out event is generated by the WATCHDOG function in the SWC module (see Section 9.2.9 on page 173). An asserted WATCHDOG event sets the WDO_EVT_STS status bit in the GPE1_STS_3 register (see Section 9.4.11 on page 210). A status bit is cleared only when the software writes `1' to it. If the WATCHDOG event is asserted when software writes `1' to the status bit, the status bit remains set. Software Power ON/OFF Events A Software Power event is triggered when software writes `1' to the SW_ON_CTL bit (for Power ON) or to the SW_OFF_CTL bit (for Power OFF). After being written `1', these bits automatically return to their default value of `0'. Both bits are located in the SWC_CTL register (see Section 9.3.10 on page 186). If the VDD power is not preset, these two bits can be written `1' through the ACCESS.bus (PC87413 and PC87417), which is powered by VSB. 165 www.national.com 9.0 System Wake-Up Control (SWC) (Continued) A Software Power ON event sets the SW_ON_STS status bit and a Software Power OFF event sets the SW_OFF_STS status bit. Both bits are in the GPE1_STS_3 register (see Section 9.4.11 on page 210). A status bit is cleared only when the software writes `1' to it. 9.2.3 Sleep States Compliance with ACPI Specification, Revision 1.0b, Feb. 2, 1999 requires the PC8741x devices to recognize the six system states: Working (G0/S0), Sleeping (G1-S1 to G1-S4) and Soft-off (G2/S5). The system state is written by the host into the SLP_TYPx field of the PM1b_CNT_HIGH register (see Section 9.4.7 on page 207) and updated by writing a `1' to the SLP_EN bit in the same register. The value written in the SLP_TYPx field is translated to one of the internal states (S0 to S5), using the data programmed in the Sleep Type Encoding registers. This translation mechanism allows the software to use any SLP_TYPx encoding scheme. Each of the six Sleep Type Encoding registers (S0_SLP_TYP to S5_SLP_TYP; see Section 9.3.30 on page 198) contains a 3-bit SLP_ENC_TYP field. The software must program this field with the SLP_TYPx code used for the internal state represented by the register. The software must program all six registers even if not all the system states are supported. The SWC uses three current sleep states to control its operation. The six decoded internal states are converted to the current sleep states as follows (see Section 9.2.5 for the usage of the current sleep states): S0, S1 and S2 are converted to the S12 current state; this is the active state for the PC8741x device, with VDD and VSB power supplies being ON. S3 is converted to the S3I current state; in this sleep state the VSB power is ON but the VDD power supply can be ON or OFF, according to the setting of the S3I_VDD_ON bit in the SLP_ST_CFG register (see Section 9.3.31 on page 199). S4 is converted to either S3I or S45 current states, according to the setting of the S4_SELECT bit in the SLP_ST_CFG register (see Section 9.3.31 on page 199). S5 is converted to the S45 current state; in this sleep state, the VSB power is ON but the VDD power supply is OFF. If an active (optional) ACPI controller is located in an external device, the SLPS3 and SLPS5 signals are used to determine the system sleep state. This option is selected by setting both the EXTSTMUX bit in the SIOCF3 register (see Section 3.7.4 on page 50) and the EXT_ST_SELECT bit in the SLP_ST_CFG register (see Section 9.3.31 on page 199) to `1'. Table 41 shows how the levels of the SLPS3 and SLPS5 signals are converted to current sleep states. Table 41. SLPS3, SLPS5 Conversion to Current Sleep States SLPS3 SLPS5 Current Sleep State 1 1 S12 0 1 S3I 0 0 S45 1 0 Reserved Note: The internal and external sleep state modes are mutually exclusive. The internal sleep state register (PM1b_CNT_HIGH) should not be used when external sleep state mode is selected. Similarly, pins SLPS3 and SLPS5 should not be used when internal sleep state mode is selected. The use of the external SLPS3 and SLPS5 signals to determine the current sleep state is enabled 1 second after the VSB power is on. This prevents the selection of an erroneous current sleep state during VSB power-On transitions. In Legacy Power Button mode, when the VDD power is on, an S45 current state is generated by a low-level signal at PWBTIN. 9.2.4 Interrupt Signals The SWC generates three system interrupts: IRQ (via SERIRQ), SMI (via SIOSMI) and SCI (via SIOSCI). The IRQ and SMI interrupts are not related to the ACPI-compatible system control but are based on the external and internal events, each with its status and enable bit in the SWC module. However, the status and enable bits for the GPIOE events (GPIOE10-17 and GPIOE40-47) related to IRQ and SMI generation are located in the GPIO functional block (see Section 7.3 on page 136). SCI is the Power Management interrupt defined by ACPI. Its status and enable bits are all located in the SWC module. www.national.com 166 9.0 System Wake-Up Control (SWC) (Continued) IRQ Interrupt The external and internal events processed by the SWC for IRQ generation set a status bit in the GPE1_STS_2 and GPE1_STS_3 registers. Only those events that are allowed to be routed to the IRQ interrupt by the SWC have an associated enable bit in the GPE1_2IRQ_LOW and GPE1_2IRQ_HIGH registers (see Sections 9.3.4 and 9.3.5 on pages180ff.). When an enable bit is set, and if the corresponding status bit is set, an active IRQ is generated. The IRQ interrupt is independent of the system sleep state. SMI Interrupt The external and internal events processed by the SWC for SMI generation set a status bit in the GPE1_STS_2 and GPE1_STS_3 registers. Only those events that are allowed to be routed to the SMI interrupt by the SWC have an associated enable bit in the GPE1_2SMI_LOW and GPE1_2SMI_HIGH registers (see Sections 9.3.6 and 9.3.7 on pages 182ff.). When an enable bit is set, and if the corresponding status bit is set, an active SMI is generated. The SMI interrupt is independent of the system sleep state. SCI Interrupt All external and internal events (including GPIOE) are exclusively processed by the SWC to generate the Power Management interrupt, SCI. Each active event sets a status bit in the GPE1_STS_0 to GPE1_STS_3 registers. Three events, the Power button event, the Sleep button event and the RTC event each have an additional status bit in the PM1b_STS_HIGH register (PWRBTN_STS, SLPBTN_STS and RTC_STS bits, respectively). Each of the additional status bits is set only if the PC8741x device is assigned the specific function by the ACPI software (see Sections 9.2.1 and 9.2.2 on pages 161ff.). For each status bit, the SWC holds an enable bit in the GPE1_EN_0 to GPE1_EN_3 registers (see Sections 9.4.12 to 9.4.15 on pages 212ff.). A set status bit can cause the assertion of the SCI interrupt only when an enable bit is set. Each of the three events mentioned in the previous paragraph also has additional enable bits in the PM1b_EN_HIGH register (see Section 9.4.5 on page 206). Each additional enable and status bit is reset if the respective bit (PWRBTN_EV_DIS, SLPBTN_EV_DIS or RTC_EV_DIS) in the ACPI_CFG register is reset (see Section 9.3.32 on page 200). This "dual control" behavior is required for ACPI compatibility in case one of these events is implemented in an (optional) external ACPI controller. An SCI from one of these dual control functions is generated if at least one enabled status bit (of the pair) is set. The SCI interrupt is independent of the system sleep state with one exception, the Power button event. When the system is in a sleep state (S1-S5), a set PWRBTN_STS bit generates an active SCI regardless of the value of the PWRBTN_EN bit. S0 can be separated from the sleep states (S1-S5) only when the PC8741x device serves as an ACPI controller and the software writes the system state (SLP_TYPx) in the PM1b_CNT_HIGH register. The bypass of the PWRBTN_EN bit during sleep states (i.e., a set PWRBTN_STS bit generates SCI regardless of the PWRBTN_EN bit) is therefore available only if the EXT_ST_SELECT bit in the SLP_ST_CFG register is reset (see Section 9.3.31 on page 199). When the SCI interrupt is asserted and the system is in a sleep state (S1-S5), the WAK_STS bit of the PM1b_STS_HIGH register is set. This feature, too, is available only if the EXT_ST_SELECT bit in the SLP_ST_CFG register is reset (the ACPI controller is implemented by the PC8741x device). Figure 49 shows the SCI generation by the dual control functions and the behavior of the Power button event as a function of the sleep state. 167 www.national.com 9.0 System Wake-Up Control (SWC) (Continued) GPE1_STS_2/3 Status Set Detected Event Enable SCI Interrupt GPE1_STS_2/3 Only for Power Button Event State S0 PM1b_STS_HIGH 0 Status 1 Set Reset From Other Enabled Events Enable ACPI_CFG Reset PM1b_EN_HIGH Disable Figure 49. Dual Control Functions 9.2.5 Power Management Signals The SWC generates two Power Management signals: ONCTL, for the VDD power supply control, and PWBTOUT, which is used by an external ACPI controller. These signals are based on the external and internal events, each with its status and enable bits in the SWC module (including GPIOE). ONCTL and the PWBTOUT are generated according to the current sleep state. Special Power Management functions, either required by the ACPI Specification or inherited from the Legacy Power Management, also affect the ONCTL and PWBTOUT outputs. These functions are described in Section 9.2.6. Power Supply Control (ONCTL) Each active external or internal event (including GPIOE) sets a status bit in the GPE1_STS_0 to GPE1_STS_3 registers. Three events (Power button, Sleep button and RTC alarm) each have an additional status bit in the PM1b_STS_HIGH register. Their behavior is described in the SCI Interrupt section (page 167). ONCTL generation is independent of the enable bits in the GPE1_EN_0 to GPE1_EN_3 registers. It is also independent of the three additional enable bits in the PM1b_EN_HIGH register (for Power button, Sleep button and RTC alarm events). ONCTL is not affected by the WATCHDOG status bit (WDO_EVT_STS). ONCTL is turned OFF (inactive: ONCTL = high level) according to the current sleep states, S3I and S45 (S12 is the active state for the PC8741x device and does not influence ONCTL; see Section 9.2.3 on page 166). These current sleep states are decoded from the value of the SLP_TYPx field of the PM1b_CNT_HIGH register (for EXT_ST_SELECT = 0 in the SLP_ST_CFG register) or from the levels of the SLPS3 and SLPS5 signals (for EXT_ST_SELECT = 1 in the SLP_ST_CFG register and EXTSTMUX = 1 in the SIOCF3 register). In Legacy Power button mode, when the VDD power is on, an S45 current state is generated by a low-level signal at PWBTIN, overriding the decoded sleep states. When the PC8741x device enters the S45 state, it turns the VDD power supply OFF by setting ONCTL = 1. The state of the VDD power supply (ON or OFF) in S3I state depends on the setting of the S3I_VDD_ON bit in the SLP_ST_CFG register (see Section 9.3.31 on page 199). If the PC8741x device is the ACPI controller of the system (EXT_ST_SELECT = 0 in the SLP_ST_CFG register), ONCTL is turned ON by an active wake-up event. This is possible only if the event is enabled for wake-up (in the WK_ST_EN register) in the current sleep state. Each external or internal event has its own Wake-Up State Enable register (WK_ST_EN), which is accessed by the software writing its index value (see Table 48 on page 178) into the WKUPSEL field of the Wake-Up Event Select register (WK_EVT_SEL - see Section 9.3.2). The currently accessed WK_ST_EN register selects the current sleep states for which www.national.com 168 9.0 System Wake-Up Control (SWC) (Continued) the related event generates a wake-up (i.e., it turns the VDD power supply ON by setting ONCTL = 0). The ONCTL_EN_S3I and ONCTL_EN_S45 bits enable or disable wake-up by the event when the PC8741x device is in S3I or in S45 current state, respectively. Only two events lack a Wake-Up State Enable register (WK_ST_EN). These are: -- The WATCHDOG event (flagged by the WDO_EVT_STS bit): this event does not affect ONCTL generation. -- The Power button event (flagged by either the PWBT_EVT_STS bit or the PWRBTN_STS bit): this event unconditionally generates a wake-up (sets ONCTL = 0) when the PC8741x device is in S3I or S45 current states. In addition, in Legacy Power Button mode (LEGACY_PWBT = 1 in the PWONCTL register), all wake-up events are ignored (regardless of the bit value in their WK_ST_EN register) after the power supply has been turned OFF (by setting ONCTL = 1) in response to a Power button event. In this case, the next Power button event unconditionally generates a wake-up (sets ONCTL = 0). Optionally, the system ACPI controller can be located in an external device. To select this option, both the EXT_ST_SELECT bit in the SLP_ST_CFG register (see Section 9.3.31 on page 199) and the EXTSTMUX bit in the SIOCF3 register (see Section 3.7.4 on page 50) must be set to `1'. In this case, ONCTL is turned ON when the SLPS3 signal goes high (the system is in S0 - S2 states). In this mode, ONCTL is independent of any wake-up event, including the Power button event (flagged by either the PWBT_EVT_STS bit or the PWRBTN_STS bit). Any valid wake-up event is disabled from reactivating the VDD power supply (by setting ONCTL = 0) for 1 second after the power supply has been turned OFF (by setting ONCTL = 1). This feature protects the power supply from repeated on/off switching if an event (such as Power button) is active for an extended period of time. If the Keyboard/Mouse Power Control feature (VDDFELL; see Section 9.2.10 on page 173) is enabled by setting the VDDFLMUX bit to `1' (in the SIOCF2 register; see Section 3.7.3 on page 49), the Keyboard and Mouse wake-up events are disabled from reactivating the VDD for 2 seconds after the power supply has been turned OFF (by setting ONCTL = 1). S3I_ VDD_ON Power Button Override Crowbar State S3I State S45 SLPS5 EXT_ST_ SELECT OFF Reset SLPS3 GPE1_STS_0-3 Detected Status Event Set (one of 31 events) 1 Second Pulse ONCTL Set State S45 1 ONCTL_ EN_S45 0 State S3I ONCTL_ EN_S3I ON Resume from Power Fail From Other Enabled Events Figure 50. ONCTL Control Power Button Output (PWBTOUT) The PWBTOUT function of the PC8741x device enables the (optional) external ACPI controller to synchronize its operation to the wake-up events detected by the PC8741x device and to control the VDD power supply. The Power button input (PWBTIN) is bridged to PWBTOUT regardless of any PC8741x device configuration bits, internal state or wake-up event. This bridging is also independent of the status of the VDD power supply. In addition, a wake-up mechanism can be enabled to trigger a 100 ms pulse at the PWBTOUT output on each valid wakeup event. This wake-up mechanism is routed to the PWBTOUT pulse generator only if the PWBTOUT_MODE bit in the ACPI_CFG register (see Section 9.3.32 on page 200) is reset. 169 www.national.com 9.0 System Wake-Up Control (SWC) (Continued) The PWBTOUT wake-up mechanism is similar to the one described for the ONCTL signal, as follows: It is based on status bits in the GPE1_STS_0 to GPE1_STS_3 registers and in the PM1b_STS_HIGH register (except the PWBT_EVT_STS and the PWRBTN_STS bits). It is not affected by the WATCHDOG status bit (WDO_EVT_STS). It is independent of the enable bits in the GPE1_EN_0 to GPE1_EN_3 registers and in the PM1b_EN_HIGH register. It is dependent only on the S3I and S45 current sleep states. Its configuration bits are also located in the WK_ST_EN register, which is accessed by writing the event index value into the WKUPSEL field of the WK_EVT_SEL register. The PWBT_EN_S3I and PWBT_EN_S45 bits control the generation of a wake-up pulse on PWBTOUT by an active event (currently accessed through the WK_EVT_SEL register) when the PC8741x device is in S3I or in S45 current state, respectively. Any valid wake-up event is disabled from generating a wake-up pulse on PWBTOUT for 1 second after the power supply has been turned OFF (by setting ONCTL = 1). If the Keyboard/Mouse Power Control feature (VDDFELL) is enabled by setting the VDDFLMUX bit to `1' (in the SIOCF2 register; see Section 3.7.3 on page 49), the Keyboard and Mouse wake-up events are disabled from generating a wake-up pulse for 2 seconds after the power supply has been turned OFF (by setting ONCTL = 1). A PWBTOUT pulse is generated only when the VDD power is not present or when a PWBTIN pulse occurred. PWBTIN PWBTIN Status Set OFF State S45 GPE1_STS_0-3 Detected Event (one of 30 events; PWBTN is separate) Resume from Power Fail 1 Second Pulse No_Vdd Status Set PWBT_ EN_S45 PWBTOUT 100 ms Pulse State S3I PWBTOUT _MODE PWBT_ EN_S3I From Other Enabled Events 4s Pulse Crowbar Figure 51. PWBTOUT Control 9.2.6 Special Power Management Functions Three special Power Management functions are provided by the PC8741x device to respond to abnormal system behavior. These are: Power Button Override, which forces the VDD power supply to be turned OFF when the software does not respond to the SCI interrupt. Crowbar, which forces the ONCTL to release the ON request, thus protecting an overloaded VDD power supply that refuses to turn on. Resume from Power Fail, which enables a system to return to a predetermined state when returning from Power Fail (caused by the mechanical switch or by AC power failure). These functions bypass the mechanisms described in Section 9.2.5 and thus directly control the ONCTL and PWBTOUT outputs. www.national.com 170 9.0 System Wake-Up Control (SWC) (Continued) Power Button Override Whenever the Power button (PWBTIN) is pressed continuously for more than 3.9 seconds, the PC8741x device detects a Power Button Override condition. The Power button pressing at PWBTIN is replicated at PWBTOUT during these 3.9 seconds. PWBTOUT is then forced active for 0.2 seconds regardless of the actual level at PWBTIN. Thus, the pulse generated at PWBTOUT has a width of minimum 4.1 seconds, allowing an (optional) external ACPI controller to detect this Power Button Override condition. In addition, at the end of the 4.1 seconds, ONCTL is forced to inactive level (VDD power supply OFF). A Power Button Override condition also resets the PWRBTN_STS bit in the PM1b_STS_HIGH register (set by the Power button event) and updates the current sleep state of the PC8741x device to S45 (since the software is not capable of doing it). In addition, it sets the PWR_OVR_STS bit in the SWC_CTL register. This function bypasses the regular control on the ONCTL and PWBTOUT signals (see Figures 50 and 51). After a Power Button Override condition, only an active Power button event is allowed to wake-up the system (by setting ONCTL = 0 and generating a PWBTOUT pulse). However, in order to protect the power supply, ONCTL can go active (ONCTL = 0) only 1 second after the power supply has been turned OFF (by setting ONCTL = 1). In Legacy Power Button mode, when the VDD power is on, pressing the Power button (PWBTIN) forces ONCTL to inactive level (VDD power supply OFF) before a Power Button Override condition is detected. In this case, the PWR_OVR_STS bit is not set. Crowbar When a valid wake-up event or a high SLPS3 signal activates the VDD power supply (by setting ONCTL = 0), the PC8741x device starts checking the presence of the VDD power. If the VDD power fails to resume for a time period longer than the Crowbar timeout, the power-on request is aborted (by setting ONCTL = 1). Crowbar timeout is also started if the VDD power falls while the VDD power supply is ON (ONCTL = 0). If the VDD power fails to resume before the timeout period expired, the VDD power supply is turned OFF (by setting ONCTL = 1). After turning the VDD power supply OFF (by setting ONCTL = 1), a 4 sec pulse is generated at the PWBTOUT output. This pulse informs an (optional) external ACPI controller of the occurrence of the Crowbar timeout by simulating a Power Button Override condition. This function bypasses the regular control of the ONCTL and PWBTOUT signals (see Figures 50 and 51). The Crowbar timeout value is selected by the CRBAR_TOUT field in the PWONCTL register (see Section 9.3.11 on page 187). The equivalent timeout is in the range of 0.5 to 20 seconds (the default value is 20 seconds). When a Crowbar event is detected, the CROWBAR_STS bit in the SWC_CTL register (see Section 9.3.10 on page 186) is set. Only an active Power button event is allowed to retry the activation of the VDD power supply (by setting ONCTL = 0). However, no retry can take place for 5 seconds after the VDD power supply was turned OFF (by setting ONCTL = 1) because all wakeup events (including Power button) are disabled for 1 second after the end of the PWBTOUT pulse. Resume from Power Fail Whenever a Power Fail condition is detected (i.e., when VDD and VSB power supplies are off), the value of the ONCTL signal is saved in the LAST_ONCTL bit of the PWONCTL register (see Section 9.3.11 on page 187). When the system exits Power Fail (i.e., when VSB power is back on), this read-only bit serves as a snapshot of the VDD power supply status before the power was turned off (by an external agent, such as a mechanical switch). The WAS_PFAIL bit in the PWONCTL register is set by VSB Power-Up reset (the system exits Power Fail), thus indicating that a Resume from Power Fail condition occurred. This indication is used by the software to decide if the system woke up from Power Fail or from a sleep state. The Resume from Power Fail process starts 1 second after the VSB power is on. This prevents the selection of an erroneous current sleep state during VSB power-On transitions. The RESUME_MD field in the PWONCTL register controls the behavior of the ONCTL and PWBTOUT signals during a Resume from Power Fail condition (see Table 49 on page 188): * 00b - The state of the ONCTL and PWBTOUT signals is controlled solely by the SLPS3 input generated by an (optional) external ACPI controller. If the sleep state control by SLPS3, SLPS5 option is selected by setting both the EXT_ST_SELECT bit in the SLP_ST_CFG register and the EXTSTMUX bit in the SIOCF3 register to `1', and if SLPS3 = 1 (no sleep), the VDD power supply is turned on (ONCTL = 0). Otherwise, the VDD power supply remains off. Whenever ONCTL is asserted, a 100 ms pulse is also generated at the PWBTOUT output to inform an (optional) external ACPI controller of the new status of the VDD power supply. If the SLPS3, SLPS5 option is not selected (EXT_ST_SELECT bit in the SLP_ST_CFG register and EXTSTMUX bit in the SIOCF3 register are both `0'), the VDD power supply remains off ("Silent mode"). * 01b - The PC8741x device behaves the same as in the 00b combination. In addition, if an RTC Alarm event was active during the Power Fail, the VDD power supply is turned on (ONCTL = 0) and 171 www.national.com 9.0 System Wake-Up Control (SWC) (Continued) a 100 ms pulse is generated at the PWBTOUT output. This happens regardless of the setting of the EXT_ST_SELECT and EXTSTMUX bits or of the value of the SLPS3 input. * 10b - The state of the ONCTL and PWBTOUT signals is controlled solely by the LAST_ONCTL bit of the PWONCTL register regardless of the setting of the EXT_ST_SELECT and EXTSTMUX bits. If LAST_ONCTL = 1 (VDD power was on before Power Fail), the VDD power supply is turned on (ONCTL = 0) and a 100 ms pulse is generated at the PWBTOUT output. Otherwise, the VDD power supply remains off. * 11b - The PC8741x device behaves the same as in the 10b combination. In addition, if an RTC Alarm event was active during the Power Fail, the VDD power supply is turned on (ONCTL = 0) and a 100 ms pulse is generated at the PWBTOUT output. This happens regardless of the value of the LAST_ONCTL bit of the PWONCTL register. The Resume from Power Fail function bypasses the regular control on the ONCTL and PWBTOUT signals. After the Resume from Power Fail process ends, the ONCTL and PWBTOUT signals behave as described in Section 9.2.5 and in the Power Button Override and Crowbar sections (page 171). 9.2.7 LED Control The PC8741x devices support LED indicators for two purposes: Visual indication of the system power state or sleep state. General-purpose visual indication of the software status. The LEDCFG bit selects the configuration of the LED connection. There are two possible configurations: two regular LEDs are connected between each pin and ground or VSB (one at LED1 and the other at LED2 pins) or one dual-color LED is connected between the LED1 and LED2 pins. The LEDPOL bit selects the polarity of the ON state at both pins (LED1 and LED2). The LEDCFG and LEDPOL bits are located in the LEDCTL register (see Section 9.3.12 on page 189). The polarity of the ON state at LED1 and LED2 pins depends on the setting of the LEDCFG and LEDPOL bits (see Table ). Table 42. LED ON Polarity as a Function of LEDCFG and LEDPOL LEDCFG LEDPOL LED1 LED2 Connection 0 0 High Low LED1 to LED2 0 1 Low High LED2 to LED1 1 0 High High LED1 and LED2 to GND 1 1 Low Low LED1 and LED2 to VSB The LED1BLNK and LED2BLNK fields in the LEDBLNK register control the ON/OFF state or the blinking rate of the LED1 and LED2 pins, respectively. For each LED pin, a different blink rate can be selected. Different blink rates can also be selected for the dual-color LED mode (LEDCFG = 0). The LEDMOD field in the LEDCTL register controls the behavior of the LED1 and LED2 pins in each power state or sleep state (see Table 50 on page 189): * 00b - The behavior of the LED1 and LED2 pins is controlled by software only (through the setting of the LED1BLNK and LED2BLNK fields), except for the Power Fail state (VSB and VDD off) when both LEDs are OFF. * 01b - The behavior of the LED1 and LED2 pins is controlled by the power states and by software. In the Power Fail state (VSB and VDD off), both LEDs are OFF; In the Power Off state (VSB on and VDD off), both LEDs blink at a 1 Hz rate, with a 50% duty cycle; In the Power On state (VSB and VDD on), each LED behaves according to the setting of its LEDxBLNK field. * 10b - The behavior of the LED1 and LED2 pins is controlled by the S3I sleep state and by software. In the Power Fail state (VSB and VDD off) and in the S45 sleep state, both LEDs are OFF; In the Power On state (VSB and VDD on) and in the S3I sleep state, each LED behaves according to the setting of its LEDxBLNK field. * 11b - The behavior of the LED1 and LED2 pins is controlled by the sleep states and by software. In the Power Fail state (VSB and VDD off), both LEDs are OFF; In the Power On state (VSB and VDD on) and in the S45 and S3I sleep states, each LED behaves according to the setting of its LEDxBLNK field. www.national.com 172 9.0 System Wake-Up Control (SWC) 9.2.8 (Continued) Power Active Timers The SWC includes two 32-bit Power Active timers: a VDD Active Timer, and a VSB Active Timer. Each timer is clocked by a 1 Hz internal clock derived from the battery-backed 32.768 kHz crystal clock generator. These timers measure the cumulative amount of time (in seconds) that the VSB and the VDD power supplies are active (ON). Each of them is enabled for counting when its related power supply is turned on and stops counting when the power supply goes off. Due to their 32-bit length, the timers do not need to be reset; however, a reset bit is available for each timer (VSB_TMR_RST and VDD_TMR_RST) in the PWTMRCTL register (see Section 9.3.29 on page 198). The timer count data of the VDD Active Timer is available to the software in the VDD_ON_TMR_0 to VDD_ON_TMR_3 readonly registers (see Sections 9.3.21 to 9.3.24 on pages 195ff.), which are updated each second with the actual count value of the timer. When VDD_ON_TMR_0 (the LSByte of the count data) is read, the updating of all four registers (VDD_ON_TMR_0 to VDD_ON_TMR_3) is stopped, freezing the count value. The VDD_ON_TMR_1 and VDD_ON_TMR_2 registers can then be read in any order. Finally, reading from the VDD_ON_TMR_3 register resumes the registers updating with the actual count value of the timer. Therefore, the VDD_ON_TMR_0 register must be read first and the VDD_ON_TMR_3 register last. The same applies for the VSB Active Timer, whose timer count data is available to the software in the VSB_ON_TMR_0 to VSB_ON_TMR_3 read-only registers (see Sections 9.3.25 to 9.3.28 on pages 196ff.). 9.2.9 WATCHDOG Function The WATCHDOG includes an 8-bit timer clocked by a 1-minute internal clock that is derived from the battery-backed 32.768 KHz crystal clock generator. The timer is loaded with the WATCHDOG Time-Out Data value written in the WDTO register (see Section 9.3.34 on page 201) and counts down to zero. This 8-bit data enables time-out values between 1 to 255 minutes to be programmed (00h is an invalid data value). Five events can trigger the WATCHDOG by reloading the timer: Keyboard interrupt. Mouse interrupt. Serial Port 1 interrupt. Serial Port 2 interrupt. Software writing a `1' to the SW_WD_TRG bit of the WDCTL register (see Section 9.3.33 on page 201). Each event can be masked by an enable bit in the WDCFG register (see Section 9.3.35 on page 202). Whenever an active edge of any enabled event is detected, the timer is restarted from the WATCHDOG Time-Out Data value. If no event occurs before the timer reaches 00h, the WDO_EVT_STS status bit in the GPE1_STS_3 register (see Section 9.4.11 on page 210) is set to `1' and a 250 ms active low pulse is generated at the WDO pin. After a WATCHDOG time-out or when the Hardware reset is active (LRESET), the timer is reloaded. The WDO_EVT_STS status bit can be routed either to the SIOSMI pin by the WDO_EVT_2SMI bit in the GPE1_2SMI_HIGH register (see Section 9.3.7 on page 183) or to the SIOSCI pin by the WDO_EVT_EN bit in the GPE1_EN_3 register (see Section 9.4.15 on page 214). After either VSB Power-up reset or VDD Power-up reset, the WATCHDOG is disabled. Its operation is enabled by setting the WDEN bit in the WDCTL register (see Section 9.3.33 on page 201) to `1'. Once set, this bit cannot be cleared by software. The VSB Power-up and VDD Power-up resets both de-assert the WDO signal before the 250 ms have passed. The WDO_EVT_STS status bit is cleared by the VSB Power-up reset. Usage Hints Before changing the WATCHDOG Time-Out Data value in the WDTO register, set all the enable bits of the WATCHDOG trigger events to `0' - disable (in the WDCFG register - see Section 9.3.35 on page 202). Re-enable the WATCHDOG trigger events (set to `1') after writing the new WATCHDOG Time-Out Data. 9.2.10 Miscellaneous Functions Power Management Control The SWC contains two Power Management registers, which allows the software to disable each Legacy module and to TRI-STATE its outputs in a centralized manner. The SWC Fast Disable register (SWCFDIS) provides a fast way for the Power Management software to disable one or more Legacy modules without having to access the Activate register of each module (at index 30h) through the Index/Data registers. The FDC, Parallel Port, Serial Port 1, Serial Port 2, Mouse Control and Keyboard Control logical devices can be disabled through the SWCFDIS register (see Section 9.3.8 on page 184). 173 www.national.com 9.0 System Wake-Up Control (SWC) (Continued) The SWC TRI-STATE register (SWCTRIS) also provides a fast way for the Power Management software to float the outputs of one or more Legacy modules without having to access their TRI-STATE Control bit in the Special Configuration register at index F0h. The module outputs enter TRI-STATE only when the module is disabled. The FDC, Parallel Port, Serial Port 1, Serial Port 2, Mouse and Keyboard Control module outputs can be TRI-STATED through the SWCTRIS register (see Section 9.3.9 on page 185). Keyboard/Mouse Power Control (VDDFELL) If the VDDFLMUX bit in the SIOCF2 register (see Section 3.7.3 on page 49) is set to `1', the SWC generates a 1 second, active high pulse at the VDDFELL pin each time the VDD power supply is turned off (by setting the ONCTL signal to high level). This signal can be used by the system to turn off VSB power to the Keyboard and Mouse devices, thus causing them to reset their internal circuits. www.national.com 174 9.0 System Wake-Up Control (SWC) (Continued) 9.3 SWC REGISTERS The SWC registers are organized in four banks. The offsets are related to the base address determined by the SWC Base Address register at indexes 60h - 61h in the SWC device configuration. The lower 16 offsets (00h-0Fh) are common to the four banks; the upper offsets (10h-1Fh) are divided as follows: * * * * Bank 0 holds registers related to the Keyboard/Mouse Wake-up Detector. Bank 1 holds registers related to the Power Active timers. Bank 2 holds registers related to sleep states and ACPI configuration. Bank 3 holds registers related to the WATCHDOG. The active bank is selected through the BNK_SEL1-BNK_SEL0 bits in the Bank Select register (BANKSEL). For details, see Section 9.3.15 on page 191. The following abbreviations are used to indicate the Register Type: R/W = Read/Write. R = Read from a specific register (write to the same address is to a different register). W = Write (see above). RO = Read Only. WO = Write Only. Reading from the bit returns 0. R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect. R/W1S = Read/Write 1 to Set. Writing 1 to a bit sets its value to 1. Writing 0 has no effect. 9.3.1 SWC Register Map The following tables list the SWC registers. For the SWC register bitmap, see Section 9.5 on page 215. Most of the registers are battery backed, however some are VSB powered. Table 43. Banks 0, 1, 2 and 3 - Common Register Map Offset Mnemonic Register Name Type Power Well Section 00h WK_EVT_SEL Wake-Up Event Select R/W VPP 9.3.2 01h WK_ST_EN Wake-Up State Enable R/W VPP 9.3.3 02h GPE1_2IRQ_LOW GPE1_STS Events to IRQ Enable Low R/W VPP 9.3.4 03h GPE1_2IRQ_HIGH GPE1_STS Events to IRQ Enable High R/W VPP 9.3.5 04h GPE1_2SMI_LOW GPE1_STS Events to SMI Enable Low R/W VPP 9.3.6 05h GPE1_2SMI_HIGH GPE1_STS Events to SMI Enable High R/W VPP 9.3.7 06h SWCFDIS SWC Fast Disable R/W VSB 9.3.8 07h SWCTRIS SWC TRI-STATE R/W VSB 9.3.9 08h SWC_CTL SWC Miscellaneous Control Varies per bit VPP 9.3.10 09h PWONCTL Power ON Control Varies per bit VPP 9.3.11 0Ah LEDCTL LED Control R/W VPP 9.3.12 0Bh LEDBLNK LED Blinking Control R/W VPP 9.3.13 0Ch-0Dh Reserved 0Eh BIOSGPR BIOS General-Purpose Scratch R/W VPP 9.3.14 0Fh BANKSEL Bank Select R/W VPP 9.3.15 175 www.national.com 9.0 System Wake-Up Control (SWC) (Continued) Table 44. Bank 0 - Keyboard/Mouse Wake-Up Detector Register Map Offset Mnemonic Register Name Type Power Well Section 10h-11h Reserved 12h KBDWKCTL Keyboard Wake-Up Control R/W VPP 9.3.16 13h PS2CTL PS2 Protocol Control R/W VPP 9.3.17 14h-15h Reserved 16h KDSR Keyboard Data Shift-Register RO VPP 9.3.18 17h MDSR Mouse Data Shift-Register RO VPP 9.3.19 18h PS2KEY0 PS2 Keyboard Key Data 0 R/W VPP 9.3.20 19h PS2KEY1 PS2 Keyboard Key Data 1 R/W VPP 9.3.20 1Ah PS2KEY2 PS2 Keyboard Key Data 2 R/W VPP 9.3.20 1Bh PS2KEY3 PS2 Keyboard Key Data 3 R/W VPP 9.3.20 1Ch PS2KEY4 PS2 Keyboard Key Data 4 R/W VPP 9.3.20 1Dh PS2KEY5 PS2 Keyboard Key Data 5 R/W VPP 9.3.20 1Eh PS2KEY6 PS2 Keyboard Key Data 6 R/W VPP 9.3.20 1Fh PS2KEY7 PS2 Keyboard Key Data 7 R/W VPP 9.3.20 Table 45. Bank 1 - Power Active Timers Register Map Offset Mnemonic Register Name Type Power Well Section 10h VDD_ON_TMR_0 VDD Active Timer 0 RO VPP 9.3.21 11h VDD_ON_TMR_1 VDD Active Timer 1 RO VPP 9.3.22 12h VDD_ON_TMR_2 VDD Active Timer 2 RO VPP 9.3.23 13h VDD_ON_TMR_3 VDD Active Timer 3 RO VPP 9.3.24 14h VSB_ON_TMR_0 VSB Active Timer 0 RO VPP 9.3.25 15h VSB_ON_TMR_1 VSB Active Timer 1 RO VPP 9.3.26 16h VSB_ON_TMR_2 VSB Active Timer 2 RO VPP 9.3.27 17h VSB_ON_TMR_3 VSB Active Timer 3 RO VPP 9.3.28 18h PWTMRCTL Power Active Timers Control Varies per bit VPP 9.3.29 19h-1Fh Reserved www.national.com 176 9.0 System Wake-Up Control (SWC) (Continued) Table 46. Bank 2 - Sleep States and ACPI Configuration Register Map Offset Mnemonic Register Name Type Power Well Section 10h S0_SLP_TYP S0 Sleep Type Encoding R/W or RO VPP 9.3.30 11h S1_SLP_TYP S1 Sleep Type Encoding R/W or RO VPP 9.3.30 12h S2_SLP_TYP S2 Sleep Type Encoding R/W or RO VPP 9.3.30 13h S3_SLP_TYP S3 Sleep Type Encoding R/W or RO VPP 9.3.30 14h S4_SLP_TYP S4 Sleep Type Encoding R/W or RO VPP 9.3.30 15h S5_SLP_TYP S5 Sleep Type Encoding R/W or RO VPP 9.3.30 16h SLP_ST_CFG Sleep State Configuration Varies per bit VPP 9.3.31 17h ACPI_CFG ACPI Configuration R/W VPP 9.3.32 18h-1Fh Reserved Table 47. Bank 3 - WATCHDOG Register Map Offset Mnemonic Register Name 10h WDCTL WATCHDOG Control 11h WDTO 12h WDCFG Type Power Well Section Varies per bit VSB 9.3.33 WATCHDOG Time-Out R/W VSB 9.3.34 WATCHDOG Configuration R/W VSB 9.3.17 13h-1Fh Reserved 9.3.2 Wake-Up Event Select Register (WK_EVT_SEL) This register selects the wake-up event to be configured (i.e., which register is accessed via the Wake-Up State Enable register). Since access to the Wake-Up State Enable register requires two transactions (first to WK_EVT_SEL and then to WK_ST_EN) and since the LPC bus and ACCESS.bus access the module concurrently (PC87413 and PC87417), the WK_EVT_SEL register is duplicated (one accessed by the host and one by the ACCESS.bus).This register is reset by hardware to 00h. The wake-up events selected through this register are active when either the bits of the GPE1_STS_0 to GPE1_STS_3 registers or the PM1b_STS_HIGH register are set. Table 48 shows the mapping of the WKUPSEL field value to each wake-up event and the related status bit. Power Well: VPP Location: All Banks, Offset 00h Type: R/W Bit 7 Name 6 5 4 3 0 Bit 0 1 0 0 0 WKUPSEL Reserved Reset 2 0 0 0 0 Description 7-5 Reserved. 4-0 WKUPSEL (Wake-Up Event Select). These bits select a wake-up event to be configured through the WK_ST_EN register (see Table 48). 00000: GPIOE10 Event Status (default) 00001 to 11111: Wake-up events (see Table 48) 177 www.national.com 9.0 System Wake-Up Control (SWC) (Continued) Table 48. Wake-Up Event Select Field Map WKUPSEL Wake-Up Event Name WK_ST_EN Class GPE1_STS_n Bit PM1b_STS_HIGH Bit Notes 00h GPIOE10 Event Status A GPIOE10_STS 01h GPIOE11 Event Status A GPIOE11_STS 02h GPIOE12 Event Status A GPIOE12_STS 03h GPIOE13 Event Status A GPIOE13_STS 04h GPIOE14 Event Status A GPIOE14_STS 05h GPIOE15 Event Status A GPIOE15_STS 06h GPIOE16 Event Status A GPIOE16_STS 07h GPIOE17 Event Status A GPIOE17_STS 08h GPIOE40 Event Status A GPIOE40_STS 09h GPIOE41 Event Status A GPIOE41_STS 0Ah GPIOE42 Event Status A GPIOE42_STS 0Bh GPIOE43 Event Status A GPIOE43_STS 0Ch GPIOE44 Event Status A GPIOE44_STS 0Dh GPIOE45 Event Status A GPIOE45_STS 0Eh GPIOE46 Event Status A GPIOE46_STS 0Fh GPIOE47 Event Status A GPIOE47_STS 10h RI1 Event Status A RI1_EVT_STS 11h RI2 Event Status A RI2_EVT_STS 12h Mouse Event Status A MS_EVT_STS 13h Keyboard Event 1 Status A KBD_EVT1_STS 14h Keyboard Event 2 Status A KBD_EVT2_STS 15h Keyboard Event 3 Status A KBD_EVT3_STS 16h Sleep Button Event Status A SLBT_EVT_STS SLPBTN_STS ORed bits 17h Reserved 18h RTC Alarm Event Status A RTC_EVT_STS RTC_STS ORed bits 19h Port P12 Event Status B P12_EVT_STS 1Ah Keyboard IRQ Event Status B KBD_IRQ_STS 1Bh Mouse IRQ Event Status B MS_IRQ_STS 1Ch Modules IRQ Event Status A MOD_IRQ_STS 1Dh Reserved 1Eh Software ON Event Status A SW_ON_STS 1Fh Software OFF Event Status A SW_OFF_STS www.national.com 178 9.0 System Wake-Up Control (SWC) 9.3.3 (Continued) Wake-Up State Enable Register (WK_ST_EN) This register configures the wake-up event selected by the Wake-Up Event Select register. Two different classes (A and B) are defined for this register (see Table 48 on page 178). Both classes are reset by hardware to 00h. The sleep states for which the outputs are enabled when the event is active are PC8741x device current states (see Section 9.2.3 on page 166). Power Well: VPP Location: All Banks, Offset 01h Type: R/W Class: A Bit 7 6 Name 3 PWBT_EN _S3I 2 1 0 PWBT_EN ONCTL_EN ONCTL_EN _S45 _S3I _S45 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 B Bit Name Reserved Reset 0 Bit 7-4 4 Reserved Reset Class: 5 0 0 ONCTL_EN ONCTL_EN _S3I _S45 0 0 0 0 0 Description Reserved. 3 PWBT_EN_S3I (PWBTOUT Pulse Enable in S3I). Enables generating a PWBTOUT pulse when the selected Class A event becomes active and the device is in S3I sleep state. The selected event affects the output regardless of the setting of the related enable bit in the GPE1_EN_n register. However, for a PWBTOUT pulse to be generated, the PWBTOUT_MODE bit in the ACPI_CFG register (see Section 9.3.32 on page 200) must be `0'. 0: Disable pulse (default) 1: Enable pulse in S3I state 2 PWBT_EN_S45 (PWBTOUT Pulse Enable in S45). Enables generating a PWBTOUT pulse when the selected Class A event becomes active and the device is in S45 sleep state. The selected event affects the output regardless of the setting of the related enable bit in the GPE1_EN_n register. However, for a PWBTOUT pulse to be generated, the PWBTOUT_MODE bit in the ACPI_CFG register (see Section 9.3.32 on page 200) must be `0'. 0: Disable pulse (default) 1: Enable pulse in S45 state 3-2 Reserved. Class B 1 ONCTL_EN_S3I (ONCTL Active Enable in S3I). Enables activation (turning the VDD power ON) of the ONCTL output when the selected event becomes active and the device is in the S3I sleep state. The selected event affects the output regardless of the setting of the related enable bit in the GPE1_EN_n register. This bit is relevant only if the PC8741x device is the ACPI controller of the system (EXT_ST_SELECT = 0 in the SLP_ST_CFG register). 0: Disable activation (default) 1: Enable activation in S3I state 0 ONCTL_EN_S45 (ONCTL Active Enable in S45). Enables activation (turning the VDD power ON) of the ONCTL output when the selected event becomes active and the device is in the S45 sleep state. The selected event affects the output regardless of the setting of the related enable bit in the GPE1_EN_n register. This bit is relevant only if the PC8741x device is the ACPI controller of the system (EXT_ST_SELECT = 0 in the SLP_ST_CFG register). 0: Disable activation (default) 1: Enable activation in S45 state 179 www.national.com 9.0 System Wake-Up Control (SWC) 9.3.4 (Continued) GPE1_STS Events to IRQ Enable Low Register (GPE1_2IRQ_LOW) This register enables the wake-up events contained in bits 16-23 of the GPE1_STS register to generate an IRQ. It is reset by hardware to 00h. Power Well: VPP Location: All Banks, Offset 02h Type: R/W Bit 7 Name 6 5 4 3 PWBT_EVT SLBT_EVT KBD_EVT3 KBD_EVT2 KBD_EVT1 _2IRQ _2IRQ _2IRQ _2IRQ _2IRQ Reset 0 Bit 0 0 0 0 2 1 0 MS_EVT _2IRQ RI2_EVT _2IRQ RI1_EVT _2IRQ 0 0 0 Description 7 PWBT_EVT_2IRQ (Power Button Event to IRQ Enable). generate an IRQ. 0: Disable IRQ (default) 1: Enable IRQ from Power button pressing event 6 SLBT_EVT_2IRQ (Sleep Button Event to IRQ Enable). Enables the Sleep button pressing event to generate an IRQ. 0: Disable IRQ (default) 1: Enable IRQ from Sleep button pressing event 5 KBD_EVT3_2IRQ (Keyboard Event 3 to IRQ Enable). Enables the "PM Key 3" (keyboard) pressing event to generate an IRQ. 0: Disable IRQ (default) 1: Enable IRQ from pressing "PM Key 3" on the keyboard 4 KBD_EVT2_2IRQ (Keyboard Event 2 to IRQ Enable). Enables the "PM Key 2" (keyboard) pressing event to generate an IRQ. 0: Disable IRQ (default) 1: Enable IRQ from pressing "PM Key 2" on the keyboard 3 KBD_EVT1_2IRQ (Keyboard Event 1 to IRQ Enable). Enables the event of pressing any keyboard key, key sequence or "PM Key 1" to generate an IRQ. 0: Disable IRQ (default) 1: Enable IRQ from pressing any key, key sequence or "PM Key 1" on the keyboard 2 MS_EVT_2IRQ (Mouse Event to IRQ Enable). Enables a mouse event identified by the Keyboard/Mouse Wake-up Detector to generate an IRQ. 0: Disable IRQ (default) 1: Enable IRQ from a mouse event identified by the Keyboard/Mouse Wake-up Detector 1 RI2_EVT_2IRQ (RI2 Event to IRQ Enable). Enables a telephone ring event received at the Serial Port 2, identified by the RI Wake-up Detector, to generate an IRQ. 0: Disable IRQ (default) 1: Enable IRQ from the telephone ring event received at the Serial Port 2 0 RI1_EVT_2IRQ (RI1 Event to IRQ Enable). Enables a telephone ring event received at the Serial Port 1, identified by the RI Wake-up Detector, to generate an IRQ. 0: Disable IRQ (default) 1: Enable IRQ from the telephone ring event received at the Serial Port 1 www.national.com 180 Enables the Power button pressing event to 9.0 System Wake-Up Control (SWC) 9.3.5 (Continued) GPE1_STS Events to IRQ Enable High Register (GPE1_2IRQ_HIGH) This register enables the wake-up events contained in 24-31 of the GPE1_STS register to generate an IRQ. It is reset by hardware to 00h. Power Well: VPP Location: All Banks, Offset 03h Type: R/W Bit 7 6 Name SW_OFF _2IRQ SW_ON _2IRQ Reset 0 0 Bit 5 4 3 2 Reserved 0 0 0 0 1 0 P12_EVT _2IRQ Reserved 0 0 Description 7 SW_OFF_2IRQ (Software OFF Event to IRQ Enable). Enables the event of the software writing a `1' to the SW_OFF_CTL bit in the SWC_CTL register to generate an IRQ. 0: Disable IRQ (default) 1: Enable IRQ from the software writing a `1' to the SW_OFF_CTL bit in the SWC_CTL register 6 SW_ON_2IRQ (Software ON Event to IRQ Enable). Enables the event of the software writing a `1' to the SW_ON_CTL bit in the SWC_CTL register to generate an IRQ. 0: Disable IRQ (default) 1: Enable IRQ from the software writing a `1' to the SW_ON_CTL bit in the SWC_CTL register 5-2 Reserved. 1 P12_EVT_2IRQ (Port P12 Event to IRQ Enable). Enables an active high signal generated at the P12 pin to generate an IRQ. 0: Disable IRQ (default) 1: Enable IRQ from an active high signal generated at the P12 pin 0 Reserved. 181 www.national.com 9.0 System Wake-Up Control (SWC) 9.3.6 (Continued) GPE1_STS Events to SMI Enable Low Register (GPE1_2SMI_LOW) This register enables the wake-up events contained in bits 16-23 of the GPE1_STS register to generate an SMI interrupt. It is reset by hardware to 00h. Power Well: VPP Location: All Banks, Offset 04h Type: R/W Bit 7 Name 6 5 4 3 PWBT_EVT SLBT_EVT KBD_EVT3 KBD_EVT2 KBD_EVT1 _2SMI _2SMI _2SMI _2SMI _2SMI Reset 0 Bit 0 0 0 0 2 1 0 MS_EVT _2SMI RI2_EVT _2SMI RI1_EVT _2SMI 0 0 0 Description 7 PWBT_EVT_2SMI (Power Button Event to SMI Enable). generate an SMI interrupt. 0: Disable SMI (default) 1: Enable SMI from Power button pressing event 6 SLBT_EVT_2SMI (Sleep Button Event to SMI Enable). Enables the Sleep button pressing event to generate an SMI interrupt. 0: Disable SMI (default) 1: Enable SMI from Sleep button pressing event 5 KBD_EVT3_2SMI (Keyboard Event 3 to SMI Enable). Enables the "PM Key 3" (keyboard) key pressing event to generate an SMI interrupt. 0: Disable SMI (default) 1: Enable SMI from pressing "PM Key 3" on the keyboard 4 KBD_EVT2_2SMI (Keyboard Event 2 to SMI Enable). Enables the "PM Key 2" (keyboard) key pressing event to generate an SMI interrupt. 0: Disable SMI (default) 1: Enable SMI from pressing "PM Key 2" on the keyboard 3 KBD_EVT1_2SMI (Keyboard Event 1 to SMI Enable). Enables the event of pressing any keyboard key, key sequence or "PM Key 1" to generate an SMI interrupt. 0: Disable SMI (default) 1: Enable SMI from pressing any key, key sequence or "PM Key 1" on the keyboard 2 MS_EVT_2SMI (Mouse Event to SMI Enable). Enables a mouse event, identified by the Keyboard/Mouse Wake-up Detector, to generate an SMI interrupt. 0: Disable SMI (default) 1: Enable SMI from the mouse event identified by the Keyboard/Mouse Wake-up Detector 1 RI2_EVT_2SMI (RI2 Event to SMI Enable). Enables a telephone ring event received at the Serial Port 2, identified by the RI Wake-up Detector, to generate an SMI interrupt. 0: Disable SMI (default) 1: Enable SMI from the telephone ring event received at the Serial Port 2 0 RI1_EVT_2SMI (RI1 Event to SMI Enable). Enables a telephone ring event received at the Serial Port 1, identified by the RI Wake-up Detector, to generate an SMI interrupt. 0: Disable SMI (default) 1: Enable SMI from the telephone ring event received at the Serial Port 1 www.national.com 182 Enables the Power button pressing event to 9.0 System Wake-Up Control (SWC) 9.3.7 (Continued) GPE1_STS Events to SMI Enable High Register (GPE1_2SMI_HIGH) This register enables the wake-up events contained in bits 24-31 of the GPE1_STS register to generate an SMI interrupt. It is reset by hardware to 00h. Power Well: VPP Location: All Banks, Offset 05h Type: R/W Bit 7 6 5 Name SW_OFF _2SMI SW_ON _2SMI WDO_EVT _2SMI Reset 0 0 0 Bit 4 3 2 1 RTC_EVT _2SMI Reserved 0 0 0 0 0 0 Description 7 SW_OFF_2SMI (Software OFF Event to SMI Enable). Enables the event of the software writing a `1' to the SW_OFF_CTL bit in the SWC_CTL register to generate an SMI interrupt. 0: Disable SMI (default) 1: Enable SMI from the software writing a `1' to the SW_OFF_CTL bit in the SWC_CTL register 6 SW_ON_2SMI (Software ON Event to SMI Enable). Enables the event of the software writing a `1' to the SW_ON_CTL bit in the SWC_CTL register to generate an SMI interrupt. 0: Disable SMI (default) 1: Enable SMI from the software writing a `1' to the SW_ON_CTL bit in the SWC_CTL register 5 WDO_EVT_2SMI (WATCHDOG Event to SMI Enable). Enables a WATCHDOG time-out to generate an SMI interrupt. 0: Disable SMI (default) 1: Enable SMI from WATCHDOG time-out 4-1 0 Reserved. RTC_EVT_2SMI (RTC Alarm Event to SMI Enable). Enables an RTC alarm to generate an SMI interrupt. 0: Disable SMI (default) 1: Enable SMI from RTC alarm 183 www.national.com 9.0 System Wake-Up Control (SWC) 9.3.8 (Continued) SWC Fast Disable Register (SWCFDIS) This register provides a fast way for the Power Management software to disable one or more modules without having to access the Activate register of each module (see Section 3.3.1 on page 42). It is reset by hardware to 00h. Power Well: VSB Location: All Banks, Offset 06h Type: R/W Bit 7 Name Reset 0 Bit 7-6 6 Reserved 0 5 4 3 2 1 0 KBDDIS MSDIS SER1DIS SER2DIS PARPDIS FDCDIS 0 0 0 0 0 0 Description Reserved. 5 KBDDIS (Keyboard Controller Disable). When set to 1, this bit forces the Keyboard Controller module (Logical Device 6) to be disabled (and its resources released) regardless of the actual setting of its Activation bit (index 30). 0: Enabled or Disabled, according to Activation bit (default) 1: Disabled 4 MSDIS (Mouse Controller Disable). When set to 1, this bit forces the Mouse Controller module (Logical Device 5) to be disabled (and its resources released) regardless of the actual setting of its Activation bit (index 30). 0: Enabled or Disabled, according to Activation bit (default) 1: Disabled 3 SER1DIS (Serial Port 1 Disable). When set to 1, this bit forces the Serial Port 1 module to be disabled (and its resources released) regardless of the actual setting of its Activation bit (index 30). 0: Enabled or Disabled, according to Activation bit (default) 1: Disabled 2 SER2DIS (Serial Port 2 Disable). When set to 1, this bit forces the Serial Port 2 module to be disabled (and its resources released) regardless of the actual setting of its Activation bit (index 30). 0: Enabled or Disabled, according to Activation bit (default) 1: Disabled 1 PARPDIS (Parallel Port Disable). When set to 1, this bit forces the Parallel Port module to be disabled (and its resources released) regardless of the actual setting of its Activation bit (index 30). 0: Enabled or Disabled, according to Activation bit (default) 1: Disabled 0 FDCDIS (Floppy Disk Controller Disable). When set to 1, this bit forces the Floppy Disk Controller module to be disabled (and its resources released) regardless of the actual setting of its Activation bit (index 30). 0: Enabled or Disabled, according to Activation bit (default) 1: Disabled www.national.com 184 9.0 System Wake-Up Control (SWC) 9.3.9 (Continued) SWC TRI-STATE Register (SWCTRIS) This register provides a fast way for the Power Management software to float the outputs of one or more modules without having to access their TRI-STATE Control bit in the Special Configuration register at index F0h. The module outputs enter TRI-STATE only when the module is disabled (see Section 9.3.8). The register is reset by hardware to 00h. Power Well: VSB Location: All Banks, Offset 07h Type: R/W Bit 7 Name 5 Reserved Reset 0 Bit 7-5 6 0 4 3 KBMSTRIS SER1TRIS 0 0 0 2 1 0 SER2TRIS PARPTRIS FDCTRIS 0 0 0 Description Reserved. 4 KBMSTRIS (Keyboard and Mouse Outputs TRI-STATE). When set to 1 and the module is disabled, this bit forces the outputs of the Keyboard and Mouse Controller to be in TRI-STATE regardless of bit 0 in the Keyboard Configuration register (see Section 3.13.3 on page 68). 0: Enabled or Disabled, according to bit 0 in the Keyboard Configuration register (default) 1: Outputs in TRI-STATE 3 SER1TRIS (Serial Port 1 Outputs TRI-STATE). When set to 1 and the module is disabled, this bit forces the outputs of the Serial Port 1 module to be in TRI-STATE regardless of bit 0 in the Serial Port 1 Configuration register (see Section 3.11.3 on page 65). 0: Enabled or Disabled, according to bit 0 in the Serial Port 1 Configuration register (default) 1: Outputs in TRI-STATE 2 SER2TRIS (Serial Port 2 Outputs TRI-STATE). When set to 1 and the module is disabled, this bit forces the outputs of the Serial Port 2 module to be in TRI-STATE regardless of bit 0 in the Serial Port 2 Configuration register (see Section 3.10.3 on page 63). 0: Enabled or Disabled, according to bit 0 in the Serial Port 2 Configuration register (default) 1: Outputs in TRI-STATE 1 PARPTRIS (Parallel Port Outputs TRI-STATE). When set to 1 and the module is disabled, this bit forces the outputs of the Parallel Port module to be in TRI-STATE regardless of bit 0 in the Parallel Port Configuration register (see Section 3.9.3 on page 61). 0: Enabled or Disabled, according to bit 0 in the Parallel Port Configuration register (default) 1: Outputs in TRI-STATE 0 FDCTRIS (Floppy Disk Controller Outputs TRI-STATE). When set to 1 and the module is disabled, this bit forces the outputs of the Floppy Disk Controller module to be in TRI-STATE regardless of bit 0 in the FDC Configuration register (see Section 3.8.3 on page 58). 0: Enabled or Disabled, according to bit 0 in the FDC Configuration register (default) 1: Outputs in TRI-STATE 185 www.national.com 9.0 System Wake-Up Control (SWC) (Continued) 9.3.10 SWC Miscellaneous Control Register (SWC_CTL) This register contains control and status bits for the SWC module. It is reset by hardware to 00h. Power Well: VPP Location: All Banks, Offset 08h Type: Varies per bit Bit 7 6 Name SW_OFF _CTL SW_ON _CTL Reset 0 0 5 4 3 PWB_OVR CROWBAR _STS _STS 0 0 2 1 SWAP _KBMS Reserved 0 0 0 0 0 Bit Type Description 7 R/W SW_OFF_CTL (Software OFF Control). Writing `1' to this bit sets the SW_OFF_STS bit in the GPE1_STS_3 register (see Section 9.4.11 on page 210), which requests a VDD power off sequence. This bit then returns to `0' (read always returns `0'). 0: Inactive (default) 1: Requests a VDD power off sequence 6 R/W SW_ON_CTL (Software ON Control). Writing `1' to this bit sets the SW_ON_STS bit in the GPE1_STS_3 register (see Section 9.4.11 on page 210), which requests a VDD power on sequence. This bit then returns to `0' (read always returns `0'). When the VDD power is off, this bit can be written only through the ACCESS.bus (PC87413 and PC87417). 0: Inactive (default) 1: Requests a VDD power on sequence 5 R/W1C PWB_OVR_STS (Power Button Override Status). Indicates that the Power Button Override event has occurred (Power button pressed for more than 4 seconds). In this condition the VDD power is unconditionally turned off. Writing `1' clears this bit; writing `0' is ignored. 0: Inactive (default) 1: Power Button Override event has occurred 4 R/W1C CROWBAR_STS (Crowbar Status). Indicates that the Crowbar event has been detected (VDD remained Off for longer than the Crowbar Timeout). In this condition the VDD power is turned off. Writing `1' clears this bit; writing `0' is ignored. 0: Inactive (default) 1: Crowbar event has been detected 3-1 0 Reserved. R/W www.national.com SWAP_KBMS (Swap Keyboard and Mouse Inputs). When this bit is set, the keyboard signals (KBCLK and KBDAT) are swapped with the mouse signals (MCLK and MDAT). This bit must be set to the same value as the Swap bit in the KBC Configuration register (see Section 3.13.3 on page 68). 0: No swapping (default) 1: Swaps the keyboard and mouse signals 186 9.0 System Wake-Up Control (SWC) (Continued) 9.3.11 Power ON Control Register (PWONCTL) This register controls the power-On process and the way the PC8741x device resumes operation after Power Fail. It is reset by hardware to 87h. Power Well: VPP Location: All Banks, Offset 09h Type: Varies per bit Bit 7 6 Name WAS _PFAIL LAST _ONCTL Reset 1 0 5 4 RESUME_MD 0 0 3 2 LEGACY _PWBT1 0 1 0 CRBAR_TOUT 1 1 1 1. This bit is powered from the VDD well and is reset either by VDD power-up reset or by hardware reset. Bit 7 6 Type Description R/W1C WAS_PFAIL (Was Power Fail Status). Indicates that the device has woken up from a Power Fail condition (VDD and VSB off). This bit is set by VSB Power-Up reset. Writing `1' clears this bit; writing `0' is ignored. 0: Inactive 1: Wake-up from Power Fail (default) RO LAST_ONCTL (Last Value of ONCTL). This bit reflects the last value of the ONCTL signal when the previous Power Fail condition (VDD and VSB off) occurred. Writing to this bit is ignored. 0: ONCTL inactive - VDD power off (default) 1: ONCTL active - VDD power on 5-4 R/W RESUME_MD (Resume Mode Control). These bits control the power state to which the PC8741x device resumes after waking-up from a Power Fail condition (i.e., when VDD and VSB are off). Table 49 shows the behavior of the ONCTL and PWBTOUT signals in all four Resume modes. 3 R/W LEGACY_PWBT (Legacy Power Button). This bit allows the Power button to set ONCTL to inactive level (VDD power supply OFF). 0: ACPI-compliant Power button - VDD power turned off by sleep state (written into SLP_TYPx field or decoded from SLPS3 and SLPS5) or by a Power Button Override condition (default) 1: Legacy Power button - VDD power turned off by pressing the Power button (PWBTIN) when the VDD power is on 2-0 R/W CRBAR_TOUT (Crowbar Timeout Configuration). This field controls the timeout value for the Crowbar function (the time between the activation of ONCTL and its deactivation as a result of VDD remaining off). After the Crowbar timeout, the PC8741x device waits another second before it accepts a new Power button event. Bits 2 1 0 Timeout (Seconds) 0 0 0 0 1 1 1 1 0.5 1 2 3 6 10 15 20 (default) 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 187 www.national.com 9.0 System Wake-Up Control (SWC) (Continued) Table 49. ONCTL and PWBTOUT as a Function of the Power Fail Resume Mode RESUME_MD EXT_ST_SELECT1 0 00 (Default) RTC Alarm in Power Fail2 ONCTL Pin PWBTOUT Pin X X X 1 - 0 X X 1 - 1 X X 0 (ON) Pulse3 X X 0 1 - 0 X 0 1 - 1 X X 0 (ON) Pulse3 X X X 1 0 (ON) Pulse3 X X 0 X 1 - X X 1 X 0 (ON) Pulse3 X X 0 0 1 - X X 1 X 0 (ON) Pulse3 X X X 1 0 (ON) Pulse3 1 0 01 SLPS3 Pin LAST_ONCTL 1 10 11 1. EXT_ST_SELECT bit in the SLP_ST_CFG register (see Section 9.3.31 on page 199). The EXTSTMUX bit in the SIOCF3 register (see Section 3.7.4 on page 50) has to be set to the same value as EXT_ST_SELECT. 2. RTC Alarm event active during Power Fail. 3. A pulse is generated only if the PWBTOUT_MODE bit in the ACPI_CFG register is `0' (see Section 9.3.32 on page 200). www.national.com 188 9.0 System Wake-Up Control (SWC) (Continued) 9.3.12 LED Control Register (LEDCTL) This register controls the operation mode of the two LEDs driven by the PC8741x device. It is reset by hardware to 00h. Power Well: VPP Location: All Banks, Offset 0Ah Type: R/W Bit 7 Name 6 Reserved Reset 0 5 4 LEDCFG LEDPOL 0 0 0 Bit 7-6 5 3 2 1 0 0 Reserved 0 0 LEDMOD 0 Description Reserved. LEDCFG (LED Configuration). This bit enables the use of either two regular LEDs, connected between each pin (LED1, LED2) and ground or VSB, or one dual-colored LED, connected between the LED1 and LED2 pins. 0: One dual-colored LED (default) 1: Two regular LEDs 4 LEDPOL (LED Polarity). This bit determines the polarity of LED1 and LED2 outputs. An active output, according to this bit setting, turns the LED ON. For the dual-colored LED configuration, changing the polarity reverses the LED colors. 0: Active high - LED cathode connected to ground (default) 1: Active low - LED anode connected to VSB 3-2 Reserved. 1-0 LEDMOD (LED Operation Mode). These bits control the operation mode of LED1 and LED2 in each power state. Table 50 shows the behavior of the LED1 and LED2 outputs as a function of the system power state. Table 50. LED1 and LED2 as a Function of the Power State LEDMOD 00 (default) Power Fail1 Power OFF1 State S452 State S3I2 Power ON1 LED1 LED2 Yes OFF OFF No S/W13 S/W24 OFF OFF Blink5 Blink5 S/W1 S/W2 OFF OFF OFF OFF S/W1 S/W2 S/W1 S/W2 OFF OFF S/W1 S/W2 S/W1 S/W2 S/W1 S/W2 X X X X Yes 01 Yes X X Yes Yes X Yes 10 X Yes Yes Yes X Yes 11 X Yes Yes 1. Power Fail: VSB and VDD OFF. Power OFF: VSB ON, VDD OFF. Power ON: VSB and VDD ON; 2. Sleep states S3I and S45 are PC8741x device current states (see Section 9.3.31 on page 199). 3. Controlled by the value of LED1BLNK in the LEDBLNK register. 4. Controlled by the value of LED2BLNK in the LEDBLNK register. 5. 1 Hz blink with 50% duty cycle. 189 www.national.com 9.0 System Wake-Up Control (SWC) (Continued) 9.3.13 LED Blink Control Register (LEDBLNK) This register controls the blinking rate of the two LEDs driven by the PC8741x device. It is reset by hardware to 70h. Power Well: VPP Location: All Banks, Offset 0Bh Type: R/W Bit 7 Name Reserved Reset 0 6 5 4 LED2BLNK 1 6-4 3 2-0 2 Reserved 1 1 Bit 7 3 0 1 0 LED1BLNK 0 0 0 Description Reserved. LED2BLNK (LED2 Blink Rate). These bits control the blinking rate of LED2 output. Bits 6 5 4 Rate (Hz) Duty Cycle 0 0 0 0 1 1 1 1 OFF 0.25 0.5 1 2 3 4 ON Always inactive 12.5% 25% 50% 50% 50% 50% Always active (default) 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Reserved. LED1BLNK (LED1 Blink Rate). These bits control the blinking rate of LED1 output. Bits 2 1 0 Rate (Hz) Duty Cycle 0 0 0 0 1 1 1 1 OFF 0.25 0.5 1 2 3 4 ON Always inactive (default) 12.5% 25% 50% 50% 50% 50% Always active 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 9.3.14 BIOS General-Purpose Scratch Register (BIOSGPR) This register may be used by the BIOS for general-purpose battery-backed data storage. It is reset by hardware to 00h. Power Well: VPP Location: All Banks, Offset 0Eh Type: R/W Bit 7 6 5 0 0 0 Name 3 2 1 0 0 0 0 General-Purpose Scratch Reset Bit 7-0 4 0 Description General-Purpose Scratch www.national.com 190 0 9.0 System Wake-Up Control (SWC) (Continued) 9.3.15 Bank Select Register (BANKSEL) This register selects the active bank for the upper offsets (10h-1Fh). Since the access to registers at offsets 10h-1Fh requires two transactions (first to BANKSEL and then to the specific register) and since the LPC bus and ACCESS.bus access the module concurrently (PC87413 and PC87417), the BANKSEL register is duplicated (one is accessed by the host and one by the ACCESS.bus).This register is reset by hardware to 00h. Power Well: VPP Location: All Banks, Offset 0Fh Type: R/W Bit 7 6 5 Name 4 3 2 1 Reserved Reset 0 0 Bit 0 0 BNK_SEL 0 0 0 0 0 Description 7-2 Reserved. 1-0 BNK_SEL (Bank Select). This field selects the active bank for the upper offsets (10h-1Fh). Bits 1 0 Active Bank 0 0 1 1 Bank 0: holds registers related to the Keyboard/Mouse Wake-up Detector (default) Bank 1: holds registers related to the Power Active timers Bank 2: holds registers related to sleep states and ACPI configuration Bank 3: holds registers related to WATCHDOG configuration and control 0 1 0 1 191 www.national.com 9.0 System Wake-Up Control (SWC) (Continued) 9.3.16 Keyboard Wake-Up Control Register (KBDWKCTL) This register configures the keyboard events detected by the Keyboard/Mouse Wake-up Detector. It is reset by hardware to 00h. Power Well: VPP Location: Bank 0, Offset 12h Type: R/W Bit 7 6 Name KBDMODE Reserved Reset 0 0 Bit 5 4 3 EVT3CFG 0 2 1 EVT2CFG 0 0 0 EVT1CFG 0 0 Description 7 KBDMODE (Keyboard Mode Select). This bit selects one of the keyboard wake-up modes for the Keyboard/Mouse Wake-up Detector. 0: Special Key Sequence or Password modes - configured by bits 3-0 of the PS2CTL register (default) 1: Power Management Key mode - configured by bits 5-0 of the KBDWKCTL register 6 Reserved. 5-4 3-2 1-0 0 EVT3CFG (Keyboard Event 3 Configuration). These bits configure the keyboard data sequence for Keyboard Event 3, which indicates that "PM Key 3" was pressed on the keyboard. The setting of the EVT3CFG field is relevant only if the Keyboard/Mouse Wake-up Detector is in Power Management Key mode (KBDMODE = 1). The keyboard data sequence used to detect Keyboard Event 3 is stored in registers PS2KEY6 and PS2KEY7, starting with PS2KEY6. Bits 5 4 Sequence Length 0 0 1 1 0 bytes - Keyboard Event 3 disabled (default) 1 byte (PS2KEY6) 2 bytes (PS2KEY6, PS2KEY7) Reserved 0 1 0 1 EVT2CFG (Keyboard Event 2 Configuration). These bits configure the keyboard data sequence for Keyboard Event 2, which indicates that "PM Key 2" was pressed on the keyboard. The setting of the EVT2CFG field is relevant only if the Keyboard/Mouse Wake-up Detector is in Power Management Key mode (KBDMODE = 1). The keyboard data sequence used to detect Keyboard Event 2 is stored in registers PS2KEY3 to PS2KEY5, starting with PS2KEY3. Bits 3 2 Sequence Length 0 0 1 1 0 bytes - Keyboard Event 2 disabled (default) 1 byte (PS2KEY3) 2 bytes (PS2KEY3, PS2KEY4) 3 bytes (PS2KEY3, PS2KEY4, PS2KEY5) 0 1 0 1 EVT1CFG (Keyboard Event 1 Configuration). These bits configure the keyboard data sequence for Keyboard Event 1, which indicates that "PM Key 1" was pressed on the keyboard. The setting of the EVT1CFG field is relevant only if the Keyboard/Mouse Wake-up Detector is in Power Management Key mode (KBDMODE = 1). The keyboard data sequence used to detect Keyboard Event 1 is stored in registers PS2KEY0 to PS2KEY2, starting with PS2KEY0. Bits 1 0 Sequence Length 0 0 1 1 0 bytes - Keyboard Event 1 disabled (default) 1 byte (PS2KEY0) 2 bytes (PS2KEY0, PS2KEY1) 3 bytes (PS2KEY0, PS2KEY1, PS2KEY2) 0 1 0 1 www.national.com 192 9.0 System Wake-Up Control (SWC) (Continued) 9.3.17 PS2 Protocol Control Register (PS2CTL) This register configures the keyboard and mouse events detected by the Keyboard/Mouse Wake-up Detector. It is reset by hardware to 00h. Power Well: VPP Location: Bank 0, Offset 13h Type: R/W Bit 7 6 Name DISPAR Reset 0 5 0 Bit 7 6-4 3-0 4 3 2 MSEVCFG 0 1 0 0 0 KBEVCFG 0 0 0 Description DISPAR (Disable Parity Check). This controls the parity checking of the keyboard and mouse data by the Keyboard/Mouse Wake-up Detector. 0: Enable parity check (default) 1: Disable parity check MSEVCFG (Mouse Event Configuration). These bits configure the mouse data sequence for the Mouse event. Before setting them to a new value, these bits must be cleared by writing a value of 000b. Bits 6 5 4 Event Configuration 0 0 0 0 1 1 1 1 Disable mouse wake-up detection (default) Wake-up on any mouse movement or button click Wake-up on left button click Wake-up on left button double-click Wake-up on right button click Wake-up on right button double-click Wake-up on any button single-click (left, right or middle) Wake-up on any button double-click (left, right or middle) 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 KBEVCFG (Keyboard Event Configuration). These bits configure the keyboard data sequence for the Keyboard event, which indicates that any key or key sequence was pressed on the keyboard. The setting of the KBEVCFG field is relevant only if the Keyboard/Mouse Wake-up Detector is in either Special Key Sequence or Password mode (KBDMODE = 0). The keyboard data sequence used to detect a Keyboard Event is stored in registers PS2KEY0 to PS2KEY7, starting with PS2KEY0. Before setting them to a new value, the KBEVCFG field must be cleared by writing a value of 0000b. Bits 3 2 1 0 Event Configuration 0 0 0 0 Disable keyboard wake-up detection (default) 0 0 0 1 to 0 1 1 1 1 0 0 0 to 1 1 1 1 } } Special Key Sequence mode 2-8 PS/2 data bytes, "Make" and "Break" (including Shift and Alt keys) Password Enabled mode with 1-8 keys "Make" code (excluding Shift and Alt keys) 193 www.national.com 9.0 System Wake-Up Control (SWC) (Continued) 9.3.18 Keyboard Data Shift Register (KDSR) When keyboard wake-up detection is enabled, this register stores the keyboard data shifted in from the keyboard during transmission. It is reset by hardware to 00h. Power Well: VPP Location: Bank 0, Offset 16h Type: RO Bit 7 6 5 Name Reset 0 0 0 Bit 7-0 4 3 2 1 0 0 0 0 Keyboard Data 0 0 Description Keyboard Data. 9.3.19 Mouse Data Shift Register (MDSR) When mouse wake-up detection is enabled, this register stores the mouse data shifted in from the mouse during transmission. It is reset by hardware to 00h. Power Well: VPP Location: Bank 0, Offset 17h Type: RO Bit 7 6 Name 5 4 3 2 Reserved Reset 0 0 0 Bit 1 0 Mouse Data 0 0 0 0 0 Description 7-3 Reserved. 2-0 Mouse Data. 9.3.20 PS2 Keyboard Key Data 0 to 7 Registers (PS2KEY0 to PS2KEY7) These eight registers (PS2KEY0-PS2KEY7) store the data bytes for Special Key Sequence or Password mode (KBDMODE = 0) or for Power Management Key mode (KBDMODE = 1) of the Keyboard/Mouse Wake-up Detector. In Special Key Sequence or in Password modes, the keyboard data is stored as follows: PS2KEY0 register stores the data byte for the first key in the sequence. PS2KEY1 register stores the data byte for the second key in the sequence. PS2KEY2 - PS2KEY7 registers store data bytes for the third to eighth key in the sequence. For keyboard data storage in Power Management Key mode, see Section 9.3.16 on page 192. When one of these registers is set to 00h, it indicates that the value of the corresponding data byte is ignored (not compared). These registers are reset by hardware to 00h. Power Well:VPP Location: Bank 0, Offset 18h to 1Fh Type: R/W Bit 7 6 5 Name Reset 0 Bit 7-0 4 3 2 1 0 0 0 0 Data Byte of Key 0 0 0 Description Data Byte of Key. www.national.com 194 0 9.0 System Wake-Up Control (SWC) (Continued) 9.3.21 VDD Active Timer 0 Register (VDD_ON_TMR_0) This register holds a copy of bits 0-7 of the VDD Active Timer. Whenever the VDD_ON_TMR_0 register is read, the updating of all four VDD_ON_TMR_0 to VDD_ON_TMR_3 registers is stopped, freezing the count value. Therefore, this register must be read first. It is reset by hardware to 00h. Power Well: VPP Location: Bank 1, Offset 10h Type: RO Bit 7 6 5 Reset 0 0 0 Bit 7-0 4 3 2 1 0 0 0 0 VDD Timer Data Bits 0-7 Name 0 0 Description VDD Timer Data, bits 0-7. An LSBit is equivalent to 1 second of the VDD power being active (ON). 9.3.22 VDD Active Timer 1 Register (VDD_ON_TMR_1) This register holds a copy of bits 8-15 of the VDD Active Timer. It is reset by hardware to 00h. Power Well: VPP Location: Bank 1, Offset 11h Type: RO Bit 7 6 5 3 2 1 0 0 0 0 2 1 0 0 0 0 VDD Timer Data Bits 8-15 Name Reset 0 0 0 Bit 7-0 4 0 0 Description VDD Timer Data, bits 8-15. 9.3.23 VDD Active Timer 2 Register (VDD_ON_TMR_2) This register holds a copy of bits 16-23 of the VDD Active Timer. It is reset by hardware to 00h. Power Well: VPP Location: Bank 1, Offset 12h Type: RO Bit 7 6 5 Reset 0 0 Bit 7-0 4 3 VDD Timer Data Bits 16-23 Name 0 0 0 Description VDD Timer Data, bits 16-23. 195 www.national.com 9.0 System Wake-Up Control (SWC) (Continued) 9.3.24 VDD Active Timer 3 Register (VDD_ON_TMR_3) This register holds a copy of bits 24-31 of the VDD Active Timer. Whenever the VDD_ON_TMR_3 register is read, the updating of all four VDD_ON_TMR_0 to VDD_ON_TMR_3 registers is resumed. Therefore, this register must be read last. It is reset by hardware to 00h. Power Well: VPP Location: Bank 1, Offset 13h Type: RO Bit 7 6 5 Reset 0 0 0 Bit 7-0 4 3 2 1 0 0 0 0 VDD Timer Data Bits 24-31 Name 0 0 Description VDD Timer Data, bits 24-31. 9.3.25 VSB Active Timer 0 Register (VSB_ON_TMR_0) This register holds a copy of bits 0-7 of the VSB Active Timer. Whenever the VSB_ON_TMR_0 register is read, the updating of all four VSB_ON_TMR_0 to VSB_ON_TMR_3 registers is stopped, freezing the count value. Therefore, this register must be read first. It is reset by hardware to 00h. Power Well: VPP Location: Bank 1, Offset 14h Type: RO Bit 7 6 5 3 2 1 0 0 0 0 VSB Timer Data Bits 0-7 Name Reset 0 0 0 Bit 7-0 4 0 0 Description VSB Timer Data, bits 0-7. An LSBit is equivalent to 1 second of the VDD power being active (ON). 9.3.26 VSB Active Timer 1 Register (VSB_ON_TMR_1) This register holds a copy of bits 8-15 of the VSB Active Timer. It is reset by hardware to 00h. Power Well: VPP Location: Bank 1, Offset 15h Type: RO Bit 7 6 5 3 2 1 0 0 0 0 VSB Timer Data Bits 8-15 Name Reset 0 0 Bit 7-0 4 0 0 Description VSB Timer Data, bits 8-15. www.national.com 196 0 9.0 System Wake-Up Control (SWC) (Continued) 9.3.27 VSB Active Timer 2 Register (VSB_ON_TMR_2) This register holds a copy of bits 16-23 of the VSB Active Timer. It is reset by hardware to 00h. Power Well: VPP Location: Bank 1, Offset 16h Type: RO Bit 7 6 5 Reset 0 0 0 Bit 7-0 4 3 2 1 0 0 0 0 VSB Timer Data Bits 16-23 Name 0 0 Description VSB Timer Data, bits 16-23. 9.3.28 VSB Active Timer 3 Register (VSB_ON_TMR_3) This register holds a copy of bits 24-31 of the VSB Active Timer. Whenever the VSB_ON_TMR_3 register is read, the updating of all four VSB_ON_TMR_0 to VSB_ON_TMR_3 registers is resumed. Therefore, this register must be read last. It is reset by hardware to 00h. Power Well: VPP Location: Bank 1, Offset 17h Type: Bit RO 7 6 5 Reset 0 0 Bit 7-0 4 3 2 1 0 0 0 0 VSB Timer Data Bits 24-31 Name 0 0 0 Description VSB Timer Data, bits 24-31. 197 www.national.com 9.0 System Wake-Up Control (SWC) (Continued) 9.3.29 Power Active Timers Control Register (PWTMRCTL) This register controls the reset by software of the VDD and VSB Active Timers. It is reset by hardware to 00h. Power Well: VPP Location: Bank 1, Offset 18h Type: Varies per bit Bit 7 Name LOCK _TMRRST Reset 0 Bit 7 4 3 Reserved 0 0 0 0 2 1 0 VSB_TMR _RST Reserved VDD_TMR _RST 0 0 0 Description R/W1S LOCK_TMRRST (Lock Timers Reset). When set to 1, this bit locks the VSB_TMR_RST and VDD_TMR_RST bits by disabling the writing to them (including to the LOCK_TMRRST bit itself). Once set, this bit can be cleared either by VDD Power-Up reset (or Hardware reset) or by VSB Power-Up reset, according to the VSBLOCK bit in the ACBLKCTL register (see Section 6.3.4 on page 127). In addition, this bit is cleared by setting the UNLOCKS bit in the ACBLKCTL register (PC87413 and PC87417). 0: R/W bits are enabled for write (default) 1: All bits are RO Reserved. R/W or VSB_TMR_RST (VSB Active Timer Reset). Writing `1' to this bit resets the VSB Active Timer (the timer RO is reset within 1 second following the write). This bit then returns to `0' (read always returns `0'). 0: Inactive (default) 1: Reset the VSB Active Timer 1 0 5 Type 6-3 2 6 Reserved. R/W or VDD_TMR_RST (VDD Active Timer Reset). Writing `1' to this bit resets the VDD Active Timer (the timer RO is reset within 1 second following the write). This bit then returns to `0' (read always returns `0'). 0: Inactive (default) 1: Reset the VDD Active Timer 9.3.30 S0 to S5 Sleep Type Encoding Registers (S0_SLP_TYP to S5_SLP_TYP) These registers hold the system Sleep Type encoding for each sleep state: Working (G0/S0), Sleeping (G1/S1-S4) and Soft-off (G2/S5). The Sleep Type is defined by the SLP_TYPx field of the PM1b_CNT_HIGH register (see Section 9.4.7 on page 207). These registers are reset by hardware to 00h. Power Well: VPP Location: Bank 2, Offset 10h to 15h Type: R/W or RO Bit 7 6 0 0 Name 5 4 3 2 0 0 0 Reserved Reset Bit 0 1 0 SLP_TYP_ENC 0 0 Description 7-3 Reserved. 2-0 SLP_TYP_ENC (Sleep Type Encoding). The value used by the system for the sleep state defined by the specific register. This value must always be set after VPP reset (default = 000b). For sleep states not supported by the system, select an unused value. www.national.com 198 9.0 System Wake-Up Control (SWC) (Continued) 9.3.31 Sleep State Configuration Register (SLP_ST_CFG) This register controls the operation of the Sleep Type encoding. It is reset by hardware to 00h. Power Well: VPP Location: Bank 2, Offset 16h Type: Varies per bit Bit 7 Name LOCK _SLP_ENC Reset 0 Bit 7 6-3 6 5 4 3 Reserved 0 0 0 Type 0 2 1 0 EXT_ST _SELECT S3I _VDD_ON S4 _SELECT 0 0 0 Description R/W1S LOCK_SLP_ENC (Lock Sleep Type Encoding). When set to 1, this bit locks the S0_SLP_TYP to S5_SLP_TYP and the SLP_ST_CFG registers by disabling the writing to them (including to the LOCK_SLP_ENC bit itself). Once set, this bit can be cleared either by VDD Power-Up reset (or Hardware reset) or by VSB Power-Up reset, according to the VSBLOCK bit in the ACBLKCTL register (see Section 6.3.4 on page 127). In addition, this bit is cleared by setting the UNLOCKS bit in the ACBLKCTL register (PC87413 and PC87417). 0: R/W bits are enabled for write (default) 1: All bits are RO Reserved. 2 R/W or EXT_ST_SELECT (External Sleep State Select). Selects the source of the current sleep states. RO 0: SLP_TYPx field in the PM1b_CNT_HIGH register (see Section 9.4.7 on page 207); (default) 1: SLPS3 and SLPS5 signals from an external ACPI controller (see also the EXTSTMUX bit in the SIOCF3 register, Section 3.7.4 on page 50) 1 R/W or S3I_VDD_ON (VDD-ON in S3I Select). Selects the state of the VDD power supply in the S3I current RO sleep state. 0: VDD power supply OFF (default) 1: VDD power supply ON 0 R/W or S4_SELECT (S4 Select). Selects whether the sleep state S4 (if supported) is included in either S3I or RO S45 current sleep states. 0: S45 = S5 or S4 (default) 1: S3I = S3 or S4 199 www.national.com 9.0 System Wake-Up Control (SWC) (Continued) 9.3.32 ACPI Configuration Register (ACPI_CFG) This register configures some of the ACPI wake-up events and the PWBTOUT operation mode. It is reset by hardware to 00h. Power Well: VPP Location: Bank 2, Offset 17h Type: R/W Bit 7 Name PWBTOUT _MODE Reset 0 6 5 4 3 Reserved 0 0 0 0 2 1 0 RTC_EV _DIS SLPBTN _EV_DIS PWRBTN _EV_DIS 0 0 0 Bit Description 7 PWBTOUT_MODE (PWBTOUT Mode). When reset, this bit enables the pulsing of the PWBTOUT pin whenever an enabled wake-up event occurs. 0: PWBTOUT pulsed by (default): -- PWBTIN activation -- Crowbar condition -- Wake-Up events 1: PWBTOUT pulsed by: -- PWBTIN activation -- Crowbar condition 6-3 Reserved. 2 RTC_EV_DIS (RTC Event Disable). Disables the RTC alarm event to the PM1b_STS_HIGH and PM1b_EN_HIGH, ACPI registers (RTC_STS = 0, RTC_EN = 0). However, the RTC_EVT_STS bit in the GPE1_STS_3 register and the RTC_EVT_EN bit in the GPE1_EN_3 register are not affected. 0: Disable event (default) 1: Enable the RTC alarm event 1 SLPBTN_EV_DIS (Sleep Button Event Disable). Enables the Sleep button pressing event to the PM1b_STS_HIGH and PM1b_EN_HIGH ACPI registers (SLPBTN_STS = 0, SLPBTN_EN = 0). The SLBT_EVT_STS bit in the GPE1_STS_2 register and the SLBT_EVT_EN bit in the GPE1_EN_2 register are not affected. 0: Disable event (default) 1: Enable Sleep button pressing event 0 PWRBTN_EV_DIS (Power Button Event Disable). Enables the Power button pressing event to the PM1b_STS_HIGH and PM1b_EN_HIGH ACPI registers (PWRBTN_STS = 0, PWRBTN_EN = 0). The PWBT_EVT_STS bit in the GPE1_STS_2 register and the PWBT_EVT_EN bit in the GPE1_EN_2 register are not affected. 0: Disable event (default) 1: Enable Power button pressing event www.national.com 200 9.0 System Wake-Up Control (SWC) (Continued) 9.3.33 WATCHDOG Control Register (WDCTL) This register contains the control bits for the WATCHDOG. It is reset by hardware to 00h. Power Well: VSB Location: Bank 3, Offset 10h Type: Varies per bit Bit 7 Name SW_WD _TRG Reset 0 6 5 4 3 2 1 Reserved 0 0 0 0 WDEN 0 0 0 0 Bit Type Description 7 R/W SW_WD_TRG (Software WATCHDOG Trigger). Writing `1' to this bit triggers the WATCHDOG to start a new count. This bit then returns to `0' (read always returns `0'). 0: Inactive (default) 1: Triggers a new WATCHDOG count 6-1 0 Reserved. R/W1S WDEN (WATCHDOG Enable). When set to 1, this bit enables the WATCHDOG function. Once set, this bit can be cleared either by VDD Power-Up reset, or by VSB Power-Up reset. 0: WATCHDOG disabled (default) 1: WATCHDOG enabled 9.3.34 WATCHDOG Time-Out Register (WDTO) This register contains the WATCHDOG time-out period. It is reset by hardware to 01h. Power Well: VSB Location: Bank 3, Offset 11h Type: Bit R/W 7 6 5 0 0 0 3 2 1 0 0 0 1 WATCHDOG Time-Out Data Name Reset 4 0 0 Bit Description 7-0 WATCHDOG Time-Out Data. The load value for the WATCHDOG down counter. The value defines the timeout in minutes for a span of: 1 to 255 minutes. The 00h value is reserved. 201 www.national.com 9.0 System Wake-Up Control (SWC) (Continued) 9.3.35 WATCHDOG Configuration Register (WDCFG) This register contains the enable bits for the WATCHDOG trigger sources. Reset all the bits before writing a new value to the WDTO register. It is reset by hardware to 00h. Power Well: VSB Location: Bank 3, Offset 12h Type: R/W Bit 7 Name SW_WD _TREN Reset 0 6 5 4 Reserved 0 0 3 2 1 0 SER2_IRQ _TREN SER1_IRQ _TREN MS_IRQ _TREN KBD_IRQ _TREN 0 0 0 0 0 Bit Description 7 SW_WD_TREN (Software WATCHDOG Trigger Enable). Enables the event of the software writing a `1' to the SW_WD_TRG bit in the WDCTL register (see Section 9.3.33) to trigger the WATCHDOG to start a new count. 0: Disable trigger (default) 1: Enable trigger by the SW_WD_TRG bit in the WDCTL register 6-4 Reserved. 3 SER2_IRQ_TREN (Serial Port 2 IRQ, WATCHDOG Trigger Enable). Enables an active IRQ from the Serial Port 2 to trigger the WATCHDOG to start a new count. 0: Disable trigger (default) 1: Enable trigger by an active IRQ from the Serial Port 2 2 SER1_IRQ_TREN (Serial Port 1 IRQ, WATCHDOG Trigger Enable). Enables an active IRQ from the Serial Port 1 to trigger the WATCHDOG to start a new count. 0: Disable trigger (default) 1: Enable trigger by an active IRQ from the Serial Port 1 1 MS_IRQ_TREN (Mouse IRQ, WATCHDOG Trigger Enable). Enables an active IRQ from the mouse interface section of the KBC module to trigger the WATCHDOG to start a new count. 0: Disable trigger (default) 1: Enable trigger by an active IRQ from the mouse interface section of the KBC module 0 KBD_IRQ_TREN (Keyboard IRQ, WATCHDOG Trigger Enable). Enables an active IRQ from the keyboard interface section of the KBC module to trigger the WATCHDOG to start a new count. 0: Disable trigger (default) 1: Enable trigger by an active IRQ from the keyboard interface section of the KBC module www.national.com 202 9.0 System Wake-Up Control (SWC) (Continued) 9.4 ACPI REGISTERS The ACPI registers are organized in three groups, all of which are VSB powered. The offsets are related to the base address determined by the Base Address registers at indexes 62h - 67h in the SWC device configuration. The PC8741x devices support the following ACPI fixed register groups: * * * PM1 Event Group (block b), containing the PM1b_STS and PM1b_EN registers, each with a length of two bytes. PM1 Control Group (block b), containing the PM1b_CNT register with a length of 2 bytes. General-Purpose Event 1 Group, containing the GPE1_STS and GPE1_EN registers, each with a length of four bytes. The following abbreviations are used to indicate the Register Type: R/W = Read/Write. R = Read from a specific register (write to the same address is to a different register). W = Write (see above). RO = Read Only. WO = Write Only. Reading from the bit returns 0. R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect. R/W1S = Read/Write 1 to Set. Writing 1 to a bit sets its value to 1. Writing 0 has no effect. 9.4.1 ACPI Register Map The following table lists the ACPI registers. All these registers are VSB powered. Base Registers At index 62h, 63h At index 64h, 65h At index 66h, 67h Offset Mnemonic Register Name Type Power Well Section 00h PM1b_STS_LOW PM1 Status Low Register RO VSB 9.4.2 01h PM1b_STS_HIGH PM1 Status High Register R/W1C VSB 9.4.3 02h PM1b_EN_LOW PM1 Enable Low Register RO VSB 9.4.4 03h PM1b_EN_HIGH PM1 Enable High Register R/W VSB 9.4.5 00h PM1b_CNT_LOW PM1 Control Low Register RO VSB 9.4.6 01h PM1b_CNT_HIGH PM1 Control High Register Varies per bit VSB 9.4.7 00h GPE1_STS_0 General-Purpose Status 1 Register 0 R/W1C VSB 9.4.8 01h GPE1_STS_1 General-Purpose Status 1 Register 1 R/W1C VSB 9.4.9 02h GPE1_STS_2 General-Purpose Status 1 Register 2 R/W1C VSB 9.4.10 03h GPE1_STS_3 General-Purpose Status 1 Register 3 R/W1C VSB 9.4.11 04h GPE1_EN_0 General-Purpose Enable 1 Register 0 R/W VSB 9.4.12 05h GPE1_EN_1 General-Purpose Enable 1 Register 1 R/W VSB 9.4.13 06h GPE1_EN_2 General-Purpose Enable 1 Register 2 R/W VSB 9.4.14 07h GPE1_EN_3 General-Purpose Enable 1 Register 3 R/W VSB 9.4.15 203 www.national.com 9.0 System Wake-Up Control (SWC) 9.4.2 (Continued) PM1 Status Low Register (PM1b_STS_LOW) This register contains the eight low bits of the PM1_STS register. The PC8741x devices contain the block `b' instance of the PM1_STS register. This register belongs to the PM1 Event Group of the ACPI fixed-feature space registers. PM1_STS register bits that are specified by the ACPI but not implemented in the PC8741x devices have a `0' value. Power Well: VSB Location: Offset 00h Type: RO Bit 7 Name 6 Reserved Reset 0 0 5 4 GBL_STS BM_STS 0 0 Bit 7-6 3 0 TMR_STS 0 0 Reserved. 4 BM_STS (Bus Master Status). Not implemented. Always at `0'. 9.4.3 0 0 Description GBL_STS (Global Lock Status). Not implemented. Always at `0'. 0 1 Reserved 5 3-1 2 Reserved. TMR_STS (PM Timer Status). Not implemented. Always at `0'. PM1 Status High Register (PM1b_STS_HIGH) This register contains the eight high bits of the PM1_STS register. The PC8741x devices contain the block `b' instance of the PM1_STS register. This register belongs to the PM1 Event Group of the ACPI fixed-feature space registers. PM1_STS register bits that are specified by the ACPI but not implemented in the PC8741x devices have a `0' value. All the implemented status bits behave according to the Sticky Status Bit definition (the bit is set by the HIGH level of the hardware signal and is only cleared by the software writing `1' to it) in the ACPI Specification. Power Well: VSB Location: Offset 01h Type: R/W1C Bit 7 Name 6 WAK_STS Reset 0 5 4 Reserved 0 0 3 2 1 0 Ignored RTC_STS SLPBTN _STS PWRBTN _STS 0 0 0 0 0 Bit Description 7 WAK_STS (Wake-up Event Status). Indicates that a power management event, enabled to generate SCI, has occurred. This bit is set only if the system is in a sleep state (S1-S5). Writing `1' while the system is in the working state (S0), clears this bit; writing `0' is ignored. When the system is in a sleep state (S1-S5) and an enabled event is active, writing `1' does not clear the WAK_STS bit. 0: Inactive (default) 1: At least one event enabled to SCI was active while the system was in a sleep state (S1-S5), since this bit was last cleared 6-4 3 Reserved. Ignored. The data written is ignored; the data read is undefined. www.national.com 204 9.0 System Wake-Up Control (SWC) (Continued) Bit Description 2 RTC_STS (RTC Event Status). Indicates that an enabled RTC alarm has occurred. This bit is set by the RTC alarm becoming active. Writing `1' clears this bit and the RTC_EVT_STS bit in the GPE1_STS_3 register; writing `0' is ignored. This bit is forced to `0' when the RTC_EV_DIS bit in the ACPI_CFG register is reset to `0', ignoring any RTC alarm. 0: Inactive (default) 1: An RTC alarm has occurred 1 SLPBTN_STS (Sleep Button Event Status). Indicates that the Sleep button was pressed. This feature is compatible with the ACPI model for a two-button system. The SLBTIN signal is internally debounced. Writing `1' clears this bit and the SLBT_EVT_STS bit in the GPE1_STS_2 register; writing `0' is ignored. This bit is forced to `0' when the SLPBTN_EV_DIS bit in the ACPI_CFG register is reset to `0', ignoring any Sleep button event. 0: Inactive (default) 1: The Sleep button was pressed 0 PWRBTN_STS (Power Button Event Status). Indicates that the Power button was pressed. This feature is compatible with the ACPI model for both a single-button and a two-button system. The PWBTIN signal is internally debounced. Writing `1' clears this bit and the PWBT_EVT_STS bit in the GPE1_STS_2 register; writing `0' is ignored. This bit is forced to `0' when the PWRBTN_EV_DIS bit in the ACPI_CFG register is reset to `0', ignoring any Power button event. This bit is also cleared in Legacy Power Button mode (LEGACY_PWBT = 1 in PWONCTL) when VDD is turned off by pressing the Power button. 0: Inactive (default) 1: The Power button was pressed 9.4.4 PM1 Enable Low Register (PM1b_EN_LOW) This register contains the eight low bits of the PM1_EN register. The PC8741x devices contain the block `b' instance of the PM1_EN register. This register belongs to the PM1 Event Group of the ACPI fixed-feature space registers. PM1_EN register bits that are specified by the ACPI but not implemented in the PC8741x devices have a `0' value. Power Well: VSB Location: Offset 02h Type: RO Bit 7 Name Reserved Reset 0 Bit 7-6 5 4-1 0 6 5 4 3 GBL_EN 0 0 2 1 Reserved 0 0 0 TMR_EN 0 0 0 Description Reserved. GBL_EN (Global Lock Enable). Not implemented. Always at `0'. Reserved. TMR_EN (PM Timer Enable). Not implemented. Always at `0'. 205 www.national.com 9.0 System Wake-Up Control (SWC) 9.4.5 (Continued) PM1 Enable High Register (PM1b_EN_HIGH) This register contains the eight high bits of the PM1_EN register. The PC8741x devices contain the block `b' instance of the PM1_EN register. This register belongs to the PM1 Event Group of the ACPI fixed-feature space registers. PM1_EN register bits that are specified by the ACPI but not implemented in the PC8741x devices have a `0' value. All the implemented enable bits behave according to the Enable Bit definition (the bit is read/write by software) in the ACPI Specification. Power Well: VSB Location: Offset 03h Type: R/W Bit 7 6 Name 4 3 Reserved Reset 0 Bit 7-3 5 0 0 0 0 2 1 0 RTC_EN SLPBTN _EN PWRBTN _EN 0 0 0 Description Reserved. 2 RTC_EN (RTC Event Enable). Enables the RTC alarm to generate a power management interrupt (SIOSCI). This bit is forced to `0' when the RTC_EV_DIS bit in the ACPI_CFG register is reset to `0', disabling any RTC alarm event. 0: Disable SCI (default) 1: Enable SCI from RTC alarm 1 SLPBTN_EN (Sleep Button Event Enable). Enables Sleep button pressing to generate a power management interrupt (SIOSCI). This bit is forced to `0' when the SLPBTN_EV_DIS bit in the ACPI_CFG register is reset to `0', disabling any Sleep button event. 0: Disable SCI (default) 1: Enable SCI from Sleep button pressing 0 PWRBTN_EN (Power Button Event Enable). Enables Power button pressing to generate a power management interrupt (SIOSCI) when the system is in the active state (S0). This bit does not influence SCI generation when the system is in a sleep state (S1-S5). This bit is forced to `0' when the PWRBTN_EV_DIS bit in the ACPI_CFG register is reset to `0', disabling any Power button event. 0: Disable SCI (default) 1: Enable SCI from Power button pressing www.national.com 206 9.0 System Wake-Up Control (SWC) 9.4.6 (Continued) PM1 Control Low Register (PM1b_CNT_LOW) This register contains the eight low bits of the PM1_CNT register. The PC8741x devices contain the block `b' instance of the PM1_CNT register. This register belongs to the PM1 Control Group of the ACPI fixed-feature space registers. PM1_CNT register bits that are specified by the ACPI but not implemented in the PC8741x devices have a `0' value. Power Well: VSB Location: Offset 00h Type: RO Bit 7 6 Name 5 3 Reserved Reset 0 0 0 Bit 7-3 4 0 2 1 0 GBL_RLS BM_RLD SCI_EN 0 0 0 0 Description Reserved. 2 GBL_RLS (Global Lock Release). Not implemented. Always at `0'. 1 BM_RLD (Bus Master Request Control). Not implemented. Always at `0'. 0 SCI_EN (SCI Enable). Not implemented. Always at `0'. 9.4.7 PM1 Control High Register (PM1b_CNT_HIGH) This register contains the eight high bits of the PM1_CNT register. The PC8741x devices contain the block `b' instance of the PM1_CNT register. This register belongs to the PM1 Control Group of the ACPI fixed-feature space registers. PM1_CNT register bits that are specified by the ACPI but not implemented in the PC8741x devices have a `0' value. All the implemented control bits behave according to the Control bit definition (the bit is read/write by software) and Write-Only Control Bit definition (the bit is written by software; when read, it returns 0) in the ACPI Specification. Power Well: VSB Location: Offset 01h Type: Varies per bit Bit 7 Name 6 Reserved Reset 0 5 4 SLP_EN 0 0 3 2 SLP_TYPx 0 0 0 1 0 Ignored Reserved 0 0 Bit Type Description 7-6 - 5 WO SLP_EN (Sleep Enable). Setting this bit causes the PC8741x device to accept the value of SLP_TYPx as the system state code. This bit may be set in the same write cycle with a new SLP_TYPx value. 0: Inactive (default) 1: Update the system state code from the SLP_TYPx value 4-2 R/W SLP_TYPx (Sleep Type). This field defines the system sleep state type (encoded). The states supported by the PC8741x devices are: Working (G0/S0), Sleeping (G1/S1-S4) and Soft-off (G2/S5). The encoding of the sleep state is programmed through the VPP-powered registers S0_SLP_TYP to S5_SLP_TYP. Reserved. Bits 210 000 xxx Function Encoded 3-bit value for state Sn (n = 0-5); (default) Encoded 3-bit value (except 000b) for the remaining 5 sleep states: Sn (n = 0-5) 1 - Ignored. The data written is ignored; the data read is undefined. 0 - Reserved. 207 www.national.com 9.0 System Wake-Up Control (SWC) 9.4.8 (Continued) General-Purpose Status 1 Register 0 (GPE1_STS_0) This register contains bits 0-7 of the GPE1_STS register. This register belongs to the General-Purpose Event 1 Group of the ACPI fixed-feature space registers. The status bits behave according to the Sticky Status Bit definition (the bit is set by the HIGH level of the hardware signal and is only cleared by the software writing `1' to it) in the ACPI Specification. Power Well: VSB Location: Offset 00h Type: R/W1C Bit 7 6 5 4 3 2 1 0 Name GPIOE17 _STS GPIOE16 _STS GPIOE15 _STS GPIOE14 _STS GPIOE13 _STS GPIOE12 _STS GPIOE11 _STS GPIOE10 _STS Reset 0 0 0 0 0 0 0 0 Bit Description 7 GPIOE17_STS (GPIOE17 Event Status). Indicates that an active event has been detected at pin 7 of the GPIOE Port 1. The event has programmable polarity and the debounce option (see Section 7.3.1 on page 136). The bit is set by an active level at the GPIOE17 pin. Writing `1' clears this bit; writing `0' is ignored. 0: Inactive since last cleared (default) 1: An active event has occurred 6-0 9.4.9 GPIOE16_STS to GPIOE10_STS (GPIOE16 to GPIOE10 Event Status). Same as above for pins 6-0 of the GPIOE Port 1. General-Purpose Status 1 Register 1 (GPE1_STS_1) This register contains bits 8-15 of the GPE1_STS register. This register belongs to the General-Purpose Event 1 Group of the ACPI fixed-feature space registers. The status bits behave according to the Sticky Status Bit definition (the bit is set by the HIGH level of the hardware signal and is only cleared by the software writing `1' to it) in the ACPI Specification. Power Well: VSB Location: Offset 01h Type: R/W1C Bit 7 6 5 4 3 2 1 0 Name GPIOE47 _STS GPIOE46 _STS GPIOE45 _STS GPIOE44 _STS GPIOE43 _STS GPIOE42 _STS GPIOE41 _STS GPIOE40 _STS Reset 0 0 0 0 0 0 0 0 Bit Description 7 GPIOE47_STS (GPIOE47 Event Status). Indicates that an active event has been detected at pin 7 of the GPIOE Port 4. The event has programmable polarity and the debounce option (see Section 7.3.1 on page 136). The bit is set by an active level at the GPIOE47 pin. Writing `1' clears this bit; writing `0' is ignored. 0: Inactive since last cleared (default) 1: An active event has occurred 6-0 GPIOE46_STS to GPIOE40_STS (GPIOE46 to GPIOE40 Event Status). Same as above for pins 6-0 of the GPIOE Port 4. www.national.com 208 9.0 System Wake-Up Control (SWC) (Continued) 9.4.10 General-Purpose Status 1 Register 2 (GPE1_STS_2) This register contains bits 16-23 of the GPE1_STS register. This register belongs to the General-Purpose Event 1 Group of the ACPI fixed-feature space registers. The status bits behave according to the Sticky status bit definition (the bit is set by the HIGH level of the hardware signal and is only cleared by the software writing `1' to it) in the ACPI Specification. Power Well: VSB Location: Offset 02h Type: R/W1C Bit 7 Name 6 5 4 3 PWBT_EVT SLBT_EVT KBD_EVT3 KBD_EVT2 KBD_EVT1 _STS _STS _STS _STS _STS Reset 0 0 0 0 0 2 1 0 MS_EVT _STS RI2_EVT _STS RI1_EVT _STS 0 0 0 Bit Description 7 PWBT_EVT_STS (Power Button Event Status). Indicates that the Power button was pressed. This bit is similar to the PWRBTN_STS bit in the PM1b_STS_HIGH register. The PWBTIN signal is internally debounced. Writing `1' clears this bit and the PWRBTN_STS bit in the PM1b_STS_HIGH register; writing `0' is ignored. This bit is also cleared in Legacy Power Button mode (LEGACY_PWBT = 1 in PWONCTL) when VDD is turned off by pressing the Power button. 0: Inactive (default) 1: The Power button was pressed 6 SLBT_EVT_STS (Sleep Button Event Status). Indicates that the Sleep button was pressed. This bit is similar to the SLPBTN_STS bit in the PM1b_STS_HIGH register. The SLBTIN signal is internally debounced. Writing `1' clears this bit and the SLPBTN_STS bit in the PM1b_STS_HIGH register; writing `0' is ignored. 0: Inactive (default) 1: The Sleep button was pressed 5 KBD_EVT3_STS (Keyboard Event 3 Status). Indicates that "PM Key 3" was pressed and that the event was identified by the Keyboard/Mouse Wake-up Detector. This bit is set only if the Keyboard/Mouse Wake-up Detector is in the Power Management Key mode (see Section 9.3.16 on page 192). Writing `1' clears this bit; writing `0' is ignored. 0: Inactive since last cleared (default) 1: The "PM Key 3" key was pressed on the keyboard 4 KBD_EVT2_STS (Keyboard Event 2 Status). Indicates that "PM Key 2" was pressed and that the event was identified by the Keyboard/Mouse Wake-up Detector. This bit is set only if the Keyboard/Mouse Wake-up Detector is in the Power Management Key mode (see Section 9.3.16 on page 192). Writing `1' clears this bit; writing `0' is ignored. 0: Inactive since last cleared (default) 1: The "PM Key 2" key was pressed on the keyboard 3 KBD_EVT1_STS (Keyboard Event 1 Status). This bit indicates that a keyboard event occurred and was identified by the Keyboard/Mouse Wake-up Detector. The event type depends on the selected operation mode for the Keyboard/Mouse Wake-up Detector (see Sections 9.3.16 and 9.3.17 on pages 192ff.): Pressing any key or a sequence of special keys in Special Key Sequence mode. Pressing a sequence of keys in Password mode. Pressing the "PM Key 1" in Power Management Key mode. Writing `1' clears this bit; writing `0' is ignored. 0: Inactive since last cleared (default) 1: A keyboard event occurred 209 www.national.com 9.0 System Wake-Up Control (SWC) (Continued) Bit Description 2 MS_EVT_STS (Mouse Event Status). Indicates that a mouse event occurred and was identified by the Keyboard/Mouse Wake-up Detector (see Section 9.3.17 on page 193). Writing `1' clears this bit; writing `0' is ignored. 0: Inactive since last cleared (default) 1: A mouse event occurred 1 RI2_EVT_STS (RI2 Event Status). Indicates that a telephone ring signal was received at Serial Port 2 and the event was identified by the RI Wake-up Detector. This bit is set by a high-to-low transition at the RI2 pin (see Section 9.2.1 on page 161). Writing `1' clears this bit; writing `0' is ignored. 0: Inactive since last cleared (default) 1: A telephone ring signal was received at the Serial Port 2 0 RI1_EVT_STS (RI1 Event Status). Indicates that a telephone ring signal was received at Serial Port 1 and the event was identified by the RI Wake-up Detector. This bit is set by a high-to low transition at the RI1 pin (see Section 9.2.1 on page 161). Writing `1' clears this bit; writing `0' is ignored. 0: Inactive since last cleared (default) 1: A telephone ring signal was received at the Serial Port 1 9.4.11 General-Purpose Status 1 Register 3 (GPE1_STS_3) This register contains bits 24-31 of the GPE1_STS register. This register belongs to the General-Purpose Event 1 Group of the ACPI fixed-feature space registers. The status bits behave according to the Sticky Status Bit definition (the bit is set by the HIGH level of the hardware signal and is only cleared by the software writing `1' to it) in the ACPI Specification. Power Well: VSB Location: Offset 03h Type: R/W1C Bit 7 6 5 4 3 2 1 0 Name SW_OFF _STS SW_ON _STS WDO_EVT _STS MOD_IRQ _STS MS_IRQ _STS KBD_IRQ _STS P12_EVT _STS RTC_EVT _STS Reset 0 0 0 0 0 0 0 0 Bit Description 7 SW_OFF_STS (Software OFF Event Status). Indicates that the software wrote a `1' to the SW_OFF_CTL bit in the SWC_CTL register to request a VDD power off sequence. Writing `1' clears this bit; writing `0' is ignored. 0: Inactive since last cleared (default) 1: `1' was written to the SW_OFF_CTL bit in the SWC_CTL register 6 SW_ON_STS (Software ON Event Status). Indicates that the software wrote a `1' to the SW_ON_CTL bit in the SWC_CTL register to request a VDD power on sequence. When the VDD power is off, the SW_ON_CTL bit can be written only through the ACCESS.bus (PC87413 and PC87417). Writing `1' clears this bit; writing `0' is ignored. 0: Inactive since last cleared (default) 1: `1' was written to the SW_ON_CTL bit in the SWC_CTL register 5 WDO_EVT_STS (WATCHDOG Event Status). Indicates that WATCHDOG time-out has occurred. Writing `1' clears this bit; writing `0' is ignored. 0: Inactive (default) 1: An WATCHDOG time-out has occurred www.national.com 210 9.0 System Wake-Up Control (SWC) (Continued) Bit Description 4 MOD_IRQ_STS (Modules IRQ Event Status). Indicates that an IRQ was generated by one of the Legacy modules (FDC, Parallel Port, Serial Port 1 and 2) or by the XIRQ pin (PC87416 and PC87417). For Legacy modules IRQ, this bit is set only if the IRQ is enabled for wake-up (bit 4 of the Standard configuration register at index 70h) and the related module is active (see Section 3.2.3 on page 39). For the XIRQ pin, this bit is set only if XIRQ is enabled for wake-up by setting both the IRQEN and the PWUREN bits in the XIRQC register (see Section 5.4.4 on page 109) to `1'. Writing `1' clears this bit; writing `0' is ignored. 0: Inactive since last cleared (default) 1: An enabled IRQ, from one of the Legacy modules or from the XIRQ pin, is active 3 MS_IRQ_STS (Mouse IRQ Event Status). Indicates that an IRQ was generated by the mouse interface section of the KBC module. This bit is set only if the IRQ is enabled for wake-up (bit 4 of the Mouse Logical Device configuration register at index 70h) and the KBC module is active (see Section 3.2.3 on page 39). Writing `1' clears this bit; writing `0' is ignored. 0: Inactive since last cleared (default) 1: An enabled IRQ, from the mouse interface section of the KBC module, is active 2 KBD_IRQ_STS (Keyboard IRQ Event Status). Indicates that an IRQ was generated by the keyboard interface section of the KBC module. This bit is set only if the IRQ is enabled for wake-up (bit 4 of the Keyboard Logical Device configuration register at index 70h) and the KBC module is active (see Section 3.2.3 on page 39). Writing `1' clears this bit; writing `0' is ignored. 0: Inactive since last cleared (default) 1: An enabled IRQ, from the keyboard interface section of the KBC module, is active 1 P12_EVT_STS (Port P12 Event Status). Indicates that an active high signal was generated by the KBC module, at the P12 pin. This bit is set only if the KBC module is active (see Section 3.2.3 on page 39). Writing `1' clears this bit; writing `0' is ignored. 0: Inactive since last cleared (default) 1: An active high signal at the P12 pin was generated by the KBC module 0 RTC_EVT_STS (RTC Alarm Event Status). Indicates that an enabled RTC alarm has occurred. This bit is similar to the RTC_STS bit in the PM1b_STS_HIGH register. Writing `1' clears this bit and the RTC_STS bit in the PM1b_STS_HIGH register; writing `0' is ignored. 0: Inactive (default) 1: An RTC alarm has occurred 211 www.national.com 9.0 System Wake-Up Control (SWC) (Continued) 9.4.12 General-Purpose Enable 1 Register 0 (GPE1_EN_0) This register contains bits 0-7 of the GPE1_EN register. This register belongs to the General-Purpose Event 1 Group of the ACPI fixed-feature space registers. The enable bits behave according to the Enable Bit definition (the bit is read/write by software) in the ACPI Specification. Power Well: VSB Location: Offset 04h Type: R/W Bit 7 6 5 4 3 2 1 0 Name GPIOE17 _EN GPIOE16 _EN GPIOE15 _EN GPIOE14 _EN GPIOE13 _EN GPIOE12 _EN GPIOE11 _EN GPIOE10 _EN Reset 0 0 0 0 0 0 0 0 Bit Description 7 GPIOE17_EN (GPIOE17 Event Enable). Enables an active event at pin 7 of the GPIOE Port 1 to generate a power management interrupt (SIOSCI). 0: Disable SCI (default) 1: Enable SCI 6-0 GPIOE16_EN to GPIOE10_EN (GPIOE16 to GPIOE10 Event Enable). Same as above for pins 6-0 of GPIOE Port 1. 9.4.13 General-Purpose Enable 1 Register 1 (GPE1_EN_1) This register contains bits 8-15 of the GPE1_EN register. This register belongs to the General-Purpose Event 1 Group of the ACPI fixed-feature space registers. The enable bits behave according to the Enable Bit definition (the bit is read/write by software) in the ACPI Specification. Power Well: VSB Location: Offset 05h Type: R/W Bit 7 6 5 4 3 2 1 0 Name GPIOE47 _EN GPIOE46 _EN GPIOE45 _EN GPIOE44 _EN GPIOE43 _EN GPIOE42 _EN GPIOE41 _EN GPIOE40 _EN Reset 0 0 0 0 0 0 0 0 Bit 7 6-0 Description GPIOE47_EN (GPIOE47 Event Enable). Enables an active event at pin 7 of the GPIOE Port 4 to generate a power management interrupt (SIOSCI). 0: Disable SCI (default) 1: Enable SCI GPIOE46_EN to GPIOE40_EN (GPIOE46 to GPIOE40 Event Enable). Same as above for pins 6-0 of the GPIOE Port 4. www.national.com 212 9.0 System Wake-Up Control (SWC) (Continued) 9.4.14 General-Purpose Enable 1 Register 2 (GPE1_EN_2) This register contains bits 16-23 of the GPE1_EN register. This register belongs to the General-Purpose Event 1 Group of the ACPI fixed-feature space registers. The enable bits behave according to the Enable Bit definition (the bit is read/write by software) in the ACPI Specification. Power Well: VSB Location: Offset 06h Type: Bit R/W 7 Name Reset Bit 6 5 4 3 PWBT_EVT SLBT_EVT KBD_EVT3 KBD_EVT2 KBD_EVT1 _EN _EN _EN _EN _EN 0 0 0 0 0 2 1 0 MS_EVT _EN RI2_EVT _EN RI1_EVT _EN 0 0 0 Description 7 PWBT_EVT_EN (Power Button Event Enable). Enables Power button pressing to generate a power management interrupt (SIOSCI). This bit is similar to the PWRBTN_EN bit in the PM1b_EN_HIGH register. It should be enabled only if the system does not support the PM1b_EVT register block. 0: Disable SCI (default) 1: Enable SCI from Power button pressing 6 SLBT_EVT_EN (Sleep Button Event Enable). Enables Sleep button pressing to generate a power management interrupt (SIOSCI). This bit is similar to the SLPBTN_EN bit in the PM1b_EN_HIGH register. It should be enabled only if the system does not support the PM1b_EVT register block. 0: Disable SCI (default) 1: Enable SCI from Sleep button pressing 5 KBD_EVT3_EN (Keyboard Event 3 Enable). Enables the event of pressing "PM Key 3" (on the keyboard) to generate a power management interrupt (SIOSCI). 0: Disable SCI (default) 1: Enable SCI from pressing the "PM Key 3" on the keyboard 4 KBD_EVT2_EN (Keyboard Event 2 Enable). Enables the event of pressing "PM Key 2" (on the keyboard) to generate a power management interrupt (SIOSCI). 0: Disable SCI (default) 1: Enable SCI from pressing the "PM Key 2" on the keyboard 3 KBD_EVT1_EN (Keyboard Event 1 Enable). Enables the event of pressing any key, key sequence or "PM Key 1" (on the keyboard) to generate a power management interrupt (SIOSCI). 0: Disable SCI (default) 1: Enable SCI from pressing a sequence of keys or the "PM Key 1" on the keyboard 2 MS_EVT_EN (Mouse Event Enable). Enables a mouse event identified by the Keyboard/Mouse Wake-up Detector to generate a power management interrupt (SIOSCI). 0: Disable SCI (default) 1: Enable SCI from mouse event identified by the Keyboard/Mouse Wake-up Detector 1 RI2_EVT_EN (RI2 Event Enable). Enables a telephone ring received at the Serial Port 2 event, and identified by the RI Wake-up Detector, to generate a power management interrupt (SIOSCI). 0: Disable SCI (default) 1: Enable SCI from telephone ring event received at the Serial Port 2 0 RI1_EVT_EN (RI1 Event Enable). Enables a telephone ring received at the Serial Port 1 event, and identified by the RI Wake-up Detector, to generate a power management interrupt (SIOSCI). 0: Disable event (default) 1: Enable SCI from telephone ring event received at the Serial Port 1 213 www.national.com 9.0 System Wake-Up Control (SWC) (Continued) 9.4.15 General-Purpose Enable 1 Register 3 (GPE1_EN_3) This register contains bits 24-31 of the GPE1_EN register. This register belongs to the General-Purpose Event 1 Group of the ACPI fixed-feature space registers. The enable bits behave according to the Enable Bit definition (the bit is read/write by software) in the ACPI Specification. Power Well: VSB Location: Offset 07h Type: R/W Bit 7 6 5 4 3 2 1 0 Name SW_OFF _EN SW_ON _EN WDO_EVT _EN MOD_IRQ _EN MS_IRQ _EN KBD_IRQ _EN P12_EVT _EN RTC_EVT _EN Reset 0 0 0 0 0 0 0 0 Bit Description 7 SW_OFF_EN (Software OFF Event Enable). Enables the event of the software writing a `1' to the SW_OFF_CTL bit in the SWC_CTL register to generate a power management interrupt (SIOSCI). 0: Disable SCI (default) 1: Enable SCI from the software writing a `1' to the SW_OFF_CTL bit in the SWC_CTL register 6 SW_ON_EN (Software ON Event Enable). Enables the event of the software writing a `1' to the SW_ON_CTL bit in the SWC_CTL register to generate a power management interrupt (SIOSCI). 0: Disable SCI (default) 1: Enable SCI from the software writing a `1' to the SW_ON_CTL bit in the SWC_CTL register 5 WDO_EVT_EN (WATCHDOG Event Enable). Enables an WATCHDOG time-out event to generate a power management interrupt (SIOSCI). 0: Disable SCI (default) 1: Enable SCI from WATCHDOG time-out 4 MOD_IRQ_EN (Modules IRQ Event Enable). Enables an active IRQ from one of the Legacy modules or from the XIRQ pin (PC87413 and PC87417) to generate a power management interrupt (SIOSCI). 0: Disable SCI (default) 1: Enable SCI by an active IRQ from one of the Legacy modules or from the XIRQ pin 3 MS_IRQ_EN (Mouse IRQ Event Enable). Enables an IRQ generated by the mouse interface section of the KBC module to generate a power management interrupt (SIOSCI). 0: Disable SCI (default) 1: Enable SCI from an IRQ generated by the mouse interface section of the KBC module 2 KBD_IRQ_EN (Keyboard IRQ Event Enable). Enables an IRQ generated by the keyboard interface section of the KBC module to generate a power management interrupt (SIOSCI). 0: Disable SCI (default) 1: Enable SCI from an IRQ generated by the keyboard interface section of the KBC module 1 P12_EVT_EN (Port P12 Event Enable). Enables an IRQ by an active high signal generated at the P12 pin to generate a power management interrupt (SIOSCI). 0: Disable SCI (default) 1: Enable SCI from an active high signal generated at the P12 pin 0 RTC_EVT_EN (RTC Alarm Event Enable). Enables an RTC alarm to generate a power management interrupt (SIOSCI). This bit is similar to the RTC_EN bit in the PM1b_EN_HIGH register. It should be enabled only if the system does not support the PM1b_EVT register block. 0: Disable SCI (default) 1: Enable SCI from RTC alarm www.national.com 214 9.0 System Wake-Up Control (SWC) (Continued) 9.5 SYSTEM WAKE-UP CONTROL REGISTERS BITMAP Table 51. Banks 0, 1, 2 and 3 - Common Register Map Bits Register Offset Mnemonic 00h WK_EVT_SEL 01h WK_ST_EN 02h GPE1_2IRQ PWBT_ SLBT_ KBD_EVT3 KBD_EVT2 KBD_EVT1 _LOW EVT_2IRQ EVT_2IRQ _2IRQ _2IRQ _2IRQ 03h GPE1_2IRQ _HIGH 04h GPE1_2SMI PWBT_ SLBT_ KBD_EVT3 KBD_EVT2 KBD_EVT1 _LOW EVT_2SMI EVT_2SMI _2SMI _2SMI _2SMI 05h GPE1_2SMI _HIGH 06h SWCFDIS 07h SWCTRIS 08h SWC_CTL SW_OFF _CTL SW_ON _CTL PWB_OVR CROWBAR _STS _STS 09h PWONCTL WAS _PFAIL LAST _ONCTL RESUME_MD 0Ah LEDCTL 0Bh LEDBLNK 0Ch0Dh 7 6 5 4 3 2 Reserved SW_OFF _2SMI PWBT_EN PWBT_EN _S3I _S45 SW_ON _2IRQ SW_ON _2SMI Reserved Reserved MS_EVT _2IRQ Reserved WDO_EVT _2SMI ONCTL _EN_S3I ONCTL _EN_S45 RI2_EVT _2IRQ RI1_EVT _2IRQ P12_EVT _2IRQ Reserved MS_EVT _2SMI RI2_EVT _2SMI RI1_EVT _2SMI RTC_EVT _2SMI Reserved KBDDIS MSDIS Reserved Reserved 0 WKUPSEL Reserved SW_OFF _2IRQ 1 SER1DIS SER2DIS PARPDIS FDCDIS KBMSTRIS SER1TRIS SER2TRIS PARPTRIS FDCTRIS LEDCFG LEDPOL LED2BLNK SWAP _KBMS Reserved LEGACY _PWBT Reserved Reserved CRBAR_TOUT LEDMOD LED1BLNK Reserved 0Eh BIOSGPR 0Fh BANKSEL General-Purpose Scratch Reserved 215 BNK_SEL www.national.com 9.0 System Wake-Up Control (SWC) (Continued) Table 52. Bank 0 - Keyboard/Mouse Wake-Up Detector Register Map Bits Register Offset Mnemonic 7 6 5 4 10h11h 3 2 1 0 Reserved 12h KBDWKCTL KBDMODE Reserved 13h PS2CTL DISPAR EVT3CFG EVT2CFG EVT1CFG MSEVCFG 14h15h KBEVCFG Reserved 16h KDSR Keyboard Data 17h MDSR 18h PS2KEY0 Data Byte of Key 19h PS2KEY1 Data Byte of Key 1Ah PS2KEY2 Data Byte of Key 1Bh PS2KEY3 Data Byte of Key 1Ch PS2KEY4 Data Byte of Key 1Dh PS2KEY5 Data Byte of Key 1Eh PS2KEY6 Data Byte of Key 1Fh PS2KEY7 Data Byte of Key Reserved Mouse Data Table 53. Bank 1 - Power Active Timers Register Map Bits Register Offset Mnemonic 7 6 5 4 3 2 1 0 VSB_TMR _RST Reserved VDD_TMR _RST 10h VDD_ON_ TMR_0 VDD Timer Data Bits 0-7 11h VDD_ON_ TMR_1 VDD Timer Data Bits 8-15 12h VDD_ON_ TMR_2 VDD Timer Data Bits 16-23 13h VDD_ON_ TMR_3 VDD Timer Data Bits 24-31 14h VSB_ON_ TMR_0 VSB Timer Data Bits 0-7 15h VSB_ON_ TMR_1 VSB Timer Data Bits 8-15 16h VSB_ON_ TMR_2 VSB Timer Data Bits 16-23 17h VSB_ON_ TMR_3 VSB Timer Data Bits 24-31 18h PWTMRCTL 19h1Fh www.national.com LOCK _TMRRST Reserved Reserved 216 9.0 System Wake-Up Control (SWC) (Continued) Table 54. Bank 2 - Sleep States and ACPI Configuration Register Map Bits Register Offset Mnemonic 7 6 5 4 10h S0_SLP_TYP Reserved SLP_TYP_ENC 11h S1_SLP_TYP Reserved SLP_TYP_ENC 12h S2_SLP_TYP Reserved SLP_TYP_ENC 13h S3_SLP_TYP Reserved SLP_TYP_ENC 14h S4_SLP_TYP Reserved SLP_TYP_ENC 15h S5_SLP_TYP Reserved SLP_TYP_ENC 16h SLP_ST_CFG LOCK_ SLP_ENC Reserved EXT_ST S3I S4 _SELECT _VDD_ON _SELECT 17h ACPI_CFG PWBTOUT _MODE Reserved RTC_EV _DIS SLPBTN _EV_DIS PWRBTN _EV_DIS 2 1 0 18h1Fh 3 2 1 0 Reserved Table 55. Bank 3 - WATCHDOG Register Map Bits Register Offset Mnemonic 10h WDCTL 11h WDTO 12h WDCFG 7 6 5 4 SW_WD _TRG 3 Reserved WDEN WATCHDOG Time-Out Data SW_WD _TREN SER2_IRQ SER1_IRQ _TREN _TREN Reserved 13h1Fh MS_IRQ _TREN KBD_IRQ _TREN 1 0 Reserved Table 56. ACPI Register Map with Base Address at Index 62h, 63h Bits Register Offset Mnemonic 7 6 5 4 GBL_STS BM_STS 00h PM1b_STS _LOW 01h PM1b_STS WAK_STS _HIGH Reserved 02h PM1b_EN_ LOW GBL_EN 03h PM1b_EN_ HIGH Reserved Reserved 3 2 Reserved Ignored RTC_STS TMR_STS SLPBTN _STS Reserved Reserved RTC_EN 217 PWRBTN _STS TMR_EN SLPBTN _EN PWRBTN _EN www.national.com 9.0 System Wake-Up Control (SWC) (Continued) Table 57. ACPI Register Map with Base Address at Index 64h, 65h Bits Register Offset Mnemonic 00h PM1b_CNT _LOW 01h PM1b_CNT _HIGH 7 6 5 4 3 Reserved Reserved SLP_EN 2 1 0 GBL_RLS BM_RLD SCI_EN Ignored Reserved SLP_TYPx Table 58. ACPI Register Map with Base Address at Index 66h, 67h Bits Register Offset Mnemonic 7 6 5 4 3 2 1 0 00h GPE1_STS _0 GPIOE17 _STS GPIOE16 _STS GPIOE15 _STS GPIOE14 _STS GPIOE13 _STS GPIOE12 _STS GPIOE11 _STS GPIOE10 _STS 01h GPE1 _STS_1 GPIOE47 _STS GPIOE46 _STS GPIOE45 _STS GPIOE44 _STS GPIOE43 _STS GPIOE42 _STS GPIOE41 _STS GPIOE40 _STS 02h GPE1 _STS_2 PWBT_ EVT_STS SLBT_ KBD_ KBD_ KBD_ EVT_STS EVT3_STS EVT2_STS EVT1_STS MS_EVT _STS RI2_EVT _STS RI1_EVT _STS 03h GPE1 _STS_3 SW_OFF _STS SW_ON _STS 04h GPE1 _EN_0 GPIOE17 _EN 05h GPE1 _EN_1 06h 07h WDO_ MOD_IRQ EVT_STS _STS MS_IRQ _STS KBD_IRQ _STS P12_EVT _STS RTC_EVT _STS GPIOE16 _EN GPIOE15 _EN GPIOE14 _EN GPIOE13 _EN GPIOE12 _EN GPIOE11 _EN GPIOE10 _EN GPIOE47 _EN GPIOE46 _EN GPIOE45 _EN GPIOE44 _EN GPIOE43 _EN GPIOE42 _EN GPIOE41 _EN GPIOE40 _EN GPE1 _EN_2 PWBT_EV T_EN SLBT_ EVT_EN KBD_EVT KBD_EVT KBD_EVT 3_EN 2_EN 1_EN MS_EVT _EN RI2_EVT _EN RI1_EVT _EN GPE1 _EN_3 SW_OFF _EN SW_ON _EN KBD_IRQ _EN P12_EVT _EN RTC_EVT _EN www.national.com WDO_ EVT_EN MOD_IRQ _EN 218 MS_IRQ _EN 10.0 Legacy Functional Blocks This chapter briefly describes the following blocks, which provide legacy device functions: Floppy Disk Controller (FDC). Parallel Port (PP). Serial Port 1 and 2 (SP1 and SP2). Keyboard and Mouse Controller (KBC). The description of each Legacy block includes the sections listed below. For details on the general implementation of each legacy block, see the SuperI/O Legacy Functional Blocks datasheet. General Description. Register Map table(s). Bitmap table(s). The register maps in this chapter use the following abbreviations for Type: R/W = Read/Write. R = Read from a specific register (write to the same address is to a different register). W = Write (see above). RO = Read Only. WO = Write Only. Reading from the bit returns 0. R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect. R/W1S = Read/Write 1 to Set. Writing 1 to a bit sets its value to 1. Writing 0 has no effect. 10.1 FLOPPY DISK CONTROLLER (FDC) 10.1.1 General Description The generic FDC is a standard FDC with a digital data separator and is DP8473 and N82077 software compatible. The PC8741x FDC supports 14 of the 17 standard FDC signals described in the generic Floppy Disk Controller (FDC) chapter, including: * FM and MFM modes are supported. To select either mode, set bit 6 of the first command byte when writing to/reading from a diskette, where: -- 0 = FM mode -- 1 = MFM mode * A logic 1 is returned during LPC I/O read cycles by all register bits, reflecting the state of floating (TRI-STATE) FDC pins. Exceptions to standard FDC are: * * Automatic media sense using the MSEN1 signal is not supported. DRATE1 is not supported. Table 59 lists the FDC functional block registers. All registers are VDD powered. Table 59. FDC Registers Offset1 Mnemonic 00h SRA Status A RO 01h SRB Status B RO 02h DOR Digital Output R/W 03h TDR Tape Drive R/W 04h MSR Main Status R DSR Data Rate Select W FIFO Data (FIFO) 05h Register Name 219 Type R/W www.national.com 10.0 Legacy Functional Blocks (Continued) Table 59. FDC Registers (Continued) Offset1 Mnemonic 06h Register Name Type N/A X DIR Digital Input R CCR Configuration Control W 07h 1. From the 8-byte aligned FDC base address. 10.1.2 FDC Bitmap Summary The FDC supports two system operation modes: PC-AT mode and PS/2 mode. Unless specifically indicated otherwise, all fields in all registers are valid in both drive modes. Register Bits Offset Mnemonic 7 6 5 4 3 2 1 0 00h SRA1 IRQ Pending Reserved Step TRK0 Head Select INDEX WP Head Direction 01h SRB1 Drive Select 0 Status WDATA RDATA WGATE MTR1 MTR0 02h DOR Motor Enable 1 Motor Enable 0 DMAEN Reset Controller Reserved Motor Enable 3 Motor Enable 2 TDR 03h Reserved Tape Drive Select 1,0 TDR2 Reserved (must be 1) MSEN0 Drive ID Information MSR RQM Data I/O Direction Non-DMA Command Execution in Progress DSR Software Reset Logical Drive Exchange Drive 3 Busy Drive 2 Busy 04h 05h Low Power Reserved Precompensation Delay Select FIFO Drive Select Tape Drive Select 1,0 Drive 1 Busy Data Transfer Rate Select Data Bits DIR3 DSKCHG DIR1 DSKCHG Reserved 07h 07h CCR Reserved Reserved 1. Applicable only in PS/2 Mode. 2. Applicable only in Enhanced TDR Mode. 3. Applicable only in PC-AT Compatible Mode. www.national.com Drive 0 Busy 220 DRATE 1,0 Status High Density DRATE1,0 10.0 Legacy Functional Blocks (Continued) 10.2 PARALLEL PORT 10.2.1 General Description The Parallel Port supports all IEEE1284 standard communication modes: Compatibility (known also as Standard or SPP). Bi-directional (known also as PS/2). FIFO. EPP (known also as Mode 4). ECP (with an optional Extended ECP mode). 10.2.2 Parallel Port Register Map The Parallel Port includes two groups of runtime registers, as follows: * A group of 21 registers at first level offset, sharing 14 entries. Three of these registers (at offsets 403h, 404h and 405h) are used only in the Extended ECP mode. * A group of four registers, used only in the Extended ECP mode, accessed by a second level offset. EPP and second level offset registers are available only when the base address is 8-byte aligned. The desired mode is selected by the ECR runtime register (offset 402h). The selected mode determines which runtime registers are used and which address bits are used for the base address. See Tables 60 and 61 for a listing of all registers, their offset addresses and the associated modes. All registers are VDD powered. Table 60. Parallel Port Registers at First Level Offset Offset Mnemonic 00h DATAR 0,1 Data AFIFO 3 ECP FIFO (Address) DTR 4 Data (for EPP) R/W DSR 0,1,2,3 Status RO STR 4 Status (for EPP) RO DCR 0,1,2,3 Control R/W CTR 4 Control (for EPP) R/W 03h ADDR 4 EPP Address R/W 04h DATA0 4 EPP Data Port 0 R/W 05h DATA1 4 EPP Data Port 1 R/W 06h DATA2 4 EPP Data Port 2 R/W 07h DATA3 4 EPP Data Port 3 R/W 400h CFIFO DFIFO TFIFO CNFGA 2 3 6 7 PP Data FIFO ECP Data FIFO Test FIFO Configuration A W R/W R/W RO 401h CNFGB 7 Configuration B RO 402h ECR 0,1,2,3 Extended Control R/W 403h 1 EIR 0,1,2,3 Extended Index R/W 404h EDR1 0,1,2,3 Extended Data R/W 405h EAR1 0,1,2,3 Extended Auxiliary Status R/W 01h 02h Mode(s) Register Name Type R/W W 1. These registers are extended to the standard IEEE1284 registers. They are only accessible when enabled by bit 4 of the Parallel Port Configuration register (see Section 3.9.3 on page 61). 221 www.national.com 10.0 Legacy Functional Blocks (Continued) Table 61. Parallel Port Registers at Second Level Offset Offset Mnemonic Register Name Type 00h Control0 Extended Control 0 R/W 02h Control2 Extended Control 1 R/W 04h Control4 Extended Control 4 R/W 05h PP Confg0 Configuration 0 R/W 10.2.3 Parallel Port Bitmap Summary The Parallel Port functional block bitmaps are grouped according to first and second level offsets. Table 62. Parallel Port Bitmap Summary for First Level Offset Register Offset Mnemonic Bits 7 6 5 4 3 DATAR Data Bits AFIFO Address Bits 2 1 0 000h Printer Status ACK Status PE Status SLCT Status ERR Status Reserved EPP Timeout Status Direction Control Interrupt Enable PP Input Control Printer Automatic Initialization Line Feed Control Control Data Strobe Control 001h DSR 002h DCR 003h ADDR EPP Device or Register Selection Address Bits 004h DATA0 EPP Device or R/W Data 005h DATA1 EPP Device or R/W Data 006h DATA2 EPP Device or R/W Data 007h DATA3 EPP Device or R/W Data 400h CFIFO Data Bits 400h DFIFO Data Bits 400h TFIFO Data Bits 400h CNFGA 401h CNFGB 402h ECR 403h EIR 404h EDR 405h EAR www.national.com Reserved Bit 7 of PP Confg0 Reserved Reserved Interrupt Request Value Interrupt Select Reserved DMA Channel Select ECP Mode Control ECP Interrupt Mask ECP Interrupt Service FIFO Full Reserved ECP DMA Enable Reserved FIFO Empty Second Level Offset Data Bits FIFO Tag Reserved 222 10.0 Legacy Functional Blocks (Continued) Table 63. Parallel Port Bitmap Summary for Second Level Offset Register Second Level Mnemonic Offset Bits 7 6 Reserved 5 4 DCR Register Live Freeze Bit Reserved Revision 1.7 or 1.9 Select 00h Control0 02h Control2 SPP Compatibility Channel Address Enable 04h Control4 Reserved PP DMA Request Inactive Time 05h PP Confg0 Bit 3 of CNFGA Demand DMA Enable 3 1 0 EPP Timeout Interrupt Mask Reserved Reserved Reserved ECP IRQ Channel Number 223 2 PP DMA Request Active Time PE Internal Pull-up or Pull-down ECP DMA Channel Number www.national.com 10.0 Legacy Functional Blocks (Continued) 10.3 UART FUNCTIONALITY (SP1 AND SP2) 10.3.1 General Description Both SP1 and SP2 provide UART functionality. The generic SP1 and SP2 support serial data communication with remote peripheral device or modem, using a wired interface. The functional blocks can function as a standard 16450 or 16550 or as an Extended UART. 10.3.2 UART Mode Register Bank Overview Four register banks, each containing eight registers, control UART operation. All registers use the same 8-byte address space to indicate offsets 00h through 07h. The BSR register selects the active bank and is common to all banks (see Figure 52). BANK 3 BANK 2 BANK 1 Common Register Throughout All Banks BANK 0 Offset 07h Offset 06h Offset 05h Offset 04h LCR/BSR Offset 02h Offset 01h Offset 00h 16550 Banks Figure 52. UART Mode Register Bank Architecture 10.3.3 SP1 and SP2 Register Maps for UART Functionality All registers are VDD powered. Table 64. Bank 0 Register Map Offset Mnemonic Register Name Type 00h RXD Receiver Data Port RO 00h TXD Transmitter Data Port W 01h IER Interrupt Enable R/W EIR Event Identification (Read Cycles) RO FCR FIFO Control (Write Cycles) W LCR1 Line Control BSR1 Bank Select 04h MCR Modem/Mode Control R/W 05h LSR Link Status RO 06h MSR Modem Status RO 02h R/W 03h 07h SPR/ASCR Scratchpad/Auxiliary Status and Control 1. When bit 7 of this register is set to 1, bits 6-0 of BSR select the bank. www.national.com 224 R/W 10.0 Legacy Functional Blocks (Continued) Table 65. Bank Selection Encoding BSR Bits 6 5 4 3 2 1 0 Bank Selected 0 x x x x x x x 0 1 0 x x x x x x 1 1 1 x x x x 1 x 1 1 1 x x x x x 1 1 1 1 1 0 0 0 0 0 2 1 1 1 0 0 1 0 0 3 7 Functionality UART (SP1 + SP2) Table 66. Bank 1 Register Map Offset Mnemonic Register Name Type 00h LBGD(L) Legacy Baud Generator Divisor Port (Low Byte) R/W 01h LBGD(H) Legacy Baud Generator Divisor Port (High Byte) R/W 02h 03h Reserved LCR/BSR Line Control/Bank Select 04h - 07h R/W Reserved Table 67. Bank 2 Register Map Offset Mnemonic Register Name 00h BGD(L) Baud Generator Divisor Port (Low Byte) R/W 01h BGD(H) Baud Generator Divisor Port (High Byte) R/W 02h EXCR1 Extended Control1 R/W 03h LCR/BSR Line Control/Bank Select R/W 04h EXCR2 Extended Control2 R/W 05h Type Reserved 06h TXFLV TX_FIFO Level R/W 07h RXFLV RX_FIFO Level R/W Table 68. Bank 3 Register Map Offset Mnemonic 00h MRID 01h Register Name Type Module Revision ID RO SH_LCR Shadow of LCR (Read Only) RO 02h SH_FCR Shadow of FIFO Control (Read Only) RO 03h LCR/BSR Line Control/Bank Select R/W 04h-07h Reserved 225 www.national.com 10.0 Legacy Functional Blocks (Continued) 10.3.4 SP1 and SP2 Bitmap Summary for UART Functionality Table 69. Bank 0 Bitmap Register Offset Mnemonic Bits 7 6 5 4 3 RXD Receiver Data Bits TXD Transmitter Data Bits 2 1 0 00h IER1 Reserved MS_IE LS_IE TXLDL_IE RXHDL_IE TXEMP_IE Reserved MS_IE LS_IE TXLDL_IE RXHDL_IE Reserved RXFT IPR1 TXEMP_EV Reserved MS_EV 01h IER2 EIR1 02h EIR2 Reserved FEN1 FEN0 Reserved IPR0 IPF LS_EV or TXLDL_EV RXHDL_EV TXHLT_EV FCR RXFTH1 RXFTH0 TXFTH1 TXFTH0 Reserved TXSR RXSR FIFO_EN LCR3 BKSE SBRK STKP EPS PEN STB WLS1 WLS0 BSR3 BKSE ISEN or DCDLP RILP RTS DTR TX_DFR Reserved RTS DTR 03h MCR1 Bank Select Reserved LOOP 04h MCR2 Reserved 05h LSR ER_INF TXEMP TXRDY BRK FE PE OE RXDA 06h MSR DCD RI DSR CTS DDCD TERI DDSR DCTS SPR1 Scratch Data 07h ASCR2 Reserved RXF_TOUT 1. Non-Extended Mode. 2. Extended Mode. 3. When bit 7 of this register is set to 1, bits 6-0 of BSR select the bank, as shown in Table 65 on page 225. www.national.com 226 10.0 Legacy Functional Blocks (Continued) Table 70. Bank 1 Bitmap Register Bits Offset Mnemonic 7 6 5 4 00h LBGD(L) Legacy Baud Generator Divisor (Least Significant Bits) 01h LBGD(H) Legacy Baud Generator Divisor (Most Significant Bits) 02h 03h 3 2 1 0 1 0 Reserved LCR/BSR Same as Bank 0 04h07h Reserved Table 71. Bank 2 Bitmap Register Bits Offset Mnemonic 7 00h BGD(L) Baud Generator Divisor Low (Least Significant Bits) 01h BGD(H) Baud Generator Divisor High (Most Significant Bits) 02h EXCR1 03h LCR/BSR 04h EXCR2 05h Reserved BTEST 6 Reserved 5 4 ETDLBK 3 LOOP 2 Reserved EXT_SL Same as Bank 0 LOCK Reserved PRESL1 PRESL0 Reserved 06h TXFLV Reserved TFL4 TFL3 TFL2 TFL1 TFL0 07h RXFLV Reserved RFL4 RFL3 RFL2 RFL1 RFL0 3 2 1 0 Table 72. Bank 3 Bitmap Register Bits Offset Mnemonic 00h MRID 01h SH_LCR BKSE SBRK STKP EPS PEN STB WLS1 WLS0 02h SH_FCR RXFTH1 RXFTH0 TXFHT1 TXFTH0 Reserved TXSR RXSR FIFO_EN 03h LCR/BSR 04h07h 7 6 5 4 Module ID (MID 7-4) Revision ID (RID 3-0) Same as Bank 0 Reserved 227 www.national.com 10.0 Legacy Functional Blocks (Continued) 10.4 KEYBOARD AND MOUSE CONTROLLER (KBC) 10.4.1 General Description The KBC is implemented physically as a single hardware module and houses two separate logical devices: a mouse controller (Logical Device 5) and a keyboard controller (Logical Device 6). The KBC is functionally equivalent to the industry standard 8042A keyboard controller. The 8042A datasheet can be used as a detailed technical reference for the KBC. The hardware KBC module is integrated to provide the following pin functions: P12, P16, P17, KBRST (P20), GA20 (P21), KBDAT, KBCLK, MDAT and MCLK. KBRST and GA20 are implemented as bi-directional open-drain pins. The keyboard and mouse interfaces are implemented as bi-directional open-drain pins. P12, P16 and P17 are implemented as quasi-bidirectional pins. Their internal connections are shown in Figure 53. P10, P11, P13-P15 and P22-P27 of the KBC core are not available on dedicated pins; neither are T0 and T1. P10, P11, P22, P23, P26, P27, T0 and T1 are used to implement the keyboard and mouse interface. Internal pull-ups are implemented only on P12, P16 and P17. The KBC executes a program fetched from an on-chip 2Kbyte ROM. The code programmed in this ROM is user-customizable. The KBC has two interrupt request signals: one for the keyboard and one for the mouse. The interrupt requests are implemented using ports P24 and P25 of the KBC core. The interrupt requests are controlled exclusively by the KBC firmware, except for the type and number, which are affected by configuration registers (see Section 3.2.3 on page 39). The interrupt requests are implemented as bi-directional signals. When an I/O port is read, all unused bits return the value latched in the output registers of the ports. For KBC firmware that implements interrupt-on-OBF schemes, the following is the recommended implementation: 1. Put the data in DBBOUT. 2. Set the appropriate port bit to issue an interrupt request. KBC Internal Interface Bus STATUS DBBIN DBBOUT P12 P12 P16 P16 P17 P17 P20 KBRST P21 GA20 P26 KBCLK T0 P27 KBDAT P10 P23 KBD IRQ T1 P24 Matrix Mouse IRQ P22 P25 P11 Figure 53. Keyboard and Mouse Interfaces www.national.com MCLK 228 MDAT 10.0 Legacy Functional Blocks (Continued) 10.4.2 KBC Register Map All registers are VDD powered. Offset Mnemonic Register Name Type DBBOUT Read KBC Data 00h DBBIN R Write KBC Data W STATUS Read Status 04h DBBIN R Write KBC Command W 10.4.3 KBC Bitmap Summary Register Offset Mnemonic Bits 7 6 5 4 3 DBBOUT KBC Data Bits (For Read cycles) DBBIN KBC Data Bits (For Write cycles) 2 1 0 F0 IBF OBF 00h STATUS General-Purpose Flags F1 04h DBBIN KBC Command Bits (For Write cycles) 229 www.national.com 11.0 Device Characteristics 11.1 GENERAL DC ELECTRICAL CHARACTERISTICS 11.1.1 Recommended Operating Conditions Symbol Parameter Min Typ Max Unit VDD Supply Voltage 3.0 3.3 3.6 V VSB Standby Voltage 3.0 3.3 3.6 V VBAT Battery Backup Supply Voltage 2.4 3.0 3.6 V +70 C TA Operating Temperature 0 11.1.2 Absolute Maximum Ratings Absolute maximum ratings are values beyond which damage to the device may occur. Unless otherwise specified, all voltages are relative to ground. Symbol VSUP VI VO TSTG Parameter Conditions Min Max Unit -0.5 +6.5 V All other pins -0.5 5.5 V LCLK, LAD3-0, LFRAME, LRESET, SERIRQ, CLKRUN, 32KX1_32KCLKIN -0.5 VDD + 0.5 V All other pins -0.5 5.5 V LAD3-0, LDRQ, SERIRQ, CLKRUN, 32KX2 -0.5 VDD + 0.5 V -65 +165 C 1 W +260 C Supply Voltage1 Input Voltage Output Voltage Storage Temperature PD Power Dissipation TL Lead Temperature Soldering (10 s) ESD Tolerance CZAP = 100 pF 2000 RZAP = 1.5 K2 V 1. VSUP is VDD, VSB or VBAT. 2. Value based on test complying with RAI-5-048-RA human body model ESD testing. 11.1.3 Capacitance Symbol Min2 Parameter Max2 Unit 4 5 pF 8 12 pF CIN Input Pin Capacitance CIN1 Clock Input Capacitance3 CIO I/O Pin Capacitance 8 10 pF CO Output Pin Capacitance 6 8 pF 5 1. TA = 25C, f = 1 MHz. 2. Not tested. Guaranteed by characterization. 3. LCLK, CLKIN. www.national.com Typ1 230 11.0 Device Characteristics (Continued) 11.1.4 Power Consumption under Recommended Operating Conditions Symbol IDD VDD Average Main Supply Current IDDLP ISB IBAT VDD Quiescent Main Supply Current in Low Power Mode2 VSB Average Main Supply Current ISBLP Conditions1 Typ Max Unit VIL = 0.5V, VIH = 2.4V No Load 21 30 mA VIL = VSS, VIH = VDD No Load 0.5 0.8 mA VIL = 0.5V, VIH = 2.4V No Load 14 20 mA VIL = VSS, VIH = VSB No Load 5 8 mA VDD, VSB = 0V, VBAT = 3V 0.9 1.5 A Parameter VSB Quiescent Main Supply Current in Low Power Mode2 VBAT Battery Supply Current 1. All parameters specified for 0 C TA 70 C; VDD and VSB = 3.3V 10%, unless otherwise specified. 2. All the modules disabled; clock outputs disabled; no LPC or ACCESS.bus activity. 11.1.5 Voltage Thresholds Symbol Parameter1 Min2 Typ Max2 Unit VDDON VDD Detected as Power-on 2.3 2.6 2.9 V VDDOFF VDD Detected as Power-off 2.2 2.5 2.8 V VDDHY VDD Hysteresis (VDDON - VDDOFF) 0.1 VSBON VSB Detected as Power-on 2.3 2.6 2.9 V VSBOFF VSB Detected as Power-off 2.2 2.5 2.8 V VSBHY VSB Hysteresis (VSBON - VSBOFF) 0.1 VBATDTC Battery Detected 1.0 1.2 V VLOWBAT Low Battery Voltage 1.3 1.9 V V V 1. All parameters specified for 0 C TA 70 C. 2. Not tested. Guaranteed by characterization. 231 www.national.com 11.0 Device Characteristics (Continued) 11.2 DC CHARACTERISTICS OF PINS, BY I/O BUFFER TYPES The following tables summarize the DC characteristics of all device pins described in Section 1.2 on page 19. The characteristics describe the general I/O buffer types defined in Table 1 on page 19. For exceptions, refer to Section 11.2.9 on page 234. The DC characteristics of the LPC Interface meet the PCI Local Bus Specification (Rev 2.2 December 18, 1998) for 3.3V DC signaling. The DC characteristics of the ACCESS.bus Interface meet the SMBus (Rev 1.1 Dec. 11, 1998) and ACCESS.bus (Rev. 3.0 Sep. 1995) specifications for on-board devices. 11.2.1 Input, CMOS Compatible with Schmitt Trigger Symbol: INCS Symbol Parameter Conditions Min Max Unit VIH Input High Voltage 0.75 VSUP1 5.52 V VIL Input Low Voltage -0.51 1.1 V VHY Input Hysteresis 2003 IIL Input Leakage Current mV 14 0 < VIN < VSUP A 1. VSUP is VDD, VSB or VPP according to the input power well. 2. Not tested. Guaranteed by design. 3. Not tested. Guaranteed by characterization. 4. Maximum 10 A for all pins together. Not tested. Guaranteed by characterization. 11.2.2 Input, PCI 3.3V Symbol: INPCI Symbol Parameter Conditions Min Max Unit VIH Input High Voltage 0.5 VDD VDD + 0.51 V VIL Input Low Voltage -0.51 0.3 VDD V lIL2 Input Leakage Current 13 A 0 < VIN < VDD 1. Not tested. Guaranteed by design. 2. Input leakage current includes the output leakage of the bi-directional buffers with TRI-STATE outputs. 3. Maximum 10 A for all pins together. Not tested. Guaranteed by characterization. 11.2.3 Input, SMBus Compatible Symbol: INSM Symbol Parameter Conditions Min Max Unit VIH Input High Voltage 1.4 5.51 V VIL Input Low Voltage -0.51 0.8 V IIL2 Input Leakage Current 13 A 0 < VIN < VSB 1. Not tested. Guaranteed by design. 2. Input leakage current includes the output leakage of the bi-directional buffers with TRI-STATE outputs. 3. Maximum 10 A for all pins together. Not tested. Guaranteed by characterization. www.national.com 232 11.0 Device Characteristics (Continued) 11.2.4 Input, TTL Compatible Symbol: INT Symbol Parameter Conditions Min Max Unit VIH Input High Voltage 2.0 5.51 V VIL Input Low Voltage -0.51 0.8 V IIL2 Input Leakage Current 14 A 0 < VIN < VSUP3 1. Not tested. Guaranteed by design. 2. Input leakage current includes the output leakage of the bi-directional buffers with TRI-STATE outputs. 3. VSUP is VDD, VSB or VPP according to the input power well. 4. Maximum 10 A for all pins together. Not tested. Guaranteed by characterization. 11.2.5 Input, TTL Compatible with Schmitt Trigger Symbol: INTS Symbol Parameter Conditions Min Max Unit VIH Input High Voltage 2.0 5.51 V VIL Input Low Voltage -0.51 0.8 V VHY Input Hysteresis 2002 IIL3 Input Leakage Current mV 15 0 < VIN < VSUP4 A 1. Not tested. Guaranteed by design. 2. Not tested. Guaranteed by characterization. 3. Input leakage current includes the output leakage of the bi-directional buffers with TRI-STATE outputs. 4. VSUP is VDD, VSB or VPP according to the input power well. 5. Maximum 10 A for all pins together. Not tested. Guaranteed by characterization. 11.2.6 Output, TTL Compatible Push-Pull Buffer Symbol: Op/n Output, TTL Compatible, rail-to-rail Push-Pull buffer that is capable of sourcing p mA and sinking n mA Symbol VOH VOL Parameter Output High Voltage Output Low Voltage Conditions Min Max Unit IOH = -p mA 2.4 V IOH = -50 A VSUP - 0.21 V IOL = n mA 0.4 V IOL = 50 A 0.2 V 1. VSUP is VDD, VSB or VPP according to the output power well. 233 www.national.com 11.0 Device Characteristics (Continued) 11.2.7 Output, Open-Drain Buffer Symbol: ODn Output, TTL Compatible Open-Drain output buffer capable of sinking n mA. Output from these signals is open-drain and is never forced high. Symbol Parameter Conditions Output Low Voltage VOL Min Max Unit IOL = n mA 0.4 V IOL = 50 A 0.2 V Max Unit 11.2.8 Output, PCI 3.3V Symbol: OPCI Symbol Parameter Conditions Min 0.9 VDD VOH Output High Voltage lout = -500 A VOL Output Low Voltage lout =1500 A V 0.1 VDD V 11.2.9 Exceptions 1. All pins are back-drive protected except for the output pins with PCI (OPCI) and oscillator (OOSC) Buffer Types. 2. The following pins have an internal static pull-up resistor (when enabled) and therefore may have leakage current to VSUP (when VIN = 0): ACK, AFD_DSTRB, ERR, INIT, PE, SLIN_ASTRB, STB_WRITE, PPDIS, P12, P16, P17, ACBCLK, ACBDAT, PWBTIN, SLBTIN, PWBTOUT, GPIO00-07, GPIOE10-17, GPIO20-27, GPIO30-37, GPIOE40-47, GPIO50-55 and GPIO60-64. 3. The following pins have an internal static pull-down resistor (when enabled) and therefore may have leakage current to VSS (when VIN = VSUP): BUSY_WAIT, PE and SLCT. 4. The following strap pins have an internal static pull-down resistor enabled during power-up reset and therefore may have leakage current to VSS (when VIN = VSUP): BADDR, TRIS, CKIN48, XCNF2-0 and ACBSA. 5. When VDD = 0V, the following pins present a DC load to VSS of 30 K minimum (not tested, guaranteed by design) for a pin voltage of 0V to 3.6V: CTS1, CTS2, DCD1, DCD2, DSR1, DSR2, DTR1_BOUT1, DTR2_BOUT2, RI1, RI2, RTS1, RTS2, SIN1, SIN2, SOUT1, SOUT2. 6. Output from SLCT, BUSY_WAIT (and PE if bit 2 of PP Confg0 register is 0) is open-drain in all SPP modes except in SPP-Compatible mode when the setup mode is ECP-based FIFO and bit 4 of the Control2 parallel port register is 1. Otherwise, output from these signals is level 2. External 4.7 K pull-up resistors should be used. 7. Output from ACK, ERR (and PE if bit 2 of PP Confg0 register is set to 1) is open-drain in all SPP modes except in SPPCompatible mode when the setup mode is ECP-based FIFO and bit 4 of the Control2 parallel port register is set to 1. Otherwise, output from these signals is level 2. External 4.7 K pull-up resistors should be used. 8. Output from STB, AFD, INIT and SLIN is open-drain in all SPP modes, except in SPP-Compatible mode when the setup mode is ECP-based (FIFO). Otherwise, output from these signals is level 2. External 4.7 K pull-up resistors should be used. 9. IOH is valid for a GPIO pin only when it is not configured as open-drain. www.national.com 234 11.0 Device Characteristics (Continued) 11.3 INTERNAL RESISTORS DC Test Conditions Pull-Up Resistor Test Circuit Pull-Down Resistor Test Circuit VSUP VSUP VSUP Device Under Test RPU Device Under Test IPU Pin IPD Pin A A VPIN RPD V V VPIN Figure 54. Internal Resistor Test Conditions, TA = 0 C to 70 C, VSUP = 3.3V Pull-Down Resistor for Straps VSUP VSUP VPIN > VIH Device Under Test VPIN < VIL VSUP IPD Device Under Test 10K (Note 3) Pin 10A IPD Pin A RPD VPIN V VSUP A RPD 10A VPIN V Figure 55. Internal Pull-Down Resistor for Straps, TA = 0 C to 70 C, VSUP = 3.3V Notes for Figures 54 and 55: 1. VSUP is VDD or VSB according to the pin power well. 1. The equivalent resistance of the pull-up resistor is calculated by RPU = (VSUP - VPIN) / IPU. 2. The equivalent resistance of the pull-down resistor is calculated by RPD = VPIN / IPD. 3. The external pull-up resistor is 4.7K for the TRIS strap. 235 www.national.com 11.0 Device Characteristics (Continued) 11.3.1 Pull-Up Resistor Symbol: PUnn Symbol RPU Parameter Pull-up equivalent resistance Conditions1 Min2 Typical Max2 Unit VPIN = 0V nn-30% nn nn+30% K Conditions1 Min2 Typical Max2 Unit VPIN = VSUP nn-30% nn nn+30% K nn-50% K 1. TA = 0 C to 70 C, VSUP = 3.3V. 2. Not tested. Guaranteed by characterization. 11.3.2 Pull-Down Resistor Symbol: PDnn Symbol RPD Parameter Pull-down equivalent resistance VPIN = 0.17 VSUP3 VPIN = 0.8 VSUP3 1. TA = 0 C to 70 C, VSUP = 3.3V. 2. Not tested. Guaranteed by characterization. 3. For strap pins only. www.national.com 236 nn-48% K 11.0 Device Characteristics (Continued) 11.4 AC ELECTRICAL CHARACTERISTICS 11.4.1 AC Test Conditions Load Circuit AC Testing Input, Output Waveform VSUP S1 2.4 0.1 f 0.4 2.0 0.8 Test Points 2.0 0.8 RL Input Device Under Test Output CL Figure 56. AC Test Conditions, TA = 0 C to 70 C, VSUP = 3.3V 10% Notes: 1. VSUP is VDD, VSB or VPP according to the pin power well. 1. CL = 50 pF for all output pins except the following pin groups: CL = 100 pF for Serial Port 1 and 2 (see Section 1.4.4 on page 23), Parallel Port (see Section 1.4.5) and Floppy Disk Controller (see Section 1.4.6) pins; CL = 40 pF for HFCKOUT pin; CL = 400 pF for ACCESS.bus pins (see Section 1.4.2 on page 22); These values include both jig and oscilloscope capacitance. 2. S1 = Open for push-pull output pins. S1 = VSUP for high impedance to active low and active low to high impedance transition measurements. S1 = GND for high impedance to active high and active high to high impedance transition measurements. RL = 1.0 K for all the pins. 3. For the FDC open-drain interface pins, S1 = VDD and RL = 150 . 237 www.national.com 11.0 Device Characteristics (Continued) 11.4.2 Reset Timing VSB Power-Up Reset Description Min1 Reference Conditions Max1 Symbol Figure tLRST 57 Minimum LRESET active time Power stable to end of LRESET 2048 * t32KOSC tIRST 57 Internal power-on reset time Power stable to end of internal reset 8192 * t32KOSC2 t32KW3 + 8192 * t32KOSC tIPLV 57 Internal strap pull-down resistors, valid time4 Before end of internal reset 512 * t32KOSC tIRST tEPLV 57 External strap pull-up resistors, valid time Before end of internal reset 512 * t32KOSC tIRST 1. Not tested. Guaranteed by design. 2. Valid VBAT; the 32 KHz internal clock is running while VSB is OFF (see Low Frequency Clock Timing on page 241). 3. No VBAT; the 32 KHz internal clock is stopped while VSB is OFF (see Low Frequency Clock Timing on page 241). 4. Active on VSB Power-Up reset only. VSB (Power) VSBONmin t32KOSC t32KW 32 KHz Clock (Internal) VSB Power-Up Reset (Internal) tIRST tLRST LRESET tIPLV Internal Straps (Pull-Down) tEPLV External Straps (Pull-Up) Figure 57. Internal VSB Power-Up Reset (No VBAT) www.national.com 238 11.0 Device Characteristics (Continued) VDD Power-Up Reset Description Reference Conditions Min1 Max1 Symbol Figure tLRST 58 Minimum LRESET active time Power stable to end of LRESET 2048 * t32KOSC tIRST 58 Internal Power-Up reset time Power stable to end of internal reset 8192 * t32KOSC 8704 * t32KOSC tIPLV 58 Internal strap pull-down resistors, valid time2 Before end of internal reset 512 * t32KOSC tIRST tEPLV 58 External strap pull-up resistors, valid time Before end of internal reset 512 * t32KOSC tIRST 1. Not tested. Guaranteed by design. 2. Active on VDD Power-Up reset only. VDDONmin VDD (Power) t32KOSC 32 KHz Clock (Internal) tIRST VDD Power-Up Reset (Internal) tLRST LRESET tIPLV Internal Straps (Pull-Down) tEPLV External Straps (Pull-Up) Figure 58. Internal VDD Power-Up Reset Hardware Reset Symbol Figure tWRST 59 Description Reference Conditions LRESET pulse width Min Max 100 ns Internal Clock tWRST LRESET Figure 59. Hardware Reset 239 www.national.com 11.0 Device Characteristics (Continued) 11.4.3 Clock Timing High Frequency Clock Timing CLKIN (48 MHz) Symbol Clock Input Parameter Min Typ Clock High Pulse Width2 8.2 ns tCL Clock Low Pulse Width2 8.2 ns tCR tCF 2 20 Clock Period (50%-50%) 20.83 2 Clock Rise Time (20%-80%) 2 Clock Fall Time (80%-20%) HFCKOUT (48 MHz) 21.5 ns 2.5 ns 2.5 ns HFCKOUT (40 MHz) Clock Output Parameter Min tCH Unit tCH tCP Symbol Max Typ Max Min Typ Max Unit Clock High Pulse Width1,4 8.2 10.3 ns tCL Clock Low Pulse Width1,4 8.2 10.3 ns tCP Clock Period2 (50%-50%) t48TYP - 20.83 32KTOL3 - 50ppm t48TYP + t40TYP - 25 32KTOL3 + 32KTOL3 - 50ppm 150ppm t40TYP + 32KTOL3 + 150ppm ns tCR Clock Rise Time4 (20%-80%) CL = 15 pF 2.5 2.5 ns CL = 40 pF 5 5 ns tCF Clock Fall Time4 (80%-20%) CL = 15 pF 2.5 2.5 ns CL = 40 pF 5 5 ns 1. CL = 15 pF. 2. Not tested. Guaranteed by design. 3. t32KCLKIN tolerance. 4. Not tested. Guaranteed by characterization. . tCP tCH CLKIN HFCKOUT VIH VIH VIL VIL tCL Figure 60. External High Frequency Clock Timing www.national.com 240 11.0 Device Characteristics (Continued) Low Frequency Clock Timing Symbol Figure Description Reference Conditions Min Typ Max Units 30.5145 (t32TYP - 100ppm) 30.517578 (t32TYP) 30.5206 (t32TYP + 100ppm) s Clock Input Timing t32KCLKIN - Required clock period for 32KCLKIN1 From RE to RE of 32KCLKIN. Clock Output Timing s t32KOSC 61 Clock period of the internal From RE to RE of LFCKOUT. oscillator2 t32KW 61 32K oscillator wake-up time3 After VSB > VSBON 1 sec t32KD 62 Internally generated After VSB > VSBON 40/48 MHz clock delay time3 33 ms 30.517578 (t32TYP) 1. Recommended for RTC timekeeping accuracy and for HFCKOUT, LFCKOUT frequency accuracy. 2. Determined by the values of the external crystal circuit components. 3. Not tested. Guaranteed by characterization. VBAT VSB t32KW t32KOSC 32KX1/32KCLKIN 0V 32KX2 0V Figure 61. Low Frequency Clock Waveforms VBAT 0V VSB t32KD Internally Generated 40/48 MHz Clock Figure 62. Internal Clock Waveforms 241 www.national.com 11.0 Device Characteristics (Continued) 11.4.4 LPC Interface Timing The AC characteristics of the LPC Interface meet the PCI Local Bus Specification (Rev 2.2 December 18, 1998) for 3.3V DC signaling. LCLK and LRESET Symbol Parameter Min Max Units tCYC1 LCLK Cycle Time 30 ns tHIGH LCLK High Time2 11 ns tLOW LCLK Low Time2 11 ns - LCLK Slew Rate2,3 1 - LRESET Slew Rate2,4 50 4 V/ns mV/ns 1. The PCI may have any clock frequency between nominal DC and 33 MHz. Device operational parameters at frequencies under 16 MHz are guaranteed by design rather than by testing. The clock frequency may be changed at any time during the operation of the system as long as the clock edges remain "clean" (monotonic) and the minimum cycle high and low times are not violated. The clock may only be stopped in a low state. 2. Not tested. Guaranteed by characterization. 3. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to-peak portion of the clock wavering (0.2 VDD to 0.6 VDD) as shown below. 4. The minimum LRESET slew rate applies only to the rising (de-assertion) edge of the reset signal and ensures that system noise cannot make an otherwise monotonic signal appear to bounce in the switching range. VDD = 3.3V 10% tHIGH tLOW 0.6 VDD 0.5 VDD 0.4 VDD p-to-p (minimum) 0.4 VDD 0.3 VDD 0.2 VDD tCYC www.national.com 242 11.0 Device Characteristics (Continued) SERIRQ and LPC Signals Symbol Figure Description Reference Conditions Min Max Unit tVAL Output Output Valid Delay After RE CLK 11 ns tON Output Float to Active Delay After RE CLK tOFF Output Active to Float Delay After RE CLK tSU Input Input Setup Time Before RE CLK 7 ns tHL Input Input Hold Time After RE CLK 0 ns 21 ns 281 ns 1. Not tested. Guaranteed by characterization. Outputs VDD = 3.3V 10% LCLK 0.4 VDD 0.4 VDD tVAL tVAL 0.615 VDD LAD3-LAD0, LDRQ, SERIRQ 0.285 VDD tON LAD3-LAD0, Leakage Only SERIRQ VDD = 3.3V 10% LCLK tOFF Output Enabled Leakage Only Inputs 0.4 VDD tSU LAD3-LAD0, LFRAME LRESET, SERIRQ tHL 0.4 VDD 243 www.national.com 11.0 Device Characteristics (Continued) 11.4.5 X-Bus Extension Timing (PC87416 and PC87417) Symbol Figure tVAL Outputs Output Valid Delay After RE Internal Clock tON Outputs Float to Active Delay After RE Internal Clock 02 ns tOH Outputs Output Hold time After RE Internal Clock 02 ns tOFF Outputs Active to Float Delay After RE Internal Clock tSU Inputs Input Setup Time Before RE Internal Clock 151 ns tHL Inputs Input Hold Time After RE Internal Clock 01 ns tCSDV Description Reference Conditions Min 1. Not tested. Guaranteed by characterization. 2. Not tested. Guaranteed by design. Outputs tVAL tOH tON XA11-0, XD7-0, XRD_XEN, XWR_XRW, XSTB2-0, XCS3-0 tOFF Inputs Internal Clock (for reference only: not available off chip) tSU XD7-0 XRDY, XIRQ tHL Input Valid Mode 0 Turbo Read Transaction XCS3-0 tCSDV Data Valid XD7-0 www.national.com 244 Unit 201 ns 301 Mode 0 Turbo Chip Select active to Data Valid Read from External Device Read Transaction Internal Clock (for reference only; not available off chip) Max 75 ns ns 11.0 Device Characteristics (Continued) 11.4.6 ACCESS.bus Timing (PC87413 and PC87417) Type of Requirement1 Symbol Figure Description tACBR 63 Rise time (ACBCLK and ACBDAT) tACBF 63 Fall time (ACBCLK and ACBDAT) Min Max Unit Input2 10003 ns Input 3003 ns Output2 2504 ns tACBCKL 63 Clock low period (ACBCLK) Input 4.7 s tACBCKH 63 Clock high period (ACBCLK) Input 4 s tACBCY 64 Clock cycle (ACBCLK) Input 10 s tACBDS 64 Data setup time (before clock rising edge) Input 250 ns Output2 250 ns Input 0 ns Output2 300 ns tACBDH 64 Data hold time (after clock falling edge) tACBPS 65 Stop condition setup time (clock before data) Input 4 s tACBSH 65 Start condition hold time (clock after data) Input 4 s tACBBUF 65 Bus free time between Stop and Start conditions (ACBDAT) Input 4.7 s tACBRS 66 Restart condition setup time (clock before data) Input 4.7 s tACBRH 66 Restart condition hold time (clock after data) Input 4 s tACBLEX - Cumulative clock low extend time from Start to Stop (ACBCLK) Output tACBTO - Clock low time-out (ACBCLK) Input ms 253 ms 253,5 Output ms 353,6 1. An "Input" type is a value the PC8741x device expects from the system; an "Output" type is a value the PC8741x device provides to the system. 2. Test conditions: RL = 1 K to VSB = 3.3V, CL = 400 pF to GND. 3. Not tested. Guaranteed by design. 4. Not tested. Guaranteed by characterization. 5. The PC8741x device detects a time-out condition if ACBCLK is held low for more than tACBTO. 6. Upon detection of a time-out condition, the PC8741x device resets the ACCESS.bus Interface no later than tACBTO. tACBCKH 3.0V 2.5V 2.5V 0.4V 0.4V tACBR 0.4V tACBCKL 0.4V tACBF Figure 63. ACCESS.bus Signals (ACBCLK and ACBDAT) Rising Time and Falling Time 245 www.national.com 11.0 Device Characteristics (Continued) ACBDAT tACBDH tACBDS ACBCLK tACBCY Figure 64. ACCESS.bus Data Bit Timing Start Condition Stop Condition ACBDAT tACBDS ACBCLK tACBPS tBUF tACBSH Figure 65. ACB Start and Stop Condition Timing Restart Condition ACBDAT ACBCLK tACBDS tACBRS tACBRH Figure 66. ACB Restart Condition TIming www.national.com 246 11.0 Device Characteristics (Continued) 11.4.7 FDC Timing FDC Write Data Timing Symbol Parameter Min Max Unit tHDH HDSEL Hold from WGATE Inactive1 100 s tHDS HDSEL Setup to WGATE Active1 100 s tWDW Write Data Pulse Width1 See tDRP, tICP and tWDW values in table below 1. Not tested. Guaranteed by design. HDSEL WGATE tHDS tHDH tWDW WDATA tDRP tICP tWDW Values Data Rate tDRP tICP tICP Nominal tWDW tWDW Minimum Unit 1 Mbps 1000 6 x tCP1 125 2 x tICP 250 ns 500 Kbps 2000 6 x tCP1 125 2 x tICP 250 ns 300 Kbps 3333 10 x tCP1 208 2 x tICP 375 ns 250 Kbps 4000 12 x tCP1 250 2 x tICP 500 ns 1. tCP is the clock period defined for CLKIN in Clock Timing on page 240. 247 www.national.com 11.0 Device Characteristics (Continued) FDC Drive Control Timing Symbol Parameter Min Max Unit 6 s Index Pulse Width 100 ns tSTD DIR Hold from STEP Inactive tSTR ms tSTP STEP Active High Pulse Width1 8 s tSTR STEP Rate Time1 0.5 ms tDST DIR Setup to STEP Active1 tIW 1. Not tested. Guaranteed by design. DIR tSTD tDST STEP tSTP tSTR INDEX tIW FDC Read Data Timing Symbol tRDW Parameter Min Read Data Pulse Width 50 tRDW RDATA www.national.com 248 Max Unit ns 11.0 Device Characteristics (Continued) 11.4.8 Parallel Port Timing Standard Parallel Port Timing Symbol Parameter Conditions Typ Max Unit tPDH Port Data Hold These times are system dependent and therefore are not tested. 500 ns tPDS Port Data Setup These times are system dependent and therefore are not tested. 500 ns tSW Strobe Width These times are system dependent and therefore are not tested. 500 ns Typical Data Exchange BUSY ACK tPDH tPDS PD7-0 tSW STB Enhanced Parallel Port Timing Symbol Parameter Min Max EPP 1.7 EPP 1.9 Unit tWW19a WRITE Active from WAIT Low 45 ns tWW19ia WRITE Inactive from WAIT Low 45 ns tWST19a DSTRB or ASTRB Active from WAIT Low 65 ns tWEST DSTRB or ASTRB Active after WRITE Active 10 ns tWPDH PD7-0 Hold after WRITE Inactive 0 ns tWPDS PD7-0 Valid after WRITE Active ns tEPDW PD7-0 Valid Width 80 ns tEPDH PD7-0 Hold after DSTRB or ASTRB Inactive 0 ns 15 tWW19a WRITE DSTRB or ASTRB tWST19a tWEST tWPDH PD7-0 tWPDS tWW19ia tWST19a tEPDH Valid tEPDW WAIT 249 www.national.com 11.0 Device Characteristics (Continued) Extended Capabilities Port (ECP) Timing Forward Mode Symbol Parameter Min Max Unit tECDSF Data Setup before STB Active 0 ns tECDHF Data Hold after BUSY Inactive 0 ns tECLHF BUSY Active after STB Active 75 ns tECHHF STB Inactive after BUSY Active1 0 1 s tECHLF BUSY Inactive after STB Active1 0 35 ms tECLLF STB Active after BUSY Inactive 0 ns 1. Not tested. Guaranteed by design. tECDHF PD7-0 AFD tECDSF tECLLF STB tECHLF tECLHF BUSY tECHHF Reverse Mode Symbol Parameter Min Max tECDSR Data Setup before ACK Active 0 ns tECDHR Data Hold after AFD Active 0 ns tECLHR AFD Inactive after ACK Active 75 ns tECHHR ACK Inactive after AFD Inactive1 0 35 ms tECHLR AFD Active after ACK Inactive1 0 1 s tECLLR ACK Active after AFD Active 0 ns 1. Not tested. Guaranteed by design. tECDHR PD7-0 BUSY tECDSR ACK tECLLR tECLHR AFD www.national.com Unit tECHLR tECHHR 250 11.0 Device Characteristics (Continued) 11.4.9 Serial Ports 1 and 2 Timing Serial Port Data Timing Symbol tBT Parameter Single Bit Time in Serial Port1 Conditions Min Max Unit Transmitter tBTN - 252 tBTN + 252 ns Receiver tBTN - 2%2 tBTN + 2%2 ns 1. Not tested. Guaranteed by design. 2. tBTN is the nominal bit time in the Serial Port; it is determined by the setting of the Baud Generator Divisor registers. tBT SIN1, SIN2 SOUT1, SOUT2 Modem Control Timing Symbol Parameter Min Max Unit tL RI2,1 Low Time1 10 ns tH RI2,1 High Time1 10 ns tSIM Delay to Set IRQ from Modem Input 40 ns 1. Not tested. Guaranteed by characterization. CTS, DSR, DCD tSIM tSIM INTERRUPT (Read MSR) (Read MSR) tSIM tL tH RI 251 www.national.com 11.0 Device Characteristics (Continued) 11.4.10 SWC Timing Inputs at VSB Power Switching Symbol Figure Description Reference Conditions tEWIV 67 External Wake-up inputs valid1 At VSB power ON, after the tPBOP 68 PWBTOUT pulse time1 Resume by SLPS3, SLPS5 after Power Fail Min Max 1s 1.25 s 100 ms3, 100.03 ms 32 KHz clock is stable2 1. Not tested. Guaranteed by design. 2. No VBAT; the 32 KHz internal clock is stopped while VSB is OFF (see Low Frequency Clock Timing on page 241). 3. Except when generated by PWBTIN pulse. VSB (Power) VSBOFF VSBON tIRST VSB Power-Up Reset (Internal) t32KW 32 KHz Clock (internal) tEWIV GPIOE10-17, GPIOE40-47 RI1, RI2 PWBTIN, SLBTIN XIRQ KBCLK, MCLK KBDAT, MDAT SLPS3, SLPS5 Figure 67. Inputs at VSB Power Switching (No VBAT) www.national.com 252 11.0 Device Characteristics (Continued) VSBOFF VSBON VSB (Power) tIRST VSB Power-Up Reset (Internal) t32KW 32 KHz Clock (internal) tEWIV SLPS3, SLPS5 TRI-STATE ONCTL tPBOP TRI-STATE PWBTOUT Figure 68. Resume by SLPS3, SLPS5, After Power Fail (No VBAT) Wake-Up Inputs at VDD Power Switching Symbol Figure Description Reference Conditions Min Max tEWIV 69 External Wake-up inputs valid1 After VDD power ON 1s 1.25 s tVDFH 69 VDDFELL high time1 After VDD power OFF 1s 1.25 s tKBMID 69 Keyboard and Mouse Wake- After VDD power OFF, if VDDFELL is enabled up inputs disable1 2s 2.25 s 1. Not tested. Guaranteed by design. VDD (Power) GPIOE10-17, GPIOE40-47 (VDDLOAD = 1) VDDON VDDOFF tEWIV tVDFH VDDFELL tKBMID KBCLK, MCLK KBDAT, MDAT Figure 69. Wake-Up Inputs at VDD Power Switching (VDDFELL Enabled) 253 www.national.com 11.0 Device Characteristics (Continued) Power Button Override Symbol Figure Description tPBOV 70 Power Button Override1 tOVEX 70 tPBID 70 Reference Conditions Min Max After PWBTIN active 3.89 s 3.92 s Power Button Override Extension1 After the end of tPBOV 0.2 s 0.24 s PWBTIN disable time1 After a Power-OFF event 1s 1.25 s 1. Not tested. Guaranteed by design. tPBOV tOVEX tPBID PWBTIN PWBTOUT ONCTL Figure 70. Power Button Override Timing www.national.com 254 11.0 Device Characteristics (Continued) Crowbar Symbol Figure tCBTO 71, 72 tCBPBO tPBID Description Reference Conditions Min Max Crowbar Timeout1 After ONCTL active, or VDD power fall 0.5 s2 20 s2 71, 72 Crowbar generated, PWBTOUT pulse time1 After completion of Crowbar Timeout 4s 4.25 s 71, 72 PWBTIN disable time1 After a Power-OFF event 1s 1.25 s 1. Not tested. Guaranteed by design. 2. Set by CRBAR_TOUT (see Section 9.3.11 on page 187). tPBID PWBTIN tCBPBO PWBTOUT ONCTL tCBTO VDD (Power) Figure 71. Power-ON Crowbar Timing tPBID PWBTIN tCBPBO PWBTOUT ONCTL tCBTO VDD (Power) Figure 72. Power-Fall Crowbar Timing 255 www.national.com PC87413, PC87414, PC87416, PC87417 LPC ServerI/O for Servers and Workstations Physical Dimensions All dimensions are in millimeters Plastic Quad Flatpack (PQFP), JEDEC Order Number PC8741x-xxx/VLA NS Package Number VLA128A LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Email: new.feedback@nsc.com 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Francais Tel: +33 (0) 1 41 91 87 90 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 Email: nsj.crc@jksmtp.nsc.com National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. www.national.com