2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM Features DDR2 SDRAM SOCDIMM MT18HTS25672CH - 2GB MT18HTS51272CH - 4GB For component data sheets, refer to Micron's Web site: www.micron.com Features Figure 1: * 200-pin, small outline clocked dual in-line memory module (SOCDIMM) * Fast data transfer rates: PC2-4200 or PC2-5300 * 2GB (256 Meg x 72), 4GB (512 Meg x 72) * Supports ECC error detection and correction * VDD = VDDQ = +1.8V * VDDSPD = +3.0V to +3.6V * JEDEC-standard 1.8V I/O (SSTL_18-compatible) * Differential data strobe (DQS, DQS#) option * 4n-bit prefetch architecture * DLL to align DQ and DQS transitions with CK * Multiple internal device banks for concurrent operation * Programmable CAS# latency (CL) * Posted CAS additive latency (AL) * WRITE latency = READ latency - 1 tCK * Programmable burst lengths (BLs): 4 or 8 * Adjustable data-output drive strength * 64ms, 8,192-cycle refresh * On-die termination (ODT) * Serial presence-detect (SPD) with EEPROM * Phase-lock loop (PLL) to reduce system clock line loading * Gold edge contacts * Dual rank * I2C temperature sensor Table 1: 200-Pin SOCDIMM (MO-274 R/C C) PCB height 30.0mm (1.18in) Options Marking * Operating temperature1 - Commercial (0C TA +70C) - Industrial (-40C TA +85C) * Package - 200-pin DIMM (Pb-free) * Frequency/CAS latency2 - 3.0ns @ CL = 5 (DDR2-667) - 3.75ns @ CL = 4 (DDR2-533) * PCB height - 30.0mm (1.18in) None I Y -667 -53E Notes: 1. Contact Micron for industrial temperature module offerings. 2. CL = CAS (READ) latency. Key Timing Parameters Data Rate (MT/s) Speed Grade Industry Nomenclature CL = 5 CL = 4 -667 -53E PC2-5300 PC2-4200 667 - 533 533 PDF: 09005aef8253e3ea/Source: 09005aef8253e404 HTS18C256_512x72CH.fm - Rev. C 2/09 EN 1 tRCD tRP tRC CL = 3 (ns) (ns) (ns) 400 400 15 15 15 15 55 55 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM Features Table 2: Addressing Parameter Refresh count Row address Device bank address Device page size per bank Device configuration Column address Module rank address Table 3: 2GB 4GB 8K 16K (A0-A13) 8 (BA0-BA2) 1KB 2Gb TwinDieTM (256 Meg x 8) 1K (A0-A9) 2 (S0#, S1#) 8K 32K (A0-A14) 8 (BA0-BA2) 1KB 4Gb TwinDie (512 Meg x 8) 1K (A0-A9) 2 (S0#, S1#) Part Numbers and Timing Parameters - 2GB Modules Base device: MT47H256M8THN,1 2Gb TwinDie DDR2 SDRAM Part Number2 MT18HTS25672CHY-667__ MT18HTS25672CHY-53E__ Table 4: Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL-tRCD-tRP) 2GB 2GB 256 Meg x 72 256 Meg x 72 5.3 GB/s 4.3 GB/s 3.0ns/667 MT/s 3.75ns/533 MT/s 5-5-5 4-4-4 Part Numbers and Timing Parameters - 4GB Modules Base device: MT47H512M8THM,1 4Gb TwinDie DDR2 SDRAM Part Number2 MT18HTS51272CHY-667__ MT18HTS51272CHY-53E__ Notes: PDF: 09005aef8253e3ea/Source: 09005aef8253e404 HTS18C256_512x72CH.fm - Rev. C 2/09 EN Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL-tRCD-tRP) 4GB 4GB 512 Meg x 72 512 Meg x 72 5.3 GB/s 4.3 GB/s 3.0ns/667 MT/s 3.75ns/533 MT/s 5-5-5 4-4-4 1. Data sheets for the base devices can be found on Micron's Web site. 2. All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT18HTS51272CHY-53EA1. 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM Pin Assignments and Descriptions Pin Assignments and Descriptions Table 5: Pin Assignments 200-Pin SOCDIMM Front 200-Pin SOCDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 VREF DQ0 VSS DQ1 DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 DQ18 DQ19 VSS DQ24 DQ25 VSS DQS3# DQS3 VSS DQ26 DQ27 VSS CB0 CB1 VSS DQS8# DQS8 VSS CKE0 CKE1 EVENT# 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 VDD A5 A3 A2 VDD A10 BA0 RAS# VDD CAS# S1# VDD ODT1 NC DQ32 VSS DQ33 DQS4# DQS4 VSS DQ34 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 VSS DQS5# DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7# DQS7 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 43 45 47 49 VSS DQS2# DQS2 VSS 93 95 97 99 VDD A12 A9 A7 143 145 147 149 DQ35 VSS DQ40 DQ41 193 195 197 199 DQ58 VSS DQ59 VDDSPD 44 46 48 50 Notes: PDF: 09005aef8253e3ea/Source: 09005aef8253e404 HTS18C256_512x72CH.fm - Rev. C 2/09 EN VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS DQ14 DQ15 VSS DQ20 DQ21 VSS RESET# DM2 VSS DQ22 DQ23 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 VSS DQ28 DQ29 VSS DM3 VSS DQ30 DQ31 VSS CB4 CB5 VSS DM8 VSS CB6 CB7 VSS CB2 CB3 VSS BA2 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 A6 A4 VDD A1 A0 BA1 VDD WE# S0# ODT0 A13 VDD CK0 CK0# VSS DQ36 DQ37 VSS DM4 VSS DQ38 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 VSS DM5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7 DQ62 VSS DQ63 941 NC/A14 144 96 A11 146 148 98 VDD 100 A8 150 DQ39 VSS DQ44 DQ45 194 196 198 200 SDA SCL SA1 SA0 1. Pin 94 is NC for 2GB and A14 for 4GB modules. 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM Pin Assignments and Descriptions Table 6: Pin Descriptions Symbol Type Description ODT0, ODT1 Input CK0, CK0# Input CKE0, CKE1 Input S0#, S1# Input RAS#, CAS#, WE# Input BA0-BA2 Input A0-A13 (2GB) A0-A14 (4GB) Input DM0-DM8 Input SCL Input SA0-SA1 Input DQ0-DQ63 CB0-CB7 DQS0-DQS8, DQS0#-DQS8# I/O I/O I/O SDA I/O EVENT# VDD VREF VSS VDDSPD Output Supply Supply Supply Supply NC - On-die termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to each of the following pins: DQ, DQS, DQS#, and DM. The ODT input will be ignored if disabled via the LOAD MODE command. Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data (DQs and DQS/DQS#) is referenced to the crossings of CK and CK#. Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking circuitry on the DDR2 SDRAM. Chip select: S# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# provides for external rank selection on systems with multiple ranks. S# is considered part of the command code. Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. Bank address inputs: BA0-BA2 define to which device bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA0-BA2 define which mode register, including MR, EMR, EMR(2), and EMR(3), is loaded during the LOAD MODE command. Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0-BA2) or all device banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and DQS pins. Serial clock: SCL is used to synchronize the presence-detect and temperature sensor data transfer to and from the module. Serial address inputs: These pins are used to configure the presence-detect and temperature sensor devices. Data input/output: Bidirectional data bus. Check bits. Data strobe: Output with read data, input with write data for source synchronous operation. Edge-aligned with read data, center-aligned with write data. DQS# is only used when differential data strobe mode is enabled via the LOAD MODE command. Serial data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presence-detect and temperature sensor portion of the module. Temperature sensor alarm output. Power supply: +1.8V 0.1V. SSTL_18 reference voltage. VDD/2. Ground. Serial EEPROM and temperature sensor positive power supply: +3.0V to +3.6V. No connect: These pins should be left unconnected. PDF: 09005aef8253e3ea/Source: 09005aef8253e404 HTS18C256_512x72CH.fm - Rev. C 2/09 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM Functional Block Diagram Functional Block Diagram Figure 2: Functional Block Diagram S1# S0# DQS0# DQS0 DM0 DQS4# DQS4 DM4 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ DQ DQ DQ DQ DQ DQ DQ CS# DQS DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U1b CS# DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 U1t DQS1# DQS1 DM1 DQ DQ DQ DQ DQ DQ DQ DQ CS# DQS DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U13b CS# DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ CS# DQS DQS# U7t DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 U13t CS# DQ DQ DQ DQ DQ DQ DQ DQ DQS DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U10b CS# DQS DQS# U10t DQS6# DQS6 DM6 DM DQ DQ DQ DQ DQ DQ DQ DQ CS# DQS DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U2b CS# DM DQS DQS# DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 U2t DQS3# DQS3 DM3 CS# DQ DQ DQ DQ DQ DQ DQ DQ DQS DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U8b CS# DQS DQS# U8t DQS7# DQS7 DM7 DM DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS U7b DM DQS DQS# DQS2# DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 CS# DQ DQ DQ DQ DQ DQ DQ DQ DQS5# DQS5 DM5 DM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ CS# DQS DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U12b CS# DM DQS DQS# DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 U12t CS# DQ DQ DQ DQ DQ DQ DQ DQ DQS DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U9b CS# DQS DQS# U9t DQS8# DQS8 DM8 DM CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DQ DQ DQ DQ DQ DQ DQ DQ CS# DQS DQS# U11b DM DQ DQ DQ DQ DQ DQ DQ DQ CS# CK0 CK0# PLL U11t U4 SPD EEPROM WP A0 SCL U1, U13 U2, U12 U11 U7, U10 U8, U9 SDA A2 VSS SA0 SA1 VSS EVT A0 PDF: 09005aef8253e3ea/Source: 09005aef8253e404 HTS18C256_512x72CH.fm - Rev. C 2/09 EN A1 U3 Temp Sensor Rank 0 = U1b, U2b, U7b-U13b Rank 1 = U1t, U2t, U7t-U13t BA0-BA2 A0-A13/A14 RAS# CAS# WE# CKE0 CKE1 ODT0 ODT1 CLK0/CLK0# CLK1/CLK1# CLK2/CLK2# CLK3/CLK3# CLK4/CLK4# U6 DQS DQS# A1 SDA A2 SA0 SA1 VSS EVENT# BA0-BA2: DDR2 SDRAM A0-A13/A14: DDR2 SDRAM RAS#: DDR2 SDRAM CAS#: DDR2 SDRAM WE#: DDR2 SDRAM CKE0: DDR2 SDRAM Rank 0 CKE1: DDR2 SDRAM Rank 1 ODT0: DDR2 SDRAM Rank 0 ODT1: DDR2 SDRAM Rank 1 VDDSPD 5 SPD EEPROM, Temp Sensor VDD DDR2 SDRAM VREF DDR2 SDRAM VSS DDR2 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM General Description General Description The MT18HTS25672CH and MT18HTS51272CH DDR2 SDRAM modules are high-speed, CMOS, dynamic random-access 2GB and 4GB memory modules, organized in a x72 configuration. These DDR2 SDRAM modules use internally configured 8-bank 2Gb TwinDie or 4Gb TwinDie DRAM devices. DDR2 SDRAM modules use double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM module effectively consists of a single 4n-bitwide, one-clock-cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM device during READs and by the memory controller during WRITEs. DQS is edgealigned with data for READs and center-aligned with data for WRITEs. DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. PLL Operation A phase-lock loop (PLL) on the module receives and redrives the differential clock signals (CK, CK#) to the DDR2 SDRAM devices. The PLL minimizes system clock line loading. PLL clock timing is defined by JEDEC specifications and is ensured by use of JEDEC clock reference board. Temperature Sensor An on-board temperature sensor provides the ability to monitor the module temperature along with monitoring alarms. Programmable registers can be used to specify temperature events and critical boundaries. An EVENT# pin is used to signal when different conditions occur based on how the registers are defined. Serial Presence-Detect Operation DDR2 SDRAM modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes are programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device occur via a standard I2C bus using the DIMM's SCL (clock) and SDA (data) signals, together with SA (1:0), which provide four unique DIMM/EEPROM addresses. Write protect (WP) is tied to VSS on the module, permanently disabling hardware write protect. PDF: 09005aef8253e3ea/Source: 09005aef8253e404 HTS18C256_512x72CH.fm - Rev. C 2/09 EN 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM Electrical Specifications Electrical Specifications Stresses greater than those listed in Table 7 may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other conditions outside those indicated in the device data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 7: Absolute Maximum DC Ratings Symbol Parameter Min Max Units VDD VIN, VOUT II VDD supply voltage relative to VSS Voltage on any pin relative to VSS Address inputs Input leakage current; Any input 0V VIN VDD; VREF input 0V VIN 0.95V (All other pins not under RAS#, CAS#, WE#, test = 0V) ODT S#, CKE CK0, CK0# DM Output leakage current; 0V VOUT VDDQ; DQs and DQ, DQS, DQS# ODT are disabled VREF leakage current; VREF = Valid VREF level Module ambient operating temperature Commercial Industrial DDR2 SDRAM component case operating Commercial temperature2 Industrial -1.0 -0.5 -90 +2.3 +2.3 +90 V V A -45 -250 -10 -10 +45 +250 +10 +10 A -36 0 -40 0 -40 +36 +70 +85 +85 +95 A C C C C IOZ IVREF TA TC1 1. The refresh rate is required to double when 85C < TC 95C. 2. For further information, refer to technical note TN-00-08: Thermal Applications, available on Micron's Web site. Notes: Input Capacitance Micron encourages designers to simulate the performance of the module to achieve optimum values. Simulations are significantly more accurate and realistic than a gross estimation of module capacitance when inductance and delay parameters associated with trace lengths are used in simulations. AC Timing and Operating Conditions Recommended AC operating conditions are given in the DDR2 component data sheets. Component specifications are available on Micron's Web site. Module speed grades correlate with component speed grades, as shown in Table 8. Table 8: Module and Component Speed Grades Module Speed Grade Component Speed Grade -667 -53E -3 -37E PDF: 09005aef8253e3ea/Source: 09005aef8253e404 HTS18C256_512x72CH.fm - Rev. C 2/09 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM Electrical Specifications Table 9: DDR2 IDD Specifications and Conditions - 2GB Values shown are for MT47H256M8THN DDR2 TwinDie SDRAM components from device IDD values in the 2Gb TwinDie (256 Meg x 8) component data sheet Parameter/Condition t t t t Operating one bank active-precharge current: CK = CK (IDD), RC = RC (IDD), RAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), t RCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data pattern is same as IDD4W Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching Active power-down current: All device banks open; Fast PDN exit tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs MR[12] = 0 are stable; Data bus inputs are floating Slow PDN exit MR[12] = 1 t t Active standby current: All device banks open; CK = CK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Operating burst write current: All device banks open; Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating burst read current: All device banks open; Continuous burst reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Burst refresh current: tCK = tCK (IDD); REFRESH command at every tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Self refresh current: CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating Operating bank interleave read current: All device banks interleaving reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during deselects; Data bus inputs are switching Symbol -667 -53E Units IDD0 873 738 mA IDD1 1,008 963 mA IDD2P 126 126 mA IDD2Q 423 423 mA IDD2N 468 468 mA IDD3P 333 333 mA 153 153 mA IDD3N 603 513 mA IDD4W 1,323 1,233 mA IDD4R 1,323 1,233 mA IDD5 2,043 1,998 mA IDD6 126 126 mA IDD7 2,628 2,538 mA t PDF: 09005aef8253e3ea/Source: 09005aef8253e404 HTS18C256_512x72CH.fm - Rev. C 2/09 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM Electrical Specifications Table 10: DDR2 IDD Specifications and Conditions - 4GB Values shown are for MT47H512M8THM DDR2 TwinDie SDRAM components from device IDD values in the 4Gb TwinDie (512 Meg x 8) component data sheet Parameter/Condition t t t t Operating one bank active-precharge current: CK = CK (IDD), RC = RC (IDD), t RAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), t RCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data pattern is same as IDD4W Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching Active power-down current: All device banks open; Fast PDN exit tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs MR[12] = 0 are stable; Data bus inputs are floating Slow PDN exit MR[12] = 1 t t Active standby current: All device banks open; CK = CK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Operating burst write current: All device banks open; Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating burst read current: All device banks open; Continuous burst reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Burst refresh current: tCK = tCK (IDD); REFRESH command at every tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Self refresh current: CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating Operating bank interleave read current: All device banks interleaving reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during deselects; Data bus inputs are switching PDF: 09005aef8253e3ea/Source: 09005aef8253e404 HTS18C256_512x72CH.fm - Rev. C 2/09 EN 9 Symbol -667 -53E Units IDD0 1,017 927 mA IDD1 1,422 1,062 mA IDD2P 144 144 mA IDD2Q 567 477 mA IDD2N 657 567 mA IDD3P 432 387 mA 162 162 mA IDD3N 612 522 mA IDD4W 1,467 1,287 mA IDD4R 1,647 1,467 mA IDD5 2,637 2,457 mA IDD6 144 144 mA IDD7 3,177 2,772 mA Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM PLL Specifications PLL Specifications Table 11: PLL Specifications CUA845 device or JESD82-21 equivalent Parameter Symbol Pins Condition Min Max Units DC high-level input voltage DC low-level input voltage Input voltage (limits) Input differential-pair cross voltage Input differential voltage Input differential voltage Input current VIH OE, OS, CK, CK# LVCMOS 0.65 x VDD - V VIL OE, OS, CK, CK# LVCMOS - 0.35 x VDD V VID(DC) VID(AC) II Output disabled current Static supply current Dynamic supply IODL IDDLD IDD CIN Input capacitance Table 12: VIN VIX Differential input Differential input Differential input OE, OS, FBIN, FBIN# VI = VDD or VSS CK, CK# VI = VDD or VSS OE = L, VODL = 100mV CL = 0pf n/a CK and CK# = 410 MHZ all output are open (not connected to a PCB) Each input VI = VDD or VSS -0.3 VDD + 0.3 (VDD/2) - 0.15 (VDD/2) + 0.15 V V 0.3 0.6 -10 -250 100 - - VDD + 0.4 VDD + 0.4 +10 +250 - +500 +300 V V A A A A mA 2 3 pF PLL Clock Driver Timing Requirements and Switching Characteristics Parameter Stabilization time Input clock slew rate SSC modulation frequency SSC clock input frequency deviation PLL loop bandwidth (-3dB from unity gain) Notes: PDF: 09005aef8253e3ea/Source: 09005aef8253e404 HTS18C256_512x72CH.fm - Rev. C 2/09 EN Symbol Min Max Units tL - 1 30 0.0 2 6 4 33 -0.5 - s V/ns kHz % MHz slr(i) 1. PLL timing and switching specifications are critical for proper operation of the DDR2 DIMM. This is a subset of parameters for the specific PLL used. 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM Temperature Sensor Temperature Sensor The temperature sensor continuously monitors the module's temperature and can be read back at any time over the I2C bus shared with the SPD. This sensor complies with the JEDEC standard JESD21-C, page 4.7-1. Table 13: Temperature Sensor Specifications All voltages referenced to VSS Parameter/Condition Supply voltage Average operating supply current Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Output low voltage: IOUT = 3mA Logic input current Symbol Min Max Units VDDSPD +3.0 - +2.1 - - -5 -5 -40 +3.6 +500 - +0.8 +0.4 +5 +5 +125 V A V V V A A C Symbol Min Max Units tBUF 4.7 - 300 4.0 4 4.7 - - 250 4.7 4 10 - 300 - - 50 - 1 400 - - - 100 s ns ns s s s ns kHz ns s s kHz VIH VIL VOL IIH IIL Temperature sensing range Table 14: Temperature Sensor AC Timing Parameter/Condition Time bus must be free before a new transition can start SDA and SCL fall time Data hold time Start condition hold time Clock HIGH period Clock LOW period SDA and SCL rise time SCL clock frequency Data setup time Start condition setup time Stop condition setup time Clock frequency tF tHD:DAT tHD:STA tHIGH tLOW tR fSCL tSU:DAT tSU:STA tSU:STO f CK EVENT# Pin The temperature sensor also adds the EVENT# pin. Not used by the SPD, the EVENT# is a temperature sensor output used to flag critical events that can be set up in the sensor's configuration register. EVENT# has three defined modes of operation: interrupt mode, compare mode, and critical temperature mode. The open-drain output of EVENT# under the three separate operating modes is illustrated in Figure 3 on page 12. Event thresholds are programmed in the 0x01 register using a hysteresis. The alarm window provides a comparison window, with upper and lower limits set in the alarm upper boundary register and the alarm lower boundary register, respectively. When the alarm window is enabled, EVENT# will trigger whenever the temperature is outside the MIN or MAX values set by the user. PDF: 09005aef8253e3ea/Source: 09005aef8253e404 HTS18C256_512x72CH.fm - Rev. C 2/09 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM Temperature Sensor The interrupt mode enables software to reset EVENT# after a critical temperature threshold has been detected. Threshold points are set in the configuration register by the user. This mode triggers the critical temperature limit and both the MIN and MAX of the temperature window. The compare mode is similar to the interrupt mode, except EVENT# cannot be reset by the user and only returns to the logic HIGH state when the temperature falls below the programmed thresholds. Critical temperature mode triggers EVENT# only when the temperature has exceeded the programmed critical trip point. When the critical trip point has been reached, the temperature sensor goes into comparator mode and the critical EVENT# cannot be cleared through software. SMBus Slave Subaddress Decoding The temperature sensor's physical address differs from the module's SPD device physical addresses: 0011 for A0, A1, A2, and RW# in binary where A2, A1, and A0 are the three slave subaddress pins and the RW# pin is the READ/WRITE flag. If the slave base address is fixed for the SPD and temperature sensor, then the pins set the subaddress bits of the slave address, enabling the devices to be located anywhere within the eight slave address locations. For example, they could be set from 30h to 3Eh. Figure 3: EVENT# Pin Functionality Temperature Critical Hysteresis affects these trip points Alarm window (MAX) Alarm window (MIN) Clears event Time EVENT# interrupt mode EVENT# comparator mode EVENT# critical temperature only mode PDF: 09005aef8253e3ea/Source: 09005aef8253e404 HTS18C256_512x72CH.fm - Rev. C 2/09 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM Temperature Sensor Table 15: Temperature Sensor Registers Name Pointer register Capability register Configuration register Alarm temperature upper boundary register Alarm temperature lower boundary register Critical temperature register Temperature register Address Power-On Default Not applicable 0x00 0x01 0x02 0x03 0x04 0x05 Undefined 0x0001 0x0000 0x0000 0x0000 0x0000 Undefined Pointer Register The pointer register selects which of the 16-bit registers is being accessed in subsequent READ and WRITE operations. This register is a write-only register. Table 16: Pointer Register Bits 0-7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 Register select Register select Register select Register select Table 17: Pointer Register Bits 0-2 Descriptions Bit 2 Bit 1 Bit 0 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 Register Capability register Configuration register Alarm temperature upper boundary register Alarm temperature lower boundary register Critical temperature register Temperature register Capability Register The capability register indicates the features and functionality supported by the temperature sensor. This register is a read-only register. Table 18: Bit 15 Capability Register Bits 0-15 Bit 14 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 RFU RFU RFU RFU RFU RFU RFU RFU Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RFU RFU RFU TRES1 TRES0 Wider range Precision Has alarm and critical temperature Notes: Table 19: Bit 0 Bit 13 1. RFU = reserved for future use. Capability Register Bits 0-15 Descriptions Description Basic capability 1: Has alarm and critical trip point capabilities PDF: 09005aef8253e3ea/Source: 09005aef8253e404 HTS18C256_512x72CH.fm - Rev. C 2/09 EN 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM Temperature Sensor Table 19: Bit 1 2 4:3 15:5 Capability Register Bits 0-15 Descriptions (continued) Description Accuracy 0: 2C over the active range and 3C over the monitor range 1: 1C over the active range and 2C over the monitor range Wider range 0: Temperatures lower than 0C are clamped to a binary value of 0 1: Temperatures below 0C can be read Temperature resolution 00: 0.5C LSB 01: 0.25C LSB 10: 0.125C LSB 11: 0.0625C LSB 0: Must be set to zero Configuration Register Table 20: Configuration Register Bits 0-15 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 RFU RFU RFU RFU RFU Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Critical lock bit Alarm lock bit Clear event Event output status Event output control Table 21: Bit 0 1 2 3 4 5 6 Bit 10 Bit 9 Hysteresis Bit 2 Bit 8 Shutdown mode Bit 1 Critical event Event polarity only Bit 0 Event mode Configuration Register Bits 0-10 Descriptions Description Note Event mode 0: Comparator mode 1: Interrupt mode EVENT# polarity 0: Active LOW 1: Active HIGH Critical event only 0: EVENT# trips on alarm or critical temperature event 1: EVENT# trips only if critical temperature is reached Event output control 0: Event output disabled 1: Event output enabled Event status 0: EVENT# has not been asserted by this device 1: EVENT# is being asserted due to an alarm window or critical temperature condition Clear event 0: No effect 1: Clears the event when the temperature sensor is in the interrupt mode Alarm window lock bit 0: Alarm trips are not locked and can be changed 1: Alarm trips are locked and cannot be changed Cannot be changed if either of the lock bits is set PDF: 09005aef8253e3ea/Source: 09005aef8253e404 HTS18C256_512x72CH.fm - Rev. C 2/09 EN 14 Cannot be changed if either of the lock bits is set This is a read-only field in the register; the event causing the event can be determined from the read temperature register This is a write-only field in the register and is self clearing Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM Temperature Sensor Table 21: Bit 7 8 10:9 Configuration Register Bits 0-10 Descriptions (continued) Description Note Critical trip lock bit 0: Critical trip is not locked and can be changed 1: Critical trip is locked and cannot be changed Shutdown mode 0: Enabled 1: Shutdown Hysteresis enable 00: Disable 01: Enable at 1.5C 10: Enable at 3C 11: Enable at 6C The shutdown mode is a power-saving mode that disables the temperature sensor When enabled, a hysteresis is applied to temperature movement around the trip points. As an example, if the hysteresis register is enabled to a delta of 6C, the preset trip points will toggle when the temperature reaches the programmed value. These values will reset when the temperature drops below the trip points minus the set hysteresis level. In this case, this would be critical temperature minus 6C The hysteresis is applied to both the above alarm window and the below alarm window bits found in the read-only temperature register. EVENT# is also affected by this register Figure 4: Hysteresis TH 1 1 TH - Hyst TL 3 2 2 3 TL - Hyst Below window bit Above window bit Notes: Table 22: 1. TH is the value set in the alarm temperature upper boundary trip register. 2. TL is the value set in the alarm temperature lower boundary trip register. 3. Hyst is the value set in the hysteresis bits of the configuration register. Hysteresis Condition Sets Clears Below Alarm Window Bit Temperature gradient Falling Rising PDF: 09005aef8253e3ea/Source: 09005aef8253e404 HTS18C256_512x72CH.fm - Rev. C 2/09 EN Above Alarm Window Bit Critical temperature TL - Hyst TL 15 Temperature gradient Rising Falling Critical temperature TH TH - Hyst Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM Temperature Sensor Temperature Format The temperature trip point registers and temperature readout register use a "2's complement" format to enable negative numbers. The least significant bit (LSB) is equal to 0.0625C or 0.25C depending on which register is referenced. As an example, assuming an LSB of 0.0625C: * A value of 0x018C would equal 24.75C * A value of 0x06C0 would equal 108C * A value of 0x1E74 would equal -24.75C Upper Boundary Temperature Register The upper boundary temperature register is used to set the maximum value of the alarm window. The LSB for this register is 0.25C. All RFU bits in the register will always report zero. Table 23: Upper Boundary Temperature Register Bits 15 14 13 12 11 0 0 0 MSB 10 9 8 7 6 5 4 3 2 1 0 LSB RFU RFU Alarm window upper boundary temperature Lower Boundary Temperature Register The lower boundary temperature register is used to set the minimum value of the alarm window. The LSB for this register is 0.25oC. All RFU bits in the register will always report zero. Table 24: Lower Boundary Temperature Register Bits 15 14 13 12 0 0 0 MSB 11 10 9 8 7 6 5 4 3 2 1 0 LSB RFU RFU Alarm window lower boundary temperature Critical Temperature Register The critical temperature register is used to set the maximum temperature above the alarm window. The LSB for this register is 0.25C. All RFU bits in the register will always report zero. Table 25: Critical Temperature Register Bits 15 14 13 12 0 0 0 MSB 11 10 9 8 7 6 5 4 3 2 1 0 LSB RFU RFU Critical temperature trip point PDF: 09005aef8253e3ea/Source: 09005aef8253e404 HTS18C256_512x72CH.fm - Rev. C 2/09 EN 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM Temperature Sensor Temperature Register The temperature register is a read-only register that provides the current temperature detected by the temperature sensor. The LSB for this register is 0.0625C with a resolution of 0.0625C. The most significant bit (MSB) is 128C in the readout section of this register. The upper three bits of the register are used to monitor the trip points that are set in the previous three registers. Table 26: Temperature Register Bits 15 14 13 12 Above critical trip Above alarm window Below alarm window MSB Table 27: 11 10 9 8 5 4 3 2 1 0 LSB Temperature Register Bits Descriptions Description 13 Below alarm window 0: Temperature is equal to or above the lower boundary 1: Temperature is below alarm window Above alarm window 0: Temperature is equal to or below the upper boundary 1: Temperature is above alarm window Above critical trip point 0: Temperature is below critical trip point 1: Temperature is above critical trip point 15 6 Temperature BIT 41 7 PDF: 09005aef8253e3ea/Source: 09005aef8253e404 HTS18C256_512x72CH.fm - Rev. C 2/09 EN 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM Serial Presence-Detect Serial Presence-Detect Table 28: Serial Presence-Detect EEPROM and Temperature Sensor DC Operating Conditions All voltages referenced to VSS Parameter/Condition Supply voltage with temperature sensor option Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Output low voltage: IOUT = 3mA SPD input leakage current: VIN = GND to VDD SPD output leakage current: VOUT = GND to VDD SPD standby current Power supply current, READ: SCL clock frequency = 100 kHz Power supply current, WRITE: SCL clock frequency = 100 kHz Average temperature sensor current Table 29: Symbol Min Max Units VDDSPD VIH VIL VOL ILI ILO ISB ICCR ICCW 3.0 2.1 -0.6 - 0.10 0.05 1.6 0.4 2 - 3.6 VDDSPD + 0.5 0.8 0.4 3 3 4 1 3 500 V V V V A A A mA mA A Serial Presence-Detect EEPROM AC Operating Conditions All voltages referenced to VSS Parameter/Condition SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SDA and SCL rise time SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time Notes: PDF: 09005aef8253e3ea/Source: 09005aef8253e404 HTS18C256_512x72CH.fm - Rev. C 2/09 EN Symbol Min Max Units Notes tAA 0.2 1.3 200 - 0 0.6 0.6 - 1.3 - - 100 0.6 0.6 - 0.9 - - 300 - - - 50 - 0.3 400 - - - 10 s s ns ns s s s ns s s kHz ns s s ms 1 tBUF tDH tF tHD:DAT tHD:STA tHIGH tI tLOW tR fSCL tSU:DAT t SU:STA tSU:STO tWRC 2 2 3 4 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a restart condition, or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistance, and the EEPROM does not respond to its slave address. 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM Serial Presence-Detect Table 30: Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Serial Presence-Detect Matrix Description Entry (Version) 128 Number of SPD bytes used by Micron 256 Total number of bytes in SPD device DDR2 SDRAM Fundamental memory type 14 or 15 Number of row addresses on assembly 10 Number of column addresses on assembly 30mm, dual rank DIMM height and module ranks 72 Module data width 0 Reserved SSTL 1.8V Module voltage interface levels -667 SDRAM cycle time, tCK (CL = MAX value, see byte 18) -53E t -667 SDRAM access from clock, AC (CL = MAX value, see -53E byte 18) ECC Module configuration type 7.81s/SELF Refresh rate/type 8 SDRAM device width (primary SDRAM) 8 Error-checking SDRAM data width 1 clock MIN clock delay, back-to-back random column access 4, 8 Burst lengths supported 4 or 8 Number of banks on SDRAM device -667 (5, 4, 3) CAS latencies supported -53E (4, 3) Module thickness SODIMM DDR2 DIMM type No reg, 1 PLL SDRAM module attributes -667 SDRAM device attributes: weak driver (01) or 50 -53E ODT (03) -667 SDRAM cycle time, tCK, MAX CL - 1 -53E -667 SDRAM access from CK, tAC, MAX CL - 1 -53E -667 SDRAM cycle time, tCK, MAX CL - 2 -53E -667 SDRAM access from CK, tAC, MAX CL - 2 -53E MIN row precharge time, tRP MIN row active-to-row active, tRRD MIN RAS#-to-CAS# delay, tRCD -667/-53E MIN active-to-precharge time, tRAS 1GB or 2GB Module rank density -667 Address and command setup time, tISb -53E -667 Address and command hold time, tIHb -53E -667/-53E Data/data mask input setup time, tDSb -667 Data/data mask input hold time, tDHb -53E PDF: 09005aef8253e3ea/Source: 09005aef8253e404 HTS18C256_512x72CH.fm - Rev. C 2/09 EN 19 2GB 4GB 80 08 08 0E 0A 61 48 00 05 30 3D 45 50 02 82 08 08 00 0C 04 38 18 01 04 04 03 01 3D 50 45 50 50 00 45 00 3C 1E 3C 2D 01 20 25 27 37 10 17 22 80 08 08 0F 0A 61 48 00 05 30 3D 45 50 02 82 08 08 00 0C 08 38 18 01 04 04 03 01 3D 50 45 50 50 00 45 00 3C 1E 3C 2D 02 20 25 27 37 10 17 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM Serial Presence-Detect Table 30: Byte Serial Presence-Detect Matrix (continued) Description Entry (Version) tWR 36 37 38 39 40 Write recovery time, WRITE-to-READ command delay, tWTR READ-to-PRECHARGE command delay, tRTP Memory analysis probe Extension for bytes 41 and 42 41 42 MIN active auto refresh time, tRC1 MIN AUTO REFRESH to ACTIVE/AUTO REFRESH command period, tRFC SDRAM device MAX cycle time, tCK (MAX) SDRAM device MAX DQS-DQ skew time, tDQSQ 43 44 -667/-53E -667 -53E -667/-53E -667 -53E -667 -53E 45 SDRAM device MAX read data hold skew factor, tQHS 46 PLL relock time 47-61 Optional features, not supported 62 SPD revision 63 Checksum for bytes 0-62 64 65-71 72 73-90 91 92 93 94 95-98 99-127 128-255 Release 1.2 -667 -53E MICRON (continued) 1-12 - 1-9 0 - - - Manufacturer's JEDEC ID code Manufacturer's JEDEC ID code Manufacturing location Module part number (ASCII) PCB identification code Identification code (continued) Year of manufacture in BCD Week of manufacture in BCD Module serial number Reserved for manufacturer-specific data Reserved for customer-specific data Notes: PDF: 09005aef8253e3ea/Source: 09005aef8253e404 HTS18C256_512x72CH.fm - Rev. C 2/09 EN 2GB 4GB 3C 1E 1E 00 00 00 3C 69 3C 1E 1E 00 06 06 3C 7F 80 18 1E 22 28 0F 00 12 14 BF 2C 00 01-0C Variable data 01-09 00 Variable data Variable data Variable data 00 FF 80 18 1E 22 28 0F 00 12 5C 07 2C 00 01-0C Variable data 01-09 00 Variable data Variable data Variable data 00 FF 1. The tRC SPD values shown are JEDEC DDR2 device specification values. The actual Micron DDR2 device specification is tRC = 55ns for all speed grades. 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM Module Dimensions Module Dimensions Figure 5: 200-Pin DDR2 SOCDIMM Front view 3.80 (0.150) MAX 67.75 (2.667) 67.75 (2.667) U3 2.0 (0.079) R (2X) U5 1.0 (0.039) R (2X) 1.80 (0.071) (2X) U1 U7 U2 U8 30.15 (1.187) 29.85 (1.175) 20.0 (0.787) TYP U6 6.0 (0.236) TYP 0.50 (0.0197) R 2.00 (0.079) TYP 0.60 (0.024) TYP 0.45 (0.018) TYP 1.10 (0.043) 0.90 (0.035) Pin 199 Pin 1 63.60 (2.504) TYP Back view U9 U10 U11 U12 U13 10.00 (0.394) TYP 3.50 (0.138) TYP 4.2 (0.165) TYP Pin 200 1.0 (0.039) TYP Pin 2 47.4 (1.87) TYP 11.4 (0.45) TYP 16.26 (0.64) TYP Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. 2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for complete design dimensions. (R) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, TwinDie, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef8253e3ea/Source: 09005aef8253e404 HTS18C256_512x72CH.fm - Rev. C 2/09 EN 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved.