DMG6602SVT-7 - DIODES INC - Datasheet.Directory

DMG6602SVT

COMPLEMENTARY PAIR ENHANCEMENT MODE MOSFET

Product Summa r y

Device V(BR)DSS RDS(on) ID

TA = +25°C

Q1 30V 60mΩ @ VGS = 10V 3.4A

100mΩ @ VGS = 4.5V 2.7A

Q2 -30V 95mΩ @ VGS = -10V -2.8A

140mΩ @ VGS = -4.5V -2.3A

Description and Applications

This new generation MOSFET is designed to minimize the on-

state

resistance (RDS(on)

) yet maintain superior switching performance,

making it ideal for high-efficiency power management applications.

• Backlighting

• DC-DC Converters

• Power Management Functions

Features an d Benef its

• Low On-Resistance

• Low Input Capacitance

• Fast Switching Speed

• Low Input/Output Leakage

• Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)

• Halogen and Antimony Free. “Green” Device (Note 3)

• Qualified to AEC-Q101 Standards for High Reliability

Mechanical Data

• Case: TSOT26

• Case Material: Molded Plast ic, “Green” Molding Com pound.

UL Flammabilit y Classification Rating 94V-0

• Moisture Sensitivi t y: Level 1 per J-STD-020

• Terminals Connections: See Diagram

• Terminals: Finish—Matte Tin Annealed over Copper Leadframe.

Solderable per MIL-STD-202, Method 208

• Weight : 0.013 gr ams (Approximate)

Ordering Information (Note 3)

Part Number

Case

Packaging

DMG6602SVT-7

TSOT26

3000 / Tape & Reel

Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant.

2. See https://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green" and

Lead-free.

3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and

<1000ppm antimony compounds.

4. For packaging details, go to our website at http://www.diodes.com/products/packages.html.

Marking Information

Date Code Key

Year

2010

2011

2012

2013

2014

2015

2016

2017

Code

X

Y

Z

A

B

C

D

E

Month

Jan

Feb

Mar

Apr

May

Jun

Jul

Aug

Sep

Oct

Nov

Dec

Code

1

2

3

4

5

6

7

8

9

O

N

D

TSOT26

Top View

1

2

3

6

5

4

D1

S1

D2

G1

S2

G2

Q1 N-Channel

Q2 P-Channel

66C = Product Type Marking Code

YM = Date Code Marking

Y = Year (ex: X = 2010)

M = Month (ex: 9 = September)

66C

YM

D1

S1

G1

D2

S2

G2

NOT RECOMMENDED FOR NEW DESIGN

USE DMC3071LVT

DMG6602SVT

Document number: DS35159 Rev. 8 - 3 1 of 10

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DMG6602SVT

Maximum Ratings – Q1 (@TA = +25°C unless otherwise spec ifi ed.)

Characteristic

Symbol

Value

Unit

Drain-Source Voltage

VDSS

30

V

Gate-Source Voltage

VGSS

±20

V

Continuous Drain Current (Note 6) VGS = 10V Steady State

T

A

= +25°C

TA = +70°C

ID

3.4

2.7

A

Continuous Drain Current (Note 6) VGS = 4.5V St eady State

T

A

= +25°C

TA = +70°C

ID

2.7

2.2 A

Maximum Continuous Body Diode Forward Current (Note 6)

IS

1.5

A

Pulsed Drain Current (Note 6)

IDM

25

A

Maximum Ratings – Q2 (@TA = +25°C unless otherwise specifi ed. )

Characteristic

Symbol

Value

Unit

Drain-Source Voltage

VDSS

-30

V

Gate-Source Voltage

VGSS

±20

V

Continuous Drain Current (Note 6) VGS = -10V Steady State

T

A

= +25°C

TA = +70°C

ID -2.8

-2.4 A

Continuous Drain Current (Note 6) VGS = -4.5V Steady State

T

A

= +25°C

TA = +70°C

ID

-2.3

-2.1

A

Maximum Continuous Body Diode Forward Current (Note 6)

IS

-1.5

A

Pulsed Drain Current (Note 6)

ID

-20

A

Thermal Characteristics

Characteristic

Symbol

Value

Units

Total Power Dissipation (Note 5)

TA = +25°C

PD

0.84

W

TA = +70°C

0.52

Thermal Resistance, Junction to Ambient (Note 5)

Steady State

RϴJA

155

°C/W

t < 10s

109

Total Power Dissipation (Note 6)

TA = +25°C

PD

1.27

W

TA = +70°C

0.8

Thermal Resistance, Junction to Ambient (Note 6)

Steady State

RϴJA

102

°C/W

t < 10s

71

Thermal Resistance, Junction to Case (Note 6)

RϴJC

34

Operating and Storage Tem perature Range

TJ, TSTG

-55 to +150

°C

Notes: 5. Device mounted on FR-4 substrate PCB, 2oz copper, with minimum recommended pad layout.

6. Device mounted on FR-4 substrate PCB, 2oz copper, with 1inch square copper plate.

DMG6602SVT

Document number: DS35159 Rev. 8 - 3 2 of 10

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DMG6602SVT

Electrical Characteristics – Q1 NMOS (@TA = +25°C unl ess otherwise specified.)

Characteristic

Symbol

Min

Typ

Max

Unit

Test Condition

OFF CH ARACTERISTICS (Note 7)

Drain-Source Breakdown Voltage

BVDSS

30

—

V

VGS = 0V , ID = 250µA

Zero Gate Voltage Drain Current

IDSS

—

1.0

µA

VDS = 24V, VGS = 0V

Gate-Source Leakage

IGSS

—

±100

nA

VGS = ±20V, VDS = 0V

ON CHARACTERIS TICS (Note 7)

Gate Threshold Voltage

VGS(th)

1.0

—

2.3

V

VDS = VGS, ID = 250μA

Static Drain-Source On-Resistance RDS (ON) —

38

55

60

100 mΩ

VGS = 10V, ID = 3.1A

VGS = 4.5V, ID = 2A

Forward Transfer Admittance

|Yfs|

—

4

—

S

VDS = 5V, ID = 3.1A

Diode Forward Voltage

VSD

—

0.8

1

V

VGS = 0V , IS = 1A

DYNAMIC CH ARACTERISTICS (Note 8)

Input Capacitance

Ciss

—

290

400

pF VDS = 15V, VGS = 0V,

f = 1.2MHz

Output Capacit ance

Coss

—

40

80

Reverse Transfer Capaci t ance

Crss

—

40

80

Gate Resistance

Rg

—

1.4

—

Ω

VDS = 0V, VGS = 0V, f = 1MHz

Total Gate Charge (VGS = 4.5V)

Qg

—

4

6

nC

VDS = 15V, VGS = 4.5V, ID = 3.1A

Total Gate Charge (VGS = 10V)

Qg

—

9

13

VDS = 15V, VGS = 10V, ID = 3A

Gate-Source Charge

Qgs

—

1.2

—

Gate-Drain Charge

Qgd

—

1.5

—

Turn-On Delay Time

tD(on)

—

3

—

ns VGS = 10V, VDS = 15V,

RG = 3Ω, RL = 4.7Ω

Turn-On Rise Time

tr

—

5

—

Turn-Off Delay Time

tD(off)

—

13

—

Turn-Off Fall Time

tf

—

3

—

Notes: 7. Short duration pulse test used to minimize self-heating effect .

8. Guaranteed by design. Not subject to product testing.

00.5 11.5 22.5 33.5 44.5 5

V , DRAIN -SOURCE VO LTAGE(V )

Fig. 1 Typi c al Output Characteristic s

DS

I , DRAIN CURRENT (A)

D

0.0

2.0

4.0

6.0

8.0

10.0

V , GATE SOURCE VOLTAGE(V)

Fig. 2 Typical Transfer Characteristics

GS

I , DRAIN CURRENT (A)

D

0

2

4

6

8

10

0 1 2 3 4 5

V = 5.0V

DS

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DMG6602SVT

I , DRAIN SOURCE CURRENT

Fig. 3 Typical On-R esistance v s .

Dr ain Curr ent an d Gate Voltage

D

R ,DRAIN-SOURCE ON-RESISTANCE( )

DS(ON)

Ω

0.01

0.1

1

0 4 812 16 20

R ( ) Ave @ V =4.5V

DS(ON) G

Ω

R ( ) Ave @ V =10V

DS(ON) G

Ω

I , DRAIN SOURCE CURRENT (A)

Fig. 4 Typical On-Res istance v s .

Dr ain Curr ent and Temp erature

D

R , DRAIN-SOURCE ON-RESISTANCE( )

DS(ON)

Ω

0

0.04

0.08

0.12

0.16

0 2 4 6810

V = 4.5V

GS

Ave R ( ) @ 150°C

DS(ON)

Ω

Ave R ( ) @ -55°C

DS(ON)

Ω

Ave R ( ) @ 25°C

DS(ON)

Ω

Ave R ( ) @ 85°C

DS(ON)

Ω

Ave R ( ) @ 125°C

DS(ON)

Ω

-50 -25 0 25 50 75 100 125 150

T , JUNCTION TEMPERATURE ( C)

J

°

Fig. 5 On-Resistance Variation with Temperature

R , DRAIN-SOURCE ON-RESISTANCE

(Normalized)

DS(ON)

0.6

0.8

1

1.2

1.4

1.6

-50 -25 0 25 50 75 100 125 150

T , JUNCTION TEMPERATURE ( C)

J°

Fig. 6 On-Resistance Variatio n with Temperature

R , DRAIN-SOURCE ON-RESISTANCE

DS(ON)

0

0.02

0.04

0.06

0.08

0.1

0

0.4

0.8

1.6

1.2

2.4

-50 -25 0 25 50 75 100 125 150

V , GATE THRESHOLD VOLTAGE (V)

GS(th)

T , JUNCTION TEMPERATURE ( C)

Fig. 7 Gate Threshold Variation vs. Ambient Temperature

J

°

I = 250 A

D

µ

I = 1mA

D

2.0

I , SOURCE CURRENT (A)

S

00.2 0.4 0.6 0.8 1.0 1.2

V , SOURCE-DRAIN VOLTAGE (V)

Fig. 8 Diode Forward Voltage vs. Current

SD

0

2

4

6

8

10

V (V) @ V =0V T = 25 C

SD DS A

°

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DMG6602SVT

f = 1MHz

V , DRAIN-SOURCE VOLT AGE (V)

Fig. 9 Typica l J unction Cap acitanc e

DS

C , JUNCTION CAPACITANCE (pF)

T

C Ave (pF)

RSS

10

100

1000

0 5 10 15 20 25 30

C Ave (pF)

ISS

C Ave (pF)

OSS

0

2

4

6

8

10

0 2 4 6 810

V = 10V

I = 3. 0A

DS

D

Q (nC)

g

, TOTAL GATE CHARGE

Fig. 10 Gat e Charge

V GATE THRESHOLD VOLTAGE (V)

GS

0.1 110 100

V , DRAIN-SOURCE VOLTAGE (V)

Fig. 11 SOA, Safe Operation Area

DS

0.01

0.1

1

10

100

I , DRAIN CURRENT (A)

D

R

Limited

DS(on)

T = 150°C

T = 25°C

J(max)

A

V = 10V

Single Pulse

GS

DUT on 1 * MRP Board

DC

P = 10s

WP = 1s

W

P = 100ms

WP = 10ms

W P = 1ms

W

P = 100µs

W

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Electrical Characteristics – Q2 PMOS (@TA = +25°C unless otherwise specif i ed.)

Characteristic

Symbol

Min

Typ

Max

Unit

Test Condition

OFF CH ARACTERISTICS (Note 7)

Drain-Source Breakdown Voltage

BVDSS

-30

—

V

VGS = 0V , ID = -250µA

Zero Gate Voltage Drain Current

IDSS

—

-1.0

µA

VDS = -24V, VGS = 0 V

Gate-Source Leakage

IGSS

—

±100

nA

VGS = ±20V, VDS = 0V

ON CHARACTERIS TICS (Note 7)

Gate Threshold Voltage

VGS(th)

-1.0

—

-2.3

V

VDS = VGS, ID = -250μA

Static Drain-Source On-Resistance RDS (ON) —

73

99

95

140 mΩ

VGS = -10V, ID = -2.7A

VGS = -4.5V, I D = -2A

Forward Transfer Admittance

|Yfs|

—

6

—

S

VDS = -5V, ID = -2.7A

Diode Forward Voltage

VSD

—

-0.8

-1.0

V

VGS = 0V , IS = -1A

DYNAMIC CH ARACTERISTICS (Note 8)

Input Capacitance

Ciss

—

350

420

pF VDS = -15V, VGS = 0V,

f = 1.2MHz

Output Capacit ance

Coss

—

50

100

Reverse Transfer Capaci t ance

Crss

—

45

80

Gate Resistance

Rg

—

17.1

—

Ω

VDS = 0V, VGS = 0V, f = 1MHz

Total Gate Charge (VGS = -4.5V)

Qg

—

4

6

nC

VDS = -15V, VGS = -4.5V, ID = -3A

Total Gate Charge (VGS = -10V)

Qg

—

7

9

VDS = -15V, VGS = -10V, ID = -3A

Gate-Source Charge

Qgs

—

0.9

—

Gate-Drain Charge

Qgd

—

1.2

—

Turn-On Delay Time

tD(on)

—

4.8

—

ns VGS = -10V, VDS = -15V,

RG = 6Ω, RL = 15Ω

Turn-On Rise Time

tr

—

7.3

—

Turn-Off Delay Time

tD(off)

—

20

—

Turn-Off Fall Time

tf

—

13

—

Notes: 7. Short duration pulse test used to minimize self-heating effect.

8. Guaran te ed by design. Not s ubj ect t o prod uction testi ng.

00.5 11.5 22.5 33.5 44.5 5

V , DRAIN -SOURCE VOLTAGE(V)

Fig. 12 Typi c al Output Cha racteristics

DS

0.0

2.0

4.0

6.0

8.0

I , DRAIN CURRENT

D

V , GATE SOURCE VOLTAGE(V)

Fig. 13 Typi c al Trans fer Characteristi c s

GS

I , DRAIN CURRENT (A)

D

0

2

4

6

8

00.5 11.5 22.5 33.5 44.5 5

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I , DRAIN SOURCE CURRENT

Fig. 14 Typical On-Resistance vs.

Dr ain Current an d Gate Volta ge

D

R ,DRAIN-SOURCE ON-RESISTANCE( )

DS(ON)

Ω

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0 2

R ( ) Ave @ V =2.5V

DS(ON) G

Ω

R ( ) Ave @ V =4.5V

DS(ON) G

Ω

R ( ) Ave @ V =10V

DS(ON) G

Ω

4 86

0 2 4 6 8

I , DRAIN SOURCE CURRENT (A)

Fig. 15 Typical On-Resistance vs.

Dr ain Current an d Temp erature

D

R , DRAIN-SOURCE ON-RESISTANCE( )

DS(ON)

Ω

V = 4.5V

GS

0

0.04

0.08

0.12

0.16

0.2

Ave R ( ) @ 150°C

DS(ON)

Ω

Ave R ( ) @ -55°C

DS(ON)

Ω

Ave R ( ) @ 25°C

DS(ON)

Ω

Ave R ( ) @ 85°C

DS(ON)

Ω

Ave R ( ) @ 125°C

DS(ON)

Ω

-50 -25 0 25 50 75 100 125 150

T , JUNCTION TEMPERATURE ( C)

J

°

Fig. 16 On-Resis tance Variation with Temperature

R , DRAIN-SOURCE ON-RESISTANCE

(Normalized)

DS(ON)

0.6

0.8

1

1.2

1.4

1.6

-50 -25 0 25 50 75 100 125 150

T , JUNCTION TEMPERATURE ( C)

J

°

Fig. 17 On-Resis tance Variation with Tempe rature

R , DRAIN-SOURCE ON-RESISTANCE ()

DS(ON)

Ω

0

0.04

0.08

0.12

0.16

0.2

-50 -25 0 25 50 75 100 125 150

T , JUNCTION TEMPERATURE ( C)

J°

Fig. 18 Gat e Threshold Variation v s . Ambient Tempe rat ure

0

0.4

0.8

1.2

1.6

2

V , GATE THRESHOLD VOLTAGE (V)

GS(TH)

V , SOURCE -DRAIN VOLTAGE (V)

SD

Fig. 19 Diode Forward Voltage v s . Current

I , SOURCE CURRENT (V)

S

0

2

4

6

8

00.2 0.4 0.6 0.8 11.2 1.4

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-V , DRAIN-SOURCE VOLTAGE (V)

Fig. 20 Typic al Junction Cap acit ance

DS

C , JUNCTION CAPACITANCE (pF)

T

10

100

1000

0 5 10 15 20 25 30

f = 1MHz

C A ve(pF)

ISS

C Ave(pF)

OSS

C Av e(pF)

RSS

0

2

4

6

8

10

0 2 4 6 8 10

V = -15

I = -3A

DS

D

Q (nC)

g, TOTAL GATE CHARGE

Fig. 21 Gat e Charge

-V GATE THRESHOLD VOLTAGE (V)

GS

0.1 110 100

-V , DRAIN-SOURCE VOLTAGE (V)

Fig. 22 SOA, Safe Oper ation Area

DS

0.01

0.1

1

10

100

-I , DRAIN CURRENT (A)

D

R

Limited

DS(on)

T = 150°C

T = 25°C

J(max)

A

V = -10V

Single Pulse

GS

DUT on 1 * MRP Board

DC

P = 10s

WP = 1s

W

P = 100ms

WP = 10ms

W P = 1ms

W

P = 100µs

W

0.001

0.01

0.1

1

0.00001 0.0001 0.001 0.01 0.1 110 100 1000

t1, PULSE DURATION TIME (sec)

Fig. 23 Transient Thermal Resis tance

r(t), TRANSIENT THERMAL RESISTANCE

D = 0.9

D = 0.7

D = 0.5

D = 0.3

D = 0.1

D = 0.05

D = 0.02

D = 0.01

D = 0.005

Single Pulse

R (t) = r(t) * R

R = 164C/W

Duty Cycle, D = t1/ t2

θJA

θθJA JA

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Package Ou t lin e Dim en sio ns

Please see http://www.diodes.com/package-outlines.html for the latest version.

TSOT26

D

E1

E1/2

e1

E

E/2

e

A

A2

A1

Seating Plane

0

L2

L

Gauge Plane

01( 4x)

c

b

Seating Plane

TSOT26

Dim

Min

Max

Typ

A

−

1.00

−

A1

0.010

0.100

−

A2

0.840

0.900

−

D

2.800

3.000

2.900

E

2.800 BSC

E1

1.500

1.700

1.600

b

0.300

0.450

−

c

0.120

0.200

−

e

0.950 BSC

e1

1.900 BSC

L

0.30

0.50

−

L2

0.250 BSC

θ

0°

8°

4°

θ1

4°

12°

−

All Dimensions in mm

Suggested Pad Layout

Please see http://www.diodes.com/package-outlines.html for the latest version.

TSOT26

Y1

C

X

Y

Dimensions

Value (in mm)

C

0.950

X

0.700

Y

1.000

Y1

3.199

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IMPORTANT NOTICE

DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT,

INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

(AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION).

Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other changes

without further notice to this document and any product described herein. Diodes Incorporated does not assume any liability arising out of the

application or use of this document or any product described herein; neither does Diodes Incorporated convey any license under its patent or

trademark ri ghts, nor the rights of others. Any Customer or user of this document or products descri bed herein in such applic ations sh all ass ume

all risks of such use and will agree to hold Diodes Incorporated and all the companies whose products are represented on Diodes Incorporated

website, harml ess against all damages.

Diodes Incorporated does not warrant or acc ept any li ability whatsoever in respect of any products purchased through unauthori zed sales channel.

Should Customers purchase or use Diodes Incorporat ed products for any unintended or unauthorized application, Customers shall indemnify and

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indirect l y, any claim of personal injury or death associat ed with such unintended or unauthorized appl i cation.

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noted herein may also be covered by one or more United States, international or f orei gn trademarks.

This document is written in English but may be translated into multiple languages for reference. Only the English version of this document is the

final and determinative f orm at released by Diodes I ncorporat ed.

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written approval of the Chief Executive Off icer of Diodes I ncorporat ed. As us ed herein:

A. Life support devices or systems are devices or systems which:

1. are intended to implant into the body, or

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use provided in the labeling can be reasonably expected to result in significant injury to the user.

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Customers repres ent that they have all necessary expertise i n the safety and regulatory ramif ications of their life support devices or s y s t em s , and

acknowledge and agree that they are solely responsible for all legal, regulatory and safet y-related requi rements concerni ng their products and any

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representati ves against any dam ages arising out of the use of Diodes Incorporat ed products i n such safety-cri tical, life support devices or systems.

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