Multiformat SDTV Video Decoder ADV7181 FEATURES Multiformat video decoder supports NTSC-(M, N, 4.43), PAL-(B/D/G/H/I/M/N), SECAM Integrates three 54 MHz, 9-bit ADCs Clocked from a single 27 MHz crystal Line-locked clock compatible (LLC) Adaptive Digital Line Length Tracking (ADLLTTM) 5-line adaptive comb filters Proprietary architecture for locking to weak, noisy, and unstable video sources such as VCRs and tuners Subcarrier frequency lock and status information output Integrated AGC with adaptive peak white mode Macrovision(R) copy protection detection CTI (chroma transient improvement) DNR (digital noise reduction) Multiple programmable analog input formats: CVBS (composite video) S-Video (Y/C) YPrPb component (VESA, MII, SMPTE, and BetaCam) 6 analog video input channels Automatic NTSC/PAL/SECAM identification Digital output formats (8-bit or16-bit): ITU-R BT.656 YCrCb 4:2:2 output + HS, VS, and FIELD 0.5 V to 1.6 V analog signal input range Differential gain: 0.6% typ Differential phase: 0.6 typ Programmable video controls: Peak-white/hue/brightness/saturation/contrast Integrated on-chip video timing generator Free run mode (generates stable video ouput with no I/P) VBI decode support for Close captioning, WSS, CGMS, EDTV, Gemstar(R) 1x/2x Power-down mode 2-wire serial MPU interface (I2C(R) compatible) 3.3 V analog, 1.8 V digital core; 3.3 V IO supply Temperature grade:-40C to +85C 80-lead LQFP Pb-free package APPLICATIONS DVD recorders PC Video HDD-based PVRs/DVDRs LCD TVs Set-top boxes Security systems Digital televisions Portable video devices Automotive entertainment AVR receiver GENERAL DESCRIPTION The ADV7181 integrated video decoder automatically detects and converts a standard analog baseband television signal compatible with worldwide standards NTSC, PAL, and SECAM into 4:2:2 component video data compatible with 16-/8-bit CCIR601/CCIR656. The advanced and highly flexible digital output interface enables performance video decoding and conversion in linelocked clock based systems. This makes the device ideally suited for a broad range of applications with diverse analog video characteristics, including tape based sources, broadcast sources, security/surveillance cameras, and professional systems. The 6 analog input channels accept standard Composite, SVideo, YPrPb video signals in an extensive number of combinations. AGC and clamp restore circuitry allow an input video signal peak-to-peak range of 0.5 V up to 1.6 V. Alternatively, these can be bypassed for manual settings. The fixed 54 MHz clocking of the ADCs and datapath for all modes allows very precise, accurate sampling and digital filtering. The line-locked clock output allows the output data rate, timing signals, and output clock signals to be synchronous, asynchronous, or line locked even with 5% line length variation. The output control signals allow glueless interface connections in almost any application. The ADV7181 modes are set up over a 2-wire, serial, bidirectional port (I2C compatible). The ADV7181 is fabricated in a 3.3 V CMOS process. Its monolithic CMOS construction ensures greater functionality with lower power dissipation. The ADV7181 is packaged in a small 80-lead LQFP Pb-free package. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved. ADV7181 TABLE OF CONTENTS Introduction ...................................................................................... 4 SDP VBI Data Recovery ............................................................ 21 Analog Front End ......................................................................... 4 SDP General Setup ..................................................................... 21 Standard Definition Processor ................................................... 4 SDP Color Controls ................................................................... 24 Functional Block Diagram .............................................................. 5 SDP Clamp Operation............................................................... 26 Specifications..................................................................................... 6 SDP Luma Filter ......................................................................... 27 Electrical Characteristics ............................................................. 6 SDP Chroma Filter..................................................................... 30 Video Specifications..................................................................... 7 SDP Gain Operation .................................................................. 31 Timing Specifications .................................................................. 8 SDP Chroma Transient Improvement (CTI).......................... 35 Analog Specifications................................................................... 8 SDP Digital Noise Reduction (DNR) ...................................... 36 Thermal Specifications ................................................................ 8 SDP Comb Filters....................................................................... 36 Timing Diagrams.......................................................................... 9 SDP AV Code Insertion and Controls..................................... 39 Absolute Maximum Ratings.......................................................... 10 SDP Synchronization Output Signals...................................... 41 ESD Caution................................................................................ 10 SDP Sync Processing.................................................................. 50 Pin Configuration and Function Descriptions........................... 11 SDP VBI Data Decode ............................................................... 51 Analog Front End ........................................................................... 13 Pixel Port Configuration ............................................................... 62 Analog Input Muxing ................................................................ 13 MPU Port Description................................................................... 63 Global Control Registers ............................................................... 15 Register Accesses ........................................................................ 64 Power-Save Modes...................................................................... 15 Register Programming............................................................... 64 Reset Control .............................................................................. 15 I2C Sequencer.............................................................................. 64 Global Pin Control ..................................................................... 16 I2C Control Register Map.......................................................... 65 Global Status Registers................................................................... 18 I2C Register Map Details ........................................................... 69 Identification............................................................................... 18 Appendix A...................................................................................... 96 Status 1 ......................................................................................... 18 I2C Programming Examples ..................................................... 96 Status 2 ......................................................................................... 19 Appendix B...................................................................................... 99 Status 3 ......................................................................................... 19 PCB Layout Recommendations ............................................... 99 Standard Definition Processor (SDP).......................................... 20 Appendix C ................................................................................... 101 SD Luma Path ............................................................................. 20 Typical Circuit Connection .................................................... 101 SD Chroma Path......................................................................... 20 Outline Dimensions ..................................................................... 103 SDP Sync Processing.................................................................. 21 Ordering Guide ........................................................................ 104 Rev. A | Page 2 of 104 ADV7181 REVISION HISTORY Revision A 7/04--Changed from Rev. 0 to Rev. A. Addition to Applications List...........................................................1 Changes to Table 3 ............................................................................8 Changes to Table 5 ............................................................................8 Replaced Figure 3 ..............................................................................9 Changes to Global Pin Control Section .......................................16 Changes to Table 202 ......................................................................91 Changes to Table 203 ......................................................................92 Added package in Outline Dimensions Section .......................103 Changes to Ordering Guide.........................................................104 Revision 0 5/04--Revision 0: Initial Version Rev. A | Page 3 of 104 ADV7181 INTRODUCTION The ADV7181 is a high quality, single chip, multiformat video decoder that automatically detects and converts PAL, NTSC, and SECAM standards in the form of composite, S-Video, and component video into a digital ITU-R BT.656 format. The advanced and highly flexible digital output interface enables performance video decoding and conversion in line locked clock based systems. This makes the device ideally suited for a broad range of applications with diverse analog video characteristics, including tape based sources, broadcast sources, security/surveillance cameras, and professional systems. ANALOG FRONT END The ADV7181 analog front-end comprises three 9-bit ADCs that digitize the analog video signal before applying it to the standard definition processor. The analog front end employs differential channels to each ADC to ensure high performance in mixed-signal applications. The front end also includes a 6-channel input mux that enables multiple video signals to be applied to the ADV7181. Current and voltage clamps are positioned in front of each ADC to ensure that the video signal remains within the range of the converter. Fine clamping of the video signals is performed downstream by digital fine clamping within the ADV7181. The ADCs are configured to run in 4x oversampling mode. STANDARD DEFINITION PROCESSOR The ADV7181 is capable of decoding a large selection of baseband video signals in composite, S-Video, and component formats. The video standards supported by the SDP include PAL B/D/I/G/H, PAL60, PAL M, PAL N, PAL Nc, NTSC M/J, NTSC 4.43, and SECAM B/D/G/K/L. The ADV7181 can automatically detect the video standard and process it accordingly. The ADV7181 has a 5-line, superadaptive, 2D comb filter that gives superior chrominance and luminance separation when decoding a composite video signal. This highly adaptive filter automatically adjusts its processing mode according to video standard and signal quality with no user intervention required. Video user controls such as brightness, contrast, saturation, and hue are also available within the ADV7181. The ADV7181 implements a patented adaptive digital linelength tracking (ADLLT) algorithm to track varying video line lengths from sources such as a VCR. ADLLT enables the ADV7181 to track and decode poor quality video sources such as VCRs, noisy sources from tuner outputs, VCD players, and camcorders. The ADV7181 contains a chroma transient improvement (CTI) processor that sharpens the edge rate of chroma transitions, resulting in sharper vertical transitions. The SDP can process a variety of VBI data services such as closed captioning (CC), wide screen signaling (WSS), copy generation management system (CGMS), EDTV, Gemstar 1x/2x, and extended data service (XDS). The ADV7181 is fully Macrovision certified; detection circuitry enables Type I, II, and III protection levels to be identified and reported to the user. The decoder is also fully robust to all Macrovision signal inputs. Rev. A | Page 4 of 104 INPUT MUX SCLK SDA ALSB CVBS S-VIDEO YPrPb 6 A/D CLAMP 9 9 9 SERIAL INTERFACE CONTROL AND VBI DATA SYNC PROCESSING AND CLOCK GENERATION A/D A/D CLAMP CLAMP Figure 1. Rev. A | Page 5 of 104 CONTROL AND DATA ADV7181 SYNC AND CLK CONTROL DECIMATION AND DOWNSAMPLING FILTERS DATA PREPROCESSOR 9 9 CHROMA DIGITAL FINE CLAMP STANDARD AUTODETECTION MACROVISION DETECTION GAIN CONTROL LINE LENGTH PREDICTOR GAIN CONTROL GLOBAL CONTROL CHROMA FILTER SYNC EXTRACT LUMA FILTER VBI DATA RECOVERY CHROMA DEMOD FSC RECOVERY LUMA DIGITAL FINE CLAMP STANDARD DEFINITION PROCESSOR CHROMA 2D COMB (4H MAX) CTI C-DNR AV CODE INSERTION L-DNR LUMA 2D COMB (4H MAX) FREE RUN OUTPUT CONTROL SYNTHESIZED LLC CONTROL CHROMA RESAMPLE RESAMPLE CONTROL LUMA RESAMPLE 16 8 8 SFL LLC FIELD VS HS PIXEL DATA 04820-0-001 AIN1-AIN6 ADV7181 FUNCTIONAL BLOCK DIAGRAM OUTPUT FORMATTER ADV7181 SPECIFICATIONS Temperature range: TMIN to TMAX, -40C to +85C. The min/max specifications are guaranteed over this range. ELECTRICAL CHARACTERISTICS At AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V (operating temperature range, unless otherwise noted). Table 1. Parameter STATIC PERFORMANCE Resolution (Each ADC) Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS Input High Voltage Input Low Voltage Input Current Input Capacitance DIGITAL OUTPUTS Output High Voltage Output Low Voltage High Impedance Leakage Current Output Capacitance POWER REQUIREMENTS1 Digital Core Power Supply Digital I/O Power Supply PLL Power Supply Analog Power Supply Digital Core Supply Current Digital I/O Supply Current PLL Supply Current Analog Supply Current Power-Down Current Power-Up Time Symbol Test Conditions N INL DNL BSL at 54 MHz BSL at 54 MHz VIH VIL IIN Min Typ Max Unit -0.5/+0.65 -0.3/+0.6 9 2 -1/+2 Bits LSB LSB 0.8 +50 +10 10 V V A A pF 0.4 10 20 V V A pF 2 Pin 29 All other pins -50 -10 ISOURCE = 0.4 mA ISINK = 3.2 mA 2.4 CIN VOH VOL ILEAK COUT DVDD DVDDIO PVDD AVDD IDVDD IDVDDIO IPVDD IAVDD 1.65 3.0 1.65 3.15 CVBS input2 YPrPb input3 IPWRDN tPWRUP 1 Guaranteed by characterization. ADC1 and ADC2 powered down. 3 All three ADCs powered on. 2 Rev. A | Page 6 of 104 1.8 3.3 1.8 3.3 80 2 10.5 85 180 1.5 20 2 3.6 2.0 3.45 V V V V mA mA mA mA mA mA ms ADV7181 VIDEO SPECIFICATIONS Guaranteed by characterization. At AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V (operating temperature range, unless otherwise noted). Table 2. Parameter NONLINEAR SPECIFICATIONS Differential Phase Differential Gain Luma Nonlinearity NOISE SPECIFICATIONS SNR Unweighted Analog Front End Crosstalk LOCK TIME SPECIFICATIONS Horizontal Lock Range Vertical Lock Range Fsc Subcarrier Lock Range Color Lock In Time Sync Depth Range Color Burst Range Vertical Lock Time Autodetection Switch Speed CHROMA SPECIFICATIONS Hue Accuracy Color Saturation Accuracy Color AGC Range Chroma Amplitude Error Chroma Phase Error Chroma Luma Intermodulation LUMA SPECIFICATIONS Luma Brightness Accuracy Luma Contrast Accuracy Symbol Test Conditions DP DG LNL Min Typ Max Unit CVBS I/P, modulate 5-step CVBS I/P, modulate 5-step CVBS I/P, 5-step 0.6 0.6 0.6 0.7 0.7 0.7 % % Luma ramp Luma flat field 54 58 60 -5 40 dB dB dB +5 70 1.3 60 20 5 200 200 2 100 HUE CL_AC 1 1 0.5 0.5 0.2 % % % % 1 1 % % 5 CVBS, 1 V I/P CVBS, 1 V I/P Rev. A | Page 7 of 104 % Hz kHz Lines % % Fields seconds 200 ADV7181 TIMING SPECIFICATIONS Guaranteed by characterization. At AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V (operating temperature range, unless otherwise noted). Table 3. Parameter SYSTEM CLOCK AND CRYSTAL Nominal Frequency Frequency Stability I2C PORT SCLK Frequency SCLK Min Pulse Width High SCLK Min Pulse Width Low Hold Time (Start Condition) Setup Time (Start Condition) SDA Setup Time SCLK and SDA Rise Time SCLK and SDA Fall Time Setup Time for Stop Condition RESET FEATURE Reset Pulse Width CLOCK OUTPUTS LLC1 Mark Space Ratio DATA AND CONTROL OUTPUTS Data Output Transitional Time Data Output Transitional Time Symbol Test Conditions Min Typ Max Unit 50 MHz ppm 27.00 400 t1 t2 t3 t4 t5 t6 t7 t8 kHz s s s s ns ns ns s 0.6 1.3 0.6 0.6 100 300 300 0.6 5 t9:t10 ms 45:55 t11 t12 tACCESS = t10 - t11 tHOLD = t9 + t12 55:45 % Duty Cycle 6 0.1 ns ns ANALOG SPECIFICATIONS Guaranteed by characterization. At AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V (operating temperature range, unless otherwise noted). Table 4. Parameter CLAMP CIRCUITRY External Clamp Capacitor Input Impedance Large Clamp Source Current Large Clamp Sink Current Fine Clamp Source Current Fine Clamp Sink Current Symbol Test Conditions Min Clamps switched off Typ Max 0.1 10 0.75 0.75 60 60 Unit F M mA mA A A THERMAL SPECIFICATIONS Table 5. Parameter THERMAL CHARACTERISTICS Junction-to-Ambient Thermal Resistance (Still Air) Junction-to-Case Thermal Resistance Junction-to-Ambient Thermal Resistance (Still Air) Junction-to-Case Thermal Resistance Symbol Test Conditions JA 4-layer PCB with solid ground plane, 64-lead LFCSP 45.5 C/W JC JA 4-layer PCB with solid ground plane, 64-lead LFCSP 4-layer PCB with solid ground plane, 64-lead LQFP 9.2 47 C/W C/W JC 4-layer PCB with solid ground plane, 64-lead LQFP 11.1 C/W Rev. A | Page 8 of 104 Min Typ Max Unit ADV7181 TIMING DIAGRAMS t5 t3 t3 SDA t1 t6 t2 t4 t7 04819-0-003 SCLK t8 Figure 2. I2C Timing t9 t10 OUTPUT LLC1 t11 OUTPUTS P0-P15, VS, HS, FIELD, SFL/SYNC_OUT Figure 3. Pixel Port and Control Output Timing Rev. A | Page 9 of 104 04821-0-004 t12 ADV7181 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter AVDD to GND AVDD to AGND DVDD to DGND PVDD to AGND DVDDIO to DGND DVDDIO to AVDD PVDD to DVDD DVDDIO - PVDD DVDDIO - DVDD AVDD - PVDD AVDD - DVDD Digital Inputs Voltage to DGND Digital Output Voltage to DGND Analog Inputs to AGND Maximum Junction Temperature (TJMAX) Storage Temperature Range Infrared Reflow Soldering (20 s) Rating 4V 4V 2.2 V 2.2 V 4V -0.3 V to +0.3 V -0.3 V to +0.3 V -0.3V to +2 V -0.3V to +2 V -0.3V to +2 V -0.3V to +2 V -0.3V to DVDDIO + 0.3 V -0.3V to DVDDIO + 0.3 V AGND - 0.3 V to AVDD + 0.3 V 150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. -65C to +150C 260C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 10 of 104 ADV7181 VS FIELD P12 P13 P14 P15 DVDD DGND NC NC SCLK SDATA ALSB RESET NC AIN6 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 AIN5 47 AIN4 DGND 3 46 AIN3 DVDDIO 4 45 AGND P11 5 44 CAPC2 P10 6 43 AGND P9 7 42 CML 41 REFOUT 40 AVDD 39 CAPY2 DVDDIO 11 38 CAPY1 NC 12 37 AGND NC 13 36 AIN2 P7 14 35 AIN1 P6 15 34 DGND P5 16 33 NC HS 2 PIN 1 INDICATOR ADV7181 P8 8 TOP VIEW (Not to Scale) SFL 9 26 27 28 29 30 31 32 ELPF PVDD AGND XTAL1 25 PWRDN LLC 24 NC P2 23 NC P3 NC = NO CONNECT 22 P0 21 P1 20 DGND 19 DVDD 18 XTAL 17 P4 DGND 10 04820-0-002 NC 1 Figure 4. 64-Lead LFCSP/LQFP Pin Configuration Table 7. Pin Function Descriptions Pin No. 3, 10, 24, 34, 57 32, 37, 43, 45 4, 11 25, 58 40 31 35, 36, 46-49 1, 12, 13, 27, 28, 33, 50, 55, 56 5-8, 14-19, 25, 26, 59-62 2 64 63 53 54 52 Mnemonic DGND AGND DVDDIO DVDD AVDD PVDD AIN1-AIN6 NC Type G G P P P P I Function Digital Ground. Analog Ground. Digital I/O Supply Voltage (3.3 V). Digital Core Supply Voltage (1.8 V). Analog Supply Voltage (3.3 V). PLL Supply Voltage (1.8 V). Analog Video Input Channels. No Connect Pins. P0-P15 O Video Pixel Output Port. HS VS FIELD SDA SCLK ALSB O O O I/O I I 51 RESET I 20 LLC O 22 XTAL I 21 XTAL1 O 29 PWRDN I HS is a horizontal synchronization output signal. VS is a vertical synchronization output signal. FIELD is a field synchronization output signal. I2C Port Serial Data Input/Output Pin. I2C Port Serial Clock Input (Max Clock Rate of 400 kHz). This pin selects the I2C address for the ADV7181. ALSB set to a Logic 0 sets the address for a write as 0x40; for ALSB set to a logic high, the address selected is 0x42. System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to reset the ADV7181 circuitry. This is a line-locked output clock for the pixel data output by the ADV7181. Nominally 27 MHz, but varies up or down according to video line length. This is the input pin for the 27 MHz crystal, or can be overdriven by an external 3.3 V, 27 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal. This pin should be connected to the 27 MHz crystal or left as a no connect if an external 3.3 V, 27 MHz clock oscillator source is used to clock the ADV7181. In crystal mode, the crystal must be a fundamental crystal. A logic low on this pin places the ADV7181 in a power-down mode. Refer to the I2C Control Register Map section for more options on power-down modes for the ADV7181. Rev. A | Page 11 of 104 ADV7181 Pin No. 30 Mnemonic ELPF Type I 9 SFL O 41 REFOUT O 42 CML O 38, 39 CAPY1, CAPY2 I 44 CAPC2 I Function The recommended external loop filter must be connected to this ELPF pin, as shown in Figure 41. Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock the subcarrier frequency when this decoder is connected to any Analog Devices digital video encoder. Internal Voltage Reference Output. Refer to Figure 41 for a recommended capacitor network for this pin. The CML pin is a common-mode level for the internal ADCs. Refer to Figure 41 for a recommended capacitor network for this pin. ADC's Capacitor Network. Refer to Figure 41 for a recommended capacitor network for this pin. ADC's Capacitor Network. Refer to Figure 41 for a recommended capacitor network for this pin. Rev. A | Page 12 of 104 ADV7181 ANALOG FRONT END AIN2 AIN1 AIN4 AIN3 AIN6 AIN5 ADC_SW_MAN_EN AIN2 AIN1 AIN4 AIN3 AIN6 AIN5 ADC0_SW[3:0] ADC0 AIN4 AIN3 AIN6 AIN5 ADC1_SW[3:0] ADC1 AIN6 AIN5 ADC2 04820-0-006 ADC0_SW[3:0] Figure 5. Internal Pin Connections There are two key steps to configure the ADV7181 to correctly decode the input video. Descriptions of these steps follow. SETADC_sw_man_en, Manual Input Muxing Enable, Address C4, [7] 1. The analog input muxing section must be configured to correctly route the video from the analog input pins to the correct set of ADCs. ADC0_sw[3:0], ADC0 mux configuration, Address C3, [3:0] ADC1_sw[3:0], ADC1 mux configuration, Address C3, [7:4] ADC2_sw[3:0], ADC2 mux configuration, Address C4, [3:0] 2. The standard definition processor block, which decodes the digital data, should be configured to process either CVBS, YC, or YPrPb. To configure the ADV7181 analog muxing section, the user must select the analog input (AIN1-AIN6) that is to be processed by each ADC. SETADC_sw_man_en must be set to 1 to enable the muxing blocks to be configured. The three mux sections are controlled by the signal buses ADC0/1/2_sw[3:0]. Table 8 explains the control words used. ANALOG INPUT MUXING The ADV7181 has an integrated analog muxing section that allows more than one source of video signal to be connected to the decoder. Figure 5 outlines the overall structure of the input muxing provided in the ADV7181. A maximum of 6 CVBS inputs can be connected and decoded by the ADV7181. As can be seen from the Pin Configuration and Function Description section, these analog input pins lie in close proximity to one another. This calls for a careful design of the PCB layout (e.g., ground shielding between all signals routed through tracks that are physically close together). It is strongly recommended to connect any unused analog input pins to AGND to act as a shield. The input signal that contains the timing information (H/V syncs) must be processed by ADC0. For example, in YC input configuration, ADC0 should be connected to the Y channel and ADC1 to the C channel. In cases where one or more ADCs are not used to process video (e.g., CVBS input), the idle ADCs should be powered down, (see the ADC Power-Down Control section). There are restrictions on the channel routing imposed by the analog signal routing inside the IC; every input pin cannot be routed to each ADC. Refer to Table 8 for an overview on the routing capabilities inside the chip. Rev. A | Page 13 of 104 ADV7181 Table 8. Manual Mux Settings for All ADCs SETADC_sw_man_en = 1 ADC1_sw[3:0] ADC1 connected to: 0000 No Connection 0001 No Connection 0010 No Connection 0011 No Connection 0100 AIN4 0101 AIN6 0110 No Connection 0111 No Connection 1000 No Connection 1001 No Connection 1010 No Connection 1011 No Connection 1100 AIN3 1101 AIN5 1110 No Connection 1111 No Connection ADC0 connected to: No Connection AIN2 No Connection No Connection AIN4 AIN6 No Connection No Connection No Connection AIN1 No Connection No Connection AIN3 AIN5 No Connection No Connection CONNECTING ANALOG SIGNALS TO ADV7181 ADC2 connected to: No Connection No Connection No Connection No Connection No Connection AIN6 No Connection No Connection No Connection No Connection No Connection No Connection No Connection AIN5 No Connection No Connection The INSEL bits allow the user to select the input format. It configures the Standard Definition Processor core to process CVBS (Comp), S-Video (Y/C) or Component (YPbPr) format. SET INSEL[3:0] TO CONFIGURE ADV7181 TO DECODE VIDEO FORMAT: CVBS: 0000 YC: 0110 YPrPb: 1001 CONFIGURE ADC INPUTS USING MUXING CONTROL BITS (ADC_sw_man_en, ADC0_sw,adc1_sw, ADC2_sw) ADC2_sw[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 INSEL[3:0] Input Selection, Address 0x00, [3:0] Table 9. Standard Definition Processor Format Selection, INSEL[3:0] 04820-0-007 ADC0_sw[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Figure 6. Input Muxing Overview INSEL[3:0] 0000 0110 1001 Rev. A | Page 14 of 104 Video Format (SDP) Composite YC YPrPb ADV7181 GLOBAL CONTROL REGISTERS Register control bits listed in this section affect the whole chip. POWER-SAVE MODES PWRDN_ADC_0 0* 1 Power-Down PDBP, Address 0x0F, [2] There are two ways to shut down the digital core of the ADV7181: a pin (PWRDN) and a bit (PWRDN see below). The PDBP controls which of the two has the higher priority. The default is to give the pin (PWRDN) priority. This allows the user to have the ADV7181 powered down by default. Table 10. PDBP Function PDBP 0* 1 PWRDN_ADC_0, Address 0x3A, [3] Table 12. PWRDN_ADC_0 Function Description Digital core power controlled by the PWRDN pin (bit is disregarded). Bit has priority (pin is disregarded). *Default value. PWRDN_ADC_1, Address 0x3A, [2] Table 13. PWRDN_ADC_1 Function PWRDN_ADC_1 0* 1 Description ADC normal operation. Power down ADC 1. *Default value. PWRDN_ADC_2, Address 0x3A, [1] Table 14. PWRDN_ADC_2 Function PWRDN_ADC_2 0* 1 *Default value. PWRDN, Address 0x0F, [5] Setting the PWRDN bit switches the ADV7181 into a chip-wide power-down mode. The power-down stops the clock from entering the digital section of the chip, thereby freezing its operation. No I2C bits are lost during power-down. The PWRDN bit also affects the analog blocks and switches them into low current modes. The I2C interface itself is unaffected, and remains operational in power-down mode. The ADV7181 leaves the power-down state if the PWRDN bit is set to 0 (via I2C), or if the overall part is reset using Pin RESET. Note that PDBP must be set to 1 for the PWRDN bit to power down the ADV7181. Description Chip operational. ADV7181 in chip-wide power-down. *Default value. RESET CONTROL Chip Reset (RES), Address 0x0F, [7] Setting this bit, equivalent to controlling the RESET pin on the ADV7181, issues a full chip reset. All I2C registers get reset to their default values4. After the reset sequence, the part immediately starts to acquire the incoming video signal. Notes * After setting the RES bit (or initiating a reset via the pin), the part returns to the default mode of operation with respect to its primary mode of operation. All I2C bits are loaded with their default values, making this bit selfclearing. * Executing a software reset takes approximately 2 ms. However, it is recommended to wait 5 ms before any further I2C writes are performed. * The I2C master controller receives a no acknowledge condition on the ninth clock cycle when Chip Reset is implemented. See the MPU Port Description section. ADC Power-Down Control The ADV7181 contains three 9-bit ADCs (ADC 0, ADC 1, and ADC 2). If required, it is possible to power down each ADC individually. Description ADC normal operation. Power down ADC 2. *Default value. Table 11. PWRDN Function PWRDN 0* 1 Description ADC normal operation. Power down ADC 0. When should the ADCs be powered down? Table 15. RES Function * CVBS mode. ADC 1 and ADC 2 should be powered down to save on power consumption. * S-Video mode. ADC 2 should be powered down to save on power consumption RES 0* 1 Description Normal operation. Start reset sequence. *Default value. 4 Some register bits do not have a reset value specified. They keep their last written value. Those bits are marked as having a reset value of x in the register table. Rev. A | Page 15 of 104 ADV7181 Timing Signals Output Enable GLOBAL PIN CONTROL Three-State Output Drivers TIM_OE, Address 0x04, [3] TOD, Address 0x03, [6] This bit allows the user to three-state the output drivers of the ADV7181. Upon setting the TOD bit, the P15-P0, HS, VS, FIELD, and SFL pins are three-stated. Note that the timing pins (HS/VS/FIELD) can be forced active via the TIM_OE bit. For more information on three-state control, refer to the following sections: * Three-State LLC Driver * Timing Signals Output Enable The TIM_OE bit should be regarded as an addition to the TOD bit. Setting it high forces the output drivers for HS, VS, and FIELD into the active (i.e., driving) state even if the TOD bit is set. If set to low, the HS, VS, and FIELD pins are three-stated dependent on the TOD bit. This functionality is useful if the decoder is to be used as a timing generator only. This may be the case if only the timing signals are to be extracted from an incoming signal, or if the part is in free-run mode where a separate chip can output, for instance, a company logo. For more information on three-state control, refer to the following sections: * Three-State Output Drivers Individual drive strength controls are provided via the DR_STR_XX bits. * Three-State LLC Driver Table 16. TOD Function Individual drive strength controls are provided via the DR_STR_XX bits. TOD 0* 1 Description Output drivers enabled. Output drivers three-stated. Table 18. TIM_OE Function TIM_OE 0* 1 *Default value. Three-State LLC Driver *Default value. TRI_LLC, Address 0x0E, [6] This bit allows the output drivers for the LLC pin of the ADV7181 to be three-stated. For more information on threestate control, refer to the following sections: * Three-State Output Drivers * Timing Signals Output Enable Individual drive strength controls are provided via the DR_STR_XX bits. Table 17. TRI_LLC Function TRI_LLC 0* 1 *Default value. Description LLC pin drivers working according to the DR_STR_C[1:0] setting (pin enabled). LLC pin drivers three-stated. Description HS, VS, FIELD three-stated according to the TOD bit. HS, VS, FIELD are forced active all the time. The DR_STR_S[1:0] setting determines drive strength. Drive Strength Selection (Data) DR_STR[1:0] Address 0x04, [5:4] For EMC and crosstalk reasons, it may be desirable to strengthen or weaken the drive strength of the output drivers. The DR_STR[1:0] bits affect the P[15:0] output drivers. For more information on three-state control, refer to the following sections: * Drive Strength Selection (Clock) * Drive Strength Selection (Sync) Table 19. DR_STR Function DR_STR[1:0] 00 01* 10 11 *Default value. Rev. A | Page 16 of 104 Description Low drive strength (1x). Medium low drive strength (2x). Medium high drive strength (3x). High drive strength (4x). ADV7181 Drive Strength Selection (Clock) Enable Subcarrier Frequency Lock Pin DR_STR_C[1:0] Address 0x0E, [3:2] EN_SFL_PIN Address 0x04, [1] The DR_STR_C[1:0] bits can be used to select the strength of the clock signal output driver (LLC pin). For more information, refer to the following sections: The subcarrier frequency lock pin (SDP, output only) has a double function: it can also output raw sync-related information (SogOut). The EN_SFL_PIN bit enables the output of subcarrier lock information (also known as GenLock) from the SDP core to an encoder in a decoder-encoder back-to-back arrangement. * Drive Strength Selection (Sync) * Drive Strength Selection (Data) Table 22. EN_SFL_PIN Table 20. DR_STR Function DR_STR[1:0] 00 01* 10 11 EN_SFL_PIN 0* 1 Description Low drive strength (1x). Medium low drive strength (2x). Medium high drive strength (3x). High drive strength (4x). Description Subcarrier frequency lock output is disabled. Subcarrier frequency lock information is presented on the SFL pin. *Default value. *Default value. Polarity LLC Pin Drive Strength Selection (Sync) PCLK Address 0x37, [0] DR_STR_S[1:0] Address 0x0E, [1:0] The polarity of the clock that leaves the ADV7181 via the LLC pin can be inverted using the PCLK bit. Note that this inversion affects the clock for SDP. The DR_STR_S[1:0] bits allow the user to select the strength of the synchronization signals with which HS, VS, and F are driven. For more information, refer to the following sections: * Drive Strength Selection (Data) Changing the polarity of the LLC clock output may be necessary to meet the setup-and-hold time expectations of follow-on chips. Table 21. DR_STR Function Table 23. PCLK Function DR_STR[1:0] 00 01* 10 11 PCLK 0 1* Description Low drive strength (1x). Medium low drive strength (2x). Medium high drive strength (3x). High drive strength (4x). *Default value. *Default value. Rev. A | Page 17 of 104 Description Invert LLC output polarity. LLC output polarity normal (as per the Timing Diagrams) ADV7181 GLOBAL STATUS REGISTERS There are four registers that provide summary information about the video decoder. The IDENT register allows the user to identify the revision code of the ADV7181. The other three registers contain status bits from the SDP. Depending on the setting of the FSCLE bit, the Status[0] and Status[1] are based solely on horizontal timing info or on the horizontal timing and lock status of the color subcarrier. See the FSCLE Fsc Lock Enable (SDP), Address 0x51, [7] section. IDENTIFICATION SDP Autodetection Result IDENT[7:0] Address 0x11, [7:0] AD_RESULT[2:0] Address 0x10, [6:4] Provides identification of the revision of the ADV7181. Please review the list of IDENT code readback values for the various versions shown in Table 24. The AD_RESULT[2:0] bits report back on the findings from the SDP autodetection block. Consult the SDP General Setup section for more information on enabling the autodetection block, and the Autodetection of SDP Modes section to find out how to configure it. Table 24. IDENT Function IDENT[7:0] 0x0D 0x0E 0x0F or 0x10 0x11 Description ADV7181-ES1 ADV7181-ES2 ADV7181-FT ADV7181 (Version 2) Table 25. AD_RESULT Function STATUS 1 STATUS_1[7:0] Address 0x10, [7:0] This read-only register provides information about the internal status of the ADV7181. AD_RESULT[2:0] 000 001 010 011 100 101 110 111 Description NTSM-MJ NTSC-443 PAL-M PAL-60 PAL-BGHID SECAM PAL-Combination N SECAM 525 Please see CIL[2:0] Count Into Lock (SDP), Address 0x51, [2:0] and COL[2:0] Count Out of Lock (SDP), Address 0x51, [5:3] for information on the timing. Table 26. STATUS 1 Function STATUS 1 [7:0] 0 1 2 3 4 5 6 7 Bit Name IN_LOCK LOST_LOCK FSC_LOCK FOLLOW_PW AD_RESULT.0 AD_RESULT.1 AD_RESULT.2 COL_KILL Block SDP SDP SDP SDP SDP SDP SDP SDP Description In lock (right now). Lost lock (since last read of this register). Fsc locked (right now). AGC follows peak white algorithm. Result of SDP autodetection. Result of SDP autodetection. Result of SDP autodetection. Color kill active. Rev. A | Page 18 of 104 ADV7181 STATUS 2 STATUS_2[7:0], Address 0x12, [7:0] Table 27. STATUS 2 Function STATUS 2 [7:0] 0 1 2 3 4 5 6 7 Bit Name MVCS DET MVCS T3 MV_PS DET MV_AGC DET LL_NSTD FSC_NSTD Reserved Reserved Block SDP SDP SDP SDP SDP SDP Description Detected Macrovision color striping. Macrovision color striping protection. Conforms to Type 3 (if high), and Type 2 (if low). Detected Macrovision pseudo Sync pulses. Detected Macrovision AGC pulses. Line length is nonstandard. Fsc frequency is nonstandard. STATUS 3 STATUS_3[7:0], Address 0x13, [7:0] Table 28. STATUS 3 Function STATUS 3 [7:0] 0 1 2 3 4 Bit Name INST_HLOCK Block SDP FREE_RUN_ACT SDP 5 6 7 STD_FLD_LEN INTERLACED PAL_SW_LOCK SDP SDP SDP Description Horizontal lock indicator (instantaneous). Reserved for future use. Reserved for future use. Reserved for future use. SDP outputs a blue screen (see theDEF_VAL_AUTO_EN Default Value Automatic Enable (SDP), Address 0x0C, [1] section). Field length is correct for currently selected video standard. Interlaced video detected (field sequence found). Reliable sequence of swinging bursts detected. Rev. A | Page 19 of 104 ADV7181 STANDARD DEFINITION PROCESSOR (SDP) STANDARD DEFINITION PROCESSOR MACROVISION DETECTION DIGITIZED CVBS DIGITIZED Y (YC) DIGITIZED CVBS DIGITIZED C (YC) VBI DATA RECOVERY LUMA DIGITAL FINE CLAMP CHROMA DIGITAL FINE CLAMP CHROMA DEMOD STANDARD AUTODETECTION SLLC CONTROL LUMA FILTER GAIN CONTROL LUMA RESAMPLE SYNC EXTRACT LINE LENGTH PREDICTOR RESAMPLE CONTROL CHROMA FILTER GAIN CONTROL CHROMA RESAMPLE LUMA 2D COMB AV CODE INSERTION CHROMA 2D COMB VIDEO DATA OUTPUT MEASUREMENT BLOCK (= >12C) VIDEO DATA PROCESSING BLOCK 04819-0-008 FSC RECOVERY Figure 7. Block Diagram of the Standard Definition Processor A block diagram of the ADV7181's standard definition processor (SDP) is shown in Figure 7. SD CHROMA PATH The SDP block can handle standard definition video in CVBS, YC, and YPrPb formats. It can be divided into a luminance and chrominance path. If the input video is of a composite type (CVBS), both processing paths are fed with the CVBS input. * Digital Fine Clamp. This block uses a high precision algorithm to clamp the video signal. * Digital Fine Clamp. This block uses a high precision algorithm to clamp the video signal. Chroma Demodulation. This block employs a color subcarrier (Fsc) recovery unit to regenerate the color subcarrier for any modulated chroma scheme. The demodulation block then performs an AM demodulation for PAL and NTSC ,and an FM demodulation for SECAM. * Luma Filter Block. This block contains a luma decimation filter (YAA) with a fixed response, and some shaping filters (YSH) that have selectable responses. Chroma Filter Block. This block contains a chroma decimation filter (CAA) with a fixed response, and some shaping filters (CSH) that have selectable responses. * Gain Control. Automatic gain control (AGC) can operate on several different modes, including gain based on the color subcarrier's amplitude, gain based on the depth of the horizontal sync pulse on the Luma channel, or fixed manual gain. * Chroma Resample. The chroma data is digitally resampled to keep it perfectly aligned with the luma data. The resampling is done to correct for static and dynamic linelength errors of the incoming video signal. The input signal is processed by the following blocks: SD LUMA PATH The input signal is processed by the following blocks: * * * Luma Gain Control. The automatic gain control (AGC) can operate on a variety of different modes, including gain based on the depth of the horizontal sync pulse, peak white mode, and fixed manual gain. * Luma Resample. To correct for line-length errors as well as dynamic line-length changes, the data is digitally resampled. * Luma 2D Comb. The two-dimensional comb filter provides YC separation. * * AV Code Insertion. At this point, the decoded luma (Y) signal is merged with the retrieved chroma values. AV codes (as per ITU-R. BT-656) can be inserted. Chroma 2D Comb. The two-dimensional, 5-line, superadaptive comb filter provides high quality YC separation in case the input signal is CVBS. * AV Code Insertion. At this point, the demodulated chroma (Cr and Cb) signal is merged with the retrieved luma values. AV codes (as per ITU-R. BT-656) can be inserted. Rev. A | Page 20 of 104 ADV7181 SDP SYNC PROCESSING SDP GENERAL SETUP The SDP extracts syncs embedded in the video data stream. There is currently no support for external HS/VS inputs. The sync extraction has been optimized to support imperfect video sources (e.g., videocassette recorders with head switches). The actual algorithm used employs a coarse detection based on a threshold crossing followed by a more detailed detection using an adaptive interpolation algorithm. The raw sync information is sent to a line-length measurement and prediction block. The output of this is then used to drive the digital resampling section to ensure that the SDP outputs 720 active pixels per line. Video Standard Selection (SDP) The sync processing on the ADV7181 also includes two specialized postprocessing blocks that filter and condition the raw sync information retrieved from the digitized analog video. * VSYNC Processor. This block provides extra filtering of the detected VSYNCs to give improved vertical lock. * HSYNC Processor. The HSYNC processor is designed to filter incoming HSYNCs that have been corrupted by noise, providing much improved performance for video signals with stable time base but poor SNR. SDP VBI DATA RECOVERY The SDP can retrieve the following information from the input video: * Wide-screen signaling (WSS) * Copy generation management system (CGMS) * Closed caption (CC) * Macrovision protection presence * EDTV data * Gemstar compatible data slicing The SDP is also capable of automatically detecting the incoming video standard with respect to * Color subcarrier frequency * Field rate * Line rate The VID_SEL[3:0] register allows the user to force the digital core into a specific video standard. Under normal circumstances, this should not be necessary. The VID_SEL[3:0] bits default to an autodetection mode that supports PAL, NTSC, SECAM, and variants thereof. Refer to the Autodetection of SDP Modes section for more information on the autodetection system. Autodetection of SDP Modes In order to guide the autodetect system of the SDP block, individual enable bits are provided for each of the supported video standards. Setting the relevant bit to 0 inhibits the standard from being detected automatically. Instead, the system picks the closest of the remaining enabled standards. The results of SDP autodetection can be read back via the status registers. See the Global Status Registers section for more information. Table 29. VID_SEL Function VID_SEL[3:0] Address 0x00 [7:4] 0000* 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Autodetect (PAL BGHID) <-> NTSC J. Autodetect (PAL BGHID) <-> NTSC M. Autodetect (PAL N) <-> NTSC J. Autodetect (PAL N) <-> NTSC M. NTSC J (1) NTSC M (1). PAL 60. NTSC 4.43 (1). PAL BGHID. PAL N (= PAL BGHID (with pedestal)). PAL M (without pedestal). PAL M. PAL combination N. PAL combination N (with pedestal). SECAM. SECAM (with pedestal). *Default value. AD_SEC525_EN Enable Autodetection of SECAM 525 line video (SDP), Address 0x07, [7] Table 30. AD_SEC525_EN Function and can configure itself to support PAL-BGHID, PAL-M/N, PAL-combination N, NTSC-M, NTSC-J, SECAM 50 Hz/60 Hz, NTSC4.43, and PAL60. AD_SEC525_EN 0* 1 *Default value. Rev. A | Page 21 of 104 Description Disable the autodetection of a 525-line system with a SECAM style, FM-modulated color component. Enable the detection. ADV7181 AD_SECAM_EN Enable Autodetection of SECAM (SDP), Address 0x07, [6] Table 31. AD_SECAM_EN Function AD_PAL_EN Enable Autodetection of PAL (SDP), Address 0x07, [0] Table 37. AD_PAL_EN Function AD_SECAM_EN 0 1* AD_PAL_EN 0 1* Description Disable the autodetection of SECAM. Enable the detection. *Default value. Description Disable the detection of standard PAL. Enable the detection. *Default value. SFL_INV Subcarrier Frequency Lock Inversion (SDP) AD_N443_EN Enable Autodetection of NTSC 443 (SDP), Address 0x07, [5] Table 32. AD_N443_EN Function AD_N443_EN 0 1* Description Disable the autodetection of NTSC style systems with a 4.43 MHz color subcarrier. Enable the detection. This bit controls the behavior of the PAL switch bit in the SFL (GenLock Telegram) data stream. It was implemented to solve some compatibility issues with video encoders. It solves two problems: 1. The PAL switch bit is only meaningful in PAL. Some encoders (including Analog Devices encoders) also look at the state of this bit in NTSC. 2. There was a design change in Analog Devices encoders from ADV717x to ADV719x. The older versions used the SFL (GenLock Telegram) bit directly, while the later ones invert the bit prior to using it. The reason for this is that the inversion compensated for the 1-line delay of an SFL (GenLock Telegram) transmission. *Default value. AD_P60_EN Enable Autodetection of PAL60 (SDP), Address 0x07, [4] Table 33. AD_P60_EN Function AD_P60_EN 0 1* Description Disable the autodetection of PAL systems with a 60 Hz field rate. Enable the detection. *Default value. As a result: AD_PALN_EN Enable Autodetection of PAL N (SDP), Address 0x07, [3] Table 34. AD_PALN_EN Function 1. ADV717x encoders need the PAL switch bit in the SFL (GenLock Telegram) to be 1 for NTSC to work. 2. ADV7190/ADV7191/ADV7194 encoders need the PAL switch bit in the SFL to be 0 to work in NTSC. AD_PALN_EN 0 1* Description Disable the detection of the PAL N standard. Enable the detection. *Default value. If the state of the PAL switch bit is wrong, a 180phase shift occurs. AD_PALM_EN Enable Autodetection of PAL M (SDP), Address 0x07, [2] Table 35. AD_PALM_EN Function In a decoder/encoder back-to-back system in which SFL is used, this bit must be set up properly for the specific encoder used. AD_PALM_EN 0 1* SFL_INV Address 0x41, [6] 0 Description Disable the autodetection of PAL M. Enable the detection. Table 38. SFL_INV Function *Default value. 1* AD_NTSC_EN Enable Autodetection of NTSC (SDP), Address 0x07, [1] Table 36. AD_NTSC_EN Function AD_NTSC_EN 0 1* *Default value. Description Disable the detection of standard NTSC. Enable the detection. *Default value. Rev. A | Page 22 of 104 Description SFL compatible with ADV7190/ADV7191/ ADV7194 encoders. SFL compatible with ADV717x/ADV7173x encoders. ADV7181 Lock Related Controls (SDP) CIL[2:0] Count Into Lock (SDP), Address 0x51, [2:0] Lock information is presented to the user through Bits [1:0] of the Status 1 register. See the STATUS_1[7:0] Address 0x10, [7:0] section. Figure 8 outlines the signal flow and the controls available to influence the way the lock status information is generated. CIL[2:0] determines the number of consecutive lines for which the into lock condition must be true before the system switches into the locked state, and reports this via Status 0 [1:0]. SRLS Select Raw Lock Signal (SDP), Address 0x51, [6] Using the SRLS bit, the user can choose between two sources for determining the lock status (per Bits [1:0] in the Status 1 register). * * The time_win signal is based on a line-to-line evaluation of the horizontal synchronization pulse of the incoming video. It reacts quite quickly. The free_run signal evaluates the properties of the incoming video over several fields, and takes vertical synchronization information into account. CIL[2:0] 000 001 010 011 100* 101 110 111 Description (Count Value in Lines of Video) 1 2 5 10 100 500 1000 100000 *Default value. COL[2:0] Count Out of Lock (SDP), Address 0x51, [5:3] COL[2:0] determines the number of consecutive lines for which the out of lock condition must be true before the system switches into unlocked state, and reports this via Status 0 [1:0]. Table 39. SRLS Function SRLS 0* 1 Table 41. CIL Function Description Select the free_run signal. Select the time_win signal. Table 42. COL Function *Default value. FSCLE Fsc Lock Enable (SDP), Address 0x51, [7] The FSCLE bit allows the user to choose whether the status of the color subcarrier loop is taken into account when the overall lock status is determined and presented via Bits [1:0] in Status Register 1. This bit must be set to 0 when operating the SDP in YPrPb component mode in order to generate a reliable HLOCK status bit. COL[2:0] 000 001 010 011 100* 101 110 111 Description (Count Value in Lines of Video) 1 2 5 10 100 500 1000 100000 *Default value. Table 40. FSCLE Function FSCLE 0 1* Description Overall lock status only dependent on horizontal sync lock. Overall lock status dependent on horizontal sync lock and Fsc Lock. *Default value. SELECT THE RAW LOCK SIGNAL SRLS 1 0 0 1 FSC LOCK COUNTER INTO LOCK COUNTER OUT OF LOCK STATUS 1 [0] MEMORY STATUS 1 [1] 04819-0-009 TIME_WIN FREE_RUN FILTER THE RAW LOCK SIGNAL CIL[2:0], COL[2:0] TAKE FSC LOCK INTO ACCOUNT FSCLE Figure 8. SDP Lock Related Signal Path Rev. A | Page 23 of 104 ADV7181 SDP COLOR CONTROLS The following registers provide user control over the picture appearance, including control of the active data in the event of video being lost. They are independent of any other controls. For instance, brightness control is independent from picture clamping, although both controls affect the signal's dc level. SD_SAT_Cr[7:0] SD Saturation Cr Channel (SDP), Address 0xE4, [7:0] This register allows the user to control the gain of the Cr channel only. This register affects the SDP core only. This is the user control for contrast adjustment for the SDP block only. For this register to be active, SAT[7:0] must be programmed with its default value of 0x80. If SAT[7:0] is programmed with a different value, SD_SAT_Cb[7:0] and SD_SAT_Cr[7:0] are inactive. Table 43. CON Function Table 46. SD_SAT_Cr Function CON[7:0] Contrast Adjust (SDP), Address 0x08, [7:0] CON[7:0] 0x80* 0x00 0xFF Description (Adjust Contrast of the Picture) Gain on luma channel = 1. Gain on luma channel = 0. Gain on luma channel = 2. SD_SAT_Cr[7:0] 0x80* 0x00 0xFF *Default value. Description (Adjust Saturation of the Picture) Chroma gain = 0 dB *Default value. SAT[7:0] Saturation Adjust (SDP), Address 0x09, [7:0] The user can adjust the saturation of the color output using this register. This registers affects the SDP core only. ADI encourages users not to use the SAT[7:0] register, which may be removed in future revisions of the ADV7181. Instead, the SD_SAT_Cb and SD_SAT_Cr registers should be used. SD_OFF_Cb[7:0] SD Offset Cb Channel (SDP), Address 0xE1, [7:0] This register allows the user to select an offset for the Cb channel only. This register affects the SDP core only. There is a functional overlap with the Hue [7:0] register. Table 47.SD_OFF_Cb Function Table 44. SAT Function SAT[7:0] 0x80* 0x00 0xFF Description (Adjust Saturation of the Picture) Chroma gain = 0 dB. Chroma gain = -42 dB. Chroma gain = 6 dB. SD_OFF_Cb[7:0] 0x80* 0x7F 0xFF *Default value. Description (Adjust Hue of the Picture by Selecting an Offset for Data on the Cb Channel) *Default value. SD_SAT_Cb[7:0] SD Saturation Cb Channel (SDP), Address 0xE3, [7:0] SD_OFF_Cr [7:0] SD Offset Cr Channel (SDP), Address 0xE2, [7:0] This register allows the user to control the gain of the Cb channel only. For this register to be active , SAT[7:0] must be programmed with its default value of 0x80. If SAT[7:0] is programmed with a different value, SD_SAT_Cb[7:0] and SD_SAT_Cr[7:0] are inactive. Table 45. SD_SAT_Cb Function SD_SAT_Cb[7:0] 0x80* 0x00 0xFF Description (Adjust Saturation of the Picture) Chroma gain = 0 dB. This register allows the user to select an offset for the Cr channel only. This register affects the SDP core only. There is a functional overlap with the Hue [7:0] register. Table 48. SD_OFF_Cr Function SD_OFF_Cr[7:0] 0x80* 0x7F 0xFF *Default value. *Default value. Rev. A | Page 24 of 104 Description (Adjust Hue of the Picture by Selecting an Offset for Data on Cr Channel) ADV7181 BRI[7:0] Brightness Adjust (SDP), Address 0x0A, [7:0] Table 51. DEF_Y Function This register controls the brightness of the video signal through the SDP core. DEF_Y[5:0] 0x36 (Blue)* *Default value. Table 49. BRI Function BRI[7:0] 0x00* 0x7F 0xFF Description Default value of Y. Description (Adjust Brightness of the Picture) Offset of the luma channel = 0IRE. Offset of the luma channel = 100IRE. Offset of the luma channel = -100IRE. DEF_C[7:0] Default Value C (SDP), Address 0x0D, [7:0] The DEF_C[7:0] register complements the DEF_Y[5:0] value. It defines the 4 MSBs of Cr and Cb values to be output if * The DEF_VAL_AUTO_EN bit is set to high and the ADV7181 can't lock to the input video (automatic mode). This register contains the value for the color hue adjustment. * DEF_VAL_EN bit is set to high (forced output). HUE[7:0] has a range of 90, with 0x00 equivalent to an adjustment of 0. The resolution of HUE[7:0] is 1 bit = 0.7. The data that is finally output from the ADV7181 for the chroma side is Cr[7:0] = {DEF_C[7:4], 0, 0, 0, 0}, Cb[7:0] = {DEF_C[3:0], 0, 0, 0, 0}. *Default value. HUE[7:0] Hue Adjust (SDP), Address 0x0B, [7:0] The hue adjustment value is fed into the AM color demodulation block. Therefore, it only applies to video signals that contain chroma information in the form of an AM modulated carrier (CVBS or Y/C in PAL or NTSC). It does not affect SECAM and does not work on component video inputs (YPrPb). Table 52. DEF_C Function DEF_C[7:0] 0x7C (blue)* Description Default values for Cr and Cb. *Default value. Table 50. HUE Function DEF_VAL_EN Default Value Enable (SDP), Address 0x0C, [0] HUE[7:0] 0x00* 0x7F 0xFF This bit forces the use of the default values for Y, Cr, and Cb. Refer to the descriptions for DEF_Y and DEF_C for additional information. The decoder also outputs a stable 27 MHz clock, HS, and VS in this mode. Description (Adjust Hue of the Picture) Phase of the chroma signal = 0. Phase of the chroma signal = -90. Phase of the chroma signal = +90. *Default value. Table 53. DEF_VAL_EN Function DEF_Y[5:0] Default Value Y (SDP), Address 0x0C, [7:2] In cases where the ADV7181 loses lock on the incoming video signal or where there is no input signal, the DEF_Y[5:0] register allows the user to specify a default luma value to be output. DEF_VAL_EN 0* 1 This value is used under the following conditions: * If DEF_VAL_AUTO_EN bit is set to high and the ADV7181 lost lock to the input video signal. This is the intended mode of operation (automatic mode). Description Don't force the use of default Y, Cr, and Cb values. Output colors dependent on DEF_VAL_AUTO_EN. Always use default Y, Cr, and Cb values. Override picture data even if the video decoder is locked. *Default value. DEF_VAL_AUTO_EN Default Value Automatic Enable (SDP), Address 0x0C, [1] * The DEF_VAL_EN bit is set, regardless of the lock status of the video decoder. * This bit enables the automatic usage of the default values for Y, Cr, and Cb in cases where the ADV7181 cannot lock to the video signal. This is a forced mode that may be useful during configuration. Table 54. DEF_VAL_AUTO_EN Function The DEF_Y[5:0] values define the 6 MSBs of the output video. The remaining LSBs are padded with 0s. For example, in 8-bit mode, the output is Y[7:0] = {DEF_Y[5:0], 0, 0}. DEF_VAL_AUTO_EN 0 1* *Default value. Rev. A | Page 25 of 104 Description Don't use default Y, Cr, and Cb values. If unlocked, output noise. Use default Y, Cr, and Cb values when decoder loses lock. ADV7181 SDP CLAMP OPERATION COARSE CURRENT SOURCES ANALOG VIDEO INPUT DATA PRE PROCESSOR (DPP) ADC SDP WITH DIGITAL FINE CLAMP 04819-0-010 FINE CURRENT SOURCES CLAMP CONTROL Figure 9. SDP Clamping Overview The input video is ac-coupled into the ADV7181. Therefore, its dc value needs to be restored. This process is referred to as clamping the video. This section explains the general process of clamping on the ADV7181 for the SDP, and shows the different ways in which a user can configure its behavior. The SDP block uses a combination of current sources and a digital processing block for clamping, as shown in Figure 9. The analog processing channel shown is replicated three times inside the IC. While only one single channel (and only one ADC) would be needed for a CVBS signal, two independent channels are needed for YC (S-VHS) type signals, and three independent channels are needed to allow component signals (YPrPb) to be processed. The clamping scheme has to complete two tasks: it must be able to acquire a newly connected video signal with a completely unknown dc level, and it must maintain the dc level during normal operation. For a fast acquiring of an unknown video signal, the large current clamps may be activated5. Control of the coarse and fine current clamp parameters is performed automatically by the decoder. * Clamping before the ADC (analog domain): current sources. Standard definition video signals may have excessive noise on them. In particular, CVBS signals transmitted by terrestrial broadcast and demodulated using a tuner usually show very large levels of noise (>100 mV). A voltage clamp would be unsuitable for this type of video signal. Instead, the ADV7181 employs a set of four current sources that can cause coarse (>0.5 mA) and fine (<0.1 mA) currents to flow into and away from the high impedance node that carries the video signal (see Figure 9). * Clamping after the ADC (digital domain): digital processing block. The following sections describe the I2C signals that can be used to influence the behavior of SDP clamping. The clamping can be divided into two sections: The ADCs can digitize an input signal only if it resides within the ADC's 1.6 V input voltage range. An input signal with a dc level that is too large or too small is clipped at the top or bottom of the ADC range. The primary task of the analog clamping circuits is to ensure that the video signal stays within the valid ADC input window so the analog-to-digital conversion can take place. It is not necessary to clamp the input signal with a very high accuracy in the analog domain as long as the video signal fits the ADC range. After digitization, the digital fine clamp block corrects for any remaining variations in dc level. Since the dc level of an input video signal refers directly to the brightness of the picture transmitted, it is important to perform a fine clamp with high accuracy; otherwise, brightness variations may occur. Furthermore, dynamic changes in the dc level will almost certainly lead to visually objectionable artifacts, and must therefore be prohibited. Previous revisions of the ADV7181 had controls (FACL/FICL, fast and fine clamp length) to allow configuration of the length for which the coarse (fast) and fine current sources are switched on. These controls were removed on the ADV7181-FT and replaced by an adaptive scheme. CCLEN Current Clamp Enable (SDP), Address 0x14, [4] The current clamp enable bit allows the user to switch off the current sources in the analog front end altogether. This may be useful if the incoming analog video signal is clamped externally. Table 55. CCLEN Function CCLEN 0 1* Description Current sources switched off. Current sources enabled. *Default value. 5 It is assumed that the amplitude of the video signal at this point is of a nominal value. Rev. A | Page 26 of 104 ADV7181 frequency noise, reducing the bandwidth of the luma signal improves visual picture quality. A follow-on video compression stage may work more efficiently if the video is low-pass filtered. DCT[1:0] Digital Clamp Timing (SDP), Address 0x15, [6:5] The Clamp Timing register determines the time constant of the digital fine clamp circuitry. It is important to realize that the digital fine clamp reacts very fast since it is supposed to immediately correct any residual dc level error for the active line. The time constant of the digital fine clamp must be much quicker than the one from the analog blocks. The ADV7181 allows selection of two responses for the shaping filter: one that is used for good quality CVBS, component, and S-VHS type sources, and a second for nonstandard CVBS signals. By default, the time constant of the digital fine clamp is adjusted dynamically to suit the currently connected input signal. The YSH filter responses also include a set of notches for PAL and NTSC. However, it is recommended to use the comb filters for YC separation. Table 56. DCT Function DCT[1:0] 00 01 10* 11 Description Slow (TC = 1 sec). Medium (TC = 0.5 sec). Fast (TC = 0.1 sec). Determined by ADV7181 dependent on video parameters. * Luma peaking filter. This filter can be manually enabled. The user can select to boost or attenuate the midregion of the Y spectrum around 3 MHz. The peaking filter may visually improve the picture by showing more definition on those picture details that contain frequency components around 3 MHz. The peaking filter compensates for the effects of a wide notch filter: Where the notch starts to fall off, the peaking filter lifts the overall response back on. * Digital resampling filter. This block is used to allow dynamic resampling of the video signal to alter parameters such as the time base of a line of video. Fundamentally, the resampler is a set of low-pass filters. The actual response is chosen by the system with no requirement for user intervention. *Default value. DCFE Digital Clamp Freeze Enable (SDP), Address 0x15, [4] This register bit allows the user to freeze the digital clamp loop at any time. It is intended for users who would like to do their own clamping. Users should disable the current sources for analog clamping via the appropriate register bits, wait until the digital clamp loop settles, and then freeze it via the DCFE bit. Table 57. DCFE Function DCFE 0* 1 Description Digital clamp operational. Digital clamp loop frozen. Figure 11 through Figure 14 show the overall response of all filters together. Unless otherwise noted, the filters are set into a typical wideband mode, and the peaking function is disabled. *Default value. SDP LUMA FILTER Data6 from the digital fine clamp block is processed by four sets of filters: * Luma antialias filter (YAA). The SDP received video at a rate of 27 MHz7. The ITU-R BT.601 recommends a sampling frequency of 13.5 MHz. The luma antialias filter decimates the oversampled video using a high quality, linear phase, low-pass filter that preserves the luma signal while at the same time attenuating out-of-band components. The luma antialias filter (YAA) has a fixed response. * Luma shaping filters (YSH). The shaping filter block is a programmable low-pass filter with a wide variety of responses. It can be used to selectively reduce the luma video signal bandwidth (needed prior to scaling, for example). For some video sources that contain high 6 7 Y Shaping Filter For input signals in CVBS format, the luma shaping filters play an essential role in removing the chroma component from a composite signal. YC separation must aim for best possible crosstalk reduction while still retaining as much bandwidth (especially on the luma component) as possible. High quality YC separation can be achieved by using the internal comb filters of the ADV7181. Comb filtering, however, relies on the frequency relationship of the luma component (multiples of the video line rate) and the color subcarrier (Fsc). For good quality CVBS signals, this relationship is known; the comb filter algorithms can be used to separate out luma and chroma with high accuracy. In the case of nonstandard video signals, the frequency relationship may be disturbed and the comb filters may not be able to remove all crosstalk artifacts in an optimum fashion without the assistance of the shaping filter block. The data format at this point is CVBS for CVBS input or luma only for Y/C and YPrPb input formats. In the case of 4x oversampled video, the ADCs sample at 54 MHz, and the first decimation is performed inside the DPP filters. Therefore, the data rate into the SDP core is always 27 MHz. Rev. A | Page 27 of 104 ADV7181 An automatic mode is provided. Here, the ADV7181 evaluates the quality of the incoming video signal and selects the filter responses in accordance with the signal quality and video standard. YFSM, WYSFMOVR, and WYSFM allow the user to manually override the automatic decisions in part or in full. YSFM[4:0] Y Shaping Filter Mode (SDP), Address 0x17, [4:0] The Y shaping filter mode bits allow the user to select from a wide range of low-pass and notch filters. When switched in automatic mode, the filter is selected based on other register selections (e.g., detected video standard) as well as properties extracted from the incoming video itself (e.g., quality, time base stability). The automatic selection always picks the widest possible bandwidth for the video input encountered. The luma shaping filter has three control registers: YSFM[4:0] allows the user to manually select a shaping filter mode (applied to all video signals) or to enable an automatic selection (dependent on video quality and video standard). * WYSFMOVR allows the user to manually override the WYSFM decision. * WYSFM[4:0] allows the user to select a different shaping filter mode for good quality CVBS, component (YPrPb), and S-VHS (YC) input signals. * If the YSFM settings specify a filter (i.e., YSFM is set to values other than 00000 or 00001), the chosen filter is applied to all video, regardless of its quality. * In automatic selection mode, the notch filters are only used for bad quality video signals. For all other video signals, wideband filters are used. WYSFMOVR Wideband Y Shaping Filter Override (SDP), Address 0x18,[7] In automatic mode, the system preserves the maximum possible bandwidth for good CVBS sources (since they can successfully be combed) as well as for luma components of YPrPb and YC sources, since they need not be combed. For poor quality signals, the system selects from a set of proprietary shaping filter responses that complements comb filter operation in order to reduce visual artifacts. Setting the WYSFMOVR bit enables the use of the WYSFM[4:0] settings for good quality video signals. For more information, refer to the general discussion of the luma shaping filters in the Y Shaping Filter section and the flowchart shown in Figure 10. Table 58. WYSFMOVR Function WYSFMOVR 0 The decisions of the control logic are shown in Figure 10. Description Automatic selection of shaping filter for good quality video signals. Enable manual override via WYSFM[4:0]. 1* *Default value. SET YSFM YES YSFM IN AUTO MODE? 00000 OR 00001 NO VIDEO QUALITY BAD GOOD AUTO SELECT LUMA SHAPING FILTER TO COMPLEMENT COMB WYSFMOVR USE YSFM SELECTED FILTER REGARDLESS FOR GOOD AND BAD VIDEO 1 0 SELECT WIDEBAND FILTER AS PER WYSFM[4:0] SELECT AUTOMATIC WIDEBAND FILTER Figure 10. YSFM and WYSFM Control Flowchart Rev. A | Page 28 of 104 04819-0-011 * ADV7181 Table 59. YSFM Function Table 60. WYSFM Function YSFM[4:0] 0'0000 WYSFM[4:0] 0'0000 0'0001 0'0010 0'0011 0'0100 0'0101 0'0110 0'0111 0'1000 0'1001 0'1010 0'1011 0'1100 0'1101 0'1110 0'1111 1'0000 1'0001 1'0010 1'0011* 1'0100-1'1111 Description Do not use Do not use SVHS 1 SVHS 2 SVHS 3 SVHS 4 SVHS 5 SVHS 6 SVHS 7 SVHS 8 SVHS 9 SVHS 10 SVHS 11 SVHS 12 SVHS 13 SVHS 14 SVHS 15 SVHS 16 SVHS 17 SVHS 18 (CCIR 601) Do not use *Default value. v740a COMBINED Y ANTIALIAS, S-VHS LOW-PASS FILTERS, Y RESAMPLE 0 -10 -20 -30 -40 -50 04819-0-012 0'0010 0'0011 0'0100 0'0101 0'0110 0'0111 0'1000 0'1001 0'1010 0'1011 0'1100 0'1101 0'1110 0'1111 1'0000 1'0001 1'0010 1'0011 1'0100 1'0101 1'0110 1'0111 1'1000 1'1001 1'1010 1'1011 1'1100 1'1101 1'1110 1'1111 AMPLITUDE (dB) 0'0001* Description Automatic selection including a wide notch response (PAL/NTSC/SECAM) Automatic selection including a narrow notch response (PAL/NTSC/SECAM) SVHS 1 SVHS 2 SVHS 3 SVHS 4 SVHS 5 SVHS 6 SVHS 7 SVHS 8 SVHS 9 SVHS 10 SVHS 11 SVHS 12 SVHS 13 SVHS 14 SVHS 15 SVHS 16 SVHS 17 SVHS 18 (CCIR 601) PAL NN 1 PAL NN 2 PAL NN 3 PAL WN 1 PAL WN 2 NTSC NN 1 NTSC NN 2 NTSC NN 3 NTSC WN 1 NTSC WN 2 NTSC WN 3 Reserved -60 *Default value. -70 0 WYSFM[4:0] Wide Band Y Shaping Filter Mode (SDP), Address 0x18, [4:0] 2 4 6 8 FREQUENCY (MHz) 10 12 Figure 11. SDP Y S-VHS Combined Responses The WYSFM[4:0] bits allow the user to manually select a shaping filter for good quality video signals (e.g., CVBS with stable time base, luma component of YPrPb, luma component of YC). The WYSFM bits are only active if the WYSFMOVR bit is set to 1. See the general discussion of the shaping filter settings in the Y Shaping Filter section. The filter plots in Figure 11 show the S-VHS 1 (narrowest) to S-VHS 18 (widest) shaping filter settings. Figure 13 shows the PAL notch filter responses. The NTSC compatible notches are shown in Figure 14. Rev. A | Page 29 of 104 ADV7181 v740a COMBINED Y ANTIALIAS, CCIR MODE SHAPING FILTER, Y RESAMPLE YPM[2:0] Y Peaking Filter Mode (SDP), Address 0x02, [2:0] 0 Allows the user to select peaking. This function allows the user to boost/attenuate luma signals around the color subcarrier frequency. Selecting YPM = 000,001,010,011 sharpens the image; YPM = 101,110,111 attenuates the luma around the color subcarrier. In cases of incomplete cancellation in the Y comb filter, this could be used to attenuate any residual C components (hanging dots) in the Y output at the cost of a softer image. AMPLITUDE (dB) -20 -40 -60 Table 61. YPM Function -80 04819-0-013 -100 -120 0 2 4 6 8 FREQUENCY (MHz) 10 12 Figure 12. SDP Y S-VHS 18 Extra Wideband Filter (CCIR 601 Compliant) v740a COMBINED Y ANTIALIAS, PAL NOTCH FILTERS, Y RESAMPLE 0 YPM[2:0] 000 001 010 011 100* 101 110 111 Filter Response (Peak Position) Composite (2.6 MHz) S-VHS (3.75 MHz) +4.5 dB +9.25 dB +4.5 dB +9.25 dB +4.5 dB +5.75 dB +1.25 dB +3.3 dB 0 0 -1.25 dB -3.0 dB -1.75 dB -8.0 dB -3.0 dB -8.0 dB *Default value. -10 AMPLITUDE (dB) SDP CHROMA FILTER -20 -30 Data8 from the digital fine clamp block is processed by two sets of filters: -40 * Chroma Antialias Filter (CAA). The ADV7181 oversamples the CVBS by a factor of 2 and the Chroma/PrPb by a factor of 4. A decimating filter (CAA) is used to preserve the active video band and remove any out-ofband components. The CAA filter has a fixed response. * Chroma Shaping Filters (CSH). The shaping filter block (CSH) can be programmed to perform a variety of lowpass responses. It can be used to selectively reduce the bandwidth of the chroma signal for scaling or compression. * Digital Resampling Filter. This block is used to allow dynamic resampling of the video signal to alter parameters such as the time base of a line of video. Fundamentally, the resampler is a set of low-pass filters. The actual response is chosen by the system with no requirement for user intervention. 04819-0-014 -50 -60 -70 0 2 4 6 8 FREQUENCY (MHz) 10 12 Figure 13. SDP Y S-VHS 18 Extra Wideband Filter (CCIR 601 Compliant) v740a COMBINED Y ANTIALIAS, NTSC NOTCH FILTERS, Y RESAMPLE 0 -20 -30 -40 The plots in Figure 15 show the overall response of all filters together. -50 04819-0-015 AMPLITUDE (dB) -10 -60 -70 0 2 4 6 8 FREQUENCY (MHz) 10 12 Figure 14. SDP Y S-VHS 18 Extra Wideband Filter (601) 8 The data format at this point is CVBS for CVBS inputs, chroma only for Y/C, or U/V interleaved for YPrPb input formats. Rev. A | Page 30 of 104 ADV7181 CSFM[2:0] C Shaping Filter Mode (SDP), Address 0x17, [7] SDP GAIN OPERATION The C shaping filter mode bits allow the user to select from a range of low-pass filters for the chrominance signal. When switched in automatic mode, the widest filter is selected based on the video standard/format and user choice (see settings 000 and 001 in Table 62). The gain control within the ADV7181 is done on a purely digital basis. The input ADCs support a 9-bit range, mapped into a 1.6 V analog voltage range. Gain correction takes place after the digitization in the form of a digital multiplier. There are several advantages of this architecture over the commonly used PGA (programmable gain amplifier) before the ADCs; among them is the fact that the gain is now completely independent of supply, temperature, and process variations. Table 62. CSFM Function CSFM[2:0] 000* 001 010 011 100 101 110 111 Description Autoselect 1.5 MHz bandwidth Autoselect 2.17 MHz bandwidth SH1 SH2 SH3 SH4 SH5 Wideband Mode As shown in Figure 16, the ADV7181 can decode a video signal as long as it fits into the ADC window. There are two components to this: the amplitude of the input signal and the dc level it resides on. The dc level is set by the clamping circuitry (see the SDP Clamp Operation section). If the amplitude of the analog video signal is too high, clipping may occur, resulting in visual artifacts. The analog input range of the ADC, together with the clamp level, determines the maximum supported amplitude of the video signal. *Default value. v740a COMBINED C ANTIALIAS, C SHAPING FILTER, C RESAMPLER 0 The minimum supported amplitude of the input video is determined by the SDP core's ability to retrieve horizontal and vertical timing and to lock to the color burst (if present). -20 There are two gain control units, one each for luma and chroma data. Both can operate independently of each other. The chroma unit, however, can also take its gain value from the luma path. -30 -40 Several AGC modes are possible; Table 63 summarizes them. 04819-0-016 -50 -60 0 1 2 3 4 FREQUENCY (MHz) 5 It is possible to freeze the automatic gain control loops. This will cause the loops to stop updating and the AGC determined gain at the time of the freeze stays active until the loop is either unfrozen or the gain mode of operation is changed. 6 Figure 15. SDP Chroma Shaping Filter Responses Figure 15 shows the responses of SH1 (narrowest) to SH5 (widest) in addition to the wideband mode (in red). The currently active gain from any of the modes can be read back. Please refer to the description of the dual function manual gain registers, LG[11:0] Luma Gain and CG[11:0] Chroma Gain, in the SDP Luma Gain and SDP Chroma Gain sections. ANALOG VOLTAGE RANGE SUPPORTED BY ADC (1.6V RANGE FOR ADV7181) MAXIMUM VOLTAGE ADC DATA PRE PROCESSOR (DPP) SDP (GAIN SELECTION ONLY) GAIN CONTROL MINIMUM VOLTAGE CLAMP LEVEL Figure 16. SDP Gain Control Overview Rev. A | Page 31 of 104 04820-0-017 ATTENUATION (dB) -10 ADV7181 Table 63. SDP AGC Modes Input Video Type Any CVBS Luma Gain Manual gain luma. Dependent on horizontal sync depth. Chroma Gain Manual gain chroma. Dependent on color burst amplitude. Taken from luma path. Dependent on color burst amplitude. Taken from luma path. Dependent on color burst amplitude. Taken from luma path. Dependent on color burst amplitude. Taken from luma path. Taken from luma path. Peak White Y/C Dependent on horizontal sync depth. Peak White. YPrPb Dependent on horizontal sync depth. SDP Luma Gain Table 65. LAGT Function LAGC[2:0] Luma Automatic Gain Control (SDP), Address 0x30, [7:0] The luma automatic gain control mode bits select the mode of operation for the gain control in the luma path. There are ADI internal parameters to customize the peak white gain control. Contact ADI for more information. Table 64. LAGC Function LAGC[2:0] 000 001 010* 011 100 101 110 111 Description Manual fixed gain (use LMG[11:0]). AGC (blank level to sync tip). No override through white peak. AGC (blank level to sync tip). Automatic override through white peak. Reserved. Reserved. Reserved. Reserved. Freeze gain. LAGT[1:0] 00 01 10 11* *Default value. LG[11:0] Luma Gain (SDP), Address 0x2F, [3:0]; Address 0x30, [7:0]; LMG[11:0] Luma Manual Gain (SDP), Address 0x2F, [3:0]; Address 0x30, [7:0] Luma gain [11:0] is a dual function register: * If written to, a desired manual luma gain can be programmed. This gain becomes active if the LAGC[2:0] mode is switched to manual fixed gain. * Equation 1 shows how to calculate a desired gain. * If read back, this register returns the current gain value. Depending on the setting in the ALCM[2:0] bits, this is one of the following values: *Default value. LAGT[1:0] Luma Automatic Gain Timing (SDP), Address 0x2F, [7:6] The luma automatic gain timing register allows the user to influence the tracking speed of the luminance automatic gain control. Please note that this register only has an effect if the LAGC[2:0] register is set to 001, 010, 011, or 100 (automatic gain control modes). If peak white AGC is enabled and active (see the STATUS_1[7:0] Address 0x10, [7:0] section), the actual gain update speed is dictated by the peak white AGC loop and, as a result, the LAGT settings have no effect. As soon as the part leaves peak white AGC, LAGT becomes relevant again. Description Slow (TC = 2 sec) Medium (TC = 1 sec) Fast (TC = 0.2 sec) Adaptive o Luma manual gain value (ALCM[2:0] set to luma manual gain mode) o Luma automatic gain value (ALCM[2:0] set to any of the automatic modes) Table 66. LG/LMG Function LG[11:0]/LMG[11:0] LMG[11:0] = X Read/Write Write LG[11:0] Read The update speed for the peak white algorithm can be customized by the use of internal parameters. Please contact ADI for more information. Rev. A | Page 32 of 104 Luma _ Gain = Description Manual gain for luma path Actually used gain (0 < LG 4095) 2048 = 0...2 Equation 1. SDP Luma Gain Formula ADV7181 Example PW_UPD Peak White Update (SDP), Address 0x2B, [0] Program the ADV7181 into manual fixed gain mode with a desired gain of 0.89 The peak white and average video algorithms determine the gain based on measurements taken from the active video. The PW_UPD bit determines the rate of gain change. Please note that the LAGC[2:0] must be set to the appropriate mode to enable the peak white or average video mode in the first place. For more information, refer to the LAGC[2:0] Luma Automatic Gain Control (SDP), Address 0x30, [7:0] section. * Use Equation 1 to convert the gain: 0.89 x 2048 = 1822.72 * Truncate to integer value: 1822.72 = 1822 * Convert to hexadecimal: 1822d = 0x71E * Split into two registers and program: Luma Gain Control 1 [3:0] = 0x7 Luma Gain Control 2 [7:0] = 0x1E * Table 68. PW_UPD Function PW_UPD 0 1 *Default value. SDP Chroma Gain Enable Manual Fixed Gain Mode: Set LAGC[2:0] to 000 CAGC[1:0] Chroma Automatic Gain Control (SDP), Address 0x2C, [1:0] BETACAM Enable Betacam Levels (SDP), Address 0x01, [5] If YPrPb data is routed through the SDP core, the automatic gain control modes can target different video input levels, as outlined in Table 71. Please note that the BETACAM bit is valid only if the input mode is YPrPb (component) and if the data is routed through the SDP core. The BETACAM bit basically sets the target value for AGC operation. A review of the following sections is useful: * * Description Update gain once per video line. Update gain once per field. SETADC_sw_man_en, Manual Input Muxing Enable, Address C4, [7] to find how component video (YPrPb) can be routed through the SDP core. Video Standard Selection (SDP) to select the various standards (e.g., with and without pedestal) The two bits of Color Automatic Gain Control mode select the basic mode of operation for automatic gain control in the chroma path. Table 69. CAGC Function CAGC[1:0] 00 01 10* 11 Description Manual fixed gain (use CMG[11:0]). Use luma gain for chroma. Automatic gain (based on color burst). Freeze chroma gain. *Default value. CAGT[1:0] Chroma Automatic Gain Timing (SDP), Address 0x2D, [7:6] The automatic gain control (AGC) algorithms adjust the levels based on the setting of the BETACAM bit(see Table 67.). The Chroma Automatic Gain Timing register allows the user to influence the tracking speed of the chroma automatic gain control. This register only has an effect if the CAGC[1:0] register is set to 10 (automatic gain). Table 67. BETACAM Function Table 70. CAGT Function BETACAM 0* CAGT[1:0] 00 01 10 11* 1 Description Assuming YPrPb is selected as input format. Selecting PAL with pedestal selects MII. Selecting PAL without pedestal selects SMPTE. Selecting NTSC with pedestal selects MII. Selecting NTSC without pedestal selects SMPTE. Assuming YPrPb is selected as input format. Selecting PAL with pedestal selects BETACAM. Selecting PAL without pedestal selects BETACAM variant. Selecting NTSC with pedestal selects BETACAM. Selecting NTSC without pedestal selects BETACAM variant. *Default value. *Default value. Rev. A | Page 33 of 104 Description Slow (TC = 2 sec) Medium (TC = 1 sec) Fast (TC = 0.2 sec) Adaptive ADV7181 Table 71. Betacam Levels Name Y Range Pb and Pr Range Sync Depth Betacam (mV) 0 to 714 (incl. 7.5% pedestal) -467 to +467 286 Betacam Variant (mV) 0 to 714 -505 to +505 286 CG[11:0] Chroma Gain (SDP), Address 0x2D, [3:0]; Address 0x2E, [7:0] CMG[11:0] Chroma Manual Gain (SDP), Address 0x2D, [3:0]; Address 0x2E, [7:0] Chroma gain [11:0] is a dual function register: SMPTE (mV) 0 to 700 -350 to +350 300 MII (mV) 0 to 700 (incl. 7.5% pedestal) -324 to +324 300 If color kill is enabled, and if the color carrier of the incoming video signal is less than the threshold for 128 consecutive video lines, color processing is switched off (black and white output). To switch the color processing back on, another 128 consecutive lines with a color burst greater than the threshold are required. * If written to, a desired manual chroma gain can be programmed. This gain becomes active if the CAGC[1:0] mode is switched to manual fixed gain. The color kill option only works for input signals with a modulated chroma part. For component input (YPrPb), there is no color kill. * Refer to Equation 2 for calculating a desired gain. Table 73. CKE Function * If read back, this register returns the current gain value. Depending on the setting in the CAGC[1:0] bits, this will be one of the following values: CKE 0 1* Description Color kill disabled. Color kill enabled. *Default value. o Chroma manual gain value (CAGC[1:0] set to chroma manual gain mode). CKILLTHR[2:0] Color Kill Threshold (SDP), Address 0x3D, [6:4] o Chroma automatic gain value (CAGC[1:0] set to any of the automatic modes). The CKILLTHR[2:0] bits allow the user to select a threshold for the color kill function. The threshold only applies to QAM based (NTSC and PAL) or FM modulated (SECAM) video standards. Table 72. CG/CMG Function CG[11:0]/CMG[11:0] CMG[11:0] Read/Write Write CG[11:0] Read Chroma _ Gain = Description Manual gain for chroma path. Currently active gain. (0 < CG 4095) 1024 Table 74. CKILLTHR Function = 0...4 CKILLTHR[2:0] 000 001 010 011 100* 101 110 111 Equation 2. SDP Chroma Gain Formula Example Freezing the automatic gain loop and reading back the CG[11:0] register results in a value of * Convert the read back value to decimal: 0x47A = 1146d * Apply Equation 2 to convert the readback value: 1146/1024 = 1.12 To enable the color kill function, the CKE bit must be set. For settings 000, 001, 010, and 011, chroma demodulation inside the ADV7181 may not work satisfactorily for poor input video signals. *Default value. CKE Color Kill Enable (SDP), Address 0x2B, [6] The Color Kill Enable bit allows the optional color kill function to be switched on or off. For QAM based video standards (PAL and NTSC) as well as FM based systems (SECAM), the threshold for the color kill decision is selectable via the CKILLTHR[2:0] bits. Rev. A | Page 34 of 104 Description SECAM NTSC, PAL No color kill Kill at < 0.5% Kill at < 5% Kill at < 1.5% Kill at < 7% Kill at < 2.5% Kill at < 8% Kill at < 4.0% Kill at < 9.5% Kill at < 8.5% Kill at < 15% Kill at < 16.0% Kill at < 32% Kill at < 32.0% Reserved for ADI internal use only. Do not select. ADV7181 SDP CHROMA TRANSIENT IMPROVEMENT (CTI) The signal bandwidth allocated for chroma is typically much smaller than that of luminance. In the past, this was a valid way to fit a color video signal into a given overall bandwidth because the human eye is less sensitive to chrominance than to luminance. The uneven bandwidth, however, may lead to some visual artifact when it comes to sharp color transitions. At the border of two bars of color, both components (luma and chroma) change at the same time (see Figure 17). Due to the higher bandwidth, the signal transition of the luma component is usually a lot sharper than that of the chroma component. The color edge is not sharp but blurred, in the worst case, over several pixels. CTI_AB_EN Chroma Transient Improvement Alpha Blend Enable (SDP), Address 0x4D, [1] The CTI_AB_EN bit enables an alpha-blend function within the CTI block. If set to 1, the alpha blender mixes the transient improved chroma with the original signal. The sharpness of the alpha blending can be configured via the CTI_AB[1:0] bits. For the alpha blender to be active, the CTI block must be enabled via the CTI_EN bit. Table 76. CTI_AB_EN CTI_AB_EN 0 1* Description Disable CTI alpha blender. Enable CTI alpha-blend mixing function. *Default value. CTI_AB[1:0] Chroma Transient Improvement Alpha Blend (SDP), Address 0x4D, [3:2] LUMA SIGNAL WITH A TRANSITION, ACCOMPANIED BY A CHROMA TRANSITION ORIGINAL, "SLOW" CHROMA TRANSITION PRIOR TO CTI DEMODULATED CHROMA SIGNAL SHARPENED CHROMA TRANSITION AT THE OUTPUT OF CTI The CTI_AB[1:0] controls the behavior of alpha blend circuitry that mixes the sharpened chroma signal with the original one. It thereby controls the visual impact of CTI on the output data. 04819-0-018 LUMA SIGNAL Figure 17. CTI Luma/Chroma Transition The chroma transient improvement block examines the input video data. It detects transitions of chroma, and can be programmed to "steepen" the chroma edges in an attempt to artificially restore lost color bandwidth. The CTI block, however, only operates on edges above a certain threshold to ensure that noise is not emphasized. Care has also been taken to ensure that edge ringing and undesirable saturation or hue distortion are avoided. Chroma transient improvements are needed primarily for signals that experienced severe chroma bandwidth limitations. For those types of signals, it is strongly recommended to enable the CTI block via CTI_EN. CTI_EN Chroma Transient Improvement Enable (SDP), Address 0x4D, [0] The CTI_EN bit enables the CTI function. If set to 0, the CTI block is inactive and the chroma transients are left untouched. Table 75. CTI_EN Function CTI_EN 0* 1 *Default value. Description Disable CTI. Enable CTI block. For CTI_AB[1:0] to become effective, the CTI block must be enabled via the CTI_EN bit, and the alpha blender must be switched on via CTI_AB_EN. Sharp blending maximizes the effect of CTI on the picture, but may also increase the visual impact of small amplitude, high frequency chroma noise. Table 77. CTI_AB Function CTI_AB[1:0] 00 01 10 11* Description Sharpest mixing between sharpened and original chroma signal. Sharp mixing. Smooth mixing. Smoothest alpha blend function. *Default value. CTI_C_TH[7:0] CTI Chroma Threshold (SDP), Address 0x4E, [7:0] The CTI_C_TH[7:0] value is an unsigned, 8-bit number specifying how big the amplitude step in a chroma transition has to be in order to be steepened by the CTI block. Programming a small value into this register causes even smaller edges to be steepened by the CTI block. Making CTI_C_TH[7:0] a large value causes the block to improve large transitions only. Table 78. CTI_C_TH Function CTI_C_TH[7:0] 0x08* *Default value. Rev. A | Page 35 of 104 Description Threshold for chroma edges prior to CTI. ADV7181 SDP DIGITAL NOISE REDUCTION (DNR) SDP COMB FILTERS Digital noise reduction is based on the assumption that high frequency signals with low amplitude are probably noise, and that their removal therefore improves picture quality. The comb filters of the ADV7181 have been greatly improved to automatically handle video of all types, standards, and levels of quality. Two user registers are available to customize comb filter operation. DNR_EN Digital Noise Reduction Enable (SDP), Address 0x4D, [5] The DNR_EN bit enables the DNR block or bypasses it. Table 79. DNR_EN Function DNR_EN 0 1* Description Bypass DNR (disable). Enable digital noise reduction on the luma data. DNR_TH[7:0] DNR Noise Threshold, Address 0x50, [7:0] The DNR_TH[7:0] value is an unsigned 8-bit number used to determine the maximum edge that will be interpreted as noise and therefore blanked from the luma data. Programming a large value into DNR_TH[7:0] causes the DNR block to interpret even large transients as noise and remove them. The effect on the video data will therefore be more visible. Programming a small value causes only small transients to be seen as noise and to be removed. It should be noted that the recommended DNR_TH[7:0] setting for A/V inputs is 0x04, and the recommended DNR_TH[7:0] setting for tuner inputs is 0x0A. Table 80. DNR_TH Function DNR_TH[7:0] 0x08* *Default value. Description Threshold for maximum luma edges to be interpreted as noise. Depending on whichever video standard has been detected (by autodetection) or selected (by manual programming), the NTSC or PAL configuration registers are used. In addition to the bits listed in this section, there are some further ADI internal controls; please contact ADI for more information. NTSC Comb Filter Settings Used for NTSC-M/J CVBS inputs. NSFSEL[1:0] Split Filter Selection NTSC (SDP), Address 0x19, [3:2] The NSFSEL[1:0] control selects how much of the overall signal bandwidth is fed to the combs. A narrow split filter selection gives better performance on diagonal lines, but leaves more dot crawl in the final output image. The opposite is true for selecting a wide bandwidth split filter. Table 81. NSFSEL Function NSFSEL[1:0] 00* 01 10 11 Description Narrow Medium Medium Wide *Default value. CTAPSN[1:0] Chroma Comb Taps NTSC (SDP), Address 0x38, [7:6] Table 82. CTAPSN Function CTAPSN[1:0] 00 01 10* 11 *Default value. Rev. A | Page 36 of 104 Description Do not use. NTSC chroma comb adapts 3 lines (3 taps) to 2 lines (2 taps). NTSC chroma comb adapts 5 lines (5 taps) to 3 lines (3 taps). NTSC chroma comb adapts 5 lines (5 taps) to 4 lines (4 taps). ADV7181 CCMN[2:0] Chroma Comb Mode NTSC (SDP), Address 0x38, [5:3] Table 83. CCMN Function CCMN[2:0] 0xx* Description Adaptive comb mode. 100 101 Disable chroma comb. Fixed chroma comb (top lines of line memory). 110 Fixed chroma comb (all lines of line memory). 111 Fixed chroma comb (bottom lines of line memory). Adaptive 3-line chroma comb for CTAPSN = 01. Adaptive 4-line chroma comb for CTAPSN = 10. Adaptive 5-line chroma comb for CTAPSN = 11. Fixed 2-line chroma comb for CTAPSN = 01. Fixed 3-line chroma comb for CTAPSN = 10. Fixed 4-line chroma comb for CTAPSN = 11. Fixed 3-line chroma comb for CTAPSN = 01. Fixed 4-line chroma comb for CTAPSN = 10. Fixed 5-line chroma comb for CTAPSN = 11. Fixed 2-line chroma comb for CTAPSN = 01. Fixed 3-line chroma comb for CTAPSN = 10. Fixed 4-line chroma comb for CTAPSN = 11. *Default value. YCMN[2:0] Luma Comb Mode NTSC (SDP), Address 0x38, [2:0] Table 84. YCMN Function YCMN[2:0] 0xx* 100 101 110 111 Description Adaptive comb mode. Disable luma comb. Fixed luma comb (top lines of line memory). Fixed luma comb (all lines of line memory). Fixed luma comb (bottom lines of line memory). *Default value. Rev. A | Page 37 of 104 Adaptive 3-line (3 taps) luma comb. Use low-pass/notch filter; see the Y Shaping Filter section. Fixed 2-line (2 taps) luma comb. Fixed 3-line (3 taps) luma comb. Fixed 2-line (2 taps) luma comb. ADV7181 PAL Comb Filter Settings Used for PAL-B/G/H/I/D, PAL-M, PAL-Combinational N, PAL60 and NTSC443 CVBS inputs. CTAPSP[1:0] Chroma Comb Taps PAL (SDP), Address 0x39, [7:6] Table 86. CTAPSP Function PSFSEL[1:0] Split Filter Selection PAL (SDP), Address 0x19, [1:0] CTAPSP[1:0] 00 01 The NSFSEL[1:0] control selects how much of the overall signal bandwidth is fed to the combs. A wide split filter selection eliminates dot crawl, but shows imperfections on diagonal lines. The opposite is true for selecting a narrow bandwidth split filter. 10 11* Table 85. PSFSEL Function PSFSEL[1:0] 00 01* 10 11 Description Narrow Medium Wide Widest Description Do not use. PAL chroma comb adapts 5 lines (3 taps) to 3 lines (2 taps); cancels cross luma only. PAL chroma comb adapts 5 lines (5 taps) to 3 lines (3 taps); cancels cross luma and hue error less well. PAL chroma comb adapts 5 lines (5 taps) to 4 lines (4 taps); cancels cross luma and hue error well. *Default value. *Default value. CCMP[2:0] Chroma Comb Mode PAL (SDP), Address 0x39, [5:3] Table 87. CCMP Function CCMP[2:0] 0xx* Description Adaptive comb mode. 100 101 Disable chroma comb. Fixed chroma comb (top lines of line memory). 110 Fixed chroma comb (all lines of line memory). 111 Fixed chroma comb (bottom lines of line memory). Adaptive 3-line chroma comb for CTAPSP = 01. Adaptive 4-line chroma comb for CTAPSP = 10. Adaptive 5-line chroma comb for CTAPSP = 11. Fixed 2-line chroma comb for CTAPSP = 01. Fixed 3-line chroma comb for CTAPSP = 10. Fixed 4-line chroma comb for CTAPSP = 11. Fixed 3-line chroma comb for CTAPSP = 01. Fixed 4-line chroma comb for CTAPSP = 10. Fixed 5-line chroma comb for CTAPSP = 11. Fixed 2-line chroma comb for CTAPSP = 01. Fixed 3-line chroma comb for CTAPSP = 10. Fixed 4-line chroma comb for CTAPSP = 11. *Default value. YCMP[2:0] Luma Comb Mode PAL (SDP), Address 0x39, [2:0] Table 88. YCMP Function YCMP[2:0] 0xx* 100 101 110 111 Description Adaptive comb mode. Disable luma comb. Fixed luma comb (top lines of line memory). Fixed luma comb (all lines of line memory). Fixed luma comb (bottom lines of line memory). Adaptive 5 lines (3 taps) luma comb. Use low-pass/notch filter; see the Y Shaping Filter section. Fixed 3 lines (2 taps) luma comb. Fixed 5 lines (3 taps) luma comb. Fixed 3 lines (2 taps) luma comb. *Default value. Rev. A | Page 38 of 104 ADV7181 SDP AV CODE INSERTION AND CONTROLS This section describes the I2C based controls that affect * Insertion of AV codes into the data stream * Data blanking during the vertical blank interval (VBI) * The range of data values permitted in the output data stream * In an 8-bit-wide output interface (Cb/Y/Cr/Y interleaved data), the AV codes are defined as FF/00/00/AV, with AV being the transmitted word that contains information about H/V/F. In this output interface mode, the following assignment takes place: Cb = FF, Y = 00, Cr = 00, and Y = AV. In a 16-bit output interface where Y and Cr/Cb are delivered via separate data buses, the AV code is over the whole 16 bits. The SD_DUP_AV bit allows the user to double up the AV codes, so the full sequence can be found on the Y bus as well as (= duplicated) the Cr/Cb bus. See Figure 18. The relative delay of luma versus chroma signals Please note that some of the decoded VBI data is being inserted during the horizontal blanking interval. See the Gemstar Data Recovery section for more information. Table 90. SD_DUP_AV Function SD_DUP_AV 0 BT656-4 ITU Standard BT-R.656-4 Enable (SDP), Address 0x04, [7] 1 The ITU has changed the position for toggling of the V bit within the SAV EAV codes for NTSC between revisions 3 and 4. The BT656-4 standard bit allows the user to select an output mode that is compliant with either the previous or the new standard. For further information, please review the standard at http://www.itu.int. *Default value. VBI_EN Vertical Blanking Interval Data Enable (SDP), Address 0x03, [7] The VBI enable bit allows data such as intercast and closed caption data to be passed through the luma channel of the SDP decoder with only a minimal amount of filtering. All data for lines 1 to 21 is passed through and available at the output port. The ADV7181 does not blank the luma data, and automatically switches all filters along the luma data path into their widest bandwidth. For active video, the filter settings for YSH and YPK are restored. Please note that the standard change affects NTSC only and has no bearing on PAL. Table 89. BT656-4 Function BT656-4 0* 1 Description AV codes in single fashion (to suit 8-bit interleaved data output). AV codes duplicated (for 16-bit interfaces). Description BT656-3 Spec: V bit goes low at EAV of lines 10 and 273. BT656-4 Spec: V bit goes low at EAV of lines 20 and 283. Refer to the BL_C_VBI Blank Chroma during VBI section for information on the chroma path. *Default value. Table 91. SD_DUP_AV SDP Duplicate AV codes (SDP), Address 0x03, [0] VBI_EN 0* 1 Depending on the output interface width, it may be necessary to duplicate the AV codes from the luma path into the chroma path. Description All video lines are filtered/scaled. Only active video region is filtered/scaled. *Default value. SD_DUP_AV = 1 SD_DUP_AV = 0 FF 00 00 16-BIT INTERFACE AV Y 00 AV 8-BIT INTERFACE Y Cb/Y/Cr/Y INTERLEAVED Cr/Cb DATA BUS FF 00 00 AV Cb FF 00 FF 00 00 AV Cb AV CODE SECTION AV CODE SECTION AV CODE SECTION Figure 18. SDP AV Code Duplication Control Rev. A | Page 39 of 104 Cb 04821-0-019 16-BIT INTERFACE Y DATA BUS ADV7181 BL_C_VBI Blank Chroma during VBI (SDP), Address 0x04, [2] Table 94. AUTO_PDC_EN Function Setting BL_C_VBI high, the Cr and Cb values of all VBI lines get blanked. This is done so any data that may come during VBI is not decoded as color and output through Cr and Cb. As a result, it should be possible to send VBI lines into the decoder, then output them through an encoder again, undistorted. Without this blanking, any wrongly decoded color gets encoded by the video encoder; therefore, the VBI lines are distorted. Description Decode and output color during VBI. Blank Cr and Cb values during VBI (no color, 0x80). *Default value. AV codes (as per ITU-R BT-656, formerly known as CCIR-656) consist of a fixed header made up of 0xFF and 0x00 values. These two values are reserved and therefore are not to be used for active video. Additionally, the ITU also specifies that the nominal range for video should be restricted to values between 16 and 235 for luma and 16 to 240 for chroma. The RANGE bit allows the user to limit the range of values output by the ADV7181 to the recommended value range. In any case, it is ensured that the reserved values of 255d (0xFF) and 00d (0x00) are not presented on the output pins unless they are part of an AV code header. Table 93. RANGE Function Description 16 Y 235 1 Y 254 LTA[1:0] Luma Timing Adjust (SDP), Address 0x27, [1:0] The Luma Timing Adjust register allows the user to specify a timing difference between chroma and luma samples. Please note the following: RANGE Range Selection (SDP), Address 0x04, [0] RANGE 0 1* 1* Description Use LTA[1:0] and CTA[2:0] values for delaying luma and chroma samples. Refer to the LTA[1:0] Luma Timing Adjust (SDP), Address 0x27, [1:0] and CTA[2:0] Chroma Timing Adjust (SDP), Address 0x27, [5:3] sections. The ADV7181 automatically determines the LTA and CTA values to have luma and chroma aligned at the output. *Default value. Table 92. BL_C_VBI Function BL_C_VBI 0 1* AUTO_PDC_EN 0 16 C/P 240 1 C/P 254 * There is a certain functionality overlap with the CTA[2:0] register. * For manual programming, use the following defaults: o CVBS input LTA[1:0] = 00. o YC input LTA[1:0] = 01. o YPrPb input LTA[1:0] =01. Table 95. LTA Function LTA[1:0] 00* 01 10 11 *Default value. *Default value. AUTO_PDC_EN Automatic Programmed Delay Control (SDP), Address 0x27, [6] Enabling the AUTO_PDC_EN function activates a function within the ADV7181 that automatically programs the LTA[1:0] and CTA[2:0] to have the chroma and luma data match delays for all modes of operation. If set, manual registers LTA[1:0] and CTA[2:0] are not used by the SDP. If the automatic mode is disabled (via setting the AUTO_PDC_EN bit to 0), the values programmed into LTA[1:0] and CTA[2:0] registers take effect. Rev. A | Page 40 of 104 Description No delay. Luma 1 clk (37 ns) delayed. Luma 2clk (74 ns) early. Luma 1 clk (37 ns) early. ADV7181 CTA[2:0] Chroma Timing Adjust (SDP), Address 0x27, [5:3] The Chroma Timing Adjust register allows the user to specify a timing difference between chroma and luma samples. This may be used to compensate for external filter group delay differences in the luma versus chroma path, and to allow for a different number of pipeline delays while processing the video downstream. Please review this functionality together with the LTA[1:0] register. Note that the chroma can only be delayed/advanced in chroma pixel steps. One chroma pixel step is equal to two luma pixels. The programmable delay occurs after demodulation, where one can no longer delay by luma pixel steps. For manual programming use the following defaults: * CVBS input CTA[2:0] = 011. * YC input CTA[2:0] = 101. * YPrPb input CTA[2:0] =110. Table 97. HSB Function HSB[10:0] 0x002 Description Not used. Chroma + 2 chroma pixel (early). Chroma + 1 chroma pixel (early). No delay. Chroma - 1 chroma pixel (late). Chroma - 2 chroma pixel (late). Chroma - 3 chroma pixel (late). Not used. *Default value. HSE[10:0] HS End, Address 0x34, [2:0], Address 0x36, [7:0] The HS Begin and HS End registers allow the user to freely position the HS output (pin) within the video line. The values in HSB[10:0] and HSE[10:0] are measured in pixel units from the falling edge of HS. Using both values, the user can program both the position and length of the HS output signal. Table 98. HSE Function HSE[9:0] 000* Example 1. To shift the HS towards active video by 20 LLC1s, add 20 LLC1s to both HSB and HSE. i.e., HSB[10:0] = [00000010110], HSE[10:0] = [00000010100] 2. To shift the HS away from active video by 20 LLC1s, add 16969 LLC1s to both HSB and HSE (for NTSC).i.e., HSB[10:0] = [11000000100], HSE[10:0] = [11000000110] SDP SYNCHRONIZATION OUTPUT SIGNALS HS Configuration The following controls allow the user to configure the behavior of the HS output pin only: Beginning of HS signal via HSB[10:0] * End of HS signal via HSE[10:0] * Polarity of HS using PHS Description HS pulse ends after HSE[10:0] pixel after falling edge of HS. *Default value. *Default value. * Description The HS pulse starts after the HSB[10:0] pixel after falling edge of HS. The position of this edge is controlled by placing a binary number into HSE[10:0]. The number applied offsets the edge with respect to an internal counter that is reset to 0 immediately after EAV code FF,00,00,XY (see Figure 19). HSE is set to 00000000000b, which is 0 LLC1 clock cycles from count[0]. Table 96. CTA Function CTA[2:0] 000 001 010 011* 100 101 110 111 The position of this edge is controlled by placing a binary number into HSB[10:0]. The number applied offsets the edge with respect to an internal counter that is reset to 0 immediately after EAV code FF,00,00,XY (see Figure 19). HSB is set to 00000000010b, which is 2 LLC1 clock cycles from count[0]. To move 20 LLC1s away from active video is equal to subtracting 20 from 1716 and adding the result in binary to both HSB[10:0] and HSE[10:0]. PHS Polarity HS (SDP), Address 0x37, [7] HSB[10:0] HS Begin, Address 0x34, [6:4], Address 0x35, [7:0] The HS Begin and HS End registers allow the user to freely position the HS output (pin) within the video line. The values in HSB[10:0] and HSE[10:0] are measured in pixel units from the falling edge of HS. Using both values, the user can program both the position and length of the HS output signal. The polarity of the HS pin as it comes from the SDP block can be inverted using the PHS bit. Table 99. PHS Function PHS 0* 1 9 Description HS active high. HS active low. 1696 is derived from the NTSC total number of Pixels = 1716 Rev. A | Page 41 of 104 ADV7181 Table 100. HS Timing Parameters (see Figure 19) HS End Adjust (HSE[10:0])1 00000000000b 00000000000b 00000000000b HS Begin Adjust (HSB[10:0])1 00000000010b 00000000010b 00000000010b Standard NTSC NTSC Square Pixel PAL Characteristic HS to Active Video (LLC1 Clock Cycles) (C in Figure 19)1 272 276 284 Active Video Samples/Line (D in Figure 19) 720Y + 720C = 1440 640Y + 640C = 1280 720Y + 720C = 1440 Total LLC1 Clock Cycles (E in Figure 19) 1716 1560 1728 1 Default. LLC1 PIXEL BUS Cr ACTIVE VIDEO Y FF 00 00 XY 80 10 80 10 EAV 80 10 FF 00 H BLANK 00 SAV XY Cb Y Cr Y Cb Y Cr ACTIVE VIDEO HS HSB[10:0] C D D E E Figure 19. HS Timing (SDP) Rev. A | Page 42 of 104 04819-0-020 HSE[10:0] 4 LLC1 ADV7181 VS and FIELD Configuration The following controls allow the user to configure the behavior of the VS and FIELD output pins, as well as the generation of embedded AV codes: HVSTIM Horizontal VS Timing (SDP), Address 0x31, [3] * ADV encoder compatible signals via NEWAVMODE The HVSTIM bit allows the user to select where the VS signal is asserted within a line of video. Some interface circuitry may require VS to go low while HS is low. * PVS, PF Table 102. HVSTIM Function * HVSTIM * VSBHO, VSBHE HVSTIM 0* 1 * VSEHO, VSEHE * For NTSC control: o NVBEGDELO, NVBEGDELE, NVBEGSIGN, NVBEG[4:0] o NVENDDELO, NVENDDELE, NVENDSIGN, NVEND[4:0] o * *Default value. VSBHO VS Begin Horizontal Position Odd (SDP), Address 0x32, [7] The VSBHO and VSBHE bits select the position within a line at which the VS pin (not the bit in the AV code) goes active. Some follow-on chips require the VS pin to only change state when HS is high/low. Table 103. VSBHO Function VSBHO 0* NFTOGDELO, NFTOGDELE, NFTOGSIGN, NFTOG[4:0] 1 For PAL control: o PVBEGDELO, PVBEGDELE, PVBEGSIGN, PVBEG[4:0] o PVENDDELO, PVENDDELE, PVENDSIGN, PVEND[4:0] o VSBHE VS Begin Horizontal Position Even (SDP), Address 0x32, [6] The VSBHO and VSBHE bits select the position within a line at which the VS pin (not the bit in the AV code) goes active. Some follow-on chips require the VS pin to only change state when HS is high/low. Table 104. VSBHE Function NEWAVMODE New AV Mode, Address 0x31, [4] Table 101. NEWAVMODE Function 1* *Default value. Description VS pin goes high at the middle of a line of video (odd field). VS pin changes state at the start of a line (odd field). *Default value. PFTOGDELO, PFTOGDELE, PFTOGSIGN, PFTOG[4:0] NEWAVMODE 0 Description Start of line relative to HSE. Start of line relative to HSB. Description EAV/SAV codes generated to suit ADI encoders. No adjustments possible. Enable Manual Position of VSYNC, Field, and AV codes using 0x34 to 0x37 and 0xE5 to 0xEA. Default register settings are CCIR656 compliant; see Figure 20 for NTSC and Figure 25 for PAL. For recommended manual user settings, see Table 109 and Figure 21 for NTSC; see Table 122 and Figure 26 for PAL. VSBHE 0* 1 Description VS pin goes high at the middle of a line of video (even field). VS pin changes state at the start of a line (even field). *Default value. VSEHO VS End Horizontal Position Odd (SDP), Address 0x33, [7] The VSEHO and VSEHE bits select the position within a line at which the VS pin (not the bit in the AV code) goes active. Some follow-on chips require the VS pin to only change state when HS is high/low. Table 105. VSEHO Function VSEHO 0* 1 *Default value. Rev. A | Page 43 of 104 Description VS pin goes low (inactive) at the middle of a line of video (odd field). VS pin changes state at the start of a line (odd field). ADV7181 VSEHE VS End Horizontal Position Even (SDP), Address 0x33, [6] PVS Polarity VS (SDP), Address 0x37, [5] The polarity of the VS pin as it comes from the SDP block can be inverted using the PVS bit. The VSEHO and VSEHE bits select the position within a line at which the VS pin (not the bit in the AV code) goes active. Some follow-on chips require the VS pin to only change state when HS is high/low. Table 107. PVS Function PVS 0* 1 Table 106. VSEHE Function VSEHE 0* Description VS pin goes low (inactive) at the middle of a line of video (even field). VS pin changes state at the start of a line (even field). 1 Description VS active high. VS active low. *Default value. PF Polarity FIELD (SDP), Address 0x37, [3] The polarity of the FIELD pin as it comes from the SDP block can be inverted using the PF bit. *Default value. Table 108. PF Function PF 0* Description FIELD active high. 1 FIELD active low. *Default value. FIELD 1 525 1 2 3 4 5 6 7 8 9 10 11 12 13 19 20 21 22 OUTPUT VIDEO H V NVBEG[4:0] = 5h *BT.656-4 REG 04h. BIT 7 = 1 NVEND[4:0] = 4h F NFTOG[4:0] = 3h FIELD 2 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 283 284 285 OUTPUT VIDEO H V NVBEG[4:0] = 5h NVEND[4:0] = 4h *BT.656-4 REG 04h. BIT 7 = 1 F 04819-0-021 NFTOG[4:0] = 3h *APPLIES IF NEMAVMODE = 0 MUST BE MANUALLY SHIFTED IF NEWAVMODE = 1. Figure 20. NTSC Default (BT.656). The polarity of H, V, and F is embedded in the data. Rev. A | Page 44 of 104 ADV7181 FIELD 1 525 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 21 22 OUTPUT VIDEO HS OUTPUT VS OUTPUT NVBEG[4:0] = 0h FIELD OUTPUT NVEND[4:0] = 3h NFTOG[4:0] = 5h FIELD 2 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 284 285 OUTPUT VIDEO HS OUTPUT VS OUTPUT NVEND[4:0] = 3h NFTOG[4:0] = 5h Figure 21. NTSC Typical VSync/Field Positions Using Register Writes in Table 109 Table 109. Recommended User Settings for NTSC (See Figure 21) Register 0x31 0x32 0x33 0x37 0xE5 0xE6 0xE7 Register Name VSync Field Control 1 VSync Field Control 2 VSync Field Control 3 Polarity NTSV_V_Bit_Beg NTSC_V_Bit_End NTSC_F_Bit_Tog Rev. A | Page 45 of 104 Write 0x12 0x81 0x84 0x29 0x0 0x3 0x85 04819-0-022 NVBEG[4:0] = 0h FIELD OUTPUT ADV7181 1 NVBEGSIGN ADVANCE BEGIN OF VSYNC BY NVBEG[4:0] NVBEGSIGN NTSC VSync Begin Sign, Address 0xE5, [5] Table 112. NVBEGSIGN Function 0 NVBEGSIGN 0 DELAY BEGIN OF VSYNC BY NVBEG[4:0] 1* NOT VALID FOR USER PROGRAMMING *Default value. ODD FIELD? YES NO NVBEGDELO NVBEGDELE 1 0 0 ADDITIONAL DELAY BY 1 LINE Description Delay start of VSync. Set for user manual programming. Advance start of VSync. Not recommended for user programming. NVBEG[4:0] NTSC VSync Begin, Address 0xE5, [4:0] Table 113. NVBEG Function NVBEG 00101* Description NTSC VSync begin position. *Default value. 1 Note: For all NTSC/PAL VSync timing controls, both the V bit in the AV code and the VSync on the VS pin are modified. ADDITIONAL DELAY BY 1 LINE 1 VSBHO 0 0 ADVANCE BY 0.5 LINE ADVANCE END OF VSYNC BY NVEND[4:0] 0 DELAY END OF VSYNC BY NVEND[4:0] 1 NOT VALID FOR USER PROGRAMMING ADVANCE BY 0.5 LINE VSYNC BEGIN ODD FIELD? 04819-0-023 1 VSBHE NVENDSIGN YES NO NVENDDELO NVENDDELE Figure 22. NTSC VSync Begin NVBEGDELO 0* 1 Description No Delay. Delay VSync going high on an odd field by a line relative to NVBEG. *Default value. NVBEGDELE 0* 1 0 ADDITIONAL DELAY BY 1 LINE VSEHO VSEHE 0 0 ADVANCE BY 0.5 LINE Description No Delay. Delay VSync going high on an even field by a line relative to NVBEG. *Default value. Rev. A | Page 46 of 104 1 ADDITIONAL DELAY BY 1 LINE 1 NVBEGDELE NTSC Vsync Begin Delay on Even Field, Address 0xE5, [6] Table 111. NVBEGDELE Function 0 1 ADVANCE BY 0.5 LINE VSYNC END Figure 23. NTSC VSync End 04819-0-024 1 NVBEGDELO NTSC VSync Begin Delay on Odd Field, Address 0xE5, [7] Table 110. NVBEGDELO Function ADV7181 NVENDDELO NTSC VSync End Delay on Odd Field, Address 0xE6, [7] Table 114. NVENDDELO Function Description No Delay. Delay VSync going low on an odd field by a line relative to NVEND. ADVANCE TOGGLE OF FIELD BY NFTOG[4:0] Description No Delay. Delay VSync going low on an even field by a line relative to NVEND *Default value. NVEND 00100* Note: For all NTSC/PAL VSync timing controls, both the V bit in the AV code and the VSync on the VS pin are modified. 1 ADDITIONAL DELAY BY 1 LINE Description Delay field transition. Set for user manual programming. Advance field transition. Not recommended for user programming. NFTOG[4:0] NTSC Field Toggle, Address 0xE7, [4:0] Table 121. NFTOG Function Description NTSC Field toggle position. *Default value. Description No delay. Delay Field toggle/transition on an odd field by a line relative to NFTOG. *Default value. NFTOGDELE NTSC Field Toggle Delay on Even Field, Address 0xE7, [6] Table 119. NFTOGDELE Function *Default value. 0 NFTOGSIGN NTSC Field Toggle Sign, Address 0xE7, [5] Table 120. NFTOGSIGN Function NFTOG 00011* NFTOGDELO NTSC Field Toggle Delay on Odd Field, Address 0xE7, [7] Table 118. NFTOGDELO Function NFTOGDELE 0 1* 0 *Default value. *Default value. NFTOGDELO 0* 1 NFTOGDELE Figure 24. NTSC FIELD Toggle 1* Description NTSC VSync end position. NFTOGDELO FIELD TOGGLE NFTOGSIGN 0 NVEND NTSC[4:0] VSync End, Address 0xE6, [4:0] Table 117. NVEND Function NO ADDITIONAL DELAY BY 1 LINE NVENDSIGN NTSC VSync End Sign, Address 0xE6, [5] Table 116. NVENDSIGN Function Description Delay start of VSync. Set for user manual programming. Advance start of VSync. Not recommended for user programming. YES 1 *Default value. 1 DELAY TOGGLE OF FIELD BY NFTOG[4:0] ODD FIELD? NVENDDELE NTSC VSync End Delay on Even Field, Address 0xE6, [6] Table 115. NVENDDELE Function NVENDSIGN 0* 0 NOT VALID FOR USER PROGRAMMING *Default value. NVENDDELE 0* 1 NFTOGSIGN 04819-0-025 NVENDDELO 0* 1 1 Description No Delay Delay Field toggle/transition on an even field by a line relative to NFTOG. Note: For all NTSC/PAL Field timing controls, both the F bit in the AV code and the Field signal on the FIELD/DE pin are modified. Table 122. Recommended User Settings for PAL (see Figure 26) Register 0x31 0x32 0x33 0x37 0xE8 0xE9 0xEA Rev. A | Page 47 of 104 Register Name VSync Field Control 1 VSync Field Control 2 VSync Field Control 3 Polarity PAL_V_Bit_Beg PAL_V_Bit_End PAL_F_Bit_Tog Write 0x12 0x81 0x84 0x29 0x1 0x4 0x6 ADV7181 FIELD 1 622 623 624 625 1 2 3 4 5 6 7 8 9 10 22 23 24 OUTPUT VIDEO H V PVBEG[4:0] = 5 PVEND[4:0] = 4 F PFTOG[4:0] = 3 FIELD 2 310 311 312 313 314 315 316 317 318 319 320 321 322 335 336 337 OUTPUT VIDEO H V PVEND[4:0] = 4 04819-0-026 PVBEG[4:0] = 5 F PFTOG[4:0] = 3 Figure 25. PAL Default (BT.656). The polarity of H, V, and F is embedded in the data. FIELD 1 622 623 624 625 1 2 3 4 5 6 7 8 9 10 11 23 24 OUTPUT VIDEO HS OUTPUT VS OUTPUT PVBEG[4:0] = 1h FIELD OUTPUT PVEND[4:0] = 4h PFTOG[4:0] = 6h FIELD 2 310 311 312 313 314 315 316 317 318 319 320 321 322 323 336 337 OUTPUT VIDEO HS OUTPUT VS OUTPUT PVEND[4:0] = 4h PFTOG[4:0] = 6h Figure 26. PAL Typical VSync/Field Positions Using Register Writes in Table 122 Rev. A | Page 48 of 104 04819-0-027 PVBEG[4:0] = 1h FIELD OUTPUT ADV7181 1 PVBEGSIGN ADVANCE BEGIN OF VSYNC BY PVBEG[4:0] PVBEGSIGN PAL VSync Begin Sign, Address 0xE8, [5] Table 125. PVBEGSIGN Function 0 PVBEGSIGN 0 DELAY BEGIN OF VSYNC BY PVBEG[4:0] Description Delay begin of VSync. Set for user manual programming. Advance begin of VSync. Not recommended for user programming. 1* NOT VALID FOR USER PROGRAMMING *Default value. ODD FIELD? YES NO PVBEGDELO PVBEGDELE 1 0 0 ADDITIONAL DELAY BY 1 LINE PVBEG[4:0] PAL VSync Begin, Address 0xE8, [4:0] Table 126. PVBEG Function PVBEG 00101* Description PAL VSync begin position. *Default value. 1 For all NTSC/PAL VSync timing controls, both the V bit in the AV code and the VSync on the VS pin are modified. ADDITIONAL DELAY BY 1 LINE 1 VSBHO 0 0 ADVANCE BY 0.5 LINE ADVANCE END OF VSYNC BY PVEND[4:0] 0 DELAY END OF VSYNC BY PVEND[4:0] 1 NOT VALID FOR USER PROGRAMMING ADVANCE BY 0.5 LINE VSYNC BEGIN ODD FIELD? 04819-0-028 1 VSBHE PVENDSIGN YES NO PVENDDELO PVENDDELE Figure 27. PAL VSync Begin PVBEGDELO 0* 1 Description No delay. Delay VSync going high on an odd field by a line relative to PVBEG. *Default value. PVBEGDELE 0 1* 0 ADDITIONAL DELAY BY 1 LINE VSEHO VSEHE 0 0 ADVANCE BY 0.5 LINE Description No delay. Delay VSync going high on an even field by a line relative to PVBEG. 1 ADDITIONAL DELAY BY 1 LINE 1 PVBEGDELE PAL VSync Begin Delay on Even Field, Address 0xE8, [6] Table 124. PVBEGDELE Function 0 1 ADVANCE BY 0.5 LINE VSYNC END 04819-0-029 1 PVBEGDELO PAL VSync Begin Delay on Odd Field, Address 0xE8, [7] Table 123. PVBEGDELO Function Figure 28. PAL VSync End *Default value. PVENDDELO PAL VSync End Delay on Odd Field, Address 0xE9,[7] Table 127. PVENDDELO Function PVENDDELO 0* 1 *Default value. Rev. A | Page 49 of 104 Description No delay. Delay VSync going low on an odd field by a line relative to PVEND. ADV7181 PVENDDELE PAL VSync End Delay on Even Field, Address 0xE9,[6] Table 128. PVENDDELE Function PVENDDELE 0* 1 PFTOG PAL Field Toggle, Address 0xEA [4:0] Table 134. PFTOG Function Description No delay. Delay VSync going low on an even field by a line relative to PVEND. *Default value. PFTOG 00011* Description PAL Field toggle position. *Default value. For all NTSC/PAL Field timing controls, the F bit in the AV code and the Field signal on the FIELD/DE pin are modified. PVENDSIGN PAL VSync End Sign, Address 0xE9, [5] Table 129. PVENDSIGN Function PVENDSIGN 0* 1 1 Description Delay end of VSync. Set for user manual programming. Advance end of VSync. Not recommended for user programming. ADVANCE TOGGLE OF FIELD BY PTOG[4:0] 0 DELAY TOGGLE OF FIELD BY PFTOG[4:0] NOT VALID FOR USER PROGRAMMING ODD FIELD? *Default value. PVEND[4:0] PAL Vsync End, Address 0xE9,[4:0] Table 130. PVEND Function PVEND 10100* PFTOGSIGN Description PAL VSync end position. YES NO PFTOGDELO PFTOGDELE 1 0 0 1 *Default value. ADDITIONAL DELAY BY 1 LINE PFTOGDELO PAL Field Toggle Delay on Odd Field, Address 0xEA, [7] Table 131. PFTOGDELO Function PFTOGDELO 0* 1 FIELD TOGGLE Description No delay. Delay F toggle/transition on an odd field by a line relative to PFTOG. *Default value. PFTOGDELE PAL Field Toggle Delay on Even Field, Address 0xEA [6] Table 132. PFTOGDELE Function PFTOGDELE 0 1* SDP SYNC PROCESSING The ADV7181 has two additional sync processing blocks that postprocess the raw synchronization information extracted from the digitized input video. If desired, the blocks can be disabled via the following two I2C bits. The HSYNC processor is designed to filter incoming HSyncs that have been corrupted by noise, providing improved performance for video signals with stable time bases but poor SNR. For CVBS PAL/NTSC, YC PAL/NTSC enable the HSync processor. For SECAM disable the HSync Processor. For YPrPb through SDP, disable HSYNC Processor. PFTOGSIGN PAL Field Toggle Sign, Address 0xEA, [5] Table 133. PFTOGSIGN Function 1* Figure 29. PAL F Toggle ENHSPLL Enable HSync Processor (SDP), Address 0x01, [6] Description No delay. Delay F toggle/transition on an even field by a line relative to PFTOG. *Default value. PFTOGSIGN 0 ADDITIONAL DELAY BY 1 LINE 04819-0-030 Note: For all NTSC/PAL VSync timing controls, both the V bit in the AV code and the VSync on the VS pin are modified. Description Delay Field transition. Set for user manual programming. Advance Field transition. Not recommended for user programming. Table 135. ENHSPLL Function ENHSPLL 0 1* *Default value. *Default value. Rev. A | Page 50 of 104 Description Disable the HSync processor. Enable the HSync processor. ADV7181 ENVSPROC Enable VSync Processor (SDP), Address 0x01, [3] WSSD Wide Screen Signaling Detected (SDP), Address 0x90, [0] This block provides extra filtering of the detected VSyncs to give improved vertical lock. Logic 1 for this bit indicates that the data in the WSS1 and WSS2 registers is valid. Table 136. ENVSPROC Function The WSSD bit goes high if the rising edge of the start bit is detected within a time window, and if the polarity of the parity bit matches the data transmitted. ENVSPROC 0 1* Description Disable VSync processor. Enable VSync processor. Table 137. WSSD Function *Default value. SDP VBI DATA DECODE The following low data rate VBI signals can be decoded by the ADV7181: WSSD 0 1 Description No WSS detected. Confidence in decoded data is low. WSS detected. Confidence in decoded data is high. CCAPD Closed Caption Detected (SDP), Address 0x90, [1] * Wide screen signaling (WSS) * Copy generation management systems (CGMS) * Closed captioning (CCAP) * EDTV The CCAPD bit goes high if the rising edge of the start bit is detected within a time window, and if the polarity of the parity bit matches the data transmitted. * Gemstar 1x and 2x compatible data recovery Table 138. CCAPD Function Logic 1 for this bit indicates that the data in the CCAP1 and CCAP2 registers is valid. The presence of any of the above signals is detected and, if applicable, a parity check is performed. The result of this testing is contained in a confidence bit in the VBI Info[7:0] register. Users are encouraged to first examine the VBI Info register before reading the corresponding data registers. All VBI data decode bits are read-only. All VBI data registers are double-buffered with the field signals. This means that data is extracted from the video lines and appears in the appropriate I2C registers with the next field transition. They are then static until the next field. The user should start an I2C read sequence with VS by first examining the VBI Info register. Then, depending on what data was detected, the appropriate data registers should be read. Note that the data registers are filled with decoded VBI data even if their corresponding detection bits are low; it is likely that bits within the decoded data stream are wrong. CCAPD 0 1 Description No CCAP signals detected. Confidence in decoded data is low. CCAP sequence detected. Confidence in decoded data is high. EDTVD EDTV Sequence Detected (SDP), Address 0x90, [2] Logic 1 for this bit indicates that the data in the EDTV1, 2, 3 registers is valid. The EDTVD bit goes high if the rising edge of the start bit is detected within a time window, and if the polarity of the parity bit matches the data transmitted. Table 139. EDTVD Function EDTVD 0 1 Description No EDTV sequence detected. Confidence in decoded data is low. EDTV sequence detected. Confidence in decoded data is high. *Default value. Notes * * The closed captioning data (CCAP) is available in the I2C registers, and is also inserted into the output video data stream during horizontal blanking. The Gemstar compatible data is not available in the I2C registers, and is inserted into the data stream only during horizontal blanking. CGMSD CGMS-A Sequence Detected (SDP), Address 0x90, [3] Logic 1 for this bit indicates that the data in the CGMS1, 2, 3 registers is valid. The CGMSD bit goes high if a valid CRC checksum has been calculated from a received CGMS packet. Table 140. CGMSD Function CGMSD 0 1 Rev. A | Page 51 of 104 Description No CGMS transmission detected, confidence low CGMS sequence decoded, confidence high ADV7181 Wide Screen Signaling Data CRC_ENABLE CRC CGMS-A Sequence (SDP), Address 0xB2, [2] WSS1[7:0] (SDP), Address 0x91, [7:0], WSS2[7:0] (SDP), Address 0x92, [7:0] For certain video sources, the CRC data bits may have an invalid format. In such circumstances, the CRC checksum validation procedure can be disabled. The CGMSD bit goes high if the rising edge of the start bit is detected within a time window. Figure 30 shows the bit correspondence between the analog video waveform and the WSS1/WSS2 registers. Note that WSS2[7:6] are undetermined and should be masked out by software. Table 141. CRC_ENABLE Function CRC_ENABLE 0 1* EDTV Data Registers Description No CRC check performed. The CGMSD bit goes high if the rising edge of the start bit is detected within a time window. Use CRC checksum to validate the CGMS-A sequence. The CGMSD bit goes high for a valid checksum. ADI recommended setting. EDTV1[7:0] (SDP), Address 0x93, [7:0], EDTV2[7:0] (SDP), Address 0x94, [7:0], EDTV3[7:0] (SDP), Address 0x95, [7:0] Figure 31 shows the bit correspondence between the analog video waveform and the EDTV1/EDTV2/EDTV3 registers. Note that EDTV3[7:6] are undetermined and should be masked out by software. EDTV3[5] is reserved for future use and, for now, will contain 0. The three LSBs of the EDTV waveform are currently not supported. *Default value. WSS1[7:0] 0 RUN-IN SEQUENCE 1 2 3 4 5 WSS2[5:0] 6 7 0 1 2 3 4 5 START CODE ACTIVE VIDEO 04819-0-031 11.0s 38.4s 42.5s Figure 30. SDP WSS Data Extraction Table 142. SDP WSS Access Information Signal Name WSS1 [7:0] WSS2 [5:0] Block SDP SDP Register Location WSS 1 [7:0] WSS 2 [5:0] 145d 146d EDTV1[7:0] 0 1 Address 91h 92h EDTV2[7:0] Register Default Value Readback Only Readback Only EDTV3[5:0] 2 NOT SUPPORTED 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 04819-0-032 3 Figure 31. SDP EDTV Data Extraction Table 143. SDP EDTV Access Information Signal Name EDTV1[7:0] EDTV2[7:0] EDTV3[7:0] Block SDP SDP SDP Register Location EDTV 1 [7:0] EDTV 2 [7:0] EDTV 3 [7:0] 147d 148d 149d Rev. A | Page 52 of 104 Address 93h 94h 95h Register Default Value Readback Only Readback Only Readback Only ADV7181 CGMS Data Registers Closed Caption Data Registers CGMS1[7:0] (SDP), Address 0x96, [7:0], CGMS2[7:0] (SDP), Address 0x97, [7:0], CGMS3[7:0] (SDP), Address 0x98, [7:0] CCAP1[7:0] (SDP), Address 0x99, [7:0], CCAP2[7:0] (SDP), Address 0x9A, [7:0] Figure 32 shows the bit correspondence between the analog video waveform and the CGMS1/CGMS2/CGMS3 registers. CGMS3[7:4] are undetermined and should be masked out by software. Figure 33 shows the bit correspondence between the analog video waveform and the CCAP1/CCAP2 registers. Notes * CCAP1[7] contains the parity bit from the first word. CCAP2[7] contains the parity bit from the second word. * Refer to the GDECAD Gemstar Decode Ancillary Data Format (SDP), Address 0x4C, [0] section. +100 IRE REF CGMS1[7:0] +70 IRE 0 1 2 3 4 5 CGMS2[7:0] 6 7 0 1 2 3 4 CGMS3[3:0] 5 6 7 0 1 2 3 0 IRE 04819-0-033 49.1s 0.5s -40 IRE 11.2s CRC SEQUENCE 2.235s 20ns Figure 32. SDP CGMS Data Extraction Table 144. SDP CGMS Access Information Block SDP SDP SDP Register Location CGMS 1 [7:0] CGMS 2 [7:0] CGMS 3 [3:0] 10.5 0.25s 150d 151d 152d Address 96h 97h 98h Register Default Value Readback Only Readback Only Readback Only 12.91s 7 CYCLES OF 0.5035MHz (CLOCK RUN-IN) CCAP2[7:0] CCAP1[7:0] S T A R T 50 IRE 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 P A R I T Y P A R I T Y BYTE 0 40 IRE BYTE 1 REFERENCE COLOR BURST (9 CYCLES) FREQUENCY = FSC = 3.579545MHz AMPLITUDE = 40 IRE 10.003s 27.382s 33.764s 04819-0-034 Signal Name CGMS1[7:0] CGMS2[7:0] CGMS3[3:0] Figure 33. SDP Closed Caption Data Extraction Table 145. SDP CCAP Access Information Signal Name CCAP1[7:0] CCAP2[7:0] Block SDP SDP Register Location CCAP 1 [7:0] CCAP 2 [7:0] 153d 154d Rev. A | Page 53 of 104 Address 99h 9Ah Register Default Value Readback Only Readback Only ADV7181 Letterbox Detection Incoming video signals may conform to different aspect ratios (16:9 wide screen of 4:3 standard). For certain transmissions in the wide screen format, a digital sequence (WSS) is transmitted with the video signal. If a WSS sequence is provided, the aspect ratio of the video can be derived from the digitally decoded bits WSS contains. In the absence of a WSS sequence, letterbox detection may be used to find wide screen signals. The detection algorithm examines the active video content of lines at the start and end of a field. If black lines are detected, this may serve as an indication that the currently shown picture is in wide screen format. The active video content (luminance magnitude) over a line of video is summed together. At the end of a line, this accumulated value is compared with a threshold, and a decision is made as to whether or not a particular line is black. The threshold value needed may depend on the type of input signal; some control is provided via LB_TH[4:0]. Detection at the Start of a Field The ADV7181 expects a section of at least six consecutive black lines of video at the top of a field. Once those lines have been detected, Register LB_LCT[7:0] reports back the number of black lines that were actually found. By default, the ADV7181 starts looking for those black lines in sync with the beginning of active video (e.g., straight after the last VBI video line). LB_SL[3:0] allows the user to set the start of letterbox detection from the beginning of a frame on a line-by-line basis. The detection window closes in the middle of the field. Detection at the End of a Field The ADV7181 expects at least six continuous lines of black video at the bottom of a field before reporting back the number of lines actually found via the LB_LCB[7:0] value. The activity window for letterbox detection (end of field) starts in the middle of an active field. Its end is programmable via LB_EL[3:0]. to come to a conclusion about the presence of letterbox type video in software. LB_LCT[7:0] Letterbox Line Count Top (SDP), Address 0x9B, [7:0]; LB_LCM[7:0] Letterbox Line Count Mid (SDP), Address 0x9C, [7:0]; LB_LCB[7:0] Letterbox Line Count Bottom (SDP), Address 0x9D, [7:0] Table 146. LB_LCx Access Information Signal Name LB_LCT[7:0] LB_LCM[7:0] LB_LCB[7:0] Block SDP SDP SDP Address 0x9B 0x9C 0x9D Register Default Value Readback only Readback only Readback only LB_TH[4:0] Letterbox Threshold Control (SDP), Address 0xDC, [4:0] Table 147. LB_TH Function LB_TH[4:0] 01100* 01101 to 10000 00000 to 01011 Description Default threshold for detection of black lines. Increase threshold (need larger active video content before identifying non-black lines). Decrease threshold (even small noise levels can cause the detection of non-black lines). *Default value. LB_SL[3:0] Letterbox Start Line (SDP), Address 0xDD, [7:4] Table 148. LB_SL Function LB_SL[3:0] 0100* 0001, 0010 Description Letterbox detection is aligned with active video. Window starts after the EDTV VBI data line. For example, 0100 = 23/286 (NTSC). For example, 0101 = 24/287 (NTSC). *Default value. LB_EL[3:0] Letterbox End Line (SDP), Address 0xDD, [3:0] Table 149. LB_EL Function LB_EL[3:0] 1101* 0001,0010 Description Letterbox detection ends with the last active line of video on a field. For example, 1101 = 262/ 525 (NTSC). For example, 1100 = 261/524 (NTSC). *Default value. Detection at the Midrange Gemstar Data Recovery Some transmissions of wide screen video include subtitles within the lower black box. If the ADV7181 finds at least two black lines followed by some more nonblack video (e.g.,. the subtitle) and finally followed by the remainder of the bottom black block, it reports back a midcount via LB_LCM[7:0]. In cases where no subtitles are found, LB_LCM[7:0] reports the same number as LB_LCB[7:0]. The Gemstar compatible data recovery block (GSCD) supports 1x and 2x data transmissions. In addition, it can also serve as a closed caption decoder. Gemstar compatible data transmissions can only occur in NTSC. Closed caption data can be decoded in both PAL and NTSC. * Notes * * The block is configured via I2C in the following way: There is a 2-field delay in the reporting of any line count parameters. There is no "letterbox detected" bit. The user is asked to read the LB_LCT[7:0] and LB_LCB[7:0] register values and * * Rev. A | Page 54 of 104 GDECEL[15:0] allow data recovery on selected video lines on even fields to be enabled and disabled. GDECOL[15:0] enable the data recovery on selected lines for odd fields. GDECAD configures the way in which data is embedded in the video data stream. ADV7181 The recovered data is not available through I2C, but is being inserted into the horizontal blanking period of an ITU-R. BT656 compatible data stream. The data format is intended to comply with the recommendation by the International Telecommunications Union, ITU-R BT.13641. See Figure 34. Entries within the packet are as follows: * Fixed preamble sequence of 0x00, 0xFF, 0xFF. * Data identification word (DID). The value for the DID marking a Gemstar or CCAP data packet is 0x140 (10-bit value). * Secondary data identification word (SDID), which contains information about the video line from which data was retrieved, whether the Gemstar transmission was of 1x or 2x format, and whether it was retrieved from an even or odd field. * Data count byte, giving the number of user data-words that follow. * User data section. * Optional padding to ensure that the length of the user data-word section of a packet is a multiple of four bytes2. * Checksum byte. The format of the data packet depends on the following criteria: * Transmission is 1x or 2x * Data is output in 8-bit or 4-bit format (see the description of the GDECAD Gemstar Decode Ancillary Data Format (SDP), Address 0x4C, [0] bit) * Data is Closed Caption (CCAP) or Gemstar compatible Data packets are output if the corresponding enable bit is set (see the GDECEL and GDECOL descriptions), and if the decoder detects the presence of data. This means that for video lines where no data has been decoded, no data packet is output even if the corresponding line enable bit is set. Each data packet starts immediately after the EAV code of the preceding line. See Figure 34 and Table 150, which show the overall structure of the data packet. Table 150 lists the values within a generic data packet that is output by the ADV7181 in 8-bit format. 3 1 For more information, see the ITU website at www.itu.ch. Requirement as set in ITU-R BT.1364. 3 In 8-bit systems, Bits D1 and D0 in the data packets are disregarded. 2 00 FF FF DID SECONDARY DATA IDENTIFICATION SDID DATA COUNT PREAMBLE FOR ANCILLARY DATA OPTIONAL PADDING BYTES USER DATA CHECK SUM 04819-0-035 DATA IDENTIFICATION USER DATA (4 OR 8 WORDS) Figure 34. Gemstar and CCAP Embedded Data Packet (Generic) Table 150. Generic Data Output Packet Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D[9] 0 1 1 0 !EP !EP !EP !EP !EP !EP !EP !EP !EP !EP !CS[8] D[8] 0 1 1 1 EP EP EP EP EP EP EP EP EP EP CS[8] D[7] 0 1 1 0 EF 0 0 0 0 0 0 0 0 0 CS[7] D[6] 0 1 1 1 2X 0 0 0 0 0 0 0 0 0 CS[6] D[5] 0 1 1 0 0 CS[5] D[4] 0 1 1 0 D[3] 0 1 1 0 line[3:0] 0 DC[1] word1[7:4] word1[3:0] word2[7:4] word2[3:0] word3[7:4] word3[3:0] word4[7:4] word4[3:0] CS[4] CS[3] Rev. A | Page 55 of 104 D[2] 0 1 1 0 DC[0] CS[2] D[1] 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 D[0] 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Description Fixed preamble Fixed preamble Fixed preamble DID SDID Data count (DC) User data-words User data-words User data-words User data-words User data-words User data-words User data-words User data-words Checksum ADV7181 Table 151. Data Byte Allocation Raw Information Bytes Retrieved from the Video Line 4 4 2 2 2x 1 1 0 0 GDECAD 0 1 0 1 User Data-Words (Including Padding) 8 4 4 4 * Notes * DID. The data identification value is 140h (10-bit value). Care has been taken that in 8-bit systems, the 2 LSBs do not carry vital information. * EP and !EP. The EP bit is set to ensure even parity on the data-word D[8:0]. Even parity means there will always be an even number of 1s within the D[8:0] bit arrangement. This includes the EP bit. !EP describes the logic inverse of EP and is output on D[9]. The !EP is output to ensure that the reserved codes of 00 and FF cannot happen. Padding Bytes 0 0 0 2 DC[1:0] 10 01 01 01 CS[8:2]. The checksum is provided to determine the integrity of the ancillary data packet. It is calculated by summing up D[8:2] of DID, SDID, the Data Count byte, and all UDWs, and ignoring any overflow during the summation. Since all data bytes that are used to calculate the checksum have their 2 LSBs set to 0, the CS[1:0] bits are also always 0. !CS[8] describes the logic inversion of CS[8]. The value !CS[8] is included in the checksum entry of the data packet to ensure that the reserved values of 0x00 and 0xFF do not occur. * EF. Even field identifier. EF = 1 indicates that the data was recovered from a video line on an even field. Table 152 to Table 155 outline the possible data packages. * 2X. This bit indicates whether the data sliced was in Gemstar 1x or 2x format. A high indicates 2x format. Gemstar 2x Format, Half-Byte Output Mode * line[3:0]. This entry provides a code that is unique for each of the possible 16 source lines of video from which Gemstar data may have been retrieved. Please refer to Table 163 and Table 164. * DC[1:0]. Data count value. The number of User Data Words in the packet divided by 4. The number of user data words (UDW) in any packet must be an integral number of 4. Padding is required at the end, if necessary10. Refer to Table 151. * The 2X bit determines whether the raw information retrieved from the video line was 2 or 4 bytes. The state of the GDECAD bit affects whether the bytes are transmitted straight (i.e., two bytes transmitted as two bytes) or whether they are split into nibbles (i.e., two bytes transmitted as four half bytes). Padding bytes are then added where necessary. 10 Half-byte output mode is selected by setting CDECAD = 0; fullbyte output mode is selected by setting CDECAD = 1. See the GDECAD Gemstar Decode Ancillary Data Format (SDP), Address 0x4C, [0] section. Gemstar 1x Format Half-byte output mode is selected by setting CDECAD = 0, fullbyte output mode is selected by setting CDECAD = 1. See the GDECAD Gemstar Decode Ancillary Data Format (SDP), Address 0x4C, [0] section. Requirement as set in ITU-R BT.1364. Rev. A | Page 56 of 104 ADV7181 Table 152. Gemstar 2x Data, Half-Byte Mode Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D[9] 0 1 1 0 !EP !EP !EP !EP !EP !EP !EP !EP !EP !EP !CS[8] D[8] 0 1 1 1 EP EP EP EP EP EP EP EP EP EP CS[8] D[7] 0 1 1 0 EF 0 0 0 0 0 0 0 0 0 CS[7] D[6] 0 1 1 1 1 0 0 0 0 0 0 0 0 0 CS[6] D[5] 0 1 1 0 0 CS[5] D[4] 0 1 1 0 D[3] 0 1 1 0 line[3:0] 0 1 Gemstar word1[7:4] Gemstar word1[3:0] Gemstar word2[7:4] Gemstar word2[3:0] Gemstar word3[7:4] Gemstar word3[3:0] Gemstar word4[7:4] Gemstar word4[3:0] CS[4] CS[3] D[2] 0 1 1 0 0 CS[2] D[1] 0 1 1 0 0 0 0 0 0 0 0 0 0 0 CS[1] D[0] 0 1 1 0 0 0 0 0 0 0 0 0 0 0 CS[0] Description Fixed preamble Fixed preamble Fixed preamble DID SDID Data count User data-words User data-words User data-words User data-words User data-words User data-words User data-words User data-words Checksum Table 153. Gemstar 2x Data, Full-Byte Mode Byte 0 1 2 3 4 5 6 7 8 9 10 D[9] 0 1 1 0 !EP !EP D[8] 0 1 1 1 EP EP D[7] 0 1 1 0 EF 0 !CS[8] CS[8] CS[7] D[6] D[5] 0 0 1 1 1 1 1 0 1 0 0 Gemstar word1[7:0] Gemstar word2[7:0] Gemstar word3[7:0] Gemstar word4[7:0] CS[6] CS[5] D[4] D[3] 0 0 1 1 1 1 0 0 line[3:0] 0 0 D[2] 0 1 1 0 CS[4] CS[2] CS[3] 1 D[1] 0 1 1 0 0 0 0 0 0 0 CS[1] D[0] 0 1 1 0 0 0 0 0 0 0 CS[0] Description Fixed preamble Fixed preamble Fixed preamble DID SDID Data count User data-words User data-words User data-words User data-words Checksum Table 154. Gemstar 1x Data, Half-Byte Mode Byte 0 1 2 3 4 5 6 7 8 9 10 D[9] 0 1 1 0 !EP !EP !EP !EP !EP !EP !CS[8] D[8] 0 1 1 1 EP EP EP EP EP EP CS[8] D[7] 0 1 1 0 EF 0 0 0 0 0 CS[7] D[6] 0 1 1 1 0 0 0 0 0 0 CS[6] D[5] 0 1 1 0 0 CS[5] D[4] 0 1 1 0 D[3] 0 1 1 0 line[3:0] 0 0 Gemstar word1[7:4] Gemstar word1[3:0] Gemstar word2[7:4] Gemstar word2[3:0] CS[4] CS[3] Rev. A | Page 57 of 104 D[2] 0 1 1 0 1 CS[2] D[1] 0 1 1 0 0 0 0 0 0 0 CS[1] D[0] 0 1 1 0 0 0 0 0 0 0 CS[0] Description Fixed preamble Fixed preamble Fixed preamble DID SDID Data count User data-words User data-words User data-words User data-words Checksum ADV7181 Table 155. Gemstar 1x Data, Full-Byte Mode Byte 0 1 2 3 4 5 6 7 8 9 10 D[9] 0 1 1 0 !EP !EP D[8] 0 1 1 1 EP EP D[7] 0 1 1 0 EF 0 1 1 !CS[8] 0 0 CS[8] 0 0 CS[7] D[6] D[5] 0 0 1 1 1 1 1 0 0 0 0 Gemstar word1[7:0] Gemstar word2[7:0] 0 0 0 0 CS[6] CS[5] D[4] 0 1 1 0 0 D[3] 0 1 1 0 line[3:0] 0 0 0 CS[4] D[2] 0 1 1 0 1 0 0 CS[3] 0 0 CS[2] D[1] 0 1 1 0 0 0 0 0 0 0 CS[1] D[0] 0 1 1 0 0 0 0 0 0 0 CS[0] Description Fixed preamble Fixed preamble Fixed preamble DID SDID Data count User data-words User data-words UDW padding 200h UDW padding 200h Checksum Table 156. NTSC CCAP Data, Half-Byte Mode Byte 0 1 2 3 4 5 6 7 8 9 10 D[9] 0 1 1 0 !EP !EP !EP !EP !EP !EP !CS[8] D[8] 0 1 1 1 EP EP EP EP EP EP CS[8] D[7] 0 1 1 0 EF 0 0 0 0 0 CS[7] D[6] 0 1 1 1 0 0 0 0 0 0 CS[6] D[5] 0 1 1 0 1 0 CS[5] D[4] D[3] 0 0 1 1 1 1 0 0 0 1 0 0 CCAP word1[7:4] CCAP word1[3:0] CCAP word2[7:4] CCAP word2[3:0] CS[4] CS[3] D[2] 0 1 1 0 1 1 CS[2] D[1] 0 1 1 0 0 0 0 0 0 0 CS[1] D[0] 0 1 1 0 0 0 0 0 0 0 CS[0] Description Fixed preamble Fixed preamble Fixed preamble DID SDID Data count User data-words User data-words User data-words User data-words Checksum Table 157. NTSC CCAP Data, Full-Byte Mode Byte 0 1 2 3 4 5 6 7 8 9 10 D[9] 0 1 1 0 !EP !EP D[8] 0 1 1 1 EP EP D[7] 0 1 1 0 EF 0 1 1 !CS[8] 0 0 CS[8] 0 0 CS[7] D[6] D[5] 0 0 1 1 1 1 1 0 0 1 0 0 CCAP word1[7:0] CCAP word2[7:0] 0 0 0 0 CS[6] CS[5] D[4] 0 1 1 0 0 0 D[3] 0 1 1 0 1 0 D[2] 0 1 1 0 1 1 0 0 CS[4] 0 0 CS[3] 0 0 CS[2] D[1] 0 1 1 0 0 0 0 0 0 0 CS[1] D[0] 0 1 1 0 0 0 0 0 0 0 CS[0] Description Fixed preamble Fixed preamble Fixed preamble DID SDID Data count User data-words User data-words UDW padding 200h UDW padding 200h Checksum Notes NTSC CCAP Data Half-byte output mode is selected by setting CDECAD = 0, the full-byte mode is enabled by CDECAD = 1. Refer to the GDECAD Gemstar Decode Ancillary Data Format (SDP), Address 0x4C, [0] section. The data packet formats are shown in Table 156 and Table 157. * Only closed caption data from the SDP core can be embedded in the output data stream. * NTSC closed caption data is sliced on line 21d on even and odd fields. The corresponding enable bit has to be set high. See the GDECEL[15:0] Gemstar Decoding Even Lines (SDP), Address 0x48, [7:0]; Address 0x49, [7:0] and GDECOL[15:0] Gemstar Decoding Odd Lines (SDP), Address 0x4A, [7:0]; Address 0x4B, [7:0] sections. Rev. A | Page 58 of 104 ADV7181 PAL CCAP Data Notes Half-Byte output mode is selected by setting CDECAD = 0, fullbyte output mode is selected by setting CDECAD = 1. See the GDECAD Gemstar Decode Ancillary Data Format (SDP), Address 0x4C, [0] section. Table 158 and Table 159 list the bytes of the data packet. * Only closed caption data from the SDP core can be embedded in the output data stream. PAL closed caption data is sliced from lines 22 and 335. The corresponding enable bits have to be set. * See the GDECEL[15:0] Gemstar Decoding Even Lines (SDP), Address 0x48, [7:0]; Address 0x49, [7:0] and GDECOL[15:0] Gemstar Decoding Odd Lines (SDP), Address 0x4A, [7:0]; Address 0x4B, [7:0] sections. Table 158. PAL CCAP Data, Half-Byte Mode Byte 0 1 2 3 4 5 6 7 8 9 10 D[9] 0 1 1 0 !EP !EP !EP !EP !EP !EP !CS[8] D[8] 0 1 1 1 EP EP EP EP EP EP CS[8] D[7] 0 1 1 0 EF 0 0 0 0 0 CS[7] D[6] 0 1 1 1 0 0 0 0 0 0 CS[6] D[5] 0 1 1 0 1 0 CS[5] D[4] D[3] 0 0 1 1 1 1 0 0 0 1 0 0 CCAP word1[7:4] CCAP word1[3:0] CCAP word2[7:4] CCAP word2[3:0] CS[4] CS[3] D[2] 0 1 1 0 0 1 CS[2] D[1] 0 1 1 0 0 0 0 0 0 0 CS[1] D[0] 0 1 1 0 0 0 0 0 0 0 CS[0] Description Fixed preamble Fixed preamble Fixed preamble DID SDID Data count User data-words User data-words User data-words User data-words Checksum Table 159. PAL CCAP Data, Full-Byte Mode Byte 0 1 2 3 4 5 6 7 8 9 10 D[9] 0 1 1 0 !EP !EP D[8] 0 1 1 1 EP EP D[7] 0 1 1 0 EF 0 1 1 !CS[8] 0 0 CS[8] 0 0 CS[7] D[6] D[5] 0 0 1 1 1 1 1 0 0 1 0 0 CCAP word1[7:0] CCAP word2[7:0] 0 0 0 0 CS[6] CS[5] D[4] 0 1 1 0 0 0 D[3] 0 1 1 0 1 0 D[2] 0 1 1 0 0 1 0 0 CS[4] 0 0 CS[3] 0 0 CS[2] Rev. A | Page 59 of 104 D[1] 0 1 1 0 0 0 0 0 0 0 CS[1] D[0] 0 1 1 0 0 0 0 0 0 0 CS[0] Description Fixed preamble Fixed preamble Fixed preamble DID SDID Data Count User data-words User data-words UDW padding 200h UDW padding 200h Checksum ADV7181 GDECEL[15:0] Gemstar Decoding Even Lines (SDP), Address 0x48, [7:0]; Address 0x49, [7:0] GDECAD Gemstar Decode Ancillary Data Format (SDP), Address 0x4C, [0] The 16 bits of the GDECEL[15:0] are interpreted as a collection of 16 individual line decode enable signals. Each bit refers to a line of video in an even field. Setting the bit enables the decoder block trying to find Gemstar or closed caption compatible data on that particular line. Setting the bit to 0 prevents the decoder from trying to retrieve data. See Table 163 and Table 164. The decoded data from Gemstar compatible transmissions or closed caption is inserted into the horizontal blanking period of the respective line of video. There is a potential problem if the retrieved data bytes have the value 0x00 or 0xFF. In an ITU-R BT.656 compatible data stream, those values are reserved and used only to form a fixed preamble. Notes The GDECAD bit allows the data to be inserted into the horizontal blanking period in two ways: * * To retrieve closed caption data services on NTSC (line 284), GDECEL[11] must be set. * Insert all data straight into the data stream, even the reserved values of 0x00 and 0xFF, if they occur. This may violate the output data format specification ITU-R BT.1364. * Split all data into nibbles and insert the half-bytes over double the number of cycles in a 4-bit format. To retrieve closed caption data services on PAL (line 335), GDECEL[14] must be set. Table 160. GDECEL Function GDECEL[15:0] 0x0000* Description Do not attempt to decode Gemstar compatible data or CCAP on any line (even field). *Default value. Table 162. GDECAD Function GDECAD 0* 1 GDECOL[15:0] Gemstar Decoding Odd Lines (SDP), Address 0x4A, [7:0]; Address 0x4B, [7:0] *Default value. The 16 bits of the GDECOL[15:0] form a collection of 16 individual line decode enable signals. See Table 163 and Table 164. Notes * To retrieve closed caption data services on NTSC (line 21), GDECOL[11] must be set. * To retrieve closed caption data services on PAL (line 22), GDECOL[14] must be set. Table 161. GDECOL Function GDECOL[15:0] 0x0000* Description Do not attempt to decode Gemstar compatible data or CCAP on any line (odd field). *Default value. Rev. A | Page 60 of 104 Description Split data into half-bytes and insert. Output data straight in 8-bit format. ADV7181 Table 163. NTSC Line Enable Bits and Corresponding Line Numbering line[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 Line Number (ITU-R BT.470) 10 11 12 13 14 15 16 17 18 19 20 21 Enable Bit GDECOL[0] GDECOL[1] GDECOL[2] GDECOL[3] GDECOL[4] GDECOL[5] GDECOL[6] GDECOL[7] GDECOL[8] GDECOL[9] GDECOL[10] GDECOL[11] 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 22 23 24 25 273 (10) 274 (11) 275 (12) 276 (13) 277 (14) 278 (15) 279 (16) 280 (17) 281 (18) 282 (19) 283 (20) 284 (21) GDECOL[12] GDECOL[13] GDECOL[14] GDECOL[15] GDECEL[0] GDECEL[1] GDECEL[2] GDECEL[3] GDECEL[4] GDECEL[5] GDECEL[6] GDECEL[7] GDECEL[8] GDECEL[9] GDECEL[10] GDECEL[11] 12 13 14 15 285 (22) 286 (23) 287 (24) 288 (25) GDECEL[12] GDECEL[13] GDECEL[14] GDECEL[15] Comment Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar or closed caption Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar or closed caption Gemstar Gemstar Gemstar Gemstar Table 164. PAL Line Enable Bits and Corresponding Line Numbering line[3:0] 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 Rev. A | Page 61 of 104 Line Number (ITU-R BT.470) 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 321 (8) 322 (9) 323 (10) 324 (11) 325 (12) 326 (13) 327 (14) 328 (15) 329 (16) 330 (17) 331 (18) 332 (19) 333 (20) 334 (21) 335 (22) 336 (23) Enable Bit GDECOL[0] GDECOL[1] GDECOL[2] GDECOL[3] GDECOL[4] GDECOL[5] GDECOL[6] GDECOL[7] GDECOL[8] GDECOL[9] GDECOL[10] GDECOL[11] GDECOL[12] GDECOL[13] GDECOL[14] GDECOL[15] GDECEL[0] GDECEL[1] GDECEL[2] GDECEL[3] GDECEL[4] GDECEL[5] GDECEL[6] GDECEL[7] GDECEL[8] GDECEL[9] GDECEL[10] GDECEL[11] GDECEL[12] GDECEL[13] GDECEL[14] GDECEL[15] Comment Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Closed caption Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Closed caption Not valid ADV7181 PIXEL PORT CONFIGURATION The ADV7181 has a very flexible pixel port that can be configured in a variety of formats to accommodate downstream ICs. Table 167 and Table 168 summarize the various functions that the ADV7181's pins can have in different modes of operation. The ordering of components (e.g., Cr versus Cb, CHA/B/C) can be changed. Refer to the SWPC Swap Pixel Cr/Cb (SDP), Address 0x27, [7] section. Table 167 indicates the default positions for the Cr/Cb components. OF_SEL[3:0] Output Format Selection, Address 0x03, [5:2] There are several modes in which the ADV7181 pixel port can be configured. These modes are under the control of OF_SEL[3:0]. See Table 168 for details. The default LLC frequency output on the LLC1 pin is approximately 27 MHz. For modes that operate with a nominal data rate of 13.5 MHz (0001, 0010), the clock frequency on the LLC1 pin stays at the higher rate of 27 MHz. For information on outputting the nominal 13.5 MHz clock on the LLC1 pin, see the LLC1 Output Selection, LLC_PAD_SEL[2:0] (SDP), Address 0x8F, [6:4] section. SWPC Swap Pixel Cr/Cb (SDP), Address 0x27, [7] This bit allows Cr and Cb samples of the SDP block to be swapped. Table 165. SWPC Function SWPC 0* 1 Description No swapping. Swap Cr and Cb values. *Default value. LLC1 Output Selection, LLC_PAD_SEL[2:0] (SDP), Address 0x8F, [6:4] The following I2C write allows the user to select between the LLC1 (nominally at 27 MHz) and LLC2 (nominally at 13.5 MHz). The LLC2 signal is useful for LLC2 compatible wide bus (16-bit) output modes. See the OF_SEL[3:0] Output Format Selection, Address 0x03, [5:2] section for additional information. The LLC2 signal and data on the data bus are synchronized. By default, the rising edge of LLC1/LLC2 is aligned with the Y data; the falling edge occurs when the data bus holds C data. The polarity of the clock, and therefore the Y/C assignments to the clock edges, can be altered by using the Polarity LLC pin. Table 166. LLC_PAD_SEL Function LLC_PAD_SEL[2:0] 000* 101 Description Output nominal 27 MHz LLC on LLC1 pin Output nominal 13.5 MHz LLC on LLC1 pin *Default value. Table 167. P15-P0 Output/Input Pin Mapping SDP SDP Processor, Format, and Mode Video Out, 8-Bit, 4:2:2 Video Out, 16-Bit, 4:2:2 15 14 13 12 11 YCrCb[7:0]OUT Y[7:0]OUT Data Port Pins P[15:0] 10 9 8 7 6 5 4 3 CrCb[7:0] OUT Table 168. Standard Definition Pixel Port Modes OF_SEL[3:0] 0010 0011* 0110-1111 Format 16-Bit @LLC2 4:2:2 8-Bit @LLC1 4:2:2 Reserved P[15:8] Y[7:0] YCrCb[7:0] *Default value. Rev. A | Page 62 of 104 2 P[15: 0] P[7: 0] CrCb[7:0] Three-State Reserved. Do not use. 1 0 ADV7181 MPU PORT DESCRIPTION The ADV7181 supports a 2-wire (I2C compatible) serial interface. Four inputs, serial data (SDA1 and SDA2) and serial clock (SCLK1 and SCLK2), carry information between the ADV7181 and the system I2C master controller. Each slave device is recognized by a unique address. The ADV7181 has two ports: the control port, which allows the user to set up and configure the decoder; and the VBI data readback port, which allows the user to read back captured VBI data. Both the control and VBI ports have four possible slave addresses for both read and write operations, depending on the logic level on the ALSB pin. These four unique addresses are shown in Table 169. The ADV7181's ALSB pin controls Bit 1 of the slave address. By altering the ALSB, it is possible to control two ADV7181s in an application without having a conflict with the same slave address. The LSB (Bit 0) sets either a read or write operation. Logic 1 corresponds to a read operation; Logic 0 corresponds to a write operation. condition and the correct transmitted address. The R/W bit determines the direction of the data. Logic 0 on the LSB of the first byte means the master will write information to the peripheral. Logic 1 on the LSB of the first byte means the master will read information from the peripheral. Table 169. I2C Address for ADV7181 Stop and Start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. During a given SCLK high period, the user should only issue one Start condition, one Stop condition, or a single Stop condition followed by a single Start condition. If an invalid subaddress is issued by the user, the ADV7181 will not issue an acknowledge and will return to the idle condition. R/W 0 1 0 1 Slave Address Control Port 0x40 0x41 0x42 0x43 Slave Address VBI Port 0x20 0x21 0x22 0x23 To control the device on the bus, a specific protocol must be followed. First, the master initiates a data transfer by establishing a Start condition, which is defined by a high-to-low transition on SDA1/SDA2 while SCLK1/SCLK2 remains high. This indicates that an address/data stream will follow. All peripherals respond to the Start condition and shift the next eight bits (7-bit address + R/W bit). The bits are transferred from MSB down to LSB. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse; this is known as an acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. The idle condition is where the device monitors the SDA1/SDA2 and SCLK1/SCLK2 lines, waiting for the Start If in auto-increment mode the user exceeds the highest subaddress, the following action is taken: 1. In read mode, the highest subaddress register contents continue to be output until the master device issues a noacknowledge. This indicates the end of a read. A noacknowledge condition is when the SDA line is not pulled low on the ninth pulse. 2. In write mode, the data for the invalid byte is not loaded into any subaddress register, a no acknowledge is issued by the ADV7181, and the part returns to the idle condition. SDATA SCLOCK S 1-7 8 9 1-7 8 9 START ADDR R/W ACK SUBADDRESS ACK 1-7 DATA 8 9 P ACK STOP 04819-0-036 Figure 35. Bus Data Transfer WRITE SEQUENCE S SLAVE ADDR A(S) SUB ADDR A(S) DATA LSB = 0 READ SEQUENCE S SLAVE ADDR A(S) S = START BIT P = STOP BIT A(S) DATA A(S) P LSB = 1 SUB ADDR A(S) S SLAVE ADDR A(S) A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER DATA A(M) A(S) = NO-ACKNOWLEDGE BY SLAVE A(M) = NO-ACKNOWLEDGE BY MASTER Figure 36: Read and Write Sequence Rev. A | Page 63 of 104 DATA A(M) P 04819-0-037 ALSB 0 0 1 1 The ADV7181 acts as a standard slave device on the bus. The data on the SDA pin is eight bits long, supporting the 7-bit addresses plus the R/W bit. The ADV7181 has 196 subaddresses to enable access to the internal registers. It therefore interprets the first byte as the device address and the second byte as the starting subaddress. The subaddresses autoincrement, allowing data to be written to or read from the starting subaddress. A data transfer is always terminated by a Stop condition. The user can also access any unique subaddress register on a one-by-one basis without updating all the registers. ADV7181 REGISTER ACCESSES I2C SEQUENCER The MPU can write to or read from all of the ADV7181's registers, except the Subaddress register, which is write-only. The Subaddress register determines which register the next read or write operation accesses. All communications with the part through the bus start with an access to the Subaddress register. Then, a read/write operation is performed from/to the target address, which then increments to the next address until a Stop command on the bus is performed. An I2C sequencer is employed in cases where a parameter exceeds eight bits, and is therefore distributed over two or more I2C registers (e.g., HSB [11:0]). REGISTER PROGRAMMING When such a parameter is changed using two or more I2C write operations, the parameter may hold an invalid value for the time between the first I2C finishing and the last I2C being completed. In other words, the top bits of the parameter may already hold the new value while the remaining bits of the parameter still hold the previous value. The following sections describe each register in terms of its configuration. The Communications register is an 8-bit, writeonly register. After the part has been accessed over the bus and a read/write operation is selected, the subaddress is set up. The Subaddress register determines to/from which register the operation takes place. Table 171 lists the various operations under the control of the Subaddress register for the control port. To avoid this problem, the I2C sequencer holds the already updated bits of the parameter in local memory; all bits of the parameter are updated together once the last register write operation has completed. Table 172 lists the various read back registers under the control of the Subaddress register for the VBI port. * All I2C registers for the parameter in question must be written to in order of ascending addresses. (e.g., for HSB[10:0], write to Address 0x34 first, followed by 0x35). * No other I2C taking place between the two (or more) I2C writes for the sequence (e.g., for HSB[10:0], write to Address 0x34 first, immediately followed by 0x35). The correct operation of the I2C sequencer relies on the following: Register Select (SR7-SR0) These bits are set up to point to the required starting address. Rev. A | Page 64 of 104 ADV7181 I2C CONTROL REGISTER MAP Table 170. Control Port Register Map Details Register Name Input Control Video Selection Video Selection 2 Output Control Extended Output Control Reserved Reserved Autodetect Enable Contrast Reserved Brightness Hue Default Value Y Default Value C ADI Control Power Management Status 1 Ident Status 2 Status 3 Analog Clamp Control Digital Clamp Control 1 Reserved Shaping Filter Control Shaping Filter Control 2 Comb Filter Control Reserved Pixel Delay Control Reserved Misc Gain Control AGC Mode Control Chroma Gain Control 1 Chroma Gain Control 2 Luma Gain Control 1 Luma Gain Control 2 VSync Field Control 1 VSync Field Control 2 VSync Field Control 3 HSync Position Control 1 HSync Position Control 2 HSync Position Control 3 Polarity NTSC Comb Control PAL Comb Control ADC Control Reserved Manual Window Control Reserved Gemstar Ctrl 1 Gemstar Ctrl 2 Reset Value 0000 0000 1100 1000 0000 0100 0000 1100 0101 0101 0000 0000 0000 0010 0111 1111 1000 0000 1000 0000 0000 0000 0000 0000 0011 0110 0111 1100 0000 0101 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0001 0010 0100 xxxx xxxx xxxx 0000 0001 1001 0011 1111 0001 xxxx xxxx 0101 1000 xxxx xxxx 1110 0011 1010 1110 1111 0100 0000 0000 1111 xxxx xxxx xxxx 0001 0010 0100 0001 1000 0100 0000 0000 0000 0010 0000 0000 0000 0001 1000 0000 1100 0000 0001 0000 xxxx xxxx 0100 0011 0101 0000 00000000 0000 0000 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw r r r r rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Subaddress Hex 0 00 1 01 2 02 3 03 4 04 5 05 6 06 7 07 8 08 9 09 10 0A 11 0B 12 0C 13 0D 14 0E 15 0F 16 10 17 11 18 12 19 13 20 14 21 15 22 16 23 17 24 18 25 19 26-38 1A-26 39 27 40 28-2A 43 2B 44 2C 45 2D 46 2E 47 2F 48 30 49 31 50 32 51 33 52 34 53 35 54 36 55 37 56 38 57 39 58 3A 59-60 3B-3C 61 3D 62-70 3E-47 72 48 73 49 Register Name Reset Value rw Gemstar Ctrl 3 Gemstar Ctrl 4 GemStar Ctrl 5 CTI DNR Ctrl 1 CTI DNR Ctrl 2 Reserved CTI DNR Ctrl 4 Lock Count Reserved Free Run Line Length 1 Free Run Line Length 2 VBI Info WSS 1 WSS 2 EDTV 1 EDTV 2 EDTV 3 CGMS 1 CGMS 2 CGMS 3 CCAP 1 CCAP 2 Letterbox 1 Letterbox 2 Letterbox 3 Reserved CRC Enable Reserved ADC Switch 1 ADC Switch 2 Reserved Letterbox Control 1 Letterbox Control 2 Reserved Reserved Reserved SD Offset Cb SD Offset Cr SD Saturation Cb SD Saturation Cr NTSC V Bit Begin NTSC V Bit End NTSC F Bit Toggle PAL V Bit Begin PAL V Bit End PAL F Bit Toggle 0000 0000 0000 0000 xxxx xxx0 1110 1111 0000 1000 xxxx xxxx 0000 1000 1010 0100 xxxx xxxx 0000 0000 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0001 1100 xxxx xxxx xxxx xxxx 0xxx xxxx xxxx xxxx 1010 1100 0100 1100 0000 0000 0000 0000 0001 0100 1000 0000 1000 0000 1000 0000 1000 0000 0010 0101 0000 0100 0110 0011 0110 0101 0001 0100 0110 0011 rw rw rw rw rw rw rw rw rw w w r r r r r r r r r r r r r r rw w rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Rev. A | Page 65 of 104 Subaddress Hex 74 4A 75 4B 76 4C 77 4D 78 4E 79 4F 80 50 81 51 82-142 52-8E 143 8F 144 90 144 90 145 91 146 92 147 93 148 94 149 95 150 96 151 97 152 98 153 99 154 9A 155 9B 156 9C 157 9D 158-177 9E-B1 178 B2 179-194 B2-C2 195 C3 196 C4 197-219 C5-DB 220 DC 221 DD 222 DE 223 DF 224 E0 225 E1 226 E2 227 E3 228 E4 225 E5 226 E6 227 E7 225 E8 226 E9 227 EA ADV7181 Table 171. Control Port Register Map Bit Details Register Name Input Control Video Selection Video Selection 2 Output Control Extended Output Control Reserved Reserved Autodetect Enable Contrast Reserved Brightness Hue Default Value Y Default Value C ADI Control Power Management Status 1 Ident Status 2 Status 3 Analog Clamp Control Digital Clamp Control 1 Reserved Shaping Filter Control Shaping Filter Control 2 Comb Filter Control Reserved Pixel Delay Control Reserved Misc Gain Control AGC Mode Control Chroma Gain Control 1 Chroma Gain Control 2 Luma Gain Control 1 Luma Gain Control 2 VSync Field Control 1 VSync Field Control 2 VSync Field Control 3 HSync Position Control 1 HSync Position Control 2 HSync Position Control 3 Polarity NTSC Comb Control PAL Comb Control ADC Control Reserved Manual Window Control Bit 7 VID_SEL.3 Bit 6 VID_SEL.2 ENHSPLL VBI_EN BT656-4 TOD AD_SEC525_EN CON.7 BRI.7 HUE.7 DEF_Y.5 DEF_C.7 Bit 5 VID_SEL.1 BETACAM Bit 4 VID_SEL.0 Bit 3 INSEL.3 ENVSPROC Bit 1 INSEL.1 Bit 0 INSEL.0 YPM.2 YPM.1 YPM.0 OF_SEL.3 DR_STR.1 OF_SEL.2 DR_STR.0 OF_SEL.1 TIM_OE OF_SEL.0 BL_C_VBI EN_SFL_PI SD_DUP_AV RANGE AD_SECAM_EN CON.6 AD_N443_EN CON.5 AD_P60_EN CON.4 AD_PALN_EN CON.3 AD_PALM_EN CON.2 AD_NTSC_EN CON.1 AD_PAL_EN CON.0 BRI.6 HUE.6 DEF_Y.4 DEF_C.6 TRI_LLC BRI.5 HUE.5 DEF_Y.3 DEF_C.5 BRI.4 HUE.4 DEF_Y.2 DEF_C.4 BRI.3 HUE.3 DEF_Y.1 DEF_C.3 DR_STR_C.1 BRI.2 HUE.2 DEF_Y.0 DEF_C.2 DR_STR_C.0 PDBP BRI.1 HUE.1 DEF_VAL_AUTO_EN DEF_C.1 DR_STR_S.1 BRI.0 HUE.0 DEF_VAL_EN DEF_C.0 DR_STR_S.0 AD_RESULT.0 IDENT.4 LL NSTD FREE_RUN_ACT CCLEN FOLLOW_PW IDENT.3 MV AGC DET FSC_LOCK IDENT.2 MV PS DET LOST_LOCK IDENT.1 MVCS T3 IN_LOCK IDENT.0 MVCS DET INST_HLOC K YSFM.4 YSFM.3 YSFM.2 YSFM.1 YSFM.0 WYSFM.4 WYSFM.3 WYSFM.2 WYSFM.1 WYSFM.0 NSFSEL.1 NSFSEL.0 PSFSEL.1 PSFSEL.0 CTA.0 LTA.1 LTA.0 CMG.11 CMG.10 CAGC.1 CMG.9 PW_UPD CAGC.0 CMG.8 CMG.3 CMG.2 CMG.1 CMG.0 LMG.11 LMG.10 LMG.9 LMG.8 LMG.4 LMG.3 LMG.2 LMG.1 LMG.0 NEWAVMODE HVSTIM HSE.10 HSE.9 HSE.8 PWRDN COL_KILL IDENT.7 AD_RESULT.2 IDENT.6 PAL SW LOCK INTERLACE AD_RESULT.1 IDENT.5 FSC NSTD STD FLD LEN DCT.1 DCT.0 CSFM.1 CSFM.0 CSFM.2 Bit 2 INSEL.2 WYSFMOVR SWPC AUTO_PDC_EN CTA.2 CTA.1 LAGC.1 LAGC.0 CAGT.1 CKE LAGC.2 CAGT.0 CMG.7 CMG.6 CMG.5 LAGT.1 LGAT.0 LMG.7 LMG.6 VSBHO VSBHE VSEHO VSEHE LMG.5 CMG.4 HSB.10 HSB.9 HSB.8 HSB.7 HSB.6 HSB.5 HSB.4 HSB.3 HSB.2 HSB.1 HSB.0 HSE.7 HSE.6 HSE.5 HSE.4 HSE.3 HSE.2 HSE.1 HSE.0 PHS CTAPSN.1 CTAPSP.1 CTAPSN.0 CTAPSP.0 PVS CCMN.2 CCMP.2 CCMN.1 CCMP.1 PF CCMN.0 CCMP.0 PWRDN_AD C_0 YCMN.2 YCMP.2 PWRDN_AD C_1 YCMN.1 YCMP.1 PWRDN_ADC_2 CKILLTHR.2 CKILLTHR.1 CKILLTHR.0 Rev. A | Page 66 of 104 PCLK YCMN.0 YCMP.0 ADV7181 Register Name Reserved Gemstar Ctrl 1 Gemstar Ctrl 2 Gemstar Ctrl 3 Gemstar Ctrl 4 Gemstar Ctrl 5 CTI DNR Ctrl 1 CTI DNR Ctrl 2 Reserved CTI DNR Ctrl 4 Lock Count Reserved Free Run Line Length 1 Free Run Line Length 2 VBI Info WSS 1 WSS 2 EDTV 1 EDTV 2 EDTV 3 CGMS 1 CGMS 2 CGMS 3 CCAP 1 CCAP 2 Letterbox 1 Letterbox 2 Letterbox 3 Reserved CRC Enable Reserved ADC Switch 1 ADC Switch 2 Reserved Letterbox Control 1 Letterbox Control 2 Reserved Reserved Reserved SD Offset Cb SD Offset Cr SD Saturation Cb SD Saturation Cr NTSC V Bit Begin NTSC V Bit End NTSC F Bit Toggle PAL V Bit Begin PAL V Bit End PAL F Bit Toggle Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GDECEL.15 GDECEL.7 GDECOL.15 GDECOL.7 GDECEL.14 GDECEL.6 GDECOL.14 GDECOL.6 GDECEL.13 GDECEL.5 GDECOL.13 GDECOL.5 GDECEL.12 GDECEL.4 GDECOL.12 GDECOL.4 GDECEL.11 GDECEL.3 GDECOL.11 GDECOL.3 GDECEL.10 GDECEL.2 GDECOL.10 GDECOL.2 GDECEL.9 GDECEL.1 GDECOL.9 GDECOL.1 CTI_C_TH.7 CTI_C_TH.6 DNR_EN CTI_C_TH.5 CTI_C_TH.4 CTI_AB.1 CTI_C_TH.3 CTI_AB.0 CTI_C_TH.2 CTI_AB_EN CTI_C_TH.1 GDECEL.8 GDECEL.0 GDECOL.8 GDECOL.0 GDECAD CTI_EN CTI_C_TH.0 DNR_TH.7 FSCLE DNR_TH.6 SRLS DNR_TH.5 COL.2 DNR_TH.4 COL.1 DNR_TH.3 COL.0 DNR_TH.2 CIL.2 DNR_TH.1 CIL.1 DNR_TH.0 CIL.0 LLC_PAD_SEL.2 LLC_PAD_SEL.1 LLC_PAD_SEL.0 WSS1.6 WSS2.6 EDTV1.6 EDTV2.6 EDTV3.6 CGMS1.6 CGMS2.6 CGMS3.6 CCAP1.6 CCAP2.6 LB_LCT.6 LB_LCM.6 LB_LCB.6 WSS1.5 WSS2.5 EDTV1.5 EDTV2.5 EDTV3.5 CGMS1.5 CGMS2.5 CGMS3.5 CCAP1.5 CCAP2.5 LB_LCT.5 LB_LCM.5 LB_LCB.5 WSS1.4 WSS2.4 EDTV1.4 EDTV2.4 EDTV3.4 CGMS1.4 CGMS2.4 CGMS3.4 CCAP1.4 CCAP2.4 LB_LCT.4 LB_LCM.4 LB_LCB.4 CGMSD WSS1.3 WSS2.3 EDTV1.3 EDTV2.3 EDTV3.3 CGMS1.3 CGMS2.3 CGMS3.3 CCAP1.3 CCAP2.3 LB_LCT.3 LB_LCM.3 LB_LCB.3 EDTVD WSS1.2 WSS2.2 EDTV1.2 EDTV2.2 EDTV3.2 CGMS1.2 CGMS2.2 CGMS3.2 CCAP1.2 CCAP2.2 LB_LCT.2 LB_LCM.2 LB_LCB.2 CCAPD WSS1.1 WSS2.1 EDTV1.1 EDTV2.1 EDTV3.1 CGMS1.1 CGMS2.1 CGMS3.1 CCAP1.1 CCAP2.1 LB_LCT.1 LB_LCM.1 LB_LCB.1 WSSD WSS1.0 WSS2.0 EDTV1.0 EDTV2.0 EDTV3.0 CGMS1.0 CGMS2.0 CGMS3.0 CCAP1.0 CCAP2.0 LB_LCT.0 LB_LCM.0 LB_LCB.0 WSS1.7 WSS2.7 EDTV1.7 EDTV2.7 EDTV3.7 CGMS1.7 CGMS2.7 CGMS3.7 CCAP1.7 CCAP2.7 LB_LCT.7 LB_LCM.7 LB_LCB.7 CRC_ENABLE ADC1_SW.3 ADC_SW_M AN ADC1_SW.2 ADC1_SW.1 ADC1_SW.0 ADC0_SW.3 ADC2_SW.3 ADC0_SW.2 ADC2_SW.2 ADC0_SW.1 ADC2_SW.1 ADC0_SW.0 ADC2_SW.0 LB_SL.3 LB_SL.2 LB_SL.1 LB_TH.4 LB_SL.0 LB_TH.3 LB_EL.3 LB_TH.2 LB_EL.2 LB_TH.1 LB_EL.1 LB_TH.0 LB_EL.0 SD_OFF_CB.7 SD_OFF_CR.7 SD_SAT_CB.7 SD_SAT_CR.7 NVBEGDEL O NVENDDEL O NFTOGDEL O PVBEGDEL O PVENDDEL O PFTOGDEL O SD_OFF_CB.6 SD_OFF_CR.6 SD_SAT_CB.6 SD_SAT_CR.6 NVBEGDEL E NVENDDEL E NFTOGDEL E PVBEGDEL E PVENDDEL E PFTOGDEL E SD_OFF_CB.5 SD_OFF_CR.5 SD_SAT_CB.5 SD_SAT_CR.5 NVBEGSIGN NVENDSIGN NFTOGSIGN PVBEGSIGN PVENDSIGN PFTOGSIGN SD_OFF_CB.4 SD_OFF_CR.4 SD_SAT_CB.4 SD_SAT_CR.4 NVBEG.4 NVEND.4 NFTOG.4 PVBEG.4 PVEND.4 PFTOG.4 SD_OFF_CB.3 SD_OFF_CR.3 SD_SAT_CB.3 SD_SAT_CR.3 NVBEG.3 NVEND.3 NFTOG.3 PVBEG.3 PVEND.3 PFTOG.3 SD_OFF_CB.2 SD_OFF_CR.2 SD_SAT_CB.2 SD_SAT_CR.2 NVBEG.2 NVEND.2 NFTOG.2 PVBEG.2 PVEND.2 PFTOG.2 SD_OFF_CB.1 SD_OFF_CR .1 SD_SAT_CB.1 SD_SAT_CR.1 NVBEG.1 NVEND.1 NFTOG.1 PVBEG.1 PVEND.1 PFTOG.1 SD_OFF_CB.0 SD_OFF_CR.0 SD_SAT_CB.0 SD_SAT_CR.0 NVBEG.0 NVEND.0 NFTOG.0 PVBEG.0 PVEND.0 PFTOG.0 Rev. A | Page 67 of 104 ADV7181 Table 172. VBI Port Register Map Details Register Name VBI Info WSS 1 WSS 2 EDTV 1 EDTV 2 EDTV 3 CGMS 1 CGMS 2 CGMS 3 CCAP 1 CCAP 2 Reset Value xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx rw r r r r r r r r r r r Subaddress 0 0x00 1 0x01 2 0x02 3 0x03 4 0x04 5 0x05 6 0x06 7 0x07 8 0x08 9 0x09 10 0x0A 7 6 5 4 WSS1.7 WSS2.7 EDTV1.7 EDTV2.7 EDTV3.7 CGMS1.7 CGMS2.7 CGMS3.7 CCAP1.7 CCAP2.7 WSS1.6 WSS2.6 EDTV1.6 EDTV2.6 EDTV3.6 CGMS1.6 CGMS2.6 CGMS3.6 CCAP1.6 CCAP2.6 WSS1.5 WSS2.5 EDTV1.5 EDTV2.5 EDTV3.5 CGMS1.5 CGMS2.5 CGMS3.5 CCAP1.5 CCAP2.5 WSS1.4 WSS2.4 EDTV1.4 EDTV2.4 EDTV3.4 CGMS1.4 CGMS2.4 CGMS3.4 CCAP1.4 CCAP2.4 Rev. A | Page 68 of 104 3 CGMSD WSS1.3 WSS2.3 EDTV1.3 EDTV2.3 EDTV3.3 CGMS1.3 CGMS2.3 CGMS3.3 CCAP1.3 CCAP2.3 2 EDTVD WSS1.2 WSS2.2 EDTV1.2 EDTV2.2 EDTV3.2 CGMS1.2 CGMS2.2 CGMS3.2 CCAP1.2 CCAP2.2 1 CCAPD WSS1.1 WSS2.1 EDTV1.1 EDTV2.1 EDTV3.1 CGMS1.1 CGMS2.1 CGMS3.1 CCAP1.1 CCAP2.1 0 WSSD WSS1.0 WSS2.0 EDTV1.0 EDTV2.0 EDTV3.0 CGMS1.0 CGMS2.0 CGMS3.0 CCAP1.0 CCAP2.0 ADV7181 I2C REGISTER MAP DETAILS Table 173. Register 0x00 Bit Subaddress 0x00 Register Input Control Bit Description 7 6 5 4 INSEL [3:0]. The INSEL bits must be set to correctly configure the ADV7181 to process the input video format. VID_SEL [3:0]. The VID_SEL bits allow the user to select the input video standard. 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 1 0 1 0 1 1 1 1 1 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 1 1 1 0 1 3 2 1 0 Register Setting 0 0 1 0 1 0 0 1 0 0 0 1 Composite S-Video YPrPb Auto-detect PAL (BGHID), NTSC (without pedestal) Auto-detect PAL (BGHID), NTSC (M) (with pedestal) Auto-detect PAL (N), NTSC (M) (without pedestal) Auto-detect PAL (N), NTSC (M) (with pedestal) NTSC(J) NTSC(M) PAL 60 NTSC 4.43 PAL BGHID PAL N (BGHID without pedestal) PAL M (without pedestal) PAL M PAL combination N PAL combination N (with pedestal) SECAM SECAM (with pedestal) Note: Grayed out sections mark the reset value of the register Table 174. Register 0x01 Bit Subaddress 0x01 Register Video Selection Bit Description Reserved 7 6 5 4 3 2 1 0 Register Setting 0 0 0 Set to default Comments ENVSPROC 0 1 Disable VSync processor Enable VSync processor Reserved 0 Set to default BETACAM 0 1 Standard video input Betacam input enable ENHSPLL 0 1 Disable HSync processor Enable HSync processor Reserved 1 Set to default Rev. A | Page 69 of 104 SECAM standard. YPrPb through SDP. ADV7181 Table 175. Register 0x02 Bit Subaddress 0x02 Register Video Enhancement Control Bit Description YPM [2:0]. Y Peaking Filter mode. This function allows the user to boost/ attenuate luma signals around the color subcarrier frequency. 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Register Setting C = +4.5 dB, S = +9.25 dB C = +4.5 dB, S = +9.25 dB C = +4.5 dB, S = +5.75 dB C = +1.25 dB, S = +3.3 dB No Change. C = +0 dB, S = +0 dB C = -1.25 dB, S = -3 dB C = -1.75 dB, S = -8 dB C = -3.0 dB, S = -8 dB Reserved 0 0 0 0 Rev. A | Page 70 of 104 0 Set to default Comments Used to enhance the picture and improve contrast C = Composite (2.6 MHz), S = S-Video (3.75 MHz) ADV7181 Table 176. Register 0x03 Bit Subaddress 0x03 Register Output Control Bit Description SD_DUP_AV. Duplicates the AV codes from the Luma into the chroma path. 7 6 5 4 3 2 1 0 1 Reserved 0 OF_SEL [3:0]. Allows the user to choose from a set of output formats. 0 0 0 0 0 0 1 0 0 0 1 1 0 1 0 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Register Setting AV codes to suit 8-bit interleaved data output AV codes duplicated (for 16-bit interfaces) Set as default Reserved Reserved 16-bit @ LLC1 4:2:2 8-bit @ LLC1 4:2:2 ITU-R BT.656 Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used See also TIM_OE (Table 177); TRI_LLC (Table 179) TOD. Three-State Output Drivers. This bit allows the user to three-state the output drivers: P[19:0], HS, VS, FIELD, and SFL. 0 1 VBI_EN. Allows VBI data (Lines 1 to 21) to be passed through with only a minimum amount of filtering performed. Comments 0 1 Rev. A | Page 71 of 104 Output pins enabled Drivers three-stated All lines filtered and scaled Only active video region filtered ADV7181 Table 177. Register 0x04 Bit Subaddress 0x04 Register Extended Output Control Bit Description RANGE. Allows the user to select the range of output values. Can be BT656 compliant, or can fill the whole accessible number range. 7 6 5 4 3 2 1 0 0 1 Register Setting 16 < Y < 235, 16 < C < 240 1 < Y < 254, 1 < C < 254 EN_SFL_PIN 0 1 SFL output is disabled SFL information output on the SFL pin Comments ITU-R BT.656 Extended Range SFL output enables encoder and decoder to be connected directly During VBI BL_C_VBI. Blank Chroma during VBI. If set, enables data in the VBI region to be passed through the decoder undistorted. 0 1 Decode and output color Blank Cr and Cb Controlled by TOD TIM_OE. Timing signals output enable. 0 1 HS, VS, F threestated HS, VS, F forced active Recommended DR_STR[1:0]. Drive strength of output drivers can be increased or decreased for EMC or crosstalk reasons. 0 0 1 0 1 0 1 1 Low drive, 1x Medium-low, 2x Medium-high, 3x High drive, 4x Reserved 1 BT656-4. Allows the user to select an output mode compatible with ITU- R BT656-3/4. 0 1 Rev. A | Page 72 of 104 Set to default BT656-3 compatible BT656-4 compatible ADV7181 Table 178. Register 0x07 and 0x08 Bit Subaddress 0x07 Register Autodetect Enable Bit Description AD_PAL_EN. PAL B/G/I/H autodetect enable. 7 6 5 4 3 2 1 0 Register Setting 0 1 Disable Enable Comments AD_NTSC_EN. NTSC autodetect enable. 0 1 Disable Enable AD_PALM_EN. PAL M autodetect enable 0 1 Disable Enable AD_PALN_EN. PAL N autodetect enable. 0 1 Disable Enable AD_P60_EN. PAL 60 autodetect enable. 0 1 Disable Enable AD_N443_EN. NTSC443 autodetect enable. 0 1 Disable Enable AD_SECAM_EN. SECAM autodetect enable. 0 1 AD_SEC525_EN. SECAM 525 autodetect enable. 0x08 Contrast Register CON[7:0]. Contrast adjust. This is the user control for contrast adjustment. Disable Enable 0 1 1 Disable Enable 0 Rev. A | Page 73 of 104 0 0 0 0 0 0 Luma gain = 1 0x00 Gain = 0 0x80 Gain = 1 0xFF Gain = 2 ADV7181 Table 179. Register 0x09 to 0x0E Bit Subaddress 0x09 Register Reserved (Saturation) Bit Description Reserved 0x0A Brightness Register BRI[7:0]. This register controls the brightness of the video signal. HUE[7:0]. This register contains the value for the color hue adjustment. DEF_VAL_EN. Default value enable. 0x0B 0x0C Hue Register Default Value Y 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 DEF_VAL_AUTO_EN. Default value. 0 0x0D Default Value C 0 ADI Control 1 1 0 1 1 1 1 1 1 DR_STR_S[1:0]. Select the drive strength of the sync signals. HS, VS, and F can be increased or decreased for EMC or crosstalk reasons. DR_STR_C[1:0]. Select the strength of the clock signal output driver. Can be increased or decreased for EMC or crosstalk reasons. 0 0 0 1 1 1 0 1 Free Run mode dependent on DEF_VAL_AUTO_EN Force SDP Free Run mode on and output blue screen Y[7:0] = {DEF_Y[5:0], 0, 0, 0, 0} Cr[7:0] = {DEF_C[7:4], 0, 0, 0, 0, 0, 0} Cb[7:0] = {DEF_C[3:0], 0, 0, 0, 0, 0, 0} DEF_C[7:0]. Default value C. Cr and Cb default values are defined in this register. 0 0x0E 0 0 0 0 0 0 1 1 1 0 1 Comments 0x00 = 0IRE 0x7F = 100IRE 0xFF = -100IRE Hue range = -90 to +90 Disable SDP Free Run mode Enable Automatic Free Run mode (blue screen) 1 DEF_Y[5:0]. Default value Y. This register holds the Y default value. Register Setting When lock is lost, Free Run mode can be enabled to output stable timing, clock, and a set color Default Y value output in freerun mode Default Cb/Cr value output in Free Run mode. Default values give blue screen output Low drive strength (1x) Medium-low (2x) Medium-high (3x) High drive strength (4x) Low drive strength (1x) Medium-low (2x) Medium-high (3x) High drive strength (4x) Reserved 0 0 Set as default TRI_LLC. Enables the LLC pin to be three-stated. 0 1 LLC pin active LLC pin drivers threestated Reserved 0 Rev. A | Page 74 of 104 Set as default See TOD (Table 176); TIM_OE (Table 177) ADV7181 Table 180. Register 0x0F to 0x11 Bit Subaddress 0x0F Register Power Management Bit Description Reserved 7 6 5 4 3 PDBP. Power-down bit priority selects between PWRDN bit or PIN. 2 1 0 Register Setting 0 0 Set to default 0 Comments Chip power-down controlled by pin Bit has priority (pin disregarded) 1 Reserved 0 PWRDN. Power-down places the decoder in a full power-down mode. 0 Set to default 0 1 System functional Powered down See PDBP, 0x0F, Bit 2 Reserved 0 RES. Chip Reset will load all I2C bits with default values. 0x10 Status Register Read-Only 0 Set to default Normal operation 1 Start reset sequence STATUS_1[7:0]. Provides information about the internal status of the decoder. STATUS_1[3:0] x x x x STATUS_1[6:4] AD_RESULT[2:0]. Autodetection result reports the findings. STATUS_1[7] COL_KILL. Color Kill. 0x11 Info Register Read-Only IDENT[7:0] Provides identification on the revision of the part. 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 x In lock (right now) = 1 Lost lock (since last read) Fsc lock (right now) = 1 Peak white AGC mode active = 1 NTSM-MJ NTSC-443 PAL-M PAL-60 PAL-BGHID SECAM PAL combination N SECAM 525 x Color kill is active = 1 x x x x Rev. A | Page 75 of 104 x x x Executing reset takes approx. 2 ms. This bit is self clearing. Detected standard ADV7181 Table 181. Register 0x12 to 0x13 Subaddress 0x12 Register Status Register 2. Read-only. Bit Description STATUS_2[7:0]. Provides information about the internal status of the decoder. STATUS_2[5:0] 7 6 Bit 4 3 5 2 1 0 Register Setting Comments x MV color striping detected MV color striping type MV pseudosync detected MV AGC pulses detected Nonstandard line length Fsc frequency nonstandard 1 = Detected 1 = Horizontal lock achieved 1 = Reserved bits 1 = Free Run mode active 1 = Field length standard 1 = Swinging burst detected Unfiltered x x x x x 0 = Type 2, 1 = Type 3 1 = Detected 1 = Detected 1 = Detected 1 = Detected Reserved x 0x13 Status Register 3. Read-only. x STATUS_3[7:0]. Provides information about the internal status of the decoder. x x x x x x x No function Blue screen output Reliable sequence Table 182. Register 0x14 Bit Subaddress 0x14 Register Analog Clamp Control Bit Description Reserved 7 6 5 CCLEN. Current clamp enable allows the user to switch off the current sources in the analog front. 4 3 2 1 0 Register Setting 0 0 1 0 Reserved. Set to default. 0 1 I sources switched off. I sources enabled. Reserved 0 Reserved. Set to default. Reserved 0 0 7 6 Reserved. Set to default. Table 183. Register 0x15 Bit Subaddress 0x15 Register Digital Clamp Control 1 Bit Description Reserved DCT[1:0]. Digital clamp timing determines the time constant of the digital fine clamp circuitry. 0 0 1 1 5 0 1 0 1 4 3 2 1 0 Register Setting x x x x x Set to default Slow (TC = 1 s) Medium (TC = 0.5 s) Fast (TC = 0.1 s) TC dependant on video Reserved 0 Rev. A | Page 76 of 104 Set to default ADV7181 Table 184. Register 0x17 Bit Subaddress 0x17 Register Shaping Filter Control Bit Description YSFM[4:0]. Selects Y Shaping Filter mode when in CVBS only mode. Allows the user to select a wide range of low-pass and notch filters. If either auto mode is selected, the decoder selects the optimum Y filter depending on the CVBS video source quality (good vs. bad). CSFM[2:0]. C Shaping Filter mode allows the selection from a range of low-pass chrominance filters. If either auto mode is selected, the decoder selects the optimum C filter depending on the CVBS video source quality (good vs. bad).Nonauto settings force a C filter for all standards and quality of CVBS video. 7 0 0 0 0 1 1 1 1 6 0 0 1 1 0 0 1 1 5 4 3 2 1 0 Register Setting 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Auto wide notch for poor quality sources or wideband filter with Comb for good quality input Auto narrow notch for poor quality sources or wideband filter with comb for good quality input SVHS 1 SVHS 2 SVHS 3 SVHS 4 SVHS 5 SVHS 6 SVHS 7 SVHS 8 SVHS 9 SVHS 10 SVHS 11 SVHS 12 SVHS 13 SVHS 14 SVHS 15 SVHS 16 SVHS 17 SVHS 18 (CCIR601) PAL NN1 PAL NN2 PAL NN3 PAL WN 1 PAL WN 2 NTSC NN1 NTSC NN2 NTSC NN3 NTSC WN1 NTSC WN2 NTSC WN3 Reserved 0 1 0 1 0 1 0 1 Rev. A | Page 77 of 104 Auto selection 1.5 MHz Auto selection 2.17 MHz SH1 SH2 SH3 SH4 SH5 Wideband mode Comments Decoder selects optimum Y shaping filter depending on CVBS quality. If one of these modes is selected, the decoder does not change filter modes depending on video quality. A fixed filter response (the one selected) is used for good and bad quality video. Automatically selects a C filter based on video standard and quality. Selects a C filter for all video standards and for good and bad video. ADV7181 Table 185. Register 0x18 to 0x19 Bit Subaddress 0x18 Register Shaping Filter Control 2 Bit Description WYSFM[4:0] Wideband Y Shaping Filter Mode allows the user to select which Y shaping filter is used for the Y component of Y/C, YPbPr, B/W input signals; it is also used when a good quality input CVBS signal is detected. For all other inputs, the Y shaping filter chosen is controlled by YSFM[4:0]. 7 6 5 4 3 2 1 0 Comments 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 Reserved. Do not use. Reserved. Do not use. SVHS 1 SVHS 2 SVHS 3 SVHS 4 SVHS 5 SVHS 6 SVHS 7 SVHS 8 SVHS 9 SVHS 10 SVHS 11 SVHS 12 SVHS 13 SVHS 14 SVHS 15 SVHS 16 SVHS 17 SVHS 18 (CCIR 601) Reserved. Do not use. Reserved. Do not use. Reserved. Do not use. Reserved 0 WYSFMOVR. Enables the use of the automatic WYSFN filter. 0 Set to default 0 Manual select filter using WYSFM[4:0] Auto selection of best filter 1 0x19 Comb Filter Control PSFSEL[1:0]. Controls the signal bandwidth that is fed to the comb filters (PAL). 0 0 1 1 NSFSEL[1:0]. Controls the signal bandwidth that is fed to the comb filters (NTSC). 0 0 1 1 0 1 0 1 0 1 0 1 Narrow Medium Wide Widest Narrow Medium Medium Wide Reserved 1 Rev. A | Page 78 of 104 1 1 1 Set as default ADV7181 Table 186. Register 0x27 to 0x2A Bit Subaddress 0x27 Register Pixel Delay Control Bit Description LTA[1:0]. Luma timing adjust allows the user to specify a timing difference between chroma and luma samples. 7 6 5 4 3 2 1 0 Comments 0 0 1 0 0 1 0 1 No Delay Luma 1 clk (37 ns) delayed Luma 2 clk (72 ns) early Luma 1 clk (37 ns) early Notes CVBS mode LTA[1:0] = 00b; S-Video mode LTA[1:0]= 01b, YPrPb mode LTA[1:0] = 01b Reserved 0 CTA[2:0]. Chroma timing adjust allows a specified timing difference between the luma and chroma samples. 0 0 0 0 1 1 1 1 AUTO_PDC_EN. Automatically programs the LTA/CTA values so that luma and chroma are aligned at output for all modes of operation. SWPC. Allows the Cr and Cb samples to be swapped. 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 Set to 0 Not a valid setting Chroma + 2 pixels (early) Chroma + 1 pixel (early) No Delay Chroma - 1 pixel (late) Chroma - 2 pixels (late) Chroma - 3 pixels (late) Not a valid setting Use values in LTA[1:0] and CTA[2:0] for delaying luma/chroma LTA and CTA values determined automatically No swapping Swap the Cr and Cb Rev. A | Page 79 of 104 CVBS mode CTA[2:0] = 011b, S-Video mode CTA[2:0] = 101b, YPrPb mode CTA[2:0] = 110b ADV7181 Table 187. Register 0x2B to 0x2C Bit Subaddress 0x2B Register Misc Gain Control Bit Description PW_UPD. Peak white update determines the rate of gain. 7 6 5 4 3 2 1 0 Comments Notes 0 Update once per video line Update once per field Peak white must be enabled. See LAGC[2:0]. 1 Reserved 1 0 0 0 0 1 Set to default For SECAM color kill, threshold is set at 8%. CKE. Color kill enable allows the color kill function to be switched on and off. 0 1 Color kill disabled Color kill enabled See CKILLTHR[2:0] (Table 195). Reserved 1 0x2C AGC Mode Control 1 1 Set to default CAGC[1:0]. Chroma automatic gain control selects the basic mode of operation for the AGC in the chroma path. 0 0 0 1 1 1 0 1 Manual fixed gain Use luma gain for chroma Automatic gain Freeze chroma gain Use CMG[11:0]. Based on color burst. Reserved 1 LAGC[2:0]. Luma automatic gain control selects the mode of operation for the gain control in the luma path. 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 Set to 1 Manual fixed gain AGC no override through white peak. Man IRE control. AGC auto-override through white peak. Man IRE control. AGC no override through white peak. Auto IRE control. AGC auto-override through white peak. Auto IRE control. AGC active video with white peak AGC active video with average video Freeze gain Reserved 1 Rev. A | Page 80 of 104 Set to 1 Use LMG[11:0]. Blank level to sync tip. Blank level to sync tip. Blank level to sync tip. Blank level to sync tip ADV7181 Table 188. Register 0x2D to 0x30 Bit Subaddress 0x2D Register Chroma Gain Control 1 Bit Description CMG[11:8]. Chroma manual gain can be used to program a desired manual chroma gain. Reading back from this register in AGC mode gives the current gain. Reserved 7 6 5 1 4 3 2 1 0 0 1 0 0 1 Set to 1 Has an effect only if CAGC[1:0] is set to auto gain (10). Slow (TC = 2 s) Medium (TC = 1 s) Fast (TC = 0.2 s) Adaptive CMG[11:0] = 750d; gain is 1 in NTSC CMG[11:0] = 741d; gain is 1 in PAL. CAGT[1:0]. Chroma automatic gain timing allows adjustment of the chroma AGC tracking speed. 0 0 1 1 0x2E Chroma Gain Control 2 CMG[7:0]. Chroma manual gain lower 8 bits. See CMG[11:8] for description. 0x2F Luma Gain Control 1 LMG[11:8]. Luma manual gain can be used program a desired manual chroma gain, or to read back the actual gain value used. 0 0 1 0 1 0 0 0 Comments CAGC[1:0] settings decide in which mode CMG[11:0] operates . 0 0 0 Notes Min value is 0dec (G = -60 dB) Max value is 3750 (Gain = 5). 0 LAGC[1:0] settings decide in which mode LMG[11:0] operates. x x x x Reserved 1 1 Set to 1 Only has an effect if AGC[1:0] is set to auto gain (001, 010, 011,or 100) Slow (TC = 2 s) Medium (TC = 1 s) Fast (TC = 0.2 s) Adaptive LMG[11:0] = 1234dec; gain is 1 in NTSC LMG[11:0] = 1266dec; gain is 1 in PAL. LAGT[1:0]. Luma automatic gain timing allows adjustment of the luma AGC tracking speed. 0 0 1 1 0x30 Luma Gain Control 2 0 1 0 1 LMG[7:0]. Luma manual gain can be used to program a desired manual chroma gain or read back the actual used gain value. x x x x x Rev. A | Page 81 of 104 x x x Min value NTSC 1024 (G = 0.85) PAL (G = 0.81) Max value NTSC 2468 (G = 2), PAL = 2532 (G = 2) ADV7181 Table 189. Register 0x31 Bit Subaddress 0x31 Register VS and FIELD Control 1 Bit Description Reserved 7 6 5 4 3 HVSTIM. Selects where within a line of video the VS signal is asserted. 0 1 NEWAVMODE. Sets the EAV/SAV mode. 2 1 0 Comments 0 1 0 Set to default Notes Start of line relative to HSE Start of line relative to HSB 0 HSE = Hsync end HSB = Hsync begin EAV/SAV codes generated to suit ADI encoders Manual VS/Field position controlled by registers 0x32, 0x33, and 0xE5-0xEA 1 Reserved 0 0 0 Set to default Table 190. Register 0x32 to 0x33 Subaddress 0x32 Register VSync Field Control 2 Bit Description Bit 7 6 5 4 3 2 1 0 Comments 0 0 0 0 0 1 Set to default. Notes Reserved VSBHE 0 VS goes high in the middle of the line (even field). VS changes state at the start of the line (even field). 1 NEWAVMODE bit must be set high. VSBHO 0 VS goes high in the middle of the line (odd field). VS changes state at the start of the line (odd field). 1 0x33 VSync Field Control 3 Reserved 0 0 0 1 0 0 Set to default. VSEHE 0 VS goes low in the middle of the line (even field). VS changes state at the start of the line (even field). 1 VSEHO 0 VS goes low in the middle of the line (odd field). VS changes state at the start of the line odd field. 1 Rev. A | Page 82 of 104 NEWAVMODE bit must be set high. ADV7181 Table 191. Register 0x34 to 0x36 Bit Subaddress 0x34 Register HS Position Control 1 Bit Description 7 6 5 4 3 HSE[10:8]. HS end allows the positioning of the HS output within the video line. 2 1 0 Comments Notes 0 0 0 HS output ends HSE[10:0] pixels after the falling edge of HSync Using HSB and HSE, the user can program the position and length of the output HSync. Reserved 0 HSB[10:8]. HS begin allows the positioning of the HS output within the video line. Reserved 0 0 Set to 0 HS output starts HSB[10:0] pixels after the falling edge of HSync 0 0 0x35 0x36 HS Position Control 2 HS Position Control 3 HSB[7:0] See above, using HSB[9:0] and HSE[9:0] the user can program the position and length of HS output signal. HSE[7:0] See above. Set to 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 Table 192. Register 0x37 Subaddress 0x37 Register Polarity Bit Description PCLK. Sets the polarity of LLC1. 7 6 5 Bit 4 3 2 1 0 Comment 0 1 Invert polarity Normal polarity as per Timing Diagrams Reserved 0 0 Set to 0 PF. Sets the FIELD polarity. 0 1 Active high Active low Reserved 0 Set to 0 PVS. Sets the VS polarity. 0 1 Active high Active low Reserved 0 Set to 0 PHS. Sets HS polarity. 0 1 Rev. A | Page 83 of 104 Active high Active low ADV7181 Table 193. Register 0x38 Bit Subaddress 0x38 Register NTSC Comb Control Bit Description YCMN[2:0]. Luma Comb Mode, NTSC. 7 6 CCMN[2:0]. Chroma Comb Mode, NTSC. CTAPSN[1:0]. Chroma Comb Taps, NTSC. 0 0 1 1 5 4 3 0 0 0 1 1 0 0 0 1 1 1 0 1 1 1 2 1 0 Comments 0 0 0 1 1 0 0 0 1 1 1 0 1 1 1 Adaptive 3-line, 3-tap luma Use low-pass notch Fixed luma comb (2-line) Fixed luma comb (3-line) Fixed luma comb (2-line) 0 1 0 1 Rev. A | Page 84 of 104 3-line adaptive for CTAPSN = 01 4-line adaptive for CTAPSN = 10 5-line adaptive for CTAPSN = 11 Disable chroma comb Fixed 2-line for CTAPSN = 01 Fixed 3-line for CTAPSN = 10 Fixed 4-line for CTAPSN = 11 Fixed 3-line for CTAPSN = 01 Fixed 4-line for CTAPSN = 10 Fixed 5-line for CTAPSN = 11 Fixed 2-line for CTAPSN = 01 Fixed 3-line for CTAPSN = 10 Fixed 4-line for CTAPSN = 11 Adapts 3 lines - 2 lines Not used Adapts 5 lines - 3 lines Adapts 5 lines - 4 lines Notes Top lines of memory All lines of memory Bottom lines of memory Top lines of memory All lines of memory Bottom lines of memory ADV7181 Table 194. Register 0x39 to 0x3A Bit Subaddress 0x39 Register PAL Comb Control Bit Description YCMP[2:0]. Luma Comb mode, PAL. 7 6 CCMP[2:0]. Chroma Comb mode, PAL. 5 4 3 2 1 0 Comments 0 1 1 0 0 1 0 0 0 Adaptive 5-line, 3-tap luma comb Use low-pass notch Fixed luma comb 1 1 0 Fixed luma comb (5-line) 1 1 1 Fixed luma comb (3-line) 0 0 0 1 1 0 0 0 1 3-line adaptive for CTAPSN = 01 4-line adaptive for CTAPSN = 10 5-line adaptive for CTAPSN = 11 Disable chroma comb Fixed 2-line for CTAPSN = 01 0 Fixed 3-line for CTAPSN = 10 Fixed 4-line for CTAPSN = 11 Fixed 3-line for CTAPSN = 01 1 Fixed 4-line for CTAPSN = 10 Fixed 5-line for CTAPSN = 11 Fixed 2-line for CTAPSN = 01 1 1 1 1 Fixed 3-line for CTAPSN = 10 Fixed 4-line for CTAPSN = 11 CTAPSP[1:0]. Chroma comb taps, PAL. 0x3A 0 0 1 1 0 1 0 1 Adapts 5-lines - 2 lines (2 taps) Not used Adapts 5 lines - 3 lines (3 taps) Adapts 5 lines - 4 lines (4 taps) Reserved 0 PWRDN_ADC_2. Enables power down of ADC2. 0 1 PWRDN_ADC_1. Enables power down of ADC1. 0 1 PWRDN_ADC_0. Enables power down of ADC0. 0 1 Set as default ADC2 normal operation Power down ADC2 ADC1 normal operation Power down ADC1 ADC0 normal operation Power down ADC0 Reserved 0 0 0 1 Rev. A | Page 85 of 104 Set as default Notes Top lines of memory All lines of memory Bottom lines of memory Top lines of memory All lines of memory Bottom lines of memory ADV7181 Table 195. Register 0x3D Bit Subaddress 0x3D Register Manual Window Bit Description Reserved 7 6 5 4 3 2 1 0 Comments 0 0 1 1 Set to default CKILLTHR[2:0]. 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Kill at 0.5% Kill at 1.5% Kill at 2.5% Kill at 4% Kill at 8.5% Kill at 16% Kill at 32% Reserved Notes CKE = 1 enables the color kill function and must be enabled for CKILLTHR[2:0] to take effect. Reserved 0 Set to default Table 196. Registers 0x41 to 0x4C Bit Subaddress 0x41 Register Resample Control Bit Description Reserved 7 SFL_INV. Controls the behavior of the PAL switch bit. 6 5 4 3 2 1 0 Comments 0 1 0 0 0 0 Set to default 0 Notes SFL compatible with ADV7190/ADV7191/ADV7194 encoders SFL compatible with ADV717x/ADV7173x encoders 1 Reserved 0 0x48 Gemstar Control 1 0x49 Gemstar Control 2 0x4A Gemstar Control 3 0x4B Gemstar Control 4 0x4C Gemstar Control 5 GDECEL[15:0]. 16 individual enable bits that select the lines of video (even field lines 10-25) that the decoder checks for Gemstar compatible data. GDECEL[15:8]. See above. GDECEL[7:0]. See above. GDECOL[15:0]. 16 individual enable bits that select the lines of video (odd field lines 10-25) that the decoder checks for Gemstar compatible data. GDECOL[15:8]. See above. GDECOL[7:0]. See above. Set to default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GDECAD. Controls the manner in which decoded Gemstar data is inserted into the horizontal blanking period. Reserved x x x x x x Rev. A | Page 86 of 104 x LSB = Line 10 MSB = Line 25 Default = Do not check for Gemstar compatible data on any lines [10- 25] in even fields LSB = Line 10 MSB = Line 25 Default = Do not check for Gemstar compatible data on any lines [10- 25] in odd fields 0 Split data into half byte 1 Output in straight 8-bit format Undefined To avoid 00/FF code ADV7181 Table 197. Registers 0x4D to 0x50 Bit Subaddress 0x4D Register CTI DNR Control 1 Bit Description CTI_EN. CTI enable. 7 6 5 4 3 2 CTI_AB_EN. Enables the mixing of the transient improved chroma with the original signal. 1 0 Comments 0 1 Disable CTI Enable CTI 0 1 CTI_AB[1:0]. Controls the behavior of the alpha-blend circuitry. 0 0 1 1 Disable CTI alpha blender Enable CTI alpha blender 0 1 0 1 Sharpest mixing Sharp mixing Smooth Smoothest Reserved 0 Set to default DNR_EN. Enable or bypass the DNR block. 0 1 Bypass the DNR block Enable the DNR block Reserved 1 Set to default Reserved 1 0x4E 0x50 CTI DNR Control 2 CTI DNR Control 4 CTI_CTH[7:0]. Specifies how big the amplitude step must be to be steepened by the CTI block. DNR_TH[7:0]. Specifies the maximum edge that is interpreted as noise and is therefore blanked. 0 Set to default 0 0 0 1 0 0 0 Set to 0x04 for A/V input; set to 0x0A for tuner input. 0 0 Rev. A | Page 87 of 104 0 0 1 0 0 0 ADV7181 Table 198. Register 0x51 Bit Subaddress 0x51 Register Lock Count Bit Description CIL[2:0]. Count-into-lock determines the number of lines the system must remain in lock before showing a locked status. 7 6 COL[2:0]. Count-out-of-lock determines the number of lines the system must remain out-oflock before showing a lostlocked status. 5 0 0 0 0 1 1 1 1 SRLS. Select raw lock signal. Selects the determination of the lock status. 4 0 0 1 1 0 0 1 1 3 0 1 0 1 0 1 0 1 0 1 2 1 0 Comments 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 line of video 2 lines of video 5 lines of video 10 lines of video 100 lines of video 500 lines of video 1000 lines of video 100000 lines of video Notes Only operational for SDP modes 1 line of video 2 lines of video 5 lines of video 10 lines of video 100 lines of video 500 lines of video 1000 lines of video 100000 lines of video Over field with vertical info Line-to-line evaluation FSCLE must be set to 0 in YPrPb mode if a reliable LOST_LOCK bit is set to 0. FSCLE. Fsc lock enable. 0 Lock status set only by horizontal lock Lock status set by horizontal lock and subcarrier lock. 1 Rev. A | Page 88 of 104 ADV7181 Table 199. Registers 0x8F to 0x90 Bit Subaddress 0x8F Register Free Run Line Length 1 Bit Description Reserved 7 LLC_PAD_SEL [2:0]. Enables manual selection of clock for LLC1 pin. 6 5 4 0 0 0 1 0 1 3 2 1 0 Comments 0 0 0 0 Set to default LLC1 (nominal 27 MHz) selected out on LLC1 pin LLC2 (nominally 13.5 MHz) selected out on LLC1 pin Notes For 16-bit 4:2:2 out, OF_SEL[3:0] = 0010. Reserved 0 0x90 VBI Info Read Mode Details Set to default WSSD. Screen signaling detected. 0 1 No WSS detected WSS detected CCAPD. Closed caption data. 0 1 No CCAP signals detected CCAP sequence detected EDTVD. EDTV sequence. 0 1 No EDTV sequence detected EDTV sequence detected CGMSD. CGMS sequence. 0 1 Reserved x x x x Rev. A | Page 89 of 104 No CGMS transition detected CGMS sequence decoded Ready-only status bits ADV7181 Table 200. Registers 0x91 to 0x9D Bit Subaddress 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D Register WSS1[7:0]. Wide screen signaling data. Read-only register. WSS1[7:0]. Wide screen signaling data. Read-only register EDTV1[7:0]. EDTV data register. Readonly register. EDTV2[7:0]. EDTV data register. Readonly register. EDTV3[7:0]. EDTV data register. Readonly register. CGMS1[7:0]. CGMS data register. Readonly register. CGMS2[7:0]. CGMS data register. Readonly register. CGMS3[7:0]. CGMS data register. Readonly register. CCAP1[7:0]. Closed caption data register. Read-only register. CCAP2[7:0]. Closed caption data register. Read-only register. Letterbox 1. Read-only register. Letterbox 2. Read-only register. Letterbox 3. Read-only register. Bit Description WSS1[7:0] 7 6 5 4 3 2 1 0 x x x x x x x x WSS2[7:0] Comments Notes WSS2[7:6] are undetermined. x x x x x x x x x x x x x x x x x x x x x x x x EDTV1[7:0] EDTV2[7:0] EDTV3[7:0] EDTV3[7:6] are undetermined. x x x x x x x x x x x x x x x x x x x x x x x x EDTV3[5] is reserved for future use CGMS1[7:0] CGMS2[7:0] CGMS3[7:0] CGMS3[7:4] are undetermined. x x x x x x x x CCAP1[7:0] CCAP1[7] contains parity bit for byte 0. x x x x x x x x CCAP2[7:0] CCAP2[7] contains parity bit for byte 0. x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x LB_LCT[7:0] LB_LCM[7:0] LB_LCB[7:0] Rev. A | Page 90 of 104 Reports the number of black lines detected at top of active video. Reports the number of black lines detected in the bottom half of active video if subtitles are detected. Reports the number of black lines detected at the bottom of active video. This feature examines the active video at the start and at the end of each field. It enables format detection even if the video is not accompanied by a CGMS or WSS sequence. ADV7181 Table 201. Register 0xB2 Bit Subaddress 0xB2 Register CRC Enable Write Register Bit Description Reserved 7 6 5 4 3 CRC_ENABLE. Enables CRC checksum decoded from CGMS packet to validate CGMSD. 2 1 0 Comments 0 0 Set as default. 0 1 Turn off CRC check. CGMSD goes high with valid checksum. Reserved 0 0 0 1 1 Set as default. Table 202. Register 0xC3 Bit Subaddress 0xC3 Register ADC SWITCH 1 Bit Description ADC0_SW[3:0]. Manual muxing control for ADC0. ADC1_SW[3:0]. Manual muxing control for ADC1. 7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * NC = no connection. Rev. A | Page 91 of 104 3 2 1 0 Comment* 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 NC AIN2 NC NC AIN4 AIN6 NC NC NC AIN1 NC NC AIN3 AIN5 NC NC NC NC NC NC AIN4 AIN6 NC NC NC NC NC NC AIN3 AIN5 NC NC Note SETADC_sw_man_en = 1 ADV7181 Table 203. Register 0xC4 Bit Subaddress 0xC4 Register ADC SWITCH 2 Bit Description ADC2_SW[3:0]. Manual muxing control for ADC2. 7 6 5 4 3 2 1 0 Comments* 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 NC NC NC NC NC AIN6 NC NC NC NC NC NC NC AIN5 NC NC Reserved x ADC_SW_MAN_EN. Enable manual setting of the input signal muxing. x x 0 1 * NC = no connection. Rev. A | Page 92 of 104 Disable Enable Notes SETADC_sw_man_en = 1 ADV7181 Table 204. Registers 0xDC to 0xE4 Bit Subaddress 0xDC Register Letterbox Control 1 Bit Description LB_TH [4:0]. Sets the threshold value that detects a black. 7 6 5 4 3 2 1 0 Comments 0 1 1 0 0 Default threshold for detection of black lines. Reserved 1 0xDD Letterbox Control 2 0 1 Set as default LB_EL[3:0]. Programs the end line of the activity window for LB detection (end of field). LB_SL[3:0]. Programs the start line of the activity window for LB detection (start of field). 0xDE Reserved 0xDF Reserved 0xE0 Reserved 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LB detection ends with the last line of active video on a field. 1100: 262/525. Letterbox detection aligned with the start of active video. 0100: 23/286 NTSC. 0 0 0 1 0 1 0 0 0xE1 SD Offset Cb SD_OFF_CB [7:0]. Adjusts hue by selecting offset for the Cb channel. 1 0 0 0 0 0 0 0 0xE2 SD Offset Cr SD_OFF_CR [7:0]. Adjusts hue by selecting offset for the Cr channel. 1 0 0 0 0 0 0 0 0xE3 SD Saturation Cb SD_SAT_CB [7:0]. Adjusts saturation of the picture by affecting gain on the Cb channel. SD_SAT_CR [7:0]. Adjusts saturation of the picture by affecting gain on the Cr channel. 1 0 0 0 0 0 0 0 Chroma gain = 0 dB 1 0 0 0 0 0 0 0 Chroma gain = 0 dB 0xE4 SD Saturation Cr Rev. A | Page 93 of 104 ADV7181 Table 205. Registers 0xE5 to 0xE7 Bit Subaddress 0xE5 Register NTSC V Bit Begin Bit Description NVBEG[4:0]. How many lines after lCOUNT rollover to set V high. 7 6 5 4 3 2 1 0 Comments 0 0 1 0 1 NTSC default (BT.656) NVBEGSIGN 0 Set to low when manual programming Not suitable for user programming 1 NVBEGDELE. Delay V bit going high by one line relative to NVBEG (even field). NVBEGDELO. Delay V bit going high by one line relative to NVBEG (odd field). 0xE6 NTSC V Bit End 0 1 No delay Additional delay by 1 line 0 1 No delay Additional delay by 1 line NVEND[4:0]. How many lines after lCOUNT rollover to set V low. 0 0 1 0 0 NTSC default (BT.656) NVENDSIGN 0 Set to low when manual programming Not suitable for user programming 1 NVENDDELE. Delay V bit going low by one line relative to NVEND (even field). NVENDDELO. Delay V bit going low by one line relative to NVEND (odd field). 0xE7 NTSC F Bit Toggle 0 1 No delay Additional delay by 1 line 0 1 No delay Additional delay by 1 line NFTOG[4:0]. How many lines after lCOUNT rollover to toggle F signal. 0 0 0 1 1 NTSC default NFTOGSIGN 0 1 NFTOGDELE. Delay F transition by one line relative to NFTOG (even field). NFTOGDELO. Delay F transition by one line relative to NFTOG (odd field). Rev. A | Page 94 of 104 0 1 0 1 Set to low when manual programming Not suitable for user programming No delay Additional delay by 1 line No delay Additional delay by 1 line ADV7181 Table 206. Registers 0xE8 to 0xEA Bit Subaddress 0xE8 Register PAL V Bit Begin Bit Description PVBEG[4:0]. How many lines after lCOUNT rollover to set V high. 7 6 5 4 3 2 1 0 Comments 0 0 1 0 1 PAL default (BT.656) PVBEGSIGN 0 Set to low when manual programming Not suitable for user programming 1 PVBEGDELE. Delay V bit going high by one line relative to PVBEG (even field). PVBEGDELO. Delay V bit going high by one line relative to PVBEG (odd field). 0xE9 PAL V Bit End 0 1 No delay Additional delay by 1 line 0 1 No delay Additional delay by 1 line PVEND[4:0]. How many lines after lCOUNT rollover to set V low. 1 0 1 0 0 PAL default (BT.656) PVENDSIGN 0 Set to low when manual programming Not suitable for user programming 1 PVENDDELE. Delay V bit going low by one line relative to PVEND (even field). PVENDDELO. Delay V bit going low by one line relative to PVEND (odd field). 0xEA PAL F Bit Toggle 0 1 No delay Additional delay by 1 line 0 1 No delay Additional delay by 1 line PFTOG[4:0]. How many lines after lCOUNT rollover to toggle F signal. 0 0 0 1 1 PAL default (BT.656) PFTOGSIGN. 0 1 PFTOGDELE. Delay F transition by one line relative to PFTOG (even field). PFTOGDELO. Delay F transition by one line relative to PFTOG (odd field). Rev. A | Page 95 of 104 0 1 0 1 Set to low when manual programming Not suitable for user programming No delay Additional delay by 1 line No delay Additional delay by 1 line ADV7181 APPENDIX A I2C PROGRAMMING EXAMPLES Mode 1 CVBS Input (Composite Video on AIN6) All standards are supported through autodetect, 8-bit, 4:2:2, ITU-R BT.656 output on P15-P8. Table 207. Mode 1 CVBS Input Register Address 0x00 0x01 0x17 0x2B 0x3A 0x50 0x51 0xC3 0xC4 0xD2 0xD3 0xD8 0x0E Register Value 0x04 0x88 0x41 0xE2 0x16 0x04 0x24 0x05 0x80 0x01 0x01 0x9B 0x85 0x89 0x8D 0x8F 0xB5 0xD4 0xD6 0xE2 0xE3 0xE4 0xE8 0x0E 0x0D 0x9B 0x48 0x8B 0xFB 0x6D 0xAF 0x00 0xB5 0xF3 0x05 11 Notes CVBS input Turn off HSYNC processor (SECAM only11). Set CSFM to SH1. AGC flash tweak. Power down ADC 1 and ADC 2. Set DNR threshold. Turn off FSC detect for IN LOCK status. Man mux AIN6 to ADC0 (0101). Set setadc_sw_man_en = 1. AGC flash tweak. AGC flash tweak. AGC flash tweak. ADI recommended programming sequence. This sequence must be followed exactly when setting up the decoder. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. For all SECAM modes of operation, HSYNC PROCESSOR must be turned off. Rev. A | Page 96 of 104 ADV7181 Mode 2 S-Video Input (Y on AIN1 and C on AIN4) All standards are supported through autodetect, 8-bit, ITU-R BT.656 output on P15-P8. Table 208. Mode 2 S-Video Input Register Address 0x00 0x01 0x2B 0x3A 0x50 0x51 0xC3 0xC4 0xD2 0xD3 0xDB 0x0E Register Value 0x06 0x88 0xE2 0x12 0x04 0x24 0x41 0x80 0x01 0x01 0x9B 0x85 0xB5 0xD4 0xD6 0xE2 0xE3 0xE4 0xE8 0x0E 0x8B 0xFB 0x6D 0xAF 0x00 0xB5 0xF3 0x05 Notes S-Video input Turn off HSYNC processor (SECAM only12). AGC flash tweak. Power down ADC 2. Set DNR threshold. Turn off FSC detect for IN LOCK status. Man mux AIN2 to ADC0 (0001), AIN4 to ADC1 (0100). Set setadc_sw_man_en = 1. AGC flash tweak. AGC flash tweak. AGC flash tweak. ADI recommended programming sequence. This sequence must be followed exactly when setting up the decoder. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Mode 3 525i/625i YPrPb Input (Y on AIN1, Pr on AIN3, and Pb on AIN5) All standards are supported through autodetect, 8-bit, ITU-R BT.656 output on P15-P8. Table 209. Mode 3 YPrPb Input 525i/625i Register Address 0x00 0x01 0x2B 0x3A 0x51 0xC3 0xC4 0xD2 0xD3 0xDB 0x0E Register Value 0x0A 0x88 0xE2 0x10 0x24 0xC9 0x8D 0x01 0x01 0x9B 0x85 0xD6 0xE8 0x0E 0x6D 0xF3 0x05 12 13 Notes Y2 = AIN2, Pr2 = AIN3, Pb2 = AIN6. Disable HSync PLL13. AGC flash tweak. Set latch clock. Turn off FSC detect for IN LOCK status. Man mux AIN1 to ADC0 (1001), AIN3 to ADC1 (1100). Set setadc_sw_man_en = 1. AGC flash tweak. AGC flash tweak. AGC flash tweak. ADI recommended programming sequence. This sequence must be followed exactly when setting up the decoder. Recommended setting. Recommended setting. Recommended setting. For all SECAM modes of operation HSYNC PROCESSOR must be turned off For all YPrPb input modes of operation, HSYNC PROCESSOR must be turned off. Rev. A | Page 97 of 104 ADV7181 Mode 4 CVBS Tuner Input CVBS PAL on AIN6 8-bit, ITU-R BT.656 output on P15-P8. Table 210. Mode 4 Tuner Input CVBS PAL Only Register Address 0x07 0x17 0x2B 0x19 0x3A 0x50 0x51 0xC3 0xC4 0xD2 0xD3 0xDB 0x0E Register Value 0x01 0x41 0xE2 0xFA 0x16 0x0A 0x24 0x05 0x80 0x01 0x01 0x9B 0x85 0x89 0x8D 0x8F 0xB5 0xD4 0xD6 0xE2 0xE3 0xE4 0xE8 0x0E 0x0D 0x9B 0x48 0x8B 0xFB 0x6D 0xAF 0x00 0xB5 0xF3 0x05 Notes Enable PAL autodetection only. Set CSFM to SH1. AGC flash tweak. Stronger dot crawl reduction. Power down ADC 1 and ADC 2. Set higher DNR threshold. Turn off FSC detect for IN LOCK status. Man mux AIN6 to ADC0 (0101). Set setadc_sw_man_en = 1. AGC flash tweak. AGC flash tweak. AGC flash tweak. ADI recommended programming sequence. This sequence must be followed exactly when setting up the decoder. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Rev. A | Page 98 of 104 ADV7181 APPENDIX B The ADV7181 is a high precision, high speed mixed-signal device. To achieve the maximum performance from the part, it is important to have a well laid-out PCB board. The following is a guide for designing a board using the ADV7181. It is also recommend to use a single ground plane for the entire board. This ground plane should have a spacing gap between the analog and digital sections of the PCB (see Figure 38). ADV7181 Analog Interface Inputs ANALOG SECTION The inputs should receive care when being routed on the PCB. Track lengths should be kept to a minimum, and 75 trace impedances should be used when possible. Trace impedances other than 75 also increase the chance of reflections. Power Supply Decoupling It is recommended to decouple each power supply pin with 0.1 F and 10 nF capacitors. The fundamental idea is to have a decoupling capacitor within about 0.5 cm of each power pin. Also, avoid placing the capacitor on the opposite side of the PC board from the ADV7181, as doing so interposes resistive vias in the path. The decoupling capacitors should be located between the power plane and the power pin. Current should flow from the power plane to the capacitor to the power pin. Do not make the power connection between the capacitor and the power pin. Placing a via underneath the 100 nF capacitor pads, down to the power plane, is generally the best approach (see Figure 37). DIGITAL SECTION 04820-0-039 PCB LAYOUT RECOMMENDATIONS Figure 38. PCB Ground Layout Experience has repeatedly shown that the noise performance is the same or better with a single ground plane. Using multiple ground planes can be detrimental because each separate ground plane is smaller, and long ground loops can result. In some cases, using separate ground planes is unavoidable. For those cases, it is recommended to at least place a single ground plane under the ADV7181. The location of the split should be under the ADV7181. For this case, it is even more important to place components wisely because the current loops will be much longer (current takes the path of least resistance). An example of a current loop: power plane to ADV7181 to digital output trace to digital data receiver to digital ground plane to analog ground plane. PLL VDD VIA TO SUPPLY 10nF VIA TO GND 04819-0-038 GND Place the PLL loop filter components as close to the ELPF pin as possible. Do not place any digital or other high frequency traces near these components. Use the values suggested in the data sheet with tolerances of 10% or less. 100nF Digital Outputs (Both Data and Clocks) Figure 37. Recommend Power Supply Decoupling It is particularly important to maintain low noise and good stability of PVDD. Careful attention must be paid to regulation, filtering, and decoupling. It is highly desirable to provide separate regulated supplies for each of the analog circuitry groups (AVDD, DVDD, DVDDIO, and PVDD). Some graphic controllers use substantially different levels of power when active (during active picture time) and when idle (during horizontal and vertical sync periods). This can result in a measurable change in the voltage supplied to the analog supply regulator, which can, in turn, produce changes in the regulated analog supply voltage. This can be mitigated by regulating the analog supply, or at least PVDD, from a different, cleaner, power source (for example, from a 12 V supply). Try to minimize the trace length that the digital outputs have to drive. Longer traces have higher capacitance, which requires more current, which causes more internal digital noise. Shorter traces reduce the possibility of reflections. Adding a series resistor of a value between 30 and 50 can suppress reflections, reduce EMI, and reduce the current spikes inside the ADV7181. If series resistors are used, place them as close to the ADV7181 pins as possible. However, try not to add vias or extra length to the output trace to get the resistors closer. If possible, limit the capacitance that each of the digital outputs drives to less than 15 pF. This can easily be accomplished by keeping traces short and by connecting the outputs to only one device. Loading the outputs with excessive capacitance increases the current transients inside the ADV7181, creating more digital noise on its power supplies. Rev. A | Page 99 of 104 ADV7181 Digital Inputs The digital inputs on the ADV7181 were designed to work with 3.3 V signals, and are not tolerant of 5 V signals. Extra components are needed if 5 V logic signals are required to be applied to the decoder. It is essential that the cutoff of this filter be less than 1 Hz to ensure correct operation of the internal clamps within the part. These clamps ensure that the video stays within the 5 V range of the op amp used. Antialiasing Filters 0 The buffer is a simple emitter-follower using a single npn transistor. The antialiasing filter is implemented using passive components. The passive filter is a third-order Butterworth filter with a -3dB point of 9MHz. The frequency response of the passive filter is shown in Figure 39. The flat pass band up to 6 MHz is essential. The attenuation of the signal at the output of the filter due to the voltage divider of R24 and R63 is compensated for in the ADV7181 part using the automatic gain control. The ac coupling capacitor at the input to the buffer creates a high-pass filter with the biasing resistors for the transistor. This filter has a cut-off of: {2 x x (R39||R89) x C93}-1 = 0.62 Hz Rev. A | Page 100 of 104 -20 -40 -60 -80 -100 04819-0-040 For inputs from some video sources that are not bandwidth limited, signals outside the video band can alias back into the video band during A/D conversion and appear as noise on the output video. The ADV7181 oversamples the analog inputs by a factor of 4. This 54 MHz sampling frequency reduces the requirement for an input filter; for optimal performance it is recommended that an antialiasing filter be employed. The recommended low cost circuit for implementing this buffer and filter circuit for all analog input signals is shown in Figure 40. -120 100kHz 300kHz 1MHz 3MHz 10MHz 30MHz 100MHz 300MHz FREQUENCY Figure 39. Third-Order Butterworth Filter Response 1GHz ADV7181 APPENDIX C TYPICAL CIRCUIT CONNECTION Examples of how to connect the ADV7181 video decoder are shown in Figure 40 and Figure 41. AVDD_5V BUFFER R39 4.7k R38 75 R53 56 R89 5.6k C B IN Q6 E FILTER L10 12H OUT R24 470 C95 22pF AGND C102 10pF R63 820 04819-0-041 C93 100F R43 0 Figure 40. ADI Recommended Antialiasing Circuit for All Input Channels Rev. A | Page 101 of 104 ADV7181 FERITE BEAD DVDDIO (3.3V) 33F 10F 0.1F DGND DGND FERITE BEAD PVDD (1.8V) 33F DGND 10F 0.1F AGND AGND FERITE BEAD AVDD (3.3V) 33F AGND 10F 0.1F AGND AGND FERITE BEAD 10F DGND DVDD 100nF S-VIDEO DGND AIN2 100nF DVDDIO DGND 0.1F AVDD 33F PVDD DVDD (1.8V) AGND DGND AGND AIN1 Y 100nF Pr AIN3 Pb ADV7181 100nF AIN4 100nF AIN5 100nF CBVS 0.01F POWER SUPPLY DECOUPLING FOR EACH POWER PIN DGND 0.01F POWER SUPPLY DECOUPLING FOR EACH POWER PIN AGND 0.01F POWER SUPPLY DECOUPLING FOR EACH POWER PIN AGND 0.01F POWER SUPPLY DECOUPLING FOR EACH POWER PIN DGND P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 MULTI FORMAT PIXEL PORT P15-P8 8-BIT ITU-R BT.656 PIXEL DATA @ 27MHz P7-P0 Cb AND Cr 16-BIT ITU-R BT.656 PIXEL DATA @ 13.5MHz P15-P8 Y1 AND Y2 16-BIT ITU-R BT.656 PIXEL DATA @ 13.5MHz AIN6 75 75 75 75 75 75 AGND 0.1F + CAP Y1 10F 0.1F 0.1nF LLC CAP Y2 27MHz OUTPUT CLOCK 0.1F AGND + 10F 0.1F 0.1nF CAP C2 AGND CML 10F 0.1F REFOUT + 10F 0.1F AGND XTAL 33pF 27MHz DVDDIO SELECT I2C ADDRESS XTAL1 DGND SFL SFL O/P HS HS O/P VS VS O/P FIELD FIELD O/P 33pF DVDDIO DGND PWRDN ALSB DVSS DVDDIO 2k ELPF DVDDIO 2k 1.7k 10nF 82nF 33 SCLK MPU INTERFACE CONTROL LINES 33 PVDD SDA DVDDIO 4.7k RESET RESET AGND DGND AGND DGND 100nF DGND Figure 41. Typical Connection Diagram Rev. A | Page 102 of 104 04820-0-042 + ADV7181 OUTLINE DIMENSIONS 9.00 BSC SQ 0.60 MAX 0.60 MAX 49 48 PIN 1 INDICATOR TOP VIEW 0.30 0.25 0.18 PIN 1 INDICATOR 64 8.75 BSC SQ 1 7.25 7.10 SQ* 6.95 BOTTOM VIEW 0.45 0.40 0.35 33 32 17 16 0.25 MIN 7.50 REF 1.00 0.85 0.80 0.80 MAX 0.65 TYP 12 MAX 0.05 MAX 0.02 NOM 0.50 BSC SEATING PLANE 0.20 REF * COMPLIANT TO JEDEC STANDARDS MO-220-VMMD EXCEPT FOR EXPOSED PAD DIMENSION Figure 42. 64-Lead Lead Frame Chip Scale Package [LFCSP] 9 mm x 9 mm Body (CP-64-3) Dimensions shown in millimeters 0.75 0.60 0.45 12.00 BSC SQ 1.60 MAX 64 49 1 48 SEATING PLANE PIN 1 10.00 BSC SQ TOP VIEW (PINS DOWN) 10 6 2 1.45 1.40 1.35 0.15 0.05 SEATING PLANE 0.20 0.09 7 3.5 0 0.08 MAX COPLANARITY VIEW A 16 33 32 17 0.50 BSC VIEW A ROTATED 90 CCW COMPLIANT TO JEDEC STANDARDS MS-026BCD Figure 43. 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-2) Dimensions shown in Millimeters Rev. A | Page 103 of 104 0.27 0.22 0.17 ADV7181 ORDERING GUIDE Model ADV7181BCP ADV7181BST EVAL-ADV7181EBM Temperature Range -40C to +85C -40C to +85C Package Description Lead Frame Chip Scale Package (LFCSP) Low Profile Quad Flat Package (LQFP) Evaluation Board Package Option CP-64-3 ST-64-2 Note: The ADV7181 is a Pb-free environmentally friendly product. It is manufactured using the most up-to-date materials and processes. The coating on the leads of each device is 100% pure Sn electroplate. The device is suitable for Pb-free applications, and can withstand surface-mount soldering at up to 255C (5C). In addition, it is backward-compatible with conventional SnPb soldering processes. This means the electroplated Sn coating can be soldered with Sn/Pb solder pastes at conventional reflow temperatures of 220C to 235C. Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. (c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04820-0-7/04(A) Rev. A | Page 104 of 104