Wide Bandwidth, Low Noise, Vibration Sensor ADcmXL1021-1 Data Sheet FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Vibration analysis Condition-based monitoring (CbM) systems Machine health Instrumentation and diagnostics Safety shutoff sensing Rev. 0 VDD GND OUT_VDDM POWER MANAGEMENT ADC CS SCLK DIN DOUT SYNC/RTS BUSY ALM1 ALM2 ADcmXL1021-1 Figure 1. GENERAL DESCRIPTION The ADcmXL1021-1 is a complete vibration sensing system that combines high performance vibration sensing (using a microelectromechanical systems (MEMS) accelerometer) with a variety of signal processing functions to simplify the development of smart sensor nodes in condition-based monitoring (CBM) systems. The typical ultralow noise density (26 g/Hz) in the MEMS accelerometers supports excellent resolution. The wide bandwidth (dc to 10 kHz within 3 dB flatness) enables tracking of key vibration signatures on many machine platforms. The signal processing includes high speed data sampling (220 kSPS), 4096 time sample record lengths, filtering, windowing, fast Fourier transform (FFT), user configurable spectral or time statistic alarms, and error flags. The serial peripheral interface (SPI) provides access to a register structure that contains the vibration data and a wide range of user configurable functions. The ADcmXL1021-1 is available in a 23.7 mm x 27.0 mm x 12.4 mm aluminum package with four mounting flanges to support installation with standard machine screws. This light weight package (13 g) provides consistent mechanical coupling to the core sensors over a broad frequency range. The electrical interface is through a 14-lead connector on a 36 mm flexible cable, which enables a wide range of location and orientation options for system mating connectors. The ADcmXL1021-1 requires only a single, 3.3 V power supply and supports an operating temperature range of -40C to +105C. Multifunction pin names may be referenced by their relevant function only. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 21125-001 MEMS ACCELEROMETER RST INTERFACE Single axis, digital output MEMS vibration sensing module 50 g measurement range Ultralow output noise density, 26 g/Hz (MTC mode) Wide bandwidth: dc to 10 kHz within 3 dB flatness (RTS mode) Embedded fast data conversion rate: 220 kSPS 6 digital FIR filters, 32 taps (coefficients), default options High-pass filter cutoff frequencies: 1 kHz, 5 kHz, 10 kHz Low-pass filter cutoff frequencies: 1 kHz, 5 kHz, 10 kHz User configurable digital filter option (32 coefficients) Spectral analysis through internal FFT Extended record length: 2048 bins with user configurable bin sizes from 0.42 Hz to 53.7 Hz Manual or timer-based (automatic) triggering Windowing options: rectangular, Hanning, flat top FFT record averaging, configurable up to 255 records Spectral defined alarm monitoring, 6 alarms Time domain capture with statistical metrics Extended record length: 4096 samples Mean, standard deviation, peak, crest factor, skewness, and Kurtosis Configurable alarm monitoring Real-time data streaming at 220 kSPS Burst mode communication with CRC-16 error checking Storage: 10 data records On demand self test with status flags Sleep mode with external and timer driven wakeup Digital temperature and power supply measurements SPI-compatible serial interface Identification registers: factory preprogrammed serial number, device ID, user programmable ID Single-supply operation: 3.0 V to 3.6 V Operating temperature range: -40C to +105C Automatic shutdown at 125C (junction temperature) 23.7 mm x 27.0 mm x 12.4 mm aluminum package 36 mm flexible, 14-lead module with integrated flexible connector Mass: 13 g EMBEDDED PROCESSING FEATURES ADcmXL1021-1 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 REC_CTRL, Recording Control .............................................. 31 Applications ....................................................................................... 1 REC_PRD, Record Period ......................................................... 32 Functional Block Diagram .............................................................. 1 ALM_F_LOW, Alarm Frequency Band .................................. 33 General Description ......................................................................... 1 ALM_F_HIGH, Alarm Frequency Band ................................ 33 Revision History ............................................................................... 2 ALM_MAG1, Alarm Level 1 .................................................... 33 Specifications..................................................................................... 3 ALM_MAG2, Alarm Level 2 .................................................... 33 Timing Specifications .................................................................. 4 ALM_PNTR, Alarm Pointer..................................................... 34 Absolute Maximum Ratings ............................................................ 6 ALM_S_MAG Alarm Level ...................................................... 34 Thermal Resistance ...................................................................... 6 ALM_CTRL, Alarm Conrol ..................................................... 34 ESD Caution .................................................................................. 6 FILT_CTRL, Filter Control ....................................................... 34 Pin Configuration and Function Descriptions ............................. 7 AVG_CNT, Decimation Control.............................................. 35 Typical Performance Characteristics ............................................. 8 DIAG_STAT, Status, and Error Flags....................................... 35 Theory of Operation ...................................................................... 11 GLOB_CMD, Global Commands ............................................ 36 Core Sensors ................................................................................ 11 ALM_STAT, Alarm Status ......................................................... 36 Signal Processsing....................................................................... 11 ALM_PEAK, Alarm Peak Level ............................................... 36 Modes of Operation ................................................................... 12 Data Recording Options ............................................................ 13 TIME_STAMP_L and TIME_STAMP_H, Data Record Timestamp................................................................................... 36 User Interface .............................................................................. 16 DAY_REV, Day and Revision ................................................... 37 Basic Operation............................................................................... 19 YEAR_MON, Year and Month................................................. 37 Device Configuration ................................................................ 19 PROD_ID, Product Identification ........................................... 37 Dual Memory Structure ............................................................ 19 SERIAL_NUM, Serial Number ................................................ 37 Power-Up Sequence ................................................................... 19 USER_SCRATCH ...................................................................... 37 Trigger .......................................................................................... 19 REC_FLASH_CNT, Record Flash Endurance ....................... 37 Sample Rate ................................................................................. 20 MISC_CTRL, Miscellaneous Control ..................................... 37 Datapath Processing ................................................................... 20 REC_INFO1, Record Information........................................... 38 Spectral Alarms........................................................................... 22 REC_INFO2, Record Information,.......................................... 38 Mechanical Mounting Recommendations .............................. 22 REC_CNTR, Record Counter .................................................. 38 User Register Memory Map .......................................................... 23 ALM_FREQ, Severe Alarm Frequency ................................... 38 User Register Details ...................................................................... 28 STAT_PNTR, Statistic Result Pointer ...................................... 38 PAGE_ID, Page Number ........................................................... 28 STATISTIC, Statistic Result ...................................................... 39 TEMP_OUT, Internal Temperature ......................................... 28 FUND_FREQ, Fundamental Frequency ................................. 39 SUPPLY_OUT, Power Supply Voltage ..................................... 28 FLASH_CNT_L, Flash Memory Endurance ......................... 39 FFT_AVG1, Spectral Averaging ............................................... 28 FLASH_CNT_U, Flash Memory Endurance ......................... 39 FFT_AVG2, Spectral Averaging ............................................... 29 FIR Filter Registers ..................................................................... 40 BUF_PNTR, Buffer Pointer ...................................................... 29 Applications Information .............................................................. 41 REC_PNTR, Record Pointer ..................................................... 30 Mechanical Interface .................................................................. 41 OUT_BUF, Buffer Access Register ........................................... 30 Outline Dimensions ....................................................................... 42 ANULL, Bias Calibration Register ........................................... 31 Ordering Guide .......................................................................... 42 REVISION HISTORY 11/2019--Revision 0: Initial Version Rev. 0 | Page 2 of 42 Data Sheet ADcmXL1021-1 SPECIFICATIONS TA = 25C and VDD = 3.3 V, unless otherwise noted. Table 1. Parameter ACCELEROMETERS Measurement Range 1 Sensitivity FFT Time Domain Error over Temperature Nonlinearity Cross Axis Sensitivity Alignment Error Offset Error Over Temperature Offset Temperature Coefficient Output Noise Output Noise Density 3 dB Bandwidth Sensor Resonant Frequency CONVERSION RATE Clock Accuracy FUNCTIONAL TIMING Factory Reset Time Recovery Start-Up Time Self Test Time LOGIC INPUTS Input High Voltage, VIH Input Low Voltage, VIL Logic 1 Input Current, IIH Logic 0 Input Current, IIL All Except RST RST Input Capacitance, CIN DIGITAL OUTPUTS Output Voltage High, VOH Low, VOL Output Current High, IOH Low, IOL FLASH MEMORY Endurance 2 Data Retention 3 THERMAL SHUTDOWN Threshold Hysteresis OUT_VDDM MONITOR OUTPUT Output Resistance Test Conditions/Comments Min Best fit, straight line, full scale (FS) = 50 g With respect to package TA = -40C to +105C TA = -40C to +105C Real-time streaming (RTS) mode 100 Hz to 10 kHz, AVG_CNT = 0, MTC mode 1 Hz to 10 kHz, no filtering, RTS mode Typ Max 50 g 0.9535 1.907 5 0.2 2 2 5 34 3.2 26 32 3 mg/LSB mg/LSB % % % Degrees g mg/C mg rms g/Hz g/Hz Hz kHz kSPS % 126 205 ms ms 92 ms 1.25 10,000 21 220 Time from supply voltage reaching 3.0 V from power-down until ready for command 2.5 VIH = 3.3 V VIL = 0 V 0.01 0.45 0.2 100 1 10 IOH = -1 mA IOL = 1 mA Unit 1.4 IOH = -1 mA IOL = 1 mA V V A A mA pF 0.4 V V 2 2 mA mA TJ = 85C, see Figure 44 10,000 10 Cycles Years TJ rising 125 15 C C Logic output, logic high indicates good condition Logic low when internal temperature exceeds allowed range Rev. 0 | Page 3 of 42 90 100 110 k ADcmXL1021-1 Data Sheet Parameter POWER SUPPLY VOLTAGE Power Supply Current 1 2 3 Test Conditions/Comments Operating voltage range, VDD Operating mode, VDD = 3.0 V Operating mode, VDD = 3.3 V Operating mode, VDD = 3.6 V Sleep mode, VDD = 3.0 V Sleep mode, VDD = 3.3 V Sleep mode, VDD = 3.6 V Min 3.0 Typ 3.3 22.9 23.2 23.9 0.1 0.6 1.5 Max 3.6 Unit V mA mA mA mA mA mA The maximum range depends on the frequency of the vibration. Endurance is qualified as per JEDEC Standard 22, Method A117 and measured at -40C, +25C, +85C, and +125C. Retention lifetime equivalent at junction temperature (TJ) = 85C as per JEDEC Standard 22, Method A117. Retention lifetime depends on TJ. TIMING SPECIFICATIONS TC = 25C and VDD = 3.3 V, unless otherwise noted. Table 2. Parameter fSCLK tSTALL tCLS tCHS tCS Description SCLK frequency Stall period between data bytes SCLK low period SCLK high period CS to SCLK edge tDAV tDSU tDHD tDSOE tHD tSFS DOUT valid after SCLK edge DIN setup time before SCLK rising edge DIN hold time after SCLK rising edge CS assertion to DOUT active SCLK edge to DOUT invalid Last SCLK edge to CS deassertion tRTS_BUSY RTS mode only, data out valid burst readout period ends before BUSY rising edge for next burst 1 2 Min 1 0.01 16 35.7 35.7 35.7 Normal Mode Typ Max1 14 RTS Mode Typ Min 8 Max1 14 Unit MHz s ns ns ns 20 35.7 ns ns ns ns ns ns 12 s N/A 2 35.7 35.7 35.7 20 6 8 20 20 35.7 N/A2 6 8 0 20 20 Guaranteed by design and characterization, but not tested in production. N/A means not applicable. When using real-time streaming (RTS), the stall period is not applicable. Timing Diagrams CS tCLS tCHS tCS 1 2 3 4 5 tSFS 6 15 16 SCLK DOUT MSB tHD tDAV DB14 DB13 tDSU DIN R/W A6 DB12 DB11 DB10 A4 A3 A2 DB2 DB1 LSB tDHD A5 Figure 2. SPI Timing and Sequence Rev. 0 | Page 4 of 42 D2 D1 LSB 21125-002 tDSOE Data Sheet ADcmXL1021-1 tSTALL 21125-003 CS SCLK Figure 3. Stall Time (Does Not Apply to RTS Mode) 12ms DELAY TRIGGER CAPTURE START BY WRITING 0x0800 TO GLOB_CMD REAL-TIME STREAMING FRAME (16 x 44 BITS) HEADER 8 0x0000 WORDS, XL1:XL32, TEMP, STATUS, CRC CS SCLK DON'T CARE DIN 8 0x0000 WORDS DOUT DON'T CARE 0x00, 0xAD XL1[LSB, MSB] 21125-004 BUSY NOTES 1. XLx IS ACCELEROMETER DATA; TEMP IS TEMPERATURE DATA. Figure 4. RTS Mode Timing Diagram, Assumes REC_CTRL, Bits[1:0] = 0b11 (See Table 17) NOT SHOWN ARE 31 16-BIT WORDS: XL3 TO XL32 TEMPERATURE CS CRC STATUS XL2 XL1 0xAD04 8 0x0000 WORDS CRC STATUS XL2 XL1 0xAD03 8 0x0000 WORDS CRC STATUS XL2 XL1 0xAD02 8 0x0000 WORDS CRC STATUS XL2 XL1 0xAD01 8 0x0000 WORDS CRC STATUS XL2 XL1 0xAD00 DOUT 8 0x0000 WORDS SCLK tRTS_BUSY NOTES 1. XLx IS ACCELEROMETER DATA. Figure 5. RTS Read Function Sequence Diagram, First Five Segments (See Table 17) Rev. 0 | Page 5 of 42 21125-005 BUSY ADcmXL1021-1 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 3. Parameter Acceleration Unpowered Powered VDD to GND Digital Input Voltage to GND Digital Output Voltage to GND Temperature Range Operating Temperature Storage Temperature Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Pay careful attention to PCB thermal design. Rating 2000 g 2000 g -0.3 V to +3.6 V -0.3 V to +3.6 V -0.3 V to +3.6 V JA is the natural convection, junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. JC is the junction to case thermal resistance. -40C to +105C -65C to +150C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. The ADcmXL1021-1 is a multichip module that includes many active components. The values in Table 4 identify the thermal response of the hottest component inside of the ADcmXL1021-1 with respect to the overall power dissipation of the module. This approach enables a simple method for predicting the temperature of the hottest junction based on either ambient or case temperature. For example, when TA = 70C, under normal operation mode with a typical 23.2 mA current and 3.3 V supply voltage, the hottest junction temperature in the ADcmXL1021-1 is 75.0C. TJ = JA x VDD x IDD + 70C TJ = 65.1C/W x 3.3 V x 0.0232 A + 70C TJ 75.0C where IDD is the current consumption of the device. Table 4. Thermal Resistance Package Type ML-14-71 1 JA 65.1C/W JC 33.2C/W Thermal impedance simulated values come from a case with four machine screws at a size of M2.5 x 0.4 mm (torque = 25 inch pounds). Secure the ADcmXL1021-1 to the PCB. ESD CAUTION Rev. 0 | Page 6 of 42 Data Sheet ADcmXL1021-1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 13 2 14 Z PIN 1 PIN 13 X 21125-007 Y PIN 14 Figure 6. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 Mnemonic GND ALM1 Type Supply Output 3 SYNC/RTS Input 4 ALM2 Output 5 BUSY Output 6 OUT_VDDM Output 7 RST Input 8 9 10 11 12 VDD GND GND DIN DOUT Supply Supply Supply Input Output 13 14 SCLK CS Input Input Description Ground. Digital Output Only, Alarm 1 Output. This pin is configured by the ALM_CTRL register and is not used in RTS mode. Sync Function (SYNC)/RTS Burst Start/Stop (RTS). This pin is a digital input only and is edge (not level) sensitive. This pin must be enabled in the MISC_CTRL register (Bit 12) before being used as an external trigger. The SYNC pulse width must be at least 50 ns. In MTC and MFFT modes, the SYNC pin acts as a manual trigger, this pin initiates a record capture event when a low to high transition is detected, equivalent to SPI Command 0x0800 to the GLOB_CMD register. In RTS and AFFT mode, when the logic level on this pin is high, conversion is active. When the logic level on this pin is low, conversion is stopped after the current data record is completed. Digital Output Only, Alarm 2 Output. This pin is configured by the ALM_CTRL register and is not used in RTS mode. Busy or Data Ready Indicator, Digital Output Only. In RTS mode, this pin is a logical output to indicate that data is ready and available for download. The logical state resets to logic low when data is loading to the output buffers. The pin is set high when data is ready for download. In other capture modes, the busy indicator identifies the state of the module processor and if it is available for external commands. When a command is executing, SPI access is not allowed, and the device is in a busy state. After this process completes, whether a command or a record, the SPI is released, and the BUSY pin is set to logic high state. Note that there is one exception to SPI port access while in the busy state, a capture can be terminated by writing the unique 16-bit escape code, 0x00E8, to the GLOB_CMD register. Power Supply Monitor (Digital Output). This pin is logic low when temperature exceeds threshold and automatic shutdown occurs. Hardware Reset, Digital Input Only, Active Low. This pin enters the device in a known state by resetting the microcontroller. This pin also loads the user configurable parameters from flash memory. Power Supply. Ground. Ground. SPI, Data Input Line. SPI, Data Output. DOUT is an output when CS is low. When CS is high, DOUT is in a three-state, high impedance mode. SPI, Serial Clock. SPI, Chip Select. Rev. 0 | Page 7 of 42 ADcmXL1021-1 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1000 NOISE DENSITY (g/Hz) 10 1 100 1k 10k 100k 1M FREQUENCY (Hz) 100 10 1 1 Figure 7. Noise Density, Wideband, MTC, AVG_CNT = 0 100 Figure 10. Noise Density, Low Frequency, RTS Mode 25 3 SENSITIVITY ERROR (% Full-Scale) AMBIENT TEMPERATURE (C) 21125-208 90 80 70 60 50 40 100 FREQUENCY (Hz) 30 -3 20 10k 0 1k -2 -50 -10 100 21125-205 -5 -1 10 0 0 -10 5 1 -20 10 -30 15 2 -40 20 RELATIVE RESPONSE (dB) 10 FREQUENCY (Hz) 21125-207 100 21125-202 NOISE DENSITY (g/Hz) 1000 Figure 11. Sensitivity Error vs. Ambient Temperature, Normalized at 25C Figure 8. Relative Response, RTS Mode at 25C 1000 14 12 10 NORMALIZED OFFSET (g) 100 10 6 4 2 0 -2 -4 -6 -8 -10 -12 1 100 90 80 21125-209 AMBIENT TEMPERATURE (C) Figure 9. Noise Density, Wideband, RTS Mode 70 60 50 40 30 20 10 0 -14 -10 FREQUENCY (Hz) 1M -20 100k -30 10k -40 1k -50 100 21125-206 NOISE DENSITY (g/Hz) 8 Figure 12. Normalized Offset vs. Ambient Temperature, Normalized at 25C Rev. 0 | Page 8 of 42 ADcmXL1021-1 35 30 30 25 25 MORE 21125-213 0.20 0.18 0.16 0.14 0.12 CURRENT (mA) Figure 16. Sleep Mode Current Distribution at 3.0 V Supply 25 60 50 20 40 FREQUENCY (%) 30 20 15 10 5 10 MORE CURRENT (mA) Figure 14. Operating Mode Current Distribution at 3.3 V Supply 21125-214 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 21125-211 MORE 24.0 23.8 23.6 23.4 23.2 23.0 22.8 22.6 22.4 22.2 22.0 CURRENT (mA) 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 0 0 Figure 17. Sleep Mode Current Distribution at 3.3 V Supply 30 35 25 30 25 FREQUENCY (%) 20 15 10 20 15 10 5 5 MORE 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.0 CURRENT (mA) Figure 15. Operating Mode Current Distribution at 3.6 V Supply Figure 18. Sleep Mode Current Distribution at 3.6 V Supply Rev. 0 | Page 9 of 42 21125-215 CURRENT (mA) 0 21125-212 23.0 23.1 23.2 23.3 23.4 23.5 23.6 23.7 23.8 23.9 24.0 24.1 24.2 24.3 24.4 24.5 24.6 24.7 24.8 24.9 MORE 0 1.1 FREQUENCY (%) 0.10 0.02 MORE CURRENT (mA) 21125-210 23.5 23.4 23.3 23.2 23.1 0 23.0 0 22.9 5 22.8 5 22.7 10 22.6 10 Figure 13. Operating Mode Current Distribution at 3.0 V Supply FREQUENCY (%) 15 0.08 15 20 0.06 20 0.04 FREQUENCY (%) 35 22.5 FREQUENCY (%) Data Sheet ADcmXL1021-1 Data Sheet 0 0 -10 -20 -10 MAGNITUDE (dB) MAGNITUDE (dB) -30 -40 -50 -60 -20 -30 -70 -40 -80 10 20 30 40 50 60 70 FREQUENCY (kHz) 80 90 100 110 -50 21125-115 0 0 Figure 19. Digital Filter Frequency Response of the 1 kHz Low-Pass Filter 10 20 30 40 50 60 70 FREQUENCY (kHz) 80 90 100 110 21125-118 -90 -100 Figure 22. Digital Filter Frequency Response of the 1 kHz High-Pass Filter 0 0 -10 -20 -10 MAGNITUDE (dB) MAGNITUDE (dB) -30 -40 -50 -60 -20 -30 -70 -80 -40 0 10 20 30 40 50 60 70 FREQUENCY (kHz) 80 90 100 110 -50 21125-116 -100 0 Figure 20. Digital Filter Frequency Response of the 5 kHz Low-Pass Filter 10 20 30 40 50 60 70 FREQUENCY (kHz) 80 90 100 110 21125-119 -90 Figure 23. Digital Filter Frequency Response of the 5 kHz High-Pass Filter 0 0 -10 -20 -10 MAGNITUDE (dB) MAGNITUDE (dB) -30 -40 -50 -60 -20 -30 -70 -80 -40 0 10 20 30 40 50 60 70 FREQUENCY (kHz) 80 90 100 110 -50 21125-117 -100 0 Figure 21. Digital Filter Frequency Response of the 10 kHz Low-Pass Filter 10 20 30 40 50 60 70 FREQUENCY (kHz) 80 90 100 110 21125-120 -90 Figure 24. Digital Filter Frequency Response of the 10 kHz High-Pass Filter Rev. 0 | Page 10 of 42 Data Sheet ADcmXL1021-1 THEORY OF OPERATION The ADcmXL1021-1 is a single axis, vibration monitoring subsystem that includes a wide bandwidth, low noise MEMS accelerometer, an analog-to-digital converter (ADC), high performance signal processing, data buffers, record storage, and a user interface that easily interfaces with most embedded processors. See Figure 25 for a basic signal chain. The subsystem is housed in an aluminum module that is mounted using four screws (accepts screw size M2.5) and is designed to be mechanically stable beyond 40 kHz. The combination of this mechanical mounting and oversampling ensures that aliasing artifacts are minimized. USER INTERFACE BUFFER/RECORDS ANCHOR Figure 25. Basic Signal Chain The ADcmXL1021-1 has a high operating input range of 50 g and is suitable for vibration measurements in high bandwidth applications, such as vibration analysis systems that monitor and diagnose machine or system health. User configurable internal processing supports both time domain and frequency domain calculations. The low noise and high frequency bandwidth enable the measurement of both repetitive vibration patterns and single shock events caused by small moving parts, such as internal bearings. The high g range provides the dynamic range used in high vibration environments, such as heating, ventilation, and air conditioning systems (HVAC), and heavy machine equipment. To achieve best performance, be aware of system noise, mounting, and signal conditioning for the particular application. Proper mounting is required to ensure full mechanical transfer of vibration to accurately measure the desired vibration. A common technique for high frequency mechanical coupling is to use a combination of a threaded screw mount system and adhesive where possible. For lower frequencies (below the full capable bandwidth of the sensor), it is possible to use magnetic or adhesive mounting. Proper mounting techniques ensure accurate and repeatable results that are not influenced by measurement system mechanical resonances and/or damping at the desired frequencies and represents an efficient and proper mechanical transfer to the system being monitored. CORE SENSORS The ADcmXL1021-1 uses one ADXL1002 MEMS accelerometer, with the sensing axis aligned with the axis of interest. Figure 26 is a simple mechanical diagram that shows how MEMS accelerometers translate linear acceleration to representative output signals. MOVABLE FRAME PLATE CAPACITORS FIXED PLATES UNIT SENSING CELL UNIT FORCING CELL MOVING PLATE ANCHOR 21125-010 SIGNAL PROCESSING ACCELERATION ADC Deflection of the structure is measured using differential capacitors that consist of independent fixed plates and plates attached to the moving mass. Acceleration deflects the structure and unbalances the differential capacitor, resulting in a sensor output with an amplitude proportional to acceleration. Phase sensitive demodulation determines the magnitude and polarity of the acceleration. 21125-009 MEMS SENSOR The moving component of the sensor is a polysilicon surfacemicromachined structure built on top of a silicon wafer. Polysilicon springs suspend the structure over the surface of the wafer and provide a resistance against acceleration forces. Figure 26. MEMS Sensor Diagram SIGNAL PROCESSSING The signal chain of the ADcmXL1021-1 includes a wideband accelerometer, a low-pass analog filter with a 13.5 kHz cutoff frequency, an oversampling ADC (sampling at 220 kSPS), a microcontroller, and discrete components to provide a flexible vibration monitor subsystem that supports multiple processed output modes. There are four modes of operation. One mode of operation is the full rate RTS output. The three other modes include system level signal processing: manual FFT mode (MFFT), automatic FFT mode (AFFT), and manual time capture (MTC) mode MTC mode supports 4096 consecutive time domain samples to which averaging, finite impulse response (FIR), and windowing signal processing can be enabled, along with the calculation of statistics, alarm configuring, and monitoring. In MTC mode, the raw time domain data is made available in register buffers for the user to access and externally process. In both FFT modes, MFFT and AFFT modes support the process of calculating an FFT of the current time domain record. A continuous RTS mode bypasses all device digital computations and alarm monitoring, outputting real-time data over the SPI in burst data output format (see Figure 5). Rev. 0 | Page 11 of 42 ADcmXL1021-1 Data Sheet The ADcmXL1021-1 supports four different modes of operation: RTS, MTC, MFFT, and AFFT. Users can select the mode of operation by writing the corresponding code to the REC_CTRL register, Bits[1:0] (see Table 47). In three of these modes (MFFT, AFFT, and MTC), the ADcmXL1021-1 captures, analyzes, and stores vibration data in discrete events, known as capture events, and generates a record. Each capture event concludes with storing the data as configured in REC_CTRL register in the user data buffers, which are accessible through the BUF_PNTR register (see Table 35). The two different FFT modes that produce vibration data in spectral terms are MFFT and AFFT. The difference between these two modes is the manner in which data capture and analysis starts. In MFFT mode, users trigger a capture event by an external digital signal or through a software command using the GLOB_ CMD register, Bit 11 (see Table 73). In AFFT mode, an internal timer automatically triggers additional spectral record captures without the need for an external trigger. Up to four different sample rate profiles can be selected for the modes to cycle through. The REC_PRD register (see Table 49) contains the user configuration settings for the time that elapses between each capture event when operating in the AFFT mode. MTC Mode When operating in MTC mode, the ADcmXL1021-1 captures 4096 consecutive time domain samples. An offset null signal can be calculated and applied to the data using the command register option. Signal processing functions such as low-pass and high-pass FIR filtering and averaging can be applied. After ADC fS = 220kSPS DECIMATION FILTER fS / D FIR FILTER 32 TAPS REGISTERS: FILT_CTRL FIR_COEFF_xxx REGISTER: AVG_CNT Capturing is triggered by either a SPI write to the GLOB_CMD register or by an external trigger. The ADcmXL1021-1 toggles the output BUSY when the data record is stored and the alarms are checked. The decimation filter reduces the effective rate of stored data capture in the time record by averaging the sequential samples together and filtering out of band signal and noise. This filter has eight decimation rate settings (1, 2, 4, 8, 16, 32, 64, and 128) and can support up to four different settings. These time data records are time continuous captures with the decimation filter acting on real-time data from the ADC to produce 4096 samples (producing the 4096 time domain samples requires 2N samples to be processed internally, where N is the average count value, AVG_ CNT). When more than one user configured sample record setting is in use, the ADcmXL1021-1 applies a single filter for each data record and cycles through all desired options, one for each data capture. Time statistic alarms can be configured for three levels of reporting: normal, critical, and warning. A record mode option allows all enabled time domain statistics to be stored, depending on user preference, and is configured by setting the record mode in Register REC_CTRL, Bits[3:2] (Register 0x1A and Register 0x1B) = 0b10. DECIMATION FILTER TIME RECORD N = 4096 CALCULATE STATUS/ CHECK ALARMS DATA BUFFER Figure 27. Signal Processing Diagram for Manual Time Capture (MTC) Mode USER DATA BUFFER N = 4096 REGISTERS: OUT_BUF NULL REGISTERS: ANULL GLOB_CMD STATISTICAL ANALYSIS/ STATS ALARM CHECK STAT HEADER REGISTERS: STAT STAT_PNTR 21125-025 MEMS SENSOR digital processing is complete, the 4096 time domain sample data record of vibration data is stored into the user data buffers, using the signal flow diagram shown in Figure 28. 21125-028 MODES OF OPERATION Figure 28. MTC Signal Flow Diagram Rev. 0 | Page 12 of 42 Data Sheet ADcmXL1021-1 MFFT Mode RTS Mode MFFT mode can manually trigger a capture to create a single FFT record with 2048 bins and allows various configuration options. The ADcmXL1021-1 has configurable high-pass and low-pass filters, decimation filtering, FFT averaging, and spectral alarms. The ADcmXL1021-1 also has options to calculate velocity, apply windowing, and apply offset compensation. MFFT mode is configured by setting the record mode in Register REC_CTRL, Bits[1:0] (Register 0x1A and Register 0x1B) = 0b00. RTS mode is configured by setting the record mode in Register REC_CTRL, Bits[1:0] (Register 0x1A and Register 0x1B) = 0b11. Processing steps collect 4096 consecutive time domain samples and filters the data similar to the MTC case. Additional windowing and FFT averaging can be enabled and configured using the 4096 sample burst captures. The ADcmXL1021-1 provides three different mathematical filtering options to processes the time record data, prior to performing an FFT, the filter options are rectangular, Hanning, or flat top. See the REC_CTRL register in Table 47 for more information on selecting the window option. The ADcmXL1021-1 creates data records in FFT and MTC modes and supports three methods of data storage for each data record: immediate only, alarm triggered, and all mode. In MTC mode, the time domain statistics are stored and are not the time records. When a capture event is triggered by the user, the event follows the process flow diagram shown in Figure 29. The FIR filter has 32 coefficients and processes at the full internal ADC sample rate of 220 kSPS. Users can select from one of six FIR filter bank options. Three of these filter banks have preset coefficients that provide low-pass responses to support half power bandwidths of 1 kHz, 5 kHz, and 10 kHz, respectively. The other three filter banks have preset coefficients that provide high-pass responses to support half power bandwidths of 1 kHz, 5 kHz, and 10 kHz filter. All six filter banks can be overwritten through user programming and stored to flash memory. DECIMATION FILTER FIR TIME RECORD N = 4096 FFT AND AVERAGING DATA BUFFER 21125-029 After the FIR filter is applied to the time domain data, if enabled, the data is decimated according to the AVG_CNT setting until a full 4096 time sample capture fills the data buffer. This decimation produces a time record that is converted to a spectral record and averaged, depending on the FFT_AVG1 or the FFT_AVG2 setting, as appropriate (see Figure 41 for the FFT capture datapath and appropriate registers). Figure 29. Signal Processing Diagram for FFT Modes AFFT Mode AFFT mode is configured by setting the record mode in Register REC_CTRL, Bits[1:0] (Register 0x1A and Register 0x1B) = 0b01. AFFT mode supports the same functionality as MFFT mode, except AFFT mode automatically advances and independently controls new capture events. New capture events are triggered periodically and are configured in the register map using REC_PRD. When operating in RTS mode, the ADcmXL1021-1 samples the accelerometer at a rate of 220 kSPS and makes this data available through a burst pattern via the SPI. DATA RECORDING OPTIONS When immediate only mode is selected, only the most recent capture data record is retained and accessible. In alarm triggered mode, only data that triggered an alarm is stored. When an alarm event is triggered, the ADcmXL1021-1 stores the header registers and the FFT data to flash memory. Alarm triggered mode is helpful for continuous operation while minimally impacting the limited endurance of the flash memory. In all mode, each data record is stored. The data stored includes FFT header information and FFT data. Up to 10 FFT records can be stored and retrieved. The ADcmXL1021-1 samples, processes, and stores vibration data to the FFT or the MTC data. In MTC mode, the record contains 4096 samples. In MFFT mode and AFFT mode, each record contains the 2048 bin FFT results. Table 6 describes the registers that provide access to processed sensor data. Table 6. Output Data Registers Register TEMP_OUT SUPPLY_OUT BUF_PNTR REC_PNTR OUT_BUF Address 0x02 0x04 0x0A 0x0C 0x12 Description Internal temperature measurement Internal power supply measurement Data buffer index pointer FFT record index pointer Accelerometer data buffer GLOB_CMD TIME_STAMP_L TIME_STAMP_H REC_INFO1 REC_INFO2 0x3E 0x4C 0x4E 0x66 0x68 Global command register Timestamp, lower word Timestamp, upper word FFT record header information FFT record header information To save power for long off time durations, the device can be configured to sleep between auto captures using Bit 7 in the REC_CTRL register. Rev. 0 | Page 13 of 42 ADcmXL1021-1 Data Sheet Reading Data from the Data Buffer Accessing FFT Record Data After completing a spectral record and updating each data buffer, the ADcmXL1021-1 loads the first data sample from each data buffer to the OUT_BUF registers (see Table 11) and sets the buffer index pointer in the BUF_PNTR register to 0x0000 (see Table 7). The index pointer determines which data samples load to the OUT_BUF registers. For example, writing 0x009F to the BUF_PNTR register (DIN = 0x8A9F, DIN = 0x8B00) causes the 160th sample in each data buffer location to load to the OUT_BUF registers. The index pointer automatically increments with each OUT_BUF read command, which causes the next set of capture data to load to each capture buffer register. This automatic increment enables an efficient method for reading all 4096 time samples or 2048 FFT points in a record, using sequential read commands, without needing to manipulate the BUF_PNTR register. Up to 10 FFT records can be stored in flash memory. The REC_ PNTR register (see Table 8) and GLOB_CMD bit (Bit 13, see Figure 31) provide access to the FFT records. DATA IN BUFFERS LOAD INTO USER OUTPUT REGISTERS OUT_BUF 0 BUF_PNTR The process when FFT averaging is enabled is as follows: 1. 2. A capture is initiated. Time domain samples are captured and filtered according to AVG_CNT setting until 4096 time samples fill the buffer. 3. The FFT is calculated from the time samples in the buffer and the record is stored. 4. After the number of FFT averages is reached, all FFT records in memory are averaged and stored. 5. Alarms are checked, flags are set, and the data record is stored as per configuration 6. In either manual or automatic mode, the next sample rate option is set. 7. The BUSY signal is set. An FFT record is an FFT stored in flash, and an FFT capture is an FFT stored in RAM. Table 8. REC_PNTR (Base Address = 0x0C), Read/Write ACCELEROMETER TIME/FFT BUFFER Bits [12:8] [3:0] 4096/2048 Description (Default = 0x0000) Time statistic record pointer address FFT record number pointer address TIME/FFT ANALYSIS FFT RECORD 0 FFT RECORD 1 FFT RECORD m FFT RECORD 9 m = REC_PNTR GLOB_CMD, BIT 13 = 1 Figure 30. Data Buffer Structure and Operation SPI REGISTERS Table 7. BUF_PNTR (Base Address = 0x0A), Read/Write Bits [15:12] [11:0] Description (Default = 0x0000) Not used Data bits; range = 0 to 2047 (FFT), 0 to 4095 (time) FFT BUFFER 21125-032 TEMP_OUT INTERNAL SAMPLING SYSTEM SAMPLES, PROCESSES, AND STORES DATA IN FFT BUFFERS 21125-031 SUPPLY_OUT Figure 31. FFT Record Access MTC Data Format In MTC mode, the OUT_BUF register contains a single time domain sample. When reading OUT_BUF, BUF_PNTR automatically advances from 0 to 4095. The time domain data is 16-bit, twos complement acceleration data by default with a resolution of 1 LSB = 1.907 mg. If velocity data is selected by setting REC_CTRL, Bit 5 = 1, velocity data is stored in the buffer registers instead. Velocity data has a resolution of 1 LSB = 18.62 mm/sec and is calculated by integrating the acceleration data. Rev. 0 | Page 14 of 42 Data Sheet ADcmXL1021-1 Table 11 lists the bit assignments for the OUT_BUF register. The acceleration data format depends on the record type setting in the REC_CTRL register. Table 41 and Table 42 shows data formatting examples for the 16-bit, twos complement format used in manual time mode. In MTC mode, time domain statistic can be calculated by enabling Bit 6 in the REC_CTRL register. The statistics value scales are calculated based on setting of accelerometer or velocity. The time domain statistics available are mean, standard deviation, peak, peak-to-peak, crest factor, Kurtosis, and skewness. The scale of all statistics are consistent with the data format selected (1 LSB = 1.907 mg or 18.62 mm/sec for acceleration or velocity, respectively), except crest factor, Kurtosis, and skew, which require fractional numbers. The magnitude (out) can be calculated from the value read by using the following equation: OUT _ BUF 2 2048 Out = x 0.9535 mg Number of FFT Averages Table 12 and Table 43 show the data formatting examples for FFT mode conversions from the OUT_BUF value to acceleration. When reading the OUT_BUF register, BUF_PNTR automatically advances from 0 to 2047. The FFT data is unsigned 16-bit data. Table 12. FFT Magnitude Conversion from Register Value, Data Format Examples FFT Averages 1 1 1 1 2 2 2 4 4 4 8 8 16 128 Table 10. MTC Mode, 50 g Range, Data Format Examples, Configured for Optional Velocity Output Mode FFT Buffer Read Value (Bits) 0x0001 0x0002 0x00FF 0x7D00 0x0001 0x0002 0x00FF 0x0005 0x05FF 0x7530 0x00FF 0x7D00 0x7D00 0xAFCE Velocity (mm/sec), LSB = 18.62 mm/sec LSB Hex. Binary RTS Data Format +610,121.5 +122,035.5 +37.24 +18.62 0 -18.62 -37.24 -122,035.5 -610,121.5 +32,767 +6554 +2 +1 0 -1 -2 -6554 -32,768 0x7FFF 0x199A 0x0002 0x0001 0x0000 0xFFFF 0xFFFE 0xE666 0x8000 0111 1111 1111 1111 0001 1001 10011010 0000 0000 0000 0010 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1110 1110 0110 0110 0110 1000 0000 0000 0000 In RTS mode, continuous data is burst out of the SPI. Each data frame consists of 16 samples of accelerometer data plus eight words of zeros and a frame header, temperature reading, status bits, and a 16-bit cyclical redundancy check (CRC) code. Each data sample is 16-bit, twos complement acceleration data by default with a resolution of 1 LSB = 1.907 mg. It is important that the external host device is able to retrieve the burst data in a sufficient time allotment, which is approximately 135 s per data frame. No internal corrections are applied to this data. Therefore, the data may deviate from the results of other capture modes. Data is unsigned and must be offset (subtract) by 0x8000 to obtain g (signed data). Table 9. MTC Mode, 50 g Range, Data Format Examples Acceleration (mg) (1.907 mg/LSB) LSB Hex. Binary +62486.7 +12498.5 +3.9 +1.9 0 -1.9 -3.8 -12498.5 -62488.6 +32,767 +6554 +2 +1 0 -1 -2 -6554 -32,768 0x7FFF 0x199A 0x0002 0x0001 0x0000 0xFFFF 0xFFFE 0xE666 0x8000 0111 1111 1111 1111 0001 1001 10011010 0000 0000 0000 0010 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1110 1110 0110 0110 0110 1000 0000 0000 0000 Table 11. OUT_BUF (Base Address = 0x12), Read Only Bits [15:0] Description (Default = 0x8000) Output acceleration data buffer register. Format = twos complement (time), unsigned integer (FFT). FFT Data Format for AFFT and MFFT Modes In both AFFT and MFFT modes, the OUT_BUF contains a calculated FFT bin magnitude. The values contained in buffer locations from 0 to 2047 represent the magnitude of frequency bins of size, depending on the AVG_CNT value as shown in Table 18. Magnitude 0.953823 mg 0.954146 mg 1.039447 mg 48.18528 g 0.476911 mg 0.477073 mg 0.519724 mg 0.238779 mg 0.400762 mg 6.121809 g 0.129931 mg 6.02316 g 3.01158 g 30.65768 g When first entering RTS mode capture, the first eight samples are all 0s and the CRC for the first frame is invalid. It is recommended that the first data frame be ignored, and data for the second frame and all subsequent frames be used. Rev. 0 | Page 15 of 42 ADcmXL1021-1 Data Sheet Table 13 shows several examples of how to translate RTS data values, assuming nominal sensitivity and zero bias error. I/O LINES ARE COMPATIBLE WITH 3.3V LOGIC LEVEL 3.3V VDD Table 13. RTS Mode Data Format Examples LSB 65,535 58,967 32,770 32,769 32,768 32,767 32,766 6567 0 Hex. 0xFFFF 0xE657 0x8002 0x8001 0x8000 0x7FFF 0x7FFE 0x19A7 0x0000 Binary 1111 1111 1111 1111 1110 0110 0101 0111 1000 0000 0000 0010 1000 0000 0000 0001 1000 0000 0000 0000 0111 1111 1111 1111 0111 1111 1111 1110 0001 1001 1010 0111 0000 0000 0000 0000 ADcmXL1021-1 SS 14 CS SCLK 13 SCLK MOSI 11 DIN MISO 12 DOUT IRQ2 2 ALM1 IRQ1 4 ALM2 3 SYNC/RTS 5 BUSY 7 RST GND GND GND 1 9 USER INTERFACE The user interface includes several important functions: a data communications port, a trigger input, a busy indicator, and two alarm indicator signals. Data communication between an embedded processor (master) and the ADcmXL1021-1 takes place through the SPI, which includes the CS, SCLK, DIN, and DOUT pins (see Table 5). The SYNC/RTS (see Table 5) pin provides user triggering options in manual triggering modes. The alarm pins, ALM1 and ALM2, are configurable to alert the user of an event that exceeds a user defined threshold of a parameter. The SYNC/RTS pin is used in RTS mode to support start and stop control over data capture and analysis operations. The BUSY pin (see Table 5) provides an indication of internal operation when the ADcmXL1021-1 is executing a command. This signal helps the master processor avoid SPI communication when the ADcmXL1021-1 cannot support a response and can trigger an external data acquisition after data capture and analysis events are complete. The ADcmXL1021-1 uses an SPI for communication, which enables simple connection with most embedded processor platforms, as shown in Figure 32. 10 21125-011 Acceleration (g) +62.532 +50 +0.003816 +0.001908 0 -0.001908 -0.003816 -50 -62.534 8 SYSTEM PROCESSOR SPI MASTER Figure 32. Electrical Hookup Diagram The register structure uses a paged addressing scheme that contains seven pages, with each page containing 64 register locations. Each register is 16 bits wide, with each 2-byte word having its own unique address within the memory map of that page. The SPI port has access to one page at a time. Select the page to activate for SPI access by writing the corresponding code to the PAGE_ID register. Read the PAGE_ID register to determine which page is currently active. Table 14 displays the PAGE_ID contents for each page and the basic functions. The PAGE_ID register is located at Address 0x00 on each page. Table 14. User Register Page Assignments Page No. PAGE_ID Function 0 1 2 3 4 5 6 0x00 0x01 0x02 0x03 0x04 0X05 0x06 Configuration, data acquisition FIR Filter Bank A FIR Filter Bank B FIR Filter Bank C FIR Filter Bank D FIR Filter Bank E FIR Filter Bank F The factory default configuration for the BUSY pin provides a busy indicator signal that transitions high when an event completes and data is available for user access and remains low during processing. Table 15. Generic Master Processor Pin Mnemonics and Functions Pin Mnemonic SS SCLK MOSI MISO IRQ1, IRQ2 Function Slave select Serial clock Master output, slave input Master input, slave output Interrupt request inputs (optional) The ADcmXL1021-1 SPI supports full duplex serial communication (simultaneous transmit and receive) and uses the bit sequence shown in Figure 36. Table 16 shows a list of the most common settings that control the operation of SPI-compatible ports in most embedded processor platforms. Rev. 0 | Page 16 of 42 Data Sheet ADcmXL1021-1 SPI Write Commands Embedded processors typically use control registers to configure serial ports for communicating with SPI slave devices, such as the ADcmXL1021-1. Table 16 lists settings that describe the SPI protocol of the ADcmXL1021-1. The initialization routine of the master processor typically establishes these settings using firmware commands to write them into the serial control registers. User control registers govern many internal operations. The DIN bit sequence in Figure 36 provides a description to write to these registers. Each configuration register contains 16 bits (two bytes). Bits[7:0] contain the low byte, and Bits[15:8] contain the high byte of each register. Each byte has a unique address in the user register map (see Table 19). Updating the contents of a register requires writing both bytes in the following sequence: low byte first, high byte second. There are three parts to coding a SPI command (see Figure 36) that write a new byte of data to a register: the write bit (R/W = 1), the address of the byte [A6:A0], followed by the new data for that register address [DC7:DC0]. Table 16. Generic Master Processor SPI Settings Description ADcmXL1021-1 operates as slave Bit rate setting Clock polarity/phase (CPOL = 1, CPHA = 1) Bit sequence Shift register/data length Little Endian Figure 34 provides a coding example for writing 0x2345 to the FFT_AVG1 register, the 0x8623 command writes 0x23 to Address 0x06 (lower byte) and the 0x8745 command writes 0x45 to Address 0x07 (upper byte). Table 19 lists user registers with lower byte addresses. Each register consists of two bytes. Each byte has a unique 7-bit address. Figure 33 relates the bits of each register to the upper and lower addresses. 12 11 10 9 8 7 6 UPPER BYTE 5 4 3 2 1 0 LOWER BYTE DIN 0x8623 0x8745 Figure 34. Single SPI Write Command Figure 33. Generic Register Bit Definitions SPI Read Commands Register Structure A single register read requires two 16-bit SPI cycles that use the bit assignments shown in Figure 36. The beginning sequence sets R/W = 0 and communicates the target address (Bits[A6:A0]). Bits[DC7:DC0] are don't care bits for a read DIN sequence. DOUT clocks out the requested register contents during the second sequence. The second sequence can also use DIN to set up the next read. All communication with the ADcmXL1021-1 involves accessing the user registers. The register structure contains both output data and control registers. The output data registers include the latest sensor data, alarm information, error flags, and identification data. The control register contained in Page 0 includes configurable options, such as time domain averaging, FFT averaging, filtering, alarm parameters, diagnostics, and data collection mode settings. Each user accessible register has two bytes (upper and lower), and each byte has a unique address. See Table 19 for a detailed list of all user registers, along with the corresponding addresses. Figure 35 provides an example that includes two register reads in succession. This example starts with DIN = 0x0C00 to request the contents of the REC_PNTR register, and follows with 0x0E00, to request the contents of the OUT_BUF register. The sequence in Figure 35 also shows the full duplex mode of operation, which means that the ADcmXL1021-1 can receive requests on DIN while also transmitting data out on DOUT within the same 16-bit SPI cycle. All communication between the ADcmXL1021-1 and an external processor involves either reading or writing these 16-bit user registers. DIN 0x0C00 DOUT 0x0E00 NEXT ADDRESS REC_PNTR OUT_BUF Figure 35. SPI Mulitbyte Read Command Example CS SCLK DIN DOUT R/W D15 21125-022 13 A6 A5 A4 A3 A2 A1 A0 D14 D13 D12 D11 D10 D9 D8 DC7 DC6 D7 D6 DC5 DC4 DC3 DC2 DC1 DC0 D5 D4 D3 D2 D1 D0 R/W D15 A6 A5 D14 D13 NOTES 1. DOUT BITS ARE PRODUCED ONLY WHEN THE PREVIOUS 16-BIT DIN SEQUENCE STARTS WITH R/W = 0. 2. WHEN CS IS HIGH, DOUT IS IN A THREE-STATE, HIGH IMPEDANCE MODE, WHICH ALLOWS MULTIFUNCTIONAL USE OF THE LINE FOR OTHER DEVICES. Figure 36. SPI Communication, Multibyte Sequence Rev. 0 | Page 17 of 42 21125-015 14 SCLK 21125-012 15 CS 21125-121 Processor Setting Master SCLK Rate 14 MHz SPI Mode 3 MSB First 16-Bit Mode Readout Formatting ADcmXL1021-1 Data Sheet Busy Signal The factory default configuration provides the user with a busy signal (BUSY) that pulses low when the output data registers are updating (see signal orientation of busy signal in Figure 37). In this configuration, connect BUSY to an interrupt service pin on the embedded processor, which triggers data collection, when this signal pulses high. 21125-016 SPI COMMAND BUSY AVAILABLE NOT AVAILABLE Figure 37. Busy Signal (BUSY) Orientation After SPI Command During the start-up and reset recovery processes, the BUSY signal can exhibit some transient behavior before data production begins. Figure 37 provides an example of the BUSY behavior during command processing. A low signal indicates SPI access is not available with the exception of the escape code that can terminate a capture. Figure 38 shows the BUSY signal during start up. TIME THAT VDD > 3V The RTS burst contains 44 16-bit words (8 zero words, a header, including an incrementing counter, 32 accelerometer data words, temperature, status, and CRC). The external SCLK rate must be between 8 MHz to 14 MHz to ensure that the complete burst is read out before current data in the register buffer is overwritten. The maximum SCLK for RTS burst outputs is 14 MHz 1%. The minimum SCLK required to support the transfer is 8 MHz. The RTS burst response uses the sequencing diagrams shown in Figure 4 and Figure 5 and the data format shown in Table 17. When first entering RTS mode capture, the first eight samples are all 0s, and the CRC for the first frame is invalid. It is recommended that the first frame be ignored, and that the data for the second frame and all subsequent frames be used. Table 17. RTS Data Format Byte Location in Output Dataset 0 ... 14 16 VDD MICROCONTROLLER IS BUSY WHEN BUSY IS LOW START-UP TIME ~200ms 21125-017 BUSY Figure 38. BUSY Response During Start Up RTS 18 20 22 ... 80 82 84 86 The RTS function provides a method for reading data (time domain acceleration data, temperature, status, and CRC code) that does not require a stall time between each 16-bit segment and only requires one command on the DIN line to initiate. System processors can execute this mode by reading each segment of data in the response, while holding the CS line in a low state until after reading the last 16-bit segment of data. If the CS line goes high before the completion of all data acquisition, the data from that read request is lost. Rev. 0 | Page 18 of 42 2-Byte Value Represents 0x0000 ... 0x0000 Fixed header: 0xccAD; where cc is an incrementing counter value from 0x00 to 0xFF, which returns to 0x00 after 0xFF XL1 (oldest data from accelerometer) XL2 XL3 ... XL32 Temperature Status CRC-16 Data Sheet ADcmXL1021-1 BASIC OPERATION DEVICE CONFIGURATION TRIGGER Each register contains 16 bits (two bytes). Bits[7:0] contain the low byte, and Bits[15:8] contain the high byte. Each byte has a unique address in the user register map (see Table 19). Updating the contents of a register requires writing to the low byte first and the high byte second. There are three parts to coding a SPI command, which writes a new byte of data to a register: the write bit (R/W = 1), the 7-bit address code for the byte that this command is updating, and the 16 bits of new data for that location. All modes, including RTS mode, require a trigger to start. AFFT mode and RTS mode also require a trigger to stop recording. DUAL MEMORY STRUCTURE The ADcmXL1021-1 uses a dual memory structure (see Figure 39) with static random access memory (SRAM), supporting real-time operation and flash memory storing operational code and user configurable register settings. The manual flash update command (Bit 6 in the GLOB_CMD register) provides a single command method for storing user configuration settings to flash memory for automatic recall during the next power-on or reset recovery process. During power-on or reset recovery, the ADcmXL1021-1 performs a CRC on the SRAM and compares this result to a CRC computation from the same memory locations in flash memory. If this memory test fails, the ADcmXL1021-1 resets and boots up from the other flash memory location. The ADcmXL1021-1 provides an error flag for detecting when the backup flash memory supported the last power-on or reset recovery. Table 19 shows a memory map for the user registers in the ADcmXL10211, which includes flash backup support (indicated by yes or no in the flash column). NONVOLATILE FLASH MEMORY VOLATILE SRAM (NO SPI ACCESS) SPI ACCESS START-UP RESET 21125-023 MANUAL FLASH BACKUP Figure 39. SRAM and Flash Memory Diagram POWER-UP SEQUENCE The ADcmXL1021-1 requires only a single 3.3 V supply voltage and supports communication with most 3 V compliant embedded processor platforms using an SPI protocol. Avoid applying voltage to the SYNC/RTS, CS, SCLK, and DIN input pins until the proper supply voltage is applied to the module. The power ramp from 0 V to 3.0 V must be monotonic. The module performs internal initialization, tests flash memory, and performs a sensor self test after powering on. No SPI access is allowed during this time. The module signals a completed initialization by setting the BUSY pin logic high. Start triggers arise either from using the SYNC/RTS digital input pin or by setting Bit 11 in the GLOB_CMD register (see Table 73). If using the SYNC/RTS pin as a trigger, the user must set Bit 12 in the MISC_CTRL register = 1 to enable this feature. While in RTS mode, during a valid capture period, normal SPI access is disabled until a valid stop is received. The user can stop a capture in RTS mode in two ways: via a hardware pin or using software. The hardware pin method uses the RTS pin, which is enabled in Bit 12 of the MISC_CTRL register. The software method requires the user to set Bit 15 in the REC_CTRL register to 1, which enables timeout mode which must be configured prior to initiating a capture. In this case, RTS mode stops after 30 ms with no user supplied external readback clocks with CS low. To restart RTS mode, use the normal start trigger options described in this section. To stop a capture in AFFT mode, the user must issue a stop command during a period when BUSY is high (BUSY is low when the device is configured for power saving mode and sleeps between captures) or by write an escape code to the device at any time. All other SPI writes are ignored. When the ADcmXL1021-1 is in between active collecting periods (as configured in the REC_PRD register), setting Bit 11 in the GLOB_CMD register (see Table 73) to 1 (DIN = 0xBF08) interrupts the operation and the ADcmXL1021-1 returns to operating in the idle state. The REC_PRD counter starts at the beginning of the capture and must be set to a period greater than the longest capture time if multiple rate options (Sample Rate 0 to Sample Rate 3) are enabled. When operating in MFFT or MTC mode, the ADcmXL1021-1 operates in an idle state until it receives a command to start collecting data. When the ADcmXL1021-1 is in this idle state, setting Bit 11 in the GLOB_CMD register (see Table 73) to 1 starts a data collection and processing event. An interruption of data collection and processing causes a loss of all data from the interrupted process. A positive pulse on the SYNC/RTS pin provides the same start function as raising Bit 11 in the GLOB_CMD register when operating in MFFT mode. In cases with many averages, a capture event can last an extended period with access to the SPI port (for example, when a device stays in a busy state). In this case, an escape code is used to terminate the active capture. The escape code is 0x00E8 and is written to the GLOB_CMD register, using the two 16-bit sequence 0xBEE8, followed by 0xBF00 and repeat until BUSY returns to a high logic state. A valid escape is also indicated in Bit 4 of the DIAG_STAT register. After an escape is issued, any data collected during the last capture is no longer valid. To continue capturing data, refer to the normal start trigger options. Rev. 0 | Page 19 of 42 ADcmXL1021-1 Data Sheet SAMPLE RATE RTS mode has a fixed sample rate of 220 kSPS. The output is streamed out in a burst data packet over the SPI communications port. After the device is configured for RTS mode, conversion starts and stops are controlled by the SYNC/RTS pin or by stopping SPI activity for a period of time (see Bit 15 of the REC_CTRL register). RTS mode is unique in that, when configured, no additional processing is preformed and samples are output directly from the ADC without null, filter, or digital signal processing and alarms are not checked. A low-pass analog filter with a 13.5 kHz cutoff frequency is always in the datapath and, along with the high ADC sample rate, prevents aliasing. For MTC mode, the sampling rate is always 220 kSPS and captures 4096 samples. The module can be configured to perform internal digital averaging. For the null function (see Figure 28), the user can write offset correction values into the ANULL register (see Table 45). The user can also initiate the autonull command via Bit 0 in the GLOB_CMD register (see Table 73), which automatically estimates the offset error and writes correction values to the ANULL register. The autonull feature uses settings of SR3 to capture and calculate a correction value and requires time to complete. The AVG_CNT register allows the selection of the number of averages used in each capture for up to four sample rate options. The REC_CTRL register selects which sample rate options are enabled. The number of averages determines the sample rate for each sample rate option by the following equation: Effective FFT Bin Size, f_MIN (Hz) 53.71094 26.85547 13.42773 6.713867 3.356934 1.678467 0.839233 0.419617 DATAPATH PROCESSING For RTS mode, there is no digital processing of data internal to the ADcmXL1021-1. Data is buffered internally to 32 sample packets that are burst output over the SPI interface. For MTC mode, AFFT mode, and MFFT mode, the initial capture and processing procedure is the same and is as follows: 1. 2. Capture 4096 consecutive time domain samples at 220 kSPS. If AVG_CNT is enabled, apply the appropriate decimation filter. Continue to collect data until 4096 time sample buffer is filled. Null data, if enabled. Apply the FIR filter, if enabled. If MTC mode is enabled, the remaining steps are required: Table 18. FFT Bin Sizes, Frequency Limits (Hz) Effective Sample Rate, fS (SPS) 220000 110000 55000 27500 13750 6875 3437.5 1718.75 An important note is that the execution of the retrieve record with many FFT averages and a low sample rate may take minutes to hours to complete. Because the device turns off SPI interrupts during a recording, the user cannot send a stop command. Instead, the device monitors the SPI receive buffer for the escape code, a SPI write of 0x00E8 to the GLOB_CMD register, during the data capture portion of the recording. Therefore, the user can escape from a recording by writing 0x00E8 to the GLOB_CMD register. It is recommended to write only 0x00E8 to the device, provide a small delay, and then monitor the busy indicator or poll the status register. Repeatedly send the 0x00E8 code and check the status register until the status register shows the escape flag and busy indicator/data ready flag. 3. 4. Sample Rate = 220 kHz/2AVG_CNT[3:0] AVG_CNT Setting (Averages) 0 (1) 1 (2) 2 (4) 3 (8) 4 (16) 5 (32) 6 (64) 7 (128) data is stored in user accessible buffer, in place of the time domain values, and spectral alarms are checked. Effective Maximum FFT Frequency, f_MAX (Hz) 110000 55000 27500 13750 6875 3437.5 1718.75 859.375 In MFFT mode and AFFT mode, each FFT data record starts with a capture of 4096 time domain samples (after decimation, if enabled), as with MTC mode. The data is processed with the null function and FIR filter after the decimation filter, as with MTC mode. An FFT calculation is performed on the data. This 5. 6. 7. 8. 9. Calculate the statistic values enabled. Check the statistics against alarm settings. Write the statistic values to the data buffer. Calculate time domain statistics. Check time domain alarms and set the alarm bit if appropriate. 10. Record statistic data according to the storage option selected. 11. Perform signal completion by setting the BUSY pin. If AFFT or MFFT mode is enabled, the remaining steps occur after the initial capture and processing: 5. 6. 7. 8. Rev. 0 | Page 20 of 42 Calculate the FFT based on the AVG_CNT setting. Record data according to the storage option selected. Check frequency domain alarms, set the alarm bit if appropriate. Signal completion by setting the BUSY pin. Data Sheet ADcmXL1021-1 MEMS SENSOR DECIMATION FILTER fS / D ADC fS = 220kSPS USER DATA BUFFER1 N = 4096 FIR FILTER 32 TAPS REGISTERS: FILT_CTRL FIR_COEFF_xxx REGISTER: AVG_CNT STATISTICAL ANALYSIS/ ALARM CHECK REGISTERS: OUT_BUF STAT HEADER REGISTERS: STAT STAT_PNTR NULL 21125-027 REGISTERS: ANNUL GLOB_CMD 1OPTIONAL VELOCITY CALCULATIONS APPLIED PRIOR TO USER BUFFER. Figure 40. MTC Mode Datapath Processing MEMS SENSOR ADC fS = 220kSPS DECIMATION FILTER fS / D FIR FILTER 32 TAPS TIME RECORD CAPTURE N = 4096 REGISTER: REC_CTRL REGISTERS: FILT_CTRL FIR_COEFF_xxx REGISTERS: AVG_CNT WINDOW FUNCTION NULL FAST FOURIER TRANSFORM REGISTERS: FFT_AVG1 FFT_AVG2 REC_INFO1 REC_INFO2 REGISTERS: OUT_BUF SPECTRAL ALARMS REGISTERS: ALM_CTRL ALM_PNTR ALM_F_LOW ALM_F_HIGH ALM_MAG1 ALM_MAG2 ALM_S_MAG FUND_FREQ ALM_STAT ALM_PEAK ALM_FREQ 21125-026 REGISTERS: ANNUL GLOB_CMD USER DATA BUFFERS Figure 41. AFFT Mode and MFFT Mode Datapath Processing After null corrections are applied, the data of the inertial sensor passes through an FIR filter (using the FILT_CTRL register), decimation filter (using the AVG_CNT register), and windowing filter (using the REC_CTRL register), all of which have user configurable attributes. The FIR filter includes six banks of coefficients with 32 taps each. The FILT_CTRL register (see Table 65) provides the configuration options for the use of the FIR filters of each inertial sensor. Each FIR filter bank includes a preconfigured filter, but the user can design filters and write over these values using the register of each coefficient. Default filter configuration options are either low-pass or high-pass filters with cutoff frequencies of either 1 kHz, 5 kHz, or 10 kHz. Page 1 through Page 6 define the six sets of FIR filter coefficients. Each page is dedicated to a single filter. For example, Page 1 in the register map provides the details for the 1 kHz low-pass FIR filter. These filters represent typical cutoff frequencies for machine vibration monitoring applications. FIR Filter Six FIR filters are preprogrammed by default in memory and available for use. The coefficients for these filters are stored in Page 1 to Page 6 and provide selectable filter options for the 1 kHz, 5 kHz, or 10 kHz low-pass filter, and the 1 kHz, 5 kHz, or 10 kHz high-pass filter. Users can write and store custom filter setting by overwriting existing filter coefficients and saving these values to flash memory. Decimation Averaging options are available within the ADcmXL1021-1 and reduce the amount of data required to be transferred for a given bandwidth while also reducing random noise impact on the signal to noise ratio. Decimation is set using the AVG_CNT register and enabled in REC_CTRL register. The decimation filter can be used when the module is configured for MTC, MFFT, or AFFT operation but is not available in RTS mode. Table 69 shows selectable sample rates and resulting FFT bin width options. MTC mode, AFFT mode, and MFFT mode can be configured to cycle automatically through up to four different AVG_CNT settings (enabled in the REC_CTRL register): SR0, SR1, SR2, and SR3. When more than one sample rate option is enabled (REC_ CTRL register, Bit 8 through Bit 11, see Table 47), the device cycles through each one. Windowing There are three windowing options that can be applied to the time domain recording before the FFT is computed. The typical window for vibration monitoring is the Hanning window. This window is provided as a default. A Hanning window is optimal because it offers good amplitude resolution of the peaks between frequency bins and minimal broadening of the peak. The rectangular and flat top windows are also available because they are common windowing options for vibration monitoring. The rectangular window is a window of magnitude 1 providing a flat time domain response. The flat top window is advantageous because it can provide very accurate amplitudes with the disadvantage of significant broadening of the peaks. This window is useful when the magnitude accuracy of the peak is important. Rev. 0 | Page 21 of 42 ADcmXL1021-1 Data Sheet SPECTRAL ALARMS ALM_F_LOW When using MFFT mode or AFFT mode, six flexible alarms can be configured with settings. There are 48 possible alarm configurations considering there are six alarm bands (x4 sample rate options x 2 magnitude alarm levels). ALM_MAG2 The alarm status is reported in the ALM_STAT register. These registers show which alarm caused the last alarm event. If the alarm is serviced immediately, REC_INFO1 and REC_INFO2 contain the last capture settings for additional information about the event. Based on the record mode (REC_CTRL, Bits[3:2]) setting, up to 10 FFT capture records can be stored in memory. When an alarm is triggered, the values in the ALM_PEAK register represent the peak value. Only the values that triggered the alarm are stored when the measured value for the given conditions exceed the ALM_MAG1 and ALM_MAG2 threshold settings. The magnitude is in the resolution as configured by the FFT_AVG1 or FFT_AVG2 setting for the specific capture. The alarm frequency bin of the peak deviation point is reported in ALM_FREQ. The result is in units of resolution (Hz), configured through the AVG_CNT setting for the specific capture. ALM_MAG1 MAGNITUDE 1 2 3 4 5 6 FREQUENCY 21125-024 The ALM_PNTR register cycles through up to six alarm band configurations per capture. A lower frequency register (ALM_ F_LOW) and an upper frequency register (ALM_F_HIGH) are set to define a bandwidth of interest. ALM_MAG1 and ALM_MAG2 define two levels of magnitude within the band set on which to base two triggers. These levels allow two warning levels for a trigger. Setting ALM_CTRL allows the setting of enabling and disabling individual axes, two warning levels, the number of events required to trigger an alarm, and the clearing options for the trigger alerts. ALM_F_HIGH Figure 42. Spectral Alarm Band Registers MECHANICAL MOUNTING RECOMMENDATIONS Mechanical mounting is critical to ensure the best transfer of vibration and avoiding resonances that may affect performance. The ADcmXL1021-1 module has four mounting holes integrated in the aluminum housing. The mounting holes accept M2.5 screws to hold the module in place. Stainless steel screws torqued to about 25 inch-pounds are used for many of the characterization curves shown in the Typical Performance Characteristics section. In some cases, when permanent mounting is an option, industrial epoxies or adhesives, such as cyanoacrylate adhesive, in addition to the mounting screws can enhance mechanical coupling. Rev. 0 | Page 22 of 42 Data Sheet ADcmXL1021-1 USER REGISTER MEMORY MAP Table 19. User Register Memory Map 1 Register Name PAGE_ID 2 TEMP_OUT SUPPLY_OUT FFT_AVG1 FFT_AVG2 BUF_PNTR REC_PNTR OUT_BUF ANULL REC_CTRL Reserved REC_PRD ALM_F_LOW ALM_F_HIGH ALM_MAG1 ALM_MAG2 ALM_PNTR ALM_S_MAG ALM_CTRL Reserved FILT_CTRL AVG_CNT DIAG_STAT GLOB_CMD ALM_STAT ALM_PEAK TIME_STAMP_L TIME_STAMP_H Reserved DAY_REV YEAR_MON PROD_ID R/W R/W R R R/W R/W R/W R/W R R/W R/W N/A R/W R/W R/W R/W R/W R/W R/W R/W N/A R/W R/W R W R R R R N/A R R R Flash Backup No No No Yes Yes No No No Yes Yes N/A Yes Yes 4 Yes4 Yes4 Yes4 No No Yes N/A Yes Yes No No Yes 5 Yes5 Yes5 Yes5 N/A N/A N/A N/A PAGE_ID 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Address 0x00, 0x01 0x02, 0x03 0x04, 0x05 0x06, 0x07 0x08, 0x09 0x0A, 0x0B 0x0C, 0x0D 0x12, 0x13 0x18, 0x19 0x1A, 0x1B 0x1C, 0x1D 0x1E, 0x1F 0x20, 0x21 0x22, 0x23 0x28, 0x29 0x2E, 0x2F 0x30, 0x31 0x32, 0x33 0x34, 0x35 0x36, 0x37 0x38, 0x39 0x3A, 0x3B 0x3C, 0x3D 0x3E, 0x3F 0x44, 0x45 0x4A, 0x4B 0x4C, 0x4D 0x4E, 0x4F 0x50, 0x51 0x52, 0x53 0x54, 0x55 0x56, 0x57 Default 0x0000 0x8000 3 0x80003 0x0108 0x0101 0x0000 0x0000 0x8000 0x0000 0x1102 0x00FF 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0080 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 N/A N/A N/A 0x03FD SERIAL_NUM USER_SCRATCH REC_FLASH_CNT Reserved MISC_CTRL REC_INFO1 REC_INFO2 REC_CNTR ALM_FREQ STAT_PNTR Statistic FUND_FREQ FLASH_CNT_L FLASH_CNT_U PAGE_ID FIR_COEF_A00 FIR_COEF_A01 R R/W R N/A R/W R R R R R/W R R/W R R R/W R/W R/W N/A Yes N/A N/A No Yes5 Yes5 N/A Yes5 No Yes5 Yes N/A N/A No Yes Yes 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x01 0x58, 0x59 0x5A, 0x5B 0x5C, 0x5D 0x5E to 0x63 0x64, 0x65 0x66, 0x67 0x68, 0x69 0x6A, 0x6B 0x70, 0x71 0x72, 0x73 0x78, 0x79 0x7A, 0x7B 0x7C, 0x7D 0x7E, 0X7F 0x00, 0x01 0x02, 0x03 0x04, 0x05 N/A N/A N/A N/A N/A 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 N/A 0x0000 0x0001 0x0006 0x0015 Rev. 0 | Page 23 of 42 Register Description Page identifier Internal temperature Power supply voltage (VDD) FFT average settings (SR0 and SR1) FFT average settings (SR2 and SR3) Buffer address pointer Data record pointer Output buffer data Bias correction value (from auto null) Record control register (mode of operation) Reserved Record period setting Spectral alarm band, low frequency setting Spectral alarm band, high frequency setting Spectral alarm band, Alarm Magnitude 1 Spectral alarm band, Alarm Magnitude 2 Spectral alarm pointer System alarm threshold setting Alarm control settings Reserved Filter control settings Sample rate settings (SR0, SR1, SR2, and SR3) Diagnostic and status flags Global command triggers Alarm status Alarm peak value Time stamp, lower word Time stamp, upper word Reserved Firmware revision and firmware day code Firmware date (month, year) Product identification for ADcmXL1021-1 models, equals decimal 1021 Serial number, lot-specific , unique per device Scratch register for user ID option Write counter for data record portion of flash memory Reserved Miscellaneous control Record Information 1 Record Information 2 Record counter Frequency bin of most severe alarm Pointer for time domain statistics Selected statistical value Fundamental frequency setting Flash access counter, lower 16 bits Flash access counter, upper 16 bits Page identifier FIR Filter Bank A, Coefficient 0 FIR Filter Bank A, Coefficient 1 ADcmXL1021-1 Register Name FIR_COEF_A02 FIR_COEF_A03 FIR_COEF_A04 FIR_COEF_A05 FIR_COEF_A06 FIR_COEF_A07 FIR_COEF_A08 FIR_COEF_A09 FIR_COEF_A10 FIR_COEF_A11 FIR_COEF_A12 FIR_COEF_A13 FIR_COEF_A14 FIR_COEF_A15 FIR_COEF_A16 FIR_COEF_A17 FIR_COEF_A18 FIR_COEF_A19 FIR_COEF_A20 FIR_COEF_A21 FIR_COEF_A22 FIR_COEF_A23 FIR_COEF_A24 FIR_COEF_A25 FIR_COEF_A26 FIR_COEF_A27 FIR_COEF_A28 FIR_COEF_A29 FIR_COEF_A30 FIR_COEF_A31 Reserved PAGE_ID FIR_COEF_B00 FIR_COEF_B01 FIR_COEF_B02 FIR_COEF_B03 FIR_COEF_B04 FIR_COEF_B05 FIR_COEF_B06 FIR_COEF_B07 FIR_COEF_B08 FIR_COEF_B09 FIR_COEF_B10 FIR_COEF_B11 FIR_COEF_B12 FIR_COEF_B13 FIR_COEF_B14 FIR_COEF_B15 FIR_COEF_B16 FIR_COEF_B17 FIR_COEF_B18 FIR_COEF_B19 FIR_COEF_B20 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W N/A R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Data Sheet Flash Backup Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes N/A No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes PAGE_ID 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 Address 0x06, 0x07 0x08, 0x09 0x0A, 0x0B 0x0C, 0x0D 0x0E, 0x0F 0x10, 0x11 0x12, 0x13 0x14, 0x15 0x16, 0x17 0x18, 0x19 0x1A, 0x1B 0x1C, 0x1D 0x1E, 0x1F 0x20, 0x21 0x22, 0x23 0x24, 0x25 0x26, 0x27 0x28, 0x29 0x2A, 0x2B 0x2C, 0x2D 0x2E, 0x2F 0x30, 0x31 0x32, 0x33 0x34, 0x35 0x36, 0x37 0x38, 0x39 0x3A, 0x3B 0x3C, 0x3D 0x3E, 0x3F 0x40, 0x41 0x42 to 0x7F 0x00, 0x01 0x02, 0x03 0x04, 0x05 0x06, 0x07 0x08, 0x09 0x0A, 0x0B 0x0C, 0x0D 0x0E, 0x0F 0x10, 0x11 0x12, 0x13 0x14, 0x15 0x16, 0x17 0x18, 0x19 0x1A, 0x1B 0x1C, 0x1D 0x1E, 0x1F 0x20, 0x21 0x22, 0x23 0x24, 0x25 0x26, 0x27 0x28, 0x29 0x2A, 0x2B Default 0x0035 0x006B 0x00C1 0x013C 0x01E0 0x02AE 0x03A2 0x04B3 0x05D2 0x06EE 0x07F2 0x08CB 0x0967 0x09B9 0x09B9 0x0967 0x08CB 0x07F2 0x06EE 0x05D2 0x04B3 0x03A2 0x02AE 0x01E0 0x013C 0x00C1 0x006B 0x0035 0x0015 0x0006 N/A 0x0002 0x0004 0x0001 0xFFEC 0xFFB9 0xFF62 0xFEF1 0xFE8C 0xFE76 0xFEFE 0x006B 0x02E1 0x0645 0x0A34 0x0E13 0x1130 0x12EC 0x12EC 0x1130 0x0E13 0x0A34 0x0645 Rev. 0 | Page 24 of 42 Register Description FIR Filter Bank A, Coefficient 2 FIR Filter Bank A, Coefficient 3 FIR Filter Bank A, Coefficient 4 FIR Filter Bank A, Coefficient 5 FIR Filter Bank A, Coefficient 6 FIR Filter Bank A, Coefficient 7 FIR Filter Bank A, Coefficient 8 FIR Filter Bank A, Coefficient 9 FIR Filter Bank A, Coefficient 10 FIR Filter Bank A, Coefficient 11 FIR Filter Bank A, Coefficient 12 FIR Filter Bank A, Coefficient 13 FIR Filter Bank A, Coefficient 14 FIR Filter Bank A, Coefficient 15 FIR Filter Bank A, Coefficient 16 FIR Filter Bank A, Coefficient 17 FIR Filter Bank A, Coefficient 18 FIR Filter Bank A, Coefficient 19 FIR Filter Bank A, Coefficient 20 FIR Filter Bank A, Coefficient 21 FIR Filter Bank A, Coefficient 22 FIR Filter Bank A, Coefficient 23 FIR Filter Bank A, Coefficient 24 FIR Filter Bank A, Coefficient 25 FIR Filter Bank A, Coefficient 26 FIR Filter Bank A, Coefficient 27 FIR Filter Bank A, Coefficient 28 FIR Filter Bank A, Coefficient 29 FIR Filter Bank A, Coefficient 30 FIR Filter Bank A, Coefficient 31 Reserved Page identifier FIR Filter Bank B, Coefficient 0 FIR Filter Bank B, Coefficient 1 FIR Filter Bank B, Coefficient 2 FIR Filter Bank B, Coefficient 3 FIR Filter Bank B, Coefficient 4 FIR Filter Bank B, Coefficient 5 FIR Filter Bank B, Coefficient 6 FIR Filter Bank B, Coefficient 7 FIR Filter Bank B, Coefficient 8 FIR Filter Bank B, Coefficient 9 FIR Filter Bank B, Coefficient 10 FIR Filter Bank B, Coefficient 11 FIR Filter Bank B, Coefficient 12 FIR Filter Bank B, Coefficient 13 FIR Filter Bank B, Coefficient 14 FIR Filter Bank B, Coefficient 15 FIR Filter Bank B, Coefficient 16 FIR Filter Bank B, Coefficient 17 FIR Filter Bank B, Coefficient 18 FIR Filter Bank B, Coefficient 19 FIR Filter Bank B, Coefficient 20 Data Sheet Register Name FIR_COEF_B21 FIR_COEF_B22 FIR_COEF_B23 FIR_COEF_B24 FIR_COEF_B25 FIR_COEF_B26 FIR_COEF_B27 FIR_COEF_B28 FIR_COEF_B29 FIR_COEF_B30 FIR_COEF_B31 Reserved PAGE_ID FIR_COEF_C00 FIR_COEF_C01 FIR_COEF_C02 FIR_COEF_C03 FIR_COEF_C04 FIR_COEF_C05 FIR_COEF_C06 FIR_COEF_C07 FIR_COEF_C08 FIR_COEF_C09 FIR_COEF_C10 FIR_COEF_C11 FIR_COEF_C12 FIR_COEF_C13 FIR_COEF_C14 FIR_COEF_C15 FIR_COEF_C16 FIR_COEF_C17 FIR_COEF_C18 FIR_COEF_C19 FIR_COEF_C20 FIR_COEF_C21 FIR_COEF_C22 FIR_COEF_C23 FIR_COEF_C24 FIR_COEF_C25 FIR_COEF_C26 FIR_COEF_C27 FIR_COEF_C28 FIR_COEF_C29 FIR_COEF_C30 FIR_COEF_C31 Reserved PAGE_ID FIR_COEF_D00 FIR_COEF_D01 FIR_COEF_D02 FIR_COEF_D03 FIR_COEF_D04 FIR_COEF_D05 ADcmXL1021-1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W N/A R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W N/A R/W R/W R/W R/W R/W R/W R/W Flash Backup Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes N/A No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes N/A No Yes Yes Yes Yes Yes Yes PAGE_ID 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x04 0x04 0x04 0x04 0x04 0x04 0x04 Address 0x2C, 0x2D 0x2E, 0x2F 0x30, 0x31 0x32, 0x33 0x34, 0x35 0x36, 0x37 0x38, 0x39 0x3A, 0x3B 0x3C, 0x3D 0x3E, 0x3F 0x40, 0x41 0x42 to 0x7F 0x00, 0x01 0x02, 0x03 0x04, 0x05 0x06, 0x07 0x08, 0x09 0x0A, 0x0B 0x0C, 0x0D 0x0E, 0x0F 0x10, 0x11 0x12, 0x13 0x14, 0x15 0x16, 0x17 0x18, 0x19 0x1A, 0x1B 0x1C, 0x1D 0x1E, 0x1F 0x20, 0x21 0x22, 0x23 0x24, 0x25 0x26, 0x27 0x28, 0x29 0x2A, 0x2B 0x2C, 0x2D 0x2E, 0x2F 0x30, 0x31 0x32, 0x33 0x34, 0x35 0x36, 0x37 0x38, 0x39 0x3A, 0x3B 0x3C, 0x3D 0x3E, 0x3F 0x40, 0x41 0x42 to 0x7F 0x00, 0x01 0x02, 0x03 0x04, 0x05 0x06, 0x07 0x08, 0x09 0x0A, 0x0B 0x0C, 0x0D Default 0x02E1 0x006B 0XFEFE 0xFE76 0XFE8C 0xFEF1 0xFF62 0xFFB9 0xFFEC 0x0001 0x0004 N/A 0x0003 0x0025 0x005A 0x008F 0x009A 0x004D 0xFF8D 0xFE74 0xFD5D 0xFCDD 0xFD97 0x0003 0x0430 0x09A2 0x0F5F 0x142C 0x16E8 0x16E8 0x142C 0x0F5F 0x09A2 0x0430 0x0003 0xFD97 0xFCDD 0xFD5D 0xFE74 0xFF8D 0x004D 0x009A 0x008F 0x005A 0x0025 N/A 0x0004 0xFD94 0xFD62 0xFD2A 0xFCE8 0xFC9C 0xFC43 Rev. 0 | Page 25 of 42 Register Description FIR Filter Bank B, Coefficient 21 FIR Filter Bank B, Coefficient 22 FIR Filter Bank B, Coefficient 23 FIR Filter Bank B, Coefficient 24 FIR Filter Bank B, Coefficient 25 FIR Filter Bank B, Coefficient 26 FIR Filter Bank B, Coefficient 27 FIR Filter Bank B, Coefficient 28 FIR Filter Bank B, Coefficient 29 FIR Filter Bank B, Coefficient 30 FIR Filter Bank B, Coefficient 31 Reserved Page identifier FIR Filter Bank C, Coefficient 0 FIR Filter Bank C, Coefficient 1 FIR Filter Bank C, Coefficient 2 FIR Filter Bank C, Coefficient 3 FIR Filter Bank C, Coefficient 4 FIR Filter Bank C, Coefficient 5 FIR Filter Bank C, Coefficient 6 FIR Filter Bank C, Coefficient 7 FIR Filter Bank C, Coefficient 8 FIR Filter Bank C, Coefficient 9 FIR Filter Bank C, Coefficient 10 FIR Filter Bank C, Coefficient 11 FIR Filter Bank C, Coefficient 12 FIR Filter Bank C, Coefficient 13 FIR Filter Bank C, Coefficient 14 FIR Filter Bank C, Coefficient 15 FIR Filter Bank C, Coefficient 16 FIR Filter Bank C, Coefficient 17 FIR Filter Bank C, Coefficient 18 FIR Filter Bank C, Coefficient 19 FIR Filter Bank C, Coefficient 20 FIR Filter Bank C, Coefficient 21 FIR Filter Bank C, Coefficient 22 FIR Filter Bank C, Coefficient 23 FIR Filter Bank C, Coefficient 24 FIR Filter Bank C, Coefficient 25 FIR Filter Bank C, Coefficient 26 FIR Filter Bank C, Coefficient 27 FIR Filter Bank C, Coefficient 28 FIR Filter Bank C, Coefficient 29 FIR Filter Bank C, Coefficient 30 FIR Filter Bank C, Coefficient 31 Reserved Page identifier FIR Filter Bank D, Coefficient 0 FIR Filter Bank D, Coefficient 1 FIR Filter Bank D, Coefficient 2 FIR Filter Bank D, Coefficient 3 FIR Filter Bank D, Coefficient 4 FIR Filter Bank D, Coefficient 5 ADcmXL1021-1 Register Name FIR_COEF_D06 FIR_COEF_D07 FIR_COEF_D08 FIR_COEF_D09 FIR_COEF_D10 FIR_COEF_D11 FIR_COEF_D12 FIR_COEF_D13 FIR_COEF_D14 FIR_COEF_D15 FIR_COEF_D16 FIR_COEF_D17 FIR_COEF_D18 FIR_COEF_D19 FIR_COEF_D20 FIR_COEF_D21 FIR_COEF_D22 FIR_COEF_D23 FIR_COEF_D24 FIR_COEF_D25 FIR_COEF_D26 FIR_COEF_D27 FIR_COEF_D28 FIR_COEF_D29 FIR_COEF_D30 FIR_COEF_D31 Reserved PAGE_ID FIR_COEF_E00 FIR_COEF_E01 FIR_COEF_E02 FIR_COEF_E03 FIR_COEF_E04 FIR_COEF_E05 FIR_COEF_E06 FIR_COEF_E07 FIR_COEF_E08 FIR_COEF_E09 FIR_COEF_E10 FIR_COEF_E11 FIR_COEF_E12 FIR_COEF_E13 FIR_COEF_E14 FIR_COEF_E15 FIR_COEF_E16 FIR_COEF_E17 FIR_COEF_E18 FIR_COEF_E19 FIR_COEF_E20 FIR_COEF_E21 FIR_COEF_E22 FIR_COEF_E23 FIR_COEF_E24 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W N/A R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Data Sheet Flash Backup Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes N/A No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes PAGE_ID 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 Address 0x0E, 0x0F 0x10, 0x11 0x12, 0x13 0x14, 0x15 0x16, 0x17 0x18, 0x19 0x1A, 0x1B 0x1C, 0x1D 0x1E, 0x1F 0x20, 0x21 0x22, 0x23 0x24, 0x25 0x26, 0x27 0x28, 0x29 0x2A, 0x2B 0x2C, 0x2D 0x2E, 0x2F 0x30, 0x31 0x32, 0x33 0x34, 0x35 0x36, 0x37 0x38, 0x39 0x3A, 0x3B 0x3C, 0x3D 0x3E, 0x3F 0x40, 0x41 0x42 to 0x7F 0x00, 0x01 0x02, 0x03 0x04, 0x05 0x06, 0x07 0x08, 0x09 0x0A, 0x0B 0x0C, 0x0D 0x0E, 0x0F 0x10, 0x11 0x12, 0x13 0x14, 0x15 0x16, 0x17 0x18, 0x19 0x1A, 0x1B 0x1C, 0x1D 0x1E, 0x1F 0x20, 0x21 0x22, 0x23 0x24, 0x25 0x26, 0x27 0x28, 0x29 0x2A, 0x2B 0x2C, 0x2D 0x2E, 0x2F 0x30, 0x31 0x32, 0x33 Default 0xFBD7 0xFB52 0xFAAB 0xF9D2 0xF8AB 0xF702 0xF468 0xEFBC 0xE4DC 0xAE85 0x517B 0x1B24 0x1044 0x0B98 0x08FE 0x0755 0x062E 0x0555 0x04AE 0x0429 0x03BD 0x0364 0x0318 0x02D6 0x029E 0x026C N/A 0x0005 0xFF2B 0xFEF0 0xFEAA 0xFE59 0xFDFB 0xFD8C 0xFD09 0xFC6B 0xFBA8 0xFAB1 0xF96B 0xF7A1 0xF4E5 0xF017 0xE512 0xAE97 0x5169 0x1AEE 0x0FE9 0x0B1B 0x085F 0x0695 0x054F 0x0458 0x0395 Rev. 0 | Page 26 of 42 Register Description FIR Filter Bank D, Coefficient 6 FIR Filter Bank D, Coefficient 7 FIR Filter Bank D, Coefficient 8 FIR Filter Bank D, Coefficient 9 FIR Filter Bank D, Coefficient 10 FIR Filter Bank D, Coefficient 11 FIR Filter Bank D, Coefficient 12 FIR Filter Bank D, Coefficient 13 FIR Filter Bank D, Coefficient 14 FIR Filter Bank D, Coefficient 15 FIR Filter Bank D, Coefficient 16 FIR Filter Bank D, Coefficient 17 FIR Filter Bank D, Coefficient 18 FIR Filter Bank D, Coefficient 19 FIR Filter Bank D, Coefficient 20 FIR Filter Bank D, Coefficient 21 FIR Filter Bank D, Coefficient 22 FIR Filter Bank D, Coefficient 23 FIR Filter Bank D, Coefficient 24 FIR Filter Bank D, Coefficient 25 FIR Filter Bank D, Coefficient 26 FIR Filter Bank D, Coefficient 27 FIR Filter Bank D, Coefficient 28 FIR Filter Bank D, Coefficient 29 FIR Filter Bank D, Coefficient 30 FIR Filter Bank D, Coefficient 31 Reserved Page identifier FIR Filter Bank E, Coefficient 0 FIR Filter Bank E, Coefficient 1 FIR Filter Bank E, Coefficient 2 FIR Filter Bank E, Coefficient 3 FIR Filter Bank E, Coefficient 4 FIR Filter Bank E, Coefficient 5 FIR Filter Bank E, Coefficient 6 FIR Filter Bank E, Coefficient 7 FIR Filter Bank E, Coefficient 8 FIR Filter Bank E, Coefficient 9 FIR Filter Bank E, Coefficient 10 FIR Filter Bank E, Coefficient 11 FIR Filter Bank E, Coefficient 12 FIR Filter Bank E, Coefficient 13 FIR Filter Bank E, Coefficient 14 FIR Filter Bank E, Coefficient 15 FIR Filter Bank E, Coefficient 16 FIR Filter Bank E, Coefficient 17 FIR Filter Bank E, Coefficient 18 FIR Filter Bank E, Coefficient 19 FIR Filter Bank E, Coefficient 20 FIR Filter Bank E, Coefficient 21 FIR Filter Bank E, Coefficient 22 FIR Filter Bank E, Coefficient 23 FIR Filter Bank E, Coefficient 24 Data Sheet Register Name FIR_COEF_E25 FIR_COEF_E26 FIR_COEF_E27 FIR_COEF_E28 FIR_COEF_E29 FIR_COEF_E30 FIR_COEF_E31 Reserved PAGE_ID FIR_COEF_F00 FIR_COEF_F01 FIR_COEF_F02 FIR_COEF_F03 FIR_COEF_F04 FIR_COEF_F05 FIR_COEF_F06 FIR_COEF_F07 FIR_COEF_F08 FIR_COEF_F09 FIR_COEF_F10 FIR_COEF_F11 FIR_COEF_F12 FIR_COEF_F13 FIR_COEF_F14 FIR_COEF_F15 FIR_COEF_F16 FIR_COEF_F17 FIR_COEF_F18 FIR_COEF_F19 FIR_COEF_F20 FIR_COEF_F21 FIR_COEF_F22 FIR_COEF_F23 FIR_COEF_F24 FIR_COEF_F25 FIR_COEF_F26 FIR_COEF_F27 FIR_COEF_F28 FIR_COEF_F29 FIR_COEF_F30 FIR_COEF_F31 Reserved ADcmXL1021-1 R/W R/W R/W R/W R/W R/W R/W R/W N/A R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W N/A Flash Backup Yes Yes Yes Yes Yes Yes Yes N/A No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes N/A PAGE_ID 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x06 0x06 0x06 0x06 0x06 0x06 0x06 0x06 0x06 0x06 0x06 0x06 0x06 0x06 0x06 0x06 0x06 0x06 0x06 0x06 0x06 0x06 0x06 0x06 0x06 0x06 0x06 0x06 0x06 0x06 0x06 0x06 0x06 0x06 Address 0x34, 0x35 0x36, 0x37 0x38, 0x39 0x3A, 0x3B 0x3C, 0x3D 0x3E, 0x3F 0x40, 0x41 0x42 to 0x7F 0x00, 0x01 0x02, 0x03 0x04, 0x05 0x06, 0x07 0x08, 0x09 0x0A, 0x0B 0x0C, 0x0D 0x0E, 0x0F 0x10, 0x11 0x12, 0x13 0x14, 0x15 0x16, 0x17 0x18, 0x19 0x1A, 0x1B 0x1C, 0x1D 0x1E, 0x1F 0x20, 0x21 0x22, 0x23 0x24, 0x25 0x26, 0x27 0x28, 0x29 0x2A, 0x2B 0x2C, 0x2D 0x2E, 0x2F 0x30, 0x31 0x32, 0x33 0x34, 0x35 0x36, 0x37 0x38, 0x39 0x3A, 0x3B 0x3C, 0x3D 0x3E, 0x3F 0x40, 0x41 0x42 to 0x7F Default 0x02F7 0x0274 0x0205 0x01A7 0x0156 0x0110 0x00D5 N/A 0x0006 0xFFD9 0xFFB9 0xFF8C 0xFF50 0xFF02 0xFE9E 0xFE1F 0xFD7D 0xFCB0 0xFBA8 0xFA49 0xF861 0xF581 0xF089 0xE558 0xAEAF 0x5151 0x1AA8 0x0F77 0x0A7F 0x079F 0x05B7 0x0458 0x0350 0x0283 0x01E1 0x0162 0x00FE 0x00B0 0x0074 0x0047 0x0027 N/A Register Description FIR Filter Bank E, Coefficient 25 FIR Filter Bank E, Coefficient 26 FIR Filter Bank E, Coefficient 27 FIR Filter Bank E, Coefficient 28 FIR Filter Bank E, Coefficient 29 FIR Filter Bank E, Coefficient 30 FIR Filter Bank E, Coefficient 31 Reserved Page identifier FIR Filter Bank F, Coefficient 0 FIR Filter Bank F, Coefficient 1 FIR Filter Bank F, Coefficient 2 FIR Filter Bank F, Coefficient 3 FIR Filter Bank F, Coefficient 4 FIR Filter Bank F, Coefficient 5 FIR Filter Bank F, Coefficient 6 FIR Filter Bank F, Coefficient 7 FIR Filter Bank F, Coefficient 8 FIR Filter Bank F, Coefficient 9 FIR Filter Bank F, Coefficient 10 FIR Filter Bank F, Coefficient 11 FIR Filter Bank F, Coefficient 12 FIR Filter Bank F, Coefficient 13 FIR Filter Bank F, Coefficient 14 FIR Filter Bank F, Coefficient 15 FIR Filter Bank F, Coefficient 16 FIR Filter Bank F, Coefficient 17 FIR Filter Bank F, Coefficient 18 FIR Filter Bank F, Coefficient 19 FIR Filter Bank F, Coefficient 20 FIR Filter Bank F, Coefficient 21 FIR Filter Bank F, Coefficient 22 FIR Filter Bank F, Coefficient 23 FIR Filter Bank F, Coefficient 24 FIR Filter Bank F, Coefficient 25 FIR Filter Bank F, Coefficient 26 FIR Filter Bank F, Coefficient 27 FIR Filter Bank F, Coefficient 28 FIR Filter Bank F, Coefficient 29 FIR Filter Bank F, Coefficient 30 FIR Filter Bank F, Coefficient 31 Reserved N/A means not applicable. The PAGE_ID register can be written to change the target register location but does not change values on the defined page in the PAGE_ID register. 3 The default value is valid until the first capture event, when the measurement data replaces the default value. 4 For these registers, values can be stored in flash but are not available for readback until ALM_PNTR is set. 5 Register values can be retrieved from records stored in flash using record retrieve commands. 1 2 Rev. 0 | Page 27 of 42 ADcmXL1021-1 Data Sheet USER REGISTER DETAILS PAGE_ID, PAGE NUMBER SUPPLY_OUT, POWER SUPPLY VOLTAGE The contents in the PAGE_ID register (see Table 20 and Table 21) contain the current page setting. The ADcmXL1021-1 has output and control registers split over seven pages, numbered from zero to six. Page 1 to Page 6 are the configurable filter coefficients. Page 0 contains user registers for various configuration options and outputs. The SUPPLY_OUT register (see Table 25 and Table 26) provides a measurement (uncalibrated) of the voltage between the VDD and GND pins at the start of a data capture event, when the ADcmXL1021-1 is operating in the MFFT, AFFT, or MTC mode of operation (see Table 47). Table 27 shows several examples of the data format for the SUPPLY_OUT register. As an example, write 0x8002 to select Page 2 for SPI-based user access. After the register map is pointed to Page 2, any register writes are used to configure the Filter Bank B coefficients. The ADcmXL1021-1 user register map (see Table 19) provides a functional summary of each page and the page assignments associated with each user accessible register. Page 0x00 Table 20. PAGE_ID Register Definition Table 26. SUPPLY_OUT Bit Descriptions Page1 0x0000 1 Addresses 0x00, 0x01 Default 0x0000 Access R/W Table 21. PAGE_ID Bit Descriptions The TEMP_OUT register (see Table 22 and Table 23) provides a measurement (uncalibrated) of the temperature inside of the unit at the conclusion of a data capture or analysis event, when the ADcmXL1021-1 is operating in the MFFT, AFFT, or MTC mode of operation (see Table 47). Table 24 shows several examples of the data format for the TEMP_OUT register. The TEMP_OUT value is related to the sensed temperature by the following relationship: TEMP_OUT = (Temperature - 460C)/(-0.46C/LSB) Table 22. TEMP_OUT Register Definition 1 Addresses 0x02, 0x03 Default 0x80001 Access R Flash Backup No The default value is valid until the first capture event, when the measurement data replaces the default value. Table 23. TEMP_OUT Bit Definitions Bits [15:0] Description Internal temperature data. Offset binary format is twos complement, 1 LSB = -0.46C, and there is an offset of +460C, except in RTC mode. Table 24. TEMP_OUT Data Format Examples Temperature +105C +60C +20C +0C -40C Decimal 772 870 957 1000 1087 Hexadecimal 0x0303 0x0365 0x03BC 0x03E8 0x043F Default 0x80001 Access R Flash Backup No Default value is valid until the first capture event, when the measurement data replaces the default value Description Do not use Voltage between VDD and GND pins. 0x0000 = 0 V, 1 LSB = 3.22 mV. Table 27. Power Supply Data Format Examples Description Page number, binary numerical format TEMP_OUT, INTERNAL TEMPERATURE Page 0x00 1 Addresses 0x04, 0x05 Bits [15:12] [11:0] Flash Backup No This register is located at Address 0x00 and Address 0x01 of each page. Bits [15:0] Table 25. SUPPLY_OUT Register Definition Binary 0000 0011 0000 0011 0000 0011 0110 0101 0000 0011 1011 1100 0000 0011 1110 1000 0000 0100 0011 1111 Supply Level (V) 3.6 3.3 + 0.003226 3.3 3.3 - 0.003226 3.0 LSB 1117 1025 1024 1023 930 Hexadecimal 0x45D 0x401 0x400 0x3FF 0x3A2 Binary 0100 0101 1101 0100 0000 0001 0100 0000 0000 0011 1111 1111 0011 1010 0010 FFT_AVG1, SPECTRAL AVERAGING The FFT_AVG1 register (see Table 28 and Table 29) contains the user-configurable, spectral averaging settings for the SR0 and SR1 sample rate settings (see the AVG_CNT register in Table 68). These settings determine the number of FFT records that the ADcmXL1021-1 averages when generating the final FFT result. When using the factory default value for the FFT_AVG1 register, the FFT result for the sample rate, SR0, contains an average of eight separate FFT records. The FFT result for the SR1 sample rate contains a single FFT record (no spectral averaging). Increasing the number of FFT averages increases the overall time for a record to be generated. The FFT averaging sequence is as follows: 4096 samples are measured, FFT on 4096 samples, accumulate FFT result, repeat until the number of FFTs specified in FFT_AVG1 or FFT_AVG2 is reached. Then, compute the average FFT, average power supply, and average temperature. The power supply and temperature are measured after the 4096 samples are captured each time and accumulated. Table 28. FFT_AVG1 Register Definition Addresses 0x06, 0x07 Rev. 0 | Page 28 of 42 Default 0x0108 Access R/W Flash Backup Yes Data Sheet ADcmXL1021-1 Table 29. FFT_AVG1 Bit Descriptions BUF_PNTR, BUFFER POINTER Bits [15:8] The BUF_PNTR (see Table 34 and Table 35) controls the data sample that loads to the OUT_BUF register (see Table 39) from the user data buffers. The BUF_PNTR register contains 0x0000 at the conclusion of each capture event and increments with each read of the OUT_BUF register. When BUF_PNTR contains the maximum value (2047 or 4095, see Table 35), the next increment (caused by a read request OUT_BUF) causes the value in the BUF_PNTR register to wrap around to 0x0000. The depth of the user data buffer and, therefore, the range of numbers that BUF_PNTR supports, depends on the mode of operation, according to the setting in the REC_CTRL register, Bit 0 and Bit 1 (see Table 47). [7:0] Description Number of records, SR1, 8 bit unsigned format, range: 1 to 255 Number of records, SR0, 8 bit unsigned format, range: 1 to 255 To eliminate averaging on both SR0 and SR1 settings, set FFT_AVG1 = 0x0101 by using the following codes (in order) for the DIN serial string: 0x8601 and 0x8701. Table 30 shows three more examples of FFT_AVG1 settings, the number of records that each setting corresponds to that produces each FFT_AVG1 value. Table 30. FFT_AVG1 Formatting Examples FFT_AVG1 Value 0x040C 0x0E1A 0xFF42 SR0 12 26 66 Table 34. BUF_PNTR Register Definition Number of FFT Records SR1 4 14 255 Addresses 0x0A, 0x0B Default 0x0000 Access R/W Flash Backup No Table 35. BUF_PNTR Bit Descriptions Bits [15:12] [11:0] FFT_AVG2, SPECTRAL AVERAGING The FFT_AVG2 register (see Table 31 and Table 32) contains the user-configurable, spectral averaging settings for the SR2 and SR3 sample rate settings (see the AVG_CNT register in Table 68). These settings determine the number of FFT records that the ADcmXL1021-1 averages when generating the final FFT result. When using the factory default value for the FFT_AVG2 register, the FFT result for the SR2 and SR3 sample rates contains a single FFT record (no spectral averaging). Description Set these bits to 0, when writing to this register. Buffer pointer value. Range = 0 to 2047 (in MFFT mode or AFFT mode). Range = 0 to 4095 (in MTC mode). Writing a number to the BUF_PNTR register causes that sample number for user data buffer to load to the OUT_BUF register. For example, using the following code sequence on DIN writes 0x031C to the BUF_PNTR register: 0x8A1C and 0x8B03. This write causes the sample pointer to output (796) from the user data buffer to load to OUT_BUF (see Figure 43). XL DATA 0 Table 31. FFT_AVG2 Register Definition Addresses 0x08, 0x09 Default 0x0101 Access R/W Flash Backup Yes 796 OUT_BUF Table 32. FFT_AVG2 Bit Descriptions [7:0] Description Number of records, SR3, 8 bit unsigned format, range: 1 to 255 Number of records, SR2, 8 bit unsigned format, range: 1 to 255 To configure the ADcmXL1021-1 to average two FFT records for both SR2 and SR3 settings, set FFT_AVG2 = 0x0202 by using the following codes (in order) for the DIN serial string: 0x8802 and 0x8702. Table 33 shows three more examples of FFT_AVG2 settings, the number of records that each setting corresponds to, and the DIN code sequence that produces each FFT_AVG2 value. 2047 USER DATA BUFFERS Figure 43. Register Activity, BUF_PNTR = 0x031C (MFFT Mode or AFFT Mode) Table 33. FFT_AVG2 Formatting Examples FFT_AVG2 Value 0x0407 0x0D50 0x2FFA SR2 7 80 250 21125-034 Bits [15:8] Number of FFT Records SR3 4 13 47 Rev. 0 | Page 29 of 42 ADcmXL1021-1 Data Sheet REC_PNTR, RECORD POINTER OUT_BUF, BUFFER ACCESS REGISTER The REC_PNTR register (see Table 36 and Table 37) provides access to the statistical metrics from MTC capture events and spectral records from MFFT or AFFT capture events in the data storage bank. Each spectral analysis record in the data storage bank has a number from 0 to 9 that identifies the number to write to the REC_PNTR register, Bits[3:0]. This write loads that spectral record to the user data buffers. After the data from the spectral record is in the user data buffers, the BUF_PNTR register (see Table 35) and OUT_BUF register (see Table 39) provide access to the data in the specified data record through the SPI. For example, using the following DIN codes to set REC_PNTR = 0x0007 causes Spectral Record 7 to load to the user data buffers. See Table 38 for additional examples. The OUT_BUF register (see Table 39 and Table 40) provides access to vibration data. When operating in MTC, MFFT, or AFFT mode, OUT_BUF contains the accelerometer data sample from the user data buffer, which the BUF_PNTR register (see Table 35) commands. In RTS mode, data is streamed out from the SPI interface, and data buffers of the registers are not used. Each statistical record in the data storage bank has a number from 0 through 31 that identifies the number to write to the REC_PNTR register, Bits[12:8]. This write loads that statistical record to the user statistical buffers. After the data from a statistical record is in the user statistical buffers, the STAT_PNTR register (see Table 105), statistic register (see Table 107) provide access to this data through the SPI. For example, using the following DIN codes to set REC_PNTR = 0x0B00 causes Statistical Record 11 to load to the user statistical buffers: 0x8C00 and 0x8D0B. See Table 38 for additional examples. Table 36. REC_PNTR Register Definition Addresses 0x0C, 0x0D Default 0x0000 Access R/W Flash Backup No Table 37. REC_PNTR Bit Descriptions Bits [15:12] [12:8] [7:4] [3:0] Description Set these bits to 0 when writing to this register Record number, statistics (from MTC mode only), range = 0 to 31 Set these bits to 0 when writing to this register Record number, spectral records, range = 0 to 9 (from MFFT mode and AFFT mode only) Table 38. REC_PNTR Example Use Cases DIN Codes 0x8C05 REC_PNTR Value 0x0005 0x8D0C 0x0C00 0x8C03, 0x8D15 0x1503 Description Spectral Record 5 loads to the user data buffer. Statistical Record 12 loads to the user statistics buffer. Spectral Record 3 loads to the user data buffer and Statistical Record 21 loads to the user statistics buffer. In modes other than RTS when data is stored, after a read of the upper byte and lower byte, the buffer automatically updates with the next data sample in the internal buffer, the BUF_ PNTR is auto-incremented. For MTC mode, the buffer can support 4096 time domain samples, and BUF_PNTR can advance from 0 to 4095. For AFFT and MFFT mode, the buffer supports 2048 FFT bin values, and BUF_PNTR can advance from 0 to 2047. Table 39. OUT_BUF Register Definition Addresses 0x12, 0x13 1 Default1 0x8000 Access R/W Flash Backup No The default value changes to 0x8000 when entering the first capture event and is only valid until completion of the first capture event or commencement of RTS mode. Table 40. OUT_BUF Bit Descriptions Bits [15:0] Description Output data The numerical format of the data in OUT_BUF depends on the mode of operation (see the REC_CTRL register, Bits[1:0] in Table 47). When operating in MTC mode (REC_CTRL, Bits[1:0] = 10), the data in the OUT_BUF register uses a 16-bit, offset binary format, where 1 LSB represents ~0.001907 g. This format provides enough numerical range to support the measurement range (50 g) and the maximum bias/offset from the core sensor. Table 41 shows several examples of how to translate these codes to the acceleration magnitude that the examples represent for MTC mode, assuming nominal sensitivity and zero bias error. MTC mode data in the OUT_BUF register uses a 16-bit, twos complement format, where 1 LSB represents ~0.001907 g. This format provides enough numerical range to support the measurement range (50 g) and the maximum bias and offset from the core sensor. Table 41 shows several examples of how to translate these codes into the acceleration magnitude that the codes represent, assuming nominal sensitivity and zero bias error. If velocity calculations are enabled using Bit 5 in the REC_CTRL register, calculated velocity data is stored in place of default acceleration value. Data format examples are shown in Table 42. Rev. 0 | Page 30 of 42 Data Sheet ADcmXL1021-1 Table 41. MTC Mode Data Format Examples ANULL, BIAS CALIBRATION REGISTER Acceleration (g) +62.4867 +50 +0.003814 +0.001907 0 -0.001907 -0.003814 -50 -62.4886 The ANULL register (see Table 44 and Table 45) contains the bias correction value for the accelerometer, which the auto-null command (see the GLOB_CMD register, Bit 0, in Table 73) generates. The ANULL register also supports write access, which enables users to write their own correction factors to the output signal chain. The numerical format examples from Table 41 also apply to the ANULL register. For example, writing the following codes to DIN sets ANULL = 0xFDDE, which adjusts the offset of the output signal chain by -546 LSB (~1.042 g = 1 g / 524 LSBs x 546 LSBs): 0x98DE and 0x99FD. LSB +32,767 +26,219 +2 +1 0 -1 -2 -26,220 -32,768 Hexadecimal 0x7FFF 0x666B 0x0002 0x0001 0x0000 0xFFFF 0xFFFE 0x9995 0x8000 Binary 0111 1111 1111 1111 0110 0110 0110 1011 0000 0000 0000 0010 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1110 1001 1001 1001 0101 1000 0000 0000 0000 Table 42. MTC Mode Data Format Examples, Velocity Calculations Enabled Velocity (mm/sec) +610,121.5 +487,844 +37.24 +18.62 0 -18.62 -37.24 -487,844 -610,121.5 LSB +32,767 +26,200 +2 +1 0 -1 -2 -26,200 -32,768 Hexadecimal 0x7FFF 0x6658 0x0002 0x0001 0x0000 0xFFFF 0xFFFE 0x99A8 0x8000 Table 44. ANULL Register Definition Binary 0111 1111 1111 1111 0110 0110 0101 1000 0000 0000 0000 0010 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1110 1001 1001 1010 0111 1000 0000 0000 0000 When operating in the FFT modes, either MFFT mode (REC_ CTRL1, Bits[1:0] = 00) or AFFT mode (REC_CTRL, Bits[1:0] = 01), the OUT_BUF register uses a 16-bit, unsigned binary format. Due to the increased resolution capability of FFT values because of averaging, converting the OUT_BUF value to acceleration is accomplished by using the following equation: OUT _ BUF 2 2048 Output (mg) = x 0.9535 mg Number of FFT Averages Table 43 shows the conversion from OUT_BUF value to acceleration. Addresses 0x18, 0x19 OUT_BUF Value 32767 26200 200 1 39000 30000 8 2048 2048 Number of FFT Averages 1 1 1 1 8 8 8 2 1 Access R/W Flash Backup Yes Table 45. ANULL Bit Descriptions Bits [15:0] Description Bias correction factor. Twos complement, 1 LSB = 0.001907 g. REC_CTRL, RECORDING CONTROL The REC_CTRL register (see Table 46 and Table 47) contains the configuration bits for a number of operational settings in the ADcmXL1021-1: mode of operation, record storage, power management, sample rates, and windowing. Table 46. REC_CTRL Register Definitions Addresses 0x1A, 0x1B Default 0x1102 Access R/W Flash Backup Yes Table 47. REC_CTRL Bit Descriptions Bits 15 14 [13:12] Table 43. Spectral Analysis Data Format Examples Acceleration (mg) 62467.43 6766.87 1.02 0.95 64377.71 3060.90 0.12 0.95 1.91 Default 0x0000 11 10 9 8 7 Rev. 0 | Page 31 of 42 Description Real-time streaming timeout enable. Not used. Window setting (MFFT mode and AFFT modes only). 00 = rectangular. 01 = Hanning (default). 10 = flat top. 11 = not applicable. SR3, Sample Rate Option 3, enable = 1, disable = 0. Sample rate = 220 kSPS / 2AVG_CNT[15:12] (see Table 68). SR2, Sample Rate Option 2, enable = 1, disable = 0. Sample rate = 220 kSPS / 2AVG_CNT[11:8] (see Table 68). SR1, Sample Rate Option 1, enable = 1, disable = 0. Sample rate = 220 kSPS / 2AVG_CNT[7:4] (see Table 68). SR0, Sample Rate Option 0, enable = 1, disable = 0. Sample rate = 220 kSPS / 2AVG_CNT[3:0] (see Table 68). Automatic power-down between recordings (MFFT, AFFT, and MTC mode only). Requires a CS toggle to wake up. 0 = no power-down. 1 = power-down after data collection/processing. ADcmXL1021-1 Bits 6 5 4 [3:2] [1:0] Data Sheet Description Enable compute statistics in MTC mode. Enable velocity calculations. 0 = acceleration. 1 = calculated velocity. Reserved. Flash memory record storage method (MFFT, AFFT, and MTC modes only). 00 = none. No record storage to flash memory, current data is available in SRAM until the next recording event is stored. 01 = alarm triggered. Record storage occurs when the vibration exceeds one of the configurable alarm settings. 10 = all. Record storage happens at the conclusion of each data collection and processing event. 11 = reserved. Recording mode. 00 = MFFT mode. 01 = AFFT mode. 10 = MTC mode. 11 = RTS mode. Real-Time Burst Mode Timeout Enabled Bit 15 in the REC_CTRL register (see Table 47) contains the settings that independently disable RTS mode if the available data is not read. By default, RTS mode is enabled and disabled via the digital pin, RTS. If this bit is enabled, RTS mode is halted after failure to receive SCLK on five consecutive data ready active periods. Windowing Bits[13:12] in the REC_CTRL register (see Table 47) contain the settings for the window function that the ADcmXL1021-1 uses on the time domain data, prior to performing the FFT. The factory default setting for these bits (01) selects the Hanning window function. The other window options available are rectangular (setting 0b00), or flat top (setting 0b10). Spectral Record Selection Bits[11:8] in the REC_CTRL register (see Table 47) contain on and off settings for the four different sample rate options that are set using the AVG_CNT register. The sample rate selector bits (SR0, SR1, SR2, and SR3) are used when operating in MFFT, AFFT, or MTC mode. When only one of these bits is set to 1, every data capture event uses that sample rate setting. When two of the bits are set to 1, the ADcmXL1021-1 uses one of the sample rates for one data capture event, and then switches to the other for the next capture event. When all four bits are set to 1, the ADcmXL1021-1 uses the sample rates in the following order when switching to a new sample rate for each new capture events: SR0, SR1, SR2, SR3, SR0, SR1, and so on. Automatic Power-Down Bit 7 in the REC_CTRL register (see Table 47) contains the setting for the automated power-down function when the ADcmXL1021-1 is operating in MFFT, AFFT, or MTC mode. When this bit is set to 1, the ADcmXL1021-1 automatically powers down after completing data collection and processing. When this bit is set to 0, the ADcmXL1021-1 does not power down after completing data collection and processing functions. After the device is in sleep mode, a CS toggle is required to wake up before the next measurement can be used. If the device is powered down between records in AFFT mode, wake up occurs automatically before the next capture. Calculate MTC Statistics Bit 6 in the REC_CTRL register (see Table 47) contains the setting to enable statistic calculation on MTC records Calculate Velocity Bit 5 in the REC_CTRL register (see Table 47) contains the setting to convert accelerometer data values to velocity values. When this bit is set to 0, the user data buffers contain linear acceleration data. When this bit is set to 1, the user data buffers contain linear velocity data, which comes from integrating the acceleration data with respect to time. Record Storage Bits[3:2] in the REC_CTRL register (see Table 47) contain the settings that determine when the ADcmXL1021-1 stores the result of an FFT capture event to a record location. The MISC_ CTRL register is used for storing time domain statistics. Recording Mode Bits[1:0] in the REC_CTRL register (see Table 47) establish the mode of operation. When operating in MTC mode, the ADcmXL1021-1 uses the signal processing diagram and useraccessible registers shown in Figure 27. When operating in AFFT and MFFT mode, the ADcmXL1021-1 uses the signal processing diagram and user-accessible registers shown in Figure 29. REC_PRD, RECORD PERIOD The REC_PRD register (see Table 48 and Table 49) contains the settings for the timer function that the ADcmXL1021-1 uses when operating in AFFT mode. Table 48. REC_PRD Register Definition Addresses 0x1E, 0x1F Default 0x0000 Access R/W Flash Backup Yes Table 49. REC_PRD Bit Descriptions Bits [15:10] [9:8] [7:0] Rev. 0 | Page 32 of 42 Description Don't care Scale for data bits: 00 = 1 second/LSB, 01 = 1 minute/LSB, 10 = 1 hour/LSB Data bits, binary format; range = 0 to 255 Data Sheet ADcmXL1021-1 Setting REC_PRD to 0x0005 establishes a 5 sec setting for the time that elapses between the completion of one capture event and the beginning of the next capture event. Table 50 shows several more examples of configuration codes for the REC_PRD register. Table 50. REC_PRD Example Use Cases REC_PRD Value 0x0022 0x010F 0x0218 Timer Value 34 sec 15 minutes 24 hours ALM_MAG1, ALARM LEVEL 1 Up to six individual spectral alarm bands can be specified with two magnitude alarm levels. The ALM_PNTR register setting identifies which alarm is currently addressed and being configured. Spectral alarms apply when the ADcmXL1021-1 is operating in MFFT or AFFT mode and when the ALM_F_LOW register (see Table 51 and Table 52) contains the number of the lowest FFT bin, which is included in the spectral alarm setting that the ALM_ PNTR register (see Table 60) contains. The value of ALM_F_LOW applies to the FFT spectral record. The exact frequency depends on AVG_CNT register because this register setting reduces the full FFT bandwidth. Table 51. ALM_F_LOW Register Definition Default 0x0000 Access R/W Flash Backup Yes Table 52. ALM_F_LOW Bit Descriptions Bits [15:12] [11:0] For example, when setting ALM_F_LOW = 0x0064, the lower frequency of the alarm band starts at Bin 200. For example, if AVG_CNT = 8, the lower frequency is set to 1200 Hz (1200 Hz = (200 LSB x 220 kHz/8)/4096). If AVG_CNT = 2, the lower frequency is 4800 Hz if ALM_F_LOW = 0x0064. ALM_F_LOW, ALARM FREQUENCY BAND Addresses 0x20, 0x21 The value of ALM_F_LOW applies to the FFT spectral record. The exact frequency depends on the AVG_CNT register because this setting reduces the full FFT bandwidth. The ALM_MAG1 register sets a magnitude limit for the output in which to trigger an alarm warning. A second, higher trigger magnitude can be set in the ALM_MAG2 register and can distinguish between a warning condition vs. a more critical condition. When the ADcmXL1021-1 is operating in MFFT or AFFT mode, the ALM_MAG1 register (see Table 55 and Table 56) contains the magnitude of the vibration, which triggers Alarm 1 for the spectral alarm setting contained in the ALM_ PNTR register (see Table 60). In this mode, the FFT band that is compared to the trigger magnitude limit is between ALM_L_ LOW and ALM_F_HIGH. When in MTC mode, this limit applies to the statistics of the time domain capture. ALM_MAG1 can be used as a warning indicator and ALM_ MAG2 as a critical alarm indicator. Set ALM_MAG2 to a greater or equal value as ALM_MAG1. Table 55. ALM_MAG1 Register Definition Description Don't care Lower frequency, bin number; range = 0 to 2047 Addresses 0x28, 0x29 For example, when setting ALR_F_LOW = 0x0064, the lower frequency of the alarm band starts at Bin 100. For example, if AVG_CNT = 8, the lower frequency is set to 600 Hz (600 Hz = (100 LSB x 220 kHz/8)/4096). Default 0x0000 Access R/W Flash Backup Yes Table 56. ALM_MAG1 Bit Descriptions Bits [15:0] Description Alarm Trigger Level 1 If AVG_CNT = 2, the lower frequency is 2400 Hz if ALM_F_LOW = 0x0064. The data format in the ALM_MAG1 register is the same as the data format in the OUT_BUF register. See Table 43 for several examples of this data format. ALM_F_HIGH, ALARM FREQUENCY BAND ALM_MAG2, ALARM LEVEL 2 When the ADcmXL1021-1 is operating in MFFT or AFFT mode, the ALM_F_HIGH register (see Table 53 and Table 54) contains the number of the highest FFT bin included in the spectral alarm setting. The ALM_PNTR register (see Table 60) contains the information regarding which of the six alarms is being set. When the ADcmXL1021-1 is operating in MFFT or AFFT mode, the ALM_MAG2 register (see Table 57 and Table 58) contains the magnitude of the vibration, which triggers Alarm 2 for the spectral alarm setting that the ALM_PNTR register (see Table 60) contains. When in MTC mode, this limit applies to the statistics of the time domain capture. Table 53. ALM_F_HIGH Register Definition Addresses 0x22, 0x23 Default 0x0000 Access R/W Flash Backup Yes Table 54. ALM_F_HIGH Bit Descriptions Bits [15:12] [11:0] Description Don't care Upper frequency, bin number; range = 0 to 2047 Table 57. ALM_MAG2 Register Definition Addresses 0x2E, 0x2F Default 0x0000 Access R/W Table 58. ALM_MAG2 Bit Descriptions Bits [15:0] Rev. 0 | Page 33 of 42 Description Alarm Trigger Level 2 Flash Backup Yes ADcmXL1021-1 Data Sheet The data format in the ALM_MAG2 register is the same as the data format in the OUT_BUF register. See Table 43 for several examples of this data format. The Alarm 2 magnitudes must be greater than or equal to Alarm 1. ALM_PNTR, ALARM POINTER When Bit 4 in the ALM_CTRL register is equal to 0, the ALM_ S_MAG register uses the same data format as the SUPPLY_ OUT register (see Table 26 and Table 27). When Bit 4 in the ALM_CTRL register is equal to 1, the ALM_S_MAG register uses the same data format as the TEMP_OUT register (see Table 23 and Table 24). When the ADcmXL1021-1 is operating in MFFT or AFFT mode, the ALM_PNTR register (see Table 59 and Table 60) contains an alarm pointer that identifies a specific spectral alarm by sample rate (Bits[9:8]) and spectral band number (Bits[2:0]). Up to six alarms can be configured per sample rate setting. ALM_CTRL, ALARM CONROL Table 59. ALM_PNTR Register Definition Addresses 0x34, 0x35 Addresses 0x30, 0x31 Default 0x0000 Access R/W Flash Backup No [7:3] [2:0] Description Don't care Indicates the sample rate setting for which Alarm x is defined 00 = SR0 01 = SR1 02 = SR2 03 = SR3 Don't care Spectral band number (1, 2, 3, 4, 5, or 6) 7 6 ALM_S_MAG ALARM LEVEL The ALM_S_MAG register (see Table 61 and Table 62) contains the magnitude of the system alarm, which can monitor the temperature or power supply level according to Bits[5:4] in the ALM_CTRL register (see Table 64). Table 61. ALM_S_MAG Register Definition Default 0x0000 Access R/W Table 62. ALM_S_MAG Bit Descriptions Bits [15:0] Description System alarm setting Flash Backup No Default 0x0080 Access R/W Flash Backup Yes Table 64. ALM_CTRL Bit Descriptions [11:8] Setting ALM_PNTR = 0x0203 provides access to the settings for the spectral alarm, which is associated with Sample Rate SR2 and Spectral Band 3. The current attributes from this spectral alarm load to the ALM_F_LOW, ALM_F_HIGH, ALM_MAG1 and ALM_MAG2 registers. Writing to these registers changes each setting for the spectral alarm, which is associated with Sample Rate SR2 and Spectral Band 3 as well. Addresses 0x32, 0x33 Table 63. ALM_CTRL Register Definition Bits [15:13] [12] Table 60. ALM_PNTR Bit Descriptions Bits [15:10] [9:8] The ALM_CTRL register (see Table 63 and Table 64) contains a number of configuration settings for the alarm function. 5 4 3 2 1 0 Description Don't care. Disables automatic clearing of spectral alarm status bits upon a read of the status register. Response delay, range = 0 to 15. Represents the number of spectral records for each spectral alarm before a spectral alarm flag is set high. Latch DIAG_STAT error flags. Requires a clear status command (GLOB_CMD, Bit 4) to reset the flags to 0. 1 = enabled, 0 = disabled. Enable Alarm 1 and Alarm 2 on ALM1 and ALM2, respectively. System alarm polarity. 1 = trigger when less than ALM_S_MAG. 0 = trigger when greater than ALM_S_MAG. System alarm selection. 1 = temperature, 0 = power supply. System alarm: 1 = enabled, 0 = disabled. Output alarm: 1 = enabled, 0 = disabled. Reserved. Reserved. FILT_CTRL, FILTER CONTROL The FILT_CTRL register (see Table 65 and Table 66) provides configuration settings for the 32-tap, FIR filters. When the FILT_ CTRL pin contains the factory default value, the ADcmXL1021-1 does not use any of the FIR filters on the output. For example, set DIN = 0xB871, then set DIN = 0xB901 to write 0x0171 to the FILT_CTRL register. This code (0x0171) selects Filter Bank 5 for the accelerometer output. Table 65. FILT_CTRL Register Definition Addresses 0x38, 0x39 Rev. 0 | Page 34 of 42 Default 0x0000 Access R/W Flash Backup Yes Data Sheet ADcmXL1021-1 with the bin widths and noise predictions that come with those settings. The information in Table 69 also applies to the SR1 (AVG_CNT register, Bits[7:4]), SR2 (AVG_CNT register, Bits[11:8]), and SR3 (AVG_CNT register, Bits[15:12]) settings as well. Table 66. FILT_CTRL Bit Descriptions Bits [15:11] [10:8] [7:0] Description Don't care. Output FIR filter selection. 110: FIR Filter Bank F (high-pass filter, 10 kHz). 101: FIR Filter Bank E (high-pass filter, 5 kHz). 100: FIR Filter Bank D (high-pass filter, 1 kHz). 011: FIR Filter Bank C (low-pass filter, 10 kHz). 010: FIR Filter Bank B (low-pass filter, 5 kHz). 001: FIR Filter Bank A (low-pass filter, 1 kHz). 000: no FIR selection. Reserved. Table 69. SR0 Sample Rate Settings and Bin Widths AVG_CNT, DECIMATION CONTROL The AVG_CNT register (see Table 67 and Table 68) provides four different sample rate settings (SR0, SR1, SR2, and SR3) that users can enable using Bits[11:8] in the REC_CTRL register (see Table 47). These sample rate settings only apply to MFFT, AFFT, and MTC mode. Default 0x7421 Access R/W Flash Backup Yes [11:8] [7:4] [3:0] Bin Width (Hz) Not applicable 53.8 26.9 13.4 6.71 3.35 1.68 0.839 DIAG_STAT, STATUS, AND ERROR FLAGS The DIAG_STAT (see Table 70 and Table 71) register contains a number of status flags. Addresses 0x3C, 0x3D Default 0x0000 Access R Flash Backup No Table 71. DIAG_STAT Bit Descriptions Table 68. AVG_CNT Bit Descriptions Bits [15:12] Sample Rate (SPS) Not applicable 220000 110000 55000 27500 13750 6875 3438.5 Table 70. DIAG_STAT Register Definition Table 67. AVG_CNT Register Definition Addresses 0x3A, 0x3B AVG_CNT, Bits[3:0] 0 1 (Default) 2 3 4 5 6 7 Description SR3 sample rate scale factor (1 to 7), SR3 sample rate = 220,000 / 2AVG_CNT[15:12] SR2 sample rate scale factor (1 to 7), SR2 sample rate = 220,000 / 2AVG_CNT[11:8] SR1 sample rate scale factor (1 to 7), SR1 sample rate = 220,000 / 2AVG_CNT[7:4] SR0 sample rate scale factor (1 to 7), SR0 sample rate = 220,000 / 2AVG_CNT[3:0] Each nibble in the AVG_CNT register offers a setting for each sample rate setting: SR0, SR1, SR2, and SR3. The following formula demonstrates one of the sample rates (SR1) derived from the factory default value (0x7421) in the AVG_CNT register: Bits 15 14 13 12 11 10 9 8 7 6 5 4 SR1 = 220,000 / 22 = 55,000 SPS To change one of the sample rate values, write the control value to the specific nibble in the AVG_CNT register. For example, set DIN = 0xBB35 to set the upper byte of the AVG_CNT register to 0x35, which causes the SR2 sample rate to be 27,500 SPS and the SR3 sample rate to be 6,875 SPS. 3 2 1 0 In MFFT and AFFT mode, the sample rate settings in the AVG_CNT register influence the bin widths of each FFT result, which has an impact on the noise in each bin. Table 69 lists the SR0 sample rate settings (see the AVG_CNT register, Bits[3:0]), along Rev. 0 | Page 35 of 42 Description Not used (don't care). System alarm flag. The temperature or power supply exceeded the user configured alarm. Spectral Alarm 2 flag. Reserved. Reserved. Spectral Alarm 1 flag. Reserved. Reserved. Data ready/busy indicator (0 = busy, 1 = data ready). Flash test result, checksum flag (0 = no error, 1 = error). Self test diagnostic error flag. Recording escape flag. Indicates use of the SPI driven interruption command, 0x00E8. This flag is reset automatically after the first successful recording. SPI communication failure (SCLKs even multiple of 16). Flash update failure. Power supply > 3.625 V. Power supply < 2.975 V. ADcmXL1021-1 Data Sheet Table 75. ALM_STAT Bit Descriptions GLOB_CMD, GLOBAL COMMANDS The GLOB_CMD (see Table 72 and Table 73) register contains a number of global commands. To start any of these processes, set the corresponding bit to 1. For example, set Bit 0 to logic high to execute the autonull function and the bit self clears. Table 72. GLOB_CMD Register Definition Addresses 0x3E, 0x3F Default Not applicable Access W Flash Backup No Table 73. GLOB_CMD Bit Descriptions Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Description Clear autonull correction. Retrieve spectral alarm band information from the ALM_PNTR setting. Retrieve record data from flash memory. Save spectral alarm band registers to flash memory. Record start or stop. Set BUF_PNTR = 0x0000. Clear spectral alarm band registers from flash memory. Clear all records. Software reset. Save registers to flash memory. Flash test, compare sum of flash memory with factory value. Clear DIAG_STAT register once. Restore factory register settings and clear the capture buffers. Self test. Executes the automatic self test method. If test does not pass, then the self test diagnostic flag is set in the status register (Bit 5). Power-down (wake with CS toggle). Powers down sensor and puts embedded microcontroller in sleep mode. The device wakes up with a toggle of CS or if the automatic timer triggers a new capture (automatic mode). Autonull. ALM_STAT, ALARM STATUS Access R ALM_PEAK, ALARM PEAK LEVEL The ALM_PEAK (see Table 76 and Table 77) register contains the magnitude of the FFT bin, which contains the peak alarm value. Table 76. ALM_PEAK Register Definition Addresses 0x4A, 0x4B Default 0x0000 Access R Flash Backup Yes Table 77. ALM_PEAK Bit Descriptions Bits [15:0] Description Alarm peak, accelerometer data format TIME_STAMP_L AND TIME_STAMP_H, DATA RECORD TIMESTAMP The TIME_STAMP_L (see Table 78 and Table 79) and TIME_STAMP_H (see Table 80 and Table 81) registers contain a relative timestamp for the most recent data capture event. Addresses 0x4C, 0x4D Table 74. ALM_STAT Register Definition Default 0x0000 Description Alarm 2 on Band 6; 1 = alarm set, 0 = no alarm Alarm 1 on Band 6; 1 = alarm set, 0 = no alarm Alarm 2 on Band 5; 1 = alarm set, 0 = no alarm Alarm 1 on Band 5; 1 = alarm set, 0 = no alarm Alarm 2 on Band 4; 1 = alarm set, 0 = no alarm Alarm 1 on Band 4; 1 = alarm set, 0 = no alarm Alarm 2 on Band 3; 1 = alarm set, 0 = no alarm Alarm 1 on Band 3; 1 = alarm set, 0 = no alarm Alarm 2 on Band 2; 1 = alarm set, 0 = no alarm Alarm 1 on Band 2; 1 = alarm set, 0 = no alarm Alarm 2 on Band 1; 1 = alarm set, 0 = no alarm Alarm 1 on Band 1; 1 = alarm set, 0 = no alarm Not used Most critical alarm condition, spectral band; range = 1 to 6 Table 78. TIME_STAMP_L Register Definition The ALM_STAT (see Table 74 and Table 75) register contains status flags for alarm. Addresses 0x44, 0x45 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 [2:0] Flash Backup Yes Default 0x0000 Access R Flash Backup Yes Table 79. TIME_STAMP_L Bit Descriptions Bits [15:0] Description Timestamp, seconds, lower word Table 80. TIME_STAMP_H Register Definition Addresses 0x4E, 0x4F Default 0x0000 Access R Table 81. TIME_STAMP_H Bit Descriptions Bits [15:0] Rev. 0 | Page 36 of 42 Description Timestamp, seconds, upper word Flash Backup Yes Data Sheet ADcmXL1021-1 DAY_REV, DAY AND REVISION USER_SCRATCH The DAY_REV (see Table 82 and Table 83) contains part of the factory programming date (day) and the revision of the firmware. The USER_SCRATCH register allows end users to store a device number to identify the sensor. The register is readable and writable. Last written value is nonvolatile allowing for data recovery upon reset. Table 82. DAY_REV Register Definition Addresses 0x52, 0x53 Default 0x0000 Access R Flash Backup N/A Addresses 0x5A, 0x5B Table 83. DAY_REV Bit Descriptions Bits [15:12] [11:8] [7:4] [3:0] Description Day of the month, most significant digit Day of the month, least significant digit Firmware revision, most significant digit Firmware revision, least significant digit Bits [15:0] Table 84. YEAR_MON Register Definition Access R Flash Backup N/A Table 85. YEAR_MON Bit Descriptions Bits [15:12] [118] [7:4] [3:0] Access R/W Flash Backup Yes Description Optional user ID REC_FLASH_CNT, RECORD FLASH ENDURANCE The YEAR_MON (see Table 84 and Table 85) contains the factory programming date (month and year). Default Not applicable Default N/A Table 91. USER_SCRATCH Bit Descriptions YEAR_MON, YEAR AND MONTH Addresses 0x54, 0x55 Table 90. USER_SCRATCH Register Definition The REC_FLASH_CNT (see Table 92 and Table 93) provides a tool for tracking the endurance of the flash memory bank, which support the 10 record storage locations. The value in the REC_ FLASH_CNT register increments after clearing the user record (GLOB_CMD) and each time the record storage fills up (tenth location contains event data) Table 92. REC_FLASH_CNT Register Definition Addresses 0x5C, 0x5D Description Year, most significant digit Year, least significant digit Month of the year, most significant digit Month of the year, least significant digit Default 0x0000 Access R Flash Backup N/A Table 93. REC_FLASH_CNT Bit Descriptions Bits [15:0] Description Endurance counter for the record flash memory PROD_ID, PRODUCT IDENTIFICATION MISC_CTRL, MISCELLANEOUS CONTROL The PROD_ID (see Table 86 and Table 87) register contains the numerical portion of the model number. The MISC_CTRL register (see Table 94 and Table 95) enables the saving of MTC mode statistic values to memory, enable sensor self test, and enable SYNC pin to external control. Table 86. PROD_ID Register Definition Addresses 0x56, 0x57 Default 0x03FD Access R Flash Backup N/A Table 87. PROD_ID Bit Descriptions Bits [15:0] Table 94. MISC_CTRL Register Definition Addresses 0x64, 0x65 Bits [15:13] 12 SERIAL_NUM, SERIAL NUMBER The SERIAL_NUM (see Table 88 and Table 89) contains the serial number of the unit, within a particular manufacturing lot. 11 10 Table 88. SERIAL_NUM Register Definition Default 0x0000 Access R Table 89. SERIAL_NUM Bit Descriptions Bits [15:0] Description Lot specific serial number Access W/R Flash Backup No Table 95. MISC_CTRL Bit Descriptions Description Binary representation of the numerical portion of the model number: 0x03FD = 1,021 Addresses 0x58, 0x59 Default 0x0000 Flash Backup N/A 9 8 [7:4] 3 2 [1:0] Rev. 0 | Page 37 of 42 Description Unused. Enable sensitivity to SYNC pin to start a capture. Must be enabled for external trigger for manual capture modes. Unused. Transfer statistics record from flash memory to SRAM. REC_PNTR must point to the appropriate time domain statistic record. Transfers statistics from SRAM to flash record. Clear time domain statistics. Unused. Set self test on. Clear self test. Unused. ADcmXL1021-1 Data Sheet REC_INFO1, RECORD INFORMATION REC_CNTR, RECORD COUNTER The REC_INFO1 register (see Table 96 and Table 97) contains the sample rate (SRx), window function, and FFT average settings associated with the spectral record in the user data buffer. The contents of this register are only relevant for results that come from MFFT and AFFT mode (see the REC_CTRL register in Table 47). The REC_CNTR (see Table 100 and Table 101) register contains the record counter, which contains the number of records currently in use. Table 96. REC_INFO1 Register Definition Addresses 0x66, 0x67 Default 0x0000 Access R Flash Backup Yes Table 97. REC_INFO1 Bit Descriptions Bits [15:14] [13:12] [11:8] [7:0] Description Sample rate option 00 = SR0 01 = SR1 10 = SR2 11 = SR3 Window setting 00 = rectangular 01 = Hanning 10 = flat top 11 = not applicable Not used (don't care) FFT averages; range = 1 to 2047 Table 99. REC_INFO2 Bit Descriptions Bits [15:4] [3:0] Description Not used (don't care) AVG_CNT setting Flash Backup N/A Table 101. REC_CNTR Bit Descriptions Bits [15:4] [3:0] Description Not used Record counter range: 0 through 9 Table 102. ALM_FREQ Register Definition Addresses 0x70, 0x71 Default 0x0000 Access R Flash Backup Yes Table 103. ALM_FREQ Bit Descriptions Bits [15:12] [11:0] Table 98. REC_INFO2 Register Definition Access R Access R The ALM_FREQ register (see Table 102 and Table 103) contains the frequency bin that is associated with the value in the ALM_ PEAK (see Table 77) register. The REC_INFO2 (see Table 98 and Table 99) register contains the contents of the AVG_CNT register, which relate to the sample rate (SRx) in use for the spectral record in the user data buffer. The contents of this register are only relevant for results that come from MFFT and AFFT mode (see the REC_CTRL register in Table 47). Default 0x0000 Default 0x0000 ALM_FREQ, SEVERE ALARM FREQUENCY REC_INFO2, RECORD INFORMATION, Addresses 0x68, 0x69 Table 100. REC_CNTR Register Definition Addresses 0x6A, 0x6B Flash Backup Yes Description Not used Alarm frequency for peak alarm level, FFT bin number; range = 0 to 2047 STAT_PNTR, STATISTIC RESULT POINTER The STAT_PNTR register (see Table 104 and Table 105) controls which statistic loads to the statistic register (see Table 107). For example, set DIN = 0xF202 to write 0x02 to the lower byte of the STAT_PNTR, which causes the Kurtosis results to load to the statistic register. Table 104. STAT_PNTR Register Definition Addresses 0x72, 0x73 Default 0x0000 Access R/W Table 105. STAT_PNTR Bit Descriptions Bits [15:3] [2:0] Rev. 0 | Page 38 of 42 Description Don't care 110 = skewness 101 = Kurtosis 100 = crest factor 011 = peak-to-peak 010 = peak 001 = standard deviation 000 = mean value Flash Backup No Data Sheet ADcmXL1021-1 Table 110. FUND_FREQ Bit Descriptions STATISTIC, STATISTIC RESULT The statistic register (see Table 106 and Table 107) contains the statistical metric that represents the settings in the STAT_ PNTR register (see Table 105). The data format for this register depends on the metric that it contains. When the lower byte of the STAT_PNTR register is equal to 0x00, 0x04, 0x05, or 0x06, the data format is the same as the OUT_BUF register (MTC mode). See Table 40 and Table 41 for a definition and some examples of this data format. When the lower byte of the STAT_PNTR register is equal to 0x01, 0x02, or 0x03, the statistic register uses the binary coded decimal (BCD) format shown in Table 107. Table 108 provides some numerical examples of this format. Table 106. Statistic Register Definition Access R Flash Backup Yes Table 107. Statistic Bit Descriptions for Crest Factor, Kurtosis and Skewness results Bits [15:8] [7:0] Description Integer, offset binary format, 1 LSB = 1 Decimal, 1 LSB = 1/256 = 0.00390625 Integer 0 0 0 0 0 0 1 1 2 6 26 255 Decimal 0 1/256 = 0.00390625 2/256 = 0.0078125 10/256 = 0.0390625 254/256 = 0.9921875 255/256 = 0.99609375 0 106/256 = 0.4140625 10/256 = 0.0390625 154/256 = 0.6015625 242/256 = 0.9453125 255/256 = 0.99609375 Alarm 2 Level 0.5 g 0.5 g 0.5 g 0.5 g 0.5 g 0.5 g FLASH_CNT_L (see Table 112 and Table 113) contains the lower 16 bits of a 32-bit counter. This counter tracks the total number of update cycles that the flash memory bank experiences. Result 0 0.00390625 0.0078125 0.0390625 0.9921875 0.99609375 1 1.4140625 2.0390625 6.6015625 26. 9453125 255.99609375 Default Not applicable Access R Flash Backup N/A Table 113. FLASH_CNT_L Bit Descriptions Bits [15:0] Description Flash update counter, lower word FLASH_CNT_U, FLASH MEMORY ENDURANCE The FLASH_CNT_U register (see Table 114 and Table 115) contains the upper 16 bits of a 32-bit counter. This counter tracks the total number of update cycles that the flash memory bank experiences. Table 114. FLASH_CNT_U Register Definition Addresses 0x7E, 0x7F Default 0x0000 Access R Flash Backup N/A Table 115. FLASH_CNT_U Bit Descriptions Bits [15:0] Table 109. FUND_FREQ Register Definition Access R/W Alarm 1 Level 20% x 0.5 g 90% x 0.5 g 30% x 0.5 g 25% x 0.5 g 20% x 0.5 g 15% x 0.5 g FLASH_CNT_L, FLASH MEMORY ENDURANCE The FUND_FREQ register (see Table 109 and Table 110) provides a simple way to configure the spectral alarms to monitor the fundamental vibration frequency on a platform, along with the subsequent harmonic frequencies. Table 111 provides the start and stop frequency settings for each alarm band, which automatically loads after writing to the upper byte of the FUND_FREQ register, the units are Hz. Default is disabled. Default 0x0000 Stop Frequency 0.8 x fF 1.8 x fF 2.8 x fF 3.8 x fF 10.2 x fF fMAX Table 112. FLASH_CNT_L Register Definition FUND_FREQ, FUNDAMENTAL FREQUENCY Addresses 0x7A, 0x7B Start Frequency 0.2 x fF 0.8 x fF 1.8 x fF 2.8 x fF 3.8 x fF 10.2 x fF Addresses 0x7C, 0x7D Table 108. Statistic Data Format Examples for Crest Factor, Kurtosis and Skewness results Hex. 0x0000 0x0001 0x0002 0x000A 0x00FE 0x00FF 0x0100 0x016A 0x020A 0x069A 0x1AF2 0xFFFF Alarm Band 1 2 3 4 5 6 Flash Backup Yes Description Flash update counter, upper word 600 450 300 150 0 30 40 55 70 85 100 125 135 JUNCTION TEMPERATURE (C) Figure 44. Flash/EE Memory Data Retention Rev. 0 | Page 39 of 42 150 21125-036 Default 0x0000 Description Fundamental frequency setting, fF. Offset binary format, 1 LSB = 1 Hz. 0x0000 = no influence on alarm settings. Table 111. Statistic Data Format Examples RETENTION (Years) Addresses 0x78, 0x79 Bits [15:0] ADcmXL1021-1 Data Sheet FIR FILTER REGISTERS FIR Filter Design Guidelines The ADcmXL1021-1 signal chain includes a 32-tap, FIR filter. Register Page 1 through Register Page 6 provide user configuration access to the coefficients for six different FIR filter banks. The FILT_CTRL (see Table 66) register controls the enabling of the FIR filters and allows the selection of the FIR filter banks. Each FIR filter bank features factory default filter designs, and each filter bank provides write access to support application specific filter designs. To access one of the FIR filter banks, write the corresponding page number to the PAGE_ID register. For example, set DIN = 0x8003 to set PAGE_ID = 0x0003, which provides access to FIR Filer Bank C. See Table 19 for a complete listing of the FIR coefficient addresses and pages. User defined, 32 tap digital filtering can be programmed and stored. This filter uses 16-bit coefficients. Register Page 1 through Register Page 6 contain filter bank coefficients for Filter A to Filter F, respectively. Each of the 32 coefficients has a 16-bit register. User filters (as well as other register settings) can be stored internally in the ADcmXL1021-1. By default, the following filters are preconfigured in the respective filter bank registers: * * * * * * Filter Band A is a 32 tap, low-pass filter at 1 kHz. Filter Band B is a 32 tap, low-pass filter at 5 kHz. Filter Band C is a 32 tap, low-pass filter at 10 kHz. Filter Band D is a 32 tap, high-pass filter at 1 kHz. Filter Band E is a 32 tap, high-pass filter at 5 kHz. Filter Band F is a 32 tap, high-pass filter at 10 kHz. The numerical format for each coefficient is a 16-bit, twos complement signed value. Signed values use the MSB to identify the sign of the value. If the MSB is 1, the values are negative. If the MSB is 0, the value is positive. The remaining 15 bits are the magnitude of the coefficient. The 32 taps of the filter must sum to 0 to have unity gain. If values are summed as unsigned binary values, the summed value of 32,767 represents unity gain. By default, the FIR filters are designed to have a linear phase response up to 10 kHz. Rev. 0 | Page 40 of 42 Data Sheet ADcmXL1021-1 APPLICATIONS INFORMATION MECHANICAL INTERFACE For the best performance, follow the guidelines described in this section when installing the ADcmXL1021-1 in a system. Eliminate potential translational forces by aligning the module in a well defined orientation. Use uniform mounting force on all four corners of the module. Use all four mounting holes and M2.5 screws at a torque of 5 inch-pounds. Additional mechanical adhesives (cyanoacrylate adhesive and epoxies such as Dymax 652A gel adhesive) can be used to, in some cases, improve mechanical coupling and frequency response. Application of these additional adhesives are mechanical design and processes dependent. Therefore, the application of these additional adhesives must be evaluated thoroughly during product development. A minimum bend radius of the flex tail of 1 mm is allowed. At a lower bend radius, delamination or conductor failure may occur. The connector at the end of the flex tail is the DF12(3.0)-14DS0.5V(86) from Hirose Electric Co. Ltd. The mating connector that must be used is the DF12(3.0)-14DP-0.5V(86) from Hirose Electric Co. Ltd. Rev. 0 | Page 41 of 42 ADcmXL1021-1 Data Sheet OUTLINE DIMENSIONS 27.10 27.00 26.90 21.75 21.70 21.65 BOTTOM VIEW TOP VIEW O 2.65 (for M2.5 SS316 screws) 23.80 23.70 23.60 12.55 12.50 12.45 Hirose 14 Pin (0.5 mm Pitch Connector) DF12(3.0)-14DS-05V (86) 36.00 35.80 35.60 3.80 3.60 3.40 4.55 BSC 9.20 9.10 8.90 5.80 5.60 5.40 3.50 BSC PIN 1 FRONT VIEW 12.50 12.40 12.30 02-14-2019-B 4.60 4.50 4.40 Figure 45. 14-Lead Module with Integrated Flex Connector [MODULE] (ML-14-7) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADcmXL1021-1BMLZ EVAL-ADCM-1 ADCMXL_BRKOUT/PCBZ 1 Temperature Range -40C to +105C g Range 50 g Package Description 14-Lead Module with Integrated Flex Connector [MODULE] ADcmXL1021-1 Evaluation Kit ADcmXL1021-1 Breakout Interface Board Z = RoHS Compliant Part. (c)2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D21125-0-11/19(0) Rev. 0 | Page 42 of 42 Package Option ML-14-7