March 2001 AS7C4098 AS7C34098 (R) 5V/3.3V 256K x 16 CMOS SRAM * Low power consumption: STANDBY Features - 110 mW (AS7C4098)/max CMOS - 72 mW (AS7C34098)/max CMOS * AS7C4098 (5V version) * AS7C34098 (3.3V version) * Industrial and commercial temperature * Organization: 262,144 words x 16 bits * Center power and ground pins * High speed * Individual byte read/write controls * 2.0V data retention * Easy memory expansion with CE, OE inputs * TTL- and CMOS-compatible, three-state I/O * 44-pin JEDEC standard packages - 10/12/15/20 ns address access time - 5/6/7/8 ns output enable access time - 400-mil SOJ - 400-mil TSOP II * Low power consumption: ACTIVE * ESD protection 2000 volts * Latch-up current 200 mA - 1375 mW (AS7C4098)/max @ 12 ns - 468 mW (AS7C34098)/max @ 12 ns Logic block diagram UB OE LB CE 1024 x 256 x 16 Array (4,194,304) I/O buffer Control circuit A0 A1 A2 A3 A4 CE I/O1 I/O2 I/O3 I/O4 VCC GND I/O5 I/O6 I/O7 I/O8 WE A5 A6 A7 A8 A9 GND Column decoder A5 A9 A10 A11 A14 A15 A16 A17 WE 44-pin SOJ, TSOP II (400 mil) VCC Row Decoder A0 A1 A2 A3 A4 A6 A7 A8 A12 A13 I/O1-I/O8 I/O9-I/O16 Pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE UB LB I/O16 I/O15 I/O14 I/O13 GND VCC I/O12 I/O11 I/O10 I/O9 NC A14 A13 A12 A11 A10 Selection guide AS7C34098 -10 AS7C4098 AS7C34098 -12 AS7C4098 AS7C34098 -15 AS7C4098 AS7C34098 -20 Unit Maximum address access time 10 12 15 20 ns Maximum output enable access time 5 6 7 9 ns AS7C4098 - 250 220 180 mA AS7C34098 160 130 110 100 mA AS7C4098 - 20 20 20 mA AS7C34098 20 20 20 20 mA Maximum operating current Maximum CMOS standby current 3/23/01; v.1.0 Alliance Semiconductor P. 1 of 9 Copyright (c) Alliance Semiconductor. All rights reserved. AS7C4098 AS7C34098 (R) Functional description The AS7C4098 and AS7C34098 are high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) devices organized as 262,144 words x 16 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5/6/7/8 ns are ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory systems. When CE is High the device enters standby mode. The standard AS7C4098 is guaranteed not to exceed 110 mW power consumption in CMOS standby mode. Both devices offer 2.0V data retention. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O1-I/O16 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) High. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. These devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O1-I/O8, and UB controls the higher bits, I/O9-I/O16. All chip inputs and outputs are TTL- and CMOS-compatible, and operation is from either a single 5V (AS7C4098) or 3.3V (AS7C34098) supply. Both devices are available in the JEDEC standard 400-mL, 44-pin SOJ and TSOP II packages. Absolute maximum ratings Parameter Device Symbol Min Max Unit AS7C4098 Vt1 -0.50 +7.0 V AS7C34098 Vt1 -0.50 +5.0 V Voltage on any pin relative to GND Vt2 -0.50 VCC +0.50 V Power dissipation PD - 1.5 W Storage temperature (plastic) Tstg -65 +150 C Ambient temperature with VCC applied Tbias -55 +125 C DC current into outputs (low) IOUT - 20 mA Voltage on VCC relative to GND Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE WE OE LB UB I/O1-I/O8 I/O9-I/O16 Mode H X X X X High Z High Z Standby (ISB, ISB1) L H H X X L X X H H High Z High Z Output disable (ICC) L H DOUT High Z H L High Z DOUT L L DOUT DOUT L H DIN High Z H L High Z DIN L L DIN DIN L L H L L X Read (ICC) Write (ICC) Key: X = Don't care, L = Low, H = High. 3/23/01; v.1.0 Alliance Semiconductor P. 2 of 9 AS7C4098 AS7C34098 (R) Recommended operating conditions Parameter Supply voltage Input voltage Ambient operating temperature Symbol Min Typical Max Unit AS7C4098 VCC (10/12/15/20) 4.5 5.0 5.5 V AS7C34098 VCC (-10) 3.15 3.3 3.6 V AS7C34098 VCC (10/12/15/20) 3.0 3.3 3.6 V AS7C4098 VIH 2.2 - VCC + 0.5 V AS7C34098 VIH 2.0 - VCC + 0.5 V - 0.8 V * VIL -0.5 commercial TA 0 - 70 C industrial TA -40 - 85 C * VIL min = -3.0V for pulse width less than tRC/2. DC operating characteristics (over the operating range)1 -10 Parameter Symbol Test conditions -12 -15 -20 Min Max Min Max Min Max Min Max Unit |ILI| VCC = Max VIN = GND to VCC - 1 - 1 - 1 - 1 A Output leakage current |ILO| VCC = Max CE = VIH or OE = VIH or WE = VIL VI/O = GND to VCC - 1 - 1 - 1 - 1 A Operating power supply current VCC = Max Min cycle, 100% duty CE = VIL, IOUT = 0mA AS7C4098 - - - 250 - 220 - 180 mA ICC AS7C34098 - 160 - 130 - 110 - 100 mA ISB VCC = Max CE = VIH, f = Max AS7C4098 - - - 60 - 60 - 60 mA AS7C34098 - 60 - 60 - 60 - 60 mA VCC = Max CE VCC - 0.2V, VIN VCC - 0.2V or VIN 0.2V, f = 0 AS7C4098 - - - 20 - 20 - 20 mA ISB1 AS7C34098 - 20 - 20 - 20 - 20 mA VOL IOL = 8 mA, VCC = Min - 0.4 - 0.4 - 0.4 - 0.4 V VOH IOH = -4 mA, VCC = Min 2.4 - 2.4 - 2.4 - 2.4 - V Input leakage current Standby power supply current Output voltage Capacitance (f = 1MHz, Ta = 25 C, VCC = NOMINAL)2 Parameter Symbol Signals Test conditions Max Unit Input capacitance CIN A, CE, WE, OE, UB, LB VIN = 0V 6 pF I/O capacitance CI/O I/O VIN = VOUT = 0V 8 pF 3/23/01; v.1.0 Alliance Semiconductor P. 3 of 9 AS7C4098 AS7C34098 (R) Read cycle (over the operating range)3,9 -10 Parameter -12 -15 -20 Symbol Min Max Min Max Min Max Min Max Unit Notes Read cycle time tRC 10 - 12 - 15 - 20 - ns Address access time tAA - 10 - 12 - 15 - 20 ns Chip enable (CE) access time tACE - 10 - 12 - 15 - 20 ns Output enable (OE) access time tOE - 5 - 6 - 7 - 8 ns Output hold from address change tOH 3 - 3 - 3 - 3 - ns 5 CE Low to output in low Z tCLZ 0 - 3 - 0 - 0 - ns 4, 5 CE High to output in higfch Z tCHZ - 5 - 6 - 7 - 9 ns 4, 5 OE Low to output in low Z tOLZ 0 - 0 - 0 - 0 - ns 4, 5 OE High to output in high Z tOHZ - 5 - 6 - 7 - 9 ns 4, 5 LB, UB access time tBA - 5 - 6 - 7 - 8 ns LB, UB Low to output in low Z tBLZ 0 - 0 - 0 - 0 - ns LB, UB High to output in high Z tBHZ - 5 - 6 - 7 - 9 ns Power up time tPU 0 - 0 - 0 - 0 - ns 5 Power down time tPD - 10 - 12 - 15 - 20 ns 5 Key to switching waveforms Rising input Falling input Undefined/don't care Read waveform 1 (address controlled)6,7,9 tRC Address tAA tOH DataOUT tOH Previous data valid Data valid Read waveform 2 (CE, OE, UB, LB controlled)6,8,9 tRC Address tAA OE tOHZ tOE tOH tOLZ CE tACE tLZ tCHZ LB, UB tBA tBHZ tBLZ DataOUT 3/23/01; v.1.0 Data valid Alliance Semiconductor P. 4 of 9 AS7C4098 AS7C34098 (R) Write cycle (over the operating range)11 -10 Parameter -12 -15 -20 Symbol Min Max Min Max Min Max Min Max Unit Write cycle time tWC 10 - 12 - 15 - 20 - ns Chip enable (CE) to write end tCW 7 - 8 - 10 - 12 - ns Address setup to write end tAW 7 - 8 - 10 - 12 - ns Address setup time tAS 0 - 0 - 0 - 0 - ns Write pulse width (OE = High) tWP1 7 - 8 - 10 - 12 - ns Write pulse width (OE = Low) tWP2 10 - 12 - 15 - 20 - ns Address hold from end of write tAH 0 - 0 - 0 - 0 - ns Data valid to write end tDW 5 7 - 9 - ns Data hold time tDH 0 - 0 - 0 - 0 - ns 4, 5 Write enable to output in High-Z tWZ 0 5 0 6 0 7 0 9 ns 4, 5 Output active from write end tOW 3 - 3 - 3 - 3 - ns 4, 5 Byte enable Low to write end tBW 7 - 8 - 10 - 12 - ns 4, 5 6 Note Write waveform 1(WE controlled)10,11 tWC Address tAH tCW CE tBW LB, UB tAW tAS tWP WE tDW DataIN Data valid tWZ DataOUT tDH tOW Data undefined High Z Write waveform 2 (CE controlled)10,11 tWC Address tAS tAH tCW CE tAW tBW LB, UB tWP WE tDW DataIN DataOUT 3/23/01; v.1.0 tCLZ High Z tWZ Data undefined Alliance Semiconductor tDH Data valid tOW High Z P. 5 of 9 AS7C4098 AS7C34098 (R) Write waveform 3 10,11 tWC Address tAS tAH tCW CE tAW tBW LB, UB tWP WE tDW DataIN Data valid tDH tWZ DataOUT Data undefined High Z Data retention characteristics High Z 13 Parameter VCC for data retention Data retention current Chip deselect to data retention time Operation recovery time Input leakage current Symbol VDR ICCDR tCDR tR |ILI| Test conditions VCC = 2.0V Min 2.0 - 0 tRC - CE VCC - 0.2V VIN VCC - 0.2V or VIN 0.2V Max - 500 - - 1 Unit V A ns ns A Data retention waveform Data retention mode VCC VDR 2.0V VCC VCC tCDR tR VDR VIH CE VIH AC test conditions - Output load: see Figure B or Figure C. Input pulse level: GND to 3.0V. See Figure A. Input rise and fall times: 2 ns. See Figure A. Input and output timing reference levels: 1.5V. 168W +1.728V (5V and 3.3V) +3.3V 480W +3.0V GND Thevenin equivalent: D OUT +5V 90% 90% 10% 10% 2 ns Figure A: Input pulse DOUT 255W C(14) GND Figure B: 5V Output load 320W DOUT 350W C(14) GND Figure C: 3.3V Output load Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 14 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions, Figures A, B, C. tCLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured 500mV from steady-state voltage. This parameter is guaranteed, but not tested. WE is High for read cycle. CE and OE are Low for read cycle. Address valid prior to or coincident with CE transition Low. All read cycle timings are referenced from the last valid address to the first transitioning address. CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle. All write cycle timings are referenced from the last valid address to the first transitioning address. Not applicable. 2V data retention applies to commercial temperature range operation only. C = 30pF, except on High Z and Low Z parameters, where C = 5pF. 3/23/01; v.1.0 Alliance Semiconductor P. 6 of 9 AS7C4098 AS7C34098 (R) Typical DC and AC characteristics12 Normalized supply current ICC, ISB vs. supply voltage VCC 1.4 1.4 1.0 0.8 0.6 ISB 0.4 0.2 NOMINAL Supply voltage (V) 0.6 ISB 0.4 0.0 -55 MAX Normalized access time tAA vs. supply voltage VCC 1.5 625 5 1 0.2 0.04 -10 35 80 125 Ambient temperature (C) -55 1.2 1.1 1.0 1.3 1.2 1.1 1.0 0.9 0.8 MIN NOMINAL Supply voltage (V) 0.8 -55 MAX Output source current IOH vs. output voltage VOH 140 Output sink current (mA) VCC = VCC(NOMINAL)PL 100 Ta = 25 C 80 60 40 20 0 VCC Output voltage (V) 3/23/01; v.1.0 0.6 0.4 0.0 0 25 50 75 Cycle frequency (MHz) 100 Typical access time change tAA vs. output capacitive loading 35 120 30 VCC = VCC(NOMINAL) 100 Ta = 25 C 80 60 40 20 VCC = VCC(NOMINAL) 25 20 15 10 5 0 0 0.8 -10 35 80 125 Ambient temperature (C) Output sink current IOL vs. output voltage VOL 140 120 VCC = VCC(NOMINAL) Ta = 25 C 1.0 0.2 Change in tAA (ns) 0.9 125 1.2 VCC = VCC(NOMINAL) Normalized ICC Normalized access time 1.3 -10 35 80 Ambient temperature (C) Normalized supply current ICC vs. cycle frequency 1/tRC, 1/tWC 1.4 1.4 Ta = 25 C VCC = VCC(NOMINAL) 25 Normalized access time tAA vs. ambient temperature Ta 1.5 1.4 Normalized access time 0.8 0.2 0.0 MIN Output source current (mA) ICC 1.0 Normalized supply current ISB1 vs. ambient temperature Ta Normalized ISB1 (log scale) 1.2 ICC Normalized ICC, ISB Normalized ICC, ISB 1.2 Normalized supply current ICC, ISB vs. ambient temperature Ta 0 0 VCC Output voltage (V) Alliance Semiconductor 0 250 500 750 Capacitance (pF) 1000 P. 7 of 9 AS7C4098 AS7C34098 (R) Package dimensions e He 44-pin TSOP II 1 2 3 4 5 6 7 8 9 101112131415161718 19202122 d l A2 A 0-5 A1 A A1 A2 b c d e He E l 44-pin TSOP II Min (mm) Max (mm) 1.2 0.05 0.95 1.05 0.25 0.45 0.15 (typical) 18.28 18.54 10.06 10.26 11.56 11.96 0.80 (typical) 0.40 0.60 A A1 A2 B b c D E E1 E2 e 44-pin SOJ 400 mils Min(mils) Max(mils) 0.128 0.148 0.025 1.105 1.115 0.026 0.032 0.015 0.020 0.007 0.013 1.120 1.130 0.370 NOM 0.395 0.405 0.435 0.445 0.050 NOM c 44 434241403938373635343332313029282726252423 E b e D E1 E2 44-pin SOJ Pin 1 c B A A2 A1 b E2 Seating Plane Ordering Codes Package SOJ TSOP II Version 10 ns 12 ns 15 ns 20 ns 5V commercial NA AS7C4098-12JC AS7C4098-15JC AS7C4098-20JC 5V industrial NA AS7C4098-12JI AS7C4098-15JI AS7C4098-20JI 3.3V commercial AS7C34098-10JC AS7C34098-12JC AS7C34098-15JC AS7C34098-20JC 3.3V industrial NA AS7C34098-12JI AS7C34098-15JI AS7C34098-20JI 5V commercial NA AS7C4098-12TC AS7C4098-15TC AS7C4098-20TC 5V industrial NA AS7C4098-12TI AS7C4098-15TI AS7C4098-20TI 3.3V commercial AS7C34098-10TC AS7C34098-12TC AS7C34098-15TC AS7C34098-20TC 3.3V industrial NA AS7C34098-12TI AS7C34098-15TI AS7C34098-20TI NA: not available. 3/23/01; v.1.0 Alliance Semiconductor P. 8 of 9 AS7C4098 AS7C34098 (R) Part numbering system AS7C X 4098 -XX J, T X SRAM prefix Blank: 5V CMOS 3: 3.3V CMOS Device number Access time Packages: J: SOJ 400 mil T: TSOP II 400 mil Temperature ranges: C: Commercial, 0C to 70C I: Industrial, -40C to 85C 3/23/01; v.1.0 Alliance Semiconductor P. 9 of 9 (c) Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.