March 2001
Copyright © Alliance Semiconductor. All rights reserved.
®
AS7C4098
AS7C34098
5V/3.3V 256K × 16 CMOS SRAM
3/23/01; v.1.0 Alliance Semiconductor P. 1 of 9
Features
• AS7C4098 (5V version)
• AS7C34098 (3.3V version)
• Industrial and commercial temperature
• Organization: 262,144 words × 16 bits
• Center power and ground pins
• High speed
- 10/12/15/20 ns address access time
- 5/6/7/8 ns output enable access time
• Low power consumption: ACTIVE
- 1375 mW (AS7C4098)/max @ 12 ns
- 468 mW (AS7C34098)/max @ 12 ns
• Low power consumption: STANDBY
- 110 mW (AS7C4098)/max CMOS
- 72 mW (AS7C34098)/max CMOS
• Individual byte read/write controls
• 2.0V data retention
• Easy memory expansion with CE, OE inputs
• TTL- and CMOS-compatible, three-state I/O
• 44-pin JEDEC standard packages
-400-mil SOJ
-400-mil TSOP II
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Logic block diagram
1024 × 256 × 16
Array
(4,194,304)
OE
CE
WE Column decoder
Row Decoder
A0
A1
A2
A3
A4
A6
A7
A8
V
CC
GND
A12
A5
A9
A10
A11
A14
A15
A16
A17
A13
Control circuit
I/O1–I/O8
I/O9–I/O16
UB
LB
I/O
buffer
Pin arrangement
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
I/O14
I/O13
GND
V
CC
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
A4
CE
I/O1
I/O2
I/O3
I/O4
V
CC
GND
I/O5
I/O6
I/O7
I/O8
WE
A5
A6
A7
44-pin SOJ, TSOP II (400 mil)
21
22
A8
A9
UB
LB
I/O16
I/O15
2A1 3A2 4A3
1A0
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
43
42
41
44 A16
A15
OE
A17
Selection guide
AS7C34098
–10
AS7C4098
AS7C34098
–12
AS7C4098
AS7C34098
–15
AS7C4098
AS7C34098
–20 Unit
Maximum address
access time 10 12 15 20 ns
Maximum output
enable access time 5679ns
Maximum operating
current
AS7C4098 – 250 220 180 mA
AS7C34098 160 130 110 100 mA
Maximum CMOS
standby current
AS7C4098 – 20 20 20 mA
AS7C34098 20 20 20 20 mA
®
AS7C4098
AS7C34098
3/23/01; v.1.0 Alliance Semiconductor P. 2 of 9
Functional description
The AS7C4098 and AS7C34098 are high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) devices
organized as 262,144 words × 16 bits. They are designed for memory applications where fast data access, low power, and
simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5/6/7/8 ns
are ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank
memory systems.
When CE is High the device enters standby mode. The standard AS7C4098 is guaranteed not to exceed 110 mW power
consumption in CMOS standby mode. Both devices offer 2.0V data retention.
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O1–I/O16 is
written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive
I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) High. The chip
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or
write enable is active, output drivers stay in high-impedance mode.
These devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to
be written and read. LB controls the lower bits, I/O1–I/O8, and UB controls the higher bits, I/O9–I/O16.
All chip inputs and outputs are TTL- and CMOS-compatible, and operation is from either a single 5V (AS7C4098) or 3.3V
(AS7C34098) supply. Both devices are available in the JEDEC standard 400-mL, 44-pin SOJ and TSOP II packages.
Absolute maximum ratings
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
Key: X = Don’t care, L = Low, H = High.
Parameter Device Symbol Min Max Unit
Vol tage o n VCC relative to GND AS7C4098 Vt1 –0.50 +7.0 V
AS7C34098 Vt1 –0.50 +5.0 V
Voltage on any pin relative to GND Vt2 –0.50 VCC +0.50 V
Power dissipation PD–1.5W
Storage temperature (plastic) Tstg –65 +150 °C
Ambient temperature with VCC applied Tbias –55 +125 °C
DC current into outputs (low) IOUT –±20mA
CE WE OE LB UB I/O1–I/O8 I/O9–I/O16 Mode
H X X X X High Z High Z Standby (ISB, ISB1)
LHHXX High Z High Z Output disable (ICC)
LXXHH
LHL
LH D
OUT High Z
Read (ICC)HL High Z D
OUT
LL D
OUT DOUT
LLX
LH D
IN High Z
Write (ICC)HL High Z D
IN
LL D
IN DIN
®
AS7C4098
AS7C34098
3/23/01; v.1.0 Alliance Semiconductor P. 3 of 9
Recommended operating conditions
DC operating characteristics (over the operating range)1
Capacitance (f = 1MHz, Ta = 25° C, VCC = NOMINAL)2
Parameter Symbol Min Typical Max Unit
Supply voltage
AS7C4098 VCC (10/12/15/20) 4.5 5.0 5.5 V
AS7C34098 VCC (–10) 3.15 3.3 3.6 V
AS7C34098 VCC (10/12/15/20) 3.0 3.3 3.6 V
Input voltage
AS7C4098 VIH 2.2 – VCC + 0.5 V
AS7C34098 VIH 2.0 – VCC + 0.5 V
VIL –0.5*
* VIL min = –3.0V for pulse width less than tRC/2.
–0.8V
Ambient operating temperature commercial TA0– 70°C
industrial TA–40 – 85 °C
Parameter Symbol Test conditions
–10 –12 –15 –20
UnitMin Max Min Max Min Max Min Max
Input leakage
current |ILI|VCC = Max
VIN = GND to VCC –1– 1–1–1µA
Output leakage
current |ILO|
VCC = Max
CE = VIH or OE = VIH
or WE = VIL
VI/O = GND to VCC
–1– 1–1–1µA
Operating
power supply
current
ICC
VCC = Max
Min cycle, 100% duty
CE = VIL, IOUT = 0mA
AS7C4098 – – – 250 – 220 – 180 mA
AS7C34098 – 160 – 130 – 110 – 100 mA
Standby power
supply current
ISB
VCC = Max
CE = VIH, f = Max
AS7C4098 – – – 60 – 60 – 60 mA
AS7C34098 – 60 – 60 – 60 – 60 mA
ISB1
VCC = Max
CE ≥ VCC – 0.2V, VIN ≥ VCC
– 0.2V or VIN ≤ 0.2V, f = 0
AS7C4098 – – – 20 – 20 – 20 mA
AS7C34098 – 20 – 20 – 20 – 20 mA
Output voltage VOL IOL = 8 mA, VCC = Min – 0.4 – 0.4 – 0.4 – 0.4 V
VOH IOH = –4 mA, VCC = Min 2.4 – 2.4 – 2.4 – 2.4 – V
Parameter Symbol Signals Test conditions Max Unit
Input capacitance CIN A, CE, WE, OE, UB, LB VIN = 0V 6 pF
I/O capacitance CI/O I/O VIN = VOUT = 0V 8 pF
®
AS7C4098
AS7C34098
3/23/01; v.1.0 Alliance Semiconductor P. 4 of 9
Read cycle (over the operating range)3,9
Key to switching waveforms
Read waveform 1 (address controlled)6,7,9
Read waveform 2 (CE, OE, UB, LB controlled)6,8,9
Parameter Symbol
–10 –12 –15 –20
Unit NotesMin Max Min Max Min Max Min Max
Read cycle time tRC 10 – 12 – 15 – 20 – ns
Address access time tAA – 10 – 12 – 15 – 20 ns
Chip enable (CE) access time tACE – 10 – 12 – 15 – 20 ns
Output enable (OE) access time tOE – 5 –6–7–8ns
Output hold from address change tOH 3 – 3–3–3–ns5
CE Low to output in low Z tCLZ 0 – 3–0–0–ns4, 5
CE High to output in higfch Z tCHZ – 5 –6–7–9ns4, 5
OE Low to output in low Z tOLZ 0 – 0–0–0–ns4, 5
OE High to output in high Z tOHZ – 5 –6–7–9ns4, 5
LB, UB access time tBA – 5 –6–7–8ns
LB, UB Low to output in low Z tBLZ 0 – 0–0–0–ns
LB, UB High to output in high Z tBHZ – 5 –6–7–9ns
Power up time tPU 0 – 0–0–0–ns5
Power down time tPD – 10 – 12 – 15 – 20 ns 5
Undefined/don’t careFalling inputRising input
t
OH
t
AA
t
RC
t
OH
Data
OUT
Address
Data validPrevious data valid
Data valid
t
RC
t
AA
t
BLZ
t
BA
t
OE
t
OLZ
t
OH
t
OHZ
t
CHZ
t
BHZ
t
ACE
t
LZ
Address
OE
CE
LB, UB
Data
OUT
®
AS7C4098
AS7C34098
3/23/01; v.1.0 Alliance Semiconductor P. 5 of 9
Write cycle (over the operating range)11
Write waveform 1(WE controlled)10,11
Write waveform 2 (CE controlled)10,11
Parameter Symbol
–10 –12 –15 –20
Unit NoteMin Max Min Max Min Max Min Max
Write cycle time tWC 10 – 12 – 15 – 20 – ns
Chip enable (CE) to write end tCW 7–8–10–12–ns
Address setup to write end tAW 7–8–10–12–ns
Address setup time tAS 0–0–0–0–ns
Write pulse width (OE = High) tWP1 7–8–10–12–ns
Write pulse width (OE = Low) tWP2 10 – 12 – 15 – 20 – ns
Address hold from end of write tAH 0–0–0–0–ns
Data valid to write end tDW 5 6 7–9–ns
Data hold time tDH 0–0–0–0–ns4, 5
Write enable to output in High-Z tWZ 05060709ns4, 5
Output active from write end tOW 3–3–3–3–ns4, 5
Byte enable Low to write end tBW 7 – 8 – 10 – 12 – ns 4, 5
Address
CE
LB, UB
WE
Data
IN
Data
OUT
t
WC
t
CW
t
BW
t
AW
t
AS
t
WP
t
DW
t
DH
t
OW
t
WZ
t
AH
Data undefined High Z
Data valid
Address
CE
LB, UB
WE
Data
IN
t
WC
t
CW
t
BW
t
WP
t
DW
t
DH
t
OW
t
WZ
t
AH
Data
OUT
Data undefined
High Z High Z
t
AS
t
AW
Data valid
t
CLZ
®
AS7C4098
AS7C34098
3/23/01; v.1.0 Alliance Semiconductor P. 6 of 9
Write waveform 3 10,11
Data retention characteristics 13
Data retention waveform
AC test conditions
Notes
1During V
CC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
2 This parameter is sampled, but not 100% tested.
3 For test conditions, see AC Test Conditions, Figures A, B, C.
4t
CLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured ±500mV from steady-state voltage.
5 This parameter is guaranteed, but not tested.
6WE
is High for read cycle.
7CE
and OE are Low for read cycle.
8 Address valid prior to or coincident with CE transition Low.
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 Not applicable.
13 2V data retention applies to commercial temperature range operation only.
14 C = 30pF, except on High Z and Low Z parameters, where C = 5pF.
Parameter Symbol Test conditions Min Max Unit
VCC for data retention VDR VCC = 2.0V
CE ≥ VCC – 0.2V
VIN ≥ VCC – 0.2V or
VIN ≤ 0.2V
2.0 – V
Data retention current ICCDR –500µA
Chip deselect to data retention time tCDR 0–ns
Operation recovery time tRtRC –ns
Input leakage current |ILI|–1µA
Address
CE
LB, UB
WE
Data
IN
t
WC
t
CW
t
BW
t
WP
t
DW
t
DH
t
WZ
t
AH
Data
OUT
Data undefined
High Z High Z
t
AS
t
AW
Data valid
V
CC
CE
t
R
t
CDR
Data retention mode
V
CC
V
CC
V
DR
≥
2.0V
V
IH
V
IH
V
DR
- Output load: see Figure B or Figure C.
- Input pulse level: GND to 3.0V. See Figure A.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
10%
90%
10%
90%
GND
+3.0V
2 ns
Figure A: Input pulse
255W C(14)
480W
D
OUT
GND
+5V
Figure B: 5V Output load
350W C(14)
320W
D
OUT
GND
+3.3V
Figure C: 3.3V Output load
168W
Thevenin equivalent: D
OUT
+1.728V (5V and 3.3V)
®
AS7C4098
AS7C34098
3/23/01; v.1.0 Alliance Semiconductor P. 7 of 9
Typical DC and AC characteristics12
Supply voltage (V)
MIN MAX
NOMINAL
0.0
0.2
0.6
0.8
0.4
1.0
1.2
1.4
Normalized I
CC
, I
SB
Normalized supply current ICC, ISB
Ambient temperature (
°
C)
–55 80 125
35–10
0.0
0.2
0.6
0.8
0.4
1.0
1.2
1.4
Normalized I
CC
, I
SB
Normalized supply current I
CC
, I
SB
vs. ambient temperature T
a
vs. supply voltage VCC
I
CC
I
SB
I
CC
I
SB
Ambient temperature (
°
C)
–55 80 125
35–10
0.2
1
0.04
5
25
625
Normalized ISB1 (log scale)
Normalized supply current I
SB1
vs. ambient temperature T
a
V
CC
= V
CC
(NOMINAL)
Supply voltage (V)
MIN MAX
NOMINAL
0.8
0.9
1.1
1.2
1.0
1.3
1.4
1.5
Normalized access time
Normalized access time t
AA
Ambient temperature (
°
C)
–55 80 125
35–10
0.8
0.9
1.1
1.2
1.0
1.3
1.4
1.5
Normalized access time
Normalized access time t
AA
Cycle frequency (MHz)
075
100
5025
0.0
0.2
0.6
0.8
0.4
1.0
1.2
1.4
Normalized I
CC
Normalized supply current I
CC
vs. ambient temperature T
a
vs. cycle frequency 1/t
RC
, 1/t
WC
vs. supply voltage V
CC
V
CC
= V
CC
(NOMINAL)
T
a
= 25
°
C
V
CC
= V
CC
(NOMINAL)T
a
= 25
°
C
Output voltage (V)
V
CC
0
20
60
80
40
100
120
140
Output source current (mA)
Output source current I
OH
Output voltage (V)
V
CC
Output sink current (mA)
Output sink current I
OL
vs. output voltage V
OL
vs. output voltage V
OH
0
20
60
80
40
100
120
140
V
CC
= V
CC
(NOMINAL)PL
T
a
= 25
°
C
V
CC
= V
CC
(NOMINAL)
T
a
= 25
°
C
Capacitance (pF)
0750 1000
500250
0
5
15
20
10
25
30
35
Change in t
AA
(ns)
Typical access time change
∆
t
AA
vs. output capacitive loading
V
CC
= V
CC
(NOMINAL)
00
®
AS7C4098
AS7C34098
3/23/01; v.1.0 Alliance Semiconductor P. 8 of 9
Package dimensions
NA: not available.
Package Version 10 ns 12 ns 15 ns 20 ns
SOJ
5V commercial NA AS7C4098-12JC AS7C4098-15JC AS7C4098-20JC
5V industrial NA AS7C4098-12JI AS7C4098-15JI AS7C4098-20JI
3.3V commercial AS7C34098-10JC AS7C34098-12JC AS7C34098-15JC AS7C34098-20JC
3.3V industrial NA AS7C34098-12JI AS7C34098-15JI AS7C34098-20JI
TSOP II
5V commercial NA AS7C4098-12TC AS7C4098-15TC AS7C4098-20TC
5V industrial NA AS7C4098-12TI AS7C4098-15TI AS7C4098-20TI
3.3V commercial AS7C34098-10TC AS7C34098-12TC AS7C34098-15TC AS7C34098-20TC
3.3V industrial NA AS7C34098-12TI AS7C34098-15TI AS7C34098-20TI
44-pin TSOP II
Min (mm) Max (mm)
A1.2
A10.05
A20.95 1.05
b 0.25 0.45
c 0.15 (typical)
d 18.28 18.54
e 10.06 10.26
He11.56 11.96
E 0.80 (typical)
l 0.40 0.60
d
H
e
1234567891011121314
44 43424140393837363534333231
1516
3029
1718 1920
272625
c
l
A
1
A
2
E
44-pin TSOP II
0–5
°
21
24
22
23
e
A
b
44-pin SOJ 400 mils
Min(mils) Max(mils)
A 0.128 0.148
A1 0.025 -
A2 1.105 1.115
B 0.026 0.032
b 0.015 0.020
c 0.007 0.013
D 1.120 1.130
E0.370 NOM
E1 0.395 0.405
E2 0.435 0.445
e0.050 NOM
Seating
Plane
44-pin SOJ
28
Pin 1
D
e
E2
E1
A1
b
B
AA2
E2
c
O
rdering Codes
®
AS7C4098
AS7C34098
© Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names
may be the trademarks of their respective companies. Alliance re serves the right to make changes to this document a nd its products at any time without notice. Alliance assumes no responsibility for any errors
that may appear in this document. T he da ta c ontaine d herein represents Alli ance’s best data and/or estimates a t the time of issuance. Alliance reserves the right to change or cor rect this data at any time, without
notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information
for potential customers and users, and is not intended to operate as, or provide, any guarantee or war rantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the
application or use of any product described herein, and dis claims any express or i mplied warranties r elated to the sale and/or use of Allia nc e products including liabilit y or warranties relate d to fitness for a par-
ticular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance’ s T e rms and Conditions of Sale (which are available from Alliance). All sales of Alli-
ance products ar e made exclusively according to A lliance’s Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works
rights, trademarks, or any other intellectual prope rty rights of Allianc e or third parties. Alliance does not authoriz e its products for use as critical components in life-supporting systems where a malfunction or
failure may reasonably be expected to result in significant injury to the user , and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of s uch us e and
agrees to indemnify Alliance against all claims arising from such use.
3/23/01; v.1.0 Alliance Semiconductor P. 9 of 9
Part numbering system
AS7C X 4098 –XX J, T X
SRAM prefix Blank: 5V CMOS
3: 3.3V CMOS
Device
number Access time
Packages:
J: SOJ 400 mil
T: TSOP II 400 mil
Temperature ranges:
C: Commercial, 0°C to 70°C
I: Industrial, –40°C to 85°C
