LTC3417
1
3417fd
TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
Dual Synchronous
1.4A/800mA 4MHz
Step-Down DC/DC Regulator
The LTC
®
3417 is a dual constant frequency, synchronous
step-down DC/DC converter. Intended for medium power
applications, it operates from a 2.25V to 5.5V input volt-
age range and has a constant programmable switching
frequency, allowing the use of tiny, low cost capacitors
and inductors 2mm or less in height. Each output voltage
is adjustable from 0.8V to 5V. Internal synchronous low
RDS(ON) power switches provide high effi ciency without
the need for external Schottky diodes.
A user selectable mode input allows the user to trade
off ripple voltage for light load effi ciency. Burst Mode
®
operation provides high effi ciency at light loads, while
Pulse Skip mode provides low ripple noise at light loads.
A phase mode pin allows the second channel to operate
in-phase or 180° out-of-phase with respect to channel 1.
Out-of-phase operation produces lower RMS current on
VIN and thus lower RMS derating on the input capacitor.
To further maximize battery life, the P-channel MOSFETs
are turned on continuously in dropout (100% duty cycle)
and both channels draw a total quiescent current of only
125µA. In shutdown, the device draws <1µA.
OUT2 Effi ciency
(Burst Mode Operation)
n High Effi ciency: Up to 95%
n 1.4A/800mA Guaranteed Minimum Output Current
n No Schottky Diodes Required
n Programmable Frequency Operation: 1.5MHz or
Adjustable From 0.6MHz to 4MHz
n Low RDS(ON) Internal Switches
n Short-Circuit Protected
n
V
IN: 2.25V to 5.5V
n
Current Mode Operation for Excellent Line and
Load Transient Response
n
125µA Quiescent Current in Sleep Mode
n
Ultralow Shutdown Current: IQ < 1µA
n
Low Dropout Operation: 100% Duty Cycle
n
Power Good Output
n
Phase Pin Selects 2nd Channel Phase Relationship
with Respect to 1st Channel
n
Internal Soft-Start with Individual Run Pin Control
n Available in Small Thermally Enhanced
(5mm × 3mm) DFN and 20-Lead TSSOP Packages
n PDAs/Palmtop PCs
n
Digital Cameras
n
Cellular Phones
n
PC Cards
n Wireless and DSL Modems
L, LT, LTC, LTM and Burst Mode are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Protected by U.S. Patents
including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131, 6144194.
FREQ
SW1
RUN1
VFB1
ITH1
SW2
RUN2
VFB2
ITH2
VIN
LTC3417
GND
10µF
1.5µH 2.2µH
22pF
511k
22pF
866k
VIN VIN
412k 412k 10µF
5.9k 2.87k
2200pF 6800pF
3417 TA01
22µF
VOUT1
1.8V
1.4A
VOUT2
2.5V
800mA
VIN
2.5V TO 5.5V
LOAD CURRENT (A)
0.001
70
EFFICIENCY (%)
90
95
100
0.01 0.1 1
3417 TA01a
85
80
75
POWER LOSS (W)
0.001
0.01
0.1
1
10
0.0001
EFFICIENCY
REFER TO FIGURE 4
POWER LOSS
VIN = 3.6V
VOUT = 2.5V
FREQ = 1MHz
LTC3417
2
3417fd
ABSOLUTE MAXIMUM RATINGS
VIN1, VIN2 Voltages ...................................... –0.3V to 6V
MODE, SW1, SW2, RUN1,
RUN2, VFB1, VFB2, PHASE, FREQ,
ITH1, ITH2 Voltages............... –0.3V to (VIN1/VIN2 + 0.3V)
VIN1 – VIN2, VIN2 – VIN1 .......................................... 0.3V
PGOOD Voltage ........................................... –0.3V to 6V
(Note 1)
16
15
14
13
12
11
10
9
17
1
2
3
4
5
6
7
8
PGND1
SW1
PHASE
GNDA
FREQ
PGOOD
SW2
MODE
RUN1
VIN1
ITH1
VFB1
VFB2
ITH2
RUN2
VIN2
TOP VIEW
DHC PACKAGE
16-LEAD (3mm × 5mm) PLASTIC DFN
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 17) IS PGND2/GNDD, MUST BE SOLDERED TO PCB
FE PACKAGE
20-LEAD PLASTIC TSSOP
1
2
3
4
5
6
7
8
9
10
TOP VIEW
20
19
18
17
16
15
14
13
12
11
GNDD
RUN1
VIN1
ITH1
VFB1
VFB2
ITH2
RUN2
VIN2
PGND2
GNDD
PGND1
SW1
PHASE
GNDA
FREQ
PGOOD
SW2
MODE
PGND2
21
TJMAX = 150°C, θJA = 38°C/W
EXPOSED PAD (PIN 21) IS PGND2/GNDD, MUST BE SOLDERED TO PCB
PIN CONFIGURATION
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3417EDHC#PBF LTC3417EDHC#TRPBF 3417 16-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC3417EFE#PBF LTC3417EFE#TRPBF LTC3417EFE 20-Lead Plastic TSSOP –40°C to 85°C
LEAD BASED FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3417EDHC LTC3417EDHC#TR 3417 16-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC3417EFE LTC3417EFE#TR LTC3417EFE 20-Lead Plastic TSSOP –40°C to 85°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
Operating Ambient Temperature Range
(Note 2) .................................................. –40°C to 85°C
Junction Temperature (Notes 7, 8) ...................... 125°C
Storage Temperature Range
DFN Package ..................................... –65°C to 125°C
TSSOP Package ................................ –65°C to 150°C
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN1, VIN2 Operating Voltage Range VIN1 = VIN2 ●2.25 5.5 V
IFB1, IFB2 Feedback Pin Input Current (Note 3) ±0.1 µA
VFB1, VFB2 Feedback Voltage (Note 3) ●0.784 0.8 0.816 V
ΔVLINEREG Reference Voltage Line Regulation. %/V is the
Percentage Change in VOUT with a Change in VIN
VIN = 2.25V to 5V (Note 3) 0.04 0.2 %/V
VLOADREG Output Voltage Load Regulation ITH1, ITH2 = 0.36V (Note 3)
ITH1, ITH2 = 0.84V (Note 3)
0.02
–0.02
0.2
–0.2
%
%
ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VIN = 3.6V unless otherwise specifi ed. (Note 2)
LTC3417
3
3417fd
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3417 is guaranteed to meet specifi ed performance from
0°C to 85°C. Specifi cations over the –40°C to 85°C operating ambient
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: The LTC3417 is tested in feedback loop which servos VFB1 to the
midpoint for the error amplifi er (VITH1 = 0.6V) and VFB2 to the midpoint for
the error amplifi er (VITH2 = 0.6V).
Note 4: Total supply current is higher due to the internal gate charge being
delivered at the switching frequency.
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VIN = 3.6V unless otherwise specifi ed. (Note 2)
Note 5: Switch on-resistance is guaranteed by design and test correlation
on the DHC package and by fi nal test correlation on the FE package.
Note 6: Variable frequency operation with resistor is guaranteed by design
but not production tested and is subject to duty cycle limitations.
Note 7: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specifi ed maximum operating junction
temperature may impair device reliability.
Note 8: TJ is calculated from the ambient temperature, TA, and power dis-
sipation, PD, according to the following formula:
LTC3417EDHC: TJ = TA + (PD • 43°C/W)
LTC3417EFE: TJ = TA + (PD • 38°C/W)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
gm(EA) Error Amplifi er Transconductance ITH1, ITH2(PINLOAD) = ±5µA (Note 3) 1400 µS
ISInput DC Supply Current (Note 4)
Active Mode VFB1 = VFB2 = 0.75V, VMODE = VIN,
VRUN1 = VRUN2 = VIN
400 600 µA
Half Active Mode (VRUN2 = 0V, 1.4A Only) VFB1 = 0.75V, VMODE = VIN, VRUN1 = VIN 260 400 µA
Half Active Mode (VRUN1 = 0V, 800mA Only) VFB2 = 0.75V, VMODE = VIN, VRUN2 = VIN 260 400 µA
Both Channels in Sleep Mode VFB1 = VFB2 = 1V, VMODE = VIN,
VRUN1 = VRUN2 = VIN
125 250 µA
Shutdown VRUN1 = VRUN2 = 0V 0.1 1 µA
fOSC Oscillator Frequency VFREQ = VIN
VFREQ: RT = 143k
VFREQ: Resistor (Note 6)
1.2
0.85
1.5
1
1.8
1.25
4
MHz
MHz
MHz
ILIM1 Peak Switch Current Limit on SW1 (1.4A) 1.8 2.25 A
ILIM2 Peak Switch Current Limit on SW2 (800mA) 1 1.2 A
RDS(ON)1 SW1 Top Switch On-Resistance (1.4A)
SW1 Bottom Switch On-Resistance
VIN1 = 3.6V (Note 5)
VIN1 = 3.6V (Note 5)
0.088
0.084
RDS(ON)2 SW2 Top Switch On-Resistance (800mA)
SW2 Bottom Switch On-Resistance
VIN2 = 3.6V (Note 5)
VIN2 = 3.6V (Note 5)
0.16
0.15
ISW1(LKG) Switch Leakage Current SW1 (1.4A) VIN1 = 6V, VITH1 = 0V, VRUN1 = 0V 0.01 1 µA
ISW2(LKG) Switch Leakage Current SW2 (800mA) VIN2 = 6V, VITH2 = 0V, VRUN2 = 0V 0.01 1 µA
VUVLO Undervoltage Lockout Threshold VIN1, VIN2 Ramping Down
VIN1, VIN2 Ramping Up
1.9
1.95
2.07
2.12
2.2
2.25
V
V
TPGOOD Threshold for Power Good. Percentage
Deviation from VFB Steady State
(Typically 0.8V)
VFB1 or VFB2 Ramping Up
VFB1 or VFB2 Ramping Down
–6
–6
%
%
RPGOOD Power Good Pull-Down On-Resistance 160 300
VRUN1,
VRUN2
RUN1, RUN2 Threshold 0.3 0.85 1.5 V
VPHASE PHASE Threshold High-CMOS Levels VIN –0.5 V
PHASE Threshold Low-CMOS Levels 0.5 V
IRUN1, IRUN2,
IPHASE, IMODE
RUN1, RUN2, PHASE and MODE
Leakage Current
VIN = 6V, VPIN = 3V 0.01 1 µA
VTLMODE MODE Threshold Voltage Low 0.5 V
VTHMODE MODE Threshold Voltage High VIN –0.5 V
VTHFREQ FREQ Threshold Voltage High VIN –0.5 V
LTC3417
4
3417fd
TYPICAL PERFORMANCE CHARACTERISTICS
OUT1 Burst Mode Operation
OUT1 Pulse Skipping
Mode Operation
OUT1 Forced Continuous
Mode Operation
OUT2 Burst Mode Operation
OUT2 Pulse Skipping
Mode Operation
OUT2 Forced Continuous
Mode Operation
OUT1 Effi ciency vs Load Current OUT2 Effi ciency vs Load Current
OUT1 Effi ciency vs VIN
(Burst Mode Operation)
3417 G01
VIN = 3.6V
VOUT = 1.8V
ILOAD = 100mA
REFER TO FIGURE 4
IL
250mA/DIV
VOUT
20mV/DIV
2µs/DIV 3417 G02
VIN = 3.6V
VOUT = 1.8V
ILOAD = 100mA
REFER TO FIGURE 4
IL
250mA/DIV
VOUT
20mV/DIV
2µs/DIV 3417 G03
VIN = 3.6V
VOUT = 1.8V
ILOAD = 100mA
REFER TO FIGURE 4
IL
250mA/DIV
VOUT
20mV/DIV
2µs/DIV
3417 G04
VIN = 3.6V
VOUT = 2.5V
ILOAD = 60mA
REFER TO FIGURE 4
IL
250mA/DIV
VOUT
20mV/DIV
2µs/DIV 3417 G05
VIN = 3.6V
VOUT = 2.5V
ILOAD = 60mA
REFER TO FIGURE 4
IL
250mA/DIV
VOUT
20mV/DIV
2µs/DIV 3417 G06
VIN = 3.6V
VOUT = 2.5V
ILOAD = 60mA
REFER TO FIGURE 4
IL
250mA/DIV
VOUT
20mV/DIV
2µs/DIV
LOAD CURRENT (A)
70
EFFICIENCY (%)
80
85
95
100
0.001 0.1 1 10
3417 G07
60
0.01
90
75
65
VIN = 2.5V
VOUT = 1.8V
Burst Mode
OPERATION
PULSE SKIP
FORCED
CONTINUOUS
REFER TO FIGURE 4
LOAD CURRENT (A)
0.001
80
EFFICIENCY (%)
90
100
0.01 0.1 1
3417 G08
70
75
85
95
65
60
VIN = 3.6V
VOUT = 2.5V
Burst Mode
OPERATION
PULSE SKIP
FORCED
CONTINUOUS
REFER TO FIGURE 4
VIN (V)
2 2.5 3.5 4.5 5.5
EFFICIENCY (%)
90
95
100
3417 G09
85
80
345
75
70
VOUT = 1.8V
ILOAD = 1.4A
ILOAD = 460mA
REFER TO FIGURE 4
LTC3417
5
3417fd
TYPICAL PERFORMANCE CHARACTERISTICS
OUT2 Effi ciency vs VIN
(Pulse Skipping Mode) Load Step OUT1 Load Step OUT2
Effi ciency vs Frequency OUT1 Effi ciency vs Frequency OUT2 RDS(ON) vs VIN OUT1
RDS(ON) vs VIN OUT2 Frequency vs VIN Frequency vs Temperature
VIN (V)
2 2.5
EFFICIENCY (%)
90
95
100
3417 G10
85
80
3 3.5 4 4.5 5 5.5
75
70
VOUT = 2.5V
REFER TO FIGURE 4
ILOAD = 800mA
ILOAD = 250mA
VIN = 3.6V
VOUT = 1.8V
ILOAD = 0.25A to 1.4A
REFER TO FIGURE 4
IOUT1
500mA/DIV
VOUT1
100mV/DIV
3417 G11
100µs/DIV VIN = 3.6V
VOUT = 2.5V
ILOAD = 0.25A to 0.8A
REFER TO FIGURE 4
IOUT2
500mA/DIV
VOUT2
100mV/DIV
3417 G12
100µs/DIV
FREQUENCY (MHz)
0
82
EFFICIENCY (%)
84
86
88
90
92
94
1234
3417 G13
5
TA = 27°C
VIN = 3.6V
VOUT = 1.8V
IOUT = 300mA
FREQUENCY (MHz)
0
60
EFFICIENCY (%)
65
70
75
80
85
90
12 34
3417 G14
TA = 27°C
VIN = 3.6V
VOUT = 2.5V
IOUT = 100mA
VIN (V)
2 2.5
0.080
RDS(ON) (Ω)
0.090
0.105
344.5
3417 G15
0.085
0.100
0.095
3.5 55.5
TA = 27°C
P-CHANNEL SWITCH
N-CHANNEL SWITCH
VIN (V)
2
RDS(ON) (Ω)
0.18
0.19
0.20
3.5 4.5
3417 G16
0.17
0.16
2.5 3 4 5 5.5
0.15
0.14
TA = 27°C
P-CHANNEL SWITCH
N-CHANNEL SWITCH
VIN (V)
2
FREQUENCY VARIATION (%)
0
2
4
5 5.5
3417 G17
–4
–10 2.5 3 3.5 4 4.5
6
–2
–6
–8
FREQ = 143k TO GROUND
FREQ = VIN
TEMPERATURE (°C)
–50
FREQUENCY VARIATION (%)
5
10
15
25 75
3417 G18
0
–5
–25 0 50 100 125
–10
–15
FREQ = 143k TO GROUND
FREQ = VIN
LTC3417
6
3417fd
PIN FUNCTIONS
RUN1 (Pin 1/Pin 2): Enable for 1.4A Regulator. When
at Logic 1, 1.4A regulator is running. When at 0V, 1.4A
regulator is off. When both RUN1 and RUN2 are at 0V, the
part is in shutdown.
VIN1 (Pin 2/Pin 3): Supply Pin for P-channel Switch of
1.4A Regulator.
ITH1 (Pin 3/Pin 4): Error Amplifi er Compensation Point
for 1.4A Regulator. The current comparator threshold
increases with this control voltage. Nominal voltage range
for this pin is 0V to 1.5V.
VFB1 (Pin 4/Pin 5): Receives the feedback voltage from
external resistive divider across the 1.4A regulator output.
Nominal voltage for this pin is 0.8V.
VFB2 (Pin 5/Pin 6): Receives the feedback voltage from
external resistive divider across the 800mA regulator
output. Nominal voltage for this pin is 0.8V.
ITH2 (Pin 6/Pin 7): Error Amplifi er Compensation Point
for 800mA regulator. The current comparator threshold
increases with this control voltage. Nominal voltage range
for this pin is 0V to 1.5V.
RUN2 (Pin 7/Pin 8): Enable for 800mA Regulator. When at
Logic 1, 800mA regulator is running. When at 0V, 800mA
regulator is off. When both RUN1 and RUN2 are at 0V, the
part is in shutdown.
VIN2 (Pin 8/Pin 9): Supply Pin for P-channel Switch of
800mA Regulator and Supply for Analog Circuitry.
MODE (Pin 9/Pin 12): Mode Selection Pin. This pin
controls the operation of the device. When the voltage
on the MODE pin is >(VIN – 0.5V), Burst Mode operation
is selected. When the voltage on the MODE pin is <0.5V,
pulse skipping mode is selected. When the MODE pin is
held at VIN/2, forced continuous mode is selected.
SW2 (Pin 10/Pin 13): Switch Node Connection to the
Inductor for the 800mA Regulator. This pin swings from
VIN2 to PGND2.
PGOOD (Pin 11/Pin 14): Power Good Pin. This common
drain-logic output is pulled to GND when the output voltage
of either regulator is –6% of regulation. If either RUN1 or
RUN2 is low (the respective regulator is in sleep mode and
therefore the output voltage is low), then PGOOD refl ects
the regulation of the running regulator.
FREQ (Pin 12/Pin 15): Frequency Set Pin. When FREQ is
at VIN, internal oscillator runs at 1.5MHz. When a resistor
is connected from this pin to ground, the internal oscillator
frequency can be varied from 0.6MHz to 4MHz.
GNDA (Pin 13/Pin 16): Analog Ground Pin for Internal
Analog Circuitry.
PHASE (Pin 14/Pin 17): Selects 800mA regulator switching
phase with respect to 1.4A regulator switching. Set to VIN,
the 1.4A regulator and the 800mA regulator are in phase.
When PHASE is at 0V, the 1.4A regulator and the 800mA
regulator are switching 180 degrees out-of-phase.
SW1 (Pin 15/Pin 18): Switch Node Connection to the
Inductor for the 1.4A Regulator. This pin swings from
VIN1 to PGND1.
PGND1 (Pin 16/Pin 19): Ground for SW1 N-channel
Driver.
PGND2, GNDD (Pins 1,10,11,20): TSSOP Package Only.
Ground for SW2 N-channel driver and digital ground for
circuit.
Exposed Pad (Pin 17/Pin 21): PGND2, GNDD. Ground for
SW2 N-channel driver and digital ground for circuit. The
Exposed Pad must be soldered to PCB ground.
(DFN/TSOP)
LTC3417
7
3417fd
FUNCTIONAL DIAGRAM
–
+
–
+
–
+
–
+
–
+
ITH
LIMIT
ITH1
1.4A REGULATOR
800mA REGULATOR
VB
0.752V
0.752V
VB
0.848V
0.848V
VIN2
VIN1
SW1
PGND1
PGOOD
PHASE
SLOPE
COMPENSATION
ANTI-SHOOT-
THROUGH
OSCILLATOR
LOGIC
–
+
–
+
VFB1
–
+
–
+
–
+
–
+
–
+
–
+
–
+
RUN1
RUN2
MODE
VFB2
ITH2 VIN2
3417 BD
FREQ
PGND2
SW2
SLOPE
COMPENSATION
ANTI-SHOOT-
THROUGH
ITH
LIMIT
LOGIC
VOLTAGE
REFERENCE
LTC3417
8
3417fd
The LTC3417 uses a constant frequency, current mode
architecture. Both channels share the same clock frequency.
The PHASE pin sets whether the channels are running
in-phase or out of phase. The operating frequency is de-
termined by connecting the FREQ pin to VIN for 1.5MHz
operation or by connecting a resistor from FREQ to ground
for a frequency from 0.6MHz to 4MHz. To suit a variety
of applications, the MODE pin allows the user to trade off
noise for effi ciency.
The output voltages are set by external dividers returned
to the VFB1 and VFB2 pins. An error amplifi er compares the
divided output voltage with a reference voltage of 0.8V and
adjusts the peak inductor current accordingly. Undervoltage
comparators will pull the PGOOD output low when either
output voltage is 6% below its targeted value.
Main Control Loop
For each regulator, during normal operation, the P-chan-
nel MOSFET power switch is turned on at the beginning
of a clock cycle when the VFB voltage is below the refer-
ence voltage. The current into the inductor and the load
increases until the current limit is reached. The switch
turns off and energy stored in the inductor fl ows through
the bottom N-channel MOSFET switch into the load until
the next clock cycle.
The peak inductor current is controlled by the voltage
on the ITH pin, which is the output of the error amplifi er.
This amplifi er compares the VFB pin to the 0.8V reference.
When the load current increases the VFB voltage decreases
slightly below the reference. This decrease causes the er-
ror amplifi er to increase the ITH voltage until the average
inductor current matches the new load current.
The main control loop is shut down by pulling the RUN pin
to ground. A digital soft-start is enabled after shutdown,
which will slowly ramp the peak inductor current up over
1024 clock cycles.
Low Current Operation
Three modes are available to control the operation of
the LTC3417 at low currents. Each of the three modes
automatically switch from continuous operation to the
selected mode when the load current is low.
To optimize effi ciency, Burst Mode operation can be
selected. When the load is relatively light, the LTC3417
automatically switches into Burst Mode operation in which
the PMOS switches operate intermittently based on load
demand. By running cycles periodically, the switching
losses, which are dominated by the gate charge losses
of the power MOSFETs, are minimized. The main control
loop is interrupted when the output voltage reaches the
desired regulated value. The hysteresis voltage comparator
trips when ITH is below 0.24V, shutting off the switch and
reducing the power. The output capacitor and the induc-
tor supply the power to the load until ITH exceeds 0.31V,
turning on the switch and the main control loop which
starts another cycle.
For lower output voltage ripple at low currents, pulse
skipping mode can be used. In this mode, the LTC3417
continues to switch at constant frequency down to very
low currents, where it will begin skipping pulses used to
control the power MOSFETs.
Finally, in forced continuous mode, the inductor current is
constantly cycled creating a fi xed output voltage ripple at all
output current levels. This feature is desirable in telecom-
munications since the noise is a constant frequency and is
thus easy to fi lter out. Another advantage of this mode is
that the regulator is capable of both sourcing current into
a load and sinking some current from the output.
The mode selection for the LTC3417 is set using the MODE
pin. The MODE pin sets the mode for both the 800mA and
the 1.4A step-down DC/DC converters.
Dropout Operation
When the input supply voltage decreases toward the output
voltage, the duty cycle increases to 100%. In this dropout
condition, the PMOS switch is turned on continuously with
the output voltage being equal to the input voltage minus
the voltage drops across the internal P-channel MOSFET
and inductor.
Low Supply Operation
The LTC3417 incorporates an undervoltage lockout circuit
which shuts down the part when the input voltage drops
below about 2.07V to prevent unstable operation.
OPERATION
LTC3417
9
3417fd
APPLICATIONS INFORMATION
Figure 1. Frequency vs RT
A general LTC3417 application circuit is shown in Figure 4.
External component selection is driven by the load require-
ment, and begins with the selection of the inductors L1
and L2. Once L1 and L2 are chosen, CIN, COUT1 and COUT2
can be selected.
Operating Frequency
Selection of the operating frequency is a tradeoff between
effi ciency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves effi ciency by
reducing internal gate charge losses but requires larger
inductance values and/or capacitance to maintain low
output ripple voltage.
The operating frequency, fO, of the LTC3417 is determined
by pulling the FREQ pin to VIN for 1.5MHz operation or
by connecting an external resistor from FREQ to ground.
The value of the resistor sets the ramp current that is
used to charge and discharge an internal timing capacitor
within the oscillator and can be calculated by using the
following equation:
RT=1.61• 1011
fO
()
– 16.586k
for 0.6MHz ≤ fO ≤ 4MHz. Alternatively, use Figure 1 to
select the value for RT
.
The maximum operating frequency is also constrained
by the minimum on-time and duty cycle. This can be
calculated as:
fO(MAX) 6.67 VOUT
VIN(MAX)
MHz
()
The minimum frequency is limited by leakage and noise
coupling due to the large resistance of RT
.
Inductor Selection
Although the inductor does not infl uence the operating
frequency, the inductor value has a direct effect on ripple
current. The inductor ripple current, ΔIL, decreases with
higher inductance and increases with higher VIN or
VOUT
.
IL=VOUT
fO•L 1– VOUT
VIN
Accepting larger values of ΔIL allows the use of low induc-
tances, but results in higher output voltage ripple, greater
core losses and lower output current capability.
A reasonable starting point for setting ripple current is
Δ
IL =
0.35ILOAD(MAX), where ILOAD(MAX) is the maximum current
output. The largest ripple,
Δ
IL, occurs at the maximum
input voltage. To guarantee that the ripple current stays
below a specifi ed maximum, the inductor value should
be chosen according to the following equation:
L=VOUT
fO•IL
1– VOUT
VIN(MAX)
The inductor value will also have an effect on Burst Mode
operation. The transition from low current operation begins
when the peak inductor current falls below a level set by the
burst clamp. Lower inductor values result in higher ripple
current which causes this to occur at lower load currents.
This causes a dip in effi ciency in the upper range of low
current operation. In Burst Mode operation, lower inductor
values will cause the burst frequency to increase.
FREQUENCY (MHz)
0
RT (kΩ)
60
80
100
1.5 2.5 3.53.0 4.0
3417 F01
40
20
00.5 1.0 2.0
120
140
160
4.5
LTC3417
10
3417fd
APPLICATIONS INFORMATION
Inductor Core Selection
Different core materials and shapes will change the size/cur-
rent relationship of an inductor. Toroid or shielded pot cores
in ferrite or permalloy materials are small and don’t radiate
much energy, but generally cost more than powdered iron
core inductors with similar electrical characteristics. The
choice of which style inductor to use often depends more
on the price vs size requirements of any radiated fi eld/EMI
requirements than on what the LTC3417 requires to oper-
ate. Table 1 shows some typical surface mount inductors
that work well in LTC3417 applications.
Input Capacitor (CIN) Selection
In continuous mode, the input current of the converter can
be approximated by the sum of two square waves with
duty cycles of approximately VOUT1/VIN and VOUT2/VIN. To
prevent large voltage transients, a low equivalent series
resistance (ESR) input capacitor sized for the maximum
RMS current must be used. Some capacitors have a
de-rating spec for maximum RMS current. If the capaci-
tor being used has this requirement, it is necessary to
calculate the maximum RMS current. The RMS current
calculation is different if the part is used in “in phase” or
“out of phase”.
For “in phase”, there are two different equations:
VOUT1 > VOUT2:
I
RMS
=2•I
1
•I
2
•D2(1–D1)+I
22
(D2 – D2
2
)+I
12
(D1– D1
2
)
VOUT2 > VOUT1:
I
RMS
=2•I
1
•I
2
•D1(1–D2)+I
22
(D2 – D2
2
)+I
12
(D1– D1
2
)
where:
D1=VOUT1
VIN
and D2 =VOUT2
VIN
Table 1
MANUFACTURER PART NUMBER VALUE (μH) MAX DC CURRENT (A) DCR DIMENSIONS L × W × H (mm)
L1 on OUT1
Toko A920CY-1R5M-D62CB 1.5 2.8 0.014 6 × 6 × 2.5
A918CY-1R5M-D62LCB 1.5 2.9 0.018 6 × 6 × 2
Coilcraft DO1608C-152ML 1.5 2.6 0.06 6.6 × 4.5 × 2.9
Sumida CDRH4D22/HP 1R5 1.5 3.9 0.031 5 × 5 × 2.4
CDRH2D18/HP 1R7 1.7 1.8 0.035 3.2 × 3.2 × 2
Midcom DUP-1813-1R4R 1.4 5.5 0.033 4.3 × 4.8 × 3.5
L2 on OUT2
Toko A915AY-2R0M-D53LC 2.0 3.9 0.027 5 × 5 × 3
Coilcraft DO1608C-222ML 2.2 2.3 0.07 6.6 × 4.5 × 2.9
Sumida CDRH3D16/HP 2R2 2.2 1.75 0.047 4 × 4 × 1.8
CDRH2D18/HP 2R2 2.2 1.6 0.035 3.2 × 3.2 × 2
Midcom DUP-1813-2R2R 2.2 3.9 0.047 4.3 × 4.8 × 3.5
LTC3417
11
3417fd
APPLICATIONS INFORMATION
When D1 = D2 then the equation simplifi es to:
IRMS =I1+I2
()
D1–D
( )
or
IRMS =I1+I2
()
VOUT VIN –V
OUT
( )
VIN
where the maximum average output currents I1 and I2
equal the respective peak currents minus half the peak-
to-peak ripple currents:
I1=ILIM1 –IL1
2
I2=ILIM2 –IL2
2
These formula have a maximum at VIN = 2VOUT
, where
IRMS = (I1 + I2)/2. This simple worst case is commonly
used to determine the highest IRMS.
For “out of phase” operation, the ripple current can be
lower than the “in phase” current.
In the “out of phase” case, the maximum IRMS does not
occur when VOUT1 = VOUT2. The maximum typically oc-
curs when VOUT1 – VIN/2 = VOUT2 or when VOUT2 – VIN/2
= VOUT1. As a good rule of thumb, the amount of worst
case ripple is about 75% of the worst case ripple in the
“in phase” mode. Also note that when VOUT1 = VOUT2 =
VIN/2 and I1 = I2, the ripple is zero.
Note that capacitor manufacturer’s ripple current ratings
are often based on only 2000 hours lifetime. This makes
it advisable to further derate the capacitor, or choose a
capacitor rated at a higher temperature than required.
Several capacitors may also be paralleled to meet the
size or height requirements of the design. An additional
0.1µF to 1µF ceramic capacitor is also recommended on
VIN for high frequency decoupling, when not using an all
ceramic capacitor solution.
Output Capacitor (COUT1 and COUT2) Selection
The selection of COUT1 and COUT2 is driven by the required
ESR to minimize voltage ripple and load step transients.
Typically, once the ESR requirement is satisfi ed, the
capacitance is adequate for fi ltering. The output ripple
(ΔVOUT) is determined by:
where fO = operating frequency, COUT = output capacitance
and ΔIL = ripple current in the inductor. The output ripple
is highest at maximum input voltage, since ΔIL increases
with input voltage. With ΔIL = 0.35ILOAD(MAX), the output
ripple will be less than 100mV at maximum VIN and fO =
1MHz with:
ESRCOUT < 150m
Once the ESR requirements for COUT have been met, the
RMS current rating generally far exceeds the IRIPPLE(P-P)
requirement, except for an all ceramic solution.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the capacitance, ESR or RMS
current handling requirement of the application. Aluminum
electrolytic, special polymer, ceramic and dry tantalum
capacitors are all available in surface mount packages.
The OS-CON semiconductor dielectric capacitor avail-
able from Sanyo has the lowest ESR(size) product of any
aluminum electrolytic at a somewhat higher price. Special
polymer capacitors, such as Sanyo POSCAP, offer very
low ESR, but have a lower capacitance density than other
types. Tantalum capacitors have the highest capacitance
density, but it has a larger ESR and it is critical that the
capacitors are surge tested for use in switching power
supplies. An excellent choice is the AVX TPS series of
surface tantalums, available in case heights ranging from
2mm to 4mm. Aluminum electrolytic capacitors have a
signifi cantly larger ESR, and are often used in extremely
cost-sensitive applications provided that consideration
LTC3417
12
3417fd
APPLICATIONS INFORMATION
is given to ripple current ratings and long term reliability.
Ceramic capacitors have the lowest ESR and cost but also
have the lowest capacitance density, high voltage and
temperature coeffi cient and exhibit audible piezoelectric
effects. In addition, the high Q of ceramic capacitors along
with trace inductance can lead to signifi cant ringing. Other
capacitor types include the Panasonic specialty polymer
(SP) capacitors.
In most cases, 0.1µF to 1µF of ceramic capacitors should
also be placed close to the LTC3417 in parallel with the
main capacitors for high frequency decoupling.
Ceramic Input and Output Capacitors
Higher value, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Because the
LTC3417 control loop does not depend on the output
capacitor’s ESR for stable operation, ceramic capacitors
can be used freely to achieve very low output ripple and
small circuit size. When choosing the input and output
ceramic capacitors, choose the X5R or X7R dielectric
formulations. These dielectrics have the best temperature
and voltage characteristics of all the ceramics for a given
value and size.
Great care must be taken when using only ceramic input
and output capacitors. When a ceramic capacitor is used
at the input and the power is being supplied through long
wires, such as from a wall adapter, a load step at the output
can induce ringing at the VIN pin. At best, this ringing can
couple to the output and be mistaken as loop instability.
At worst, the ringing at the input can be large enough to
damage the part.
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must fulfi ll a charge storage re-
quirement. During a load step, the output capacitor must
instantaneously supply the current to support the load
until the feedback loop raises the switch current enough
to support the load. The time required for the feedback
loop to respond is dependent on the compensation com-
ponents and the output capacitor size. Typically, 3 to 4
cycles are required to respond to a load step, but only in
the fi rst cycle does the output drop linearly. The output
droop, VDROOP
, is usually about 2 to 3 times the linear
droop of the fi rst cycle. Thus, a good place to start is with
the output capacitor size of approximately:
COUT 2.5 IOUT
fO•V
DROOP
More capacitance may be required depending on the duty
cycle and load step requirements.
In most applications, the input capacitor is merely required
to supply high frequency bypassing, since the impedance
to the supply is very low. A 10µF ceramic capacitor is
usually enough for these conditions.
Setting the Output Voltage
The LTC3417 develops a 0.8V reference voltage between
the feedback pins, VFB1 and VFB2, and the signal ground
as shown in Figure 4. The output voltages are set by two
resistive dividers according to the following formulas:
VOUT1 0.8V 1+R1
R2
VOUT2 0.8V 1+R3
R4
Keeping the current small (<5µA) in these resistors
maximizes effi ciency, but making the current too small
may allow stray capacitance to cause noise problems and
reduce the phase margin of the error amp loop.
To improve the frequency response, a feed-forward ca-
pacitor, CF, may also be used. Great care should be taken
to route the VFB node away from noise sources, such as
the inductor or the SW line.
LTC3417
13
3417fd
APPLICATIONS INFORMATION
Figure 2. Digital Soft-Start Out1
Soft-Start
Soft-start reduces surge currents from VIN by gradu-
ally increasing the peak inductor current. Power supply
sequencing can also be accomplished by controlling the
ITH pin. The LTC3417 has an internal digital soft-start for
each regulator output, which steps up a clamp on ITH over
1024 clock cycles, as can be seen in Figures 2 and 3. As
the voltage on ITH ramps through its operating range, the
internal peak current limit is also ramped at a proportional
linear rate.
Mode Selection
The MODE pin provides mode selection. Connecting this pin
to VIN enables Burst Mode operation for both regulators,
which provides the best low current effi ciency at the cost
of a higher output voltage ripple. When MODE is connected
to ground, pulse skipping operation is selected for both
regulators, which provides the lowest output voltage and
current ripple at the cost of low current effi ciency. Applying
a voltage that is more than 1V from either supply results
in forced continuous mode for both regulators, which
creates a fi xed output ripple and allows the sinking of
some current (about 1/2ΔIL). Since the switching noise is
constant in this mode, it is also the easiest to fi lter out. In
many cases, the output voltage can be simply connected
to the MODE pin, selecting the forced continuous mode
except at start-up.
Figure 3. Digital Soft-Start Out2
VIN = 3.6V
VOUT = 1.8V
RL = 0.9Ω
200µs/DIV
IL
1A/DIV
VOUT
1V/DIV
VRUN
2V/DIV
VIN = 3.6V
VOUT = 2.5V
RL = 2Ω
200µs/DIV
IL
0.5A/DIV
VOUT
1V/DIV
VRUN
2V/DIV
Checking Transient Response
The ITH pin compensation allows the transient response
to be optimized for a wide range of loads and output
capacitors. The availability of the ITH pin not only allows
optimization of the control loop behavior, but also pro-
vides a DC coupled and AC fi ltered closed-loop response
test point. The DC step, rise time, and settling at this test
point truly refl ects the closed-loop response. Assuming a
predominantly second order system, phase margin and/or
damping factor can be estimated using the percentage of
overshoot seen at this pin. The bandwidth can also be
estimated using the percentage of overshoot seen at this
pin or by examining the rise time at this pin.
The ITH external components shown in the Figure 4 circuit
will provide an adequate starting point for most applica-
tions. The series RC fi lter sets the dominant pole-zero
loop compensation. The values can be modifi ed slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the fi nal PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because of various types and values determine the loop
feedback factor gain and phase. An output current pulse
of 20% to 100% of full load current having a rise time
of 1µs to 10µs will produce output voltage and ITH pin
waveforms that will give a sense of overall loop stability
without breaking the feedback loop.
LTC3417
14
3417fd
APPLICATIONS INFORMATION
Switching regulators take several cycles to respond to a
step in load current. When a load step occurs, VOUT im-
mediately shifts by an amount equal to ΔILOAD • ESRCOUT,
where ESRCOUT is the effective series resistance of COUT.
ΔILOAD also begins to charge or discharge COUT generat-
ing a feedback error signal used by the regulator to return
VOUT to its steady-state value. During this recovery time,
VOUT can be monitored for overshoot or ringing that would
indicate a stability problem.
The initial output voltage step may not be within the band-
width of the feedback loop, so the standard second order
overshoot/DC ratio cannot be used to determine phase
margin. The gain of the loop increases with RITH and the
bandwidth of the loop increases with decreasing CITH. If
RITH is increased by the same factor that CITH is decreased,
the zero frequency will be kept the same, thereby keeping
the phase the same in the most critical frequency range
of the feedback loop. In addition, feedforward capacitors,
C1 and C2, can be added to improve the high frequency
response, as shown in Figure 4. Capacitor C1 provides
phase lead by creating a high frequency zero with R1
which improves the phase margin for the 1.4A SW1 chan-
nel. Capacitor C2 provides phase lead by creating a high
frequency zero with R3 which improves the phase margin
for the 800mA SW2 channel.
The output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a
review of control loop theory, refer to Linear Technology
Application Note 76.
Although a buck regulator is capable of providing the full
output current in dropout, it should be noted that as the
input voltage VIN drops toward VOUT
, the load step capability
does decrease due to the decreasing voltage across the
inductor. Applications that require large load step capabil-
ity near dropout should use a different topology such as
SEPIC, Zeta, or single inductor, positive buck boost.
In some applications, a more severe transient can be
caused by switching in loads with large (>1µF) input ca-
pacitors. The discharged input capacitors are effectively
put in parallel with COUT, causing a rapid drop in VOUT. No
regulator can deliver enough current to prevent this prob-
lem, if the switch connecting the load has low resistance
and is driven quickly. The solution is to limit the turn-on
speed of the load switch driver. A Hot Swap™ controller
is designed specifi cally for this purpose and usually in-
corporates current limiting, short-circuit protection, and
soft- starting.
Effi ciency Considerations
The percent effi ciency of a switching regulator is equal to
the output power divided by the input power times 100.
It is often useful to analyze individual losses to determine
what is limiting the effi ciency and which change would
produce the most improvement. Percent effi ciency can
be expressed as:
% Effi ciency = 100% – (P1+ P2 + P3 +…)
where P1, P2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four main sources account for most of the losses
in LTC3417 circuits: 1) LTC3417 IS current, 2) switching
losses, 3) I2R losses, 4) other losses.
1) The IS current is the DC supply current given in the elec-
trical characteristics which excludes MOSFET driver and
control currents. IS current results in a small (<0.1%)
loss that increases with VIN, even at no load.
2) The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current re-
sults from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge moves from
VIN to ground. The resulting charge over the switching
period is a current out of VIN that is typically much larger
than the DC bias current. The gate charge losses are
proportional to VIN and thus their effects will be more
pronounced at higher supply voltages.
HotSwap is a trademark of Linear Technology Corporation..
LTC3417
15
3417fd
APPLICATIONS INFORMATION
3) I2R losses are calculated from the DC resistances of the
internal switches, RSW
, and the external inductor, RL. In
continuous mode, the average output current fl owing
through inductor L is “chopped” between the internal
top and bottom switches. Thus, the series resistance
looking into the SW pin is a function of both top and
bottom MOSFET RDS(ON) and the duty cycle (DC) as
follows:
R
SW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)
The RDS(ON) for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus, to obtain I2R losses:
I
2R losses = IOUT2(RSW + RL)
where RL is the resistance of the inductor.
4) Other “hidden” losses such as copper trace and internal
battery resistances can account for additional effi ciency
degradations in portable systems. It is very important
to include these “system” level losses in the design of a
system. The internal battery and fuse resistance losses
can be minimized by making sure that CIN has adequate
charge storage and very low ESRCOUT at the switching
frequency. Other losses including diode conduction
losses during dead-time and inductor core losses gener-
ally account for less than 2% total additional loss.
Thermal Considerations
The LTC3417 requires the package Exposed Pad (PGND2/
GNDD pin) to be well soldered to the PC board. This gives
the DFN and TSSOP packages exceptional thermal proper-
ties, compared to similar packages of this size, making it
diffi cult in normal operation to exceed the maximum junc-
tion temperature of the part. In a majority of applications,
the LTC3417 does not dissipate much heat due to its high
effi ciency. However, in applications where the LTC3417 is
running at high ambient temperature with low supply volt-
age and high duty cycles, such as in dropout, the heat dis-
sipated may exceed the maximum junction temperature of
the part. If the junction temperature reaches approximately
150°C, both switches in both regulators will be turned off
and the SW nodes will become high impedance.
To prevent the LTC3417 from exceeding its maximum junc-
tion temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:
T
RISE = PD • θJA
where PD is the power dissipated by the regulator and θJA
is the thermal resistance from the junction of the die to
the ambient temperature.
The junction temperature, TJ, is given by:
T
J = TRISE + TAMBIENT
As an example, consider the case when the LTC3417 is
in dropout in both regulators at an input voltage of 3.3V
with load currents of 1.4A and 800mA. From the Typical
Performance Characteristics graph of Switch Resistance,
the RDS(ON) resistance of the 1.4A P-channel switch is
0.09 and the RDS(ON) of the 800mA P-channel switch
is 0.163. The power dissipated by the part is:
PD = I12 • RDS(ON)1 + I22 • RDS(ON)2
PD = 1.42 • 0.09 + 0.82 • 0.163
PD = 281mW
The DFN package junction-to-ambient thermal resistance,
θJA, is about 43°C/W. Therefore, the junction temperature
of the regulator operating in a 70°C ambient temperature
is approximately:
T
J = 0.281 • 43 + 70
T
J = 82.1°C
Remembering that the above junction temperature is
obtained from an RDS(ON) at 25°C, we might recalculate
the junction temperature based on a higher RDS(ON) since
it increases with temperature. However, we can safely as-
sume that the actual junction temperature will not exceed
the absolute maximum junction temperature of 125°C.
LTC3417
16
3417fd
APPLICATIONS INFORMATION
Design Example
As a design example, consider using the LTC3417 in a
portable application with a Li-Ion battery. The battery
provides a VIN from 2.5V to 4.2V. One output requires
1.8V at 1.3A in active mode, and 1mA in standby mode.
The other output requires 2.5V at 700mA in active mode,
and 500µA in standby mode. Since both loads still need
power in standby, Burst Mode operation is selected for
good low load effi ciency (MODE = VIN).
First, determine what frequency should be used. Higher
frequency results in a lower inductor value for a given ΔIL
(ΔIL is estimated as 0.35ILOAD(MAX)). Reasonable values
for wire wound surface mount inductors are usually in the
range of 1µH to 10µH.
CONVERTER OUTPUT ILOAD(MAX) ΔIL
SW1 1.4A 490mA
SW2 800mA 280mA
Using the 1.5MHz frequency setting (FREQ = VIN), we get
the following equations for L1 and L2:
L1=1.8V
1.5MHz • 490mA 1– 1.8V
4.2V
=1.4μH
Use 1.5μH.
L2=2.5V
1.5MHz • 280mA1– 2.5V
4.2V
=2.4μH
Use 2.2μH.
COUT selection is based on load step droop instead of ESR
requirements. For a 5% output droop:
COUT1 =2.5 • 1.3A
1.5MHz 5% • 1.8V
( )
=24μF
COUT2 =2.5 • 0.7A
1.5MHz 5% • 2.5V
( )
=9.3μF
The closest standard values are 22µF and 10µF.
The output voltages can now be programmed by choos-
ing the values of R1, R2, R3, and R4. To maintain high
effi ciency, the current in these resistors should be kept
small. Choosing 2µA with the 0.8V feedback voltages makes
R2 and R4 equal to 400k. A close standard 1% resistor is
412k. This then makes R1 = 515k. A close standard 1%
is 511k. Similarily, with R4 at 412k, R3 is equal to 875k.
A close 1% resistor is 866k.
The compensation should be optimized for these compo-
nents by examining the load step response, but a good
place to start for the LTC3417 is with a 5.9k and 2200pF
fi lter on ITH1 and 2.87k and 6800pF on ITH2. The output
capacitor may need to be increased depending on the
actual undershoot during a load step.
The PGOOD pin is a common drain output and requires a
pull-up resistor. A 100k resistor is used for adequate speed.
Figure 4 shows a complete schematic for this design.
LTC3417
17
3417fd
APPLICATIONS INFORMATION
OUT1 Effi ciency vs Load Current
Figure 4. 1.8V at 1.4A/2.5V at 800mA Step-Down Regulators
MODE
SW1
RUN1
VFB1
PHASE
ITH1
PGOOD
SW2
RUN2
VFB2
FREQ
ITH2
VIN1
LTC3417
GNDA
EXPOSED
PAD GNDD
VIN2
CIN
10µF
CIN1
0.1µF
CIN2
0.1µF
L1
1.5µH
L2
2.2µH
C1 22pF
R1 511k
C2 22pF
R3 866k
VIN VIN
VIN
R7
100k
R2
412k
R4
412k
COUT2
10µF
R5
5.9k
R6
2.87k
C3
2200pF
C4
6800pF
3417 F04
COUT1
22µF
VOUT1
1.8V
1.4A
VOUT2
2.5V
800mA
VIN
2.25V TO 5.5V
L1: MIDCOM DUS-5121-1R5R
COUT1: KEMET C1210C226K8PAC
L2: MIDCOM DUS-5121-2R2R
COUT2, CIN: KEMET C1206C106K4PAC
LOAD CURRENT (A)
80
EFFICIENCY (%)
POWER LOSS (W)
90
100
75
85
95
0.001 0.1 1 10
3417 F04a
70
0.1
10
0.01
1
0.001
0.01
VIN = 3.6V
VOUT = 1.8V
FREQ = 1MHz
REFER TO FIGURE 4
EFFICIENCY
POWER LOSS
LTC3417
18
3417fd
APPLICATIONS INFORMATION
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3417. These items are also illustrated graphically
in the layout diagram of Figure 5. Check the following in
your layout.
1
. Does the capacitor CIN connect to the power VIN1
(Pin 2), VIN2 (Pin 8), and PGND2/GNDD (Pin 17) as
close as possible (DFN package)? It may be necessary
to split CIN into two capacitors. This capacitor provides
the AC current to the internal power MOSFETs and
their drivers.
2. Are the COUT1, L1 and COUT2, L2 closely connected? The
(–) plate of COUT1 returns current to PGND1, and the
(–) plate of COUT2 returns current to the
PGND2/GNDD
and the (–) plate of CIN.
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of COUT1 and a ground line ter-
minated near GNDA. The resistor divider, R3 and R4,
must be connected between the (+) plate of COUT2 and
a ground line terminated near GNDA. The feedback
signals VFB1 and VFB2 should be routed away from noise
components and traces, such as the SW lines, and its
trace should be minimized.
4. Keep sensitive components away from the SW pins.
The input capacitor CIN, the compensation capacitors
CC1, CC2, CITH1 and CITH2 and all resistors R1, R2, R3,
R4, RITH1 and RITH2 should be routed away from the
SW traces and the inductors L1 and L2.
5. A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small
signal components returning to the GNDA pin at one
point which is then connected to the
PGND2/GNDD
pin.
6. Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. These copper areas should be connected
to one of the input supplies.
Figure 5
VIN2
PGND2/
EXPOSED PAD
VIN1
PGND1
SW1
VFB1
ITH1
FREQ
RUN1
MODE
LTC3417
GNDD
VIN
VIN
VIN
CIN
10µF
CIN2
0.1µF
CIN1
0.1µF
COUT2
VOUT2
COUT1
VOUT1
L2 L1
CC2 CC1
R3
R4
RITH2
CITH2 CITH1
R8
R1
R2
RITH1
R7
STAR TO
GNDA
STAR TO
GNDA
GNDA
SW2
VFB2
ITH2
PGOOD
RUN2
PHASE
LTC3417
19
3417fd
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
DHC Package
16-Lead Plastic DFN (5mm × 3mm)
(Reference LTC DWG # 05-08-1706)
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation CA
3.00 ±0.10
(2 SIDES)
5.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ± 0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
R = 0.20
TYP
4.40 ±0.10
(2 SIDES)
18
169
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DHC16) DFN 1103
0.25 ± 0.05
PIN 1
NOTCH
0.50 BSC
4.40 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)2.20 ±0.05
0.50 BSC
0.65 ±0.05
3.50 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
FE20 (CA) TSSOP 0204
0.09 – 0.20
(.0035 – .0079)
0° – 8°
0.25
REF
RECOMMENDED SOLDER PAD LAYOUT
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
134
5678910
111214 13
6.40 – 6.60*
(.252 – .260)
4.95
(.195)
2.74
(.108)
20 1918 17 16 15
1.20
(.047)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC 0.195 – 0.30
(.0077 – .0118)
TYP
2
2.74
(.108)
0.45 ±0.05
0.65 BSC
4.50 ±0.10
6.60 ±0.10
1.05 ±0.10
4.95
(.195)
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
LTC3417
20
3417fd
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2008
LT 0708 REV D • PRINTED IN USA
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