August 2006 Rev 7 1/15
15
STD110NH02L
N-channel 24V - 0.0044Ω - 80A - DPAK
STripFET™ III Power MOSFET
General features
■RDS(on) * Qg industry’s benchmark
■Conduction losses reduced
■Switching losses reduced
■Low threshold device
Description
This device utilizes the latest advanced design
rules of ST’s proprietary STripFET™ technology.
This is suitable fot the most demanding DC-DC
converter application where high efficiency is to
be achieved.
Applications
■Switching application
Internal schematic diagram
Type VDSSS RDS(on) ID
STD110NH02L 24V <0.0048Ω80A(1)
1. Value limited by wire bonding 1
3
DPAK
www.st.com
Order codes
Part number Marking Package Packaging
STD110NH02LT4 D110NH02L DPAK Tape & reel
Contents STD110NH02L
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Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
STD110NH02L Electrical ratings
3/15
1 Electrical ratings
Table 1. Absolute maximum ratings
Symbol Parameter Value Unit
Vspike (1)
1. Garanted when external Rg = 4.7 Ω and tf < tfmax.
Drain-source voltage rating 30 V
VDS Drain-source voltage (VGS = 0) 24 V
VDGR Drain-gate voltage (RGS = 20KΩ)24V
VGS Drain-source voltage ± 20 V
ID (2)
2. Value limited by wire bonding.
Drain current (continuous) at TC = 25°C 80 A
ID (2) Drain current (continuous) at TC=100°C 80 A
IDM (3)
3. Pulse width limited by safe operating area
Drain current (pulsed) 320 A
PTOT Total dissipation at TC = 25°C 125 W
Derating factor 0.83 W/°C
EAS (4)
4. Starting TJ = 25 oC, ID = 30A, VDD = 15V
Single pulse avalanche energy 900 mJ
Tstg Storage temperature -55 to 175 °C
TJMax. operating junction temperature
Table 2. Thermal data
Symbol Parameter Value Unit
RthJC Thermal resistance junction-case Max 1.20 °C/W
RthJA Thermal resistance junction-ambient Max 100 °C/W
Tl
Maximum lead temperature for soldering
purpose 275 °C
Electrical characteristics STD110NH02L
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2 Electrical characteristics
(TCASE=25°C unless otherwise specified)
Table 3. On(1) /off states
1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5%
Symbol Parameter Test conditions Min. Typ. Max. Unit
V(BR)DSS Drain-source breakdown
voltage ID = 25mA, VGS = 0 24 V
IDSS
Zero gate voltage drain
current (VGS = 0)
VDS = 20
VDS = 20, TC = 125°C
1
10
µA
µA
IGSS
Gate body leakage current
(VDS = 0) VGS = ±20V ±100 nA
VGS(th) Gate threshold voltage VDS= VGS, ID = 250µA 1V
RDS(on) Static drain-source on
resistance
VGS = 10V, ID = 40A
VGS = 5V, ID = 20A
0.0044
0.0050
0.0050
0.0095
Ω
Ω
Table 4. Dynamic
Symbol Parameter Test conditions Min. Typ. Max. Unit
gfs (1)
1. Pulsed: pulse duration=300µs, duty cycle 1.5%
Forward transconductance VDS = 10 V, ID = 40A 52 S
Ciss
Coss
Crss
Input capacitance
Output capacitance
Reverse transfer
capacitance
VDS = 15V, f = 1 MHz,
VGS = 0
4450
1126
141
pF
pF
pF
Qg
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain charge
VDD = 10V, ID = 80A
VGS = 10V
69
13
9
93 nC
nC
nC
Qoss(2)
2. Qoss = Coss*∆ Vin , Coss = Cgd + Cds . See Section Appendix A
Output charge VDS = 16V, VGS = 0V 27 nC
Qgls(3)
3. Gate charge for synchronous operation
Third-quadrant gate charge VDS < 0V, VGS = 10V 64 nC
RGGate input resistance
f = 1MHz gate DC Bias = 0
Test signal level = 20mV
Open drain
16 Ω
STD110NH02L Electrical characteristics
5/15
Table 5. Switching times
Symbol Parameter Test conditions Min. Typ. Max. Unit
td(on)
tr
td(off)
tf
Turn-on delay time
Rise time
Turn-off delay time
Fall time
VDD = 10V, ID = 40A,
RG = 4.7Ω, VGS = 10V
Figure 13 on page 8
14
224
69
40 54
ns
ns
ns
ns
Table 6. Source drain diode
Symbol Parameter Test conditions Min Typ. Max Unit
ISD Source-drain current 80 A
ISDM Source-drain current (pulsed) 320 A
VSD(1)
1. Pulsed: pulse duration=300µs, duty cycle 1.5%
Forward on voltage ISD = 40A, VGS = 0 1.3 V
trr
Qrr
IRRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 80A,
di/dt = 100A/µs,
VDD = 15V, TJ = 150°C
Figure 15 on page 8
47
58
2.5
ns
µC
A
Electrical characteristics STD110NH02L
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2.1 Electrical characteristics (curves)
Figure 1. Safe operating area Figure 2. Thermal impedance
Figure 3. Output characterisics Figure 4. Transfer characteristics
Figure 5. Transconductance Figure 6. Static drain-source on resistance
STD110NH02L Electrical characteristics
7/15
Figure 7. Gate charge vs gate-source voltage Figure 8. Capacitance variations
Figure 9. Normalized gate threshold voltage
vs temperature
Figure 10. Normalized on resistance vs
temperature
Figure 11. Source-drain diode forward
characteristics
Figure 12. Normalized breakdown voltage vs
temperature
Test circuit STD110NH02L
8/15
3 Test circuit
Figure 13. Switching times test circuit for
resistive load
Figure 14. Gate charge test circuit
Figure 15. Test circuit for inductive load
switching and diode recovery times
Figure 16. Unclamped Inductive load test
circuit
Figure 17. Unclamped inductive waveform
STD110NH02L Package mechanical data
9/15
4 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
Package mechanical data STD110NH02L
10/15
DIM.
mm. inch
MIN. TYP MAX. MIN. TYP. MAX.
A 2.2 2.4 0.086 0.094
A1 0.9 1.1 0.035 0.043
A2 0.03 0.23 0.001 0.009
B 0.64 0.9 0.025 0.035
b4 5.2 5.4 0.204 0.212
C 0.45 0.6 0.017 0.023
C2 0.48 0.6 0.019 0.023
D 6 6.2 0.236 0.244
D1 5.1 0.200
E 6.4 6.6 0.252 0.260
E1 4.7 0.185
e 2.28 0.090
e1 4.4 4.6 0.173 0.181
H 9.35 10.1 0.368 0.397
L 1 0.039
(L1) 2.8 0.110
L2 0.8 0.031
L4 0.6 1 0.023 0.039
R 0.2 0.008
V2 0° 8° 0° 8°
DPAK MECHANICAL DATA
0068772-F
STD110NH02L Packaging mechanical data
11/15
5 Packaging mechanical data
TAPE AND REEL SHIPMENT
DPAK FOOTPRINT
DIM. mm inch
MIN. MAX. MIN. MAX.
A 330 12.992
B1.5 0.059
C 12.8 13.2 0.504 0.520
D20.2 0.795
G 16.4 18.4 0.645 0.724
N50 1.968
T 22.4 0.881
BASE QTY BULK QTY
2500 2500
REEL MECHANICAL DATA
DIM. mm inch
MIN. MAX. MIN. MAX.
A0 6.8 7 0.267 0.275
B0 10.4 10.6 0.409 0.417
B1 12.1 0.476
D1.5 1.6 0.059 0.063
D1 1.5 0.059
E1.65 1.85 0.065 0.073
F 7.4 7.6 0.291 0.299
K0 2.55 2.75 0.100 0.108
P0 3.9 4.1 0.153 0.161
P1 7.9 8.1 0.311 0.319
P2 1.9 2.1 0.075 0.082
R40 1.574
W 15.7 16.3 0.618 0.641
TAPE MECHANICAL DATA
All dimensions are in millimeters
Buck converter - power losses estimation STD110NH02L
12/15
Appendix A Buck converter - power losses estimation
The power losses associated with the FETs in a synchronous buck converter can be
estimated using the equations shown in the table below. The formulas give a good
approximation, for the sake of performance comparison, of how different pairs of devices
affect the converter efficiency. However a very important parameter, the working
temperature, is not considered. The real device behavior is really dependent on how the
heat generated inside the devices is removed to allow for a safer working junction
temperature.
●The low side (SW2) device requires:
●Very low RDS(on) to reduce conduction losses
●Small Qgls to reduce the gate charge losses
●Small Coss to reduce losses due to output capacitance
●Small Qrr to reduce losses on SW1 during its turn-on
●The Cgd/Cgs ratio lower than Vth/Vgg ratio especially with low drain to source
●voltage to avoid the cross conduction phenomenon;
●The high side (SW1) device requires:
●Small Rg and Ls to allow higher gate current peak and to limit the voltage feedback on
the gate
●Small Qg to have a faster commutation and to reduce gate charge losses
●Low RDS(on) to reduce the conduction losses.
Figure 18. Buck converter: power losses estimation
STD110NH02L Buck converter - power losses estimation
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Table 7. Power losses calculation
High side switching (SW1) Low side switch (SW2)
Pconduction
Pswitching Zero Voltage Switching
Pdiode
Recovery
(1)
1. Dissipated by SW1 during turn-on
Not applicable
Conductio
nNot applicable
Pgate(QG)
PQoss
Table 8. Paramiters meaning
Parameter Meaning
d Duty-cycle
Qgsth Post threshold gate charge
Qgls Third quadrant gate charge
Pconduction On state losses
Pswitching On-off transition losses
Pdiode Conduction and reverse recovery diode losses
Pgate Gate drive losses
PQoss Output capacitance losses
δ
*I *R 2
LDS(on)SW1 )1(*I *R 2
LDS(on)SW2
δ
−
g
L
I
I
*f*)Q(Q*
V
gd(SW1)gsth(SW1)in +
f*Q*V rr(SW2)in
f*t*I*V deadtimeLf(SW2)
f*V*Q ggg(SW1) f*V*Q gggls(SW2)
2
f*Q*V oss(SW1)in
2
f*Q*V oss(SW2)in
Revision history STD110NH02L
14/15
6 Revision history
Table 9. Revision history
Date Revision Changes
09-Sep-2004 6 Complete version
08-Aug-2006 7 New template, updated SOA
STD110NH02L
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