M7A3P600-2FGG484 - Microsemi Corp.

May 2007 i

ProASIC®3 Flash Family FPGAs

with Optional Soft ARM® Support

Features and Benefits

High Capacity

• 30 k to 1 Million System Gates

• Up to 144 kbits of True Dual-Port SRAM

• Up to 300 User I/Os

Reprogrammable Flash Technology

• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS

Process

• Live at Power-Up (LAPU) Level 0 Support

• Single-Chip Solution

• Retains Programmed Design when Powered Off

On-Chip User Nonvolatile Memory

• 1 kbit of FlashROM with Synchronous Interfacing

High Performance

• 350 MHz System Performance

• 3.3 V, 66 MHz 64-Bit PCI (except A3P030)

In-System Programming (ISP) and Security

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

Standard (AES) Decryption (except A3P030 and ARM®-

enabled ProASIC®3 devices) via JTAG (IEEE 1532–

compliant)

•FlashLock

® to Secure FPGA Contents

Low Power

• Core Voltage for Low Power

• Support for 1.5-V-Only Systems

• Low-Impedance Flash Switches

High-Performance Routing Hierarchy

• Segmented, Hierarchical Routing and Clock Structure

• Ultra-Fast Local and Long-Line Network

• Enhanced High-Speed, Very-Long-Line Network

• High-Performance, Low-Skew Global Network

• Architecture Supports Ultra-High Utilization

Advanced I/O

• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)

• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—Up to 4 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

2.5V/1.8V/1.5V,3.3VPCI/3.3VPCI-X(except

A3P030), and LVCMOS 2.5 V / 5.0 V Input

• Differential I/O Standards: LVPECL, LVDS, BLVDS, and

M-LVDS (A3P250 and above)

• I/O Registers on Input, Output, and Enable Paths

• Hot-Swappable and Cold Sparing I/Os (A3P030 only)

• Programmable Output Slew Rate (except A3P030) and

Drive Strength

• Weak Pull-Up/Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages Across the ProASIC3 Family

Clock Conditioning Circuit (CCC) and PLL (except A3P030)

• Six CCC Blocks, One with an Integrated PLL

• Configurable Phase-Shift, Multiply/Divide, Delay

Capabilities and External Feedback, Multiply/Divide,

Delay Capabilities, and External Feedback

• Wide Input Frequency Range (1.5 MHz to 350 MHz)

• CoreMP7Sd (with debug) and CoreMP7S (without debug

SRAMs and FIFOs (except A3P030)

• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2,

×4, ×9, and ×18 Organizations Available)

• True Dual-Port SRAM (except ×18)

• 24 SRAM and FIFO Configurations with Synchronous

Operation up to 350 MHz

Soft ARM7™ Core Support in M7 ProASIC3 Devices

• CoreMP7Sd (with debug) and CoreMP7S (without

debug)

Table 1 • ProASIC3 Product Family

ProASIC3 Devices A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 A3P1000

ARM®-Enabled

ProASIC3 Devices1M7A3P250 M7A3P400 M7A3P600 M7A3P1000

System Gates 30 k 60 k 125 k 250 k 400 k 600 k 1 M

VersaTiles (D-flip-flops) 768 1,536 3,072 6,144 9,216 13,824 24,576

RAM kbits (1,024 bits) – 18 36 36 54 108 144

4,608-Bit Blocks – 4 8 8 12 24 32

FlashROM Bits 1 k 1 k 1 k 1 k 1 k 1 k 1 k

Secure (AES) ISP2– Yes Yes Yes Yes Yes Yes

Integrated PLL in CCCs –1 1 1 1 1 1

VersaNet Globals361818 18 18 18 18

I/O Banks 22 2 4 4 4 4

Maximum User I/Os 81 96 133 157 194 235 300

Package Pins

QFN

VQFP

TQFP

PQFP

FBGA

QN132

VQ100

QN132

VQ100

TQ144

FG144

QN132

VQ100

TQ144

PQ208

FG144

QN1325

VQ100

PQ208

FG144,

FG2565

PQ208

FG144, FG256,

FG484

PQ208

FG144, FG256,

FG484

PQ208

FG144, FG256,

FG484

Notes:

1. Refer to the CoreMP7 datasheet for more information.

2. AES is not available for ARM-enabled ProASIC3 devices.

3. Six chip (main) and three quadrant global networks are available for A3P060 and above.

4. For higher densities and support of additional features, refer to the ProASIC3E Flash FPGAs datasheet.

5. The M7A3P250 device does not support this package.

v2.1

ProASIC®3 Flash Family FPGAs

ii v2.1

I/Os Per Package1

Packaging Tables

Pinout tables not published in this document will be added in future revisions of the datasheet. For updates, contact

your local Actel sales representative.

ProASIC3

Devices A3P030 A3P060 A3P125 A3P250 3A3P400 3A3P600 A3P1000

ARM-Enabled

ProASIC3

Devices M7A3P250 3, 4 M7A3P400 3M7A3P600 M7A3P1000

Package

I/O Type

Single-Ended I/O

Single-Ended I/O2

Differential I/O Pairs

Single-Ended I/O2

Differential I/O Pairs

Single-Ended I/O2

Differential I/O Pairs

Single-Ended I/O2

Differential I/O Pairs

QN132 81 80 84 87 19 – – – – –

VQ100 7771716813–– –––

TQ144 – 91 100 – – – – – – – –

PQ208 – – 133 151 34 151 34 154 35 154 35

FG144 – 96 97 97 24 97 25 97 25 97 25

FG256 – – – 157 38 178 38 177 43 177 44

FG484 – – – – – 194 38 235 60 300 74

Notes:

1. When considering migrating your design to a lower- or higher-density device, refer to "Package Pin Assignments" starting on page

4-1 to ensure complying with design and board migration requirements.

2. Each used differential I/O pair reduces the number of single-ended I/Os available by two.

3. For A3P250 and A3P400 devices, the maximum number of LVPECL pairs in east and west banks cannot exceed 15. Refer to

"Package Pin Assignments" starting on page 4-1 for position assignments of the 15 LVPECL pairs.

4. The M7A3P250 device does not support FG256 or QN132 packages.

5. FG256 and FG484 are footprint-compatible packages.

6. "G" indicates RoHS-compliant packages. Refer to "ProASIC3 Ordering Information" on page iii for the location of the "G" in the part

number.

ProASIC®3 Flash Family FPGAs

v2.1 iii

ProASIC3 Ordering Information

Note: *The DC and switching characteristics for the –F speed grade targets are based only on simulation.

The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some restrictions

might be added and will be reflected in future revisions of this document. The –F speed grade is only supported in the commercial

temperature range.

Speed Grade

Blank = Standard

1 = 15% Faster than Standard

2 = 25% Faster than Standard

F = 20% Slower than Standard*

A3P1000 FG

Part Number

ProASIC3 Devices

ARM-Enabled ProASIC3 Devices

Package Type

VQ =Very Thin Quad Flat Pack (0.5 mm pitch)

QN =Quad Flat Pack No Leads (0.5 mm pitch)

TQ =Thin Quad Flat Pack (0.5 mm pitch)

144 I

Package Lead Count

Lead-Free Packaging

Application (Temperature Range)

Blank = Commercial (0°C to +70°C)

I = Industrial (–40°C to +85°C)

Blank = Standard Packaging

G= RoHS-Compliant (Green) Packaging

PP = Pre-Production

ES = Engineering Sample (Room Temperature Only)

30,000 System Gates

A3P030 =

60,000 System Gates

A3P060 =

125,000 System Gates

A3P125 =

250,000 System Gates

A3P250 =

400,000 System Gates

A3P400 =

600,000 System Gates

A3P600 =

1,000,000 System Gates

A3P1000 =

250,000 System Gates

M7A3P250 =

400,000 System Gates

M7A3P400 =

600,000 System Gates

M7A3P600 =

1,000,000 System Gates

M7A3P1000 =

PQ =Plastic Quad Flat Pack (0.5 mm pitch)

FG =Fine Pitch Ball Grid Array (1.0 mm pitch)

ProASIC®3 Flash Family FPGAs

iv v2.1

Temperature Grade Offerings

Speed Grade and Temperature Grade Matrix

Datasheet references made to ProASIC3 devices also apply to ARM-enabled ProASIC3 devices. The ARM-enabled part

numbers start with M7.

Contact your local Actel representative for device availability (http://www.actel.com/contact/default.aspx).

Package

A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 A3P1000

M7A3P250 1M7A3P400 M7A3P600 M7A3P1000

QN132 C, I C, I C, I C, I – – –

VQ100 C, I C, I C, I C, I – – –

TQ144 – C, I C, I – – – –

PQ208 – – C, I C, I C, I C, I C, I

FG144 – C, I C, I C, I C, I C, I C, I

FG256 – – – C, I C, I C, I C, I

FG484 – – – – C, I C, I C, I

Notes:

1. The M7A3P250 device does not support FG256 or QN132 packages.

2. C = Commercial temperature range: 0°C to 70°C

3. I = Industrial temperature range: –40°C to 85°C

Temperature Grade –F 1Std. –1 –2

C2✓✓✓✓

I3–✓✓✓

Notes:

1. The DC and switching characteristics for the –F speed grade targets are based only on simulation.

The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some restrictions

might be added and will be reflected in future revisions of this document. The –F speed grade is only supported in the commercial

temperature range.

2. C = Commercial temperature range: 0°C to 70°C

3. I = Industrial temperature range: –40°C to 85°C

v2.1 v

Table of Contents

ProASIC3 Flash Family FPGAs

Introduction and Overview

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

Device Architecture

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-52

Software Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54

Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54

Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54

ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-55

DC and Switching Characteristics

General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-68

Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-72

Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-77

Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-94

JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-95

Package Pin Assignments

132-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

100-Pin VQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10

144-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15

208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20

144-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31

256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-44

484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-57

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

Export Administration Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

ProASIC®3/E Flash Family FPGAs

v2.1 1-1

Introduction and Overview

General Description

ProASIC3, the third-generation family of Actel Flash

FPGAs, offers performance, density, and features beyond

those of the ProASICPLUS® family. Nonvolatile Flash

technology gives ProASIC3 devices the advantage of

being a secure, low-power, single-chip solution that is

live at power-up (LAPU). ProASIC3 is reprogrammable

and offers time-to-market benefits at an ASIC-level unit

cost. These features enable designers to create high-

density systems using existing ASIC or FPGA design flows

and tools.

ProASIC3 devices offer 1 kbit of on-chip,

reprogrammable, nonvolatile FlashROM storage as well

as clock conditioning circuitry based on an integrated

phase-locked loop (PLL). The A3P030 device has no PLL or

RAM support. ProASIC3 devices have up to 1 million

system gates, supported with up to 144 kbits of true

dual-port SRAM and up to 288 user I/Os.

ProASIC3 devices support the ARM7 soft IP core in

devices with at least 250 k system gates. The ARM-

enabled devices have Actel ordering numbers that begin

with M7A3P and do not support AES decryption.

Flash Advantages

Reduced Cost of Ownership

Advantages to the designer extend beyond low unit cost,

performance, and ease of use. Unlike SRAM-based

FPGAs, Flash-based ProASIC3 devices allow all

functionality to be live at power-up; no external boot

PROM is required. On-board security mechanisms

prevent access to all the programming information and

enable secure remote updates of the FPGA logic.

Designers can perform secure remote in-system

reprogramming to support future design iterations and

field upgrades with confidence that valuable intellectual

property (IP) cannot be compromised or copied. Secure

ISP can be performed using the industry-standard AES

algorithm. The ProASIC3 family device architecture

mitigates the need for ASIC migration at higher user

volumes. This makes the ProASIC3 family a cost-effective

ASIC replacement solution, especially for applications in

the consumer, networking/ communications, computing,

and avionics markets.

Security

The nonvolatile, Flash-based ProASIC3 devices do not

require a boot PROM, so there is no vulnerable external

bitstream that can be easily copied. ProASIC3 devices

incorporate FlashLock, which provides a unique

combination of reprogrammability and design security

without external overhead, advantages that only an

FPGA with nonvolatile Flash programming can offer.

ProASIC3 devices utilize a 128-bit Flash-based lock and a

separate AES key to secure programmed intellectual

property and configuration data. In addition, all

FlashROM data in ProASIC3 devices can be encrypted

prior to loading, using the industry-leading AES-128

(FIPS192) bit block cipher encryption standard. The AES

standard was adopted by the National Institute of

Standards and Technology (NIST) in 2000 and replaces

the 1977 DES standard. ProASIC3 devices have a built-in

AES decryption engine and a Flash-based AES key that

make them the most comprehensive programmable logic

device security solution available today. ProASIC3 devices

with AES-based security allow for secure, remote field

updates over public networks such as the Internet, and

ensure that valuable IP remains out of the hands of

system overbuilders, system cloners, and IP thieves. The

contents of a programmed ProASIC3 device cannot be

read back, although secure design verification is possible.

ARM-enabled ProASIC3 devices do not support user-

controlled AES security mechanisms. Since the ARM core

must be protected at all times, AES encryption is always

on for the core logic, so bitstreams are always encrypted.

There is no user access to encryption for the FlashROM

programming data.

Security, built into the FPGA fabric, is an inherent

component of the ProASIC3 family. The Flash cells are

located beneath seven metal layers, and many device

design and layout techniques have been used to make

invasive attacks extremely difficult. The ProASIC3 family,

with FlashLock and AES security, is unique in being highly

resistant to both invasive and noninvasive attacks. Your

valuable IP is protected and secure, making remote ISP

possible. An ProASIC3 device provides the most

impenetrable security for programmable logic designs.

Single Chip

Flash-based FPGAs store their configuration information

in on-chip Flash cells. Once programmed, the

configuration data is an inherent part of the FPGA

structure, and no external configuration data needs to

be loaded at system power-up (unlike SRAM-based

ProASIC®3/E Flash Family FPGAs

1-2 v2.1

FPGAs). Therefore, Flash-based ProASIC3 FPGAs do not

require system configuration components such as

EEPROMs or microcontrollers to load device

configuration data. This reduces bill-of-materials costs

and PCB area, and increases security and system

reliability.

Live at Power-Up

The Actel Flash-based ProASIC3 devices support Level 0

of the LAPU classification standard. This feature helps in

system component initialization, execution of critical

tasks before the processor wakes up, setup and

configuration of memory blocks, clock generation, and

bus activity management. The LAPU feature of Flash-

based ProASIC3 devices greatly simplifies total system

design and reduces total system cost, often eliminating

the need for CPLDs and clock generation PLLs that are

used for these purposes in a system. In addition, glitches

and brownouts in system power will not corrupt the

ProASIC3 device's Flash configuration, and unlike SRAM-

based FPGAs, the device will not have to be reloaded

when system power is restored. This enables the

reduction or complete removal of the configuration

PROM, expensive voltage monitor, brownout detection,

and clock generator devices from the PCB design. Flash-

based ProASIC3 devices simplify total system design and

reduce cost and design risk while increasing system

reliability and improving system initialization time.

Firm Errors

Firm errors occur most commonly when high-energy

neutrons, generated in the upper atmosphere, strike a

configuration cell of an SRAM FPGA. The energy of the

collision can change the state of the configuration cell

and thus change the logic, routing, or I/O behavior in an

unpredictable way. These errors are impossible to

prevent in SRAM FPGAs. The consequence of this type of

error can be a complete system failure. Firm errors do

not exist in the configuration memory of ProASIC3 Flash-

based FPGAs. Once it is programmed, the Flash cell

configuration element of ProASIC3 FPGAs cannot be

altered by high-energy neutrons and is therefore

immune to them. Recoverable (or soft) errors occur in

the user data SRAM of all FPGA devices. These can easily

be mitigated by using error detection and correction

(EDAC) circuitry built into the FPGA fabric.

Low Power

Flash-based ProASIC3 devices exhibit power

characteristics similar to an ASIC, making them an ideal

choice for power-sensitive applications. ProASIC3 devices

have only a very limited power-on current surge and no

high-current transition period, both of which occur on

many FPGAs.

ProASIC3 devices also have low dynamic power

consumption to further maximize power savings.

Advanced Flash Technology

The ProASIC3 family offers many benefits, including

nonvolatility and reprogrammability through an

advanced Flash-based, 130-nm LVCMOS process with

seven layers of metal. Standard CMOS design techniques

are used to implement logic and control functions. The

combination of fine granularity, enhanced flexible

routing resources, and abundant Flash switches allows

for very high logic utilization without compromising

device routability or performance. Logic functions within

the device are interconnected through a four-level

routing hierarchy.

Advanced Architecture

The proprietary ProASIC3 architecture provides

granularity comparable to standard-cell ASICs. The

ProASIC3 device consists of five distinct and

programmable architectural features (Figure 1-1 and

Figure 1-2 on page 1-3):

• FPGA VersaTiles

• Dedicated FlashROM

• Dedicated SRAM/FIFO memory1

• Extensive CCCs and PLLs1

• Advanced I/O structure

The FPGA core consists of a sea of VersaTiles. Each

VersaTile can be configured as a three-input logic

function, a D-flip-flop (with or without enable), or a

latch by programming the appropriate Flash switch

interconnections. The versatility of the ProASIC3 core tile

as either a three-input lookup table (LUT) equivalent or

as a D-flip-flop/latch with enable allows for efficient use

of the FPGA fabric. The VersaTile capability is unique to

the Actel ProASIC family of third-generation architecture

Flash FPGAs. VersaTiles are connected with any of the

four levels of routing hierarchy. Flash switches are

distributed throughout the device to provide

nonvolatile, reconfigurable interconnect programming.

Maximum core utilization is possible for virtually any

design.

In addition, extensive on-chip programming circuitry

allows for rapid, single-voltage (3.3 V) programming of

ProASIC3 devices via an IEEE 1532 JTAG interface.

1. The A3P030 does not support PLL or SRAM.

ProASIC®3/E Flash Family FPGAs

v2.1 1-3

Note: *Not supported by A3P030

Figure 1-1 • ProASIC3 Device Architecture Overview with Two I/O Banks (A3P030, A3P060, and A3P125)

Figure 1-2 • ProASIC3 Device Architecture Overview with Four I/O Banks (A3P250, A3P600, and A3P1000)

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block*

VersaTile

CCC

I/Os

ISP AES

Decryption*

User Nonvolatile

FlashROM (FROM) Charge Pumps

Bank 0

Bank 1Bank 1

Bank 0Bank 0

Bank 1

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block

(A3P600 and A3P1000)

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block

VersaTile

CCC

I/Os

ISP AES

Decryption

User Nonvolatile

FlashROM Charge Pumps

Bank 0

Bank 3Bank 3

Bank 1Bank 1

Bank 2

ProASIC®3/E Flash Family FPGAs

1-4 v2.1

VersaTiles

The ProASIC3 core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS® core tiles. The ProASIC3

VersaTile supports the following:

• All 3-input logic functions—LUT-3 equivalent

• Latch with clear or set

• D-flip-flop with clear or set

• Enable D-flip-flop with clear or set

Refer to Figure 1-3 for VersaTile configurations.

User Nonvolatile FlashROM

Actel ProASIC3 devices have 1 kbit of on-chip, user-

accessible, nonvolatile FlashROM. The FlashROM can be

used in diverse system applications:

• Internet protocol addressing (wireless or fixed)

• System calibration settings

• Device serialization and/or inventory control

• Subscription-based business models (for example,

set-top boxes)

• Secure key storage for secure communications

algorithms

• Asset management/tracking

• Date stamping

• Version management

The FlashROM is written using the standard ProASIC3

IEEE 1532 JTAG programming interface. The core can be

individually programmed (erased and written), and on-

chip AES decryption can be used selectively to securely

load data over public networks (except in the A3P030

device), as in security keys stored in the FlashROM for a

user design.

The FlashROM can be programmed via the JTAG

programming interface, and its contents can be read

back either through the JTAG programming interface or

via direct FPGA core addressing. Note that the FlashROM

can only be programmed from the JTAG interface and

cannot be programmed from the internal logic array.

The FlashROM is programmed as 8 banks of 128 bits;

however, reading is performed on a byte-by-byte basis

using a synchronous interface. A 7-bit address from the

FPGA core defines which of the 8 banks and which of the

16 bytes within that bank are being read. The three most

significant bits (MSBs) of the FlashROM address

determine the bank, and the four least significant bits

(LSBs) of the FlashROM address define the byte.

The Actel ProASIC3 development software solutions,

Libero® Integrated Design Environment (IDE) and

Designer, have extensive support for the FlashROM. One

such feature is auto-generation of sequential

programming files for applications requiring a unique

serial number in each part. Another feature allows the

inclusion of static data for system version control. Data

for the FlashROM can be generated quickly and easily

using Actel Libero IDE and Designer software tools.

Comprehensive programming file support is also

included to allow for easy programming of large

numbers of parts with differing FlashROM contents.

SRAM and FIFO

ProASIC3 devices (except the A3P030 device) have

embedded SRAM blocks along their north and south

sides. Each variable-aspect-ratio SRAM block is 4,608 bits

in size. Available memory configurations are 256×18,

512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks

have independent read and write ports that can be

configured with different bit widths on each port. For

example, data can be sent through a 4-bit port and read

as a single bitstream. The embedded SRAM blocks can be

initialized via the device JTAG port (ROM emulation

mode) using the UJTAG macro (except in the A3P030

device).

Figure 1-3 • VersaTile Configurations

LUT-3

Data Y

CLK

Enable

CLR

D-FF

Data Y

CLK

CLR

D-FF

LUT-3 Equivalent D-Flip-Flop with Clear or Set Enable D-Flip-Flop with Clear or Set

ProASIC®3/E Flash Family FPGAs

v2.1 1-5

In addition, every SRAM block has an embedded FIFO

control unit. The control unit allows the SRAM block to

be configured as a synchronous FIFO without using

additional core VersaTiles. The FIFO width and depth are

programmable. The FIFO also features programmable

Almost Empty (AEMPTY) and Almost Full (AFULL) flags in

addition to the normal Empty and Full flags. The

embedded FIFO control unit contains the counters

necessary for generation of the read and write address

pointers. The embedded SRAM/FIFO blocks can be

cascaded to create larger configurations.

PLL and CCC

ProASIC3 devices provide designers with very flexible

clock conditioning capabilities. Each member of the

ProASIC3 family contains six CCCs. One CCC (center west

side) has a PLL. The A3P030 does not have a PLL.

The six CCC blocks are located at the four corners and the

centers of the east and west sides.

All six CCC blocks are usable; the four corner CCCs and

the east CCC allow simple clock delay operations as well

as clock spine access.

The inputs of the six CCC blocks are accessible from the

FPGA core or from one of several inputs located near the

CCC that have dedicated connections to the CCC block.

The CCC block has these key features:

• Wide input frequency range (fIN_CCC) = 1.5 MHz to

350 MHz

• Output frequency range (fOUT_CCC) = 0.75 MHz to

350 MHz

• Clock delay adjustment via programmable and

fixed delays from –7.56 ns to +11.12 ns

• 2 programmable delay types for clock skew

minimization

• Clock frequency synthesis (for PLL only)

Additional CCC specifications:

• Internal phase shift = 0°, 90°, 180°, and 270°.

Output phase shift depends on the output divider

configuration (for PLL only).

• Output duty cycle = 50% ± 1.5% or better (for PLL

only)

• Low output jitter: worst case < 2.5% × clock period

peak-to-peak period jitter when single global

network used (for PLL only)

• Maximum acquisition time = 300 µs (for PLL only)

• Low power consumption of 5 mW

• Exceptional tolerance to input period jitter—

allowable input jitter is up to 1.5 ns (for PLL only)

• Four precise phases; maximum misalignment

between adjacent phases of 40 ps × (350 MHz /

fOUT_CCC) (for PLL only)Global Clocking

ProASIC3 devices have extensive support for multiple

clocking domains. In addition to the CCC and PLL support

described above, there is a comprehensive global clock

distribution network.

Each VersaTile input and output port has access to nine

VersaNets: six chip (main) and three quadrant global

networks. The VersaNets can be driven by the CCC or

directly accessed from the core via multiplexers (MUXes).

The VersaNets can be used to distribute low-skew clock

signals or for rapid distribution of high fanout nets.

I/Os with Advanced I/O Standards

The ProASIC3 family of FPGAs features a flexible I/O

structure, supporting a range of voltages (1.5 V, 1.8 V,

2.5 V, and 3.3 V). ProASIC3 FPGAs support many different

I/O standards—single-ended and differential.

The I/Os are organized into banks, with two or four

banks per device. The configuration of these banks

determines the I/O standards supported.

Each I/O module contains several input, output, and

enable registers. These registers allow the

implementation of the following:

• Single-Data-Rate applications

• Double-Data-Rate applications—DDR LVDS, BLVDS,

and M-LVDS I/Os for point-to-point communications

ProASIC3 banks for the A3P250 device and above

support LVPECL, LVDS, BLVDS and M-LVDS. BLVDS and M-

LVDS can support up to 20 loads.

ProASIC®3/E Flash Family FPGAs

1-6 v2.1

Related Documents

Application Notes

ProASIC3/E I/O Usage Guide

http://www.actel.com/documents/PA3_E_IO_AN.pdf

In-System Programming (ISP) in ProASIC3/E Using FlashPro3

http://www.actel.com/documents/PA3_E_ISP_AN.pdf

ProASIC3/E FlashROM

http://www.actel.com/documents/PA3_E_FROM_AN.pdf

ProASIC3/E Security

http://www.actel.com/documents/PA3_E_Security_AN.pdf

ProASIC3/E SRAM/FIFO Blocks

http://www.actel.com/documents/PA3_E_SRAMFIFO_AN.pdf

Programming a ProASIC3/E Using a Microprocessor

http://www.actel.com/documents/PA3_E_Microprocessor_AN.pdf

UJTAG Applications in ProASIC3/E Devices

http://www.actel.com/documents/PA3_E_UJTAG_AN.pdf

Using DDR for ProASIC3/E Devices

http://www.actel.com/documents/PA3_E_DDR_AN.pdf

Using Global Resources in Actel ProASIC3/E Devices

http://www.actel.com/documents/PA3_E_Global_AN.pdf

Power-Up/Down Behavior of ProASIC3/E Devices

http://www.actel.com/documents/ProASIC3_E_PowerUp_AN.pdf

For additional ProASIC3 application notes, go to http://www.actel.com/techdocs/an.aspx.

User’s Guides

SmartGen Cores Reference Guide

http://www.actel.com/documents/genguide_ug.pdf

Designer User’s Guide

http://www.actel.com/documents/designer_ug.pdf

ProASIC3/E Macro Library Guide

http://www.actel.com/documents/pa3_libguide_ug.pdf

ProASIC®3/E Flash Family FPGAs

v2.1 2-1

Device Architecture

Introduction

Flash Technology

Advanced Flash Switch

Unlike SRAM FPGAs, the ProASIC3 family uses a live at

power-up ISP Flash switch as its programming element.

Flash cells are distributed throughout the device to

provide nonvolatile, reconfigurable programming to

connect signal lines to the appropriate VersaTile inputs

and outputs. In the Flash switch, two transistors share

the floating gate, which stores the programming

information (Figure 2-1). One is the sensing transistor,

which is only used for writing and verification of the

floating gate voltage. The other is the switching

transistor. The latter is used to connect or separate

routing nets, or to configure VersaTile logic. It is also

used to erase the floating gate. Dedicated high-

performance lines are connected as required using the

Flash switch for fast, low-skew, global signal distribution

throughout the device core. Maximum core utilization is

possible for virtually any design. The use of the Flash

switch technology also removes the possibility of firm

errors, which are increasingly common in SRAM-based

FPGAs.

Figure 2-1 • ProASIC3 Flash-Based Switch

Sensing Switching

Switch In

Switch Out

Word

Floating Gate

ProASIC®3/E Flash Family FPGAs

2-2 v2.1

Device Overview

The ProASIC3 device family consists of five distinct

programmable architectural features (Figure 2-2 and

Figure 2-3 on page 2-3):

• FPGA fabric/core (VersaTiles)

• Routing and clock resources (VersaNets)

• FlashROM

• Dedicated SRAM/FIFO memory (except A3P030)

• Advanced I/O structure

Core Architecture

VersaTile

The proprietary ProASIC3 family architecture provides

granularity comparable to gate arrays. The ProASIC3

device core consists of a sea-of-VersaTiles architecture.

As illustrated in Figure 2-4 on page 2-4, there are four

inputs in a logic VersaTile cell, and each VersaTile can be

configured using the appropriate Flash switch

connections:

• Any 3-input logic function

• Latch with clear or set

• D-flip-flop with clear or set

• Enable D-flip-flop with clear or set (on a fourth

input)

VersaTiles can flexibly map the logic and sequential gates

of a design. The inputs of the VersaTile can be inverted

(allowing bubble pushing), and the output of the tile can

connect to high-speed, very-long-line routing resources.

VersaTiles and larger functions can be connected with

any of the four levels of routing hierarchy.

When the VersaTile is used as an enable D-flip-flop,

SET/CLR is supported by a fourth input. The SET/CLR

signal can only be routed to this fourth input over the

VersaNet (global) network. However, if in the user’s

design the SET/CLR signal is not routed over the VersaNet

network, a compile warning message will be given and

the intended logic function will be implemented by two

VersaTiles instead of one.

The output of the VersaTile is F2 (Figure 2-4 on page 2-4)

when the connection is to the ultra-fast local lines, or YL

when the connection is to the efficient long-line or very-

long-line resources.

Note: *Not supported by A3P030.

Figure 2-2 • ProASIC3 Device Architecture Overview with Two I/O Banks (A3P030, A3P060, A3P125)

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block*

VersaTile

CCC

I/Os

ISP AES

Decryption*

User Nonvolatile

FlashROM Charge Pumps

Bank 0

Bank 1Bank 1

Bank 0Bank 0

Bank 1

ProASIC®3/E Flash Family FPGAs

v2.1 2-3

Figure 2-3 • ProASIC3 Device Architecture Overview with Four I/O Banks (A3P250, A3P400, A3P600, A3P1000)

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block

(A3P600 and A3P1000)

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block

VersaTile

CCC

I/Os

ISP AES

Decryption

User Nonvolatile

FlashROM Charge Pumps

Bank 0

Bank 3Bank 3

Bank 1Bank 1

Bank 2

ProASIC®3/E Flash Family FPGAs

2-4 v2.1

Note: *This input can only be connected to the global clock distribution network.

Figure 2-4 • ProASIC3 Core VersaTile

Switch (Flash connection) Ground

Via (hard connection)

Legend:

Pin 1

Data

CLK

CLR/

Enable

CLR

XC*

ProASIC®3/E Flash Family FPGAs

v2.1 2-5

Array Coordinates

During many place-and-route operations in the Actel

Designer software tool, it is possible to set constraints

that require array coordinates. Table 2-1 provides array

coordinates of core cells and memory blocks. The array

coordinates are measured from the lower left (0, 0). They

can be used in region constraints for specific logic

groups/blocks, designated by a wildcard, and can contain

core cells, memories, and I/Os.

I/O and cell coordinates are used for placement

constraints. Two coordinate systems are needed because

there is not a one-to-one correspondence between I/O

cells and core cells. In addition, the I/O coordinate system

changes depending on the die/package combination. It is

not listed in Table 2-1. The Designer ChipPlanner tool

provides array coordinates of all I/O locations. I/O and

cell coordinates are used for placement constraints.

However, I/O placement is easier by package pin

assignment.

Figure 2-5 illustrates the array coordinates of an A3P600

device. For more information on how to use array

coordinates for region/placement constraints, see the

Designer User's Guide or online help (available in the

software) for ProASIC3 software tools.

Table 2-1 • ProASIC3 Array Coordinates

Device

VersaTiles Memory Rows All

Min. Max. Bottom Top Min. Max.

x y x y (x, y) (x, y) (x, y) (x, y)

A3P030––––––––

A3P060 3 2 66 25 None (3, 26) (0, 0) (69, 29)

A3P125 3 2 130 25 None (3, 26) (0, 0) (133, 29)

A3P250 3 2 130 49 None (3, 50) (0, 0) (133, 53)

A3P400 3 2 194 49 None (3, 50) (0, 0) (197, 53)

A3P600 3 4 194 75 (3, 2) (3, 76) (0, 0) (197, 79)

A3P1000 3 4 258 99 (3, 2) (3, 100) (0, 0) (261, 103)

ProASIC®3/E Flash Family FPGAs

2-6 v2.1

Note: The vertical I/O tile coordinates are not shown. West side coordinates are {(0, 2) to (2, 2)} to {(0, 77) to (2, 77)}; east side coordinates

are {(195, 2) to (197, 2)} to {(195, 77) to (197, 77)}.

Figure 2-5 • Array Coordinates for A3P600

Top Row (5, 1) to (168, 1)

Bottom Row (7, 0) to (165, 0)

Top Row (169, 1) to (192, 1)

I/O Tile

Memory

Blocks

Memory

Blocks

Memory

Blocks

UJTAG FlashROM

Top Row (7, 79) to (189, 79)

Bottom Row (5, 78) to (192, 78)

I/O Tile

(3, 77)

(3, 76)

Memory

Blocks

(3, 3)

(3, 2)

VersaTile (Core)

(3, 75)

VersaTile (Core)

(3, 4)

(0, 0) (197, 0)

(194, 2)

(194, 3)

(194, 4)

VersaTile (Core)

(194, 75)

VersaTile (Core)

(197, 79)

(194, 77)

(194, 76)

(0, 79)

(197, 1)

ProASIC®3/E Flash Family FPGAs

v2.1 2-7

Routing Architecture

Routing Resources

The routing structure of ProASIC3 devices is designed to

provide high performance through a flexible four-level

hierarchy of routing resources: ultra-fast local resources,

efficient long-line resources, high-speed, very-long-line

resources, and the high-performance VersaNet networks.

The ultra-fast local resources are dedicated lines that allow

the output of each VersaTile to connect directly to every

input of the eight surrounding VersaTiles (Figure 2-6). The

exception to this is that the SET/CLR input of a VersaTile

configured as a D-flip-flop is driven only by the VersaTile

global network.

The efficient long-line resources provide routing for longer

distances and higher-fanout connections. These resources

vary in length (spanning one, two, or four VersaTiles), run

both vertically and horizontally, and cover the entire

ProASIC3 device (Figure 2-7 on page 2-8). Each VersaTile

can drive signals onto the efficient long-line resources,

which can access every input of every VersaTile. Active

buffers are inserted automatically by routing software to

limit loading effects.

The high-speed, very-long-line resources, which span the

entire device with minimal delay, are used to route very

long or high-fanout nets: length +/–12 VersaTiles in the

vertical direction and length +/–16 in the horizontal

direction from a given core VersaTile (Figure 2-8 on page

2-9). Very long lines in ProASIC3 devices have been

enhanced over those in previous ProASIC families. This

provides a significant performance boost for long-reach

signals.

The high-performance VersaNet global networks are

low-skew, high-fanout nets that are accessible from

external pins or from internal logic (Figure 2-9 on page

2-11). These nets are typically used to distribute clocks,

resets, and other high-fanout nets requiring minimum

skew. The VersaNet networks are implemented as clock

trees, and signals can be introduced at any junction.

These can be employed hierarchically, with signals

accessing every input on all VersaTiles.

Note: Input to the core cell for the D-flip-flop set and reset is only available via the VersaNet global network connection.

Figure 2-6 • Ultra-Fast Local Lines Connected to the Eight Nearest Neighbors

Inputs

Output

Ultra-Fast Local Lines

(connects a VersaTile to the

adjacent VersaTile, I/O buffer,

or memory block)

LLL

Long Lines

ProASIC®3/E Flash Family FPGAs

2-8 v2.1

Figure 2-7 • Efficient Long-Line Resources

LL LLLL

LLLLLL

LL LLLL

Spans 1 VersaTile

Spans 2 VersaTiles

Spans 4 VersaTiles

Spans 1 VersaTile

Spans 2 VersaTiles

Spans 4 VersaTiles

VersaTile

ProASIC®3/E Flash Family FPGAs

v2.1 2-9

Figure 2-8 • Very-Long-Line Resources

High-Speed, Very-Long-Line Resources

Pad Ring

I/O Ring

Pad Ring

16×12 Block of VersaTiles

SRAM

ProASIC®3/E Flash Family FPGAs

2-10 v2.1

Clock Resources (VersaNets)

ProASIC3 devices offer powerful and flexible control of

circuit timing through the use of analog circuitry. Each

chip has up to six CCCs. The west CCC also contains a

phase-locked loop (PLL) core, delay lines, a phase shifter

(0°, 90°, 180°, 270°), and clock multipliers/dividers. Each

CCC has all the circuitry needed for the selection and

interconnection of inputs to the VersaNet global

network. The east and west CCCs each have access to

three VersaNet global lines on each side of the chip (six

total lines). The CCCs at the four corners each have access

to three quadrant global lines in each quadrant of the

chip (except A3P030).

Advantages of the VersaNet Approach

One of the architectural benefits of ProASIC3 is the set of

powerful and low-delay VersaNet global networks.

ProASIC3 offers six chip (main) global networks that are

distributed from the center of the FPGA array (Figure 2-9).

In addition, ProASIC3 devices have three regional globals in

each of the four chip quadrants. Each core VersaTile has

access to nine global network resources: three quadrant

and six chip (main) global networks, and a total of 18

globals on the device. Each of these networks contains

spines and ribs that reach all the VersaTiles in the quadrants

(Figure 2-10 on page 2-12). This flexible VersaNet global

network architecture allows users to map up to 144

different internal/external clocks in a ProASIC3 device.

Details on the VersaNet networks are given in Table 2-2 on

page 2-12. The flexible use of the ProASIC3 VersaNet global

network allows the designer to address several design

requirements. User applications that are clock-resource-

intensive can easily route external or gated internal clocks

using VersaNet global routing networks. Designers can also

drastically reduce delay penalties and minimize resource

usage by mapping critical, high-fanout nets to the VersaNet

global network.

In A3P030 devices, all six VersaNets are driven from three

southern I/Os, located toward the east and west sides.

These tiles can be configured to select a central I/O on

the respective side or an internal routed signal as the

input signal. The A3P030 does not support any clock

conditioning circuitry, nor does it contain the VersaNet

global network concept of top and bottom spines.

VersaNet Global Networks and Spine Access

The ProASIC3 architecture contains a total of 18

segmented global networks that can access the

VersaTiles, SRAM, and I/O tiles of the ProASIC3 device.

There are nine global network resources in each device

quadrant: three quadrant globals and six chip (main)

global networks. Each device has a total of 18 globals.

These VersaNet global networks offer fast, low-skew

routing resources for high-fanout nets, including clock

signals. In addition, these highly segmented global

networks offer users the flexibility to create low-skew

local networks using spines for up to

144internal/external clocks (in an A3P1000 device) or

other high-fanout nets in ProASIC3 devices. Optimal

usage of these low-skew networks can result in

significant improvement in design performance on

ProASIC3 devices.

The nine spines available in a vertical column reside in

global networks with two separate regions of scope: the

quadrant global network, which has three spines, and

the chip (main) global network, which has six spines.

Note that there are three quadrant spines in each

quadrant of the device (except for A3P030). There are

four quadrant global network regions per device

(Figure 2-10 on page 2-12).

The spines are the vertical branches of the global

network tree, shown in Figure 2-11 on page 2-13. Each

spine in a vertical column of a chip (main) global

network is further divided into two equal-length spine

segments: one in the top and one in the bottom half of

the die.

Each spine and its associated ribs cover a certain area of

the ProASIC3 device (the "scope" of the spine; see

Figure 2-9 on page 2-11). Each spine is accessed by the

dedicated global network MUX tree architecture, which

defines how a particular spine is driven—either by the

signal on the global network from a CCC, for example, or

by another net defined by the user (Figure 2-12 on page

2-14). Quadrant spines can be driven from user I/Os on

the north and south sides of the die. The ability to drive

spines in the quadrant global networks can have a

significant effect on system performance for high-fanout

inputs to a design.

Details of the chip (main) global network spine-selection

MUX are presented in Figure 2-12 on page 2-14. The

spine drivers for each spine are located in the middle of

the die.

Quadrant spines are driven from a north or south rib.

Access to the top and bottom ribs is from the corner CCC

or from the I/Os on the north and south sides of the

device.

For details on using spines in ProASIC3 devices, see the

Actel application note Using Global Resources in Actel

ProASIC3/E Devices.

ProASIC®3/E Flash Family FPGAs

v2.1 2-11

Note: Not applicable to the A3P030 device.

Figure 2-9 • Overview of ProASIC3 VersaNet Global Network

Quadrant Global Pads

Top Spine

Bottom Spine

Pad Ring

I/O Ring

Chip (main)

Global Pads

Spine-Selection

Tree MUX

Global

Pads

High-Performance

VersaNet Global Network

Main (chip)

Global Network

Global Spine

Global Ribs

ProASIC®3/E Flash Family FPGAs

2-12 v2.1

Note: This does not apply to the A3P030 device.

Figure 2-10 • Global Network Architecture

Table 2-2 • ProASIC3 Globals/Spines/Rows by Device

A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 A3P1000

Global VersaNets (Trees)* 6 9 9 9 9 9 9

VersaNet Spines/Tree 4 4 4 8 8 12 16

Total Spines 24 36 36 72 72 108 144

VersaTiles in Each Top or Bottom Spine 384 384 384 768 768 1,152 1,536

Total VersaTiles 768 1,536 3,072 6,144 9,216 13,824 24,576

Rows in Each Top or Bottom Spine – 12 12 24 24 36 48

Note: *There are six chip (main) globals and three globals per quadrant (except in the A3P030 device).

Northwest Quadrant Global Network

Southeast Quadrant Global Network

Chip (main)

Global

Network

333

3333

Global Spine Quadrant Global Spine

CCC

CCC CCC

CCC

ProASIC®3/E Flash Family FPGAs

v2.1 2-13

Figure 2-11 • ProASIC3 Spines in a Global Clock Tree Network

Pad Ring

I/O Ring

I/ORing

Chip (main)

Global Pads

Global

Pads

High-Performance

Global Network

Global Spine

Global Ribs

Scope of Spine

(shaded area

plus local RAMs

and I/Os)

Spine-Selection

MUX

Embedded

RAM Blocks

Logic Tiles

Top Spine

Bottom Spine

Quadrant Global Pads

ProASIC®3/E Flash Family FPGAs

2-14 v2.1

Clock Aggregation

Clock aggregation allows for multi-spine clock domains.

A MUX tree provides the necessary flexibility to allow

long lines or I/Os to access domains of one, two, or four

global spines. Signal access to the clock aggregation

system is achieved through long-line resources in the

central rib, and also through local resources in the north

and south ribs, allowing I/Os to feed directly into the

clock system. As Figure 2-13 indicates, this access system

is contiguous.

There is no break in the middle of the chip for the north

and south I/O VersaNet access. This is different from the

quadrant clocks located in these ribs, which only reach

the middle of the rib. Refer to the Using Global

Resources in Actel ProASIC3/E Devices application note.

Figure 2-12 • Spine Selection MUX of Global Tree

Figure 2-13 • Clock Aggregation Tree Architecture

Internal/External

Signal

Internal/External

Signal

Internal/External

Signals

Spine

Global Rib

Global Driver MUX

Tree Node MUX

Internal/External

Signals

Tree Node MUX

Global Spine

Global Rib

Global Driver and MUX

I/O Access

Internal Signal Access

I/O Tiles

Global Signal Access

Tree Node MUX

ProASIC®3/E Flash Family FPGAs

v2.1 2-15

Clock Conditioning Circuits

Overview of Clock Conditioning Circuitry

In ProASIC3 devices, the CCCs are used to implement

frequency division, frequency multiplication, phase

shifting, and delay operations.

The CCCs are available in six chip locations—each of the

four chip corners and the middle of the east and west

chip sides.

Each CCC can implement up to three independent global

buffers (with or without programmable delay), or a PLL

function (programmable frequency division/multiplication,

phase shift, and delays) with up to three global outputs.

Unused global outputs of a PLL can be used to

implement independent global buffers, up to a

maximum of three global outputs for a given CCC.

A global buffer can be placed in any of the three global

locations (CLKA-GLA, CLKB-GLB, or CLKC-GLC) of a given

CCC.

A PLL macro uses the CLKA CCC input to drive its reference

clock. It uses the GLA and optionally the GLB and GLC

global outputs to drive the global networks. A PLL macro

can also drive the YB and YC regular core outputs. The GLB

(or GLC) global output cannot be reused if the YB (or YC)

output is used (Figure 2-14 on page 2-16). Refer to the

"PLL Macro" section on page 2-17 for more information.

Each global buffer, as well as the PLL reference clock, can

be driven from one of the following:

• 3 dedicated single-ended I/Os using a hardwired

connection

• 2 dedicated differential I/Os using a hardwired

connection

•The FPGA core

The CCC block is fully configurable, either via Flash

configuration bits set in the programming bitstream or

through an asynchronous interface. This asynchronous

interface is dynamically accessible from inside the

ProASIC3 device to permit parameter changes (such as

divide ratios) during device operation. To increase the

versatility and flexibility of the clock conditioning

system, the CCC configuration is determined either by

the user during the design process, with configuration

data being stored in Flash memory as part of the device

programming procedure, or by writing data into a

dedicated shift register during normal device operation.

This latter mode allows the user to dynamically

reconfigure the CCC without the need for core

programming. The shift register is accessed through a

simple serial interface. Refer to the UJTAG Applications

in ProASIC3/E Devices application note and the "CCC

Electrical Specifications" section on page 2-20 for more

information.

Global Buffers with No Programmable Delays

The CLKBUF and CLKBUF_LVPECL/LVDS/BLVDS/M-LVDS

macros are composite macros that include an I/O macro

driving a global buffer, which uses a hardwired

connection.

The CLKBUF, CLKBUF_LVPECL/LVDS/BLVDS/M-LVDS, and

CLKINT macros are pass-through clock sources and do

not use the PLL or provide any programmable delay

functionality.

The CLKINT macro provides a global buffer function

driven by the FPGA core.

Many specific CLKBUF macros support the wide variety of

single-ended and differential I/O standards supported by

ProASIC3 devices. The available CLKBUF macros are

described in the ProASIC3/E Macro Library Guide.

Global Buffer with Programmable Delay

The CLKDLY macro is a pass-through clock source that

does not use the PLL, but provides the ability to delay the

clock input using a programmable delay. The CLKDLY

macro takes the selected clock input and adds a user-

defined delay element. This macro generates an output

clock phase shift from the input clock.

The CLKDLY macro can be driven by an INBUF* macro to

create a composite macro, where the I/O macro drives

the global buffer (with programmable delay) using a

hardwired connection. In this case, the I/O must be

placed in one of the dedicated global I/O locations.

Many specific INBUF macros support the wide variety of

single-ended and differential I/O standards supported by

the ProASIC3 family. The available INBUF macros are

described in the ProASIC3/E Macro Library Guide.

The CLKDLY macro can be driven directly from the FPGA

core.

The CLKDLY macro can also be driven from an I/O that is

routed through the FPGA regular routing fabric. In this

case, users must instantiate a special macro, PLLINT, to

differentiate from the hardwired I/O connection

described earlier.

The visual CLKDLY configuration in the SmartGen part of

the Libero IDE and Designer tools allows the user to

select the desired amount of delay and configures the

delay elements appropriately. SmartGen also allows the

user to select the input clock source. SmartGen will

automatically instantiate the special macro, PLLINT,

when needed.

ProASIC®3/E Flash Family FPGAs

2-16 v2.1

Notes:

1. Visit the Actel website for future application notes concerning dynamic PLL reconfiguration. The PLL is only supported on the west

center CCC. The A3P030 has no PLL support. Refer to the "PLL Macro" section on page 2-17 for signal descriptions.

2. Refer to the ProASIC3/E Macro Library Guide for more information.

3. Many standard-specific INBUF macros (for example, INBUF_LVDS) support the wide variety of single-ended and differential I/O

standards supported by the ProASIC3 family. The available INBUF macros are described in the ProASIC3/E Macro Library Guide.

Figure 2-14 • ProASIC3 CCC Options

CLKBUF_LVDS/LVPECL Macro

PADN

PADP

PAD Y

CLKINT MacroCLKBUF Macro

Input LVDS/LVPECL Macro PLL Macro

INBUF* Macro

GLA

GLA and (GLB or YB)

GLA and (GLC or YC)

GLA and (GLB or YB) and

(GLC or YC)

GLA

GLB

GLC

Clock Source Clock Conditioning Output

OADIV[4:0]

OAMUX[2:0]

DLYGLA[4:0]

OBDIV[4:0]

OBMUX[2:0]

DLYYB[4:0]

DLYGLB[4:0]

OCDIV[4:0]

OCMUX[2:0]

DLYYC[4:0]

DLYGLC[4:0]

FINDIV[6:0]

FBDIV[6:0]

FBDLY[4:0]

FBSEL[1:0]

XDLYSEL

VCOSEL[2:0]

CLKA GLA

LOCK

GLB

GLC

POWERDOWN

CLKDLY Macro

CLK GL

DLYGL[4:0]

PADN

PADP Y

ProASIC®3/E Flash Family FPGAs

v2.1 2-17

PLL Macro1

The PLL functionality of the clock conditioning block is

supported by the PLL macro. Note that the PLL macro

reference clock uses the CLKA input of the CCC block,

which is only accessible from the global A[0:2] package

pins. Refer to Figure 2-15 on page 2-18 for more

information.

The PLL macro provides five derived clocks (three

independent) from a single reference clock. The PLL

macro also provides power-down input and lock output

signals. See Figure 2-17 on page 2-19 for more

information.

Inputs:

• CLKA: selected clock input

• POWERDOWN (active low): disables PLLs. The

default state is Powerdown On (active low).

Outputs:

• LOCK: indicates that PLL output has locked on the

input reference signal

• GLA, GLB, GLC: outputs to respective global

networks

• YB, YC: allows output from the CCC to be routed

back to the FPGA core

As previously described, the PLL allows up to five flexible

and independently configurable clock outputs. Figure 2-20

on page 2-21 illustrates the various clock output options

and delay elements.

As illustrated, the PLL supports three distinct output

frequencies from a given input clock. Two of these (GLB

and GLC) can be routed to the B and C global network

access, respectively, and/or routed to the device core (YB

and YC).

There are five delay elements to support phase control

on all five outputs (GLA, GLB, GLC, YB, and YC).

There is also a delay element in the feedback loop that

can be used to advance the clock relative to the

reference clock.

The PLL macro reference clock can be driven by an INBUF*

macro to create a composite macro, where the I/O macro

drives the global buffer (with programmable delay) using a

hardwired connection. In this case, the I/O must be placed

in one of the dedicated global I/O locations.

The PLL macro reference clock can be driven directly

from the FPGA core.

The PLL macro reference clock can also be driven from an

I/O that is routed through the FPGA regular routing

fabric. In this case, users must instantiate a special macro,

PLLINT, to differentiate from the hardwired I/O

connection described earlier.

During power-up, the PLL outputs will toggle around the

maximum frequency of the VCO gear selected. Toggle

frequencies can range from 40 Mhz to 350 Mhz. This will

continue as long as the clock input (CLKA) is constant

(high or low). This can be prevented by LOW assertion of

the POWERDOWN signal.

The visual PLL configuration in SmartGen, part of the

Libero IDE and Designer tools, will derive the necessary

internal divider ratios based on the input frequency and

desired output frequencies selected by the user.

SmartGen also allows the user to select the various delays

and phase shift values necessary to adjust the phases

between the reference clock (CLKA) and the derived

clocks (GLA, GLB, GLC, YB, and YC). SmartGen also allows

the user to select the input clock source. SmartGen

automatically instantiates the special macro, PLLINT,

when needed.

1. The A3P030 device has no CCC, and thus does not include a PLL.

ProASIC®3/E Flash Family FPGAs

2-18 v2.1

Notes:

1. Represents the global input pins. Globals have direct access to the clock conditioning block and are not routed via the FPGA fabric.

Refer to the "User I/O Naming Convention" section on page 2-50 for more information.

2. Instantiate the routed clock source input as follows:

a) Connect the output of a logic element to the clock input of a PLL, CLKDLY, or CLKINT macro.

b) Do not place a clock source I/O (INBUF or INBUF_LVPECL/LVDS/BLVDS/M-LVDS/DDR) in a relevant global pin location.

3. LVDS-, BLVDS-, and M-LVDS-based clock sources are only available on A3P250 through A3P1000 devices. A3P030, A3P060, and

A3P125 support single-ended clock sources only. The A3P030 device does not contain a PLL.

Figure 2-15 • Clock Input Sources Including CLKBUF, CLKBUF_LVDS/LVPECL, and CLKINT

Note: The A3P030 device does not support this feature.

Figure 2-16 • CLKBUF and CLKINT

Source for CCC

(CLKA or CLKB or CLKC)

Each shaded box represents an

INBUF or INBUF_LVDS/LVPECL

macro, as appropriate. To Core

Routed Clock

(from FPGA core)

Sample Pin Names

GAA0/IO0NDB0V0

GAA1/IO00PDB0V0

GAA2/IO13PDB7V1

GAA[0:2]: GA represents global in the northwest corner

of the device. A[0:2]: designates specific A clock source.

CLKBUF CLKINT

CLKBUF_LVDS/LVPECL

PADN

PADP Y

PAD Y YA

ProASIC®3/E Flash Family FPGAs

v2.1 2-19

Table 2-3 • Available ProASIC3 I/O Standards within

CLKBUF and CLKBUF_LVDS/LVPECL Macros

CLKBUF Macros

CLKBUF_LVCMOS5

CLKBUF_LVCMOS331

CLKBUF_LVCMOS18

CLKBUF_LVCMOS15

CLKBUF_PCI

CLKBUF_LVDS2

CLKBUF_LVPECL

Notes:

1. By default, the CLKBUF macro uses the 3.3 V LVTTL I/O

technology. For more details, refer to the ProASIC3/E Macro

Library Guide.

2. BLVDS and M-LVDS standards are supported by

CLKBUF_LVDS.

Note: *Visit the Actel website for future application notes

concerning the dynamic PLL.

The A3P030 device does not contain a PLL.

Figure 2-17 • CCC/PLL Macro

CLKA GLA

GLB

GLC

LOCK

POWERDOWN

OADIV[4:0]*

OAMUX[2:0]*

DLYGLA[4:0]*

OBDIV[4:0]*

OBMUX[2:0]*

DLYYB[4:0]*

DLYGLB[4:0]*

OCDIV[4:0]*

OCMUX[2:0]*

DLYYC[4:0]*

DLYGLC[4:0]*

FINDIV[6:0]*

FBDIV[6:0]*

FBDLY[4:0]*

FBSEL[1:0]*

XDLYSEL*

VCOSEL[2:0]*

Note: The CLKDLY macro uses programmable delay element type 2.

Figure 2-18 • CLKDLY

CLKDLY

CLK GL

DLYGL[4:0]

ProASIC®3/E Flash Family FPGAs

2-20 v2.1

CCC Electrical Specifications

Timing Characteristics

Table 2-4 • ProASIC3 CCC/PLL Specification

Parameter Minimum Typical Maximum Units

Clock Conditioning Circuitry Input Frequency fIN_CCC 1.5 350 MHz

Clock Conditioning Circuitry Output Frequency fOUT_CCC 0.75 350 MHz

Delay Increments in Programmable Delay Blocks1, 2 160 ps

Number of Programmable Values in Each Programmable

Delay Block

Input Period Jitter 1.5 ns

CCC Output Peak-to-Peak Period Jitter FCCC_OUT Max Peak-to-Peak Period Jitter

1 Global

Network Used

3 Global

Networks Used

0.75 MHz to 24 MHz 0.50% 0.70%

24 MHz to 100 MHz 1.00% 1.20%

100 MHz to 250 MHz 1.75% 2.00%

250 MHz to 350 MHz 2.50% 5.60%

Acquisition Time

(A3P250 and A3P1000 only) LockControl = 0 300 µs

LockControl = 1 300 µs

(all other dies) LockControl = 0 300 µs

LockControl = 1 6.0 ms

Tracking Jitter4

(A3P250 and A3P1000 only) LockControl = 0 1.6 ns

LockControl = 1 1.6 ns

(all other dies) LockControl = 0 1.6 ns

LockControl = 1 0.8 ns

Output Duty Cycle 48.5 51.5 %

Delay Range in Block: Programmable Delay 11, 2 0.6 5.56 ns

Delay Range in Block: Programmable Delay 21, 2 0.025 5.56 ns

Delay Range in Block: Fixed Delay1, 2 2.2 ns

Notes:

1. This delay is a function of voltage and temperature. See Table 3-6 on page 3-5 for deratings.

2. TJ = 25°C, VCC = 1.5 V

3. The A3P030 device does not contain a PLL.

4. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock edge. Tracking

jitter does not measure the variation in PLL output period, which is covered by the period jitter parameter.

Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max - Tperiod_min

Figure 2-19 • Peak-to-Peak Jitter Definition

period_max

period_min

Output Signal

ProASIC®3/E Flash Family FPGAs

v2.1 2-21

CCC Physical Implementation2

The CCC is composed of the following (Figure 2-20):

• PLL core

• 3 phase selectors

• 6 programmable delays and 1 fixed delay that

advances/delays phase

• 5 programmable frequency dividers that provide

frequency multiplication/division (not shown in

Figure 2-20 because they are automatically

configured based on the user's required

frequencies)

• 1 dynamic shift register that provides CCC dynamic

reconfiguration capability

CCC Programming

The CCC block is fully configurable, either via static Flash

configuration bits in the array, set by the user in the

programming bitstream, or through an asynchronous

dedicated shift register dynamically accessible from

inside the ProASIC3 device. The dedicated shift register

permits changes in parameters such as PLL divide ratios

and delays during device operation. This latter mode

allows the user to dynamically reconfigure the PLL

without the need for core programming. The register file

is accessed through a simple serial interface. Refer to the

UJTAG Applications in ProASIC3/E Devices application

note for more information.

2. The A3P030 device does not contain a PLL.

Notes:

1. Refer to the "Clock Conditioning Circuits" section on page 2-15 and Table 2-4 on page 2-20 for signal descriptions.

2. Clock divider and clock multiplier blocks are not shown in this figure or in SmartGen. They are automatically configured based on the

user's required frequencies.

Figure 2-20 • PLL Block

PLL Core Phase

Select

Phase

Select

Phase

Select

GLA

CLKA

GLB

GLC

Fixed Delay Programmable

Delay Type 1

Programmable

Delay Type 2

Programmable

Delay Type 2

Programmable

Delay Type 1

Programmable

Delay Type 2

Programmable

Delay Type 1

Four-Phase Output

ProASIC®3/E Flash Family FPGAs

2-22 v2.1

Nonvolatile Memory (NVM)

Overview of User Nonvolatile FlashROM

ProASIC3 devices have 1 kbit of on-chip nonvolatile Flash

memory that can be read from the FPGA core fabric. The

FlashROM is arranged in 8 banks of 128 bits during

programming. The 128 bits in each bank are addressable

as 16 bytes during the read back of the FlashROM from

the FPGA core (Figure 2-21).

The FlashROM can only be programmed via the IEEE1532

JTAG port. It cannot be programmed directly from the

FPGA core. When programming, each of the eight

128-bit banks can be selectively reprogrammed. The

FlashROM can only be reprogrammed on a bank

boundary. Programming involves an automatic, on-chip

bank erase prior to reprogramming the bank. The

FlashROM supports synchronous read. The address is

latched on the rising edge of the clock and the new

output data is stable after the falling edge of the same

clock cycle. Please refer to Figure 3-43 on page 3-94 for

the timing diagram. The FlashROM can be read on byte

boundaries. The upper three bits of the FlashROM

address from the FPGA core define the bank that is being

accessed. The lower four bits of the FlashROM address

from the FPGA core define which of the 16 bytes in the

bank is being accessed.

Figure 2-21 • FlashROM Architecture

Bank Number 3 MSB of

ADDR (READ)

Byte Number in Bank 4 LSB of ADDR (READ)

012345

6789101112131415

ProASIC®3/E Flash Family FPGAs

v2.1 2-23

SRAM and FIFO3

ProASIC3 devices (A3P250, A3P400, A3P600, and

A3P1000) have embedded SRAM blocks along the north

and south sides of the devices; A3P060 and A3P125

devices have embedded SRAM blocks on the north side

only. The A3P030 does not include SRAM or FIFO. To

meet the needs of high-performance designs, the

memory blocks operate strictly in synchronous mode for

both read and write operations. The read and write

clocks are completely independent, and each may

operate at any desired frequency less than or equal to

350 MHz.

• 4k×1, 2k×2, 1k×4, 512×9 (dual-port RAM—2 read,

2 write or 1 read, 1 write)

• 512×9, 256×18 (2-port RAM—1 read and 1 write)

• Sync write, sync pipelined / nonpipelined read

The ProASIC3 memory block includes dedicated FIFO

control logic to generate internal addresses and external

flag logic (FULL, EMPTY, AFULL, AEMPTY). Block

diagrams of the memory modules are illustrated in

Figure 2-22 on page 2-24.

Simultaneous dual-port read/write and write/write

operations at the same address are allowed when certain

timing requirements are met.

During RAM operation, addresses are sourced by the

user logic and the FIFO controller is ignored. In FIFO

mode, the internal addresses are generated by the FIFO

controller and routed to the RAM array by internal

MUXes. Refer to Figure 2-23 on page 2-25 for more

information about the implementation of the embedded

FIFO controller.

The ProASIC3 architecture enables the read and write

sizes of RAMs to be organized independently, allowing

for bus conversion. For example, the write side size can

be set to 256×18 and the read size to 512×9.

Both the write width and read width for the RAM blocks

can be specified independently with the WW (write

width) and RW (read width) pins. The different D×W

configurations are: 256×18, 512×9, 1k×4, 2k×2, and 4k×1.

Refer to the allowable RW and WW values supported for

each of the RAM macro types in Table 2-5 on page 2-26.

When widths of one, two, or four are selected, the ninth

bit is unused. For example, when writing nine-bit values

and reading four-bit values, only the first four bits and

the second four bits of each nine-bit value are

addressable for read operations. The ninth bit is not

accessible.

Conversely, when writing four-bit values and reading

nine-bit values, the ninth bit of a read operation will be

undefined. The RAM blocks employ little-endian byte

order for read and write operations.

3. The A3P030 device does not support SRAM or FIFO.

ProASIC®3/E Flash Family FPGAs

2-24 v2.1

Note: The A3P030 device does not support SRAM or FIFO.

Figure 2-22 • Supported Basic RAM Macros

FIFO4K18

RW2

RD17

RW1

RD16

RW0

WW2

WW1

WW0 RD0

ESTOP

FSTOP

FULL

AFULL

EMPTY

AFVAL11

AEMPTY

AFVAL10

AFVAL0

AEVAL11

AEVAL10

AEVAL0

REN

RBLK

RCLK

WEN

WBLK

WCLK

RPIPE

WD17

WD16

WD0

RESET

ADDRA11 DOUTA8

DOUTA7

DOUTA0

DOUTB8

DOUTB7

DOUTB0

ADDRA10

ADDRA0

DINA8

DINA7

DINA0

WIDTHA1

WIDTHA0

PIPEA

WMODEA

BLKA

WENA

CLKA

ADDRB11

ADDRB10

ADDRB0

DINB8

DINB7

DINB0

WIDTHB1

WIDTHB0

PIPEB

WMODEB

BLKB

WENB

CLKB

RAM4K9

RADDR8 RD17

RADDR7 RD16

RADDR0 RD0

WD17

WD16

WD0

WW1

WW0

RW1

RW0

PIPE

REN

RCLK

RAM512x18

WADDR8

WADDR7

WADDR0

WEN

WCLK

RESET

ProASIC®3/E Flash Family FPGAs

v2.1 2-25

Note: The A3P030 device does not support SRAM or FIFO.

Figure 2-23 • ProASIC3 RAM Block with Embedded FIFO Controller

CNT 12

AFVAL

AEVAL

SUB 12

RCLK

WCLK

Reset

RBLK

REN

ESTOP

WBLK

WEN

FSTOP

RD[17:0]

WD[17:0]

RCLK

WCLK

RADD[J:0]

WADD[J:0]

REN

FREN FWEN WEN

FULL

AEMPTY

AFULL

EMPTY

RPIPE

RW[2:0]

WW[2:0]

RAM

ProASIC®3/E Flash Family FPGAs

2-26 v2.1

Signal Descriptions for RAM4K94

The following signals are used to configure the RAM4K9

memory element:

WIDTHA and WIDTHB

These signals enable the RAM to be configured in one of

four allowable aspect ratios (Table 2-5).

BLKA and BLKB

These signals are active low and will enable the

respective ports when asserted. When a BLKx signal is

deasserted, that port’s outputs hold the previous value.

WENA and WENB

These signals switch the RAM between read and write

modes for the respective ports. A LOW on these signals

indicates a write operation, and a HIGH indicates a read.

CLKA and CLKB

These are the clock signals for the synchronous read and

write operations. These can be driven independently or

with the same driver.

PIPEA and PIPEB

These signals are used to specify pipelined read on the

output. A low on PIPEA or PIPEB indicates a nonpipelined

read, and the data appears on the corresponding output

in the same clock cycle. A HIGH indicates a pipelined

read, and data appears on the corresponding output in

the next clock cycle.

WMODEA and WMODEB

These signals are used to configure the behavior of the

output when the RAM is in write mode. A LOW on these

signals makes the output retain data from the previous

read. A HIGH indicates pass-through behavior, wherein

the data being written will appear immediately on the

output. This signal is overridden when the RAM is being

read.

RESET

This active low signal resets the control logic and forces

the output hold state registers to zero and disables reads

and/or writes from the SRAM block as well as clears the

data hold registers when asserted. It does not reset the

contents of the memory array.

While the RESET signal is active, read and write

operations are disabled. As with any asynchronous reset

signal, care must be taken not to assert it too close to the

edges of active read and write clocks. Refer to the tables

beginning with Table 3-101 on page 3-83 for the

specifications.

ADDRA and ADDRB

These are used as read or write addresses, and they are 12

bits wide. When a depth of less than 4 k is specified, the

unused high-order bits must be grounded (Table 2-6).

DINA and DINB

These are the input data signals, and they are nine bits

wide. Not all nine bits are valid in all configurations.

When a data width less than nine is specified, unused

high-order signals must be grounded (Table 2-7).

DOUTA and DOUTB

These are the nine-bit output data signals. Not all nine

bits are valid in all configurations. As with DINA and

DINB, high-order bits may not be used (Table 2-7). The

output data on unused pins is undefined.

4. The A3P030 device does not support SRAM or FIFO.

Table 2-5 • Allowable Aspect Ratio Settings for

WIDTHA[1:0]

WIDTHA[1:0] WIDTHB[1:0] D×W

00 00 4k×1

01 01 2k×2

10 10 1k×4

11 11 512×9

Note: The aspect ratio settings are constant and cannot be

changed on-the-fly. Table 2-6 • Address Pins Unused/Used for Various

Supported Bus Widths

D×W

ADDRx

Unused Used

4k×1 None [11:0]

2k×2 [11] [10:0]

1k×4 [11:10] [9:0]

512×9 [11:9] [8:0]

Note: The "x" in ADDRx implies A or B.

Table 2-7 • Unused/Used Input and Output Data Pins for

Various Supported Bus Widths

D×W

DINx/DOUTx

Unused Used

4k×1 [8:1] [0]

2k×2 [8:2] [1:0]

1k×4 [8:4] [3:0]

512×9 None [8:0]

Note: The "x" in DINx or DOUTx implies A or B.

ProASIC®3/E Flash Family FPGAs

v2.1 2-27

Signal Descriptions for RAM512X185

RAM512X18 has slightly different behavior than

RAM4K9, as it has dedicated read and write ports.

WW and RW

These signals enable the RAM to be configured in one of

the two allowable aspect ratios (Table 2-8).

WD and RD

These are the input and output data signals, and they

are 18 bits wide. When a 512×9 aspect ratio is used for

write, WD[17:9] are unused and must be grounded. If

this aspect ratio is used for read, RD[17:9] are undefined.

WADDR and RADDR

These are read and write addresses, and they are nine

bits wide. When the 256×18 aspect ratio is used for write

or read, WADDR[8] or RADDR[8] are unused and must be

grounded.

WCLK and RCLK

These signals are the write and read clocks, respectively.

They can be clocked on the rising or falling edge of

WCLK and RCLK.

WEN and REN

These signals are the write and read enables,

respectively. They are both active low by default. These

signals can be configured as active high.

RESET

This active low signal resets the control logic and forces

the output hold state registers to zero and disables reads

and/or writes from the SRAM block as well as clears the

data hold registers when asserted. It does not reset the

contents of the memory array.

While the RESET signal is active, read and write

operations are disabled. As with any asynchronous reset

signal, care must be taken not to assert it too close to the

edges of active read and write clocks. Refer to the tables

beginning with Table 3-102 on page 3-84 for the

specifications.

PIPE

This signal is used to specify pipelined read on the

output. A LOW on PIPE indicates a nonpipelined read,

and the data appears on the output in the same clock

cycle. A HIGH indicates a pipelined read, and data

appears on the output in the next clock cycle.

Clocking

The dual-port SRAM blocks are only clocked on the rising

edge. SmartGen allows falling-edge-triggered clocks by

adding inverters to the netlist, hence achieving dual-port

SRAM blocks that are clocked on either edge (rising or

falling). For dual-port SRAM, each port can be clocked on

either edge and/or by separate clocks by port.

ProASIC3 devices support inversion (bubble pushing)

throughout the FPGA architecture, including the clock

input to the SRAM modules. Inversions added to the

SRAM clock pin on the design schematic or in the HDL

code will be automatically accounted for during design

compile without incurring additional delay in the clock

path.

The two-port SRAM can be clocked on the rising or

falling edge of WCLK and RCLK.

If negative-edge RAM and FIFO clocking is selected for

memory macros, clock edge inversion management

(bubble pushing) is automatically used within the

ProASIC3 development tools, without performance

penalty.

Modes of Operation

There are two read modes and one write mode:

• Read Nonpipelined (synchronous—1 clock edge):

In the standard read mode, new data is driven

onto the RD bus in the same clock cycle following

RA and REN valid. The read address is registered

on the read port clock active edge, and data

appears at RD after the RAM access time. Setting

PIPE to OFF enables this mode.

• Read Pipelined (synchronous—2 clock edges): The

pipelined mode incurs an additional clock delay

from address to data but enables operation at a

much higher frequency. The read address is

registered on the read port active clock edge, and

the read data is registered and appears at RD after

the second read clock edge. Setting PIPE to ON

enables this mode.

• Write (synchronous—1 clock edge): On the write

clock active edge, the write data is written into

the SRAM at the write address when WEN is high.

The setup times of the write address, write

enables, and write data are minimal with respect

to the write clock. Write and read transfers are

described with timing requirements in the "DDR

Module Specifications" section on page 3-64.

5. The A3P030 device does not support SRAM or FIFO.

Table 2-8 • Aspect Ratio Settings for WW[1:0]

WW[1:0] RW[1:0] D×W

01 01 512×9

10 10 256×18

00, 11 00, 11 Reserved

ProASIC®3/E Flash Family FPGAs

2-28 v2.1

RAM Initialization

Each SRAM block can be individually initialized on power-

up by means of the JTAG port using the UJTAG mechanism

(refer to the "JTAG 1532" section on page 2-55 and the

ProASIC3/E SRAM/FIFO Blocks application note). The shift

with the proper bit configuration to enable serial

loading. The 4,608 bits of data can be loaded in a single

operation.

Signal Descriptions for FIFO4K186

The following signals are used to configure the FIFO4K18

memory element:

WW and RW

These signals enable the FIFO to be configured in one of

the five allowable aspect ratios (Table 2-9).

WBLK and RBLK

These signals are active low and will enable the

respective ports when LOW. When the RBLK signal is

HIGH, that port’s outputs hold the previous value.

WEN and REN

Read and write enables. WEN is active low and REN is

active high by default. These signals can be configured as

active high or low.

WCLK and RCLK

These are the clock signals for the synchronous read and

write operations. These can be driven independently or

with the same driver.

RPIPE

This signal is used to specify pipelined read on the

output. A LOW on RPIPE indicates a nonpipelined read,

and the data appears on the output in the same clock

cycle. A HIGH indicates a pipelined read, and data

appears on the output in the next clock cycle.

RESET

This active low signal resets the control logic and forces

the output hold state registers to zero when asserted. It

does not reset the contents of the memory array

(Table 2-10).

While the RESET signal is active, read and write

operations are disabled. As with any asynchronous RESET

signal, care must be taken not to assert it too close to the

edges of active read and write clocks. Refer to the tables

beginning with Table 3-103 on page 3-88 for the

specifications.

This is the input data bus and is 18 bits wide. Not all 18

bits are valid in all configurations. When a data width

less than 18 is specified, unused higher-order signals

must be grounded (Table 2-10).

This is the output data bus and is 18 bits wide. Not all 18

bits are valid in all configurations. Like the WD bus, high-

order bits become unusable if the data width is less than

18. The output data on unused pins is undefined

(Table 2-10).

ESTOP, FSTOP

ESTOP is used to stop the FIFO read counter from further

counting once the FIFO is empty (i.e., the EMPTY flag

goes HIGH). A HIGH on this signal inhibits the counting.

FSTOP is used to stop the FIFO write counter from further

counting once the FIFO is full (i.e., the FULL flag goes

HIGH). A HIGH on this signal inhibits the counting.

For more information on these signals, refer to the

"ESTOP and FSTOP Usage" section on page 2-29.

FULL, EMPTY

When the FIFO is full and no more data can be written,

the FULL flag asserts HIGH. The FULL flag is synchronous

to WCLK to inhibit writing immediately upon detection

of a full condition and to prevent overflows. Since the

write address is compared to a resynchronized (and thus

time-delayed) version of the read address, the FULL flag

will remain asserted until two WCLK active edges after a

read operation eliminates the full condition.

When the FIFO is empty and no more data can be read,

the EMPTY flag asserts HIGH. The EMPTY flag is

6. The A3P030 device does not support SRAM or FIFO.

Table 2-9 • Aspect Ratio Settings for WW[2:0]

WW[2:0] RW[2:0] D×W

000 000 4k×1

001 001 2k×2

010 010 1k×4

011 011 512×9

100 100 256×18

101, 110, 111 101, 110, 111 Reserved

Table 2-10 • Input Data Signal Usage for Different Aspect

Ratios

D×W WD/RD Unused

4k×1 WD[17:1], RD[17:1]

2k×2 WD[17:2], RD[17:2]

1k×4 WD[17:4], RD[17:4]

512×9 WD[17:9], RD[17:9]

256×18 –

ProASIC®3/E Flash Family FPGAs

v2.1 2-29

synchronous to RCLK to inhibit reading immediately

upon detection of an empty condition and to prevent

underflows. Since the read address is compared to a

resynchronized (and thus time-delayed) version of the

write address, the EMPTY flag will remain asserted until

two RCLK active edges after a write operation removes

the empty condition.

For more information on these signals, refer to the "FIFO

Flag Usage Considerations" section on page 2-29.

AFULL, AEMPTY

These are programmable flags and will be asserted on

the threshold specified by AFVAL and AEVAL,

respectively.

When the number of words stored in the FIFO reaches

the amount specified by AEVAL while reading, the

AEMPTY output will go HIGH. Likewise, when the

number of words stored in the FIFO reaches the amount

specified by AFVAL while writing, the AFULL output will

go HIGH.

AFVAL, AEVAL

The AEVAL and AFVAL pins are used to specify the

almost-empty and almost-full threshold values. They are

12-bit signals. For more information on these signals,

refer to the "FIFO Flag Usage Considerations" section on

page 2-29.

ESTOP and FSTOP Usage

The ESTOP pin is used to stop the read counter from

counting any further once the FIFO is empty (i.e., the

EMPTY flag goes HIGH). Likewise, the FSTOP pin is used

to stop the write counter from counting any further once

the FIFO is full (i.e., the FULL flag goes HIGH).

The FIFO counters in the ProASIC3 device start the count

at zero, reach the maximum depth for the configuration

(e.g., 511 for a 512×9 configuration), and then restart at

zero. An example application for ESTOP, where the read

counter keeps counting, would be writing to the FIFO

once and reading the same content over and over

without doing another write.

FIFO Flag Usage Considerations

The AEVAL and AFVAL pins are used to specify the 12-bit

AEMPTY and AFULL threshold values. The FIFO contains

separate 12-bit write address (WADDR) and read address

(RADDR) counters. WADDR is incremented every time a

write operation is performed, and RADDR is incremented

every time a read operation is performed. Whenever the

difference between WADDR and RADDR is greater than

or equal to AFVAL, the AFULL output is asserted.

Likewise, whenever the difference between WADDR and

RADDR is less than or equal to AEVAL, the AEMPTY

output is asserted. To handle different read and write

aspect ratios, AFVAL and AEVAL are expressed in terms

of total data bits instead of total data words. When users

specify AFVAL and AEVAL in terms of read or write

words, the SmartGen tool translates them into bit

addresses and configures these signals automatically.

SmartGen configures the AFULL flag to assert when the

write address exceeds the read address by at least a

predefined value. In a 2k×8 FIFO, for example, a value of

1,500 for AFVAL means that the AFULL flag will be

asserted after a write when the difference between the

write address and the read address reaches 1,500 (there

have been at least 1,500 more writes than reads). It will

stay asserted until the difference between the write and

read addresses drops below 1,500.

The AEMPTY flag is asserted when the difference

between the write address and the read address is less

than a predefined value. In the example above, a value

of 200 for AEVAL means that the AEMPTY flag will be

asserted when a read causes the difference between the

write address and the read address to drop to 200. It will

stay asserted until that difference rises above 200. Note

that the FIFO can be configured with different read and

write widths; in this case the AFVAL setting is based on

the number of write data entries, and the AEVAL setting

is based on the number of read data entries. For aspect

ratios of 512×9 and 256×18, only 4,096 bits can be

addressed by the 12 bits of AFVAL and AEVAL. The

number of words must be multiplied by 8 and 16 instead

of 9 and 18. The SmartGen tool automatically uses the

proper values. To avoid halfwords being written or read,

which could happen if different read and write aspect

ratios are specified, the FIFO will assert FULL or EMPTY as

soon as at least a minimum of one word cannot be

written or read. For example, if a two-bit word is written

and a four-bit word is being read, the FIFO will remain in

the empty state when the first word is written. This

occurs even if the FIFO is not completely empty, because

in this case a complete word cannot be read. The same is

applicable in the full state. If a four-bit word is written

and a two-bit word is read, the FIFO is full and one word

is read. The FULL flag will remain asserted because a

complete word cannot be written at this point.

Refer to the ProASIC3/E SRAM/FIFO Blocks application

note for more information.

Advanced I/Os

Introduction

ProASIC3 devices feature a flexible I/O structure,

supporting a range of mixed voltages (1.5 V, 1.8 V, 2.5 V,

and 3.3 V) through a bank-selectable voltage. Table 2-11,

Table 2-12, and Table 2-19 on page 2-47 show the

voltages and the compatible I/O standards. I/Os provide

programmable slew rates (except A3P030), drive

strengths, and weak pull-up and pull-down circuits. 3.3 V

PCI and 3.3 V PCI-X are 5 V–tolerant. See the "5 V Input

Tolerance" section on page 2-39 for possible

implementations of 5 V tolerance.

ProASIC®3/E Flash Family FPGAs

2-30 v2.1

All I/Os are in a known state during power-up and any

power-up sequence is allowed without current impact.

Refer to the "I/O Power-Up and Supply Voltage

Thresholds for Power-On Reset (Commercial and

Industrial)" section on page 3-3 for more information.

During power-up, before reaching activation levels, the

I/O input and output buffers are disabled, while the

weak pull-up is enabled. Activation levels are described

in Table 3-2 on page 3-2.

I/O Tile

The ProASIC3 I/O tile provides a flexible, programmable

structure for implementing a large number of I/O

standards. In addition, the registers available in the I/O

tile in selected I/O banks can be used to support high-

performance register inputs and outputs, with register

enable if desired (Figure 2-24 on page 2-33). The

registers can also be used to support the JESD-79C

Double Data Rate (DDR) standard within the I/O

structure (see the "Double Data Rate (DDR) Support"

section on page 2-34 for more information).

As depicted in Figure 2-24 on page 2-33, all I/O registers

share one CLR port. The output register and output

enable register share one CLK port. Refer to the "I/O

Registers" section on page 2-33 for more information.

I/O Banks and I/O Standards Compatibility

I/Os are grouped into I/O voltage banks. There are four I/O

banks on the A3P250 through A3P1000. The A3P030,

A3P060, and A3P125 have two I/O banks. Each I/O voltage

bank has dedicated I/O supply and ground voltages

(VMV/GNDQ for input buffers and VCCI/GND for output

buffers). Because of these dedicated supplies, only I/Os

with compatible standards can be assigned to the same

I/O voltage bank. Table 2-12 shows the required voltage

compatibility values for each of these voltages.

For more information about I/O and global assignments

to I/O banks, refer to the specific pin table of the device

in the "Package Pin Assignments" section on page 4-1

and the "User I/O Naming Convention" section on

page 2-50.

I/O standards are compatible if their VCCI and VMV values

are identical. VMV and GNDQ are "quiet" input power

supply pins and are not used on A3P030.

Table 2-11 • ProASIC3 Supported I/O Standards

A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 A3P1000

Single-Ended

LVTTL/LVCMOS 3.3 V, LVCMOS 2.5 V / 1.8 V / 1.5 V,

LVCMOS 2.5/5.0 V

✓✓✓✓✓✓✓

3.3 V PCI/PCI-X – ✓✓✓✓✓✓

Differential

LVPECL, LVDS, BLVDS, M-LVDS – – – ✓✓✓✓

Table 2-12 • VCCI Voltages and Compatible ProASIC3 Standards

VCCI and VMV (typical) Compatible Standards

3.3 V LVTTL/LVCMOS 3.3, PCI 3.3, PCI-X 3.3 LVPECL

2.5 V LVCMOS 2.5, LVCMOS 2.5/5.0, LVDS, BLVDS, M-LVDS

1.8 V LVCMOS 1.8

1.5 V LVCMOS 1.5

ProASIC®3/E Flash Family FPGAs

v2.1 2-31

I/O Banks

ProASIC3 I/Os are divided into multiple technology

banks. The ProASIC3 family has two to four banks, and

the number of banks is device-dependent.

A3P030, A3P060, and A3P125 support two I/O banks,

whereas A3P400, A3P600, and A3P1000 support four I/O

banks. The bank types have different characteristics, such

as drive strength, the I/O standards supported, and timing

and power differences.

There are three types of banks in the ProASIC3 family:

Advanced I/O banks, Standard+ I/O banks, and Standard I/O

banks.

Advanced I/O banks offer single-ended and differential

capabilities. These banks are available on the east and

west sides of A3P250, A3P400, A3P600, and A3P1000

devices.

Standard+ I/O banks offer LVTTL/LVCMOS and PCI single-

ended I/O standards. These banks are available on the

north and south sides of A3P250, A3P400, A3P600 and

A3P1000 as well as all sides of A3P125 and A3P060.

Standard I/O banks offer LVTTL/LVCMOS single-ended I/O

standards. These banks are available on all sides of

A3P030 devices.

Table 2-13 shows the I/O bank types, the devices and

bank location supported, drive strength, slew rate

control, and the supported standards.

Table 2-13 • ProASIC3 Bank Types Definition and Differences

I/O Bank Type

Device and Bank

Location Drive Strength

Slew Rate

Control

I/O Standards Supported

LVTTL/

LVCMOS PCI/PCI-X

LVPECL, LVDS,

BLVDS, M-LVDS

Standard A3P030 (all banks) Refer to Ta bl e 2- 21

on page 2-48

Yes ✓Not Supported Not Supported

Standard+ A3P060 and A3P125 (all

banks)

Refer to Tab le 2 -2 2

on page 2-49

Yes ✓✓Not Supported

North and south banks of

A3P250 to A3P1000

devices

Refer to Tab le 2 -2 2

on page 2-49

Yes ✓✓Not Supported

Advanced East and west banks of

A3P250 to A3P1000

devices

Refer to Tab le 2 -2 3

on page 2-49

Yes ✓✓ ✓

ProASIC®3/E Flash Family FPGAs

2-32 v2.1

Features Supported on Every I/O

Table 2-14 lists all features supported by transmitter/receiver for single-ended and differential I/Os.

Table 2-14 • ProASIC3 I/O Features

Feature Description

Single-Ended Transmitter Features • Hot insertion:

– A3P030: Hot insertion in every mode

– All other ProASIC3 devices: No hot insertion

• Weak pull-up and pull-down

• 2 slew rates (except A3P030)

• Skew between output buffer enable/disable time: 2 ns delay

on rising edge and 0 ns delay on falling edge (see "Selectable

Skew between Output Buffer Enable/Disable Time" on page 2-

44 for more information)

• 3 drive strengths

• 5 V–tolerant receiver ("5 V Output Tolerance" section on

page 2-43)

• LVTTL/LVCMOS 3.3 V outputs compatible with 5 V TTL inputs

("5 V Output Tolerance" section on page 2-43)

• High performance (Table 2-15 on page 2-32)

Single-Ended Receiver Features • Electrostatic discharge (ESD) protection

• High performance (Table 2-15 on page 2-32)

• Separate ground plane for GNDQ pin and power plane for VMV

pin are used for input buffer to reduce output induced noise.

Differential Receiver Features (A3P250 through A3P1000) • ESD protection

• High performance (Table 2-15 on page 2-32)

• Separate ground plane for GNDQ pin and power plane for VMV

pin are used for input buffer to reduce output induced noise.

CMOS-Style LVDS, BLVDS, M-LVDS, or LVPECL Transmitter • Two I/Os and external resistors are used to provide a CMOS-

style LVDS, DDR LVDS, BLVDS, and M-LVDS/LVPECL transmitter

solution.

• Weak pull-up and pull-down

• High slew rate

Table 2-15 • Maximum I/O Frequency for Single-Ended and Differential I/Os in All Banks in ProASIC3 Devices (maximum

drive strength and high slew selected)

Specification Performance Up To

LVTTL/LVCMOS 3.3 V 200 MHz

LVCMOS 2.5 V 250 MHz

LVCMOS 1.8 V 200 MHz

LVCMOS 1.5 V 130 MHz

PCI 200 MHz

PCI-X 200 MHz

LVDS 350 MHz

LVPECL 350 MHz

ProASIC®3/E Flash Family FPGAs

v2.1 2-33

I/O Registers

Each I/O module contains several input, output, and enable registers. Refer to Figure 2-24 for a simplified

representation of the I/O block.

The number of input registers is selected by a set of switches (not shown in Figure 2-24) between registers to

implement single or differential data transmission to and from the FPGA core. The Designer software sets these

switches for the user.

A common CLR/PRE signal is employed by all I/O registers when I/O register combining is used. Input Register 2 does

not have a CLR/PRE pin, as this register is used for DDR implementation. The I/O register combining must satisfy certain

rules. For more information, refer to the ProASIC3/E I/O Usage Guide.

Note: ProASIC3 I/Os have registers to support DDR functionality (see the "Double Data Rate (DDR) Support" section on page 2-34 for

more information).

Figure 2-24 • I/O Block Logical Representation

Input

E = Enable Pin

PAD

OCE

ICE

Input

CLR/PRE

Pull-Up/Down

Resistor Control

Signal Drive Strength

and Slew-Rate Control

Output

To FPGA Core

From FPGA Core

Output

Enable

OCE

I/O / CLR or I/O / PRE / OCE

I/O / Q0

I/O / Q1

I/O / ICLK

I/O / D0

I/O / D1 / ICE

I/O / OCLK

I/O / OE

ProASIC®3/E Flash Family FPGAs

2-34 v2.1

Double Data Rate (DDR) Support

ProASIC3 devices support 350 MHz DDR inputs and

outputs. In DDR mode, new data is present on every

transition of the clock signal. Clock and data lines have

identical bandwidths and signal integrity requirements,

making them very efficient for implementing very high-

speed systems.

High-speed DDR interfaces can be implemented using

LVDS. The DDR feature is primarily implemented in the

FPGA core periphery and is not limited to any I/O

standard.

Input Support for DDR

The basic structure to support a DDR input is shown in

Figure 2-25. Three input registers are used to capture

incoming data, which is presented to the core on each

rising edge of the I/O register clock.

Each I/O tile on ProASIC3 devices supports DDR inputs.

Output Support for DDR

The basic DDR output structure is shown in Figure 2-26

on page 2-35. New data is presented to the output every

half clock cycle. Note: DDR macros and I/O registers do

not require additional routing. The combiner

automatically recognizes the DDR macro and pushes its

registers to the I/O register area at the edge of the chip.

The routing delay from the I/O registers to the I/O buffers

is already taken into account in the DDR macro.

Refer to the Actel application note Using DDR for

ProASIC3/E Devices for more information.

Figure 2-25 • DDR Input Register Support in ProASIC3 Devices

Input DDR

Data

CLK

CLKBUF

INBUF

Out_QF

(to core)

FF2

FF1

INBUF

CLR

DDR_IN

Out_QR

(to core)

ProASIC®3/E Flash Family FPGAs

v2.1 2-35

Hot-Swap Support

Hot-swapping (also called hot plugging) is the operation of hot insertion or hot removal of a card in or from a

powered-up system. The levels of hot-swap support and examples of related applications are described in Table 2-16

on page 2-36. The I/Os also need to be configured in hot insertion mode if hot plugging compliance is required. The

A3P030 device has an I/O structure that allows the support of Level 3 and Level 4 hot-swap with only two levels of

staging.

Figure 2-26 • DDR Output Support in ProASIC3 Devices

Data_F

(from core)

CLK

CLKBUF

Out

FF2

INBUF

CLR

DDR_OUT

Output DDR

FF1

OUTBUF

Data_R

(from core)

ProASIC®3/E Flash Family FPGAs

2-36 v2.1

Table 2-16 • Levels of Hot-Swap Support

Hot-

Swapping

Level Description

Power

Applied

to Device Bus State

Card

Ground

Connection

Device

Circuitry

Connected

to Bus Pins

Example of

Application with

Cards that Contain

ProASIC3 Devices

Compliance of

ProASIC3 Devices

1 Cold-swap No – – – System and card with

Actel FPGA chip are

powered down and the

card is plugged into the

system. Then the power

supplies are turned on for

the system but not for the

FPGA on the card.

A3P030: Compliant

Other ProASIC3 devices:

Compliant if the bus

switch is used to isolate

FPGA I/Os from the rest

of the system.

2 Hot-swap while

reset

Yes Held in reset

state

Must be made

and

maintained

for 1 ms

before,

during, and

after

insertion/

removal

– In PCI hot-plug

specification, reset control

circuitry isolates the card

busses until the card

supplies are at their

nominal operating levels

and stable.

A3P030: Compliant I/Os

can but do not have to

be set to hot insertion

mode.

Other ProASIC3 devices:

Compliant

3 Hot-swap while

bus idle

Yes Held idle (no

ongoing I/O

processes

during

insertion/

removal)

Same as Level

Must remain

glitch-free

during

power-up or

power-down

Board bus shared with

card bus is "frozen," and

there is no toggling

activity on the bus. It is

critical that the logic states

set on the bus signal are

not disturbed during card

insertion/removal.

A3P030: Compliant with

2 levels of staging (first-

GND, second-all other

pins)

Other ProASIC3 devices:

Compliant:

Option 1 – 2 levels of

staging (first: GND and

second: all other pins)

together with bus switch

on the I/Os

Option 2 – 3 levels of

staging (first: GND

second: supplies, third:

all other pins)

4 Hot-swap on

an active bus

Yes Bus may have

active I/O

processes

ongoing, but

device being

inserted or

removed

must be idle.

Same as Level

Same as

Level 3

There is activity on the

system bus, and it is

critical that the logic states

set on the bus signal are

not disturbed during card

insertion/removal.

A3P030: Compliant with

2 levels of staging (first-

GND, second-all other

pins)

Other ProASIC3 devices:

Compliant:

Option 1 – 2 levels of

staging (first: GND and

second: all other pins)

together with bus switch

on the I/Os

Option 2 – 3 levels of

staging (first: GND

second: supplies, third:

all other pins)

ProASIC®3/E Flash Family FPGAs

v2.1 2-37

For boards and cards with three levels of staging, card

power supplies must have time to reach their final value

before the I/Os are connected. Pay attention to the sizing

of power supply decoupling capacitors on the card to

ensure that the power supplies are not overloaded with

capacitance.

Cards with three levels of staging should have the

following sequence:

• Grounds

•Powers

• I/Os and other pins

For Level 3 and Level 4 compliance with the A3P030

device, cards with two levels of staging should have the

following sequence:

• Grounds

• Powers, I/Os, and other pins

Cold-Sparing Support

Cold-sparing means that a subsystem with no power

applied (usually a circuit board) is electrically connected

to the system that is in operation. This means that all

input buffers of the subsystem must present very high

input impedance with no power applied so as not to

disturb the operating portion of the system.

The A3P030 device fully supports cold-sparing, since the I/O

clamp diode is always off (see Table 2-13 on page 2-31).

For other ProASIC3 devices, since the I/O clamp diode is

always active, cold-sparing can be accomplished either by

employing a bus switch to isolate the device I/Os from the

rest of the system or by driving each ProASIC3 I/O pin to

0V.

If the A3P030 is used in applications requiring cold-

sparing, a discharge path from the power supply to

ground should be provided. This can be done with a

discharge resistor or a switched resistor. This is necessary

because the A3P030 does not have built-in I/O clamp

diodes.

If the resistor is chosen, the resistor value must be

calculated based on decoupling capacitance on a given

power supply on the board (this decoupling capacitor is

in parallel with the resistor). The RC time constant should

ensure full discharge of supplies before cold-sparing

functionality is required. The resistor is necessary to

ensure that the power pins are discharged to ground

every time there is an interruption of power to the

device.

Electrostatic Discharge (ESD) Protection

ProASIC3 devices are tested per JEDEC Standard

JESD22-A114-B.

ProASIC3 devices contain clamp diodes at every I/O,

global, and power pad. Clamp diodes protect all device

pads against damage from ESD as well as from excessive

voltage transients.

ProASIC3 devices are tested to the following models: the

Human Body Model (HBM) with a tolerance of 2,000 V,

the Machine Model (MM) with a tolerance of 250 V, and

the Charged Device Model (CDM) with a tolerance of

200 V.

Each I/O has two clamp diodes. One diode has its

positive (P) side connected to the pad and its negative

(N) side connected to VCCI. The second diode has its P

side connected to GND and its N side connected to the

pad. During operation, these diodes are normally

biased in the off state, except when transient voltage is

significantly above VCCI or below GND levels.

In A3P030, the first diode is always off. On other

ProASIC3 devices, the clamp diode is always on and

cannot be switched off.

By selecting the appropriate I/O configuration, the diode

is turned on or off. Refer to Table 2-17 on page 2-38 for

more information about the I/O standards and the clamp

diode.

The second diode is always connected to the pad,

regardless of the I/O configuration selected.

ProASIC®3/E Flash Family FPGAs

2-38 v2.1

Table 2-17 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in ProASIC3 Devices

I/O Assignment

Clamp Diode1Hot Insertion 5 V Input Tolerance2

Input

Buffer

Output

BufferA3P030

Other

ProASIC3

Devices A3P030

Other

ProASIC3

Devices3A3P030

Other

ProASIC3

Devices

3.3 V LVTTL/LVCMOS No Yes Yes Yes Yes2Yes2Enabled/Disabled

3.3 V PCI, 3.3 V PCI-X N/A Yes N/A Yes N/A Yes2Enabled/Disabled

LVCMOS 2.5 V 5No Yes Yes Yes Yes2Yes4Enabled/Disabled

LVCMOS 2.5 V / 5.0 V 6N/A Yes N/A Yes N/A Yes4Enabled/Disabled

LVCMOS 1.8 V No Yes Yes Yes No No Enabled/Disabled

LVCMOS 1.5 V No Yes Yes Yes No No Enabled/Disabled

Differential,

LVDS/BLVDS/M-LVDS/

LVPECL

N/A Yes N/A Yes N/A No Enabled/Disabled

Notes:

1. The clamp diode is always off for the A3P030 device and always active for other ProASIC3 devices.

2. Can be implemented with an external IDT bus switch, resistor divider, or Zener with resistor.

3. Refer to Table 2-16 on page 2-36 for device-compliant information.

4. Can be implemented with an external resistor and an internal clamp diode.

5. The LVCMOS 2.5 V I/O standard is supported by the A3P030 device only. In the SmartGen Core Reference Guide, select the

LVCMOS25 macro for LVCMOS 2.5 V I/O standard support for the A3P030 device.

6. The LVCMOS 2.5 V / 5.0 V I/O standard is supported by all ProASIC3 devices except A3P030. In the SmartGen Core Reference

Guide, select the LVCMOS5 macro for LVCMOS 2.5 V / 5.0 V I/O standard support for all ProASIC3 devices except A3P030.

ProASIC®3/E Flash Family FPGAs

v2.1 2-39

5 V Input Tolerance

I/Os can support 5-V input tolerance when LVTTL 3.3 V,

LVCMOS 3.3 V, LVCMOS 2.5 V and LVCMOS 2.5 V / 5.0 V

configurations are used (see Table 2-17 on page 2-38 for

more details). There are four recommended solutions for

achieving 5 V receiver tolerance (see Figure 2-27 to

Figure 2-30 on page 2-42 for details of board and macro

setups). All the solutions meet a common requirement of

limiting the voltage at the input to 3.6 V or less. In fact,

the I/O absolute maximum voltage rating is 3.6 V, and

any voltage above 3.6 V may cause long-term gate oxide

failures.

Solution 1

The board-level design must ensure that the reflected

waveform at the pad does not exceed the limits provided

in Table 3-2 on page 3-2. This is a requirement to ensure

long-term reliability.

This scheme will also work for a 3.3 V PCI/ PCI-X

configuration, but the internal diode should not be used for

clamping, and the voltage must be limited by the two

external resistors as explained below. Relying on the

diode clamping would create an excessive pad DC

voltage of 3.3 V + 0.7 V = 4 V.

Here are some examples of possible resistor values

(based on a simplified simulation model with no line

effects and 10 Ω transmitter output resistance, where

Rtx_out_high = (VCCI – VOH) / IOH, Rtx_out_low = VOL / IOL).

Example 1 (high speed, high current):

Rtx_out_high = Rtx_out_low = 10 Ω

R1 = 36 Ω (±5%), P(r1)min = 0.069 Ω

R2 = 82 Ω (±5%), P(r2)min = 0.158 Ω

Imax_tx = 5.5 V / (82 × 0.95 + 36 × 0.95 + 10) = 45.04 mA

tRISE = tFALL = 0.85 ns at C_pad_load = 10 pF (includes up

to 25% safety margin)

tRISE = tFALL = 4 ns at C_pad_load = 50 pF (includes up to

25% safety margin)

Example 2 (low–medium speed, medium current):

Rtx_out_high = Rtx_out_low = 10 Ω

R1 = 220 Ω (±5%), P(r1)min = 0.018 Ω

R2 = 390 Ω (±5%), P(r2)min = 0.032 Ω

Imax_tx = 5.5 V / (220 × 0.95 + 390 × 0.95 + 10) = 9.17 mA

tRISE = tFALL = 4 ns at C_pad_load = 10 pF (includes up to

25% safety margin)

tRISE = tFALL = 20 ns at C_pad_load = 50 pF (includes up to

25% safety margin)

Other values of resistors are also allowed as long as the

resistors are sized appropriately to limit the voltage at

the receiving end to 2.5 V < Vin (rx) < 3.6 V* when the

transmitter sends a logic 1. This range of Vin_dc (rx) must

be assured for any combination of transmitter supply

(5 V ± 0.5 V), transmitter output resistance, and board

resistor tolerances.

Temporary overshoots are allowed according to Table 3-4

on page 3-2.

Figure 2-27 • ProASIC3 Solution 1

Solution 1

5.5 V 3.3 V

Requires two board resistors,

LVCMOS 3.3 V I/Os

ProASIC3 I/O Input

Rext1

Rext2

ProASIC®3/E Flash Family FPGAs

2-40 v2.1

Solution 2

The board-level design must ensure that the reflected waveform at the pad does not exceed limits provided in Table 3-4

on page 3-2. This is a requirement to ensure long-term reliability.

This scheme will also work for a 3.3 V PCI/PCIX configuration, but the internal diode should not be used for clamping,

and the voltage must be limited by the external resistors and Zener, as shown in Figure 2-28. Relying on the diode

clamping would create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V.

Figure 2-28 • ProASIC3 Solution 2

Solution 2

5.5 V 3.3 V

Requires one board resistor, one

Zener 3.3 V diode, LVCMOS 3.3 V I/Os

ProASIC3 I/O Input

Rext1

Zener

3.3 V

ProASIC®3/E Flash Family FPGAs

v2.1 2-41

Solution 3

The board-level design must ensure that the reflected waveform at the pad does not exceed limits provided in Table 3-4

on page 3-2. This is a requirement to ensure long-term reliability.

This scheme will also work for a 3.3 V PCI/PCI-X configuration, but the internal diode should not be used for clamping,

and the voltage must be limited by the bus switch, as shown in Figure 2-29. Relying on the diode clamping would

create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V.

Figure 2-29 • ProASIC3 Solution 3

Solution 3

Requires a bus switch on the board,

LVTTL/LVCMOS 3.3 V I/Os.

ProASIC3 I/O Input

3.3 V

5.5 V

Bus

Switch

IDTQS32X23

ProASIC®3/E Flash Family FPGAs

2-42 v2.1

Solution 4

Figure 2-30 • ProASIC3 Solution 4

Table 2-18 • Comparison Table for 5 V–Compliant Receiver Scheme

Scheme Board Components Speed Current Limitations

1 Two resistors Low to High1Limited by transmitter's drive strength

2 Resistor and Zener 3.3 V Medium Limited by transmitter's drive strength

3 Bus switch High N/A

4 Minimum resistor value2, 3, 4, 5

• R = 47 Ω at TJ = 70°C

• R = 150 Ω at TJ = 85°C

• R = 420 Ω at TJ = 100°C

Medium Maximum diode current at 100% duty cycle, signal constantly at '1'

• 52.7 mA at TJ = 70°C / 10-year lifetime

• 16.5 mA at TJ = 85°C / 10-year lifetime

• 5.9 mA at TJ = 100°C / 10-year lifetime

For duty cycles other than 100%, the currents can be increased by

a factor of 1 / duty cycle.

Example: 20% duty cycle at 70°C

Maximum current = (1 / 0.2) × 52.7 mA = 5 × 52.7 mA = 263.5 mA

Notes:

1. Speed and current consumption increase as the board resistance values decrease.

2. Resistor values ensure I/O diode long-term reliability.

3. At 70°C, customers could still use 420

on every I/O.

4. At 85°C, a 5 V solution on every other I/O is permitted, since the resistance is lower (150

) and the current is higher. Also, the

designer can still use 420

and use the solution on every I/O.

5. At 100°C, the 5 V solution on every I/O is permitted, since 420

are used to limit the current to 5.9 mA.

Solution 4

2.5 V

5.5 V On-Chip

Clamp

Diode

2.5 V

Requires one board resistor.

Available for all I/O standards

excluding 3.3 V I/O standards

(not supported for A3P030 device).

ProASIC3 I/O Input

Rext

ProASIC®3/E Flash Family FPGAs

v2.1 2-43

5 V Output Tolerance

ProASIC3 I/Os must be set to 3.3 V LVTTL or 3.3 V LVCMOS

mode to reliably drive 5 V TTL receivers. It is also critical

that there be NO external I/O pull-up resistor to 5 V, since

this resistor would pull the I/O pad voltage beyond the

3.6 V absolute maximum value, and consequently cause

damage to the I/O.

When set to 3.3 V LVTTL or 3.3 V LVCMOS mode,

ProASIC3 I/Os can directly drive signals into 5 V TTL

receivers. In fact, VOL = 0.4 V and VOH = 2.4 V in both

3.3 V LVTTL and 3.3 V LVCMOS modes exceeds the

VIL =0.8V and V

IH = 2 V level requirements of 5 V TTL

receivers. Therefore, level '1' and level '0' will be

recognized correctly by 5 V TTL receivers.

Simultaneous Switching Outputs (SSOs)

and Printed Circuit Board Layout

SSOs can cause signal integrity problems on adjacent

signals that are not part of the SSO bus. Both inductive

and capacitive coupling parasitics of bond wires inside

packages and of traces on PCBs will transfer noise from

SSO busses onto signals adjacent to those busses.

Additionally, SSOs can produce ground bounce noise and

VCCI dip noise. These two noise types are caused by

rapidly changing currents through GND and VCCI

package pin inductances during switching activities

(EQ 2-1 and EQ 2-2).

Ground bounce noise voltage = L(GND) × di/dt

EQ 2-1

VCCI dip noise voltage = L(VCCI) × di/dt

EQ 2-2

Any group of four or more input pins switching on the

same clock edge is considered an SSO bus. The shielding

should be done both on the board and inside the

package unless otherwise described.

In-package shielding can be achieved in several ways; the

required shielding will vary depending on whether pins

next to the SSO bus are LVTTL/LVCMOS inputs,

LVTTL/LVCMOS outputs, or GTL/SSTL/HSTL/LVDS/LVPECL

inputs and outputs. Board traces in the vicinity of the

SSO bus have to be adequately shielded from mutual

coupling and inductive noise that can be generated by

the SSO bus. Also, noise generated by the SSO bus needs

to be reduced inside the package.

PCBs perform an important function in feeding stable

supply voltages to the IC and, at the same time,

maintaining signal integrity between devices.

Key issues that need to considered are as follows:

• Power and ground plane design and decoupling

network design

• Transmission line reflections and terminations

ProASIC®3/E Flash Family FPGAs

2-44 v2.1

Selectable Skew between Output Buffer Enable/Disable Time

The configurable skew block is used to delay the output buffer assertion (enable) without affecting deassertion

(disable) time.

Figure 2-31 • Block Diagram of Output Enable Path

Figure 2-32 • Timing Diagram (option 1: bypasses skew circuit)

Figure 2-33 • Timing Diagram (option 2: enables skew circuit)

ENABLE (OUT)

Skew Circuit

Output Enable

(from FPGA core)

I/O Output

Buffers

ENABLE (IN)

MUX

Skew Select

ENABLE (IN)

ENABLE (OUT)

Less than

0.1 ns

Less than

0.1 ns

ENABLE (IN)

ENABLE (OUT)

1.2 ns

(typical)

Less than

0.1 ns

ProASIC®3/E Flash Family FPGAs

v2.1 2-45

At the system level, the skew circuit can be used in applications where transmission activities on bidirectional data

lines need to be coordinated. This circuit, when selected, provides a timing margin that can prevent bus contention

and subsequent data loss and/or transmitter over-stress due to transmitter-to-transmitter current shorts. Figure 2-34

presents an example of the skew circuit implementation in a bidirectional communication system. Figure 2-35 shows

how bus contention is created, and Figure 2-36 on page 2-46 shows how it can be avoided with the skew circuit.

Figure 2-34 • Example of Implementation of Skew Circuits in Bidirectional Transmission Systems Using ProASIC3 Devices

Figure 2-35 • Timing Diagram (bypasses skew circuit)

Transmitter 1: ProASIC3 I/O Transmitter 2: Generic I/O

ENABLE(t2)

EN (b1) EN (b2)

Routing

Delay (t1)

Routing

Delay (t2)

EN (r1)

ENABLE (t1)

Skew or

Bypass

Skew

Bidirectional Data Bus

Transmitter

ENABLE/

DISABLE

EN (b1)

EN (b2)

ENABLE (r1)

Transmitter 1: ON

ENABLE (t2)

Transmitter 2: ON

ENABLE (t1)

Bus

Contention

Transmitter 1: OFF Transmitter 1: OFF

Transmitter 2: OFF

ProASIC®3/E Flash Family FPGAs

2-46 v2.1

Figure 2-36 • Timing Diagram (with skew circuit selected)

EN (b1)

EN (b2)

Transmitter 1: ON

ENABLE (t2)

Transmitter 2: ON Transmitter 2: OFF

ENABLE (t1)

Result: No Bus Contention

Transmitter 1: OFF Transmitter 1: OFF

ProASIC®3/E Flash Family FPGAs

v2.1 2-47

I/O Software Support

In the ProASIC3 development software, default settings

have been defined for the various I/O standards

supported. Changes can be made to the default settings

via the use of attributes; however, not all I/O attributes

are applicable for all I/O standards. Table 2-19 lists the

valid I/O attributes that can be manipulated by the user

for each I/O standard.

Single-ended I/O standards in ProASIC3 support up to

five different drive strengths.

Table 2-19 • ProASIC3 I/O Attributes vs. I/O Standard Applications

I/O Standards

SLEW

(output

only)

OUT_DRIVE

(output

only)

SKEW

(all macros

with OE)* RES_PULL

OUT_LOAD

(output

only) COMBINE_REGISTER

LVTTL/LVCMOS 3.3 V ✓✓✓✓✓ ✓

LVCMOS 2.5 V ✓✓✓✓✓ ✓

LVCMOS 2.5/5.0 V ✓✓✓✓✓ ✓

LVCMOS 1.8 V ✓✓✓✓✓ ✓

LVCMOS 1.5 V ✓✓✓✓✓ ✓

PCI (3.3 V) ✓✓✓

PCI-X (3.3 V) ✓✓✓✓

LVDS, BLVDS, M-LVDS ✓✓

LVPECL ✓

Note: *Applies to all ProASIC3 devices except A3P030.

ProASIC®3/E Flash Family FPGAs

2-48 v2.1

Table 2-20 lists the default values for the above selectable I/O attributes as well as those that are preset for that I/O

standard. See Table 2-21 for SLEW and OUT_DRIVE settings.

Weak Pull-Up and Weak Pull-Down Resistors

ProASIC3 devices support optional weak pull-up and

pull-down resistors per I/O pin. When the I/O is pulled up,

it is connected to the VCCI of its corresponding I/O bank.

When it is pulled down, it is connected to GND. Refer to

Table 3-21 on page 3-18 for more information.

Slew Rate Control and Drive Strength

ProASIC3 devices support output slew rate control: high

and low. Actel recommends the high slew rate option to

minimize the propagation delay. This high-speed option

may introduce noise into the system if appropriate signal

integrity measures are not adopted. Selecting a low slew

rate reduces this kind of noise but adds some delays in

the system. Low slew rate is recommended when bus

transients are expected. Drive strength should also be

selected according to the design requirements and noise

immunity of the system.

The output slew rate and multiple drive strength

controls are available in LVTTL/LVCMOS 3.3 V, LVCMOS

2.5 V, LVCMOS 2.5 V / 5.0 V input, LVCMOS 1.8 V, and

LVCMOS 1.5 V. All other I/O standards have a high output

slew rate by default.

For A3P030, refer to Table 2-21; for other ProASIC3

devices, refer to Table 2-22 and Table 2-23 on page 2-49

for more information about the slew rate and drive

strength specification.

Table 2-20 • ProASIC3 I/O Default Attributes

I/O Standards

SLEW

(output only)

OUT_DRIVE

(output only)

SKEW

(tribuf and

bibuf only) RES_PULL

OUT_LOAD

(output

only) COMBINE_REGISTER

LVTTL/LVCMOS 3.3 V See Table 2-21

on page 2-48

See Table 2-21

on page 2-48

Off None 35 pF –

LVCMOS 2.5 V Off None 35 pF –

LVCMOS 2.5/5.0 V Off None 35 pF –

LVCMOS 1.8 V Off None 35 pF –

LVCMOS 1.5 V Off None 35 pF –

PCI (3.3 V) Off None 10 pF –

PCI-X (3.3 V) Off None 10 pF –

LVDS, BLVDS, M-LVDS Off None 0 pF –

LVPECL Off None 0 pF –

Table 2-21 • ProASIC3 Output Drive (OUT_DRIVE) for Standard I/O Bank Type (A3P030 device)

I/O Standards

OUT_DRIVE (mA)

Slew2468

LVTTL/LVCMOS 3.3 V ✓✓✓✓High Low

LVCMOS 2.5 V ✓✓✓✓High Low

LVCMOS 1.8 V ✓✓ ––HighLow

LVCMOS 1.5 V ✓–––HighLow

Note: Refer to Table 2-13 on page 2-31 for I/O bank type definition.

ProASIC®3/E Flash Family FPGAs

v2.1 2-49

Table 2-22 • ProASIC3 Output Drive for Standard+ I/O Bank Type

I/O Standards 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Slew

LVTTL ✓✓✓✓✓✓High Low

LVCMOS 3.3 V ✓✓✓✓✓✓High Low

LVCMOS 2.5 V ✓✓✓✓✓ –HighLow

LVCMOS 1.8 V ✓✓✓✓ ––HighLow

LVCMOS 1.5 V ✓✓ ––––High Low

Notes:

1. There will be a difference in timing between the Standard+ I/O banks when compared to the Advanced I/O banks (Tabl e 2-2 3).

Refer to the I/O timing tables beginning on page 3-28 and Table 2-11 on page 2-30 for the standards supported for each device.

2. Refer to Table 2-13 on page 2-31 for I/O bank type definition.

Table 2-23 • ProASIC3 Output Drive for Advanced I/O Bank Type

I/O Standards 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Slew

LVTTL ✓✓✓✓✓✓✓High Low

LVCMOS 3.3 V ✓✓✓✓✓✓✓High Low

LVCMOS 2.5 V ✓✓✓✓✓✓✓High Low

LVCMOS 2.5/5.0 V ✓✓✓✓✓✓✓High Low

LVCMOS 1.8 V ✓✓✓✓✓✓ – High Low

LVCMOS 1.5 V ✓✓✓✓✓ ––HighLow

Notes:

1. There will be a difference in timing between the Advanced I/O banks when compared to the Standard+ I/O banks (Table 2-2 3).

Refer to the I/O timing tables beginning on page 3-28 and Table 2-11 on page 2-30 for the standards supported for each device.

2. Refer to Table 2-13 on page 2-31 for I/O bank type definition.

ProASIC®3/E Flash Family FPGAs

2-50 v2.1

User I/O Naming Convention

Due to the comprehensive and flexible nature of ProASIC3 device user I/Os, a naming scheme is used to show the

details of the I/O (Figure 2-37 and Figure 2-38 on page 2-51). The name identifies to which I/O bank it belongs, as well

as the pairing and pin polarity for differential I/Os.

I/O Nomenclature = Gmn/IOuxwBy

Gmn is only used for I/Os that also have CCC access—i.e., global pins.

G=Global

m = Global pin location associated with each CCC on the device: A (northwest corner), B (northeast corner), C (east

middle), D (southeast corner), E (southwest corner), and F (west middle)

n = Global input MUX and pin number of the associated Global location m, either A0, A1, A2, B0, B1, B2, C0, C1, or

C2. Figure 2-15 on page 2-18 shows the three input pins per clock source MUX at CCC location m.

u = I/O pair number in the bank, starting at 00 from the northwest I/O bank and proceeding in a clockwise direction

x = P (Positive) or N (Negative) for differential pairs, or R (Regular—single-ended) for the I/Os that support single-

ended and voltage-referenced I/O standards only. U (Positive-LVDS, DDR LVDS, BLVDS, and M-LVDS only) or V

(Negative-LVDS, DDR LVDS, BLVDS, and M-LVDS only) restrict the I/O differential pair from being selected as an

LVPECL pair.

w = D (Differential Pair), P (Pair), or S (Single-Ended). D (Differential Pair) if both members of the pair are bonded

out to adjacent pins or are separated only by one GND or NC pin; P (Pair) if both members of the pair are

bonded out but do not meet the adjacency requirement; or S (Single-Ended) if the I/O pair is not bonded out.

For Differential (D) pairs, adjacency for ball grid packages means only vertical or horizontal. Diagonal

adjacency does not meet the requirements for a true differential pair.

B = Bank

y = Bank number (0–3). The Bank number starts at 0 from the northwest I/O bank and proceeds in a clockwise

direction.

Note: The A3P030 device does not support a PLL (VCOMPLF and VCCPLF pins).

Figure 2-37 • Naming Conventions of ProASIC3 Devices with Two I/O Banks – Top View

CCC

"A"

CCC

"E"

CCC/PLL

"F"

CCC

"B"

CCC

"D"

CCC

"C"

A3P030

A3P060

A3P125

GND

VCC

GND

VCCIB1

VCC

GND

VCCIB0

Bank 1

Bank 0

Bank 1

Bank 0

VCOMPLF

VCCPLF

GND

VCC

VCCIB1

GND

VCC

VCCIB0

GND

VMV1

GNDQ

GND

VCCIB1

VCC

VCCIB1

VCC

GND

VMV1

GNDQ

GND

TCK

TDI

TMS

VJTAG

TRST

TDO

VPUMP

GND

GNDQ

VMV0

GND

Vcc

GND

VCCIB0

Vcc

VCCIB0

GND

VMV0

GNDQ

ProASIC®3/E Flash Family FPGAs

v2.1 2-51

Figure 2-38 • Naming Conventions of ProASIC3 Devices with Four I/O Banks – Top View

A3P250

A3P400

A3P600

A3P1000

GND

Vcc

GND

VCCIB3 Bank 3

Bank 3

Bank 1

Bank 2

Bank 0

VCOMPLF

VCCPLF

GND

VCC

VCCIB3

GND

VMV3

GNDQ

GND

VCCIB2

VCC

VCCIB2

VCC

GND

VMV2

GNDQ

GND

TCK

TDI

TMS

VJTAG

TRST

TDO

VPUMP

GND

VCC

VCCIB1

GND

VCC

GND

VCCIB1

GND

GNDQ

VMV1

VCC

VCCIB0

GND

VCC

VCCIB0

GND

VCCIB0

GND

VMV0

GNDQ

CCC

"A"

CCC

"E"

CCC/PLL

"F"

CCC

"B"

CCC

"D"

CCC

"C"

ProASIC®3/E Flash Family FPGAs

2-52 v2.1

Pin Descriptions

Supply Pins

GND Ground

Ground supply voltage to the core, I/O outputs, and I/O

logic.

GNDQ Ground (quiet)

Quiet ground supply voltage to input buffers of I/O

banks. Within the package, the GNDQ plane is

decoupled from the simultaneous switching noise

originated from the output buffer ground domain. This

minimizes the noise transfer within the package, and

improves input signal integrity. GNDQ must always be

connected to GND on the board.

VCC Core Supply Voltage

Supply voltage to the FPGA core, nominally 1.5 V. VCC is

required for powering the JTAG state machine in

addition to VJTAG. Even when a ProASIC3 device is in

bypass mode in a JTAG chain of interconnected devices,

both VCC and VJTAG must remain powered to allow JTAG

signals to pass through the ProASIC3 device.

VCCIBx I/O Supply Voltage

Supply voltage to the bank's I/O output buffers and I/O

logic. Bx is the I/O bank number. There are eight I/O

banks on ProASIC3 devices plus a dedicated VJTAG bank.

Each bank can have a separate VCCI connection. All I/Os

in a bank will run off the same VCCIBx supply. VCCI can be

1.5 V, 1.8 V, 2.5 V, or 3.3 V nominal voltage. Unused I/O

banks should have their corresponding VCCI pins tied to

GND.

VMVx I/O Supply Voltage (quiet)

Quiet supply voltage to the input buffers of each I/O

bank. x is the bank number. Within the package, the

VMV plane is decoupled from the simultaneous

switching noise originated from the output buffer VCCI

domain. This minimizes the noise transfer within the

package and improves input signal integrity. Each bank

must have at least one VMV connection and no VMV

should be left unconnected. All I/Os in a bank run off the

same VMVx supply. VMV is used to provide a quiet supply

voltage to the input buffers of each I/O bank. VMVx can

be 1.5 V, 1.8 V, 2.5 V, or 3.3 V nominal voltage. Unused I/O

banks should have their corresponding VMV pins tied to

GND. VMV and VCCI should be at the same voltage within

a given I/O bank. Used VMV pins must be connected to

the corresponding VCCI pins of the same bank (i.e., VMV0

to VCCIB0, VMV1 to VCCIB1, etc.).

VCCPLF PLL Supply Voltage7

Supply voltage to analog PLL, nominally 1.5 V. If unused,

VCCPLF should be tied to either the power supply or GND.

Refer to the PLL application note for a complete board

solution for the PLL analog power supply and ground.

VCOMPLF PLL Ground7

Ground to analog PLL power supplies. Unused VCOMPLF

pins should be connected to GND.

VJTAG JTAG Supply Voltage

ProASIC3 devices have a separate bank for the dedicated

JTAG pins. The JTAG pins can be run at any voltage from

1.5 V to 3.3 V (nominal). Isolating the JTAG power supply

in a separate I/O bank gives greater flexibility in supply

selection and simplifies power supply and PCB design. If

the JTAG interface is neither used nor planned for use,

the VJTAG pin together with the TRST pin could be tied to

GND. It should be noted that VCC is required to be

powered for JTAG operation; VJTAG alone is insufficient. If

a ProASIC3device is in a JTAG chain of interconnected

boards, the board containing the ProASIC3 device can be

powered down, provided both VJTAG and VCC to the

ProASIC3 part remain powered; otherwise, JTAG signals

will not be able to transition the ProASIC3 device, even

in bypass mode.

VPUMP Programming Supply Voltage

ProASIC3 devices support single-voltage ISP

programming of the configuration Flash and FlashROM.

For programming, VPUMP should be 3.3 V nominal.

During normal device operation, VPUMP can be left

floating or can be tied (pulled up) to any voltage

between 0 V and 3.6 V. Programming power supply

voltage (VPP) range is 3.3 V +/- 5%.

When the VPUMP pin is tied to ground, it will shut off the

charge pump circuitry, resulting in no sources of

oscillation from the charge pump circuitry.

For proper programming, 0.01 µF and 0.33 µF capacitors

(both rated at 16 V) are to be connected in parallel across

VPUMP and GND, and positioned as close to the FPGA pins

as possible.

User Pins

I/O User Input/Output

The I/O pin functions as an input, output, tristate, or

bidirectional buffer. Input and output signal levels are

compatible with the I/O standard selected.

During programming, I/Os become tristated and weakly

pulled up to VCCI. With VCCI, VMV, and VCC supplies

continuously powered up, when the device transitions

7. The A3P030 device does not support this feature.

ProASIC®3/E Flash Family FPGAs

v2.1 2-53

from programming to operating mode, the I/Os are

instantly configured to the desired user configuration.

Unused I/Os are configured as follows:

• Output buffer is disabled (with tristate value of high

impedance)

• Input buffer is disabled (with tristate value of high

impedance)

• Weak pull-up is programmed

GL Globals

GL I/Os have access to certain clock conditioning circuitry

(and the PLL) and/or have direct access to the global

network (spines). Additionally, the global I/Os can be

used as I/Os, since they have identical capabilities.

Unused GL pins are configured as inputs with pull-up

resistors. See more detailed descriptions of global I/O

connectivity in the "Clock Conditioning Circuits" section

on page 2-15. All inputs labeled GC/GF are direct inputs

into the quadrant clocks. For example, if GAA0 is used

for an input, GAA1 and GAA2 are no longer available for

input to the quadrant globals. All inputs labeled GC/GF

are direct input into the chip level globals and the rest

are connected to the quadrant globals. The inputs to the

global network are multiplexed and only one input can

be used as a global input.

Refer to the "User I/O Naming Convention" section on

page 2-50 for a explanation of the naming of global

pins.

JTAG Pins

ProASIC3 devices have a separate bank for the dedicated

JTAG pins. The JTAG pins can be run at any voltage from

1.5 V to 3.3 V (nominal). VCC must also be powered for

the JTAG state machine to operate, even if the device is

in bypass mode; VJTAG alone is insufficient. Both VJTAG

and VCC to the ProASIC3 part must be supplied to allow

JTAG signals to transition the ProASIC3 device. Isolating

the JTAG power supply in a separate I/O bank gives

greater flexibility in supply selection and simplifies

power supply and PCB design. If the JTAG interface is

neither used nor planned for use, the VJTAG pin together

with the TRST pin could be tied to GND.

TCK Test Clock

Test clock input for JTAG boundary scan, ISP, and UJTAG.

The TCK pin does not have an internal pull-up/down

resistor. If JTAG is not used, Actel recommends tying off

TCK to GND through a resistor placed close to the FPGA

pin. This prevents JTAG operation in case TMS enters an

undesired state.

Note that to operate at all VJTAG voltages, 500 Ω to 1 kΩ

will satisfy the requirements. Refer to Table 2-24 for

more information.

TDI Test Data Input

Serial input for JTAG boundary scan, ISP, and UJTAG

usage. There is an internal weak pull-up resistor on the

TDI pin.

TDO Test Data Output

Serial output for JTAG boundary scan, ISP, and UJTAG

usage.

TMS Test Mode Select

The TMS pin controls the use of the IEEE1532 boundary

scan pins (TCK, TDI, TDO, TRST). There is an internal weak

pull-up resistor on the TMS pin.

TRST Boundary Scan Reset Pin

The TRST pin functions as an active low input to

asynchronously initialize (or reset) the boundary scan

circuitry. There is an internal weak pull-up resistor on the

TRST pin. If JTAG is not used, an external pull-down

resistor could be included to ensure the test access port

(TAP) is held in reset mode. The resistor values must be

chosen from Table 2-24 and must satisfy the parallel

resistance value requirement. The values in Table 2-24

correspond to the resistor recommended when a single

device is used and the equivalent parallel resistor when

multiple devices are connected via a JTAG chain.

In critical applications, an upset in the JTAG circuit could

allow entering an undesired JTAG state. In such cases,

Actel recommends tying off TRST to GND through a

resistor placed close to the FPGA pin.

Note that to operate at all VJTAG voltages, 500 Ω to 1 kΩ

will satisfy the requirements.

Special Function Pins

NC No Connect

This pin is not connected to circuitry within the device.

These pins can be driven to any voltage or can be left

floating with no effect on the operation of the device.

DC Do Not Connect

This pin should not be connected to any signals on the

PCB. These pins should be left unconnected.

Table 2-24 • Recommended Tie-Off Values for the TCK and

TRST Pins

VJTAG Tie-Off Resistance

VJTAG at 3.3 V 200 Ω to 1 kΩ

VJTAG at 2.5 V 200 Ω to 1 kΩ

VJTAG at 1.8 V 500 Ω to 1 kΩ

VJTAG at 1.5 V 500 Ω to 1 kΩ

Notes:

1. Equivalent parallel resistance if more than one device is on

the JTAG chain.

2. The TCK pin can be pulled up/down.

3. The TRST pin be pulled down.

ProASIC®3/E Flash Family FPGAs

2-54 v2.1

Software Tools

Overview of Tools Flow

The ProASIC3 family of FPGAs is fully supported by both

Actel Libero IDE and Designer FPGA development

software. Actel Libero IDE is an integrated design

manager that seamlessly integrates design tools while

guiding the user through the design flow, managing all

design and log files and passing necessary design data

among tools. Additionally, Libero IDE allows users to

integrate both schematic and HDL synthesis into a single

flow and verify the entire design in a single environment

(see the Libero IDE flow diagram located on the Actel

website). Libero IDE includes Synplify® AE from

Synplicity,® ViewDraw® AE from Mentor Graphics,®

ModelSim® HDL Simulator from Mentor Graphics,

WaveFormer LiteTM AE from SynaptiCAD,® PALACETM AE

Physical Synthesis from Magma Design Automation,TM

and Designer software from Actel.

Actel Designer software is a place-and-route tool and

provides a comprehensive suite of backend support tools

for FPGA development. The Designer software includes

the following:

• Timer—a world-class integrated static timing

analyzer and constraints editor that supports

timing-driven place-and-route

• NetlistViewer—a design netlist schematic viewer

• ChipPlanner—a graphical floorplanner viewer and

editor

• SmartPower—a tool that enables the designer to

quickly estimate the power consumption of a

design

• PinEditor—a graphical application for editing pin

assignments and I/O attributes

• I/O Attribute Editor—a tool that displays all

assigned and unassigned I/O macros and their

attributes in a spreadsheet format

With the Designer software, a user can lock the design

pins before layout while minimally impacting the results

of place-and-route. Additionally, Actel back-annotation

flow is compatible with all the major simulators. Another

tool included in the Designer software is the SmartGen

core generator, which easily creates popular and

commonly used logic functions for implementation into

your schematic or HDL design.

Actel Designer software is compatible with the most

popular FPGA design entry and verification tools from

EDA vendors such as Mentor Graphics, Synplicity,

Synopsys, and Cadence.® The Designer software is

available for both the Windows® and UNIX operating

systems.

Programming

Programming can be performed using tools such as

Silicon Sculptor II (BP Micro Systems) or FlashPro3 (Actel).

The user can generate STP programming files from the

Designer software and use these files to program a

device.

ProASIC3 devices can be programmed in system. For

more information on ISP of ProASIC3 devices, refer to the

In-System Programming (ISP) in ProASIC3/E Using

FlashPro3 and Programming a ProASIC3/E Using a

Microprocessor application notes.

The ProASIC3 device can be serialized with a unique

identifier stored in the FlashROM of each device.

Serialization is an automatic assignment of serial

numbers that are stored within the STAPL file used for

programming. The area of the FlashROM used for

holding such identifiers is defined using SmartGen, and

the range of serial numbers to be used is defined at the

time of STAPL file generation with FlashPoint. Serial

number values for STAPL file generation can even be

read from a file of predefined values. Serialized

programming using a serialized STAPL file can be done

through Actel In-House Programming (IHP), an external

vendor using Silicon Sculptor software, or the ISP

capabilities of the FlashPro software.

Security

ProASIC3 devices have a built-in 128-bit AES decryption

core (except the A3P030 device). The decryption core

facilitates secure in-system programming of the FPGA

core array fabric and the FlashROM. The FlashROM and

the FPGA core fabric can be programmed independently

from each other, allowing the FlashROM to be updated

without the need for change to the FPGA core fabric.

The AES master key is stored in on-chip nonvolatile

memory (Flash). The AES master key can be preloaded

into parts in a secure programming environment (such as

the Actel in-house programming center), and then

"blank" parts can be shipped to an untrusted

programming or manufacturing center for final

personalization with an AES-encrypted bitstream. Late-

stage product changes or personalization can be

implemented easily and securely by simply sending a

STAPL file with AES encrypted data. Secure remote field

updates over public networks (such as the Internet) are

possible by sending and programming a STAPL file with

AES-encrypted data.

128-Bit AES Decryption8

The 128-bit AES standard (FIPS-192) block cipher is the

NIST (National Institute of Standards and Technology)

replacement for DES (Data Encryption Standard

ProASIC®3/E Flash Family FPGAs

v2.1 2-55

FIPS46-2). AES has been designed to protect sensitive

government information well into the 21st century. It

replaces the aging DES, which NIST adopted in 1977 as a

Federal Information Processing Standard used by federal

agencies to protect sensitive, unclassified information.

The 128-bit AES standard has 3.4 × 1038 possible 128-bit

key variants, and it has been estimated that it would

take 1,000 trillion years to crack 128-bit AES cipher text

using exhaustive techniques. Keys are stored (securely) in

ProASIC3 devices in nonvolatile Flash memory. All

programming files sent to the device can be

authenticated by the part prior to programming to

ensure that bad programming data is not loaded into

the part that may possibly damage it. All programming

verification is performed on-chip, ensuring that the

contents of ProASIC3 devices remain secure.

ARM-enabled ProASIC3 devices do not support the AES

decryption capability.

AES decryption can also be used on the 1,024-bit

FlashROM to allow for secure remote updates of the

FlashROM contents. This allows for easy, secure support

for subscription model products. See the application

note ProASIC3/E Security for more details.

ISP

ProASIC3 devices support IEEE 1532 ISP via JTAG and

require a single VPUMP voltage of 3.3 V during

programming. In addition, programming via a

microcontroller in a target system can be achieved. See

the application note In-System Programming (ISP) in

ProASIC3/E Using FlashPro3 for more details.

JTAG 1532

ProASIC3 devices support the JTAG-based IEEE 1532

standard for ISP. As part of this support, when a ProASIC3

device is in an unprogrammed state, all user I/O pins are

disabled. This is achieved by keeping the global IO_EN

signal deactivated, which also has the effect of disabling

the input buffers. The SAMPLE/PRELOAD instruction

captures the status of pads in parallel and shifts them

out as new data is shifted in for loading into the

Boundary Scan Register. When the ProASIC3 device is in

an unprogrammed state, the SAMPLE/PRELOAD

instruction has no effect on I/O status; however, it will

continue to shift in new data to be loaded into the BSR.

Therefore, when SAMPLE/PRELOAD is used on an

unprogrammed device, the BSR will be loaded with

undefined data. Refer to the In-System Programming

(ISP) in ProASIC3/E Using FlashPro3 application note for

more details.

For JTAG timing information on setup, hold, and fall

times, refer to the FlashPro User’s Guide.

Boundary Scan

ProASIC3 devices are compatible with IEEE Standard

1149.1, which defines a hardware architecture and the

set of mechanisms for boundary scan testing. The basic

ProASIC3 boundary scan logic circuit is composed of the

TAP controller, test data registers, and instruction

all mandatory IEEE 1149.1 instructions (EXTEST,

SAMPLE/PRELOAD, and BYPASS) and the optional

IDCODE instruction (Table 2-25).

Each test section is accessed through the TAP, which has

five associated pins: TCK (test clock input), TDI, TDO (test

data input and output), TMS (test mode selector), and

TRST (test reset input). TMS, TDI, and TRST are equipped

with pull-up resistors to ensure proper operation when

no input data is supplied to them. These pins are

dedicated for boundary scan test usage. Refer to the

"JTAG Pins" section on page 2-53 for pull-up/down

recommendations for TDO and TCK pins. Table 2-26 gives

pull-down recommendations for the TRST and TCK

pins.

8. The A3P030 device does not support AES decryption.

Table 2-25 • Boundary Scan Opcodes

Hex Opcode

EXTEST 00

HIGHZ 07

USERCODE 0E

SAMPLE/PRELOAD 01

IDCODE 0F

CLAMP 05

BYPASS FF

Table 2-26 • TRST and TCK Pull-Down Recommendations

VJTAG Tie-Off Resistance*

VJTAG at 3.3 V 200 Ω to 1 kΩ

VJTAG at 2.5 V 200 Ω to 1 kΩ

VJTAG at 1.8 V 500 Ω to 1 kΩ

VJTAG at 1.5 V 500 Ω to 1 kΩ

Note: *Equivalent parallel resistance if more than one device

is on JTAG chain (Figure 2-39 on page 2-56).

ProASIC®3/E Flash Family FPGAs

2-56 v2.1

The TAP controller is a 4-bit state machine (16 states)

that operates as shown in Figure 2-40. The 1s and 0s

represent the values that must be present on TMS at a

rising edge of TCK for the given state transition to occur.

IR and DR indicate that the instruction register or the

data register is operating in that state.

The TAP controller receives two control inputs (TMS and

TCK) and generates control and clock signals for the rest

of the test logic architecture. On power-up, the TAP

controller enters the Test-Logic-Reset state. To guarantee

a reset of the controller from any of the possible states,

TMS must remain HIGH for five TCK cycles. The TRST pin

may also be used to asynchronously place the TAP

controller in the Test-Logic-Reset state.

ProASIC3 devices support three types of test data

registers: bypass, device identification, and boundary

scan. The bypass register is selected when no other

test data transfer to other devices in a test data path.

The 32-bit device identification register is a shift register

with four fields (LSB, ID number, part number, and

version). The boundary scan register observes and

controls the state of each I/O pin. Each I/O cell has three

boundary scan register cells, each with serial-in, serial-

out, parallel-in, and parallel-out pins.

Note: TCK is correctly wired with an equivalent tie-off resistance

of 500

, which satisfies the table for VJTAG of 1.5 V. The

resistor values for TRST are not appropriate in this case, as

the tie-off resistance of 375

is below the recommended

minimum for VJTAG = 1.5 V, but would be appropriate for

a VJTAG setting of 2.5 V or 3.3 V.

Figure 2-39 • Parallel Resistance on JTAG Chain of Devices

TDI

TDO

JTAG

Header

Actel

FPGA 1

Actel

FPGA 2

Actel

FPGA 3

Actel

FPGA 4

2 k Ω

1.5 V

TCK

TRST

VJTAG

GND

1.5 k Ω

Figure 2-40 • TAP State Machine

TEST_LOGIC_RESET

RUN_TEST_IDLE SELECT_DR

CAPTURE_DR

SHIFT_DR

EXIT1_DR

PAUSE_DR

EXIT2_DR

UPDATE_DR

SELECT_IR

CAPTURE_IR

SHIFT_IR

EXIT1_IR

PAUSE_IR

EXIT2_IR

UPDATE_IR

ProASIC®3/E Flash Family FPGAs

v2.1 2-57

The serial pins are used to serially connect all the boundary scan register cells in a device into a boundary scan register

chain, which starts at the TDI pin and ends at the TDO pin. The parallel ports are connected to the internal core logic

I/O tile and the input, output, and control ports of an I/O buffer to capture and load data into the register to control or

observe the logic state of each I/O.

Figure 2-41 • Boundary Scan Chain in ProASIC3

Device

Logic

TDI

TCK

TMS

TRST

TDO

I/OI/OI/O I/OI/O

I/O

Bypass Register

Instruction

TAP

Controller

Test Data

Registers

ProASIC®3 Flash Family FPGAs

v2.1 3-1

DC and Switching Characteristics

General Specifications

DC and switching characteristics for –F speed grade targets are based only on simulation.

The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some

restrictions might be added and will be reflected in future revisions of this document. The –F speed grade is only

supported in the commercial temperature range.

Operating Conditions

Stresses beyond those listed in Table 3-1 may cause permanent damage to the device.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute

Maximum Ratings are stress ratings only; functional operation of the device at these or any other conditions beyond

those listed under the Recommended Operating Conditions specified in Table 3-2 on page 3-2 is not implied.

Table 3-1 • Absolute Maximum Ratings

Symbol Parameter Limits Units

VCC DC core supply voltage –0.3 to 1.65 V

VJTAG JTAG DC voltage –0.3 to 3.75 V

VPUMP Programming voltage –0.3 to 3.75 V

VCCPLL Analog power supply (PLL) –0.3 to 1.65 V

VCCI DC I/O output buffer supply voltage –0.3 to 3.75 V

VMV DC I/O input buffer supply voltage –0.3 to 3.75 V

VI I/O input voltage –0.3 V to 3.6 V (when I/O hot insertion mode is enabled)

–0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower (when

I/O hot-insertion mode is disabled)

TSTG 2Storage temperature –65 to +150 °C

TJ2Junction temperature +125 °C

Notes:

1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may undershoot or

overshoot according to the limits shown in Table 3-4 on page 3-2.

2. For Flash programming and retention maximum limits refer to Table 3-3 on page 3-2 and for recommended operating limits refer to

Table 3-2 on page 3-2.

ProASIC®3 Flash Family FPGAs

3-2 v2.1

Table 3-2 • Recommended Operating Conditions

Symbol Parameter Commercial Industrial Units

TJJunction temperature 0 to +70 –40 to +85 °C

VCC 1.5 V DC core supply voltage 1.425 to 1.575 1.425 to 1.575 V

VJTAG JTAG DC voltage 1.4 to 3.6 1.4 to 3.6 V

VPUMP Programming voltage Programming Mode 3.15 to 3.45 3.15 to 3.45 V

Operation30 to 3.6 0 to 3.6 V

VCCPLL Analog power supply (PLL) 1.4 to 1.6 1.4 to 1.6 V

VCCI and VMV 1.5 V DC supply voltage 1.425 to 1.575 1.425 to 1.575 V

1.8 V DC supply voltage 1.7 to 1.9 1.7 to 1.9 V

2.5 V DC supply voltage 2.3 to 2.7 2.3 to 2.7 V

3.3 V DC supply voltage 3.0 to 3.6 3.0 to 3.6 V

LVDS/BLVDS/M-LVDS differential I/O 2.375 to 2.625 2.375 to 2.625 V

LVPECL differential I/O 3.0 to 3.6 3.0 to 3.6 V

Notes:

1. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O standard are given

in Table 3-14 on page 3-15. VMV and VCCI should be at the same voltage within a given I/O bank.

2. All parameters representing voltages are measured with respect to GND unless otherwise specified.

3. VPUMP can be left floating during operation (not programming mode).

Table 3-3 • Flash Programming Limits – Retention, Storage and Operating Temperature1

Product Grade

Programming

Cycles

Program Retention

(biased/unbiased)

Maximum Storage

Temperature TSTG (°C) 2

Maximum Operating Junction

Temperature TJ (°C) 2

Commercial 500 20 years 110 110

Industrial 500 20 years 110 110

Notes:

1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.

2. These limits apply for program/data retention only. Refer to Table 3-1 and Table 3-2 for device operating conditions and absolute

limits.

Table 3-4 • Overshoot and Undershoot Limits (as measured on quiet I/Os)1

VCCI and VMV

Average VCCI–GND Overshoot or Undershoot Duration as a

Percentage of Clock Cycle2Maximum Overshoot/

Undershoot2

2.7 V or less 10% 1.4 V

5% 1.49 V

3 V 10% 1.1 V

5% 1.19 V

3.3 V 10% 0.79 V

5% 0.88 V

3.6 V 10% 0.45 V

5% 0.54 V

Notes:

1. Based on reliability requirements at 85°C.

2. The duration is allowed at one out of six clock cycles (estimated SSO density over cycles). If the overshoot/undershoot occurs at one

out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V.

3. This table refers only to overshoot/undershoot limits for simultaneous switching I/Os and does not provide PCI

overshoot/undershoot limits.

ProASIC®3 Flash Family FPGAs

v2.1 3-3

I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and

Industrial)

Sophisticated power-up management circuitry is

designed into every ProASIC3 device. These circuits

ensure easy transition from the powered-off state to the

powered-up state of the device. The many different

supplies can power up in any sequence with minimized

current spikes or surges. In addition, the I/O will be in a

known state through the power-up sequence. The basic

principle is shown in Figure 3-1.

There are five regions to consider during power-up.

ProASIC3 I/Os are activated only if ALL of the following

three conditions are met:

1. VCC and VCCI are above the minimum specified trip

points (Figure 3-1).

2. VCCI > VCC – 0.75 V (typical)

3. Chip is in the operating mode.

VCCI Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.2 V

Ramping down: 0.5 V < trip_point_down < 1.1 V

VCC Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.1 V

Ramping down: 0.5 V < trip_point_down < 1 V

VCC and VCCI ramp-up trip points are about 100 mV

higher than ramp-down trip points. This specifically

built-in hysteresis prevents undesirable power-up

oscillations and current surges. Note the following:

• During programming, I/Os become tristated and

weakly pulled up to VCCI.

• JTAG supply, PLL power supplies, and charge pump

VPUMP supply have no influence on I/O behavior.

Internal Power-Up Activation Sequence

1. Core

2. Input buffers

3. Output buffers, after 200 ns delay from input

buffer activation

Figure 3-1 • I/O State as a Function of VCCI and VCC Voltage Levels

Region 1: I/O buffers are OFF

Region 2: I/O buffers are ON.

I/Os are functional (except differential inputs)

but slower because VCCI/VCC are below

specification. For the same reason, input

buffers do not meet VIH/VIL levels, and

output buffers do not meet VOH/VOL levels.

Min VCCI datasheet specification

voltage at a selected I/O

standard; i.e., 1.425 V or 1.7 V

or 2.3 V or 3.0 V

VCC

VCC = 1.425 V

Region 1: I/O Buffers are OFF

Activation trip point:

Va = 0.85 V ± 0.25 V

Deactivation trip point:

Vd = 0.75 V ± 0.25 V

Activation trip point:

Va = 0.9 V ± 0.3 V

Deactivation trip point:

Vd = 0.8 V ± 0.3 V

VCC = 1.575 V

Region 5: I/O buffers are ON

and power supplies are within

specification.

I/Os meet the entire datasheet

and timer specifications for

speed, VIH/VIL , VOH/VOL , etc.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential

but slower because VCCI is

below specification. For the

same reason, input buffers do not

meet VIH/VIL levels, and output

buffers do not meet VOH/VOL levels.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential inputs)

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

VCCI

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the VCC is below specification.

VCC = VCCI + VT

ProASIC®3 Flash Family FPGAs

3-4 v2.1

Thermal Characteristics

Introduction

The temperature variable in the Actel Designer software

refers to the junction temperature, not the ambient

temperature. This is an important distinction because

dynamic and static power consumption cause the chip

junction to be higher than the ambient temperature.

EQ 3-1 can be used to calculate junction temperature.

TJ = Junction Temperature = ΔT + TA

EQ 3-1

where:

TA = Ambient Temperature

ΔT = Temperature gradient between junction (silicon)

and ambient ΔT = θja * P

θja = Junction-to-ambient of the package. θja numbers

are located in Table 3-5.

P = Power dissipation

Package Thermal Characteristics

The device junction-to-case thermal resistivity is θjc and

the junction-to-ambient air thermal resistivity is θja. The

thermal characteristics for θja are shown for two air flow

rates. The absolute maximum junction temperature is

110°C. EQ 3-2 shows a sample calculation of the absolute

maximum power dissipation allowed for a 484-pin FBGA

package at commercial temperature and in still air.

EQ 3-2

Table 3-5 • Package Thermal Resistivities

Package Type Device Pin Count θjc

θja

UnitsStill Air

200

ft./min.

500

ft./min.

Quad Flat No Lead A3P030 132 0.4 21.4 16.8 15.3 C/W

A3P060 132 0.3 21.2 16.6 15.0 C/W

A3P125 132 0.2 21.1 16.5 14.9 C/W

A3P250 132 0.1 21.0 16.4 14.8 C/W

Very Thin Quad Flat Pack (VQFP) All devices 100 10.0 35.3 29.4 27.1 C/W

Thin Quad Flat Pack (TQFP) All devices 144 11.0 33.5 28.0 25.7 C/W

Plastic Quad Flat Pack (PQFP) All devices 208 8.0 26.1 22.5 20.8 C/W

Plastic Quad Flat Pack (PQFP) with

embedded heatspreader

All devices 208 3.8 16.2 13.3 11.9 C/W

Fine Pitch Ball Grid Array (FBGA) See note* 144 3.8 26.9 22.9 21.5 C/W

See note* 256 3.8 26.6 22.8 21.5 C/W

See note* 484 3.2 20.5 17.0 15.9 C/W

A3P1000 144 6.3 31.6 26.2 24.2 C/W

A3P1000 256 6.6 28.1 24.4 22.7 C/W

A3P1000 484 8.0 23.3 19.0 16.7 C/W

Note: *This information applies to all ProASIC3 devices except the A3P1000. Detailed device/package thermal information will be

available in future revisions of the datasheet.

Maximum Power Allowed Max. junction temp. (°C) Max. ambient temp. (°C)–

θja(°C/W)

--------------------------------------------------------------------------------------------------------------------------------------- 110°C70°C–

20.5°C/W

------------------------------------ 1.951 W===

ProASIC®3 Flash Family FPGAs

v2.1 3-5

Temperature and Voltage Derating Factors

Calculating Power Dissipation

Quiescent Supply Current

Power Per I/O Pin

Table 3-6 • Temperature and Voltage Derating Factors for Timing Delays

(normalized to TJ = 70°C, VCC = 1.425 V)

Array Voltage VCC

(V)

Junction Temperature (°C)

–40°C 0°C 25°C 70°C 85°C 110°C

1.425 0.87 0.92 0.95 1.00 1.02 1.05

1.500 0.83 0.88 0.90 0.95 0.97 0.99

1.575 0.80 0.85 0.87 0.92 0.93 0.96

Table 3-7 • Quiescent Supply Current Characteristics

A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 A3P1000

Typical (25°C) 2 mA 2 mA 2 mA 3 mA 3 mA 5 mA 8 mA

Maximum (Commercial) 10 mA 10 mA 10 mA 20 mA 20 mA 30 mA 50 mA

Maximum (Industrial) 15 mA 15 mA 15 mA 30 mA 30 mA 45 mA 75 mA

Notes:

1. IDD Includes VCC, VPUMP, VCCI, and VMV currents. Values do not include I/O static contribution, which is shown in Table 3-8 and

Table 3-9 on page 3-6.

2. –F speed grade devices may experience higher standby IDD of up to five times the standard IDD and higher I/O leakage.

Table 3-8 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings1

Applicable to Advanced I/O Banks

CLOAD (pF) VCCI (V)

Static Power

PDC3 (mW)2Dynamic Power

PAC10 (µW/MHz)3

Single-Ended

3.3 V LVTTL /

3.3 V LVCMOS

35 3.3 – 468.67

2.5 V LVCMOS 35 2.5 – 267.48

1.8 V LVCMOS 35 1.8 – 149.46

1.5 V LVCMOS (JESD8-11) 35 1.5 – 103.12

3.3 V PCI 10 3.3 – 201.02

3.3 V PCI-X 10 3.3 – 201.02

Differential

LVDS – 2.5 7.74 88.92

LVPECL – 3.3 19.54 166.52

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output slew.

2. PDC3 is the static power (where applicable) measured on VMV.

3. PAC10 is the total dynamic power measured on VCC and VMV.

ProASIC®3 Flash Family FPGAs

3-6 v2.1

Table 3-9 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings1

Applicable to Standard Plus I/O Banks

CLOAD (pF) VCCI (V)

Static Power

PDC3 (mW)2Dynamic Power

PAC10 (µW/MHz)3

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS 35 3.3 – 452.67

2.5 V LVCMOS 35 2.5 – 258.32

1.8 V LVCMOS 35 1.8 – 133.59

1.5 V LVCMOS (JESD8-11) 35 1.5 – 92.84

3.3 V PCI 10 3.3 – 184.92

3.3 V PCI-X 10 3.3 – 184.92

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output slew.

2. PDC3 is the static power (where applicable) measured on VMV.

3. PAC10 is the total dynamic power measured on VCC and VMV.

Table 3-10 • Summary of I/O Output Buffer Power (Per Pin) – Default I/O Software Settings1

Applicable to Standard I/O Banks

LOAD (pF) VCCI (V)

Static Power

PDC3 (mW)2 Dynamic Power

PAC10 (µW/MHz)3

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS 35 3.3 – 431.08

2.5 V LVCMOS 35 2.5 – 247.36

1.8 V LVCMOS 35 1.8 – 128.46

1.5 V LVCMOS (JESD8-11) 35 1.5 – 89.46

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output slew.

2. PDC3 is the static power (where applicable) measured on VCCI.

3. PAC10 is the total dynamic power measured on VCC and VCCI.

ProASIC®3 Flash Family FPGAs

v2.1 3-7

Power Consumption of Various Internal Resources

Table 3-11 • Different Components Contributing to Dynamic Power Consumption in ProASIC3 Devices

Parameter Definition

Device Specific Dynamic Power

(µW/MHz)

A3P1000 A3P600 A3P400 A3P250 A3P125 A3P060 A3P030

PAC1 Clock contribution of a Global Rib 14.50 12.80 12.80 11.00 11.00 9.30 9.30

PAC2 Clock contribution of a Global Spine 2.48 1.85 1.35 1.58 0.81 0.81 0.41

PAC3 Clock contribution of a VersaTile row 0.81

PAC4 Clock contribution of a VersaTile used

as a sequential module

0.12

PAC5 First contribution of a VersaTile used as

a sequential module

0.07

PAC6 Second contribution of a VersaTile

used as a sequential module

0.29

PAC7 Contribution of a VersaTile used as a

combinatorial Module

0.29

PAC8 Average contribution of a routing net 0.70

PAC9 Contribution of an I/O input pin

(standard-dependent)

See Table 3-8 on page 3-5.

PAC10 Contribution of an I/O output pin

(standard-dependent)

See Tabl e 3-8 and Table 3-9 on page 3-6.

PAC11 Average contribution of a RAM block

during a read operation

25.00

PAC12 Average contribution of a RAM block

during a write operation

30.00

PAC13 Static PLL contribution 2.55 mW

PAC14 Dynamic contribution for PLL 2.60

Note: *For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet calculator or

SmartPower tool in Libero IDE.

ProASIC®3 Flash Family FPGAs

3-8 v2.1

Power Calculation Methodology

This section describes a simplified method to estimate power consumption of an application. For more accurate and

detailed power estimations, use the SmartPower tool in Actel Libero IDE software.

The power calculation methodology described below uses the following variables:

• The number of PLLs as well as the number and the frequency of each output clock generated

• The number of combinatorial and sequential cells used in the design

• The internal clock frequencies

• The number and the standard of I/O pins used in the design

• The number of RAM blocks used in the design

• Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 3-12 on page 3-10.

• Enable rates of output buffers—guidelines are provided for typical applications in Table 3-13 on page 3-10.

• Read rate and write rate to the memory—guidelines are provided for typical applications in Table 3-13 on

page 3-10. The calculation should be repeated for each clock domain defined in the design.

Methodology

Total Power Consumption—PTOTAL

PTOTAL = PSTAT + PDYN

PSTAT is the total static power consumption.

PDYN is the total dynamic power consumption.

Total Static Power Consumption—PSTAT

PSTAT = PDC1 + NINPUTS* PDC2 + NOUTPUTS* PDC3

NINPUTS is the number of I/O input buffers used in the design.

NOUTPUTS is the number of I/O output buffers used in the design.

Total Dynamic Power Consumption—PDYN

PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL

Global Clock Contribution—PCLOCK

PCLOCK = (PAC1 + NSPINE*PAC2 + NROW*PAC3 + NS-CELL* PAC4) * FCLK

NSPINE is the number of global spines used in the user design—guideline are provided in Table 3-12 on page 3-10.

NROW is the number of VersaTile rows used in the design—guidelines are provided in Table 3-12 on page 3-10.

FCLK is the global clock signal frequency.

NS-CELL is the number of VersaTiles used as sequential modules in the design.

PAC1, PAC2, PAC3, and PAC4 are device-dependent.

Sequential Cells Contribution—PS-CELL

PS-CELL = NS-CELL * (PAC5 + α1 / 2 * PAC6) * FCLK

NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile sequential cell

is used, it should be accounted for as 1.

α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 3-12 on page 3-10.

FCLK is the global clock signal frequency.

ProASIC®3 Flash Family FPGAs

v2.1 3-9

Combinatorial Cells Contribution—PC-CELL

PC-CELL = NC-CELL* α1 / 2 * PAC7 * FCLK

NC-CELL is the number of VersaTiles used as combinatorial modules in the design.

α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 3-12 on page 3-10.

FCLK is the global clock signal frequency.

Routing Net Contribution—PNET

PNET = (NS-CELL + NC-CELL) * α1 / 2 * PAC8 * FCLK

NS-CELL is the number VersaTiles used as sequential modules in the design.

NC-CELL is the number of VersaTiles used as combinatorial modules in the design.

α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 3-12 on page 3-10.

FCLK is the global clock signal frequency.

I/O Input Buffer Contribution—PINPUTS

PINPUTS = NINPUTS * α2 / 2 * PAC9 * FCLK

NINPUTS is the number of I/O input buffers used in the design.

α2 is the I/O buffer toggle rate—guidelines are provided in Table 3-12 on page 3-10.

FCLK is the global clock signal frequency.

I/O Output Buffer Contribution—POUTPUTS

POUTPUTS = NOUTPUTS * α2 / 2 * β1 * PAC10 * FCLK

NOUTPUTS is the number of I/O output buffers used in the design.

α2 is the I/O buffer toggle rate—guidelines are provided in Table 3-12 on page 3-10.

β1 is the I/O buffer enable rate—guidelines are provided in Table 3-13 on page 3-10.

FCLK is the global clock signal frequency.

RAM Contribution—PMEMORY

PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * β2 + PAC12 * NBLOCK * FWRITE-CLOCK * β3

NBLOCKS is the number RAM blocks used in the design.

FREAD-CLOCK is the memory read clock frequency.

β2 is the RAM enable rate for read operations.

FWRITE-CLOCK is the memory write clock frequency.

β3 is the RAM enable rate for write operations—guidelines are provided in Table 3-13 on page 3-10.

PLL Contribution—PPLL

PPLL = PAC13 + PAC14 *FCLKOUT

FCLKIN is the input clock frequency.

FCLKOUT is the output clock frequency.1

1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the

PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output

clock in the formula by adding its corresponding contribution (PAC14 * FCLKOUT product) to the total PLL contribution.

ProASIC®3 Flash Family FPGAs

3-10 v2.1

Guidelines

Toggle Rate Definition

A toggle rate defines the frequency of a net or logic

element relative to a clock. It is a percentage. If the

toggle rate of a net is 100%, this means that this net

switches at half the clock frequency. Below are some

examples:

• The average toggle rate of a shift register is 100%

because all flip-flop outputs toggle at half of the

clock frequency.

• The average toggle rate of an 8-bit counter is

25%:

– Bit 0 (LSB) = 100%

– Bit 1 = 50%

– Bit 2 = 25%

–…

– Bit 7 (MSB) = 0.78125%

– Average toggle rate = (100% + 50% + 25% +

12.5% + . . . + 0.78125%) / 8.

Enable Rate Definition

Output enable rate is the average percentage of time

during which tristate outputs are enabled. When

nontristate output buffers are used, the enable rate

should be 100%.

Table 3-12 • Toggle Rate Guidelines Recommended for Power Calculation

Component Definition Guideline

α1Toggle rate of VersaTile outputs 10%

α2I/O buffer toggle rate 10%

Table 3-13 • Enable Rate Guidelines Recommended for Power Calculation

Component Definition Guideline

β1I/O output buffer enable rate 100%

β2RAM enable rate for read operations 12.5%

β3RAM enable rate for write operations 12.5%

ProASIC®3 Flash Family FPGAs

v2.1 3-11

User I/O Characteristics

Timing Model

Figure 3-2 • Timing Model

Operating Conditions: –2 Speed, Commercial Temperature Range (TJ = 70°C), Worst Case VCC = 1.425 V

DQ DQ

Combinational Cell

I/O Module

(Registered)

I/O Module

(Non-Registered)

I/O Module

(Registered)

I/O Module

(Non-Registered)

LVPECL (Applicable to

Advanced I/O Banks Only)L

LVPECL

(Applicable

to Advanced

I/O Banks only)

LVDS,

BLVDS,

M-LVDS

(Applicable for

Advanced I/O

Banks only)

LVTTL 3.3 V Output drive

strength = 12 mA High slew rate

Combinational Cell

I/O Module

(Non-Registered)

LVTTL Output drive strength = 8 mA

High slew rate

I/O Module

(Non-Registered)

LVCMOS 1.5 V Output drive strength = 4 mA

High slew rate

LVTTL Output drive strength = 12 mA

High slew rate

I/O Module

(Non-Registered)

Input LVTTL

Clock

Input LVTTL

Clock

Input LVTTL

Clock

= 0.56 ns t

= 0.49 ns

= 1.34 ns

= 0.87 ns t

= 2.64 ns (Advanced I/O Banks)

= 0.47 ns

= 3.66 ns (Advanced I/O Banks)

= 0.47 ns t

= 3.97 ns (Advanced I/O Banks)

= 0.47 ns

= 0.76 ns

(Advanced I/O Banks)

CLKQ

= 0.55 ns t

OCLKQ

= 0.59 ns

SUD

= 0.43 ns t

OSUD

= 0.31 ns

= 2.64 ns

(Advanced I/O Banks)

= 0.76 ns (Advanced I/O Banks)

= 1.20 ns

CLKQ

= 0.55 ns

SUD

= 0.43 ns

= 0.76 ns

(Advanced I/O Banks)

ICLKQ

= 0.24 ns

ISUD

= 0.26 ns

= 1.05 ns

ProASIC®3 Flash Family FPGAs

3-12 v2.1

Figure 3-3 • Input Buffer Timing Model and Delays (example)

tPY

(R)

PAD

Vtrip

GND tPY

(F)

Vtrip

50%

VIH

VCC

VIL

tDOUT

(R)

DIN

GND tDOUT

(F)

50%50%

VCC

PAD Y

tPY

CLK

I/O Interface

DIN

tDIN

To Array

tPY = MAX(tPY(R), tPY(F))

tDIN = MAX(tDIN(R), tDIN(F))

ProASIC®3 Flash Family FPGAs

v2.1 3-13

Figure 3-4 • Output Buffer Model and Delays (example)

tDP

(R)

PAD VOL

tDP

(F)

Vtrip

VOH

VCC

D50% 50%

VCC

0 V

DOUT 50% 50% 0 V

tDOUT

(R)

tDOUT

(F)

From Array

PAD

tDP

Std

Load

CLK

I/O Interface

DOUT

tDOUT

tDp = MAX(tDP(R), tDP(F))

tDOUT = MAX(tDOUT(R), tDOUT(F))

ProASIC®3 Flash Family FPGAs

3-14 v2.1

Figure 3-5 • Tristate Output Buffer Timing Model and Delays (example)

CLK

10% V

CCI

trip

50%

90% V

CCI

trip

50% 50% t

50%

EOUT

PAD

E50%

EOUT (R)

50%

EOUT (F)

PAD

DOUT

EOUT

I/O interface

EOUT

ZLS

trip

50%

ZHS

trip

50%

EOUT

PAD

E50% 50%

EOUT (R)

EOUT (F)

50%

CCI

, t

ZLS

, t

ZHS

EOUT

= MAX(t

EOUT

(r), t

EOUT

(f))

ProASIC®3 Flash Family FPGAs

v2.1 3-15

Overview of I/O Performance

Summary of I/O DC Input and Output Levels – Default I/O Software Settings

Table 3-14 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial

Conditions—Software Default Settings

Applicable to Advanced I/O Banks

I/O Standard

Drive

Strength

Slew

Rate

VIL VIH VOL VOH IOL IOH

Min, V Max, V Min, V Max, V Max, V Min, V mA mA

3.3 V LVTTL /

3.3 V LVCMOS

12 mA High –0.3 0.8 2 3.6 0.4 2.4 12 12

2.5 V LVCMOS 12 mA High –0.3 0.7 1.7 3.6 0.7 1.7 12 12

1.8 V LVCMOS 12mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 12 12

1.5 V LVCMOS 12mA High –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 *

VCCI

0.75 * VCCI 12 12

3.3 V PCI Per PCI specifications

3.3 V PCI-X Per PCI-X specifications

Note: Currents are measured at 85°C junction temperature.

Table 3-15 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial

Conditions—Software Default Settings

Applicable to Standard Plus I/O Banks

I/O Standard

Drive

Strength

Slew

Rate

VIL VIH VOL VOH IOL IOH

Min, V Max, V Min, V Max, V Max, V Min, V mA mA

3.3 V LVTTL /

3.3 V LVCMOS

12 mA High –0.3 0.8 2 3.6 0.4 2.4 12 12

2.5 V LVCMOS 12 mA High –0.3 0.7 1.7 3.6 0.7 1.7 12 12

1.8 V LVCMOS 8 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 8 8

1.5 V LVCMOS 4 mA High –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 *

VCCI

0.75 * VCCI 4 4

3.3 V PCI Per PCI specifications

3.3 V PCI-X Per PCI-X specifications

Note: Currents are measured at 85°C junction temperature.

Table 3-16 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial

Conditions—Software Default Settings

Applicable to Standard I/O Banks

I/O Standard

Drive

Strength

Slew

Rate

VIL VIH VOL VOH IOL IOH

Min, V Max, V Min, V Max, V Max, V Min, V mA mA

3.3 V LVTTL /

3.3 V LVCMOS

8 mA High –0.3 0.8 2 3.6 0.4 2.4 8 8

2.5 V LVCMOS 8 mA High –0.3 0.7 1.7 3.6 0.7 1.7 8 8

1.8 V LVCMOS 4 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 4 4

1.5 V LVCMOS 2 mA High –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 *

VCCI

0.75 * VCCI 22

Note: Currents are measured at 85°C junction temperature.

ProASIC®3 Flash Family FPGAs

3-16 v2.1

Table 3-17 • Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions

DC I/O Standards

Commercial1Industrial2

IIL IIH IIL IIH

µA µA µA µA

3.3 V LVTTL /3.3 V LVCMOS 10 10 15 15

2.5 V LVCMOS 10 10 15 15

1.8 V LVCMOS 10 10 15 15

1.5 V LVCMOS 10 10 15 15

3.3 V PCI 10 10 15 15

3.3 V PCI-X 10 10 15 15

Notes:

1. Commercial range (0°C < TJ < 70°C)

2. Industrial range (–40°C < TJ < 85°C)

ProASIC®3 Flash Family FPGAs

v2.1 3-17

Summary of I/O Timing Characteristics – Default I/O Software Settings

Table 3-18 • Summary of AC Measuring Points

Standard Measuring Trip Point (Vtrip)

3.3 V LVTTL / 3.3 V LVCMOS 1.4 V

2.5 V LVCMOS 1.2 V

1.8 V LVCMOS 0.90 V

1.5 V LVCMOS 0.75 V

3.3 V PCI 0.285 * VCCI (RR)

0.615 * VCCI (FF)

3.3 V PCI-X 0.285 * VCCI (RR)

0.615 * VCCI (FF)

Table 3-19 • I/O AC Parameter Definitions

Parameter Parameter Definition

tDP Data to Pad delay through the Output Buffer

tPY Pad to Data delay through the Input Buffer

tDOUT Data to Output Buffer delay through the I/O interface

tEOUT Enable to Output Buffer Tristate Control delay through the I/O interface

tDIN Input Buffer to Data delay through the I/O interface

tHZ Enable to Pad delay through the Output Buffer—HIGH to Z

tZH Enable to Pad delay through the Output Buffer—Z to HIGH

tLZ Enable to Pad delay through the Output Buffer—LOW to Z

tZL Enable to Pad delay through the Output Buffer—Z to LOW

tZHS Enable to Pad delay through the Output Buffer with delayed enable—Z to HIGH

tZLS Enable to Pad delay through the Output Buffer with delayed enable—Z to LOW

ProASIC®3 Flash Family FPGAs

3-18 v2.1

Table 3-20 • Summary of I/O Timing Characteristics—Software Default Settings

–2 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V

Advanced I/O Banks

I/O Standard

Drive Strength (mA)

Slew Rate

Capacitive Load (pF)

External Resistor (Ω)

tDOUT (ns)

tDP (ns)

tDIN (ns)

tPY (ns)

tEOUT (ns)

tZL (ns)

tZH (ns)

tLZ (ns)

tHZ (ns)

tZLS (ns)

tZHS (ns)

3.3 V LVTTL /

3.3 V LVCMOS

12 High 35 – 0.49 2.64 0.03 0.76 0.32 2.69 2.11 2.40 2.68 4.36 3.78

2.5 V LVCMOS 12 High 35 – 0.49 2.66 0.03 0.98 0.32 2.71 2.56 2.47 2.57 4.38 4.23

1.8 V LVCMOS 12 High 35 – 0.49 2.64 0.03 0.91 0.32 2.69 2.27 2.76 3.05 4.36 3.94

1.5 V LVCMOS 12 High 35 – 0.49 3.05 0.03 1.07 0.32 3.10 2.67 2.95 3.14 4.77 4.34

3.3 V PCI Per PCI

specification

High 10 25 20.49 2.00 0.03 0.65 0.32 2.04 1.46 2.40 2.68 3.71 3.13

3.3 V PCI-X Per PCI-X

specification

High 10 25 20.49 2.00 0.03 0.65 0.32 2.04 1.46 2.40 2.68 3.71 3.13

LVDS 24 High – –0.491.370.031.20–––––––

LVPECL 24 High – –0.491.340.031.05–––––––

Notes:

1. For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 3-10 on page 3-53 for connectivity.

This resistor is not required during normal operation.

Table 3-21 • Summary of I/O Timing Characteristics—Software Default Settings

–2 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V

Standard Plus I/O Banks

I/O Standard

Drive Strength (mA)

Slew Rate

Capacitive Load (pF)

External Resistor

tDOUT (ns)

tDP (ns)

tDIN (ns)

tPY (ns)

tEOUT (ns)

tZL (ns)

tZH (ns)

tLZ (ns)

tHZ (ns)

tZLS (ns)

tZHS (ns)

3.3 V LVTTL /

3.3 V LVCMOS

12 mA High 35 pF – 0.49 2.36 0.03 0.75 0.32 2.40 1.93 2.08 2.41 4.07 3.60

2.5 V LVCMOS 12 mA High 35pF – 0.49 2.39 0.03 0.97 0.32 2.44 2.35 2.11 2.32 4.11 4.02

1.8 V LVCMOS 8 mA High 35pF – 0.49 3.03 0.03 0.90 0.32 2.87 3.03 2.19 2.32 4.54 4.70

1.5 V LVCMOS 4 mA High 35pF – 0.49 3.61 0.03 1.06 0.32 3.35 3.61 2.26 2.34 5.02 5.28

3.3 V PCI Per PCI

specification

High 10pF 25 20.49 1.72 0.03 0.64 0.32 1.76 1.27 2.08 2.41 3.42 2.94

ProASIC®3 Flash Family FPGAs

v2.1 3-19

3.3 V PCI-X Per PCI-X

specification

High 10pF 25 20.49 1.72 0.03 0.64 0.32 1.76 1.27 2.08 2.41 3.42 2.94

Notes:

1. For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 3-10 on page 3-53 for connectivity.

This resistor is not required during normal operation.

Table 3-22 • Summary of I/O Timing Characteristics—Software Default Settings

–2 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V

Standard I/O Banks

I/O Standard

Drive Strength (mA)

Slew Rate

Capacitive Load (pF)

External Resistor

tDOUT (ns)

tDP (ns)

tDIN (ns)

tPY (ns)

tEOUT (ns)

tZL (ns)

tZH (ns)

tLZ (ns)

tHZ (ns)

3.3 V LVTTL /

3.3 V LVCMOS

8 mA High 35 pF – 0.49 3.29 0.03 0.75 0.32 3.36 2.80 1.79 2.01

2.5 V LVCMOS 8 mA High 35pF – 0.49 3.56 0.03 0.96 0.32 3.40 3.56 1.78 1.91

1.8 V LVCMOS 4 mA High 35pF – 0.49 4.74 0.03 0.90 0.32 4.02 4.74 1.80 1.85

1.5 V LVCMOS 2 mA High 35pF – 0.49 5.71 0.03 1.06 0.32 4.71 5.71 1.83 1.83

Notes:

1. For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 3-10 on page 3-53 for connectivity.

This resistor is not required during normal operation.

Table 3-21 • Summary of I/O Timing Characteristics—Software Default Settings

–2 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V

Standard Plus I/O Banks

I/O Standard

Drive Strength (mA)

Slew Rate

Capacitive Load (pF)

External Resistor

tDOUT (ns)

tDP (ns)

tDIN (ns)

tPY (ns)

tEOUT (ns)

tZL (ns)

tZH (ns)

tLZ (ns)

tHZ (ns)

tZLS (ns)

tZHS (ns)

ProASIC®3 Flash Family FPGAs

3-20 v2.1

Detailed I/O DC Characteristics

Table 3-23 • Input Capacitance

Symbol Definition Conditions Min. Max. Units

CIN Input capacitance VIN = 0, f = 1.0 MHz 8 pF

CINCLK Input capacitance on the clock pin VIN = 0, f = 1.0 MHz 8 pF

Table 3-24 • I/O Output Buffer Maximum Resistances1

Applicable to Advanced I/O Banks

Standard Drive Strength

RPULL-DOWN R

PULL-UP

(Ω)2 (Ω)3

3.3 V LVTTL/ 3.3V LVCMOS 2 mA 100 300

4 mA 100 300

6 mA 50 150

8 mA 50 150

12 mA 25 75

16 mA 17 50

24 mA 11 33

2.5 V LVCMOS 2 mA 100 200

4 mA 100 200

6 mA 50 100

8 mA 50 100

12 mA 25 50

16 mA 20 40

24 mA 11 22

1.8 V LVCMOS 2 mA 200 225

4 mA 100 112

6 mA 50 56

8 mA 50 56

12 mA 20 22

16 mA 20 22

1.5V LVCMOS 2 mA 200 224

4 mA 100 112

6 mA 67 75

8 mA 33 37

12 mA 33 37

3.3V PCI/PCI-X Per PCI/PCI-X specification 25 75

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive

strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the

corresponding IBIS models located on the Actel website at http://www.actel.com/download/ibis/default.aspx.

2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec

3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec

ProASIC®3 Flash Family FPGAs

v2.1 3-21

Table 3-25 • I/O Output Buffer Maximum Resistances1

Applicable to Standard Plus I/O Banks

Standard Drive Strength

RPULL-DOWN RPULL-UP

(Ω)2 (Ω)3

3.3 V LVTTL/ 3.3 V LVCMOS 2 mA 100 300

4 mA 100 300

6 mA 50 150

8 mA 50 150

12 mA 25 75

16 mA 25 75

2.5 V LVCMOS 2 mA 100 200

4 mA 100 200

6 mA 50 100

8 mA 50 100

12 mA 25 50

1.8 V LVCMOS 2 mA 200 225

4 mA 100 112

6 mA 50 56

8 mA 50 56

1.5 V LVCMOS 2 mA 200 224

4 mA 100 112

3.3 V PCI/PCI-X Per PCI/PCI-X specification 0 0

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive

strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the

corresponding IBIS models located on the Actel website at http://www.actel.com/download/ibis/default.aspx.

2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec

3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec

Table 3-26 • I/O Output Buffer Maximum Resistances1

Applicable to Standard I/O Banks

Standard Drive Strength

RPULL-DOWN R

PULL-UP

(Ω)2 (Ω)3

3.3 V LVTTL / 3.3 V LVCMOS 2 mA 100 300

4 mA 100 300

6 mA 50 150

8 mA 50 150

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive

strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the

corresponding IBIS models located on the Actel website at http://www.actel.com/download/ibis/default.aspx.

2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec

3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec

ProASIC®3 Flash Family FPGAs

3-22 v2.1

2.5V LVCMOS 2mA 100 200

4mA 100 200

6mA 50 100

8mA 50 100

1.8V LVCMOS 2mA 200 225

4mA 100 112

1.5V LVCMOS 2mA 200 224

Table 3-27 • I/O Weak Pull-Up/Pull-Down Resistances

Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values

VCCI

R(WEAK PULL-UP)1

(Ω)

R(WEAK PULL-DOWN)2

(Ω)

Min. Max. Min. Max.

3.3 V 10 k 45 k 10 k 45 k

2.5 V 11 k 55 k 12 k 74 k

1.8 V 18 k 70 k 17 k 110 k

1.5 V 19 k 90 k 19 k 140 k

Notes:

1. R(WEAK PULL-UP-MAX) = (VOLspec) / I(WEAK PULL-UP-MIN)

2. R(WEAK PULL-UP-MAX) = (VCCImax – VOHspec) / I(WEAK PULL-UP-MIN)

Table 3-28 • I/O Short Currents IOSH/IOSL

Applicable to Advanced I/O Banks

Drive Strength IOSL (mA)* IOSH (mA)*

3.3 V LVTTL / 3.3 V LVCMOS 2 mA 27 25

4 mA 27 25

6 mA 54 51

8 mA 54 51

12 mA 109 103

16 mA 127 132

24 mA 181 268

Table 3-26 • I/O Output Buffer Maximum Resistances1

Applicable to Standard I/O Banks

Standard Drive Strength

RPULL-DOWN R

PULL-UP

(Ω)2 (Ω)3

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive

strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the

corresponding IBIS models located on the Actel website at http://www.actel.com/download/ibis/default.aspx.

2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec

3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec

ProASIC®3 Flash Family FPGAs

v2.1 3-23

3.3 V LVCMOS 2 mA 27 25

4 mA 27 25

6 mA 54 51

8 mA 54 51

12 mA 109 103

16 mA 127 132

24 mA 181 268

2.5 V LVCMOS 2 mA 18 16

4 mA 18 16

6 mA 37 32

8 mA 37 32

12 mA 74 65

16 mA 87 83

24 mA 124 169

1.8 V LVCMOS 2 mA 11 9

4 mA 22 17

6 mA 44 35

8 mA 51 45

12 mA 74 91

16 mA 74 91

1.5 V LVCMOS 2 mA 16 13

4 mA 33 25

6 mA 39 32

8 mA 55 66

12 mA 55 66

3.3 V PCI/PCI-X Per PCI/PCI-X specification 109 103

Note: *TJ = 100°C

Table 3-29 • I/O Short Currents IOSH/IOSL

Applicable to Standard Plus I/O Banks

Drive Strength IOSL (mA)* IOSH (mA)*

3.3 V LVTTL / 3.3 V LVCMOS 2 mA 27 25

4 mA 27 25

6 mA 54 51

8 mA 54 51

12 mA 109 103

16 mA 109 103

Table 3-28 • I/O Short Currents IOSH/IOSL

Applicable to Advanced I/O Banks

Drive Strength IOSL (mA)* IOSH (mA)*

ProASIC®3 Flash Family FPGAs

3-24 v2.1

2.5 V LVCMOS 2 mA 18 16

4 mA 18 16

6 mA 37 32

8 mA 37 32

12 mA 74 65

1.8 V LVCMOS 2 mA 11 9

4 mA 22 17

6 mA 44 35

8 mA 44 35

1.5 V LVCMOS 2 mA 16 13

4 mA 33 25

3.3 V PCI/PCI-X Per PCI/PCI-X specification 109 103

Note: *TJ = 100°C

Table 3-30 • I/O Short Currents IOSH/IOSL

Applicable to Standard I/O Banks

Drive Strength IOSL (mA)* IOSH (mA)*

3.3 V LVTTL / 3.3 V LVCMOS 2 mA 27 25

4 mA 27 25

6 mA 54 51

8 mA 54 51

2.5 V LVCMOS 2 mA 18 16

4 mA 18 16

6 mA 37 32

8 mA 37 32

1.8 V LVCMOS 2 mA 11 9

4 mA 22 17

1.5 V LVCMOS 2 mA 16 13

Note: *TJ = 100°C

Table 3-29 • I/O Short Currents IOSH/IOSL

Applicable to Standard Plus I/O Banks

Drive Strength IOSL (mA)* IOSH (mA)*

ProASIC®3 Flash Family FPGAs

v2.1 3-25

The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The reliability data

below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of analysis.

For example, at 110°C, the short current condition would have to be sustained for more than three months to cause a

reliability concern. The I/O design does not contain any short circuit protection, but such protection would only be

needed in extremely prolonged stress conditions.

Table 3-31 • Short Current Event Duration before Failure

Temperature Time before Failure

–40°C > 20 years

0°C > 20 years

25°C > 20 years

70°C 5 years

85°C 2 years

100°C 6 months

110°C 3 months

Table 3-32 • I/O Input Rise Time, Fall Time, and Related I/O Reliability

Input Buffer Input Rise/Fall Time (min.) Input Rise/Fall Time (max.) Reliability

LVTTL/LVCMOS No requirement 10 ns * 20 years (110°C)

LVDS/BLVDS.M-LVDS/LVPECL No requirement 10 ns * 10 years (100°C)

Note: *The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low, then the rise time

and fall time of input buffers can be increased beyond the maximum value. The longer the rise/fall times, the more susceptible the

input signal is to the board noise. Actel recommends signal integrity evaluation/characterization of the system to ensure that there

is no excessive noise coupling into input signals.

ProASIC®3 Flash Family FPGAs

3-26 v2.1

Single-Ended I/O Characteristics

3.3 V LVTTL / 3.3 V LVCMOS

Low-Voltage Transistor–Transistor Logic (LVTTL) is a general purpose standard (EIA/JESD) for 3.3 V applications. It uses

an LVTTL input buffer and push-pull output buffer.

Table 3-33 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

3.3 V

LVTTL /

3.3 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA

Max.,

mA1Max.,

mA1µA2µA2

2 mA –0.3 0.8 2 3.6 0.4 2.4 2 2 27 25 10 10

4 mA –0.3 0.8 2 3.6 0.4 2.4 4 4 27 25 10 10

6 mA –0.3 0.8 2 3.6 0.4 2.4 6 6 54 51 10 10

8 mA –0.3 0.8 2 3.6 0.4 2.4 8 8 54 51 10 10

12 mA –0.3 0.8 2 3.6 0.4 2.4 12 12 109 103 10 10

16 mA –0.3 0.8 2 3.6 0.4 2.4 16 16 127 132 10 10

24 mA –0.3 0.8 2 3.6 0.4 2.4 24 24 181 268 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 3-34 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

3.3 V

LVTTL /

3.3 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA

Max.,

mA1Max.,

mA1µA2µA2

2 mA –0.3 0.8 2 3.6 0.4 2.4 2 2 27 25 10 10

4 mA –0.3 0.8 2 3.6 0.4 2.4 4 4 27 25 10 10

6 mA –0.3 0.8 2 3.6 0.4 2.4 6 6 54 51 10 10

8 mA –0.3 0.8 2 3.6 0.4 2.4 8 8 54 51 10 10

12 mA –0.3 0.8 2 3.6 0.4 2.4 12 12 109 103 10 10

16 mA –0.3 0.8 2 3.6 0.4 2.4 16 16 109 103 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

ProASIC®3 Flash Family FPGAs

v2.1 3-27

Table 3-35 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard I/O Banks

3.3 V

LVTTL /

3.3 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA

Max.,

mA1Max.,

mA1µA2µA2

2mA –0.3 0.8 2 3.6 0.4 2.4 2 2 25 27 10 10

4mA –0.3 0.8 2 3.6 0.4 2.4 4 4 25 27 10 10

6mA –0.3 0.8 2 3.6 0.4 2.4 6 6 51 54 10 10

8mA –0.3 0.8 2 3.6 0.4 2.4 8 8 51 54 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Figure 3-6 • AC Loading

Table 3-36 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF)

03.31.435

Note: *Measuring point = Vtrip. See Table 3-18 on page 3-17 for a complete table of trip points.

Test Point Test Point

Enable Path

Datapath 35 pF

R = 1 k R to VCCI for tLZ/tZL/tZLS

R to GND for tHZ/tZH/tZHS

35 pF for tZH/tZHS/tZL/tZLS

5 pF for tHZ/tLZ

ProASIC®3 Flash Family FPGAs

3-28 v2.1

Timing Characteristics

Table 3-37 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Advanced I/O Banks

Drive Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS

Units

4 mA –F 0.79 9.20 0.05 1.22 0.51 9.37 7.91 3.18 3.14 12.05 10.60 ns

Std. 0.66 7.66 0.04 1.02 0.43 7.80 6.59 2.65 2.61 10.03 8.82 ns

–1 0.56 6.51 0.04 0.86 0.36 6.63 5.60 2.25 2.22 8.54 7.51 ns

–2 0.49 5.72 0.03 0.76 0.32 5.82 4.92 1.98 1.95 7.49 6.59 ns

6 mA –F 0.79 5.89 0.05 1.22 0.51 6.00 4.89 3.59 3.85 8.69 7.57 ns

Std. 0.66 4.91 0.04 1.02 0.43 5.00 4.07 2.99 3.20 7.23 6.31 ns

–1 0.56 4.17 0.04 0.86 0.36 4.25 3.46 2.54 2.73 6.15 5.36 ns

–2 0.49 3.66 0.03 0.76 0.32 3.73 3.04 2.23 2.39 5.40 4.71 ns

8 mA –F 0.79 5.89 0.05 1.22 0.51 6.00 4.89 3.59 3.85 8.69 7.57 ns

Std. 0.66 4.91 0.04 1.02 0.43 5.00 4.07 2.99 3.20 7.23 6.31 ns

–1 0.56 4.17 0.04 0.86 0.36 4.25 3.46 2.54 2.73 6.15 5.36 ns

–2 0.49 3.66 0.03 0.76 0.32 3.73 3.04 2.23 2.39 5.40 4.71 ns

12 mA –F 0.79 4.24 0.05 1.22 0.51 4.32 3.39 3.86 4.30 7.01 6.08 ns

Std. 0.66 3.53 0.04 1.02 0.43 3.60 2.82 3.21 3.58 5.83 5.06 ns

–1 0.56 3.00 0.04 0.86 0.36 3.06 2.40 2.73 3.05 4.96 4.30 ns

–2 0.49 2.64 0.03 0.76 0.32 2.69 2.11 2.40 2.68 4.36 3.78 ns

16 mA –F 0.79 4.00 0.05 1.22 0.51 4.08 3.08 3.92 4.42 6.76 5.77 ns

Std. 0.66 3.33 0.04 1.02 0.43 3.39 2.56 3.26 3.68 5.63 4.80 ns

–1 0.56 2.83 0.04 0.86 0.36 2.89 2.18 2.77 3.13 4.79 4.08 ns

–2 0.49 2.49 0.03 0.76 0.32 2.53 1.91 2.44 2.75 4.20 3.58 ns

24 mA –F 0.79 3.69 0.05 1.22 0.51 3.76 2.54 3.99 4.88 6.45 5.23 ns

Std. 0.66 3.08 0.04 1.02 0.43 3.13 2.12 3.32 4.06 5.37 4.35 ns

–1 0.56 2.62 0.04 0.86 0.36 2.66 1.80 2.83 3.45 4.57 3.70 ns

–2 0.49 2.30 0.03 0.76 0.32 2.34 1.58 2.48 3.03 4.01 3.25 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

ProASIC®3 Flash Family FPGAs

v2.1 3-29

Table 3-38 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Advanced I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA –F 0.79 12.32 0.05 1.22 0.51 12.55 10.69 3.18 2.95 15.23 13.37 ns

Std. 0.66 10.26 0.04 1.02 0.43 10.45 8.90 2.64 2.46 12.68 11.13 ns

–1 0.56 8.72 0.04 0.86 0.36 8.89 7.57 2.25 2.09 10.79 9.47 ns

–2 0.49 7.66 0.03 0.76 0.32 7.80 6.64 1.98 1.83 9.47 8.31 ns

6 mA –F 0.79 8.74 0.05 1.22 0.51 8.90 7.55 3.58 3.65 11.59 10.23 ns

Std. 0.66 7.27 0.04 1.02 0.43 7.41 6.28 2.98 3.04 9.65 8.52 ns

–1 0.56 6.19 0.04 0.86 0.36 6.30 5.35 2.54 2.59 8.20 7.25 ns

–2 0.49 5.43 0.03 0.76 0.32 5.53 4.69 2.23 2.27 7.20 6.36 ns

8 mA –F 0.79 8.74 0.05 1.22 0.51 8.90 7.55 3.58 3.65 11.59 10.23 ns

Std. 0.66 7.27 0.04 1.02 0.43 7.41 6.28 2.98 3.04 9.65 8.52 ns

–1 0.56 6.19 0.04 0.86 0.36 6.30 5.35 2.54 2.59 8.20 7.25 ns

–2 0.49 5.43 0.03 0.76 0.32 5.53 4.69 2.23 2.27 7.20 6.36 ns

12 mA –F 0.79 6.70 0.05 1.22 0.51 6.83 5.85 3.85 4.10 9.51 8.54 ns

Std. 0.66 5.58 0.04 1.02 0.43 5.68 4.87 3.21 3.42 7.92 7.11 ns

–1 0.56 4.75 0.04 0.86 0.36 4.84 4.14 2.73 2.91 6.74 6.05 ns

–2 0.49 4.17 0.03 0.76 0.32 4.24 3.64 2.39 2.55 5.91 5.31 ns

16 mA –F 0.79 6.25 0.05 1.22 0.51 6.37 5.48 3.91 4.22 9.06 8.17 ns

Std. 0.66 5.21 0.04 1.02 0.43 5.30 4.56 3.26 3.51 7.54 6.80 ns

–1 0.56 4.43 0.04 0.86 0.36 4.51 3.88 2.77 2.99 6.41 5.79 ns

–2 0.49 3.89 0.03 0.76 0.32 3.96 3.41 2.43 2.62 5.63 5.08 ns

24 mA –F 0.79 5.83 0.05 1.22 0.51 5.93 5.46 3.98 4.67 8.62 8.15 ns

Std. 0.66 4.85 0.04 1.02 0.43 4.94 4.54 3.32 3.88 7.18 6.78 ns

–1 0.56 4.13 0.04 0.86 0.36 4.20 3.87 2.82 3.30 6.10 5.77 ns

–2 0.49 3.62 0.03 0.76 0.32 3.69 3.39 2.48 2.90 5.36 5.06 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

ProASIC®3 Flash Family FPGAs

3-30 v2.1

Table 3-39 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Plus I/O Banks

Drive Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA –F 0.79 8.65 0.05 1.20 0.51 8.81 7.55 2.73 2.81 11.50 10.24 ns

Std. 0.66 7.20 0.04 1.00 0.43 7.34 6.29 2.27 2.34 9.57 8.52 ns

–1 0.56 6.13 0.04 0.85 0.36 6.24 5.35 1.93 1.99 8.14 7.25 ns

–2 0.49 5.38 0.03 0.75 0.32 5.48 4.69 1.70 1.75 7.15 6.36 ns

6 mA –F 0.79 5.41 0.05 1.20 0.51 5.51 4.58 3.10 3.45 8.19 7.27 ns

Std. 0.66 4.50 0.04 1.00 0.43 4.58 3.82 2.58 2.88 6.82 6.05 ns

–1 0.56 3.83 0.04 0.85 0.36 3.90 3.25 2.19 2.45 5.80 5.15 ns

–2 0.49 3.36 0.03 0.75 0.32 3.42 2.85 1.92 2.15 5.09 4.52 ns

8 mA –F 0.79 5.41 0.05 1.20 0.51 5.51 4.58 3.10 3.45 8.19 7.27 ns

Std. 0.66 4.50 0.04 1.00 0.43 4.58 3.82 2.58 2.88 6.82 6.05 ns

–1 0.56 3.83 0.04 0.85 0.36 3.90 3.25 2.19 2.45 5.80 5.15 ns

–2 0.49 3.36 0.03 0.75 0.32 3.42 2.85 1.92 2.15 5.09 4.52 ns

12 mA –F 0.79 3.80 0.05 1.20 0.51 3.87 3.10 3.35 3.87 6.55 5.79 ns

Std. 0.66 3.16 0.04 1.00 0.43 3.22 2.58 2.79 3.22 5.45 4.82 ns

–1 0.56 2.69 0.04 0.85 0.36 2.74 2.20 2.37 2.74 4.64 4.10 ns

–2 0.49 2.36 0.03 0.75 0.32 2.40 1.93 2.08 2.41 4.07 3.60 ns

16 mA –F 0.79 3.80 0.05 1.20 0.51 3.87 3.10 3.35 3.87 6.55 5.79 ns

Std. 0.66 3.16 0.04 1.00 0.43 3.22 2.58 2.79 3.22 5.45 4.82 ns

–1 0.56 2.69 0.04 0.85 0.36 2.74 2.20 2.37 2.74 4.64 4.10 ns

–2 0.49 2.36 0.03 0.75 0.32 2.40 1.93 2.08 2.41 4.07 3.60 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

ProASIC®3 Flash Family FPGAs

v2.1 3-31

Table 3-40 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Plus I/O Banks

Drive Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA –F 0.79 11.63 0.05 1.20 0.51 11.84 10.12 2.74 2.65 14.53 12.81 ns

Std. 0.66 9.68 0.04 1.00 0.43 9.86 8.42 2.28 2.21 12.09 10.66 ns

–1 0.56 8.23 0.04 0.85 0.36 8.39 7.17 1.94 1.88 10.29 9.07 ns

–2 0.49 7.23 0.03 0.75 0.32 7.36 6.29 1.70 1.65 9.03 7.96 ns

6 mA –F 0.79 8.05 0.05 1.20 0.51 8.20 7.07 3.10 3.29 10.88 9.76 ns

Std. 0.66 6.70 0.04 1.00 0.43 6.82 5.89 2.58 2.74 9.06 8.12 ns

–1 0.56 5.70 0.04 0.85 0.36 5.80 5.01 2.20 2.33 7.71 6.91 ns

–2 0.49 5.00 0.03 0.75 0.32 5.10 4.40 1.93 2.05 6.76 6.06 ns

8 mA –F 0.79 8.05 0.05 1.20 0.51 8.20 7.07 3.10 3.29 10.88 9.76 ns

Std. 0.66 6.70 0.04 1.00 0.43 6.82 5.89 2.58 2.74 9.06 8.12 ns

–1 0.56 5.70 0.04 0.85 0.36 5.80 5.01 2.20 2.33 7.71 6.91 ns

–2 0.49 5.00 0.03 0.75 0.32 5.10 4.40 1.93 2.05 6.76 6.06 ns

12 mA –F 0.79 6.06 0.05 1.20 0.51 6.18 5.42 3.35 3.70 8.86 8.10 ns

Std. 0.66 5.05 0.04 1.00 0.43 5.14 4.51 2.79 3.08 7.38 6.75 ns

–1 0.56 4.29 0.04 0.85 0.36 4.37 3.84 2.38 2.62 6.28 5.74 ns

–2 0.49 3.77 0.03 0.75 0.32 3.84 3.37 2.09 2.30 5.51 5.04 ns

16 mA –F 0.79 6.06 0.05 1.20 0.51 6.18 5.42 3.35 3.70 8.86 8.10 ns

Std. 0.66 5.05 0.04 1.00 0.43 5.14 4.51 2.79 3.08 7.38 6.75 ns

–1 0.56 4.29 0.04 0.85 0.36 4.37 3.84 2.38 2.62 6.28 5.74 ns

–2 0.49 3.77 0.03 0.75 0.32 3.84 3.37 2.09 2.30 5.51 5.04

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

ProASIC®3 Flash Family FPGAs

3-32 v2.1

Table 3-41 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard I/O Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units

2 mA –F 0.79 8.49 0.05 1.20 0.51 8.65 7.48 2.49 2.58 ns

Std. 0.66 7.07 0.04 1.00 0.43 7.20 6.23 2.07 2.15 ns

–1 0.56 6.01 0.04 0.85 0.36 6.12 5.30 1.76 1.83 ns

–2 0.49 5.28 0.03 0.75 0.32 5.37 4.65 1.55 1.60 ns

4 mA –F 0.79 8.49 0.05 1.20 0.51 8.65 7.48 2.49 2.58 ns

Std. 0.66 7.07 0.04 1.00 0.43 7.20 6.23 2.07 2.15 ns

–1 0.56 6.01 0.04 0.85 0.36 6.12 5.30 1.76 1.83 ns

–2 0.49 5.28 0.03 0.75 0.32 5.37 4.65 1.55 1.60 ns

6 mA –F 0.79 5.30 0.05 1.20 0.51 5.40 4.51 2.88 3.23 ns

Std. 0.66 4.41 0.04 1.00 0.43 4.49 3.75 2.39 2.69 ns

–1 0.56 3.75 0.04 0.85 0.36 3.82 3.19 2.04 2.29 ns

–2 0.49 3.29 0.03 0.75 0.32 3.36 2.80 1.79 2.01 ns

8 mA –F 0.79 5.30 0.05 1.20 0.51 5.40 4.51 2.88 3.23 ns

Std. 0.66 4.41 0.04 1.00 0.43 4.49 3.75 2.39 2.69 ns

–1 0.56 3.75 0.04 0.85 0.36 3.82 3.19 2.04 2.29 ns

–2 0.49 3.29 0.03 0.75 0.32 3.36 2.80 1.79 2.01 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

ProASIC®3 Flash Family FPGAs

v2.1 3-33

Table 3-42 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units

2 mA –F 0.79 11.37 0.05 1.20 0.51 11.58 10.26 2.49 2.45 ns

Std. 0.66 9.46 0.04 1.00 0.43 9.64 8.54 2.07 2.04 ns

–1 0.56 8.05 0.04 0.85 0.36 8.20 7.27 1.76 1.73 ns

–2 0.49 7.07 0.03 0.75 0.32 7.20 6.38 1.55 1.52 ns

4 mA –F 0.79 11.37 0.05 1.20 0.51 11.58 10.26 2.49 2.45 ns

Std. 0.66 9.46 0.04 1.00 0.43 9.64 8.54 2.07 2.04 ns

–1 0.56 8.05 0.04 0.85 0.36 8.20 7.27 1.76 1.73 ns

–2 0.49 7.07 0.03 0.75 0.32 7.20 6.38 1.55 1.52 ns

6 mA –F 0.79 7.89 0.05 1.20 0.51 8.04 7.19 2.88 3.09 ns

Std. 0.66 6.57 0.04 1.00 0.43 6.69 5.98 2.40 2.57 ns

–1 0.56 5.59 0.04 0.85 0.36 5.69 5.09 2.04 2.19 ns

–2 0.49 4.91 0.03 0.75 0.32 5.00 4.47 1.79 1.92 ns

8 mA –F 0.79 7.89 0.05 1.20 0.51 8.04 7.19 2.88 3.09 ns

Std. 0.66 6.57 0.04 1.00 0.43 6.69 5.98 2.40 2.57 ns

–1 0.56 5.59 0.04 0.85 0.36 5.69 5.09 2.04 2.19 ns

–2 0.49 4.91 0.03 0.75 0.32 5.00 4.47 1.79 1.92 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

ProASIC®3 Flash Family FPGAs

3-34 v2.1

2.5 V LVCMOS

Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general purpose 2.5 V

applications. It uses a 5 V–tolerant input buffer and push-pull output buffer.

Table 3-43 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

2.5 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA

Max.,

mA1Max.,

mA1µA2µA2

2 mA –0.3 0.7 1.7 3.6 0.7 1.7 2 2 18 16 10 10

4 mA –0.3 0.7 1.7 3.6 0.7 1.7 4 4 18 16 10 10

6 mA –0.3 0.7 1.7 3.6 0.7 1.7 6 6 37 32 10 10

8 mA –0.3 0.7 1.7 3.6 0.7 1.7 8 8 37 32 10 10

12 mA –0.3 0.7 1.7 3.6 0.7 1.7 12 12 74 65 10 10

16 mA –0.3 0.7 1.7 3.6 0.7 1.7 16 16 87 83 10 10

24 mA –0.3 0.7 1.7 3.6 0.7 1.7 24 24 124 169 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 3-44 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

2.5 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA

Max.,

mA1Max.,

mA1µA2µA2

2 mA –0.3 0.7 1.7 3.6 0.7 1.7 2 2 18 16 10 10

4 mA –0.3 0.7 1.7 3.6 0.7 1.7 4 4 18 16 10 10

6 mA –0.3 0.7 1.7 3.6 0.7 1.7 6 6 37 32 10 10

8 mA –0.3 0.7 1.7 3.6 0.7 1.7 8 8 37 32 10 10

12 mA –0.3 0.7 1.7 3.6 0.7 1.7 12 12 74 65 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

ProASIC®3 Flash Family FPGAs

v2.1 3-35

Table 3-45 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard I/O Banks

2.5 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA

Max.,

mA1Max.,

mA1µA2µA2

2 mA –0.3 0.7 1.7 3.6 0.7 1.7 2 2 16 18 10 10

4 mA –0.3 0.7 1.7 3.6 0.7 1.7 4 4 16 18 10 10

6 mA –0.3 0.7 1.7 3.6 0.7 1.7 6 6 32 37 10 10

8 mA –0.3 0.7 1.7 3.6 0.7 1.7 8 8 32 37 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Figure 3-7 • AC Loading

Table 3-46 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF)

02.51.235

Note: *Measuring point = Vtrip. See Table 3-18 on page 3-17 for a complete table of trip points.

Test Point Test Point

Enable Path

Datapath 35 pF

R = 1 k R to VCCI for tLZ/tZL/tZLS

R to GND for tHZ/tZH/tZHS

35 pF for tZH/tZHS/tZL/tZLS

5 pF for tHZ/tLZ

ProASIC®3 Flash Family FPGAs

3-36 v2.1

Timing Characteristics

Table 3-47 • 2.5 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Advanced I/O Banks

Drive Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA –F 0.72 10.41 0.05 1.57 0.51 9.41 10.41 3.22 2.77 12.09 13.09 ns

Std. 0.60 8.66 0.04 1.31 0.43 7.83 8.66 2.68 2.30 10.07 10.90 ns

–1 0.51 7.37 0.04 1.11 0.36 6.66 7.37 2.28 1.96 8.56 9.27 ns

–2 0.45 6.47 0.03 0.98 0.32 5.85 6.47 2.00 1.72 7.52 8.14 ns

6 mA –F 0.72 6.21 0.05 1.57 0.51 6.05 6.21 3.66 3.60 8.74 8.89 ns

Std. 0.60 5.17 0.04 1.31 0.43 5.04 5.17 3.05 3.00 7.27 7.40 ns

–1 0.51 4.39 0.04 1.11 0.36 4.28 4.39 2.59 2.55 6.19 6.30 ns

–2 0.45 3.86 0.03 0.98 0.32 3.76 3.86 2.28 2.24 5.43 5.53 ns

8 mA –F 0.72 6.21 0.05 1.57 0.51 6.05 6.21 3.66 3.60 8.74 8.89 ns

Std. 0.60 5.17 0.04 1.31 0.43 5.04 5.17 3.05 3.00 7.27 7.40 ns

–1 0.51 4.39 0.04 1.11 0.36 4.28 4.39 2.59 2.55 6.19 6.30 ns

–2 0.45 3.86 0.03 0.98 0.32 3.76 3.86 2.28 2.24 5.43 5.53 ns

12 mA –F 0.72 4.28 0.05 1.57 0.51 4.36 4.12 3.97 4.13 7.04 6.81 ns

Std. 0.60 3.56 0.04 1.31 0.43 3.63 3.43 3.30 3.44 5.86 5.67 ns

–1 0.51 3.03 0.04 1.11 0.36 3.08 2.92 2.81 2.92 4.99 4.82 ns

–2 0.45 2.66 0.03 0.98 0.32 2.71 2.56 2.47 2.57 4.38 4.23 ns

16 mA –F 0.72 4.03 0.05 1.57 0.51 4.10 3.68 4.04 4.26 6.79 6.36 ns

Std. 0.60 3.35 0.04 1.31 0.43 3.41 3.06 3.36 3.55 5.65 5.30 ns

–1 0.51 2.85 0.04 1.11 0.36 2.90 2.60 2.86 3.02 4.81 4.51 ns

–2 0.45 2.50 0.03 0.98 0.32 2.55 2.29 2.51 2.65 4.22 3.96 ns

24 mA –F 0.72 3.71 0.05 1.57 0.51 3.78 2.93 4.13 4.80 6.47 5.62 ns

Std. 0.60 3.09 0.04 1.31 0.43 3.15 2.44 3.44 4.00 5.38 4.68 ns

–1 0.51 2.63 0.04 1.11 0.36 2.68 2.08 2.92 3.40 4.58 3.98 ns

–2 0.45 2.31 0.03 0.98 0.32 2.35 1.82 2.57 2.98 4.02 3.49 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

ProASIC®3 Flash Family FPGAs

v2.1 3-37

Table 3-48 • 2.5 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Advanced I/O Banks

Drive Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA –F 0.72 13.69 0.05 1.57 0.51 13.48 13.69 3.22 2.65 16.16 16.38 ns

Std. 0.60 11.40 0.04 1.31 0.43 11.22 11.40 2.68 2.20 13.45 13.63 ns

–1 0.51 9.69 0.04 1.11 0.36 9.54 9.69 2.28 1.88 11.44 11.60 ns

–2 0.45 8.51 0.03 0.98 0.32 8.38 8.51 2.00 1.65 10.05 10.18 ns

6 mA –F 0.72 9.56 0.05 1.57 0.51 9.74 9.39 3.66 3.47 12.43 12.07 ns

Std. 0.60 7.96 0.04 1.31 0.43 8.11 7.81 3.05 2.89 10.34 10.05 ns

–1 0.51 6.77 0.04 1.11 0.36 6.90 6.65 2.59 2.46 8.80 8.55 ns

–2 0.45 5.94 0.03 0.98 0.32 6.05 5.84 2.28 2.16 7.72 7.50 ns

8 mA –F 0.72 9.56 0.05 1.57 0.51 9.74 9.39 3.66 3.47 12.43 12.07 ns

Std. 0.60 7.96 0.04 1.31 0.43 8.11 7.81 3.05 2.89 10.34 10.05 ns

–1 0.51 6.77 0.04 1.11 0.36 6.90 6.65 2.59 2.46 8.80 8.55 ns

–2 0.45 5.94 0.03 0.98 0.32 6.05 5.84 2.28 2.16 7.72 7.50 ns

12 mA –F 0.72 7.42 0.05 1.57 0.51 7.56 7.11 3.97 3.99 10.25 9.80 ns

Std. 0.60 6.18 0.04 1.31 0.43 6.29 5.92 3.30 3.32 8.53 8.15 ns

–1 0.51 5.26 0.04 1.11 0.36 5.35 5.03 2.81 2.83 7.26 6.94 ns

–2 0.45 4.61 0.03 0.98 0.32 4.70 4.42 2.47 2.48 6.37 6.09 ns

16 mA –F 0.72 6.92 0.05 1.57 0.51 7.05 6.64 4.04 4.13 9.74 9.32 ns

Std. 0.60 5.76 0.04 1.31 0.43 5.87 5.53 3.36 3.44 8.11 7.76 ns

–1 0.51 4.90 0.04 1.11 0.36 4.99 4.70 2.86 2.92 6.90 6.60 ns

–2 0.45 4.30 0.03 0.98 0.32 4.38 4.13 2.51 2.57 6.05 5.80 ns

24 mA –F 0.72 6.61 0.05 1.57 0.51 6.61 6.61 4.13 4.65 9.30 9.30 ns

Std. 0.60 5.51 0.04 1.31 0.43 5.50 5.51 3.43 3.87 7.74 7.74 ns

–1 0.51 4.68 0.04 1.11 0.36 4.68 4.68 2.92 3.29 6.58 6.59 ns

–2 0.45 4.11 0.03 0.98 0.32 4.11 4.11 2.56 2.89 5.78 5.78 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

ProASIC®3 Flash Family FPGAs

3-38 v2.1

Table 3-49 • 2.5 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Standard Plus I/O Banks

Drive Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA –F 0.79 9.94 0.05 1.56 0.51 8.90 9.94 2.70 2.49 11.58 12.63 ns

Std. 0.66 8.28 0.04 1.30 0.43 7.41 8.28 2.25 2.07 9.64 10.51 ns

–1 0.56 7.04 0.04 1.10 0.36 6.30 7.04 1.92 1.76 8.20 8.94 ns

–2 0.49 6.18 0.03 0.97 0.32 5.53 6.18 1.68 1.55 7.20 7.85 ns

6 mA –F 0.79 5.83 0.05 1.56 0.51 5.58 5.83 3.11 3.26 8.27 8.52 ns

Std. 0.66 4.85 0.04 1.30 0.43 4.65 4.85 2.59 2.71 6.88 7.09 ns

–1 0.56 4.13 0.04 1.10 0.36 3.95 4.13 2.20 2.31 5.85 6.03 ns

–2 0.49 3.62 0.03 0.97 0.32 3.47 3.62 1.93 2.02 5.14 5.29 ns

8 mA –F 0.79 5.83 0.05 1.56 0.51 5.58 5.83 3.11 3.26 8.27 8.52 ns

Std. 0.66 4.85 0.04 1.30 0.43 4.65 4.85 2.59 2.71 6.88 7.09 ns

–1 0.56 4.13 0.04 1.10 0.36 3.95 4.13 2.20 2.31 5.85 6.03 ns

–2 0.49 3.62 0.03 0.97 0.32 3.47 3.62 1.93 2.02 5.14 5.29 ns

12 mA –F 0.79 3.85 0.05 1.56 0.51 3.92 3.77 3.39 3.74 6.61 6.46 ns

Std. 0.66 3.21 0.04 1.30 0.43 3.27 3.14 2.82 3.11 5.50 5.38 ns

–1 0.56 2.73 0.04 1.10 0.36 2.78 2.67 2.40 2.65 4.68 4.57 ns

–2 0.49 2.39 0.03 0.97 0.32 2.44 2.35 2.11 2.32 4.11 4.02 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

Table 3-50 • 2.5 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Standard Plus I/O Banks

Drive Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA –F 0.79 13.02 0.05 1.56 0.51 12.78 13.02 2.71 2.39 15.46 15.71 ns

Std. 0.66 10.84 0.04 1.30 0.43 10.64 10.84 2.26 1.99 12.87 13.08 ns

–1 0.56 9.22 0.04 1.10 0.36 9.05 9.22 1.92 1.69 10.95 11.12 ns

–2 0.49 8.10 0.03 0.97 0.32 7.94 8.10 1.68 1.49 9.61 9.77 ns

6 mA –F 0.79 8.85 0.05 1.56 0.51 9.01 8.84 3.11 3.14 11.70 11.53 ns

Std. 0.66 7.37 0.04 1.30 0.43 7.50 7.36 2.59 2.61 9.74 9.60 ns

–1 0.56 6.27 0.04 1.10 0.36 6.38 6.26 2.20 2.22 8.29 8.16 ns

–2 0.49 5.50 0.03 0.97 0.32 5.60 5.50 1.93 1.95 7.27 7.17 ns

8 mA –F 0.79 8.85 0.05 1.56 0.51 9.01 8.84 3.11 3.14 11.70 11.53 ns

Std. 0.66 7.37 0.04 1.30 0.43 7.50 7.36 2.59 2.61 9.74 9.60 ns

–1 0.56 6.27 0.04 1.10 0.36 6.38 6.26 2.20 2.22 8.29 8.16 ns

–2 0.49 5.50 0.03 0.97 0.32 5.60 5.50 1.93 1.95 7.27 7.17 ns

ProASIC®3 Flash Family FPGAs

v2.1 3-39

12 mA –F 0.79 6.76 0.05 1.56 0.51 6.89 6.61 3.40 3.62 9.57 9.30 ns

Std. 0.66 5.63 0.04 1.30 0.43 5.73 5.51 2.83 3.01 7.97 7.74 ns

–1 0.56 4.79 0.04 1.10 0.36 4.88 4.68 2.41 2.56 6.78 6.59 ns

–2 0.49 4.20 0.03 0.97 0.32 4.28 4.11 2.11 2.25 5.95 5.78 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

Table 3-51 • 2.5 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard I/O Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units

2 mA –F 0.79 9.86 0.05 1.55 0.51 8.70 9.86 2.44 2.29 ns

Std. 0.66 8.20 0.04 1.29 0.43 7.24 8.20 2.03 1.91 ns

–1 0.56 6.98 0.04 1.10 0.36 6.16 6.98 1.73 1.62 ns

–2 0.49 6.13 0.03 0.96 0.32 5.41 6.13 1.52 1.43 ns

4 mA –F 0.79 9.86 0.05 1.55 0.51 8.70 9.86 2.44 2.29 ns

Std. 0.66 8.20 0.04 1.29 0.43 7.24 8.20 2.03 1.91 ns

–1 0.56 6.98 0.04 1.10 0.36 6.16 6.98 1.73 1.62 ns

–2 0.49 6.13 0.03 0.96 0.32 5.41 6.13 1.52 1.43 ns

6 mA –F 0.79 5.72 0.05 1.55 0.51 5.47 5.72 2.86 3.07 ns

Std. 0.66 4.77 0.04 1.29 0.43 4.55 4.77 2.38 2.55 ns

–1 0.56 4.05 0.04 1.10 0.36 3.87 4.05 2.03 2.17 ns

–2 0.49 3.56 0.03 0.96 0.32 3.40 3.56 1.78 1.91 ns

8 mA –F 0.79 5.72 0.05 1.55 0.51 5.47 5.72 2.86 3.07 ns

Std. 0.66 4.77 0.04 1.29 0.43 4.55 4.77 2.38 2.55 ns

–1 0.56 4.05 0.04 1.10 0.36 3.87 4.05 2.03 2.17 ns

–2 0.49 3.56 0.03 0.96 0.32 3.40 3.56 1.78 1.91 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

Table 3-50 • 2.5 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Standard Plus I/O Banks

Drive Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

ProASIC®3 Flash Family FPGAs

3-40 v2.1

Table 3-52 • 2.5 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units

2 mA –F 0.79 13.21 0.05 1.55 0.51 12.46 13.21 2.44 2.20 ns

Std. 0.66 11.00 0.04 1.29 0.43 10.37 11.00 2.03 1.83 ns

–1 0.56 9.35 0.04 1.10 0.36 8.83 9.35 1.73 1.56 ns

–2 0.49 8.21 0.03 0.96 0.32 7.75 8.21 1.52 1.37 ns

4 mA –F 0.79 13.21 0.05 1.55 0.51 12.46 13.21 2.44 2.20 ns

Std. 0.66 11.00 0.04 1.29 0.43 10.37 11.00 2.03 1.83 ns

–1 0.56 9.35 0.04 1.10 0.36 8.83 9.35 1.73 1.56 ns

–2 0.49 8.21 0.03 0.96 0.32 7.75 8.21 1.52 1.37 ns

6 mA –F 0.79 9.01 0.05 1.55 0.51 8.84 9.01 2.87 2.96 ns

Std. 0.66 7.50 0.04 1.29 0.43 7.36 7.50 2.39 2.46 ns

–1 0.56 6.38 0.04 1.10 0.36 6.26 6.38 2.03 2.10 ns

–2 0.49 5.60 0.03 0.96 0.32 5.49 5.60 1.78 1.84 ns

8 mA –F 0.79 9.01 0.05 1.55 0.51 8.84 9.01 2.87 2.96 ns

Std. 0.66 7.50 0.04 1.29 0.43 7.36 7.50 2.39 2.46 ns

–1 0.56 6.38 0.04 1.10 0.36 6.26 6.38 2.03 2.10 ns

–2 0.49 5.60 0.03 0.96 0.32 5.49 5.60 1.78 1.84 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

ProASIC®3 Flash Family FPGAs

v2.1 3-41

1.8 V LVCMOS

Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-purpose 1.8 V

applications. It uses a 1.8 V input buffer and a push-pull output buffer.

Table 3-53 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

1.8 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA

Max.,

mA1Max.,

mA1µA2µA2

2 mA –0.3 0.35 *

VCCI

0.65 * VCCI 3.6 0.45 VCCI – 0.45 2 2 11 9 10 10

4 mA –0.3 0.35 *

VCCI

0.65 * VCCI 3.6 0.45 VCCI – 0.45 4 4 22 17 10 10

6 mA –0.3 0.35 *

VCCI

0.65 * VCCI 3.6 0.45 VCCI – 0.45 6 6 44 35 10 10

8 mA –0.3 0.35 *

VCCI

0.65 * VCCI 3.6 0.45 VCCI – 0.45 8 8 51 45 10 10

12 mA –0.3 0.35 *

VCCI

0.65 * VCCI 3.6 0.45 VCCI – 0.45 12 12 74 91 10 10

16 mA –0.3 0.35 *

VCCI

0.65 * VCCI 3.6 0.45 VCCI – 0.45 16 16 74 91 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 3-54 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O I/O Banks

1.8 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA

Max.,

mA1Max.,

mA1µA2µA2

2 mA –0.3 0.35 *

VCCI

0.65 * VCCI 3.6 0.45 VCCI – 0.45 2 2 11 9 10 10

4 mA –0.3 0.35 *

VCCI

0.65 * VCCI 3.6 0.45 VCCI – 0.45 4 4 22 17 10 10

6 mA –0.3 0.35 *

VCCI

0.65 * VCCI 3.6 0.45 VCCI – 0.45 6 6 44 35 10 10

8 mA –0.3 0.35 *

VCCI

0.65 * VCCI 3.6 0.45 V CCI – 0.45 8 8 44 35 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

ProASIC®3 Flash Family FPGAs

3-42 v2.1

Table 3-55 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard I/O Banks

1.8 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA

Max.,

mA1Max.,

mA1µA2µA2

2 mA –0.3 0.35 *

VCCI

0.65 *

VCCI

3.6 0.45 VCCI –

0.45

2 2 9 11 10 10

4 mA –0.3 0.35 *

VCCI

0.65 *

VCCI

3.6 0.45 VCCI –

0.45

4 4 17 22 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Figure 3-8 • AC Loading

Table 3-56 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF)

01.80.935

Note: *Measuring point = Vtrip. See Table 3-18 on page 3-17 for a complete table of trip points.

Test Point Test Point

Enable Path

Datapath 35 pF

R = 1 k R to VCCI for tLZ/tZL/tZLS

R to GND for tHZ/tZH/tZHS

35 pF for tZH/tZHS/tZL/tZLS

5 pF for tHZ/tLZ

ProASIC®3 Flash Family FPGAs

v2.1 3-43

Timing Characteristics

Table 3-57 • 1.8 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Applicable to Advanced I/O Banks

Drive Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA –F 0.79 14.25 0.05 1.46 0.51 10.97 14.25 3.33 1.99 13.66 16.94 ns

Std. 0.66 11.86 0.04 1.22 0.43 9.14 11.86 2.77 1.66 11.37 14.10 ns

–1 0.56 10.09 0.04 1.04 0.36 7.77 10.09 2.36 1.41 9.67 11.99 ns

–2 0.49 8.86 0.03 0.91 0.32 6.82 8.86 2.07 1.24 8.49 10.53 ns

4 mA –F 0.79 8.31 0.05 1.46 0.51 7.04 8.31 3.87 3.41 9.73 10.99 ns

Std. 0.66 6.91 0.04 1.22 0.43 5.86 6.91 3.22 2.84 8.10 9.15 ns

–1 0.56 5.88 0.04 1.04 0.36 4.99 5.88 2.74 2.41 6.89 7.78 ns

–2 0.49 5.16 0.03 0.91 0.32 4.38 5.16 2.41 2.12 6.05 6.83 ns

6 mA –F 0.79 5.34 0.05 1.46 0.51 5.02 5.34 4.24 4.06 7.71 8.03 ns

Std. 0.66 4.45 0.04 1.22 0.43 4.18 4.45 3.53 3.38 6.42 6.68 ns

–1 0.56 3.78 0.04 1.04 0.36 3.56 3.78 3.00 2.88 5.46 5.69 ns

–2 0.49 3.32 0.03 0.91 0.32 3.12 3.32 2.64 2.53 4.79 4.99 ns

8 mA –F 0.79 4.71 0.05 1.46 0.51 4.72 4.71 4.32 4.23 7.40 7.40 ns

Std. 0.66 3.92 0.04 1.22 0.43 3.93 3.92 3.60 3.52 6.16 6.16 ns

–1 0.56 3.34 0.04 1.04 0.36 3.34 3.34 3.06 3.00 5.24 5.24 ns

–2 0.49 2.93 0.03 0.91 0.32 2.93 2.93 2.69 2.63 4.60 4.60 ns

12 mA –F 0.79 4.24 0.05 1.46 0.51 4.32 3.65 4.45 4.90 7.01 6.34 ns

Std. 0.66 3.53 0.04 1.22 0.43 3.60 3.04 3.70 4.08 5.84 5.28 ns

–1 0.56 3.01 0.04 1.04 0.36 3.06 2.59 3.15 3.47 4.96 4.49 ns

–2 0.49 2.64 0.03 0.91 0.32 2.69 2.27 2.76 3.05 4.36 3.94 ns

16 mA –F 0.79 4.24 0.05 1.46 0.51 4.32 3.65 4.45 4.90 7.01 6.34 ns

Std. 0.66 3.53 0.04 1.22 0.43 3.60 3.04 3.70 4.08 5.84 5.28 ns

–1 0.56 3.01 0.04 1.04 0.36 3.06 2.59 3.15 3.47 4.96 4.49 ns

–2 0.49 2.64 0.03 0.91 0.32 2.69 2.27 2.76 3.05 4.36 3.94 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

ProASIC®3 Flash Family FPGAs

3-44 v2.1

Table 3-58 • 1.8 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Applicable to Advanced I/O Banks

Drive Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA –F 0.79 18.66 0.05 1.46 0.51 16.95 18.66 3.34 1.92 19.64 21.34 ns

Std. 0.66 15.53 0.04 1.22 0.43 14.11 15.53 2.78 1.60 16.35 17.77 ns

–1 0.56 13.21 0.04 1.04 0.36 12.01 13.21 2.36 1.36 13.91 15.11 ns

–2 0.49 11.60 0.03 0.91 0.32 10.54 11.60 2.07 1.19 12.21 13.27 ns

4 mA –F 0.79 12.58 0.05 1.46 0.51 12.51 12.58 3.88 3.28 15.19 15.27 ns

Std. 0.66 10.48 0.04 1.22 0.43 10.41 10.48 3.23 2.73 12.65 12.71 ns

–1 0.56 8.91 0.04 1.04 0.36 8.86 8.91 2.75 2.33 10.76 10.81 ns

–2 0.49 7.82 0.03 0.91 0.32 7.77 7.82 2.41 2.04 9.44 9.49 ns

6 mA –F 0.79 9.67 0.05 1.46 0.51 9.85 9.42 4.25 3.93 12.53 12.11 ns

Std. 0.66 8.05 0.04 1.22 0.43 8.20 7.84 3.54 3.27 10.43 10.08 ns

–1 0.56 6.85 0.04 1.04 0.36 6.97 6.67 3.01 2.78 8.88 8.57 ns

–2 0.49 6.01 0.03 0.91 0.32 6.12 5.86 2.64 2.44 7.79 7.53 ns

8 mA –F 0.79 9.01 0.05 1.46 0.51 9.18 8.77 4.33 4.10 11.87 11.45 ns

Std. 0.66 7.50 0.04 1.22 0.43 7.64 7.30 3.61 3.41 9.88 9.53 ns

–1 0.56 6.38 0.04 1.04 0.36 6.50 6.21 3.07 2.90 8.40 8.11 ns

–2 0.49 5.60 0.03 0.91 0.32 5.71 5.45 2.69 2.55 7.38 7.12 ns

12 mA –F 0.79 8.76 0.05 1.46 0.51 8.69 8.76 4.45 4.74 11.38 11.45 ns

Std. 0.66 7.29 0.04 1.22 0.43 7.23 7.29 3.71 3.95 9.47 9.53 ns

–1 0.56 6.20 0.04 1.04 0.36 6.15 6.20 3.15 3.36 8.06 8.11 ns

–2 0.49 5.45 0.03 0.91 0.32 5.40 5.45 2.77 2.95 7.07 7.12 ns

16 mA –F 0.79 8.76 0.05 1.46 0.51 8.69 8.76 4.45 4.74 11.38 11.45 ns

Std. 0.66 7.29 0.04 1.22 0.43 7.23 7.29 3.71 3.95 9.47 9.53 ns

–1 0.56 6.20 0.04 1.04 0.36 6.15 6.20 3.15 3.36 8.06 8.11 ns

–2 0.49 5.45 0.03 0.91 0.32 5.40 5.45 2.77 2.95 7.07 7.12 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

ProASIC®3 Flash Family FPGAs

v2.1 3-45

Table 3-59 • 1.8 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Applicable to Standard Plus I/O Banks

Drive Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA –F 0.79 13.61 0.05 1.44 0.51 10.48 13.61 2.70 1.83 13.17 16.30 ns

Std. 0.66 11.33 0.04 1.20 0.43 8.72 11.33 2.24 1.52 10.96 13.57 ns

–1 0.56 9.64 0.04 1.02 0.36 7.42 9.64 1.91 1.29 9.32 11.54 ns

–2 0.49 8.46 0.03 0.90 0.32 6.51 8.46 1.68 1.14 8.18 10.13 ns

4 mA –F 0.79 7.79 0.05 1.44 0.51 6.58 7.79 3.18 3.13 9.27 10.47 ns

Std. 0.66 6.48 0.04 1.20 0.43 5.48 6.48 2.65 2.60 7.72 8.72 ns

–1 0.56 5.51 0.04 1.02 0.36 4.66 5.51 2.25 2.21 6.56 7.42 ns

–2 0.49 4.84 0.03 0.90 0.32 4.09 4.84 1.98 1.94 5.76 6.51 ns

6 mA –F 0.79 4.88 0.05 1.44 0.51 4.61 4.88 3.52 3.73 7.30 7.56 ns

Std. 0.66 4.06 0.04 1.20 0.43 3.84 4.06 2.93 3.10 6.07 6.30 ns

–1 0.56 3.45 0.04 1.02 0.36 3.27 3.45 2.49 2.64 5.17 5.36 ns

–2 0.49 3.03 0.03 0.90 0.32 2.87 3.03 2.19 2.32 4.54 4.70 ns

8 mA –F 0.79 4.88 0.05 1.44 0.51 4.61 4.88 3.52 3.73 7.30 7.56 ns

Std. 0.66 4.06 0.04 1.20 0.43 3.84 4.06 2.93 3.10 6.07 6.30 ns

–1 0.56 3.45 0.04 1.02 0.36 3.27 3.45 2.49 2.64 5.17 5.36 ns

–2 0.49 3.03 0.03 0.90 0.32 2.87 3.03 2.19 2.32 4.54 4.70 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

ProASIC®3 Flash Family FPGAs

3-46 v2.1

Table 3-60 • 1.8 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Applicable to Standard Plus I/O Banks

Drive Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA –F 0.79 17.78 0.05 1.44 0.51 16.21 17.78 2.70 1.76 18.90 20.47 ns

Std. 0.66 14.80 0.04 1.20 0.43 13.49 14.80 2.25 1.46 15.73 17.04 ns

–1 0.56 12.59 0.04 1.02 0.36 11.48 12.59 1.91 1.25 13.38 14.49 ns

–2 0.49 11.05 0.03 0.90 0.32 10.08 11.05 1.68 1.09 11.75 12.72 ns

4 mA –F 0.79 11.89 0.05 1.44 0.51 11.69 11.89 3.19 3.00 14.38 14.58 ns

Std. 0.66 9.90 0.04 1.20 0.43 9.73 9.90 2.65 2.50 11.97 12.13 ns

–1 0.56 8.42 0.04 1.02 0.36 8.28 8.42 2.26 2.12 10.18 10.32 ns

–2 0.49 7.39 0.03 0.90 0.32 7.27 7.39 1.98 1.86 8.94 9.06 ns

6 mA –F 0.79 8.93 0.05 1.44 0.51 9.10 8.79 3.53 3.59 11.79 11.48 ns

Std. 0.66 7.44 0.04 1.20 0.43 7.58 7.32 2.94 2.99 9.81 9.56 ns

–1 0.56 6.33 0.04 1.02 0.36 6.44 6.23 2.50 2.54 8.35 8.13 ns

–2 0.49 5.55 0.03 0.90 0.32 5.66 5.47 2.19 2.23 7.33 7.14 ns

8 mA –F 0.79 8.93 0.05 1.44 0.51 9.10 8.79 3.53 3.59 11.79 11.48 ns

Std. 0.66 7.44 0.04 1.20 0.43 7.58 7.32 2.94 2.99 9.81 9.56 ns

–1 0.56 6.33 0.04 1.02 0.36 6.44 6.23 2.50 2.54 8.35 8.13 ns

–2 0.49 5.55 0.03 0.90 0.32 5.66 5.47 2.19 2.23 7.33 7.14 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

ProASIC®3 Flash Family FPGAs

v2.1 3-47

Table 3-61 • 1.8 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard I/O Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units

2 mA –F 0.79 13.47 0.05 1.44 0.51 10.25 13.47 2.39 1.45 ns

Std. 0.66 11.21 0.04 1.20 0.43 8.53 11.21 1.99 1.21 ns

–1 0.56 9.54 0.04 1.02 0.36 7.26 9.54 1.69 1.03 ns

–2 0.49 8.37 0.03 0.90 0.32 6.37 8.37 1.49 0.90 ns

4 mA –F 0.79 7.62 0.05 1.44 0.51 6.46 7.62 2.89 2.98 ns

Std. 0.66 6.34 0.04 1.20 0.43 5.38 6.34 2.41 2.48 ns

–1 0.56 5.40 0.04 1.02 0.36 4.58 5.40 2.05 2.11 ns

–2 0.49 4.74 0.03 0.90 0.32 4.02 4.74 1.80 1.85 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

Table 3-62 • 1.8 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units

2 mA –F 0.79 18.03 0.05 1.44 0.51 15.80 18.03 2.40 2.40 ns

Std. 0.66 15.01 0.04 1.20 0.43 13.15 15.01 1.99 1.99 ns

–1 0.56 12.77 0.04 1.02 0.36 11.19 12.77 1.70 1.70 ns

–2 0.49 11.21 0.03 0.90 0.32 9.82 11.21 1.49 1.49 ns

4 mA –F 0.79 12.13 0.05 1.44 0.51 11.48 12.13 2.90 2.85 ns

Std. 0.66 10.10 0.04 1.20 0.43 9.55 10.10 2.41 2.37 ns

–1 0.56 8.59 0.04 1.02 0.36 8.13 8.59 2.05 2.02 ns

–2 0.49 7.54 0.03 0.90 0.32 7.13 7.54 1.80 1.77 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

ProASIC®3 Flash Family FPGAs

3-48 v2.1

1.5 V LVCMOS (JESD8-11)

Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-purpose 1.5 V

applications. It uses a 1.5 V input buffer and a push-pull output buffer.

Table 3-63 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

1.5 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA

Max.,

mA1Max.,

mA1µA2µA2

2 mA –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 2 2 16 13 10 10

4 mA –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 4 4 33 25 10 10

6 mA –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 6 6 39 32 10 10

8 mA –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 8 8 55 66 10 10

12 mA –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 12 12 55 66 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 3-64 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

1.5 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA

Max.,

mA1Max.,

mA1µA2µA2

2 mA –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 2 2 0 0 10 10

4 mA –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 4 4 0 0 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 3-65 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard I/O Banks

1.5 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA

Max.,

mA1Max.,

mA1µA2µA2

2 mA –0.3 0.30 *

VCCI

0.7 *

VCCI

3.6 0.25 *

VCCI

0.75 *

VCCI

2 2 13 16 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

ProASIC®3 Flash Family FPGAs

v2.1 3-49

Figure 3-9 • AC Loading

Table 3-66 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF)

0 1.5 0.75 35

Note: *Measuring point = Vtrip. See Table 3-18 on page 3-17 for a complete table of trip points.

Test Point Test Point

Enable Path

Datapath 35 pF

R = 1 k R to VCCI for tLZ/tZL/tZLS

R to GND for tHZ/tZH/tZHS

35 pF for tZH/tZHS/tZL/tZLS

5 pF for tHZ/tLZ

ProASIC®3 Flash Family FPGAs

3-50 v2.1

Timing Characteristics

Table 3-67 • 1.5 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Applicable to Advanced I/O Banks

Drive Strength

Speed

Grade

tDOUT tDP tDIN tPY tEOUT t ZL tZH tLZ tHZ tZLS tZHS Units

2 mA –F 0.79 10.05 0.05 1.73 0.51 8.20 10.05 4.07 3.32 10.88 12.73 ns

Std. 0.66 8.36 0.04 1.44 0.43 6.82 8.36 3.39 2.77 9.06 10.60 ns

–1 0.56 7.11 0.04 1.22 0.36 5.80 7.11 2.88 2.35 7.71 9.02 ns

–2 0.49 6.24 0.03 1.07 0.32 5.10 6.24 2.53 2.06 6.76 7.91 ns

4 mA –F 0.79 6.38 0.05 1.73 0.51 5.83 6.38 4.49 4.09 8.51 9.07 ns

Std. 0.66 5.31 0.04 1.44 0.43 4.85 5.31 3.74 3.40 7.09 7.55 ns

–1 0.56 4.52 0.04 1.22 0.36 4.13 4.52 3.18 2.89 6.03 6.42 ns

–2 0.49 3.97 0.03 1.07 0.32 3.62 3.97 2.79 2.54 5.29 5.64 ns

6 mA –F 0.79 5.61 0.05 1.73 0.51 5.46 5.61 4.59 4.28 8.15 8.29 ns

Std. 0.66 4.67 0.04 1.44 0.43 4.55 4.67 3.82 3.56 6.78 6.90 ns

–1 0.56 3.97 0.04 1.22 0.36 3.87 3.97 3.25 3.03 5.77 5.87 ns

–2 0.49 3.49 0.03 1.07 0.32 3.40 3.49 2.85 2.66 5.07 5.16 ns

8 mA –F 0.79 4.90 0.05 1.73 0.51 4.99 4.30 4.74 5.05 7.68 6.98 ns

Std. 0.66 4.08 0.04 1.44 0.43 4.15 3.58 3.94 4.20 6.39 5.81 ns

–1 0.56 3.47 0.04 1.22 0.36 3.53 3.04 3.36 3.58 5.44 4.95 ns

–2 0.49 3.05 0.03 1.07 0.32 3.10 2.67 2.95 3.14 4.77 4.34 ns

12 mA –F 0.79 4.90 0.05 1.73 0.51 4.99 4.30 4.74 5.05 7.68 6.98 ns

Std. 0.66 4.08 0.04 1.44 0.43 4.15 3.58 3.94 4.20 6.39 5.81 ns

–1 0.56 3.47 0.04 1.22 0.36 3.53 3.04 3.36 3.58 5.44 4.95 ns

–2 0.49 3.05 0.03 1.07 0.32 3.10 2.67 2.95 3.14 4.77 4.34 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

Table 3-68 • 1.5 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Applicable to Advanced I/O Banks

Drive Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA –F 0.79 15.36 0.05 1.73 0.51 15.39 15.36 4.08 3.18 18.07 18.04 ns

Std. 0.66 12.78 0.04 1.44 0.43 12.81 12.78 3.40 2.64 15.05 15.02 ns

–1 0.56 10.87 0.04 1.22 0.36 10.90 10.87 2.89 2.25 12.80 12.78 ns

–2 0.49 9.55 0.03 1.07 0.32 9.57 9.55 2.54 1.97 11.24 11.22 ns

ProASIC®3 Flash Family FPGAs

v2.1 3-51

4 mA –F 0.79 12.02 0.05 1.73 0.51 12.25 11.47 4.50 3.93 14.93 14.15 ns

Std. 0.66 10.01 0.04 1.44 0.43 10.19 9.55 3.75 3.27 12.43 11.78 ns

–1 0.56 8.51 0.04 1.22 0.36 8.67 8.12 3.19 2.78 10.57 10.02 ns

–2 0.49 7.47 0.03 1.07 0.32 7.61 7.13 2.80 2.44 9.28 8.80 ns

6 mA –F 0.79 11.21 0.05 1.73 0.51 11.42 10.68 4.60 4.12 14.11 13.37 ns

Std. 0.66 9.33 0.04 1.44 0.43 9.51 8.89 3.83 3.43 11.74 11.13 ns

–1 0.56 7.94 0.04 1.22 0.36 8.09 7.56 3.26 2.92 9.99 9.47 ns

–2 0.49 6.97 0.03 1.07 0.32 7.10 6.64 2.86 2.56 8.77 8.31 ns

8 mA –F 0.79 10.70 0.05 1.73 0.51 10.90 10.68 4.75 4.86 13.59 13.37 ns

Std. 0.66 8.91 0.04 1.44 0.43 9.07 8.89 3.95 4.05 11.31 11.13 ns

–1 0.56 7.58 0.04 1.22 0.36 7.72 7.57 3.36 3.44 9.62 9.47 ns

–2 0.49 6.65 0.03 1.07 0.32 6.78 6.64 2.95 3.02 8.45 8.31 ns

12 mA –F 0.79 10.70 0.05 1.73 0.51 10.90 10.68 4.75 4.86 13.59 13.37 ns

Std. 0.66 8.91 0.04 1.44 0.43 9.07 8.89 3.95 4.05 11.31 11.13 ns

–1 0.56 7.58 0.04 1.22 0.36 7.72 7.57 3.36 3.44 9.62 9.47 ns

–2 0.49 6.65 0.03 1.07 0.32 6.78 6.64 2.95 3.02 8.45 8.31 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

Table 3-69 • 1.5 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Applicable to Standard Plus I/O Banks

Drive Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA –F 0.79 9.41 0.05 1.71 0.51 7.71 9.41 3.25 3.06 10.40 12.09 ns

Std. 0.66 7.83 0.04 1.42 0.43 6.42 7.83 2.71 2.55 8.65 10.07 ns

–1 0.56 6.66 0.04 1.21 0.36 5.46 6.66 2.31 2.17 7.36 8.56 ns

–2 0.49 5.85 0.03 1.06 0.32 4.79 5.85 2.02 1.90 6.46 7.52 ns

4 mA –F 0.79 5.81 0.05 1.71 0.51 5.39 5.81 3.64 3.76 8.08 8.50 ns

Std. 0.66 4.84 0.04 1.42 0.43 4.49 4.84 3.03 3.13 6.72 7.08 ns

–1 0.56 4.12 0.04 1.21 0.36 3.82 4.12 2.58 2.66 5.72 6.02 ns

–2 0.49 3.61 0.03 1.06 0.32 3.35 3.61 2.26 2.34 5.02 5.28 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

Table 3-68 • 1.5 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Applicable to Advanced I/O Banks

Drive Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

ProASIC®3 Flash Family FPGAs

3-52 v2.1

Table 3-70 • 1.5 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Applicable to Standard Plus I/O Banks

Drive Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA –F 0.79 14.51 0.05 1.71 0.51 14.42 14.51 3.26 2.91 17.11 17.20 ns

Std. 0.66 12.08 0.04 1.42 0.43 12.01 12.08 2.72 2.43 14.24 14.31 ns

–1 0.56 10.27 0.04 1.21 0.36 10.21 10.27 2.31 2.06 12.12 12.18 ns

–2 0.49 9.02 0.03 1.06 0.32 8.97 9.02 2.03 1.81 10.64 10.69 ns

4 mA –F 0.79 11.15 0.05 1.71 0.51 11.35 10.71 3.65 3.60 14.04 13.40 ns

Std. 0.66 9.28 0.04 1.42 0.43 9.45 8.91 3.04 3.00 11.69 11.15 ns

–1 0.56 7.89 0.04 1.21 0.36 8.04 7.58 2.58 2.55 9.94 9.49 ns

–2 0.49 6.93 0.03 1.06 0.32 7.06 6.66 2.27 2.24 8.73 8.33 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

Table 3-71 • 1.5 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard I/O Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units

2 mA –F 0.79 9.18 0.05 1.70 0.51 7.58 9.18 2.94 2.94 ns

Std. 0.66 7.65 0.04 1.42 0.43 6.31 7.65 2.45 2.45 ns

–1 0.56 6.50 0.04 1.21 0.36 5.37 6.50 2.08 2.08 ns

–2 0.49 5.71 0.03 1.06 0.32 4.71 5.71 1.83 1.83 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

Table 3-72 • 1.5 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units

2 mA –F 0.79 14.81 0.05 1.70 0.51 14.17 14.81 2.94 2.79 ns

Std. 0.66 12.33 0.04 1.42 0.43 11.79 12.33 2.45 2.32 ns

–1 0.56 10.49 0.04 1.21 0.36 10.03 10.49 2.08 1.98 ns

–2 0.49 9.21 0.03 1.06 0.32 8.81 9.21 1.83 1.73 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

ProASIC®3 Flash Family FPGAs

v2.1 3-53

3.3 V PCI, 3.3 V PCI-X

Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus applications.

AC loadings are defined per the PCI/PCI-X specifications for the datapath; Actel loadings for enable path

characterization are described in Figure 3-10.

AC loadings are defined per PCI/PCI-X specifications for the datapath; Actel loading for tristate is described in Table 3-74.

Timing Characteristics

Table 3-73 • Minimum and Maximum DC Input and Output Levels

3.3 V PCI/PCI-X VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive Strength Min, V Max, V Min, V Max, V Max, V Min, V mA mA Max, mA1Max, mA1µA2µA2

Per PCI specification Per PCI curves 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

Figure 3-10 • AC Loading

Table 3-74 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF)

0 3.3 0.285 * VCCI for tDP(R)

0.615 * VCCI for tDP(F)

Note: *Measuring point = Vtrip. See Table 3-18 on page 3-17 for a complete table of trip points.

Table 3-75 • 3.3 V PCI/PCI-X

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Advanced I/O Banks

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

–F 0.79 3.22 0.05 1.04 0.51 3.28 2.34 3.86 4.30 5.97 5.03 ns

Std. 0.66 2.68 0.04 0.86 0.43 2.73 1.95 3.21 3.58 4.97 4.19 ns

–1 0.56 2.28 0.04 0.73 0.36 2.32 1.66 2.73 3.05 4.22 3.56 ns

–2 0.49 2.00 0.03 0.65 0.32 2.04 1.46 2.40 2.68 3.71 3.13 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

Table 3-76 • 3.3 V PCI/PCI-X

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Plus I/O Banks

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

–F 0.79 2.77 0.05 1.02 0.51 2.82 2.05 3.35 3.87 5.51 4.73 ns

Std. 0.66 2.31 0.04 0.85 0.43 2.35 1.70 2.79 3.22 4.59 3.94 ns

–1 0.56 1.96 0.04 0.72 0.36 2.00 1.45 2.37 2.74 3.90 3.35 ns

–2 0.49 1.72 0.03 0.64 0.32 1.76 1.27 2.08 2.41 3.42 2.94 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

Test Point

Enable Path

R to V for t /t /t

CCI LZ ZL ZLS

10 pF for t /t /t /t

ZH ZHS ZLSZL

5 pF for tHZ /tLZ

R to GND for t /t /t

HZ ZH ZH

R = 1 k

Test Point

Datapath

R = 25 R to VCCI for tDP (F)

R to GND for tDP (R)

ProASIC®3 Flash Family FPGAs

3-54 v2.1

Differential I/O Characteristics

Physical Implementation

Configuration of the I/O modules as a differential pair is

handled by Actel Designer software when the user

instantiates a differential I/O macro in the design.

Differential I/Os can also be used in conjunction with the

embedded Input Register (InReg), Output Register

(OutReg), Enable Register (EnReg), and Double Data

Rate (DDR). However, there is no support for

bidirectional I/Os or tristates with the LVPECL standards.

LVDS

Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is

a high-speed, differential I/O standard. It requires that

one data bit be carried through two signal lines, so two

pins are needed. It also requires external resistor

termination.

The full implementation of the LVDS transmitter and

receiver is shown in an example in Figure 3-11. The

building blocks of the LVDS transmitter-receiver are one

transmitter macro, one receiver macro, three board

resistors at the transmitter end, and one resistor at the

receiver end. The values for the three driver resistors are

different from those used in the LVPECL implementation

because the output standard specifications are different.

Along with LVDS I/O, ProASIC3 also supports Bus LVDS

structure and Multipoint LVDS (M-LVDS) configuration

(up to 40 nodes).

Figure 3-11 • LVDS Circuit Diagram and Board-Level Implementation

Table 3-77 • Minimum and Maximum DC Input and Output Levels

DC Parameter Description Min. Typ. Max. Units

VCCI Supply Voltage 2.375 2.5 2.625 V

VOL Output LOW Voltage 0.9 1.075 1.25 V

VOH Output HIGH Voltage 1.25 1.425 1.6 V

VIInput Voltage 0 – 2.925 V

VODIFF Differential Output Voltage 250 350 450 mV

VOCM Output Common-Mode Voltage 1.125 1.25 1.375 V

VICM Input Common-Mode Voltage 0.05 1.25 2.35 V

VIDIFF Input Differential Voltage 100 350 – mV

Notes:

1. ± 5%

2. Differential input voltage = ±350 mV

Table 3-78 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V)

1.075 1.325 Cross point

Note: *Measuring point = Vtrip. See Table 3-6 on page 3-5 for a complete table of trip points.

140 Ω100 Ω

ZO = 50 Ω

165 Ω

–

INBUF_LVDS

OUTBUF_LVDS

FPGA FPGA

Bourns Part Number: CAT16-LV4F12

ProASIC®3 Flash Family FPGAs

v2.1 3-55

Timing Characteristics

BLVDS/M-LVDS

Bus LVDS (BLVDS) and Multipoint LVDS (M-LVDS)

specifications extend the existing LVDS standard to high-

performance multipoint bus applications. Multidrop and

multipoint bus configurations may contain any

combination of drivers, receivers, and transceivers. Actel

LVDS drivers provide the higher drive current required by

BLVDS and M-LVDS to accommodate the loading. The

drivers require series terminations for better signal quality

and to control voltage swing. Termination is also required

at both ends of the bus since the driver can be located

anywhere on the bus. These configurations can be

implemented using the TRIBUF_LVDS and BIBUF_LVDS

macros along with appropriate terminations. Multipoint

designs using Actel LVDS macros can achieve up to

200 MHz with a maximum of 20 loads. A sample

application is given in Figure 3-12. The input and output

buffer delays are available in the LVDS section in Table 3-

79.

Example: For a bus consisting of 20 equidistant loads, the

following terminations provide the required differential

voltage, in worst-case Industrial operating conditions, at

the farthest receiver: RS=60Ω and RT=70Ω, given

Z0=50Ω (2") and Zstub =50Ω (~1.5").

Table 3-79 • LVDS

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Speed Grade tDOUT tDP tDIN tPY Units

–F 0.79 2.20 0.05 1.92 ns

Std. 0.66 1.83 0.04 1.60 ns

–1 0.56 1.56 0.04 1.36 ns

–2 0.49 1.37 0.03 1.20 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

Figure 3-12 • BLVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers

...

BIBUF_LVDS

-T

-R

-T

EN EN EN EN EN

Receiver Transceiver Receiver TransceiverDriver

stub

ProASIC®3 Flash Family FPGAs

3-56 v2.1

LVPECL

Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is

another differential I/O standard. It requires that one

data bit be carried through two signal lines. Like LVDS,

two pins are needed. It also requires external resistor

termination.

The full implementation of the LVDS transmitter and

receiver is shown in an example in Figure 3-13. The

building blocks of the LVPECL transmitter-receiver are

one transmitter macro, one receiver macro, three board

resistors at the transmitter end, and one resistor at the

receiver end. The values for the three driver resistors are

different from those used in the LVDS implementation

because the output standard specifications are different.

Timing Characteristics

Figure 3-13 • LVPECL Circuit Diagram and Board-Level Implementation

Table 3-80 • Minimum and Maximum DC Input and Output Levels

DC Parameter Description Min. Max. Min. Max. Min. Max. Units

VCCI Supply Voltage 3.0 3.3 3.6 V

VOL Output LOW Voltage 0.96 1.27 1.06 1.43 1.30 1.57 V

VOH Output HIGH Voltage 1.8 2.11 1.92 2.28 2.13 2.41 V

VIL, VIH Input LOW, Input HIGH Voltages 0 3.3 0 3.6 0 3.9 V

VODIFF Differential Output Voltage 0.625 0.97 0.625 0.97 0.625 0.97 V

VOCM Output Common-Mode Voltage 1.762 1.98 1.762 1.98 1.762 1.98 V

VICM Input Common-Mode Voltage 1.01 2.57 1.01 2.57 1.01 2.57 V

VIDIFF Input Differential Voltage 300 300 300 mV

Table 3-81 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V)

1.64 1.94 Cross point

Note: *Measuring point = Vtrip. See Table 3-18 on page 3-17 for a complete table of trip points.

Table 3-82 • LVPECL

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Speed Grade tDOUT tDP tDIN tPY Units

–F 0.79 2.16 0.05 1.69 ns

Std. 0.66 1.80 0.04 1.40 ns

–1 0.56 1.53 0.04 1.19 ns

–2 0.49 1.34 0.03 1.05 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

187 W 100 Ω

ZO = 50 Ω

100 Ω

–

INBUF_LVPECL

OUTBUF_LVPECL

FPGA FPGA

Bourns Part Number: CAT16-PC4F12

ProASIC®3 Flash Family FPGAs

v2.1 3-57

I/O Register Specifications

Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset

Figure 3-14 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset

INBUF

INBUF INBUF

TRIBUF

CLKBUF

INBUF

CLKBUF

Data Input I/O Register with:

Active High Enable

Active High Preset

Positive Edge Triggered

Data Output Register and

Enable Output Register with:

Active High Enable

Active High Preset

Postive Edge Triggered

Pad Out

CLK

Enable

Preset

Data_out

Data

EOUT

DOUT

Enable

CLK

DFN1E1P1

PRE

DFN1E1P1

PRE

DFN1E1P1

PRE

D_Enable

Core

Array

ProASIC®3 Flash Family FPGAs

3-58 v2.1

Table 3-83 • Parameter Definition and Measuring Nodes

Parameter Name Parameter Definition Measuring Nodes (from, to)*

tOCLKQ Clock-to-Q of the Output Data Register H, DOUT

tOSUD Data Setup Time for the Output Data Register F, H

tOHD Data Hold Time for the Output Data Register F, H

tOSUE Enable Setup Time for the Output Data Register G, H

tOHE Enable Hold Time for the Output Data Register G, H

tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register L, DOUT

tOREMPRE Asynchronous Preset Removal Time for the Output Data Register L, H

tORECPRE Asynchronous Preset Recovery Time for the Output Data Register L, H

tOECLKQ Clock-to-Q of the Output Enable Register H, EOUT

tOESUD Data Setup Time for the Output Enable Register J, H

tOEHD Data Hold Time for the Output Enable Register J, H

tOESUE Enable Setup Time for the Output Enable Register K, H

tOEHE Enable Hold Time for the Output Enable Register K, H

tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register I, EOUT

tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register I, H

tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register I, H

tICLKQ Clock-to-Q of the Input Data Register A, E

tISUD Data Setup Time for the Input Data Register C, A

tIHD Data Hold Time for the Input Data Register C, A

tISUE Enable Setup Time for the Input Data Register B, A

tIHE Enable Hold Time for the Input Data Register B, A

tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register D, E

tIREMPRE Asynchronous Preset Removal Time for the Input Data Register D, A

tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register D, A

Note: *See Figure 3-14 on page 3-57 for more information.

ProASIC®3 Flash Family FPGAs

v2.1 3-59

Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear

Figure 3-15 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear

Enable

CLK

Pad Out

CLK

Enable

CLR

Data_out

Data

EOUT

DOUT

Core

Array

DFN1E1C1

CLR

DFN1E1C1

CLR

DFN1E1C1

CLR

D_Enable

CLKBUF

INBUF

TRIBUF

INBUF INBUF CLKBUF

INBUF

Data Input I/O Register with

Active High Enable

Active High Clear

Positive Edge Triggered Data Output Register and

Enable Output Register with

Active High Enable

Active High Clear

Positive Edge Triggered

ProASIC®3 Flash Family FPGAs

3-60 v2.1

Table 3-84 • Parameter Definition and Measuring Nodes

Parameter Name Parameter Definition Measuring Nodes (from, to)*

tOCLKQ Clock-to-Q of the Output Data Register HH, DOUT

tOSUD Data Setup Time for the Output Data Register FF, HH

tOHD Data Hold Time for the Output Data Register FF, HH

tOSUE Enable Setup Time for the Output Data Register GG, HH

tOHE Enable Hold Time for the Output Data Register GG, HH

tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register LL, DOUT

tOREMCLR Asynchronous Clear Removal Time for the Output Data Register LL, HH

tORECCLR Asynchronous Clear Recovery Time for the Output Data Register LL, HH

tOECLKQ Clock-to-Q of the Output Enable Register HH, EOUT

tOESUD Data Setup Time for the Output Enable Register JJ, HH

tOEHD Data Hold Time for the Output Enable Register JJ, HH

tOESUE Enable Setup Time for the Output Enable Register KK, HH

tOEHE Enable Hold Time for the Output Enable Register KK, HH

tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register II, EOUT

tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register II, HH

tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register II, HH

tICLKQ Clock-to-Q of the Input Data Register AA, EE

tISUD Data Setup Time for the Input Data Register CC, AA

tIHD Data Hold Time for the Input Data Register CC, AA

tISUE Enable Setup Time for the Input Data Register BB, AA

tIHE Enable Hold Time for the Input Data Register BB, AA

tICLR2Q Asynchronous Clear-to-Q of the Input Data Register DD, EE

tIREMCLR Asynchronous Clear Removal Time for the Input Data Register DD, AA

tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register DD, AA

Note: *See Figure 3-15 on page 3-59 for more information.

ProASIC®3 Flash Family FPGAs

v2.1 3-61

Input Register

Timing Characteristics

Figure 3-16 • Input Register Timing Diagram

50%

Preset

Clear

Out_1

CLK

Data

Enable

ISUE

50%

ISUD

IHD

50% 50%

ICLKQ

IHE

IRECPRE

IREMPRE

IRECCLR

IREMCLR

IWCLR

IWPRE

IPRE2Q

ICLR2Q

ICKMPWH

ICKMPWL

50% 50%

50% 50% 50%

50% 50%

50% 50% 50% 50% 50% 50%

50%

Table 3-85 • Input Data Register Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tICLKQ Clock-to-Q of the Input Data Register 0.24 0.27 0.32 0.38 ns

tISUD Data Setup Time for the Input Data Register 0.26 0.30 0.35 0.42 ns

tIHD Data Hold Time for the Input Data Register 0.00 0.00 0.00 0.00 ns

tISUE Enable Setup Time for the Input Data Register 0.37 0.42 0.50 0.60 ns

tIHE Enable Hold Time for the Input Data Register 0.00 0.00 0.00 0.00 ns

tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 0.45 0.52 0.61 0.73 ns

tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 0.45 0.52 0.61 0.73 ns

tIREMCLR Asynchronous Clear Removal Time for the Input Data Register 0.00 0.00 0.00 0.00 ns

tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register 0.22 0.25 0.30 0.36 ns

tIREMPRE Asynchronous Preset Removal Time for the Input Data Register 0.00 0.00 0.00 0.00 ns

tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register 0.22 0.25 0.30 0.36 ns

tIWCLR Asynchronous Clear Minimum Pulse Width for the Input Data

0.22 0.25 0.30 0.36 ns

tIWPRE Asynchronous Preset Minimum Pulse Width for the Input Data

0.22 0.25 0.30 0.36 ns

tICKMPWH Clock Minimum Pulse Width HIGH for the Input Data Register 0.36 0.41 0.48 0.57 ns

tICKMPWL Clock Minimum Pulse Width LOW for the Input Data Register 0.32 0.37 0.43 0.52 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

ProASIC®3 Flash Family FPGAs

3-62 v2.1

Output Register

Timing Characteristics

Figure 3-17 • Output Register Timing Diagram

Preset

Clear

DOUT

CLK

Data_out

Enable

tOSUE

50%

tOSUD tOHD

50% 50%

tOCLKQ

tOHE

tORECPRE

tOREMPRE

tORECCLR tOREMCLR

tOWCLR

tOWPRE

tOPRE2Q

tOCLR2Q

tOCKMPWH tOCKMPWL

50% 50%

50% 50% 50%

50% 50%

50% 50% 50% 50% 50% 50%

50%

Table 3-86 • Output Data Register Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tOCLKQ Clock-to-Q of the Output Data Register 0.59 0.67 0.79 0.95 ns

tOSUD Data Setup Time for the Output Data Register 0.31 0.36 0.42 0.50 ns

tOHD Data Hold Time for the Output Data Register 0.00 0.00 0.00 0.00 ns

tOSUE Enable Setup Time for the Output Data Register 0.44 0.50 0.59 0.70 ns

tOHE Enable Hold Time for the Output Data Register 0.00 0.00 0.00 0.00 ns

tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register 0.80 0.91 1.07 1.29 ns

tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register 0.80 0.91 1.07 1.29 ns

tOREMCLR Asynchronous Clear Removal Time for the Output Data Register 0.00 0.00 0.00 0.00 ns

tORECCLR Asynchronous Clear Recovery Time for the Output Data Register 0.22 0.25 0.30 0.36 ns

tOREMPRE Asynchronous Preset Removal Time for the Output Data Register 0.00 0.00 0.00 0.00 ns

tORECPRE Asynchronous Preset Recovery Time for the Output Data Register 0.22 0.25 0.30 0.36 ns

tOWCLR Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.22 0.25 0.30 0.36 ns

tOWPRE Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.22 0.25 0.30 0.36 ns

tOCKMPWH Clock Minimum Pulse Width HIGH for the Output Data Register 0.36 0.41 0.48 0.57 ns

tOCKMPWL Clock Minimum Pulse Width LOW for the Output Data Register 0.32 0.37 0.43 0.52 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

ProASIC®3 Flash Family FPGAs

v2.1 3-63

Output Enable Register

Timing Characteristics

Figure 3-18 • Output Enable Register Timing Diagram

Table 3-87 • Output Enable Register Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tOECLKQ Clock-to-Q of the Output Enable Register 0.59 0.67 0.79 0.95 ns

tOESUD Data Setup Time for the Output Enable Register 0.31 0.36 0.42 0.50 ns

tOEHD Data Hold Time for the Output Enable Register 0.00 0.00 0.00 0.00 ns

tOESUE Enable Setup Time for the Output Enable Register 0.44 0.50 0.58 0.70 ns

tOEHE Enable Hold Time for the Output Enable Register 0.00 0.00 0.00 0.00 ns

tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register 0.67 0.76 0.89 1.07 ns

tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register 0.67 0.76 0.89 1.07 ns

tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register 0.00 0.00 0.00 0.00 ns

tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register 0.22 0.25 0.30 0.36 ns

tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register 0.00 0.00 0.00 0.00 ns

tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register 0.22 0.25 0.30 0.36 ns

tOEWCLR Asynchronous Clear Minimum Pulse Width for the Output Enable Register 0.22 0.25 0.30 0.36 ns

tOEWPRE Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.22 0.25 0.30 0.36 ns

tOECKMPWH Clock Minimum Pulse Width HIGH for the Output Enable Register 0.36 0.41 0.48 0.57 ns

tOECKMPWL Clock Minimum Pulse Width LOW for the Output Enable Register 0.32 0.37 0.43 0.52 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

50%

Preset

Clear

EOUT

CLK

D_Enable

Enable

OESUE

50%

OESUD

OEHD

50% 50%

OECLKQ

OEHE

OERECPRE

OEREMPRE

OERECCLR

OEREMCLR

OEWCLR

OEWPRE

OEPRE2Q

OECLR2Q

OECKMPWH

OECKMPWL

50% 50%

50% 50% 50%

50% 50%

50% 50% 50% 50% 50% 50%

50%

ProASIC®3 Flash Family FPGAs

3-64 v2.1

DDR Module Specifications

Input DDR Module

Figure 3-19 • Input DDR Timing Model

Table 3-88 • Parameter Definitions

Parameter Name Parameter Definition Measuring Nodes (from, to)

tDDRICLKQ1 Clock-to-Out Out_QR B, D

tDDRICLKQ2 Clock-to-Out Out_QF B, E

tDDRISUD Data Setup Time of DDR input A, B

tDDRIHD Data Hold Time of DDR input A, B

tDDRICLR2Q1 Clear-to-Out Out_QR C, D

tDDRICLR2Q2 Clear-to-Out Out_QF C, E

tDDRIREMCLR Clear Removal C, B

tDDRIRECCLR Clear Recovery C, B

Input DDR

Data

CLK

CLKBUF

INBUF

Out_QF

(to core)

FF2

FF1

INBUF

CLR

DDR_IN

Out_QR

(to core)

ProASIC®3 Flash Family FPGAs

v2.1 3-65

Timing Characteristics

Figure 3-20 • Input DDR Timing Diagram

DDRICLR2Q2

DDRIREMCLR

DDRIRECCLR

DDRICLR2Q1

12 3 4 5 6 7 8 9

CLK

Data

CLR

Out_QR

Out_QF

DDRICLKQ1

246

357

DDRIHD

DDRISUD

DDRICLKQ2

Table 3-89 • Input DDR Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tDDRICLKQ1 Clock-to-Out Out_QR for Input DDR 0.39 0.44 0.52 0.62 ns

tDDRICLKQ2 Clock-to-Out Out_QF for Input DDR 0.27 0.31 0.37 0.44 ns

tDDRISUD Data Setup for Input DDR 0.28 0.32 0.38 0.45 ns

tDDRIHD Data Hold for Input DDR 0.00 0.00 0.00 0.00 ns

tDDRICLR2Q1 Asynchronous Clear-to-Out Out_QR for Input DDR 0.57 0.65 0.76 0.92 ns

tDDRICLR2Q2 Asynchronous Clear-to-Out Out_QF for Input DDR 0.46 0.53 0.62 0.74 ns

tDDRIREMCLR Asynchronous Clear Removal Time for Input DDR 0.00 0.00 0.00 0.00 ns

tDDRIRECCLR Asynchronous Clear Recovery Time for Input DDR 0.22 0.25 0.30 0.36 ns

tDDRIWCLR Asynchronous Clear Minimum Pulse Width for Input DDR 0.22 0.25 0.30 0.36 ns

tDDRICKMPWH Clock Minimum Pulse Width HIGH for Input DDR 0.36 0.41 0.48 0.57 ns

tDDRICKMPWL Clock Minimum Pulse Width LOW for Input DDR 0.32 0.37 0.43 0.52 ns

FDDRIMAX Maximum Frequency for Input DDR TBD TBD TBD TBD MHz

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

ProASIC®3 Flash Family FPGAs

3-66 v2.1

Output DDR Module

Figure 3-21 • Output DDR Timing Model

Table 3-90 • Parameter Definitions

Parameter Name Parameter Definition Measuring Nodes (from, to)

tDDROCLKQ Clock-to-Out B, E

tDDROCLR2Q Asynchronous Clear-to-Out C, E

tDDROREMCLR Clear Removal C, B

tDDRORECCLR Clear Recovery C, B

tDDROSUD1 Data Setup Data_F A, B

tDDROSUD2 Data Setup Data_R D, B

tDDROHD1 Data Hold Data_F A, B

tDDROHD2 Data Hold Data_R D, B

Data_F

(from core)

CLK

CLKBUF

Out

FF2

INBUF

CLR

DDR_OUT

Output DDR

FF1

OUTBUF

Data_R

(from core)

ProASIC®3 Flash Family FPGAs

v2.1 3-67

Timing Characteristics

Figure 3-22 • Output DDR Timing Diagram

116

910

28 3 9

tDDROREMCLR

tDDROHD1

tDDROREMCLR

tDDROHD2

tDDROSUD2

tDDROCLKQ

tDDRORECCLR

CLK

Data_R

Data_F

CLR

Out

tDDROCLR2Q

7104

Table 3-91 • Output DDR Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tDDROCLKQ Clock-to-Out of DDR for Output DDR 0.70 0.80 0.94 1.13 ns

tDDROSUD1 Data_F Data Setup for Output DDR 0.38 0.43 0.51 0.61 ns

tDDROSUD2 Data_R Data Setup for Output DDR 0.38 0.43 0.51 0.61 ns

tDDROHD1 Data_F Data Hold for Output DDR 0.00 0.00 0.00 0.00 ns

tDDROHD2 Data_R Data Hold for Output DDR 0.00 0.00 0.00 0.00 ns

tDDROCLR2Q Asynchronous Clear-to-Out for Output DDR 0.80 0.91 1.07 1.29 ns

tDDROREMCLR Asynchronous Clear Removal Time for Output DDR 0.00 0.00 0.00 0.00 ns

tDDRORECCLR Asynchronous Clear Recovery Time for Output DDR 0.22 0.25 0.30 0.36 ns

tDDROWCLR1 Asynchronous Clear Minimum Pulse Width for Output DDR 0.22 0.25 0.30 0.36 ns

tDDROCKMPWH Clock Minimum Pulse Width HIGH for the Output DDR 0.36 0.41 0.48 0.57 ns

tDDROCKMPWL Clock Minimum Pulse Width LOW for the Output DDR 0.32 0.37 0.43 0.52 ns

FDDOMAX Maximum Frequency for the Output DDR TBD TBD TBD TBD MHz

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

ProASIC®3 Flash Family FPGAs

3-68 v2.1

VersaTile Characteristics

VersaTile Specifications as a Combinatorial Module

The ProASIC3 library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are

presented for a sample of the library. For more details, refer to the ProASIC3/E Macro Library Guide.

Figure 3-23 • Sample of Combinatorial Cells

MAJ3

MUX2

XOR2 Y

NOR2

YOR2

INV

AND2

NAND3

XOR3

NAND2

ProASIC®3 Flash Family FPGAs

v2.1 3-69

Figure 3-24 • Timing Model and Waveforms

tPD

tPD = MAX(tPD(RR), tPD(RF),

tPD(FF), tPD(FR)) where edges are

applicable for the particular

combinatorial cell

NAND2 or

Any Combinatorial

Logic

tPD

50%

VCC

50%

GND

A, B, C

50% 50%

50%

(RR)

(RF) GND

OUT

GND

50%

(FF)

(FR)

tPD

ProASIC®3 Flash Family FPGAs

3-70 v2.1

Timing Characteristics

VersaTile Specifications as a Sequential Module

The ProASIC3 library offers a wide variety of sequential cells, including flip-flops and latches. Each has a data input and

optional enable, clear, or preset. In this section, timing characteristics are presented for a representative sample from

the library. For more details, refer to the ProASIC3/E Macro Library Guide.

Table 3-92 • Combinatorial Cell Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Combinatorial Cell Equation Parameter –2 –1 Std. –F Units

INV Y = !A tPD 0.40 0.46 0.54 0.65 ns

AND2 Y = A · B tPD 0.47 0.54 0.63 0.76 ns

NAND2 Y = !(A · B) tPD 0.47 0.54 0.63 0.76 ns

OR2 Y = A + B tPD 0.49 0.55 0.65 0.78 ns

NOR2 Y = !(A + B) tPD 0.49 0.55 0.65 0.78 ns

XOR2 Y = A ⊕ Bt

PD 0.74 0.84 0.99 1.19 ns

MAJ3 Y = MAJ(A , B, C) tPD 0.70 0.79 0.93 1.12 ns

XOR3 Y = A ⊕ B ⊕ Ct

PD 0.87 1.00 1.17 1.41 ns

MUX2 Y = A !S + B S tPD 0.51 0.58 0.68 0.81 ns

AND3 Y = A · B · C tPD 0.56 0.64 0.75 0.90 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

Figure 3-25 • Sample of Sequential Cells

DFN1

Data

CLK

Out

DFN1C1

Data

CLK

Out

CLR

DFI1E1P1

Data

CLK

Out

PRE

DFN1E1

Data

CLK

Out

ProASIC®3 Flash Family FPGAs

v2.1 3-71

Timing Characteristics

Figure 3-26 • Timing Model and Waveforms

PRE

CLR

Out

CLK

Data

tSUE

50%

tSUD

tHD

50% 50%

tCLKQ

tHE

tRECPRE tREMPRE

tRECCLR tREMCLRtWCLR

tWPRE

tPRE2Q tCLR2Q

tCKMPWH tCKMPWL

50% 50%

50% 50% 50%

50% 50%

50% 50% 50% 50% 50% 50%

50%

Table 3-93 • Register Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tCLKQ Clock-to-Q of the Core Register 0.55 0.63 0.74 0.89 ns

tSUD Data Setup Time for the Core Register 0.43 0.49 0.57 0.69 ns

tHD Data Hold Time for the Core Register 0.00 0.00 0.00 0.00 ns

tSUE Enable Setup Time for the Core Register 0.45 0.52 0.61 0.73 ns

tHE Enable Hold Time for the Core Register 0.00 0.00 0.00 0.00 ns

tCLR2Q Asynchronous Clear-to-Q of the Core Register 0.40 0.45 0.53 0.64 ns

tPRE2Q Asynchronous Preset-to-Q of the Core Register 0.40 0.45 0.53 0.64 ns

tREMCLR Asynchronous Clear Removal Time for the Core Register 0.00 0.00 0.00 0.00 ns

tRECCLR Asynchronous Clear Recovery Time for the Core Register 0.22 0.25 0.30 0.36 ns

tREMPRE Asynchronous Preset Removal Time for the Core Register 0.00 0.00 0.00 0.00 ns

tRECPRE Asynchronous Preset Recovery Time for the Core Register 0.22 0.25 0.30 0.36 ns

tWCLR Asynchronous Clear Minimum Pulse Width for the Core Register 0.22 0.25 0.30 0.36 ns

tWPRE Asynchronous Preset Minimum Pulse Width for the Core Register 0.22 0.25 0.30 0.36 ns

tCKMPWH Clock Minimum Pulse Width HIGH for the Core Register 0.32 0.37 0.43 0.52 ns

tCKMPWL Clock Minimum Pulse Width LOW for the Core Register 0.36 0.41 0.48 0.57 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

ProASIC®3 Flash Family FPGAs

3-72 v2.1

Global Resource Characteristics

A3P250 Clock Tree Topology

Clock delays are device-specific. Figure 3-27 is an example of a global tree used for clock routing. The global tree

presented in Figure 3-27 is driven by a CCC located on the west side of the A3P250 device. It is used to drive all D-flip-

flops in the device.

Figure 3-27 • Example of Global Tree Use in an A3P250 Device for Clock Routing

Central

Global Rib

VersaTile

Rows

Global Spine

CCC

ProASIC®3 Flash Family FPGAs

v2.1 3-73

Global Tree Timing Characteristics

Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input

buffer clock delays, as these are I/O standard–dependent, and the clock may be driven and conditioned internally by

the CCC module. For more details on clock conditioning capabilities, refer to the "Clock Conditioning Circuits" section

on page 2-15. Table 3-95 to Table 3-100 on page 3-76 present minimum and maximum global clock delays within each

device. Minimum and maximum delays are measured with minimum and maximum loading.

Timing Characteristics

Table 3-94 • A3P030 Global Resource

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description

–2 –1 Std. –F

UnitsMin.1Max.2Min.1Max.2Min.1Max.2Min.1Max.2

tRCKL Input LOW Delay for Global Clock 0.67 0.81 0.76 0.92 0.89 1.09 1.07 1.31 ns

tRCKH Input HIGH Delay for Global Clock 0.68 0.85 0.77 0.97 0.91 1.14 1.09 1.37 ns

tRCKMPWH Minimum Pulse Width HIGH for Global

Clock

tRCKMPWL Minimum Pulse Width LOW for Global

Clock

tRCKSW Maximum Skew for Global Clock 0.18 0.21 0.24 0.29 ns

FRMAX Maximum Frequency for Global Clock MHz

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a

lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row

(all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

Table 3-95 • A3P060 Global Resource

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description

–2 –1 Std. –F

UnitsMin.1Max.2Min.1Max.2Min.1Max.2Min.1Max.2

tRCKL Input LOW Delay for Global Clock 0.71 0.93 0.81 1.05 0.95 1.24 1.14 1.49 ns

tRCKH Input HIGH Delay for Global Clock 0.70 0.96 0.80 1.09 0.94 1.28 1.13 1.54 ns

tRCKMPWH Minimum Pulse Width HIGH for Global

Clock

tRCKMPWL Minimum Pulse Width LOW for Global

Clock

tRCKSW Maximum Skew for Global Clock 0.26 0.29 0.34 0.41 ns

FRMAX Maximum Frequency for Global Clock MHz

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a

lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row

(all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

ProASIC®3 Flash Family FPGAs

3-74 v2.1

Table 3-96 • A3P125 Global Resource

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description

–2 –1 Std. –F

UnitsMin.1Max.2Min.1Max.2Min.1Max.2Min.1Max.2

tRCKL Input LOW Delay for Global Clock 0.77 0.99 0.87 1.12 1.03 1.32 1.24 1.58 ns

tRCKH Input HIGH Delay for Global Clock 0.76 1.02 0.87 1.16 1.02 1.37 1.23 1.64 ns

tRCKMPWH Minimum Pulse Width HIGH for Global

Clock

tRCKMPWL Minimum Pulse Width LOW for Global

Clock

tRCKSW Maximum Skew for Global Clock 0.26 0.29 0.34 0.41 ns

FRMAX Maximum Frequency for Global Clock MHz

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a

lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row

(all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

Table 3-97 • A3P250 Global Resource

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description

–2 –1 Std. –F

UnitsMin.1Max.2Min.1Max.2Min.1Max.2Min.1Max.2

tRCKL Input LOW Delay for Global Clock 0.80 1.01 0.91 1.15 1.07 1.36 1.28 1.63 ns

tRCKH Input HIGH Delay for Global Clock 0.78 1.04 0.89 1.18 1.04 1.39 1.25 1.66 ns

tRCKMPWH Minimum Pulse Width HIGH for Global

Clock

tRCKMPWL Minimum Pulse Width LOW for Global

Clock

tRCKSW Maximum Skew for Global Clock 0.26 0.29 0.34 0.41 ns

FRMAX Maximum Frequency for Global Clock MHz

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a

lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row

(all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

ProASIC®3 Flash Family FPGAs

v2.1 3-75

Table 3-98 • A3P400 Global Resource

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description

–2 –1 Std. –F

UnitsMin.1Max.2Min.1Max.2Min.1Max.2Min.1Max.2

tRCKL Input LOW Delay for Global Clock 0.87 1.09 0.99 1.24 1.17 1.46 1.40 1.75 ns

tRCKH Input HIGH Delay for Global Clock 0.86 1.11 0.98 1.27 1.15 1.49 1.38 1.79 ns

tRCKMPWH Minimum Pulse Width HIGH for Global

Clock

tRCKMPWL Minimum Pulse Width LOW for Global

Clock

tRCKSW Maximum Skew for Global Clock 0.26 0.29 0.34 0.41 ns

FRMAX Maximum Frequency for Global Clock Mhz

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a

lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row

(all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

Table 3-99 • A3P600 Global Resource

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description

–2 –1 Std. –F

UnitsMin.1Max.2Min.1Max.2Min.1Max.2Min.1Max.2

tRCKL Input LOW Delay for Global Clock 0.87 1.09 0.99 1.24 1.17 1.46 1.40 1.75 ns

tRCKH Input HIGH Delay for Global Clock 0.86 1.11 0.98 1.27 1.15 1.49 1.38 1.79 ns

tRCKMPWH Minimum Pulse Width HIGH for Global

Clock

tRCKMPWL Minimum Pulse Width LOW for Global

Clock

tRCKSW Maximum Skew for Global Clock 0.26 0.29 0.34 0.41 ns

FRMAX Maximum Frequency for Global Clock MHz

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a

lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row

(all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

ProASIC®3 Flash Family FPGAs

3-76 v2.1

Table 3-100 • A3P1000 Global Resource

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description

–2 –1 Std. –F

UnitsMin.1Max.2Min.1Max.2Min.1Max.2Min.1Max.2

tRCKL Input LOW Delay for Global Clock 0.94 1.16 1.07 1.32 1.26 1.55 1.51 1.86 ns

tRCKH Input HIGH Delay for Global Clock 0.93 1.19 1.06 1.35 1.24 1.59 1.49 1.91 ns

tRCKMPWH Minimum Pulse Width HIGH for Global

Clock

tRCKMPWL Minimum Pulse Width LOW for Global

Clock

tRCKSW Maximum Skew for Global Clock 0.26 0.29 0.35 0.41 ns

FRMAX Maximum Frequency for Global Clock MHz

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a

lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row

(all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

ProASIC®3 Flash Family FPGAs

v2.1 3-77

Embedded SRAM and FIFO Characteristics

SRAM

Figure 3-28 • RAM Models

ADDRA11 DOUTA8

DOUTA7

DOUTA0

DOUTB8

DOUTB7

DOUTB0

ADDRA10

ADDRA0

DINA8

DINA7

DINA0

WIDTHA1

WIDTHA0

PIPEA

WMODEA

BLKA

WENA

CLKA

ADDRB11

ADDRB10

ADDRB0

DINB8

DINB7

DINB0

WIDTHB1

WIDTHB0

PIPEB

WMODEB

BLKB

WENB

CLKB

RAM4K9

RADDR8 RD17

RADDR7 RD16

RADDR0 RD0

WD17

WD16

WD0

WW1

WW0

RW1

RW0

PIPE

REN

RCLK

RAM512X18

WADDR8

WADDR7

WADDR0

WEN

WCLK

RESET

ProASIC®3 Flash Family FPGAs

3-78 v2.1

Timing Waveforms

Figure 3-29 • RAM Read for Pass-Through Output

Figure 3-30 • RAM Read for Pipelined Output

CLK

ADD

BLK_B

WEN_B

A0A1A2

D0D1D2

CYC

tCKH tCKL

tAS tAH

tBKS

tENS tENH

tDOH1

tBKH

tCKQ1

CLK

ADD

BLK_B

WEN_B

A0A1A2

D0D1

tCYC

tCKH tCKL

tAS tAH

tBKS

tENS tENH

tDOH2

tCKQ2

tBKH

ProASIC®3 Flash Family FPGAs

v2.1 3-79

Figure 3-31 • RAM Write, Output Retained (WMODE = 0)

Figure 3-32 • RAM Write, Output as Write Data (WMODE = 1)

tCYC

tCKH tCKL

A0A1A2

DI0DI1

tAS tAH

tBKS

tENS tENH

tDS tDH

CLK

BLK_B

WEN_B

ADD

tBKH

CYC

CKH

CKL

BKS

ENS

CLK

BLK_B

WEN_B

ADD

BKH

(pass-through) DI

(Pipelined) DI

ProASIC®3 Flash Family FPGAs

3-80 v2.1

Figure 3-33 • Write Access After Write onto Same Address

CLK1

CLK2

WEN_B1

WEN_B2

ADD1

ADD2

DI1

DI2

DO2

(pass-through)

DO2

(pipelined)

tAH

tAS

tAH

tAS

tDH

tCCKH

tDS

tCKQ1

tCKQ2

DnD0

A0A4

ProASIC®3 Flash Family FPGAs

v2.1 3-81

Figure 3-34 • Read Access After Write onto Same Address

CLK1

CLK2

WEN_B1

WEN_B2

ADD1

ADD2

DI1

DO2

(pass-through)

DO2

(pipelined)

tAH

tAS

tAH

tAS

tDH

tDS

tWRO

tCKQ1

tCKQ2

A0A1A4

DnD0

D0D1

ProASIC®3 Flash Family FPGAs

3-82 v2.1

Figure 3-35 • Write Access After Read onto Same Address

Figure 3-36 • RAM Reset

A0A1A0

A0A1A3

D1D2D3

tAH

tAS

tAH

tAS

tCKQ1 tCKQ1

tCKQ2

tCCKH

CLK1

ADD1

WEN_B1

DO1

(pass-through)

DO1

(pipelined)

CLK2

ADD2

DI2

WEN_B2

D0D1

CLK

RESET_B

DO Dn

tCYC

tCKH tCKL

tRSTBQ

ProASIC®3 Flash Family FPGAs

v2.1 3-83

Timing Characteristics

Table 3-101 • RAM4K9

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tAS Address Setup time 0.25 0.28 0.33 0.40 ns

tAH Address Hold time 0.00 0.00 0.00 0.00 ns

tENS REN_B, WEN_B Setup time 0.14 0.16 0.19 0.23 ns

tENH REN_B, WEN_B Hold time 0.10 0.11 0.13 0.16 ns

tBKS BLK_B Setup time 0.23 0.27 0.31 0.37 ns

tBKH BLK_B Hold time 0.02 0.02 0.02 0.03 ns

tDS Input data (DI) Setup time 0.18 0.21 0.25 0.29 ns

tDH Input data (DI) Hold time 0.00 0.00 0.00 0.00 ns

tCKQ1 Clock High to New Data Valid on DO (output retained, WMODE = 0) 2.36 2.68 3.15 3.79 ns

Clock High to New Data Valid on DO (flow-through, WMODE = 1) 1.79 2.03 2.39 2.87 ns

tCKQ2 Clock High to New Data Valid on DO (pipelined) 0.89 1.02 1.20 1.44 ns

tWRO Address collision clk-to-clk delay for reliable read access after write on

same address

TBD TBD TBD TBD ns

tCCKH Address collision clk-to-clk delay for reliable write access after

write/read on same address

TBD TBD TBD TBD ns

tRSTBQ RESET_B Low to Data Out Low on DO (flow through) 0.92 1.05 1.23 1.48 ns

RESET_B Low to Data Out Low on DO (pipelined) 0.92 1.05 1.23 1.48 ns

tREMRSTB RESET_B Removal 0.29 0.33 0.38 0.46 ns

tRECRSTB RESET_B Recovery 1.50 1.71 2.01 2.41 ns

tMPWRSTB RESET_B Minimum Pulse Width 0.21 0.24 0.29 0.34 ns

tCYC Clock Cycle time 3.23 3.68 4.32 5.19 ns

FMAX Maximum Frequency 310 272 231 193 MHz

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

ProASIC®3 Flash Family FPGAs

3-84 v2.1

Table 3-102 • RAM512X18

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tAS Address Setup time 0.25 0.28 0.33 0.40 ns

tAH Address Hold time 0.00 0.00 0.00 0.00 ns

tENS REN_B, WEN_B Setup time 0.13 0.15 0.17 0.21 ns

tENH REN_B, WEN_B Hold time 0.10 0.11 0.13 0.16 ns

tDS Input data (DI) Setup time 0.18 0.21 0.25 0.29 ns

tDH Input data (DI) Hold time 0.00 0.00 0.00 0.00 ns

tCKQ1 Clock High to New Data Valid on DO (output retained, WMODE = 0) 2.16 2.46 2.89 3.47 ns

tCKQ2 Clock High to New Data Valid on DO (pipelined) 0.90 1.02 1.20 1.44 ns

tWRO Address collision clk-to-clk delay for reliable read access after write on

same address

TBD TBD TBD TBD ns

tCCKH Address collision clk-to-clk delay for reliable write access after

write/read on same address

TBD TBD TBD TBD ns

tRSTBQ RESET_B Low to Data Out Low on DO (flow through) 0.92 1.05 1.23 1.48 ns

RESET_B Low to Data Out Low on DO (pipelined) 0.92 1.05 1.23 1.48 ns

tREMRSTB RESET_B Removal 0.29 0.33 0.38 0.46 ns

tRECRSTB RESET_B Recovery 1.50 1.71 2.01 2.41 ns

tMPWRSTB RESET_B Minimum Pulse Width 0.21 0.24 0.29 0.34 ns

tCYC Clock Cycle time 3.23 3.68 4.32 5.19 ns

FMAX Maximum Frequency 310 272 231 193 MHz

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

ProASIC®3 Flash Family FPGAs

v2.1 3-85

FIFO

Figure 3-37 • FIFO Model

FIFO4K18

RW2

RD17

RW1

RD16

RW0

WW2

WW1

WW0 RD0

ESTOP

FSTOP

FULL

AFULL

EMPTY

AFVAL11

AEMPTY

AFVAL10

AFVAL0

AEVAL11

AEVAL10

AEVAL0

REN

RBLK

RCLK

WEN

WBLK

WCLK

RPIPE

WD17

WD16

WD0

RESET

ProASIC®3 Flash Family FPGAs

3-86 v2.1

Timing Waveforms

Figure 3-38 • FIFO Reset

Figure 3-39 • FIFO EMPTY Flag and AEMPTY Flag Assertion

MATCH (A0)

tMPWRSTB

tRSTFG

tRSTCK

tRSTAF

RCLK/

WCLK

RESET_B

EMPTY

AEMPTY

WA/RA

(Address Counter)

tRSTFG

tRSTAF

FULL

AFULL

RCLK

NO MATCH NO MATCH Dist = AEF_TH MATCH (EMPTY)

tCKAF

tRCKEF

EMPTY

AEMPTY

tCYC

WA/RA

(Address Counter)

ProASIC®3 Flash Family FPGAs

v2.1 3-87

Figure 3-40 • FIFO FULL Flag and AFULL Flag Assertion

Figure 3-41 • FIFO EMPTY Flag and AEMPTY Flag Deassertion

Figure 3-42 • FIFO FULL Flag and AFULL Flag Deassertion

NO MATCH NO MATCH Dist = AFF_TH MATCH (FULL)

tCKAF

tWCKFF

tCYC

WCLK

FULL

AFULL

WA/RA

(Address Counter)

WCLK

WA/RA

(Address Counter) MATCH

(EMPTY) NO MATCH NO MATCH NO MATCH Dist = AEF_TH + 1

NO MATCH

RCLK

EMPTY

1st Rising

Edge

After 1st

Write

2nd Rising

Edge

After 1st

Write

RCKEF

CKAF

AEMPTY

Dist = AFF_TH – 1

MATCH (FULL) NO MATCH NO MATCH NO MATCH NO MATCH

tWCKF

tCKAF

1st Rising

Edge

After 1st

Read

1st Rising

Edge

After 2nd

Read

RCLK

WA/RA

(Address Counter)

WCLK

FULL

AFULL

ProASIC®3 Flash Family FPGAs

3-88 v2.1

Timing Characteristics

Table 3-103 • FIFO (for all dies except A3P250)

Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tENS REN_B, WEN_B Setup Time 1.34 1.52 1.79 2.15 ns

tENH REN_B, WEN_B Hold Time 0.00 0.00 0.00 0.00 ns

tBKS BLK_B Setup Time 0.19 0.22 0.26 0.31 ns

tBKH BLK_B Hold Time 0.00 0.00 0.00 0.00 ns

tDS Input Data (DI) Setup Time 0.18 0.21 0.25 0.29 ns

tDH Input Data (DI) Hold Time 0.00 0.00 0.00 0.00 ns

tCKQ1 Clock HIGH to New Data Valid on DO (flow-through) 2.17 2.47 2.90 3.48 ns

tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 0.94 1.07 1.26 1.52 ns

tRCKEF RCLK HIGH to Empty Flag Valid 1.72 1.96 2.30 2.76 ns

tWCKFF WCLK HIGH to Full Flag Valid 1.63 1.86 2.18 2.62 ns

tCKAF Clock HIGH to Almost Empty/Full Flag Valid 6.19 7.05 8.29 9.96 ns

tRSTFG RESET_B LOW to Empty/Full Flag Valid 1.69 1.93 2.27 2.72 ns

tRSTAF RESET_B LOW to Almost Empty/Full Flag Valid 6.13 6.98 8.20 9.85 ns

tRSTBQ RESET_B LOW to Data Out LOW on DO (flow-through) 0.92 1.05 1.23 1.48 ns

RESET_B LOW to Data Out LOW on DO (pipelined) 0.92 1.05 1.23 1.48 ns

tREMRSTB RESET_B Removal 0.29 0.33 0.38 0.46 ns

tRECRSTB RESET_B Recovery 1.50 1.71 2.01 2.41 ns

tMPWRSTB RESET_B Minimum Pulse Width 0.21 0.24 0.29 0.34 ns

tCYC Clock Cycle Time 3.23 3.68 4.32 5.19 ns

FMAX Maximum Frequency for FIFO 310 272 231 193 MHz

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

ProASIC®3 Flash Family FPGAs

v2.1 3-89

Table 3-104 • FIFO (for A3P250 only, aspect-ratio dependent)

Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tENS REN_B, WEN_B Setup Time 3.26 3.71 4.36 5.24 ns

tENH REN_B, WEN_B Hold Time 0.00 0.00 0.00 0.00 ns

tBKS BLK_B Setup Time 0.19 0.22 0.26 0.31 ns

tBKH BLK_B Hold Time 0.00 0.00 0.00 0.00 ns

tDS Input Data (DI) Setup Time 0.18 0.21 0.25 0.29 ns

tDH Input Data (DI) Hold Time 0.00 0.00 0.00 0.00 ns

tCKQ1 Clock HIGH to New Data Valid on DO (flow-through) 2.17 2.47 2.90 3.48 ns

tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 0.94 1.07 1.26 1.52 ns

tRCKEF RCLK HIGH to Empty Flag Valid 1.72 1.96 2.30 2.76 ns

tWCKFF WCLK HIGH to Full Flag Valid 1.63 1.86 2.18 2.62 ns

tCKAF Clock HIGH to Almost Empty/Full Flag Valid 6.19 7.05 8.29 9.96 ns

tRSTFG RESET_B LOW to Empty/Full Flag Valid 1.69 1.93 2.27 2.72 ns

tRSTAF RESET_B LOW to Almost Empty/Full Flag Valid 6.13 6.98 8.20 9.85 ns

tRSTBQ RESET_B LOW to Data Out LOW on DO (flow-through) 0.92 1.05 1.23 1.48 ns

RESET_B LOW to Data Out LOW on DO (pipelined) 0.92 1.05 1.23 1.48 ns

tREMRSTB RESET_B Removal 0.29 0.33 0.38 0.46 ns

tRECRSTB RESET_B Recovery 1.50 1.71 2.01 2.41 ns

tMPWRSTB RESET_B Minimum Pulse Width 0.21 0.24 0.29 0.34 ns

tCYC Clock Cycle Time 3.23 3.68 4.32 5.19 ns

FMAX Maximum Frequency for FIFO 310 272 231 193 MHz

ProASIC®3 Flash Family FPGAs

3-90 v2.1

Table 3-105 • A3P250 FIFO 512x8

Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tENS REN_B, WEN_B Setup Time 3.75 4.27 5.02 6.04 ns

tENH REN_B, WEN_B Hold Time 0.00 0.00 0.00 0.00 ns

tBKS BLK_B Setup Time 0.19 0.22 0.26 0.31 ns

tBKH BLK_B Hold Time 0.00 0.00 0.00 0.00 ns

tDS Input Data (DI) Setup Time 0.18 0.21 0.25 0.29 ns

tDH Input Data (DI) Hold Time 0.00 0.00 0.00 0.00 ns

tCKQ1 Clock HIGH to New Data Valid on DO (flow-through) 2.17 2.47 2.90 3.48 ns

tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 0.94 1.07 1.26 1.52 ns

tRCKEF RCLK HIGH to Empty Flag Valid 1.72 1.96 2.30 2.76 ns

tWCKFF WCLK HIGH to Full Flag Valid 1.63 1.86 2.18 2.62 ns

tCKAF Clock HIGH to Almost Empty/Full Flag Valid 6.19 7.05 8.29 9.96 ns

tRSTFG RESET_B LOW to Empty/Full Flag Valid 1.69 1.93 2.27 2.72 ns

tRSTAF RESET_B LOW to Almost Empty/Full Flag Valid 6.13 6.98 8.20 9.85 ns

tRSTBQ RESET_B LOW to Data Out LOW on DO (flow-through) 0.92 1.05 1.23 1.48 ns

RESET_B LOW to Data Out LOW on DO (pipelined) 0.92 1.05 1.23 1.48 ns

tREMRSTB RESET_B Removal 0.29 0.33 0.38 0.46 ns

tRECRSTB RESET_B Recovery 1.50 1.71 2.01 2.41 ns

tMPWRSTB RESET_B Minimum Pulse Width 0.21 0.24 0.29 0.34 ns

tCYC Clock Cycle Time 3.23 3.68 4.32 5.19 ns

FMAX Maximum Frequency for FIFO 310 272 231 193 MHz

ProASIC®3 Flash Family FPGAs

v2.1 3-91

Table 3-106 • A3P250 FIFO 1kx4

Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tENS REN_B, WEN_B Setup Time 4.05 4.61 5.42 6.52 ns

tENH REN_B, WEN_B Hold Time 0.00 0.00 0.00 0.00 ns

tBKS BLK_B Setup Time 0.19 0.22 0.26 0.31 ns

tBKH BLK_B Hold Time 0.00 0.00 0.00 0.00 ns

tDS Input Data (DI) Setup Time 0.18 0.21 0.25 0.29 ns

tDH Input Data (DI) Hold Time 0.00 0.00 0.00 0.00 ns

tCKQ1 Clock HIGH to New Data Valid on DO (flow-through) 2.36 2.68 3.15 3.79 ns

tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 0.89 1.02 1.20 1.44 ns

tRCKEF RCLK HIGH to Empty Flag Valid 1.72 1.96 2.30 2.76 ns

tWCKFF WCLK HIGH to Full Flag Valid 1.63 1.86 2.18 2.62 ns

tCKAF Clock HIGH to Almost Empty/Full Flag Valid 6.19 7.05 8.29 9.96 ns

tRSTFG RESET_B LOW to Empty/Full Flag Valid 1.69 1.93 2.27 2.72 ns

tRSTAF RESET_B LOW to Almost Empty/Full Flag Valid 6.13 6.98 8.20 9.85 ns

tRSTBQ RESET_B LOW to Data Out LOW on DO (flow-through) 0.92 1.05 1.23 1.48 ns

RESET_B LOW to Data Out LOW on DO (pipelined) 0.92 1.05 1.23 1.48 ns

tREMRSTB RESET_B Removal 0.29 0.33 0.38 0.46 ns

tRECRSTB RESET_B Recovery 1.50 1.71 2.01 2.41 ns

tMPWRSTB RESET_B Minimum Pulse Width 0.21 0.24 0.29 0.34 ns

tCYC Clock Cycle Time 3.23 3.68 4.32 5.19 ns

FMAX Maximum Frequency for FIFO 310 272 231 193 MHz

ProASIC®3 Flash Family FPGAs

3-92 v2.1

Table 3-107 • A3P250 FIFO 2kx2

Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tENS REN_B, WEN_B Setup Time 4.39 5.00 5.88 7.06 ns

tENH REN_B, WEN_B Hold Time 0.00 0.00 0.00 0.00 ns

tBKS BLK_B Setup Time 0.19 0.22 0.26 0.31 ns

tBKH BLK_B Hold Time 0.00 0.00 0.00 0.00 ns

tDS Input Data (DI) Setup Time 0.18 0.21 0.25 0.29 ns

tDH Input Data (DI) Hold Time 0.00 0.00 0.00 0.00 ns

tCKQ1 Clock HIGH to New Data Valid on DO (flow-through) 2.36 2.68 3.15 3.79 ns

tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 0.89 1.02 1.20 1.44 ns

tRCKEF RCLK HIGH to Empty Flag Valid 1.72 1.96 2.30 2.76 ns

tWCKFF WCLK HIGH to Full Flag Valid 1.63 1.86 2.18 2.62 ns

tCKAF Clock HIGH to Almost Empty/Full Flag Valid 6.19 7.05 8.29 9.96 ns

tRSTFG RESET_B LOW to Empty/Full Flag Valid 1.69 1.93 2.27 2.72 ns

tRSTAF RESET_B LOW to Almost Empty/Full Flag Valid 6.13 6.98 8.20 9.85 ns

tRSTBQ RESET_B LOW to Data Out LOW on DO (flow-through) 0.92 1.05 1.23 1.48 ns

RESET_B LOW to Data Out LOW on DO (pipelined) 0.92 1.05 1.23 1.48 ns

tREMRSTB RESET_B Removal 0.29 0.33 0.38 0.46 ns

tRECRSTB RESET_B Recovery 1.50 1.71 2.01 2.41 ns

tMPWRSTB RESET_B Minimum Pulse Width 0.21 0.24 0.29 0.34 ns

tCYC Clock Cycle Time 3.23 3.68 4.32 5.19 ns

FMAX Maximum Frequency for FIFO 310 272 231 193 MHz

ProASIC®3 Flash Family FPGAs

v2.1 3-93

Table 3-108 • A3P250 FIFO 4kx1

Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tENS REN_B, WEN_B Setup Time 4.86 5.53 6.50 7.81 ns

tENH REN_B, WEN_B Hold Time 0.00 0.00 0.00 0.00 ns

tBKS BLK_B Setup Time 0.19 0.22 0.26 0.31 ns

tBKH BLK_B Hold Time 0.00 0.00 0.00 0.00 ns

tDS Input Data (DI) Setup Time 0.18 0.21 0.25 0.29 ns

tDH Input Data (DI) Hold Time 0.00 0.00 0.00 0.00 ns

tCKQ1 Clock HIGH to New Data Valid on DO (flow-through) 2.36 2.68 3.15 3.79 ns

tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 0.89 1.02 1.20 1.44 ns

tRCKEF RCLK HIGH to Empty Flag Valid 1.72 1.96 2.30 2.76 ns

tWCKFF WCLK HIGH to Full Flag Valid 1.63 1.86 2.18 2.62 ns

tCKAF Clock HIGH to Almost Empty/Full Flag Valid 6.19 7.05 8.29 9.96 ns

tRSTFG RESET_B LOW to Empty/Full Flag Valid 1.69 1.93 2.27 2.72 ns

tRSTAF RESET_B LOW to Almost Empty/Full Flag Valid 6.13 6.98 8.20 9.85 ns

tRSTBQ RESET_B LOW to Data Out LOW on DO (pass-through) 0.92 1.05 1.23 1.48 ns

RESET_B LOW to Data Out LOW on DO (pipelined) 0.92 1.05 1.23 1.48 ns

tREMRSTB RESET_B Removal 0.29 0.33 0.38 0.46 ns

tRECRSTB RESET_B Recovery 1.50 1.71 2.01 2.41 ns

tMPWRSTB RESET_B Minimum Pulse Width 0.21 0.24 0.29 0.34 ns

tCYC Clock Cycle Time 3.23 3.68 4.32 5.19 ns

FMAX Maximum Frequency 310 272 231 193 MHz

ProASIC®3 Flash Family FPGAs

3-94 v2.1

Embedded FlashROM Characteristics

Timing Characteristics

Figure 3-43 • Timing Diagram

A0A1

tSU

tHOLD

tSU

tHOLD

tSU

tHOLD

tCKQ2 tCKQ2 tCKQ2

CLK

Address

Data D0D0D1

Table 3-109 • Embedded FlashROM Access Time

Parameter Description –2 –1 Std. Units

tSU Address Setup Time 0.53 0.61 0.71 ns

tHOLD Address Hold Time 0.00 0.00 0.00 ns

tCK2Q Clock to Out 21.42 24.40 28.68 ns

FMAX Maximum Clock Frequency 15 15 15 MHz

ProASIC®3 Flash Family FPGAs

v2.1 3-95

JTAG 1532 Characteristics

JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the

corresponding standard selected; refer to the I/O timing characteristics in the "User I/O Characteristics" section on

page 3-11 for more details.

Timing Characteristics

Table 3-110 • JTAG 1532

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. Units

tDISU Test Data Input Setup Time ns

tDIHD Test Data Input Hold Time ns

tTMSSU Test Mode Select Setup Time ns

tTMDHD Test Mode Select Hold Time ns

tTCK2Q Clock to Q (data out) ns

tRSTB2Q Reset to Q (data out) ns

FTCKMAX TCK Maximum Frequency 20 20 20 MHz

tTRSTREM ResetB Removal Time ns

tTRSTREC ResetB Recovery Time ns

tTRSTMPW ResetB Minimum Pulse ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-5 for derating values.

ProASIC3 Flash Family FPGAs

v2.1 4-1

Package Pin Assignments

132-Pin QFN

Note

For Package Manufacturing and Environmental information, visit the Resource Center at

http://www.actel.com/products/solutions/package/docs.aspx.

Note: This is the top view of the package.

Pin A1

Mark

A48

A36

A25

A12

A37

A13 A24

B44

B33

B23

B34

B12 B22

C40

C30

C21

B11

C10

C31

C11 C20

Optional

Corner Pad (4×)

ProASIC3 Flash Family FPGAs

4-2 v2.1

132-Pin QFN*

Pin Number A3P030 Function

A1 IO01RSB1

A2 IO81RSB1

A3 NC

A4 IO80RSB1

A5 GEC0/IO77RSB1

A6 NC

A7 GEB0/IO75RSB1

A8 IO73RSB1

A9 NC

A10 VCC

A11 IO71RSB1

A12 IO68RSB1

A13 IO63RSB1

A14 IO60RSB1

A15 NC

A16 IO59RSB1

A17 IO57RSB1

A18 VCC

A19 IO54RSB1

A20 IO52RSB1

A21 IO49RSB1

A22 IO48RSB1

A23 IO47RSB1

A24 TDI

A25 TRST

A26 IO44RSB0

A27 NC

A28 IO43RSB0

A29 IO42RSB0

A30 IO40RSB0

A31 IO39RSB0

A32 GDC0/IO36RSB0

A33 NC

A34 VCC

A35 IO34RSB0

A36 IO31RSB0

A37 IO26RSB0

A38 IO23RSB0

A39 NC

A40 IO22RSB0

A41 IO20RSB0

A42 IO18RSB0

A43 VCC

A44 IO15RSB0

A45 IO12RSB0

A46 IO10RSB0

A47 IO09RSB0

A48 IO06RSB0

B1 IO02RSB1

B2 IO82RSB1

B3 GND

B4 IO79RSB1

B5 NC

B6 GND

B7 IO74RSB1

B8 NC

B9 GND

B10 IO70RSB1

B11 IO67RSB1

B12 IO64RSB1

B13 IO61RSB1

B14 GND

B15 IO58RSB1

B16 IO56RSB1

B17 GND

B18 IO53RSB1

B19 IO50RSB1

B20 GND

B21 IO46RSB1

B22 TMS

B23 TDO

B24 IO45RSB0

132-Pin QFN*

Pin Number A3P030 Function

B25 GND

B26 NC

B27 IO41RSB0

B28 GND

B29 GDA0/IO37RSB0

B30 NC

B31 GND

B32 IO33RSB0

B33 IO30RSB0

B34 IO27RSB0

B35 IO24RSB0

B36 GND

B37 IO21RSB0

B38 IO19RSB0

B39 GND

B40 IO16RSB0

B41 IO13RSB0

B42 GND

B43 IO08RSB0

B44 IO05RSB0

C1 IO03RSB1

C2 IO00RSB1

C3 NC

C4 IO78RSB1

C5 GEA0/IO76RSB1

C6 NC

C7 NC

C8 VCCIB1

C9 IO69RSB1

C10 IO66RSB1

C11 IO65RSB1

C12 IO62RSB1

C13 NC

C14 NC

C15 IO55RSB1

C16 VCCIB1

132-Pin QFN*

Pin Number A3P030 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

v2.1 4-3

C17 IO51RSB1

C18 NC

C19 TCK

C20 NC

C21 VPUMP

C22 VJTAG

C23 NC

C24 NC

C25 NC

C26 GDB0/IO38RSB0

132-Pin QFN*

Pin Number A3P030 Function

C27 NC

C28 VCCIB0

C29 IO32RSB0

C30 IO29RSB0

C31 IO28RSB0

C32 IO25RSB0

C33 NC

C34 NC

C35 VCCIB0

C36 IO17RSB0

132-Pin QFN*

Pin Number A3P030 Function

C37 IO14RSB0

C38 IO11RSB0

C39 IO07RSB0

C40 IO04RSB0

D1 GND

D2 GND

D3 GND

D4 GND

132-Pin QFN*

Pin Number A3P030 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

4-4 v2.1

132-Pin QFN

Pin Number A3P060 Function

A1 GAB2/IO00RSB1

A2 IO93RSB1

A3 VCCIB1

A4 GFC1/IO89RSB1

A5 GFB0/IO86RSB1

A6 VCCPLF

A7 GFA1/IO84RSB1

A8 GFC2/IO81RSB1

A9 IO78RSB1

A10 VCC

A11 GEB1/IO75RSB1

A12 GEA0/IO72RSB1

A13 GEC2/IO69RSB1

A14 IO65RSB1

A15 VCC

A16 IO64RSB1

A17 IO63RSB1

A18 IO62RSB1

A19 IO61RSB1

A20 IO58RSB1

A21 GDB2/IO55RSB1

A22 NC

A23 GDA2/IO54RSB1

A24 TDI

A25 TRST

A26 GDC1/IO48RSB0

A27 VCC

A28 IO47RSB0

A29 GCC2/IO46RSB0

A30 GCA2/IO44RSB0

A31 GCA0/IO43RSB0

A32 GCB1/IO40RSB0

A33 IO36RSB0

A34 VCC

A35 IO31RSB0

A36 GBA2/IO28RSB0

A37 GBB1/IO25RSB0

A38 GBC0/IO22RSB0

A39 VCCIB0

A40 IO21RSB0

A41 IO18RSB0

A42 IO15RSB0

A43 IO14RSB0

A44 IO11RSB0

A45 GAB1/IO08RSB0

A46 NC

A47 GAB0/IO07RSB0

A48 IO04RSB0

B1 IO01RSB1

B2 GAC2/IO94RSB1

B3 GND

B4 GFC0/IO88RSB1

B5 VCOMPLF

B6 GND

B7 GFB2/IO82RSB1

B8 IO79RSB1

B9 GND

B10 GEB0/IO74RSB1

B11 VMV1

B12 GEB2/IO70RSB1

B13 IO67RSB1

B14 GND

B15 NC

B16 NC

B17 GND

B18 IO59RSB1

B19 GDC2/IO56RSB1

B20 GND

B21 GNDQ

B22 TMS

B23 TDO

B24 GDC0/IO49RSB0

132-Pin QFN

Pin Number A3P060 Function

B25 GND

B26 NC

B27 GCB2/IO45RSB0

B28 GND

B29 GCB0/IO41RSB0

B30 GCC1/IO38RSB0

B31 GND

B32 GBB2/IO30RSB0

B33 VMV0

B34 GBA0/IO26RSB0

B35 GBC1/IO23RSB0

B36 GND

B37 IO20RSB0

B38 IO17RSB0

B39 GND

B40 IO12RSB0

B41 GAC0/IO09RSB0

B42 GND

B43 GAA1/IO06RSB0

B44 GNDQ

C1 GAA2/IO02RSB1

C2 IO95RSB1

C3 VCC

C4 GFB1/IO87RSB1

C5 GFA0/IO85RSB1

C6 GFA2/IO83RSB1

C7 IO80RSB1

C8 VCCIB1

C9 GEA1/IO73RSB1

C10 GNDQ

C11 GEA2/IO71RSB1

C12 IO68RSB1

C13 VCCIB1

C14 NC

C15 NC

C16 IO60RSB1

132-Pin QFN

Pin Number A3P060 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

v2.1 4-5

C17 IO57RSB1

C18 NC

C19 TCK

C20 VMV1

C21 VPUMP

C22 VJTAG

C23 VCCIB0

C24 NC

C25 NC

C26 GCA1/IO42RSB0

132-Pin QFN

Pin Number A3P060 Function

C27 GCC0/IO39RSB0

C28 VCCIB0

C29 IO29RSB0

C30 GNDQ

C31 GBA1/IO27RSB0

C32 GBB0/IO24RSB0

C33 VCC

C34 IO19RSB0

C35 IO16RSB0

C36 IO13RSB0

132-Pin QFN

Pin Number A3P060 Function

C37 GAC1/IO10RSB0

C38 NC

C39 GAA0/IO05RSB0

C40 VMV0

D1 GND

D2 GND

D3 GND

D4 GND

132-Pin QFN

Pin Number A3P060 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

4-6 v2.1

132-Pin QFN

Pin Number

A3P125

Function

A1 GAB2/IO69RSB1

A2 IO130RSB1

A3 VCCIB1

A4 GFC1/IO126RSB1

A5 GFB0/IO123RSB1

A6 VCCPLF

A7 GFA1/IO121RSB1

A8 GFC2/IO118RSB1

A9 IO115RSB1

A10 VCC

A11 GEB1/IO110RSB1

A12 GEA0/IO107RSB1

A13 GEC2/IO104RSB1

A14 IO100RSB1

A15 VCC

A16 IO99RSB1

A17 IO96RSB1

A18 IO94RSB1

A19 IO91RSB1

A20 IO85RSB1

A21 IO79RSB1

A22 VCC

A23 GDB2/IO71RSB1

A24 TDI

A25 TRST

A26 GDC1/IO61RSB0

A27 VCC

A28 IO60RSB0

A29 GCC2/IO59RSB0

A30 GCA2/IO57RSB0

A31 GCA0/IO56RSB0

A32 GCB1/IO53RSB0

A33 IO49RSB0

A34 VCC

A35 IO44RSB0

A36 GBA2/IO41RSB0

A37 GBB1/IO38RSB0

A38 GBC0/IO35RSB0

A39 VCCIB0

A40 IO28RSB0

A41 IO22RSB0

A42 IO18RSB0

A43 IO14RSB0

A44 IO11RSB0

A45 IO07RSB0

A46 VCC

A47 GAC1/IO05RSB0

A48 GAB0/IO02RSB0

B1 IO68RSB1

B2 GAC2/IO131RSB1

B3 GND

B4 GFC0/IO125RSB1

B5 VCOMPLF

B6 GND

B7 GFB2/IO119RSB1

B8 IO116RSB1

B9 GND

B10 GEB0/IO109RSB1

B11 VMV1

B12 GEB2/IO105RSB1

B13 IO101RSB1

B14 GND

B15 IO98RSB1

B16 IO95RSB1

B17 GND

B18 IO87RSB1

B19 IO81RSB1

B20 GND

B21 GNDQ

B22 TMS

132-Pin QFN

Pin Number

A3P125

Function

B23 TDO

B24 GDC0/IO62RSB0

B25 GND

B26 NC

B27 GCB2/IO58RSB0

B28 GND

B29 GCB0/IO54RSB0

B30 GCC1/IO51RSB0

B31 GND

B32 GBB2/IO43RSB0

B33 VMV0

B34 GBA0/IO39RSB0

B35 GBC1/IO36RSB0

B36 GND

B37 IO26RSB0

B38 IO21RSB0

B39 GND

B40 IO13RSB0

B41 IO08RSB0

B42 GND

B43 GAC0/IO04RSB0

B44 GNDQ

C1 GAA2/IO67RSB1

C2 IO132RSB1

C3 VCC

C4 GFB1/IO124RSB1

C5 GFA0/IO122RSB1

C6 GFA2/IO120RSB1

C7 IO117RSB1

C8 VCCIB1

C9 GEA1/IO108RSB1

C10 GNDQ

C11 GEA2/IO106RSB1

C12 IO103RSB1

C13 VCCIB1

132-Pin QFN

Pin Number

A3P125

Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

v2.1 4-7

C14 IO97RSB1

C15 IO93RSB1

C16 IO89RSB1

C17 IO83RSB1

C18 VCCIB1

C19 TCK

C20 VMV1

C21 VPUMP

C22 VJTAG

C23 VCCIB0

C24 NC

132-Pin QFN

Pin Number

A3P125

Function

C25 NC

C26 GCA1/IO55RSB0

C27 GCC0/IO52RSB0

C28 VCCIB0

C29 IO42RSB0

C30 GNDQ

C31 GBA1/IO40RSB0

C32 GBB0/IO37RSB0

C33 VCC

C34 IO24RSB0

C35 IO19RSB0

132-Pin QFN

Pin Number

A3P125

Function

C36 IO16RSB0

C37 IO10RSB0

C38 VCCIB0

C39 GAB1/IO03RSB0

C40 VMV0

D1 GND

D2 GND

D3 GND

D4 GND

132-Pin QFN

Pin Number

A3P125

Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

4-8 v2.1

132-Pin QFN

Pin Number

A3P250

Function

A1 GAB2/IO117UPB3

A2 IO117VPB3

A3 VCCIB3

A4 GFC1/IO110PDB3

A5 GFB0/IO109NPB3

A6 VCCPLF

A7 GFA1/IO108PPB3

A8 GFC2/IO105PPB3

A9 IO103NDB3

A10 VCC

A11 GEA1/IO98PPB3

A12 GEA0/IO98NPB3

A13 GEC2/IO95RSB2

A14 IO91RSB2

A15 VCC

A16 IO90RSB2

A17 IO87RSB2

A18 IO85RSB2

A19 IO82RSB2

A20 IO76RSB2

A21 IO70RSB2

A22 VCC

A23 GDB2/IO62RSB2

A24 TDI

A25 TRST

A26 GDC1/IO58UDB1

A27 VCC

A28 IO54NDB1

A29 IO52NDB1

A30 GCA2/IO51PPB1

A31 GCA0/IO50NPB1

A32 GCB1/IO49PDB1

A33 IO47NSB1

A34 VCC

A35 IO41NPB1

A36 GBA2/IO41PPB1

A37 GBB1/IO38RSB0

A38 GBC0/IO35RSB0

A39 VCCIB0

A40 IO28RSB0

A41 IO22RSB0

A42 IO18RSB0

A43 IO14RSB0

A44 IO11RSB0

A45 IO07RSB0

A46 VCC

A47 GAC1/IO05RSB0

A48 GAB0/IO02RSB0

B1 IO118VDB3

B2 GAC2/IO116UDB3

B3 GND

B4 GFC0/IO110NDB3

B5 VCOMPLF

B6 GND

B7 GFB2/IO106PSB3

B8 IO103PDB3

B9 GND

B10 GEB0/IO99NDB3

B11 VMV3

B12 GEB2/IO96RSB2

B13 IO92RSB2

B14 GND

B15 IO89RSB2

B16 IO86RSB2

B17 GND

B18 IO78RSB2

B19 IO72RSB2

B20 GND

B21 GNDQ

B22 TMS

132-Pin QFN

Pin Number

A3P250

Function

B23 TDO

B24 GDC0/IO58VDB1

B25 GND

B26 IO54PDB1

B27 GCB2/IO52PDB1

B28 GND

B29 GCB0/IO49NDB1

B30 GCC1/IO48PDB1

B31 GND

B32 GBB2/IO42PDB1

B33 VMV1

B34 GBA0/IO39RSB0

B35 GBC1/IO36RSB0

B36 GND

B37 IO26RSB0

B38 IO21RSB0

B39 GND

B40 IO13RSB0

B41 IO08RSB0

B42 GND

B43 GAC0/IO04RSB0

B44 GNDQ

C1 GAA2/IO118UDB3

C2 IO116VDB3

C3 VCC

C4 GFB1/IO109PPB3

C5 GFA0/IO108NPB3

C6 GFA2/IO107PSB3

C7 IO105NPB3

C8 VCCIB3

C9 GEB1/IO99PDB3

C10 GNDQ

C11 GEA2/IO97RSB2

C12 IO94RSB2

C13 VCCIB2

132-Pin QFN

Pin Number

A3P250

Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

v2.1 4-9

C14 IO88RSB2

C15 IO84RSB2

C16 IO80RSB2

C17 IO74RSB2

C18 VCCIB2

C19 TCK

C20 VMV2

C21 VPUMP

C22 VJTAG

C23 VCCIB1

C24 IO53NSB1

132-Pin QFN

Pin Number

A3P250

Function

C25 IO51NPB1

C26 GCA1/IO50PPB1

C27 GCC0/IO48NDB1

C28 VCCIB1

C29 IO42NDB1

C30 GNDQ

C31 GBA1/IO40RSB0

C32 GBB0/IO37RSB0

C33 VCC

C34 IO24RSB0

C35 IO19RSB0

132-Pin QFN

Pin Number

A3P250

Function

C36 IO16RSB0

C37 IO10RSB0

C38 VCCIB0

C39 GAB1/IO03RSB0

C40 VMV0

D1 GND

D2 GND

D3 GND

D4 GND

132-Pin QFN

Pin Number

A3P250

Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

4-10 v2.1

100-Pin VQFP

Note

For Package Manufacturing and Environmental information, visit the Resource Center at

http://www.actel.com/products/solutions/package/docs.aspx.

Note: This is the top view of the package.

100-Pin

VQFP

100

ProASIC3 Flash Family FPGAs

v2.1 4-11

100-Pin VQFP

Pin Number A3P030 Function

1GND

2 IO03RSB1

3 IO02RSB1

4 IO01RSB1

5 IO00RSB1

6 IO82RSB1

7 IO81RSB1

8 IO80RSB1

9GND

10 IO79RSB1

11 IO78RSB1

12 GEC0/IO77RSB1

13 GEA0/IO76RSB1

14 GEB0/IO75RSB1

15 IO74RSB1

16 IO73RSB1

17 VCC

18 VCCIB1

19 IO72RSB1

20 IO71RSB1

21 IO70RSB1

22 IO69RSB1

23 IO68RSB1

24 IO67RSB1

25 IO66RSB1

26 IO65RSB1

27 IO64RSB1

28 IO63RSB1

29 IO62RSB1

30 IO61RSB1

31 IO60RSB1

32 IO59RSB1

33 IO58RSB1

34 IO57RSB1

35 IO56RSB1

36 IO55RSB1

37 VCC

38 GND

39 VCCIB1

40 IO53RSB1

41 IO51RSB1

42 IO50RSB1

43 IO49RSB1

44 IO48RSB1

45 IO47RSB1

46 IO46RSB1

47 TCK

48 TDI

49 TMS

50 NC

51 GND

52 VPUMP

53 NC

54 TDO

55 TRST

56 VJTAG

57 IO45RSB0

58 IO44RSB0

59 IO43RSB0

60 IO42RSB0

61 IO41RSB0

62 IO40RSB0

63 IO39RSB0

64 GDB0/IO38RSB0

65 GDA0/IO37RSB0

66 VCCIB0

67 GND

68 VCC

69 IO35RSB0

70 IO34RSB0

71 IO33RSB0

72 IO32RSB0

100-Pin VQFP

Pin Number A3P030 Function

73 IO31RSB0

74 IO30RSB0

75 IO29RSB0

76 IO28RSB0

77 IO27RSB0

78 IO26RSB0

79 IO25RSB0

80 IO24RSB0

81 IO23RSB0

82 IO22RSB0

83 IO21RSB0

84 IO20RSB0

85 IO19RSB0

86 IO18RSB0

87 VCCIB0

88 GND

89 VCC

90 IO16RSB0

91 IO14RSB0

92 IO12RSB0

93 IO11RSB0

94 IO10RSB0

95 IO09RSB0

96 IO08RSB0

97 IO07RSB0

98 IO06RSB0

99 IO05RSB0

100 IO04RSB0

100-Pin VQFP

Pin Number A3P030 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

4-12 v2.1

100-Pin VQFP*

Pin Number A3P060 Function

1GND

2 GAA2/IO51RSB1

3 IO52RSB1

4 GAB2/IO53RSB1

5 IO95RSB1

6 GAC2/IO94RSB1

7 IO93RSB1

8 IO92RSB1

9GND

10 GFB1/IO87RSB1

11 GFB0/IO86RSB1

12 VCOMPLF

13 GFA0/IO85RSB1

14 VCCPLF

15 GFA1/IO84RSB1

16 GFA2/IO83RSB1

17 VCC

18 VCCIB1

19 GEC1/IO77RSB1

20 GEB1/IO75RSB1

21 GEB0/IO74RSB1

22 GEA1/IO73RSB1

23 GEA0/IO72RSB1

24 VMV1

25 GNDQ

26 GEA2/IO71RSB1

27 GEB2/IO70RSB1

28 GEC2/IO69RSB1

29 IO68RSB1

30 IO67RSB1

31 IO66RSB1

32 IO65RSB1

33 IO64RSB1

34 IO63RSB1

35 IO62RSB1

36 IO61RSB1

37 VCC

38 GND

39 VCCIB1

40 IO60RSB1

41 IO59RSB1

42 IO58RSB1

43 IO57RSB1

44 GDC2/IO56RSB1

45 GDB2/IO55RSB1

46 GDA2/IO54RSB1

47 TCK

48 TDI

49 TMS

50 VMV1

51 GND

52 VPUMP

53 NC

54 TDO

55 TRST

56 VJTAG

57 GDA1/IO49RSB0

58 GDC0/IO46RSB0

59 GDC1/IO45RSB0

60 GCC2/IO43RSB0

61 GCB2/IO42RSB0

62 GCA0/IO40RSB0

63 GCA1/IO39RSB0

64 GCC0/IO36RSB0

65 GCC1/IO35RSB0

66 VCCIB0

67 GND

68 VCC

100-Pin VQFP*

Pin Number A3P060 Function

69 IO31RSB0

70 GBC2/IO29RSB0

71 GBB2/IO27RSB0

72 IO26RSB0

73 GBA2/IO25RSB0

74 VMV0

75 GNDQ

76 GBA1/IO24RSB0

77 GBA0/IO23RSB0

78 GBB1/IO22RSB0

79 GBB0/IO21RSB0

80 GBC1/IO20RSB0

81 GBC0/IO19RSB0

82 IO18RSB0

83 IO17RSB0

84 IO15RSB0

85 IO13RSB0

86 IO11RSB0

87 VCCIB0

88 GND

89 VCC

90 IO10RSB0

91 IO09RSB0

92 IO08RSB0

93 GAC1/IO07RSB0

94 GAC0/IO06RSB0

95 GAB1/IO05RSB0

96 GAB0/IO04RSB0

97 GAA1/IO03RSB0

98 GAA0/IO02RSB0

99 IO01RSB0

100 IO00RSB0

100-Pin VQFP*

Pin Number A3P060 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

v2.1 4-13

100-Pin VQFP*

Pin Number A3P125 Function

1GND

2 GAA2/IO67RSB1

3 IO68RSB1

4 GAB2/IO69RSB1

5 IO132RSB1

6 GAC2/IO131RSB1

7 IO130RSB1

8 IO129RSB1

9GND

10 GFB1/IO124RSB1

11 GFB0/IO123RSB1

12 VCOMPLF

13 GFA0/IO122RSB1

14 VCCPLF

15 GFA1/IO121RSB1

16 GFA2/IO120RSB1

17 VCC

18 VCCIB1

19 GEC0/IO111RSB1

20 GEB1/IO110RSB1

21 GEB0/IO109RSB1

22 GEA1/IO108RSB1

23 GEA0/IO107RSB1

24 VMV1

25 GNDQ

26 GEA2/IO106RSB1

27 GEB2/IO105RSB1

28 GEC2/IO104RSB1

29 IO102RSB1

30 IO100RSB1

31 IO99RSB1

32 IO97RSB1

33 IO96RSB1

34 IO95RSB1

35 IO94RSB1

36 IO93RSB1

37 VCC

38 GND

39 VCCIB1

40 IO87RSB1

41 IO84RSB1

42 IO81RSB1

43 IO75RSB1

44 GDC2/IO72RSB1

45 GDB2/IO71RSB1

46 GDA2/IO70RSB1

47 TCK

48 TDI

49 TMS

50 VMV1

51 GND

52 VPUMP

53 NC

54 TDO

55 TRST

56 VJTAG

57 GDA1/IO65RSB0

58 GDC0/IO62RSB0

59 GDC1/IO61RSB0

60 GCC2/IO59RSB0

61 GCB2/IO58RSB0

62 GCA0/IO56RSB0

63 GCA1/IO55RSB0

64 GCC0/IO52RSB0

65 GCC1/IO51RSB0

66 VCCIB0

67 GND

68 VCC

100-Pin VQFP*

Pin Number A3P125 Function

69 IO47RSB0

70 GBC2/IO45RSB0

71 GBB2/IO43RSB0

72 IO42RSB0

73 GBA2/IO41RSB0

74 VMV0

75 GNDQ

76 GBA1/IO40RSB0

77 GBA0/IO39RSB0

78 GBB1/IO38RSB0

79 GBB0/IO37RSB0

80 GBC1/IO36RSB0

81 GBC0/IO35RSB0

82 IO32RSB0

83 IO28RSB0

84 IO25RSB0

85 IO22RSB0

86 IO19RSB0

87 VCCIB0

88 GND

89 VCC

90 IO15RSB0

91 IO13RSB0

92 IO11RSB0

93 IO09RSB0

94 IO07RSB0

95 GAC1/IO05RSB0

96 GAC0/IO04RSB0

97 GAB1/IO03RSB0

98 GAB0/IO02RSB0

99 GAA1/IO01RSB0

100 GAA0/IO00RSB0

100-Pin VQFP*

Pin Number A3P125 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

4-14 v2.1

100-Pin VQFP*

Pin Number A3P250 Function

1GND

2 GAA2/IO118UDB3

3 IO118VDB3

4 GAB2/IO117UDB3

5 IO117VDB3

6 GAC2/IO116UDB3

7 IO116VDB3

8 IO112PSB3

9GND

10 GFB1/IO109PDB3

11 GFB0/IO109NDB3

12 VCOMPLF

13 GFA0/IO108NPB3

14 VCCPLF

15 GFA1/IO108PPB3

16 GFA2/IO107PSB3

17 VCC

18 VCCIB3

19 GFC2/IO105PSB3

20 GEC1/IO100PDB3

21 GEC0/IO100NDB3

22 GEA1/IO98PDB3

23 GEA0/IO98NDB3

24 VMV3

25 GNDQ

26 GEA2/IO97RSB2

27 GEB2/IO96RSB2

28 GEC2/IO95RSB2

29 IO93RSB2

30 IO92RSB2

31 IO91RSB2

32 IO90RSB2

33 IO88RSB2

34 IO86RSB2

35 IO85RSB2

36 IO84RSB2

37 VCC

38 GND

39 VCCIB2

40 IO77RSB2

41 IO74RSB2

42 IO71RSB2

43 GDC2/IO63RSB2

44 GDB2/IO62RSB2

45 GDA2/IO61RSB2

46 GNDQ

47 TCK

48 TDI

49 TMS

50 VMV2

51 GND

52 VPUMP

53 NC

54 TDO

55 TRST

56 VJTAG

57 GDA1/IO60USB1

58 GDC0/IO58VDB1

59 GDC1/IO58UDB1

60 IO52NDB1

61 GCB2/IO52PDB1

62 GCA1/IO50PDB1

63 GCA0/IO50NDB1

64 GCC0/IO48NDB1

65 GCC1/IO48PDB1

66 VCCIB1

67 GND

68 VCC

100-Pin VQFP*

Pin Number A3P250 Function

69 IO43NDB1

70 GBC2/IO43PDB1

71 GBB2/IO42PSB1

72 IO41NDB1

73 GBA2/IO41PDB1

74 VMV1

75 GNDQ

76 GBA1/IO40RSB0

77 GBA0/IO39RSB0

78 GBB1/IO38RSB0

79 GBB0/IO37RSB0

80 GBC1/IO36RSB0

81 GBC0/IO35RSB0

82 IO29RSB0

83 IO27RSB0

84 IO25RSB0

85 IO23RSB0

86 IO21RSB0

87 VCCIB0

88 GND

89 VCC

90 IO15RSB0

91 IO13RSB0

92 IO11RSB0

93 GAC1/IO05RSB0

94 GAC0/IO04RSB0

95 GAB1/IO03RSB0

96 GAB0/IO02RSB0

97 GAA1/IO01RSB0

98 GAA0/IO00RSB0

99 GNDQ

100 VMV0

100-Pin VQFP*

Pin Number A3P250 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

v2.1 4-15

144-Pin TQFP

Note

For Package Manufacturing and Environmental information, visit the Resource Center at

http://www.actel.com/products/solutions/package/docs.aspx.

Note: This is the top view of the package.

144

144-Pin

TQFP

ProASIC3 Flash Family FPGAs

4-16 v2.1

144-Pin TQFP*

Pin Number A3P060 Function

1 GAA2/IO51RSB1

2 IO52RSB1

3 GAB2/IO53RSB1

4 IO95RSB1

5 GAC2/IO94RSB1

6 IO93RSB1

7 IO92RSB1

8 IO91RSB1

10 GND

11 VCCIB1

12 IO90RSB1

13 GFC1/IO89RSB1

14 GFC0/IO88RSB1

15 GFB1/IO87RSB1

16 GFB0/IO86RSB1

17 VCOMPLF

18 GFA0/IO85RSB1

19 VCCPLF

20 GFA1/IO84RSB1

21 GFA2/IO83RSB1

22 GFB2/IO82RSB1

23 GFC2/IO81RSB1

24 IO80RSB1

25 IO79RSB1

26 IO78RSB1

27 GND

28 VCCIB1

29 GEC1/IO77RSB1

30 GEC0/IO76RSB1

31 GEB1/IO75RSB1

32 GEB0/IO74RSB1

33 GEA1/IO73RSB1

34 GEA0/IO72RSB1

35 VMV1

36 GNDQ

37 NC

38 GEA2/IO71RSB1

39 GEB2/IO70RSB1

40 GEC2/IO69RSB1

41 IO68RSB1

42 IO67RSB1

43 IO66RSB1

44 IO65RSB1

45 VCC

46 GND

47 VCCIB1

48 NC

49 IO64RSB1

50 NC

51 IO63RSB1

52 NC

53 IO62RSB1

54 NC

55 IO61RSB1

56 NC

57 NC

58 IO60RSB1

59 IO59RSB1

60 IO58RSB1

61 IO57RSB1

62 NC

63 GND

64 NC

65 GDC2/IO56RSB1

66 GDB2/IO55RSB1

67 GDA2/IO54RSB1

68 GNDQ

69 TCK

70 TDI

71 TMS

72 VMV1

144-Pin TQFP*

Pin Number A3P060 Function

73 VPUMP

74 NC

75 TDO

76 TRST

77 VJTAG

78 GDA0/IO50RSB0

79 GDB0/IO48RSB0

80 GDB1/IO47RSB0

81 VCCIB0

82 GND

83 IO44RSB0

84 GCC2/IO43RSB0

85 GCB2/IO42RSB0

86 GCA2/IO41RSB0

87 GCA0/IO40RSB0

88 GCA1/IO39RSB0

89 GCB0/IO38RSB0

90 GCB1/IO37RSB0

91 GCC0/IO36RSB0

92 GCC1/IO35RSB0

93 IO34RSB0

94 IO33RSB0

95 NC

96 NC

97 NC

98 VCCIB0

99 GND

100 VCC

101 IO30RSB0

102 GBC2/IO29RSB0

103 IO28RSB0

104 GBB2/IO27RSB0

105 IO26RSB0

106 GBA2/IO25RSB0

107 VMV0

108 GNDQ

144-Pin TQFP*

Pin Number A3P060 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

v2.1 4-17

109 NC

110 NC

111 GBA1/IO24RSB0

112 GBA0/IO23RSB0

113 GBB1/IO22RSB0

114 GBB0/IO21RSB0

115 GBC1/IO20RSB0

116 GBC0/IO19RSB0

117 VCCIB0

118 GND

119 VCC

120 IO18RSB0

144-Pin TQFP*

Pin Number A3P060 Function

121 IO17RSB0

122 IO16RSB0

123 IO15RSB0

124 IO14RSB0

125 IO13RSB0

126 IO12RSB0

127 IO11RSB0

128 NC

129 IO10RSB0

130 IO09RSB0

131 IO08RSB0

132 GAC1/IO07RSB0

144-Pin TQFP*

Pin Number A3P060 Function

133 GAC0/IO06RSB0

134 NC

135 GND

136 NC

137 GAB1/IO05RSB0

138 GAB0/IO04RSB0

139 GAA1/IO03RSB0

140 GAA0/IO02RSB0

141 IO01RSB0

142 IO00RSB0

143 GNDQ

144 VMV0

144-Pin TQFP*

Pin Number A3P060 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

4-18 v2.1

144-Pin TQFP*

Pin Number A3P125 Function

1 GAA2/IO67RSB1

2 IO68RSB1

3 GAB2/IO69RSB1

4 IO132RSB1

5 GAC2/IO131RSB1

6 IO130RSB1

7 IO129RSB1

8 IO128RSB1

10 GND

11 VCCIB1

12 IO127RSB1

13 GFC1/IO126RSB1

14 GFC0/IO125RSB1

15 GFB1/IO124RSB1

16 GFB0/IO123RSB1

17 VCOMPLF

18 GFA0/IO122RSB1

19 VCCPLF

20 GFA1/IO121RSB1

21 GFA2/IO120RSB1

22 GFB2/IO119RSB1

23 GFC2/IO118RSB1

24 IO117RSB1

25 IO116RSB1

26 IO115RSB1

27 GND

28 VCCIB1

29 GEC1/IO112RSB1

30 GEC0/IO111RSB1

31 GEB1/IO110RSB1

32 GEB0/IO109RSB1

33 GEA1/IO108RSB1

34 GEA0/IO107RSB1

35 VMV1

36 GNDQ

37 NC

38 GEA2/IO106RSB1

39 GEB2/IO105RSB1

40 GEC2/IO104RSB1

41 IO103RSB1

42 IO102RSB1

43 IO101RSB1

44 IO100RSB1

45 VCC

46 GND

47 VCCIB1

48 IO99RSB1

49 IO97RSB1

50 IO95RSB1

51 IO93RSB1

52 IO92RSB1

53 IO90RSB1

54 IO88RSB1

55 IO86RSB1

56 IO84RSB1

57 IO83RSB1

58 IO82RSB1

59 IO81RSB1

60 IO80RSB1

61 IO79RSB1

62 VCC

63 GND

64 VCCIB1

65 GDC2/IO72RSB1

66 GDB2/IO71RSB1

67 GDA2/IO70RSB1

68 GNDQ

69 TCK

70 TDI

71 TMS

72 VMV1

144-Pin TQFP*

Pin Number A3P125 Function

73 VPUMP

74 NC

75 TDO

76 TRST

77 VJTAG

78 GDA0/IO66RSB0

79 GDB0/IO64RSB0

80 GDB1/IO63RSB0

81 VCCIB0

82 GND

83 IO60RSB0

84 GCC2/IO59RSB0

85 GCB2/IO58RSB0

86 GCA2/IO57RSB0

87 GCA0/IO56RSB0

88 GCA1/IO55RSB0

89 GCB0/IO54RSB0

90 GCB1/IO53RSB0

91 GCC0/IO52RSB0

92 GCC1/IO51RSB0

93 IO50RSB0

94 IO49RSB0

95 NC

96 NC

97 NC

98 VCCIB0

99 GND

100 VCC

101 IO47RSB0

102 GBC2/IO45RSB0

103 IO44RSB0

104 GBB2/IO43RSB0

105 IO42RSB0

106 GBA2/IO41RSB0

107 VMV0

108 GNDQ

144-Pin TQFP*

Pin Number A3P125 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

v2.1 4-19

109 GBA1/IO40RSB0

110 GBA0/IO39RSB0

111 GBB1/IO38RSB0

112 GBB0/IO37RSB0

113 GBC1/IO36RSB0

114 GBC0/IO35RSB0

115 IO34RSB0

116 IO33RSB0

117 VCCIB0

118 GND

119 VCC

120 IO29RSB0

144-Pin TQFP*

Pin Number A3P125 Function

121 IO28RSB0

122 IO27RSB0

123 IO25RSB0

124 IO23RSB0

125 IO21RSB0

126 IO19RSB0

127 IO17RSB0

128 IO16RSB0

129 IO14RSB0

130 IO12RSB0

131 IO10RSB0

132 IO08RSB0

144-Pin TQFP*

Pin Number A3P125 Function

133 IO06RSB0

134 VCCIB0

135 GND

136 VCC

137 GAC1/IO05RSB0

138 GAC0/IO04RSB0

139 GAB1/IO03RSB0

140 GAB0/IO02RSB0

141 GAA1/IO01RSB0

142 GAA0/IO00RSB0

143 GNDQ

144 VMV0

144-Pin TQFP*

Pin Number A3P125 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

4-20 v2.1

208-Pin PQFP

Note

For Package Manufacturing and Environmental information, visit the Resource Center at

http://www.actel.com/products/solutions/package/docs.aspx.

Note: This is the top view of the package.

208-Pin PQFP

1208

ProASIC3 Flash Family FPGAs

v2.1 4-21

208-Pin PQFP*

Pin Number A3P125 Function

1GND

2 GAA2/IO67RSB1

3 IO68RSB1

4 GAB2/IO69RSB1

5 IO132RSB1

6 GAC2/IO131RSB1

7NC

8NC

9 IO130RSB1

10 IO129RSB1

11 NC

12 IO128RSB1

13 NC

14 NC

15 NC

16 VCC

17 GND

18 VCCIB1

19 IO127RSB1

20 NC

21 GFC1/IO126RSB1

22 GFC0/IO125RSB1

23 GFB1/IO124RSB1

24 GFB0/IO123RSB1

25 VCOMPLF

26 GFA0/IO122RSB1

27 VCCPLF

28 GFA1/IO121RSB1

29 GND

30 GFA2/IO120RSB1

31 NC

32 GFB2/IO119RSB1

33 NC

34 GFC2/IO118RSB1

35 IO117RSB1

36 NC

37 IO116RSB1

38 IO115RSB1

39 NC

40 VCCIB1

41 GND

42 IO114RSB1

43 IO113RSB1

44 GEC1/IO112RSB1

45 GEC0/IO111RSB1

46 GEB1/IO110RSB1

47 GEB0/IO109RSB1

48 GEA1/IO108RSB1

49 GEA0/IO107RSB1

50 VMV1

51 GNDQ

52 GND

53 NC

54 NC

55 GEA2/IO106RSB1

56 GEB2/IO105RSB1

57 GEC2/IO104RSB1

58 IO103RSB1

59 IO102RSB1

60 IO101RSB1

61 IO100RSB1

62 VCCIB1

63 IO99RSB1

64 IO98RSB1

65 GND

66 IO97RSB1

67 IO96RSB1

68 IO95RSB1

69 IO94RSB1

70 IO93RSB1

71 VCC

72 VCCIB1

208-Pin PQFP*

Pin Number A3P125 Function

73 IO92RSB1

74 IO91RSB1

75 IO90RSB1

76 IO89RSB1

77 IO88RSB1

78 IO87RSB1

79 IO86RSB1

80 IO85RSB1

81 GND

82 IO84RSB1

83 IO83RSB1

84 IO82RSB1

85 IO81RSB1

86 IO80RSB1

87 IO79RSB1

88 VCC

89 VCCIB1

90 IO78RSB1

91 IO77RSB1

92 IO76RSB1

93 IO75RSB1

94 IO74RSB1

95 IO73RSB1

96 GDC2/IO72RSB1

97 GND

98 GDB2/IO71RSB1

99 GDA2/IO70RSB1

100 GNDQ

101 TCK

102 TDI

103 TMS

104 VMV1

105 GND

106 VPUMP

107 NC

108 TDO

208-Pin PQFP*

Pin Number A3P125 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

4-22 v2.1

109 TRST

110 VJTAG

111 GDA0/IO66RSB0

112 GDA1/IO65RSB0

113 GDB0/IO64RSB0

114 GDB1/IO63RSB0

115 GDC0/IO62RSB0

116 GDC1/IO61RSB0

117 NC

118 NC

119 NC

120 NC

121 NC

122 GND

123 VCCIB0

124 NC

125 NC

126 VCC

127 IO60RSB0

128 GCC2/IO59RSB0

129 GCB2/IO58RSB0

130 GND

131 GCA2/IO57RSB0

132 GCA0/IO56RSB0

133 GCA1/IO55RSB0

134 GCB0/IO54RSB0

135 GCB1/IO53RSB0

136 GCC0/IO52RSB0

137 GCC1/IO51RSB0

138 IO50RSB0

139 IO49RSB0

140 VCCIB0

141 GND

142 VCC

208-Pin PQFP*

Pin Number A3P125 Function

143 IO48RSB0

144 IO47RSB0

145 IO46RSB0

146 NC

147 NC

148 NC

149 GBC2/IO45RSB0

150 IO44RSB0

151 GBB2/IO43RSB0

152 IO42RSB0

153 GBA2/IO41RSB0

154 VMV0

155 GNDQ

156 GND

157 NC

158 GBA1/IO40RSB0

159 GBA0/IO39RSB0

160 GBB1/IO38RSB0

161 GBB0/IO37RSB0

162 GND

163 GBC1/IO36RSB0

164 GBC0/IO35RSB0

165 IO34RSB0

166 IO33RSB0

167 IO32RSB0

168 IO31RSB0

169 IO30RSB0

170 VCCIB0

171 VCC

172 IO29RSB0

173 IO28RSB0

174 IO27RSB0

175 IO26RSB0

176 IO25RSB0

208-Pin PQFP*

Pin Number A3P125 Function

177 IO24RSB0

178 GND

179 IO23RSB0

180 IO22RSB0

181 IO21RSB0

182 IO20RSB0

183 IO19RSB0

184 IO18RSB0

185 IO17RSB0

186 VCCIB0

187 VCC

188 IO16RSB0

189 IO15RSB0

190 IO14RSB0

191 IO13RSB0

192 IO12RSB0

193 IO11RSB0

194 IO10RSB0

195 GND

196 IO09RSB0

197 IO08RSB0

198 IO07RSB0

199 IO06RSB0

200 VCCIB0

201 GAC1/IO05RSB0

202 GAC0/IO04RSB0

203 GAB1/IO03RSB0

204 GAB0/IO02RSB0

205 GAA1/IO01RSB0

206 GAA0/IO00RSB0

207 GNDQ

208 VMV0

208-Pin PQFP*

Pin Number A3P125 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

v2.1 4-23

208-Pin PQFP*

Pin Number A3P250 Function

1GND

2 GAA2/IO118UDB3

3 IO118VDB3

4 GAB2/IO117UDB3

5 IO117VDB3

6 GAC2/IO116UDB3

7 IO116VDB3

8 IO115UDB3

9 IO115VDB3

10 IO114UDB3

11 IO114VDB3

12 IO113PDB3

13 IO113NDB3

14 IO112PDB3

15 IO112NDB3

16 VCC

17 GND

18 VCCIB3

19 IO111PDB3

20 IO111NDB3

21 GFC1/IO110PDB3

22 GFC0/IO110NDB3

23 GFB1/IO109PDB3

24 GFB0/IO109NDB3

25 VCOMPLF

26 GFA0/IO108NPB3

27 VCCPLF

28 GFA1/IO108PPB3

29 GND

30 GFA2/IO107PDB3

31 IO107NDB3

32 GFB2/IO106PDB3

33 IO106NDB3

34 GFC2/IO105PDB3

35 IO105NDB3

36 NC

37 IO104PDB3

38 IO104NDB3

39 IO103PSB3

40 VCCIB3

41 GND

42 IO101PDB3

43 IO101NDB3

44 GEC1/IO100PDB3

45 GEC0/IO100NDB3

46 GEB1/IO99PDB3

47 GEB0/IO99NDB3

48 GEA1/IO98PDB3

49 GEA0/IO98NDB3

50 VMV3

51 GNDQ

52 GND

53 NC

54 NC

55 GEA2/IO97RSB2

56 GEB2/IO96RSB2

57 GEC2/IO95RSB2

58 IO94RSB2

59 IO93RSB2

60 IO92RSB2

61 IO91RSB2

62 VCCIB2

63 IO90RSB2

64 IO89RSB2

65 GND

66 IO88RSB2

67 IO87RSB2

68 IO86RSB2

69 IO85RSB2

70 IO84RSB2

71 VCC

72 VCCIB2

208-Pin PQFP*

Pin Number A3P250 Function

73 IO83RSB2

74 IO82RSB2

75 IO81RSB2

76 IO80RSB2

77 IO79RSB2

78 IO78RSB2

79 IO77RSB2

80 IO76RSB2

81 GND

82 IO75RSB2

83 IO74RSB2

84 IO73RSB2

85 IO72RSB2

86 IO71RSB2

87 IO70RSB2

88 VCC

89 VCCIB2

90 IO69RSB2

91 IO68RSB2

92 IO67RSB2

93 IO66RSB2

94 IO65RSB2

95 IO64RSB2

96 GDC2/IO63RSB2

97 GND

98 GDB2/IO62RSB2

99 GDA2/IO61RSB2

100 GNDQ

101 TCK

102 TDI

103 TMS

104 VMV2

105 GND

106 VPUMP

107 NC

108 TDO

208-Pin PQFP*

Pin Number A3P250 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

4-24 v2.1

109 TRST

110 VJTAG

111 GDA0/IO60VDB1

112 GDA1/IO60UDB1

113 GDB0/IO59VDB1

114 GDB1/IO59UDB1

115 GDC0/IO58VDB1

116 GDC1/IO58UDB1

117 IO57VDB1

118 IO57UDB1

119 IO56NDB1

120 IO56PDB1

121 IO55RSB1

122 GND

123 VCCIB1

124 NC

125 NC

126 VCC

127 IO53NDB1

128 GCC2/IO53PDB1

129 GCB2/IO52PSB1

130 GND

131 GCA2/IO51PSB1

132 GCA1/IO50PDB1

133 GCA0/IO50NDB1

134 GCB0/IO49NDB1

135 GCB1/IO49PDB1

136 GCC0/IO48NDB1

137 GCC1/IO48PDB1

138 IO47NDB1

139 IO47PDB1

140 VCCIB1

141 GND

142 VCC

208-Pin PQFP*

Pin Number A3P250 Function

143 IO46RSB1

144 IO45NDB1

145 IO45PDB1

146 IO44NDB1

147 IO44PDB1

148 IO43NDB1

149 GBC2/IO43PDB1

150 IO42NDB1

151 GBB2/IO42PDB1

152 IO41NDB1

153 GBA2/IO41PDB1

154 VMV1

155 GNDQ

156 GND

157 NC

158 GBA1/IO40RSB0

159 GBA0/IO39RSB0

160 GBB1/IO38RSB0

161 GBB0/IO37RSB0

162 GND

163 GBC1/IO36RSB0

164 GBC0/IO35RSB0

165 IO34RSB0

166 IO33RSB0

167 IO32RSB0

168 IO31RSB0

169 IO30RSB0

170 VCCIB0

171 VCC

172 IO29RSB0

173 IO28RSB0

174 IO27RSB0

175 IO26RSB0

176 IO25RSB0

208-Pin PQFP*

Pin Number A3P250 Function

177 IO24RSB0

178 GND

179 IO23RSB0

180 IO22RSB0

181 IO21RSB0

182 IO20RSB0

183 IO19RSB0

184 IO18RSB0

185 IO17RSB0

186 VCCIB0

187 VCC

188 IO16RSB0

189 IO15RSB0

190 IO14RSB0

191 IO13RSB0

192 IO12RSB0

193 IO11RSB0

194 IO10RSB0

195 GND

196 IO09RSB0

197 IO08RSB0

198 IO07RSB0

199 IO06RSB0

200 VCCIB0

201 GAC1/IO05RSB0

202 GAC0/IO04RSB0

203 GAB1/IO03RSB0

204 GAB0/IO02RSB0

205 GAA1/IO01RSB0

206 GAA0/IO00RSB0

207 GNDQ

208 VMV0

208-Pin PQFP*

Pin Number A3P250 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

v2.1 4-25

208-Pin PQFP*

Pin Number A3P400 Function

1GND

2 GAA2/IO155UDB3

3 IO155VDB3

4 GAB2/IO154UDB3

5 IO154VDB3

6 GAC2/IO153UDB3

7 IO153VDB3

8 IO152UDB3

9 IO152VDB3

10 IO151UDB3

11 IO151VDB3

12 IO150PDB3

13 IO150NDB3

14 IO149PDB3

15 IO149NDB3

16 VCC

17 GND

18 VCCIB3

19 IO148PDB3

20 IO148NDB3

21 GFC1/IO147PDB3

22 GFC0/IO147NDB3

23 GFB1/IO146PDB3

24 GFB0/IO146NDB3

25 VCOMPLF

26 GFA0/IO145NPB3

27 VCCPLF

28 GFA1/IO145PPB3

29 GND

30 GFA2/IO144PDB3

31 IO144NDB3

32 GFB2/IO143PDB3

33 IO143NDB3

34 GFC2/IO142PDB3

35 IO142NDB3

36 NC

37 IO141PSB3

38 IO140PDB3

39 IO140NDB3

40 VCCIB3

41 GND

42 IO138PDB3

43 IO138NDB3

44 GEC1/IO137PDB3

45 GEC0/IO137NDB3

46 GEB1/IO136PDB3

47 GEB0/IO136NDB3

48 GEA1/IO135PDB3

49 GEA0/IO135NDB3

50 VMV3

51 GNDQ

52 GND

53 VMV2

54 NC

55 GEA2/IO134RSB2

56 GEB2/IO133RSB2

57 GEC2/IO132RSB2

58 IO131RSB2

59 IO130RSB2

60 IO129RSB2

61 IO128RSB2

62 VCCIB2

63 IO125RSB2

64 IO123RSB2

65 GND

66 IO121RSB2

67 IO119RSB2

68 IO117RSB2

69 IO115RSB2

70 IO113RSB2

71 VCC

72 VCCIB2

208-Pin PQFP*

Pin Number A3P400 Function

73 IO112RSB2

74 IO111RSB2

75 IO110RSB2

76 IO109RSB2

77 IO108RSB2

78 IO107RSB2

79 IO106RSB2

80 IO104RSB2

81 GND

82 IO102RSB2

83 IO101RSB2

84 IO100RSB2

85 IO99RSB2

86 IO98RSB2

87 IO97RSB2

88 VCC

89 VCCIB2

90 IO94RSB2

91 IO92RSB2

92 IO90RSB2

93 IO88RSB2

94 IO86RSB2

95 IO84RSB2

96 GDC2/IO82RSB2

97 GND

98 GDB2/IO81RSB2

99 GDA2/IO80RSB2

100 GNDQ

101 TCK

102 TDI

103 TMS

104 VMV2

105 GND

106 VPUMP

107 NC

108 TDO

208-Pin PQFP*

Pin Number A3P400 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

4-26 v2.1

109 TRST

110 VJTAG

111 GDA0/IO79VDB1

112 GDA1/IO79UDB1

113 GDB0/IO78VDB1

114 GDB1/IO78UDB1

115 GDC0/IO77VDB1

116 GDC1/IO77UDB1

117 IO76VDB1

118 IO76UDB1

119 IO75NDB1

120 IO75PDB1

121 IO74RSB1

122 GND

123 VCCIB1

124 NC

125 NC

126 VCC

127 IO72NDB1

128 GCC2/IO72PDB1

129 GCB2/IO71PSB1

130 GND

131 GCA2/IO70PSB1

132 GCA1/IO69PDB1

133 GCA0/IO69NDB1

134 GCB0/IO68NDB1

135 GCB1/IO68PDB1

136 GCC0/IO67NDB1

137 GCC1/IO67PDB1

138 IO66NDB1

139 IO66PDB1

140 VCCIB1

141 GND

142 VCC

208-Pin PQFP*

Pin Number A3P400 Function

143 IO65RSB1

144 IO64NDB1

145 IO64PDB1

146 IO63NDB1

147 IO63PDB1

148 IO62NDB1

149 GBC2/IO62PDB1

150 IO61NDB1

151 GBB2/IO61PDB1

152 IO60NDB1

153 GBA2/IO60PDB1

154 VMV1

155 GNDQ

156 GND

157 VMV0

158 GBA1/IO59RSB0

159 GBA0/IO58RSB0

160 GBB1/IO57RSB0

161 GBB0/IO56RSB0

162 GND

163 GBC1/IO55RSB0

164 GBC0/IO54RSB0

165 IO52RSB0

166 IO49RSB0

167 IO46RSB0

168 IO43RSB0

169 IO40RSB0

170 VCCIB0

171 VCC

172 IO36RSB0

173 IO35RSB0

174 IO34RSB0

175 IO33RSB0

176 IO32RSB0

208-Pin PQFP*

Pin Number A3P400 Function

177 IO31RSB0

178 GND

179 IO29RSB0

180 IO28RSB0

181 IO27RSB0

182 IO26RSB0

183 IO25RSB0

184 IO24RSB0

185 IO23RSB0

186 VCCIB0

187 VCC

188 IO21RSB0

189 IO20RSB0

190 IO19RSB0

191 IO18RSB0

192 IO17RSB0

193 IO16RSB0

194 IO15RSB0

195 GND

196 IO13RSB0

197 IO11RSB0

198 IO09RSB0

199 IO07RSB0

200 VCCIB0

201 GAC1/IO05RSB0

202 GAC0/IO04RSB0

203 GAB1/IO03RSB0

204 GAB0/IO02RSB0

205 GAA1/IO01RSB0

206 GAA0/IO00RSB0

207 GNDQ

208 VMV0

208-Pin PQFP*

Pin Number A3P400 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

v2.1 4-27

208-Pin PQFP*

Pin Number A3P600 Function

1GND

2 GAA2/IO174PDB3

3 IO174NDB3

4 GAB2/IO173PDB3

5 IO173NDB3

6 GAC2/IO172PDB3

7 IO172NDB3

8 IO171PDB3

9 IO171NDB3

10 IO170PDB3

11 IO170NDB3

12 IO169PDB3

13 IO169NDB3

14 IO168PDB3

15 IO168NDB3

16 VCC

17 GND

18 VCCIB3

19 IO166PDB3

20 IO166NDB3

21 GFC1/IO164PDB3

22 GFC0/IO164NDB3

23 GFB1/IO163PDB3

24 GFB0/IO163NDB3

25 VCOMPLF

26 GFA0/IO162NPB3

27 VCCPLF

28 GFA1/IO162PPB3

29 GND

30 GFA2/IO161PDB3

31 IO161NDB3

32 GFB2/IO160PDB3

33 IO160NDB3

34 GFC2/IO159PDB3

35 IO159NDB3

36 VCC

37 IO152PDB3

38 IO152NDB3

39 IO150PSB3

40 VCCIB3

41 GND

42 IO147PDB3

43 IO147NDB3

44 GEC1/IO146PDB3

45 GEC0/IO146NDB3

46 GEB1/IO145PDB3

47 GEB0/IO145NDB3

48 GEA1/IO144PDB3

49 GEA0/IO144NDB3

50 VMV3

51 GNDQ

52 GND

53 VMV2

54 GEA2/IO143RSB2

55 GEB2/IO142RSB2

56 GEC2/IO141RSB2

57 IO140RSB2

58 IO139RSB2

59 IO138RSB2

60 IO137RSB2

61 IO136RSB2

62 VCCIB2

63 IO135RSB2

64 IO133RSB2

65 GND

66 IO131RSB2

67 IO129RSB2

68 IO127RSB2

69 IO125RSB2

70 IO123RSB2

71 VCC

72 VCCIB2

208-Pin PQFP*

Pin Number A3P600 Function

73 IO120RSB2

74 IO119RSB2

75 IO118RSB2

76 IO117RSB2

77 IO116RSB2

78 IO115RSB2

79 IO114RSB2

80 IO112RSB2

81 GND

82 IO111RSB2

83 IO110RSB2

84 IO109RSB2

85 IO108RSB2

86 IO107RSB2

87 IO106RSB2

88 VCC

89 VCCIB2

90 IO104RSB2

91 IO102RSB2

92 IO100RSB2

93 IO98RSB2

94 IO96RSB2

95 IO92RSB2

96 GDC2/IO91RSB2

97 GND

98 GDB2/IO90RSB2

99 GDA2/IO89RSB2

100 GNDQ

101 TCK

102 TDI

103 TMS

104 VMV2

105 GND

106 VPUMP

107 GNDQ

108 TDO

208-Pin PQFP*

Pin Number A3P600 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

4-28 v2.1

109 TRST

110 VJTAG

111 GDA0/IO88NDB1

112 GDA1/IO88PDB1

113 GDB0/IO87NDB1

114 GDB1/IO87PDB1

115 GDC0/IO86NDB1

116 GDC1/IO86PDB1

117 IO84NDB1

118 IO84PDB1

119 IO82NDB1

120 IO82PDB1

121 IO81PSB1

122 GND

123 VCCIB1

124 IO77NDB1

125 IO77PDB1

126 NC

127 IO74NDB1

128 GCC2/IO74PDB1

129 GCB2/IO73PSB1

130 GND

131 GCA2/IO72PSB1

132 GCA1/IO71PDB1

133 GCA0/IO71NDB1

134 GCB0/IO70NDB1

135 GCB1/IO70PDB1

136 GCC0/IO69NDB1

137 GCC1/IO69PDB1

138 IO67NDB1

139 IO67PDB1

140 VCCIB1

141 GND

208-Pin PQFP*

Pin Number A3P600 Function

142 VCC

143 IO65PSB1

144 IO64NDB1

145 IO64PDB1

146 IO63NDB1

147 IO63PDB1

148 IO62NDB1

149 GBC2/IO62PDB1

150 IO61NDB1

151 GBB2/IO61PDB1

152 IO60NDB1

153 GBA2/IO60PDB1

154 VMV1

155 GNDQ

156 GND

157 VMV0

158 GBA1/IO59RSB0

159 GBA0/IO58RSB0

160 GBB1/IO57RSB0

161 GBB0/IO56RSB0

162 GND

163 GBC1/IO55RSB0

164 GBC0/IO54RSB0

165 IO52RSB0

166 IO50RSB0

167 IO48RSB0

168 IO46RSB0

169 IO44RSB0

170 VCCIB0

171 VCC

172 IO36RSB0

173 IO35RSB0

174 IO34RSB0

208-Pin PQFP*

Pin Number A3P600 Function

175 IO33RSB0

176 IO32RSB0

177 IO31RSB0

178 GND

179 IO29RSB0

180 IO28RSB0

181 IO27RSB0

182 IO26RSB0

183 IO25RSB0

184 IO24RSB0

185 IO23RSB0

186 VCCIB0

187 VCC

188 IO20RSB0

189 IO19RSB0

190 IO18RSB0

191 IO17RSB0

192 IO16RSB0

193 IO14RSB0

194 IO12RSB0

195 GND

196 IO10RSB0

197 IO09RSB0

198 IO08RSB0

199 IO07RSB0

200 VCCIB0

201 GAC1/IO05RSB0

202 GAC0/IO04RSB0

203 GAB1/IO03RSB0

204 GAB0/IO02RSB0

205 GAA1/IO01RSB0

206 GAA0/IO00RSB0

207 GNDQ

208 VMV0

208-Pin PQFP*

Pin Number A3P600 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

v2.1 4-29

208-Pin PQFP*

Pin Number A3P1000 Function

1GND

2 GAA2/IO225PDB3

3 IO225NDB3

4 GAB2/IO224PDB3

5 IO224NDB3

6 GAC2/IO223PDB3

7 IO223NDB3

8 IO222PDB3

9 IO222NDB3

10 IO220PDB3

11 IO220NDB3

12 IO218PDB3

13 IO218NDB3

14 IO216PDB3

15 IO216NDB3

16 VCC

17 GND

18 VCCIB3

19 IO212PDB3

20 IO212NDB3

21 GFC1/IO209PDB3

22 GFC0/IO209NDB3

23 GFB1/IO208PDB3

24 GFB0/IO208NDB3

25 VCOMPLF

26 GFA0/IO207NPB3

27 VCCPLF

28 GFA1/IO207PPB3

29 GND

30 GFA2/IO206PDB3

31 IO206NDB3

32 GFB2/IO205PDB3

33 IO205NDB3

34 GFC2/IO204PDB3

35 IO204NDB3

36 VCC

37 IO199PDB3

38 IO199NDB3

39 IO197PSB3

40 VCCIB3

41 GND

42 IO191PDB3

43 IO191NDB3

44 GEC1/IO190PDB3

45 GEC0/IO190NDB3

46 GEB1/IO189PDB3

47 GEB0/IO189NDB3

48 GEA1/IO188PDB3

49 GEA0/IO188NDB3

50 VMV3

51 GNDQ

52 GND

53 VMV2

54 GEA2/IO187RSB2

55 GEB2/IO186RSB2

56 GEC2/IO185RSB2

57 IO184RSB2

58 IO183RSB2

59 IO182RSB2

60 IO181RSB2

61 IO180RSB2

62 VCCIB2

63 IO178RSB2

64 IO176RSB2

65 GND

66 IO174RSB2

67 IO172RSB2

68 IO170RSB2

69 IO168RSB2

70 IO166RSB2

71 VCC

72 VCCIB2

208-Pin PQFP*

Pin Number A3P1000 Function

73 IO162RSB2

74 IO160RSB2

75 IO158RSB2

76 IO156RSB2

77 IO154RSB2

78 IO152RSB2

79 IO150RSB2

80 IO148RSB2

81 GND

82 IO143RSB2

83 IO141RSB2

84 IO139RSB2

85 IO137RSB2

86 IO135RSB2

87 IO133RSB2

88 VCC

89 VCCIB2

90 IO128RSB2

91 IO126RSB2

92 IO124RSB2

93 IO122RSB2

94 IO120RSB2

95 IO118RSB2

96 GDC2/IO116RSB2

97 GND

98 GDB2/IO115RSB2

99 GDA2/IO114RSB2

100 GNDQ

101 TCK

102 TDI

103 TMS

104 VMV2

105 GND

106 VPUMP

107 GNDQ

108 TDO

208-Pin PQFP*

Pin Number A3P1000 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

4-30 v2.1

109 TRST

110 VJTAG

111 GDA0/IO113NDB1

112 GDA1/IO113PDB1

113 GDB0/IO112NDB1

114 GDB1/IO112PDB1

115 GDC0/IO111NDB1

116 GDC1/IO111PDB1

117 IO109NDB1

118 IO109PDB1

119 IO106NDB1

120 IO106PDB1

121 IO104PSB1

122 GND

123 VCCIB1

124 IO99NDB1

125 IO99PDB1

126 NC

127 IO96NDB1

128 GCC2/IO96PDB1

129 GCB2/IO95PSB1

130 GND

131 GCA2/IO94PSB1

132 GCA1/IO93PDB1

133 GCA0/IO93NDB1

134 GCB0/IO92NDB1

135 GCB1/IO92PDB1

136 GCC0/IO91NDB1

137 GCC1/IO91PDB1

138 IO88NDB1

139 IO88PDB1

140 VCCIB1

141 GND

142 VCC

208-Pin PQFP*

Pin Number A3P1000 Function

143 IO86PSB1

144 IO84NDB1

145 IO84PDB1

146 IO82NDB1

147 IO82PDB1

148 IO80NDB1

149 GBC2/IO80PDB1

150 IO79NDB1

151 GBB2/IO79PDB1

152 IO78NDB1

153 GBA2/IO78PDB1

154 VMV1

155 GNDQ

156 GND

157 VMV0

158 GBA1/IO77RSB0

159 GBA0/IO76RSB0

160 GBB1/IO75RSB0

161 GBB0/IO74RSB0

162 GND

163 GBC1/IO73RSB0

164 GBC0/IO72RSB0

165 IO70RSB0

166 IO67RSB0

167 IO63RSB0

168 IO60RSB0

169 IO57RSB0

170 VCCIB0

171 VCC

172 IO54RSB0

173 IO51RSB0

174 IO48RSB0

175 IO45RSB0

176 IO42RSB0

208-Pin PQFP*

Pin Number A3P1000 Function

177 IO40RSB0

178 GND

179 IO38RSB0

180 IO35RSB0

181 IO33RSB0

182 IO31RSB0

183 IO29RSB0

184 IO27RSB0

185 IO25RSB0

186 VCCIB0

187 VCC

188 IO22RSB0

189 IO20RSB0

190 IO18RSB0

191 IO16RSB0

192 IO15RSB0

193 IO14RSB0

194 IO13RSB0

195 GND

196 IO12RSB0

197 IO11RSB0

198 IO10RSB0

199 IO09RSB0

200 VCCIB0

201 GAC1/IO05RSB0

202 GAC0/IO04RSB0

203 GAB1/IO03RSB0

204 GAB0/IO02RSB0

205 GAA1/IO01RSB0

206 GAA0/IO00RSB0

207 GNDQ

208 VMV0

208-Pin PQFP*

Pin Number A3P1000 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

v2.1 4-31

144-Pin FBGA

Note

For Package Manufacturing and Environmental information, visit the Resource Center at

http://www.actel.com/products/solutions/package/docs.aspx.

Note: This is the bottom view of the package.

34567

101112

A1 Ball Pad Corner

ProASIC3 Flash Family FPGAs

4-32 v2.1

144-Pin FBGA*

Pin Number A3P060 Function

A1 GNDQ

A2 VMV0

A3 GAB0/IO04RSB0

A4 GAB1/IO05RSB0

A5 IO08RSB0

A6 GND

A7 IO11RSB0

A8 VCC

A9 IO16RSB0

A10 GBA0/IO23RSB0

A11 GBA1/IO24RSB0

A12 GNDQ

B1 GAB2/IO53RSB1

B2 GND

B3 GAA0/IO02RSB0

B4 GAA1/IO03RSB0

B5 IO00RSB0

B6 IO10RSB0

B7 IO12RSB0

B8 IO14RSB0

B9 GBB0/IO21RSB0

B10 GBB1/IO22RSB0

B11 GND

B12 VMV0

C1 IO95RSB1

C2 GFA2/IO83RSB1

C3 GAC2/IO94RSB1

C4 VCC

C5 IO01RSB0

C6 IO09RSB0

C7 IO13RSB0

C8 IO15RSB0

C9 IO17RSB0

C10 GBA2/IO25RSB0

C11 IO26RSB0

C12 GBC2/IO29RSB0

D1 IO91RSB1

D2 IO92RSB1

D3 IO93RSB1

D4 GAA2/IO51RSB1

D5 GAC0/IO06RSB0

D6 GAC1/IO07RSB0

D7 GBC0/IO19RSB0

D8 GBC1/IO20RSB0

D9 GBB2/IO27RSB0

D10 IO18RSB0

D11 IO28RSB0

D12 GCB1/IO37RSB0

E1 VCC

E2 GFC0/IO88RSB1

E3 GFC1/IO89RSB1

E4 VCCIB1

E5 IO52RSB1

E6 VCCIB0

E7 VCCIB0

E8 GCC1/IO35RSB0

E9 VCCIB0

E10 VCC

E11 GCA0/IO40RSB0

E12 IO30RSB0

F1 GFB0/IO86RSB1

F2 VCOMPLF

F3 GFB1/IO87RSB1

F4 IO90RSB1

F5 GND

F6 GND

F7 GND

F8 GCC0/IO36RSB0

F9 GCB0/IO38RSB0

F10 GND

F11 GCA1/IO39RSB0

F12 GCA2/IO41RSB0

144-Pin FBGA*

Pin Number A3P060 Function

G1 GFA1/IO84RSB1

G2 GND

G3 VCCPLF

G4 GFA0/IO85RSB1

G5 GND

G6 GND

G7 GND

G8 GDC1/IO45RSB0

G9 IO32RSB0

G10 GCC2/IO43RSB0

G11 IO31RSB0

G12 GCB2/IO42RSB0

H1 VCC

H2 GFB2/IO82RSB1

H3 GFC2/IO81RSB1

H4 GEC1/IO77RSB1

H5 VCC

H6 IO34RSB0

H7 IO44RSB0

H8 GDB2/IO55RSB1

H9 GDC0/IO46RSB0

H10 VCCIB0

H11 IO33RSB0

H12 VCC

J1 GEB1/IO75RSB1

J2 IO78RSB1

J3 VCCIB1

J4 GEC0/IO76RSB1

J5 IO79RSB1

J6 IO80RSB1

J7 VCC

J8 TCK

J9 GDA2/IO54RSB1

J10 TDO

J11 GDA1/IO49RSB0

J12 GDB1/IO47RSB0

144-Pin FBGA*

Pin Number A3P060 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

v2.1 4-33

K1 GEB0/IO74RSB1

K2 GEA1/IO73RSB1

K3 GEA0/IO72RSB1

K4 GEA2/IO71RSB1

K5 IO65RSB1

K6 IO64RSB1

K7 GND

K8 IO57RSB1

K9 GDC2/IO56RSB1

K10 GND

K11 GDA0/IO50RSB0

K12 GDB0/IO48RSB0

144-Pin FBGA*

Pin Number A3P060 Function

L1 GND

L2 VMV1

L3 GEB2/IO70RSB1

L4 IO67RSB1

L5 VCCIB1

L6 IO62RSB1

L7 IO59RSB1

L8 IO58RSB1

L9 TMS

L10 VJTAG

L11 VMV1

L12 TRST

144-Pin FBGA*

Pin Number A3P060 Function

M1 GNDQ

M2 GEC2/IO69RSB1

M3 IO68RSB1

M4 IO66RSB1

M5 IO63RSB1

M6 IO61RSB1

M7 IO60RSB1

M8 NC

M9 TDI

M10 VCCIB1

M11 VPUMP

M12 GNDQ

144-Pin FBGA*

Pin Number A3P060 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

4-34 v2.1

144-Pin FBGA*

Pin Number A3P125 Function

A1 GNDQ

A2 VMV0

A3 GAB0/IO02RSB0

A4 GAB1/IO03RSB0

A5 IO11RSB0

A6 GND

A7 IO18RSB0

A8 VCC

A9 IO25RSB0

A10 GBA0/IO39RSB0

A11 GBA1/IO40RSB0

A12 GNDQ

B1 GAB2/IO69RSB1

B2 GND

B3 GAA0/IO00RSB0

B4 GAA1/IO01RSB0

B5 IO08RSB0

B6 IO14RSB0

B7 IO19RSB0

B8 IO22RSB0

B9 GBB0/IO37RSB0

B10 GBB1/IO38RSB0

B11 GND

B12 VMV0

C1 IO132RSB1

C2 GFA2/IO120RSB1

C3 GAC2/IO131RSB1

C4 VCC

C5 IO10RSB0

C6 IO12RSB0

C7 IO21RSB0

C8 IO24RSB0

C9 IO27RSB0

C10 GBA2/IO41RSB0

C11 IO42RSB0

C12 GBC2/IO45RSB0

D1 IO128RSB1

D2 IO129RSB1

D3 IO130RSB1

D4 GAA2/IO67RSB1

D5 GAC0/IO04RSB0

D6 GAC1/IO05RSB0

D7 GBC0/IO35RSB0

D8 GBC1/IO36RSB0

D9 GBB2/IO43RSB0

D10 IO28RSB0

D11 IO44RSB0

D12 GCB1/IO53RSB0

E1 VCC

E2 GFC0/IO125RSB1

E3 GFC1/IO126RSB1

E4 VCCIB1

E5 IO68RSB1

E6 VCCIB0

E7 VCCIB0

E8 GCC1/IO51RSB0

E9 VCCIB0

E10 VCC

E11 GCA0/IO56RSB0

E12 IO46RSB0

F1 GFB0/IO123RSB1

F2 VCOMPLF

F3 GFB1/IO124RSB1

F4 IO127RSB1

F5 GND

F6 GND

F7 GND

F8 GCC0/IO52RSB0

F9 GCB0/IO54RSB0

F10 GND

F11 GCA1/IO55RSB0

F12 GCA2/IO57RSB0

144-Pin FBGA*

Pin Number A3P125 Function

G1 GFA1/IO121RSB1

G2 GND

G3 VCCPLF

G4 GFA0/IO122RSB1

G5 GND

G6 GND

G7 GND

G8 GDC1/IO61RSB0

G9 IO48RSB0

G10 GCC2/IO59RSB0

G11 IO47RSB0

G12 GCB2/IO58RSB0

H1 VCC

H2 GFB2/IO119RSB1

H3 GFC2/IO118RSB1

H4 GEC1/IO112RSB1

H5 VCC

H6 IO50RSB0

H7 IO60RSB0

H8 GDB2/IO71RSB1

H9 GDC0/IO62RSB0

H10 VCCIB0

H11 IO49RSB0

H12 VCC

J1 GEB1/IO110RSB1

J2 IO115RSB1

J3 VCCIB1

J4 GEC0/IO111RSB1

J5 IO116RSB1

J6 IO117RSB1

J7 VCC

J8 TCK

J9 GDA2/IO70RSB1

J10 TDO

J11 GDA1/IO65RSB0

J12 GDB1/IO63RSB0

144-Pin FBGA*

Pin Number A3P125 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

v2.1 4-35

K1 GEB0/IO109RSB1

K2 GEA1/IO108RSB1

K3 GEA0/IO107RSB1

K4 GEA2/IO106RSB1

K5 IO100RSB1

K6 IO98RSB1

K7 GND

K8 IO73RSB1

K9 GDC2/IO72RSB1

K10 GND

K11 GDA0/IO66RSB0

K12 GDB0/IO64RSB0

144-Pin FBGA*

Pin Number A3P125 Function

L1 GND

L2 VMV1

L3 GEB2/IO105RSB1

L4 IO102RSB1

L5 VCCIB1

L6 IO95RSB1

L7 IO85RSB1

L8 IO74RSB1

L9 TMS

L10 VJTAG

L11 VMV1

L12 TRST

144-Pin FBGA*

Pin Number A3P125 Function

M1 GNDQ

M2 GEC2/IO104RSB1

M3 IO103RSB1

M4 IO101RSB1

M5 IO97RSB1

M6 IO94RSB1

M7 IO86RSB1

M8 IO75RSB1

M9 TDI

M10 VCCIB1

M11 VPUMP

M12 GNDQ

144-Pin FBGA*

Pin Number A3P125 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

4-36 v2.1

144-Pin FBGA*

Pin Number A3P250 Function

A1 GNDQ

A2 VMV0

A3 GAB0/IO02RSB0

A4 GAB1/IO03RSB0

A5 IO16RSB0

A6 GND

A7 IO29RSB0

A8 VCC

A9 IO33RSB0

A10 GBA0/IO39RSB0

A11 GBA1/IO40RSB0

A12 GNDQ

B1 GAB2/IO117UDB3

B2 GND

B3 GAA0/IO00RSB0

B4 GAA1/IO01RSB0

B5 IO14RSB0

B6 IO19RSB0

B7 IO22RSB0

B8 IO30RSB0

B9 GBB0/IO37RSB0

B10 GBB1/IO38RSB0

B11 GND

B12 VMV1

C1 IO117VDB3

C2 GFA2/IO107PPB3

C3 GAC2/IO116UDB3

C4 VCC

C5 IO12RSB0

C6 IO17RSB0

C7 IO24RSB0

C8 IO31RSB0

C9 IO34RSB0

C10 GBA2/IO41PDB1

C11 IO41NDB1

C12 GBC2/IO43PPB1

D1 IO112NDB3

D2 IO112PDB3

D3 IO116VDB3

D4 GAA2/IO118UPB3

D5 GAC0/IO04RSB0

D6 GAC1/IO05RSB0

D7 GBC0/IO35RSB0

D8 GBC1/IO36RSB0

D9 GBB2/IO42PDB1

D10 IO42NDB1

D11 IO43NPB1

D12 GCB1/IO49PPB1

E1 VCC

E2 GFC0/IO110NDB3

E3 GFC1/IO110PDB3

E4 VCCIB3

E5 IO118VPB3

E6 VCCIB0

E7 VCCIB0

E8 GCC1/IO48PDB1

E9 VCCIB1

E10 VCC

E11 GCA0/IO50NDB1

E12 IO51NDB1

F1 GFB0/IO109NPB3

F2 VCOMPLF

F3 GFB1/IO109PPB3

F4 IO107NPB3

F5 GND

F6 GND

F7 GND

F8 GCC0/IO48NDB1

F9 GCB0/IO49NPB1

F10 GND

F11 GCA1/IO50PDB1

F12 GCA2/IO51PDB1

144-Pin FBGA*

Pin Number A3P250 Function

G1 GFA1/IO108PPB3

G2 GND

G3 VCCPLF

G4 GFA0/IO108NPB3

G5 GND

G6 GND

G7 GND

G8 GDC1/IO58UPB1

G9 IO53NDB1

G10 GCC2/IO53PDB1

G11 IO52NDB1

G12 GCB2/IO52PDB1

H1 VCC

H2 GFB2/IO106PDB3

H3 GFC2/IO105PSB3

H4 GEC1/IO100PDB3

H5 VCC

H6 IO79RSB2

H7 IO65RSB2

H8 GDB2/IO62RSB2

H9 GDC0/IO58VPB1

H10 VCCIB1

H11 IO54PSB1

H12 VCC

J1 GEB1/IO99PDB3

J2 IO106NDB3

J3 VCCIB3

J4 GEC0/IO100NDB3

J5 IO88RSB2

J6 IO81RSB2

J7 VCC

J8 TCK

J9 GDA2/IO61RSB2

J10 TDO

J11 GDA1/IO60UDB1

J12 GDB1/IO59UDB1

144-Pin FBGA*

Pin Number A3P250 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

v2.1 4-37

K1 GEB0/IO99NDB3

K2 GEA1/IO98PDB3

K3 GEA0/IO98NDB3

K4 GEA2/IO97RSB2

K5 IO90RSB2

K6 IO84RSB2

K7 GND

K8 IO66RSB2

K9 GDC2/IO63RSB2

K10 GND

K11 GDA0/IO60VDB1

K12 GDB0/IO59VDB1

144-Pin FBGA*

Pin Number A3P250 Function

L1 GND

L2 VMV3

L3 GEB2/IO96RSB2

L4 IO91RSB2

L5 VCCIB2

L6 IO82RSB2

L7 IO80RSB2

L8 IO72RSB2

L9 TMS

L10 VJTAG

L11 VMV2

L12 TRST

144-Pin FBGA*

Pin Number A3P250 Function

M1 GNDQ

M2 GEC2/IO95RSB2

M3 IO92RSB2

M4 IO89RSB2

M5 IO87RSB2

M6 IO85RSB2

M7 IO78RSB2

M8 IO76RSB2

M9 TDI

M10 VCCIB2

M11 VPUMP

M12 GNDQ

144-Pin FBGA*

Pin Number A3P250 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

4-38 v2.1

144-Pin FBGA*

Pin Number A3P400 Function

A1 GNDQ

A2 VMV0

A3 GAB0/IO02RSB0

A4 GAB1/IO03RSB0

A5 IO16RSB0

A6 GND

A7 IO30RSB0

A8 VCC

A9 IO34RSB0

A10 GBA0/IO58RSB0

A11 GBA1/IO59RSB0

A12 GNDQ

B1 GAB2/IO154UDB3

B2 GND

B3 GAA0/IO00RSB0

B4 GAA1/IO01RSB0

B5 IO14RSB0

B6 IO19RSB0

B7 IO23RSB0

B8 IO31RSB0

B9 GBB0/IO56RSB0

B10 GBB1/IO57RSB0

B11 GND

B12 VMV1

C1 IO154VDB3

C2 GFA2/IO144PPB3

C3 GAC2/IO153UDB3

C4 VCC

C5 IO12RSB0

C6 IO17RSB0

C7 IO25RSB0

C8 IO32RSB0

C9 IO53RSB0

C10 GBA2/IO60PDB1

C11 IO60NDB1

C12 GBC2/IO62PPB1

D1 IO149NDB3

D2 IO149PDB3

D3 IO153VDB3

D4 GAA2/IO155UPB3

D5 GAC0/IO04RSB0

D6 GAC1/IO05RSB0

D7 GBC0/IO54RSB0

D8 GBC1/IO55RSB0

D9 GBB2/IO61PDB1

D10 IO61NDB1

D11 IO62NPB1

D12 GCB1/IO68PPB1

E1 VCC

E2 GFC0/IO147NDB3

E3 GFC1/IO147PDB3

E4 VCCIB3

E5 IO155VPB3

E6 VCCIB0

E7 VCCIB0

E8 GCC1/IO67PDB1

E9 VCCIB1

E10 VCC

E11 GCA0/IO69NDB1

E12 IO70NDB1

F1 GFB0/IO146NPB3

F2 VCOMPLF

F3 GFB1/IO146PPB3

F4 IO144NPB3

F5 GND

F6 GND

F7 GND

F8 GCC0/IO67NDB1

F9 GCB0/IO68NPB1

F10 GND

F11 GCA1/IO69PDB1

F12 GCA2/IO70PDB1

144-Pin FBGA*

Pin Number A3P400 Function

G1 GFA1/IO145PPB3

G2 GND

G3 VCCPLF

G4 GFA0/IO145NPB3

G5 GND

G6 GND

G7 GND

G8 GDC1/IO77UPB1

G9 IO72NDB1

G10 GCC2/IO72PDB1

G11 IO71NDB1

G12 GCB2/IO71PDB1

H1 VCC

H2 GFB2/IO143PDB3

H3 GFC2/IO142PSB3

H4 GEC1/IO137PDB3

H5 VCC

H6 IO75PDB1

H7 IO75NDB1

H8 GDB2/IO81RSB2

H9 GDC0/IO77VPB1

H10 VCCIB1

H11 IO73PSB1

H12 VCC

J1 GEB1/IO136PDB3

J2 IO143NDB3

J3 VCCIB3

J4 GEC0/IO137NDB3

J5 IO125RSB2

J6 IO116RSB2

J7 VCC

J8 TCK

J9 GDA2/IO80RSB2

J10 TDO

J11 GDA1/IO79UDB1

J12 GDB1/IO78UDB1

144-Pin FBGA*

Pin Number A3P400 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

v2.1 4-39

K1 GEB0/IO136NDB3

K2 GEA1/IO135PDB3

K3 GEA0/IO135NDB3

K4 GEA2/IO134RSB2

K5 IO127RSB2

K6 IO121RSB2

K7 GND

K8 IO104RSB2

K9 GDC2/IO82RSB2

K10 GND

K11 GDA0/IO79VDB1

K12 GDB0/IO78VDB1

144-Pin FBGA*

Pin Number A3P400 Function

L1 GND

L2 VMV3

L3 GEB2/IO133RSB2

L4 IO128RSB2

L5 VCCIB2

L6 IO119RSB2

L7 IO114RSB2

L8 IO110RSB2

L9 TMS

L10 VJTAG

L11 VMV2

L12 TRST

144-Pin FBGA*

Pin Number A3P400 Function

M1 GNDQ

M2 GEC2/IO132RSB2

M3 IO129RSB2

M4 IO126RSB2

M5 IO124RSB2

M6 IO122RSB2

M7 IO117RSB2

M8 IO115RSB2

M9 TDI

M10 VCCIB2

M11 VPUMP

M12 GNDQ

144-Pin FBGA*

Pin Number A3P400 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

4-40 v2.1

144-Pin FBGA*

Pin Number A3P600 Function

A1 GNDQ

A2 VMV0

A3 GAB0/IO02RSB0

A4 GAB1/IO03RSB0

A5 IO10RSB0

A6 GND

A7 IO34RSB0

A8 VCC

A9 IO50RSB0

A10 GBA0/IO58RSB0

A11 GBA1/IO59RSB0

A12 GNDQ

B1 GAB2/IO173PDB3

B2 GND

B3 GAA0/IO00RSB0

B4 GAA1/IO01RSB0

B5 IO13RSB0

B6 IO19RSB0

B7 IO31RSB0

B8 IO39RSB0

B9 GBB0/IO56RSB0

B10 GBB1/IO57RSB0

B11 GND

B12 VMV1

C1 IO173NDB3

C2 GFA2/IO161PPB3

C3 GAC2/IO172PDB3

C4 VCC

C5 IO16RSB0

C6 IO25RSB0

C7 IO28RSB0

C8 IO42RSB0

C9 IO45RSB0

C10 GBA2/IO60PDB1

C11 IO60NDB1

C12 GBC2/IO62PPB1

D1 IO169PDB3

D2 IO169NDB3

D3 IO172NDB3

D4 GAA2/IO174PPB3

D5 GAC0/IO04RSB0

D6 GAC1/IO05RSB0

D7 GBC0/IO54RSB0

D8 GBC1/IO55RSB0

D9 GBB2/IO61PDB1

D10 IO61NDB1

D11 IO62NPB1

D12 GCB1/IO70PPB1

E1 VCC

E2 GFC0/IO164NDB3

E3 GFC1/IO164PDB3

E4 VCCIB3

E5 IO174NPB3

E6 VCCIB0

E7 VCCIB0

E8 GCC1/IO69PDB1

E9 VCCIB1

E10 VCC

E11 GCA0/IO71NDB1

E12 IO72NDB1

F1 GFB0/IO163NPB3

F2 VCOMPLF

F3 GFB1/IO163PPB3

F4 IO161NPB3

F5 GND

F6 GND

F7 GND

F8 GCC0/IO69NDB1

F9 GCB0/IO70NPB1

F10 GND

F11 GCA1/IO71PDB1

F12 GCA2/IO72PDB1

144-Pin FBGA*

Pin Number A3P600 Function

G1 GFA1/IO162PPB3

G2 GND

G3 VCCPLF

G4 GFA0/IO162NPB3

G5 GND

G6 GND

G7 GND

G8 GDC1/IO86PPB1

G9 IO74NDB1

G10 GCC2/IO74PDB1

G11 IO73NDB1

G12 GCB2/IO73PDB1

H1 VCC

H2 GFB2/IO160PDB3

H3 GFC2/IO159PSB3

H4 GEC1/IO146PDB3

H5 VCC

H6 IO80PDB1

H7 IO80NDB1

H8 GDB2/IO90RSB2

H9 GDC0/IO86NPB1

H10 VCCIB1

H11 IO84PSB1

H12 VCC

J1 GEB1/IO145PDB3

J2 IO160NDB3

J3 VCCIB3

J4 GEC0/IO146NDB3

J5 IO129RSB2

J6 IO131RSB2

J7 VCC

J8 TCK

J9 GDA2/IO89RSB2

J10 TDO

J11 GDA1/IO88PDB1

J12 GDB1/IO87PDB1

144-Pin FBGA*

Pin Number A3P600 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

v2.1 4-41

K1 GEB0/IO145NDB3

K2 GEA1/IO144PDB3

K3 GEA0/IO144NDB3

K4 GEA2/IO143RSB2

K5 IO119RSB2

K6 IO111RSB2

K7 GND

K8 IO94RSB2

K9 GDC2/IO91RSB2

K10 GND

K11 GDA0/IO88NDB1

K12 GDB0/IO87NDB1

144-Pin FBGA*

Pin Number A3P600 Function

L1 GND

L2 VMV3

L3 GEB2/IO142RSB2

L4 IO136RSB2

L5 VCCIB2

L6 IO115RSB2

L7 IO103RSB2

L8 IO97RSB2

L9 TMS

L10 VJTAG

L11 VMV2

L12 TRST

144-Pin FBGA*

Pin Number A3P600 Function

M1 GNDQ

M2 GEC2/IO141RSB2

M3 IO138RSB2

M4 IO123RSB2

M5 IO126RSB2

M6 IO134RSB2

M7 IO108RSB2

M8 IO99RSB2

M9 TDI

M10 VCCIB2

M11 VPUMP

M12 GNDQ

144-Pin FBGA*

Pin Number A3P600 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

4-42 v2.1

144-Pin FBGA*

Pin Number A3P1000 Function

A1 GNDQ

A2 VMV0

A3 GAB0/IO02RSB0

A4 GAB1/IO03RSB0

A5 IO10RSB0

A6 GND

A7 IO44RSB0

A8 VCC

A9 IO69RSB0

A10 GBA0/IO76RSB0

A11 GBA1/IO77RSB0

A12 GNDQ

B1 GAB2/IO224PDB3

B2 GND

B3 GAA0/IO00RSB0

B4 GAA1/IO01RSB0

B5 IO13RSB0

B6 IO26RSB0

B7 IO35RSB0

B8 IO60RSB0

B9 GBB0/IO74RSB0

B10 GBB1/IO75RSB0

B11 GND

B12 VMV1

C1 IO224NDB3

C2 GFA2/IO206PPB3

C3 GAC2/IO223PDB3

C4 VCC

C5 IO16RSB0

C6 IO29RSB0

C7 IO32RSB0

C8 IO63RSB0

C9 IO66RSB0

C10 GBA2/IO78PDB1

C11 IO78NDB1

C12 GBC2/IO80PPB1

D1 IO213PDB3

D2 IO213NDB3

D3 IO223NDB3

D4 GAA2/IO225PPB3

D5 GAC0/IO04RSB0

D6 GAC1/IO05RSB0

D7 GBC0/IO72RSB0

D8 GBC1/IO73RSB0

D9 GBB2/IO79PDB1

D10 IO79NDB1

D11 IO80NPB1

D12 GCB1/IO92PPB1

E1 VCC

E2 GFC0/IO209NDB3

E3 GFC1/IO209PDB3

E4 VCCIB3

E5 IO225NPB3

E6 VCCIB0

E7 VCCIB0

E8 GCC1/IO91PDB1

E9 VCCIB1

E10 VCC

E11 GCA0/IO93NDB1

E12 IO94NDB1

F1 GFB0/IO208NPB3

F2 VCOMPLF

F3 GFB1/IO208PPB3

F4 IO206NPB3

F5 GND

F6 GND

F7 GND

F8 GCC0/IO91NDB1

F9 GCB0/IO92NPB1

F10 GND

F11 GCA1/IO93PDB1

F12 GCA2/IO94PDB1

144-Pin FBGA*

Pin Number A3P1000 Function

G1 GFA1/IO207PPB3

G2 GND

G3 VCCPLF

G4 GFA0/IO207NPB3

G5 GND

G6 GND

G7 GND

G8 GDC1/IO111PPB1

G9 IO96NDB1

G10 GCC2/IO96PDB1

G11 IO95NDB1

G12 GCB2/IO95PDB1

H1 VCC

H2 GFB2/IO205PDB3

H3 GFC2/IO204PSB3

H4 GEC1/IO190PDB3

H5 VCC

H6 IO105PDB1

H7 IO105NDB1

H8 GDB2/IO115RSB2

H9 GDC0/IO111NPB1

H10 VCCIB1

H11 IO101PSB1

H12 VCC

J1 GEB1/IO189PDB3

J2 IO205NDB3

J3 VCCIB3

J4 GEC0/IO190NDB3

J5 IO160RSB2

J6 IO157RSB2

J7 VCC

J8 TCK

J9 GDA2/IO114RSB2

J10 TDO

J11 GDA1/IO113PDB1

J12 GDB1/IO112PDB1

144-Pin FBGA*

Pin Number A3P1000 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

v2.1 4-43

K1 GEB0/IO189NDB3

K2 GEA1/IO188PDB3

K3 GEA0/IO188NDB3

K4 GEA2/IO187RSB2

K5 IO169RSB2

K6 IO152RSB2

K7 GND

K8 IO117RSB2

K9 GDC2/IO116RSB2

K10 GND

K11 GDA0/IO113NDB1

K12 GDB0/IO112NDB1

144-Pin FBGA*

Pin Number A3P1000 Function

L1 GND

L2 VMV3

L3 GEB2/IO186RSB2

L4 IO172RSB2

L5 VCCIB2

L6 IO153RSB2

L7 IO144RSB2

L8 IO140RSB2

L9 TMS

L10 VJTAG

L11 VMV2

L12 TRST

144-Pin FBGA*

Pin Number A3P1000 Function

M1 GNDQ

M2 GEC2/IO185RSB2

M3 IO173RSB2

M4 IO168RSB2

M5 IO161RSB2

M6 IO156RSB2

M7 IO145RSB2

M8 IO141RSB2

M9 TDI

M10 VCCIB2

M11 VPUMP

M12 GNDQ

144-Pin FBGA*

Pin Number A3P1000 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

4-44 v2.1

256-Pin FBGA

Note

For Package Manufacturing and Environmental information, visit the Resource Center at

http://www.actel.com/products/solutions/package/docs.aspx.

Note: This is the bottom view of the package.

791113

15 246

101214

A1 Ball Pad Corner

ProASIC3 Flash Family FPGAs

v2.1 4-45

256-Pin FBGA*

Pin Number A3P250 Function

A1 GND

A2 GAA0/IO00RSB0

A3 GAA1/IO01RSB0

A4 GAB0/IO02RSB0

A5 IO07RSB0

A6 IO10RSB0

A7 IO11RSB0

A8 IO15RSB0

A9 IO20RSB0

A10 IO25RSB0

A11 IO29RSB0

A12 IO33RSB0

A13 GBB1/IO38RSB0

A14 GBA0/IO39RSB0

A15 GBA1/IO40RSB0

A16 GND

B1 GAB2/IO117UDB3

B2 GAA2/IO118UDB3

B3 NC

B4 GAB1/IO03RSB0

B5 IO06RSB0

B6 IO09RSB0

B7 IO12RSB0

B8 IO16RSB0

B9 IO21RSB0

B10 IO26RSB0

B11 IO30RSB0

B12 GBC1/IO36RSB0

B13 GBB0/IO37RSB0

B14 NC

B15 GBA2/IO41PDB1

B16 IO41NDB1

C1 IO117VDB3

C2 IO118VDB3

C3 NC

C4 NC

C5 GAC0/IO04RSB0

C6 GAC1/IO05RSB0

C7 IO13RSB0

C8 IO17RSB0

C9 IO22RSB0

C10 IO27RSB0

C11 IO31RSB0

C12 GBC0/IO35RSB0

C13 IO34RSB0

C14 NC

C15 IO42NPB1

C16 IO44PDB1

D1 IO114VDB3

D2 IO114UDB3

D3 GAC2/IO116UDB3

D4 NC

D5 GNDQ

D6 IO08RSB0

D7 IO14RSB0

D8 IO18RSB0

D9 IO23RSB0

D10 IO28RSB0

D11 IO32RSB0

D12 GNDQ

D13 NC

D14 GBB2/IO42PPB1

D15 NC

D16 IO44NDB1

E1 IO113PDB3

E2 NC

E3 IO116VDB3

E4 IO115UDB3

E5 VMV0

E6 VCCIB0

E7 VCCIB0

E8 IO19RSB0

256-Pin FBGA*

Pin Number A3P250 Function

E9 IO24RSB0

E10 VCCIB0

E11 VCCIB0

E12 VMV1

E13 GBC2/IO43PDB1

E14 IO46RSB1

E15 NC

E16 IO45PDB1

F1 IO113NDB3

F2 IO112PPB3

F3 NC

F4 IO115VDB3

F5 VCCIB3

F6 GND

F7 VCC

F8 VCC

F9 VCC

F10 VCC

F11 GND

F12 VCCIB1

F13 IO43NDB1

F14 NC

F15 IO47PPB1

F16 IO45NDB1

G1 IO111NDB3

G2 IO111PDB3

G3 IO112NPB3

G4 GFC1/IO110PPB3

G5 VCCIB3

G6 VCC

G7 GND

G8 GND

G9 GND

G10 GND

G11 VCC

G12 VCCIB1

256-Pin FBGA*

Pin Number A3P250 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

4-46 v2.1

G13 GCC1/IO48PPB1

G14 IO47NPB1

G15 IO54PDB1

G16 IO54NDB1

H1 GFB0/IO109NPB3

H2 GFA0/IO108NDB3

H3 GFB1/IO109PPB3

H4 VCOMPLF

H5 GFC0/IO110NPB3

H6 VCC

H7 GND

H8 GND

H9 GND

H10 GND

H11 VCC

H12 GCC0/IO48NPB1

H13 GCB1/IO49PPB1

H14 GCA0/IO50NPB1

H15 NC

H16 GCB0/IO49NPB1

J1 GFA2/IO107PPB3

J2 GFA1/IO108PDB3

J3 VCCPLF

J4 IO106NDB3

J5 GFB2/IO106PDB3

J6 VCC

J7 GND

J8 GND

J9 GND

J10 GND

J11 VCC

J12 GCB2/IO52PPB1

J13 GCA1/IO50PPB1

J14 GCC2/IO53PPB1

J15 NC

J16 GCA2/IO51PDB1

256-Pin FBGA*

Pin Number A3P250 Function

K1 GFC2/IO105PDB3

K2 IO107NPB3

K3 IO104PPB3

K4 NC

K5 VCCIB3

K6 VCC

K7 GND

K8 GND

K9 GND

K10 GND

K11 VCC

K12 VCCIB1

K13 IO52NPB1

K14 IO55RSB1

K15 IO53NPB1

K16 IO51NDB1

L1 IO105NDB3

L2 IO104NPB3

L3 NC

L4 IO102RSB3

L5 VCCIB3

L6 GND

L7 VCC

L8 VCC

L9 VCC

L10 VCC

L11 GND

L12 VCCIB1

L13 GDB0/IO59VPB1

L14 IO57VDB1

L15 IO57UDB1

L16 IO56PDB1

M1 IO103PDB3

M2 NC

M3 IO101NPB3

M4 GEC0/IO100NPB3

256-Pin FBGA*

Pin Number A3P250 Function

M5 VMV3

M6 VCCIB2

M7 VCCIB2

M8 NC

M9 IO74RSB2

M10 VCCIB2

M11 VCCIB2

M12 VMV2

M13 NC

M14 GDB1/IO59UPB1

M15 GDC1/IO58UDB1

M16 IO56NDB1

N1 IO103NDB3

N2 IO101PPB3

N3 GEC1/IO100PPB3

N4 NC

N5 GNDQ

N6 GEA2/IO97RSB2

N7 IO86RSB2

N8 IO82RSB2

N9 IO75RSB2

N10 IO69RSB2

N11 IO64RSB2

N12 GNDQ

N13 NC

N14 VJTAG

N15 GDC0/IO58VDB1

N16 GDA1/IO60UDB1

P1 GEB1/IO99PDB3

P2 GEB0/IO99NDB3

P3 NC

P4 NC

P5 IO92RSB2

P6 IO89RSB2

P7 IO85RSB2

P8 IO81RSB2

256-Pin FBGA*

Pin Number A3P250 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

v2.1 4-47

P9 IO76RSB2

P10 IO71RSB2

P11 IO66RSB2

P12 NC

P13 TCK

P14 VPUMP

P15 TRST

P16 GDA0/IO60VDB1

R1 GEA1/IO98PDB3

R2 GEA0/IO98NDB3

R3 NC

R4 GEC2/IO95RSB2

R5 IO91RSB2

R6 IO88RSB2

256-Pin FBGA*

Pin Number A3P250 Function

R7 IO84RSB2

R8 IO80RSB2

R9 IO77RSB2

R10 IO72RSB2

R11 IO68RSB2

R12 IO65RSB2

R13 GDB2/IO62RSB2

R14 TDI

R15 NC

R16 TDO

T1 GND

T2 IO94RSB2

T3 GEB2/IO96RSB2

T4 IO93RSB2

256-Pin FBGA*

Pin Number A3P250 Function

T5 IO90RSB2

T6 IO87RSB2

T7 IO83RSB2

T8 IO79RSB2

T9 IO78RSB2

T10 IO73RSB2

T11 IO70RSB2

T12 GDC2/IO63RSB2

T13 IO67RSB2

T14 GDA2/IO61RSB2

T15 TMS

T16 GND

256-Pin FBGA*

Pin Number A3P250 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

4-48 v2.1

256-Pin FBGA

Pin Number A3P400 Function

A1 GND

A2 GAA0/IO00RSB0

A3 GAA1/IO01RSB0

A4 GAB0/IO02RSB0

A5 IO16RSB0

A6 IO17RSB0

A7 IO22RSB0

A8 IO28RSB0

A9 IO34RSB0

A10 IO37RSB0

A11 IO41RSB0

A12 IO43RSB0

A13 GBB1/IO57RSB0

A14 GBA0/IO58RSB0

A15 GBA1/IO59RSB0

A16 GND

B1 GAB2/IO154UDB3

B2 GAA2/IO155UDB3

B3 IO12RSB0

B4 GAB1/IO03RSB0

B5 IO13RSB0

B6 IO14RSB0

B7 IO21RSB0

B8 IO27RSB0

B9 IO32RSB0

B10 IO38RSB0

B11 IO42RSB0

B12 GBC1/IO55RSB0

B13 GBB0/IO56RSB0

B14 IO44RSB0

B15 GBA2/IO60PDB1

B16 IO60NDB1

C1 IO154VDB3

C2 IO155VDB3

C3 IO11RSB0

C4 IO07RSB0

C5 GAC0/IO04RSB0

C6 GAC1/IO05RSB0

C7 IO20RSB0

C8 IO24RSB0

C9 IO33RSB0

C10 IO39RSB0

C11 IO45RSB0

C12 GBC0/IO54RSB0

C13 IO48RSB0

C14 VMV0

C15 IO61NPB1

C16 IO63PDB1

D1 IO151VDB3

D2 IO151UDB3

D3 GAC2/IO153UDB3

D4 IO06RSB0

D5 GNDQ

D6 IO10RSB0

D7 IO19RSB0

D8 IO26RSB0

D9 IO30RSB0

D10 IO40RSB0

D11 IO46RSB0

D12 GNDQ

D13 IO47RSB0

D14 GBB2/IO61PPB1

D15 IO53RSB0

D16 IO63NDB1

E1 IO150PDB3

E2 IO08RSB0

E3 IO153VDB3

E4 IO152VDB3

E5 VMV0

E6 VCCIB0

E7 VCCIB0

E8 IO25RSB0

256-Pin FBGA

Pin Number A3P400 Function

E9 IO31RSB0

E10 VCCIB0

E11 VCCIB0

E12 VMV1

E13 GBC2/IO62PDB1

E14 IO65RSB1

E15 IO52RSB0

E16 IO66PDB1

F1 IO150NDB3

F2 IO149NPB3

F3 IO09RSB0

F4 IO152UDB3

F5 VCCIB3

F6 GND

F7 VCC

F8 VCC

F9 VCC

F10 VCC

F11 GND

F12 VCCIB1

F13 IO62NDB1

F14 IO49RSB0

F15 IO64PPB1

F16 IO66NDB1

G1 IO148NDB3

G2 IO148PDB3

G3 IO149PPB3

G4 GFC1/IO147PPB3

G5 VCCIB3

G6 VCC

G7 GND

G8 GND

G9 GND

G10 GND

G11 VCC

G12 VCCIB1

256-Pin FBGA

Pin Number A3P400 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

v2.1 4-49

G13 GCC1/IO67PPB1

G14 IO64NPB1

G15 IO73PDB1

G16 IO73NDB1

H1 GFB0/IO146NPB3

H2 GFA0/IO145NDB3

H3 GFB1/IO146PPB3

H4 VCOMPLF

H5 GFC0/IO147NPB3

H6 VCC

H7 GND

H8 GND

H9 GND

H10 GND

H11 VCC

H12 GCC0/IO67NPB1

H13 GCB1/IO68PPB1

H14 GCA0/IO69NPB1

H15 NC

H16 GCB0/IO68NPB1

J1 GFA2/IO144PPB3

J2 GFA1/IO145PDB3

J3 VCCPLF

J4 IO143NDB3

J5 GFB2/IO143PDB3

J6 VCC

J7 GND

J8 GND

J9 GND

J10 GND

J11 VCC

J12 GCB2/IO71PPB1

J13 GCA1/IO69PPB1

J14 GCC2/IO72PPB1

J15 NC

J16 GCA2/IO70PDB1

256-Pin FBGA

Pin Number A3P400 Function

K1 GFC2/IO142PDB3

K2 IO144NPB3

K3 IO141PPB3

K4 IO120RSB2

K5 VCCIB3

K6 VCC

K7 GND

K8 GND

K9 GND

K10 GND

K11 VCC

K12 VCCIB1

K13 IO71NPB1

K14 IO74RSB1

K15 IO72NPB1

K16 IO70NDB1

L1 IO142NDB3

L2 IO141NPB3

L3 IO125RSB2

L4 IO139RSB3

L5 VCCIB3

L6 GND

L7 VCC

L8 VCC

L9 VCC

L10 VCC

L11 GND

L12 VCCIB1

L13 GDB0/IO78VPB1

L14 IO76VDB1

L15 IO76UDB1

L16 IO75PDB1

M1 IO140PDB3

M2 IO130RSB2

M3 IO138NPB3

M4 GEC0/IO137NPB3

256-Pin FBGA

Pin Number A3P400 Function

M5 VMV3

M6 VCCIB2

M7 VCCIB2

M8 IO108RSB2

M9 IO101RSB2

M10 VCCIB2

M11 VCCIB2

M12 VMV2

M13 IO83RSB2

M14 GDB1/IO78UPB1

M15 GDC1/IO77UDB1

M16 IO75NDB1

N1 IO140NDB3

N2 IO138PPB3

N3 GEC1/IO137PPB3

N4 IO131RSB2

N5 GNDQ

N6 GEA2/IO134RSB2

N7 IO117RSB2

N8 IO111RSB2

N9 IO99RSB2

N10 IO94RSB2

N11 IO87RSB2

N12 GNDQ

N13 IO93RSB2

N14 VJTAG

N15 GDC0/IO77VDB1

N16 GDA1/IO79UDB1

P1 GEB1/IO136PDB3

P2 GEB0/IO136NDB3

P3 VMV2

P4 IO129RSB2

P5 IO128RSB2

P6 IO122RSB2

P7 IO115RSB2

P8 IO110RSB2

256-Pin FBGA

Pin Number A3P400 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

4-50 v2.1

P9 IO98RSB2

P10 IO95RSB2

P11 IO88RSB2

P12 IO84RSB2

P13 TCK

P14 VPUMP

P15 TRST

P16 GDA0/IO79VDB1

R1 GEA1/IO135PDB3

R2 GEA0/IO135NDB3

R3 IO127RSB2

R4 GEC2/IO132RSB2

R5 IO123RSB2

R6 IO118RSB2

256-Pin FBGA

Pin Number A3P400 Function

R7 IO112RSB2

R8 IO106RSB2

R9 IO100RSB2

R10 IO96RSB2

R11 IO89RSB2

R12 IO85RSB2

R13 GDB2/IO81RSB2

R14 TDI

R15 NC

R16 TDO

T1 GND

T2 IO126RSB2

T3 GEB2/IO133RSB2

T4 IO124RSB2

256-Pin FBGA

Pin Number A3P400 Function

T5 IO116RSB2

T6 IO113RSB2

T7 IO107RSB2

T8 IO105RSB2

T9 IO102RSB2

T10 IO97RSB2

T11 IO92RSB2

T12 GDC2/IO82RSB2

T13 IO86RSB2

T14 GDA2/IO80RSB2

T15 TMS

T16 GND

256-Pin FBGA

Pin Number A3P400 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

v2.1 4-51

256-Pin FBGA*

Pin Number A3P600 Function

A1 GND

A2 GAA0/IO00RSB0

A3 GAA1/IO01RSB0

A4 GAB0/IO02RSB0

A5 IO11RSB0

A6 IO16RSB0

A7 IO18RSB0

A8 IO28RSB0

A9 IO34RSB0

A10 IO37RSB0

A11 IO41RSB0

A12 IO43RSB0

A13 GBB1/IO57RSB0

A14 GBA0/IO58RSB0

A15 GBA1/IO59RSB0

A16 GND

B1 GAB2/IO173PDB3

B2 GAA2/IO174PDB3

B3 GNDQ

B4 GAB1/IO03RSB0

B5 IO13RSB0

B6 IO14RSB0

B7 IO21RSB0

B8 IO27RSB0

B9 IO32RSB0

B10 IO38RSB0

B11 IO42RSB0

B12 GBC1/IO55RSB0

B13 GBB0/IO56RSB0

B14 IO52RSB0

B15 GBA2/IO60PDB1

B16 IO60NDB1

C1 IO173NDB3

C2 IO174NDB3

C3 VMV3

C4 IO07RSB0

C5 GAC0/IO04RSB0

C6 GAC1/IO05RSB0

C7 IO20RSB0

C8 IO24RSB0

C9 IO33RSB0

C10 IO39RSB0

C11 IO44RSB0

C12 GBC0/IO54RSB0

C13 IO51RSB0

C14 VMV0

C15 IO61NPB1

C16 IO63PDB1

D1 IO171NDB3

D2 IO171PDB3

D3 GAC2/IO172PDB3

D4 IO06RSB0

D5 GNDQ

D6 IO10RSB0

D7 IO19RSB0

D8 IO26RSB0

D9 IO30RSB0

D10 IO40RSB0

D11 IO45RSB0

D12 GNDQ

D13 IO50RSB0

D14 GBB2/IO61PPB1

D15 IO53RSB0

D16 IO63NDB1

E1 IO166PDB3

E2 IO167NPB3

E3 IO172NDB3

E4 IO169NDB3

E5 VMV0

E6 VCCIB0

E7 VCCIB0

E8 IO25RSB0

256-Pin FBGA*

Pin Number A3P600 Function

E9 IO31RSB0

E10 VCCIB0

E11 VCCIB0

E12 VMV1

E13 GBC2/IO62PDB1

E14 IO67PPB1

E15 IO64PPB1

E16 IO66PDB1

F1 IO166NDB3

F2 IO168NPB3

F3 IO167PPB3

F4 IO169PDB3

F5 VCCIB3

F6 GND

F7 VCC

F8 VCC

F9 VCC

F10 VCC

F11 GND

F12 VCCIB1

F13 IO62NDB1

F14 IO64NPB1

F15 IO65PPB1

F16 IO66NDB1

G1 IO165NDB3

G2 IO165PDB3

G3 IO168PPB3

G4 GFC1/IO164PPB3

G5 VCCIB3

G6 VCC

G7 GND

G8 GND

G9 GND

G10 GND

G11 VCC

G12 VCCIB1

256-Pin FBGA*

Pin Number A3P600 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

4-52 v2.1

G13 GCC1/IO69PPB1

G14 IO65NPB1

G15 IO75PDB1

G16 IO75NDB1

H1 GFB0/IO163NPB3

H2 GFA0/IO162NDB3

H3 GFB1/IO163PPB3

H4 VCOMPLF

H5 GFC0/IO164NPB3

H6 VCC

H7 GND

H8 GND

H9 GND

H10 GND

H11 VCC

H12 GCC0/IO69NPB1

H13 GCB1/IO70PPB1

H14 GCA0/IO71NPB1

H15 IO67NPB1

H16 GCB0/IO70NPB1

J1 GFA2/IO161PPB3

J2 GFA1/IO162PDB3

J3 VCCPLF

J4 IO160NDB3

J5 GFB2/IO160PDB3

J6 VCC

J7 GND

J8 GND

J9 GND

J10 GND

J11 VCC

J12 GCB2/IO73PPB1

J13 GCA1/IO71PPB1

J14 GCC2/IO74PPB1

J15 IO80PPB1

J16 GCA2/IO72PDB1

256-Pin FBGA*

Pin Number A3P600 Function

K1 GFC2/IO159PDB3

K2 IO161NPB3

K3 IO156PPB3

K4 IO129RSB2

K5 VCCIB3

K6 VCC

K7 GND

K8 GND

K9 GND

K10 GND

K11 VCC

K12 VCCIB1

K13 IO73NPB1

K14 IO80NPB1

K15 IO74NPB1

K16 IO72NDB1

L1 IO159NDB3

L2 IO156NPB3

L3 IO151PPB3

L4 IO158PSB3

L5 VCCIB3

L6 GND

L7 VCC

L8 VCC

L9 VCC

L10 VCC

L11 GND

L12 VCCIB1

L13 GDB0/IO87NPB1

L14 IO85NDB1

L15 IO85PDB1

L16 IO84PDB1

M1 IO150PDB3

M2 IO151NPB3

M3 IO147NPB3

M4 GEC0/IO146NPB3

256-Pin FBGA*

Pin Number A3P600 Function

M5 VMV3

M6 VCCIB2

M7 VCCIB2

M8 IO117RSB2

M9 IO110RSB2

M10 VCCIB2

M11 VCCIB2

M12 VMV2

M13 IO94RSB2

M14 GDB1/IO87PPB1

M15 GDC1/IO86PDB1

M16 IO84NDB1

N1 IO150NDB3

N2 IO147PPB3

N3 GEC1/IO146PPB3

N4 IO140RSB2

N5 GNDQ

N6 GEA2/IO143RSB2

N7 IO126RSB2

N8 IO120RSB2

N9 IO108RSB2

N10 IO103RSB2

N11 IO99RSB2

N12 GNDQ

N13 IO92RSB2

N14 VJTAG

N15 GDC0/IO86NDB1

N16 GDA1/IO88PDB1

P1 GEB1/IO145PDB3

P2 GEB0/IO145NDB3

P3 VMV2

P4 IO138RSB2

P5 IO136RSB2

P6 IO131RSB2

P7 IO124RSB2

P8 IO119RSB2

256-Pin FBGA*

Pin Number A3P600 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

v2.1 4-53

P9 IO107RSB2

P10 IO104RSB2

P11 IO97RSB2

P12 VMV1

P13 TCK

P14 VPUMP

P15 TRST

P16 GDA0/IO88NDB1

R1 GEA1/IO144PDB3

R2 GEA0/IO144NDB3

R3 IO139RSB2

R4 GEC2/IO141RSB2

R5 IO132RSB2

R6 IO127RSB2

256-Pin FBGA*

Pin Number A3P600 Function

R7 IO121RSB2

R8 IO114RSB2

R9 IO109RSB2

R10 IO105RSB2

R11 IO98RSB2

R12 IO96RSB2

R13 GDB2/IO90RSB2

R14 TDI

R15 GNDQ

R16 TDO

T1 GND

T2 IO137RSB2

T3 GEB2/IO142RSB2

T4 IO134RSB2

256-Pin FBGA*

Pin Number A3P600 Function

T5 IO125RSB2

T6 IO123RSB2

T7 IO118RSB2

T8 IO115RSB2

T9 IO111RSB2

T10 IO106RSB2

T11 IO102RSB2

T12 GDC2/IO91RSB2

T13 IO93RSB2

T14 GDA2/IO89RSB2

T15 TMS

T16 GND

256-Pin FBGA*

Pin Number A3P600 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

4-54 v2.1

256-Pin FBGA*

Pin Number A3P1000 Function

A1 GND

A2 GAA0/IO00RSB0

A3 GAA1/IO01RSB0

A4 GAB0/IO02RSB0

A5 IO16RSB0

A6 IO22RSB0

A7 IO28RSB0

A8 IO35RSB0

A9 IO45RSB0

A10 IO50RSB0

A11 IO55RSB0

A12 IO61RSB0

A13 GBB1/IO75RSB0

A14 GBA0/IO76RSB0

A15 GBA1/IO77RSB0

A16 GND

B1 GAB2/IO224PDB3

B2 GAA2/IO225PDB3

B3 GNDQ

B4 GAB1/IO03RSB0

B5 IO17RSB0

B6 IO21RSB0

B7 IO27RSB0

B8 IO34RSB0

B9 IO44RSB0

B10 IO51RSB0

B11 IO57RSB0

B12 GBC1/IO73RSB0

B13 GBB0/IO74RSB0

B14 IO71RSB0

B15 GBA2/IO78PDB1

B16 IO81PDB1

C1 IO224NDB3

C2 IO225NDB3

C3 VMV3

C4 IO11RSB0

C5 GAC0/IO04RSB0

C6 GAC1/IO05RSB0

C7 IO25RSB0

C8 IO36RSB0

C9 IO42RSB0

C10 IO49RSB0

C11 IO56RSB0

C12 GBC0/IO72RSB0

C13 IO62RSB0

C14 VMV0

C15 IO78NDB1

C16 IO81NDB1

D1 IO222NDB3

D2 IO222PDB3

D3 GAC2/IO223PDB3

D4 IO223NDB3

D5 GNDQ

D6 IO23RSB0

D7 IO29RSB0

D8 IO33RSB0

D9 IO46RSB0

D10 IO52RSB0

D11 IO60RSB0

D12 GNDQ

D13 IO80NDB1

D14 GBB2/IO79PDB1

D15 IO79NDB1

D16 IO82NSB1

E1 IO217PDB3

E2 IO218PDB3

E3 IO221NDB3

E4 IO221PDB3

E5 VMV0

E6 VCCIB0

E7 VCCIB0

E8 IO38RSB0

E9 IO47RSB0

E10 VCCIB0

E11 VCCIB0

E12 VMV1

256-Pin FBGA*

Pin Number A3P1000 Function

E13 GBC2/IO80PDB1

E14 IO83PPB1

E15 IO86PPB1

E16 IO87PDB1

F1 IO217NDB3

F2 IO218NDB3

F3 IO216PDB3

F4 IO216NDB3

F5 VCCIB3

F6 GND

F7 VCC

F8 VCC

F9 VCC

F10 VCC

F11 GND

F12 VCCIB1

F13 IO83NPB1

F14 IO86NPB1

F15 IO90PPB1

F16 IO87NDB1

G1 IO210PSB3

G2 IO213NDB3

G3 IO213PDB3

G4 GFC1/IO209PPB3

G5 VCCIB3

G6 VCC

G7 GND

G8 GND

G9 GND

G10 GND

G11 VCC

G12 VCCIB1

G13 GCC1/IO91PPB1

G14 IO90NPB1

G15 IO88PDB1

G16 IO88NDB1

H1 GFB0/IO208NPB3

H2 GFA0/IO207NDB3

256-Pin FBGA*

Pin Number A3P1000 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

v2.1 4-55

H3 GFB1/IO208PPB3

H4 VCOMPLF

H5 GFC0/IO209NPB3

H6 VCC

H7 GND

H8 GND

H9 GND

H10 GND

H11 VCC

H12 GCC0/IO91NPB1

H13 GCB1/IO92PPB1

H14 GCA0/IO93NPB1

H15 IO96NPB1

H16 GCB0/IO92NPB1

J1 GFA2/IO206PSB3

J2 GFA1/IO207PDB3

J3 VCCPLF

J4 IO205NDB3

J5 GFB2/IO205PDB3

J6 VCC

J7 GND

J8 GND

J9 GND

J10 GND

J11 VCC

J12 GCB2/IO95PPB1

J13 GCA1/IO93PPB1

J14 GCC2/IO96PPB1

J15 IO100PPB1

J16 GCA2/IO94PSB1

K1 GFC2/IO204PDB3

K2 IO204NDB3

K3 IO203NDB3

K4 IO203PDB3

K5 VCCIB3

K6 VCC

K7 GND

K8 GND

256-Pin FBGA*

Pin Number A3P1000 Function

K9 GND

K10 GND

K11 VCC

K12 VCCIB1

K13 IO95NPB1

K14 IO100NPB1

K15 IO102NDB1

K16 IO102PDB1

L1 IO202NDB3

L2 IO202PDB3

L3 IO196PPB3

L4 IO193PPB3

L5 VCCIB3

L6 GND

L7 VCC

L8 VCC

L9 VCC

L10 VCC

L11 GND

L12 VCCIB1

L13 GDB0/IO112NPB1

L14 IO106NDB1

L15 IO106PDB1

L16 IO107PDB1

M1 IO197NSB3

M2 IO196NPB3

M3 IO193NPB3

M4 GEC0/IO190NPB3

M5 VMV3

M6 VCCIB2

M7 VCCIB2

M8 IO147RSB2

M9 IO136RSB2

M10 VCCIB2

M11 VCCIB2

M12 VMV2

M13 IO110NDB1

M14 GDB1/IO112PPB1

256-Pin FBGA*

Pin Number A3P1000 Function

M15 GDC1/IO111PDB1

M16 IO107NDB1

N1 IO194PSB3

N2 IO192PPB3

N3 GEC1/IO190PPB3

N4 IO192NPB3

N5 GNDQ

N6 GEA2/IO187RSB2

N7 IO161RSB2

N8 IO155RSB2

N9 IO141RSB2

N10 IO129RSB2

N11 IO124RSB2

N12 GNDQ

N13 IO110PDB1

N14 VJTAG

N15 GDC0/IO111NDB1

N16 GDA1/IO113PDB1

P1 GEB1/IO189PDB3

P2 GEB0/IO189NDB3

P3 VMV2

P4 IO179RSB2

P5 IO171RSB2

P6 IO165RSB2

P7 IO159RSB2

P8 IO151RSB2

P9 IO137RSB2

P10 IO134RSB2

P11 IO128RSB2

P12 VMV1

P13 TCK

P14 VPUMP

P15 TRST

P16 GDA0/IO113NDB1

R1 GEA1/IO188PDB3

R2 GEA0/IO188NDB3

R3 IO184RSB2

R4 GEC2/IO185RSB2

256-Pin FBGA*

Pin Number A3P1000 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

4-56 v2.1

R5 IO168RSB2

R6 IO163RSB2

R7 IO157RSB2

R8 IO149RSB2

R9 IO143RSB2

R10 IO138RSB2

R11 IO131RSB2

R12 IO125RSB2

R13 GDB2/IO115RSB2

R14 TDI

256-Pin FBGA*

Pin Number A3P1000 Function

R15 GNDQ

R16 TDO

T1 GND

T2 IO183RSB2

T3 GEB2/IO186RSB2

T4 IO172RSB2

T5 IO170RSB2

T6 IO164RSB2

T7 IO158RSB2

T8 IO153RSB2

256-Pin FBGA*

Pin Number A3P1000 Function

T9 IO142RSB2

T10 IO135RSB2

T11 IO130RSB2

T12 GDC2/IO116RSB2

T13 IO120RSB2

T14 GDA2/IO114RSB2

T15 TMS

T16 GND

256-Pin FBGA*

Pin Number A3P1000 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

v2.1 4-57

484-Pin FBGA

Note

For Package Manufacturing and Environmental information, visit the Resource Center at

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Note: This is the bottom view of the package.

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A1 Ball Pad Corner

ProASIC3 Flash Family FPGAs

4-58 v2.1

484-Pin FBGA*

Pin Number A3P400 Function

A1 GND

A2 GND

A3 VCCIB0

A4 NC

A5 NC

A6 IO15RSB0

A7 IO18RSB0

A8 NC

A9 NC

A10 IO23RSB0

A11 IO29RSB0

A12 IO35RSB0

A13 IO36RSB0

A14 NC

A15 NC

A16 IO50RSB0

A17 IO51RSB0

A18 NC

A19 NC

A20 VCCIB0

A21 GND

A22 GND

B1 GND

B2 VCCIB3

B3 NC

B4 NC

B5 NC

B6 NC

B7 NC

B8 NC

B9 NC

B10 NC

B11 NC

B12 NC

B13 NC

B14 NC

B15 NC

B16 NC

B17 NC

B18 NC

B19 NC

B20 NC

B21 VCCIB1

B22 GND

C1 VCCIB3

C2 NC

C3 NC

C4 NC

C5 GND

C6 NC

C7 NC

C8 VCC

C9 VCC

C10 NC

C11 NC

C12 NC

C13 NC

C14 VCC

C15 VCC

C16 NC

C17 NC

C18 GND

C19 NC

C20 NC

C21 NC

C22 VCCIB1

D1 NC

D2 NC

D3 NC

D4 GND

D5 GAA0/IO00RSB0

D6 GAA1/IO01RSB0

484-Pin FBGA*

Pin Number A3P400 Function

D7 GAB0/IO02RSB0

D8 IO16RSB0

D9 IO17RSB0

D10 IO22RSB0

D11 IO28RSB0

D12 IO34RSB0

D13 IO37RSB0

D14 IO41RSB0

D15 IO43RSB0

D16 GBB1/IO57RSB0

D17 GBA0/IO58RSB0

D18 GBA1/IO59RSB0

D19 GND

D20 NC

D21 NC

D22 NC

E1 NC

E2 NC

E3 GND

E4 GAB2/IO154UDB3

E5 GAA2/IO155UDB3

E6 IO12RSB0

E7 GAB1/IO03RSB0

E8 IO13RSB0

E9 IO14RSB0

E10 IO21RSB0

E11 IO27RSB0

E12 IO32RSB0

E13 IO38RSB0

E14 IO42RSB0

E15 GBC1/IO55RSB0

E16 GBB0/IO56RSB0

E17 IO44RSB0

E18 GBA2/IO60PDB1

E19 IO60NDB1

E20 GND

484-Pin FBGA*

Pin Number A3P400 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

v2.1 4-59

E21 NC

E22 NC

F1 NC

F2 NC

F3 NC

F4 IO154VDB3

F5 IO155VDB3

F6 IO11RSB0

F7 IO07RSB0

F8 GAC0/IO04RSB0

F9 GAC1/IO05RSB0

F10 IO20RSB0

F11 IO24RSB0

F12 IO33RSB0

F13 IO39RSB0

F14 IO45RSB0

F15 GBC0/IO54RSB0

F16 IO48RSB0

F17 VMV0

F18 IO61NPB1

F19 IO63PDB1

F20 NC

F21 NC

F22 NC

G1 NC

G2 NC

G3 NC

G4 IO151VDB3

G5 IO151UDB3

G6 GAC2/IO153UDB3

G7 IO06RSB0

G8 GNDQ

G9 IO10RSB0

G10 IO19RSB0

G11 IO26RSB0

G12 IO30RSB0

484-Pin FBGA*

Pin Number A3P400 Function

G13 IO40RSB0

G14 IO46RSB0

G15 GNDQ

G16 IO47RSB0

G17 GBB2/IO61PPB1

G18 IO53RSB0

G19 IO63NDB1

G20 NC

G21 NC

G22 NC

H1 NC

H2 NC

H3 VCC

H4 IO150PDB3

H5 IO08RSB0

H6 IO153VDB3

H7 IO152VDB3

H8 VMV0

H9 VCCIB0

H10 VCCIB0

H11 IO25RSB0

H12 IO31RSB0

H13 VCCIB0

H14 VCCIB0

H15 VMV1

H16 GBC2/IO62PDB1

H17 IO65RSB1

H18 IO52RSB0

H19 IO66PDB1

H20 VCC

H21 NC

H22 NC

J1 NC

J2 NC

J3 NC

J4 IO150NDB3

484-Pin FBGA*

Pin Number A3P400 Function

J5 IO149NPB3

J6 IO09RSB0

J7 IO152UDB3

J8 VCCIB3

J9 GND

J10 VCC

J11 VCC

J12 VCC

J13 VCC

J14 GND

J15 VCCIB1

J16 IO62NDB1

J17 IO49RSB0

J18 IO64PPB1

J19 IO66NDB1

J20 NC

J21 NC

J22 NC

K1 NC

K2 NC

K3 NC

K4 IO148NDB3

K5 IO148PDB3

K6 IO149PPB3

K7 GFC1/IO147PPB3

K8 VCCIB3

K9 VCC

K10 GND

K11 GND

K12 GND

K13 GND

K14 VCC

K15 VCCIB1

K16 GCC1/IO67PPB1

K17 IO64NPB1

K18 IO73PDB1

484-Pin FBGA*

Pin Number A3P400 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

4-60 v2.1

K19 IO73NDB1

K20 NC

K21 NC

K22 NC

L1 NC

L2 NC

L3 NC

L4 GFB0/IO146NPB3

L5 GFA0/IO145NDB3

L6 GFB1/IO146PPB3

L7 VCOMPLF

L8 GFC0/IO147NPB3

L9 VCC

L10 GND

L11 GND

L12 GND

L13 GND

L14 VCC

L15 GCC0/IO67NPB1

L16 GCB1/IO68PPB1

L17 GCA0/IO69NPB1

L18 NC

L19 GCB0/IO68NPB1

L20 NC

L21 NC

L22 NC

M1 NC

M2 NC

M3 NC

M4 GFA2/IO144PPB3

M5 GFA1/IO145PDB3

M6 VCCPLF

M7 IO143NDB3

M8 GFB2/IO143PDB3

M9 VCC

M10 GND

484-Pin FBGA*

Pin Number A3P400 Function

M11 GND

M12 GND

M13 GND

M14 VCC

M15 GCB2/IO71PPB1

M16 GCA1/IO69PPB1

M17 GCC2/IO72PPB1

M18 NC

M19 GCA2/IO70PDB1

M20 NC

M21 NC

M22 NC

N1 NC

N2 NC

N3 NC

N4 GFC2/IO142PDB3

N5 IO144NPB3

N6 IO141PPB3

N7 IO120RSB2

N8 VCCIB3

N9 VCC

N10 GND

N11 GND

N12 GND

N13 GND

N14 VCC

N15 VCCIB1

N16 IO71NPB1

N17 IO74RSB1

N18 IO72NPB1

N19 IO70NDB1

N20 NC

N21 NC

N22 NC

P1 NC

P2 NC

484-Pin FBGA*

Pin Number A3P400 Function

P3 NC

P4 IO142NDB3

P5 IO141NPB3

P6 IO125RSB2

P7 IO139RSB3

P8 VCCIB3

P9 GND

P10 VCC

P11 VCC

P12 VCC

P13 VCC

P14 GND

P15 VCCIB1

P16 GDB0/IO78VPB1

P17 IO76VDB1

P18 IO76UDB1

P19 IO75PDB1

P20 NC

P21 NC

P22 NC

R1 NC

R2 NC

R3 VCC

R4 IO140PDB3

R5 IO130RSB2

R6 IO138NPB3

R7 GEC0/IO137NPB3

R8 VMV3

R9 VCCIB2

R10 VCCIB2

R11 IO108RSB2

R12 IO101RSB2

R13 VCCIB2

R14 VCCIB2

R15 VMV2

R16 IO83RSB2

484-Pin FBGA*

Pin Number A3P400 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

v2.1 4-61

R17 GDB1/IO78UPB1

R18 GDC1/IO77UDB1

R19 IO75NDB1

R20 VCC

R21 NC

R22 NC

T1 NC

T2 NC

T3 NC

T4 IO140NDB3

T5 IO138PPB3

T6 GEC1/IO137PPB3

T7 IO131RSB2

T8 GNDQ

T9 GEA2/IO134RSB2

T10 IO117RSB2

T11 IO111RSB2

T12 IO99RSB2

T13 IO94RSB2

T14 IO87RSB2

T15 GNDQ

T16 IO93RSB2

T17 VJTAG

T18 GDC0/IO77VDB1

T19 GDA1/IO79UDB1

T20 NC

T21 NC

T22 NC

U1 NC

U2 NC

U3 NC

U4 GEB1/IO136PDB3

U5 GEB0/IO136NDB3

U6 VMV2

U7 IO129RSB2

U8 IO128RSB2

484-Pin FBGA*

Pin Number A3P400 Function

U9 IO122RSB2

U10 IO115RSB2

U11 IO110RSB2

U12 IO98RSB2

U13 IO95RSB2

U14 IO88RSB2

U15 IO84RSB2

U16 TCK

U17 VPUMP

U18 TRST

U19 GDA0/IO79VDB1

U20 NC

U21 NC

U22 NC

V1 NC

V2 NC

V3 GND

V4 GEA1/IO135PDB3

V5 GEA0/IO135NDB3

V6 IO127RSB2

V7 GEC2/IO132RSB2

V8 IO123RSB2

V9 IO118RSB2

V10 IO112RSB2

V11 IO106RSB2

V12 IO100RSB2

V13 IO96RSB2

V14 IO89RSB2

V15 IO85RSB2

V16 GDB2/IO81RSB2

V17 TDI

V18 NC

V19 TDO

V20 GND

V21 NC

V22 NC

484-Pin FBGA*

Pin Number A3P400 Function

W1 NC

W2 NC

W3 NC

W4 GND

W5 IO126RSB2

W6 GEB2/IO133RSB2

W7 IO124RSB2

W8 IO116RSB2

W9 IO113RSB2

W10 IO107RSB2

W11 IO105RSB2

W12 IO102RSB2

W13 IO97RSB2

W14 IO92RSB2

W15 GDC2/IO82RSB2

W16 IO86RSB2

W17 GDA2/IO80RSB2

W18 TMS

W19 GND

W20 NC

W21 NC

W22 NC

Y1 VCCIB3

Y2 NC

Y3 NC

Y4 NC

Y5 GND

Y6 NC

Y7 NC

Y8 VCC

Y9 VCC

Y10 NC

Y11 NC

Y12 NC

Y13 NC

Y14 VCC

484-Pin FBGA*

Pin Number A3P400 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

4-62 v2.1

Y15 VCC

Y16 NC

Y17 NC

Y18 GND

Y19 NC

Y20 NC

Y21 NC

Y22 VCCIB1

AA1 GND

AA2 VCCIB3

AA3 NC

AA4 NC

AA5 NC

AA6 NC

AA7 NC

AA8 NC

AA9 NC

AA10 NC

484-Pin FBGA*

Pin Number A3P400 Function

AA11 NC

AA12 NC

AA13 NC

AA14 NC

AA15 NC

AA16 NC

AA17 NC

AA18 NC

AA19 NC

AA20 NC

AA21 VCCIB1

AA22 GND

AB1 GND

AB2 GND

AB3 VCCIB2

AB4 NC

AB5 NC

AB6 IO121RSB2

484-Pin FBGA*

Pin Number A3P400 Function

AB7 IO119RSB2

AB8 IO114RSB2

AB9 IO109RSB2

AB10 NC

AB11 NC

AB12 IO104RSB2

AB13 IO103RSB2

AB14 NC

AB15 NC

AB16 IO91RSB2

AB17 IO90RSB2

AB18 NC

AB19 NC

AB20 VCCIB2

AB21 GND

AB22 GND

484-Pin FBGA*

Pin Number A3P400 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

v2.1 4-63

484-Pin FBGA*

Pin Number A3P600 Function

A1 GND

A2 GND

A3 VCCIB0

A4 NC

A5 NC

A6 IO09RSB0

A7 IO15RSB0

A8 NC

A9 NC

A10 IO22RSB0

A11 IO23RSB0

A12 IO29RSB0

A13 IO35RSB0

A14 NC

A15 NC

A16 IO46RSB0

A17 IO48RSB0

A18 NC

A19 NC

A20 VCCIB0

A21 GND

A22 GND

B1 GND

B2 VCCIB3

B3 NC

B4 NC

B5 NC

B6 IO08RSB0

B7 IO12RSB0

B8 NC

B9 NC

B10 IO17RSB0

B11 NC

B12 NC

B13 IO36RSB0

B14 NC

B15 NC

B16 IO47RSB0

B17 IO49RSB0

B18 NC

B19 NC

B20 NC

B21 VCCIB1

B22 GND

C1 VCCIB3

C2 NC

C3 NC

C4 NC

C5 GND

C6 NC

C7 NC

C8 VCC

C9 VCC

C10 NC

C11 NC

C12 NC

C13 NC

C14 VCC

C15 VCC

C16 NC

C17 NC

C18 GND

C19 NC

C20 NC

C21 NC

C22 VCCIB1

D1 NC

D2 NC

D3 NC

D4 GND

D5 GAA0/IO00RSB0

D6 GAA1/IO01RSB0

484-Pin FBGA*

Pin Number A3P600 Function

D7 GAB0/IO02RSB0

D8 IO11RSB0

D9 IO16RSB0

D10 IO18RSB0

D11 IO28RSB0

D12 IO34RSB0

D13 IO37RSB0

D14 IO41RSB0

D15 IO43RSB0

D16 GBB1/IO57RSB0

D17 GBA0/IO58RSB0

D18 GBA1/IO59RSB0

D19 GND

D20 NC

D21 NC

D22 NC

E1 NC

E2 NC

E3 GND

E4 GAB2/IO173PDB3

E5 GAA2/IO174PDB3

E6 GNDQ

E7 GAB1/IO03RSB0

E8 IO13RSB0

E9 IO14RSB0

E10 IO21RSB0

E11 IO27RSB0

E12 IO32RSB0

E13 IO38RSB0

E14 IO42RSB0

E15 GBC1/IO55RSB0

E16 GBB0/IO56RSB0

E17 IO52RSB0

E18 GBA2/IO60PDB1

E19 IO60NDB1

E20 GND

484-Pin FBGA*

Pin Number A3P600 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

4-64 v2.1

E21 NC

E22 NC

F1 NC

F2 NC

F3 NC

F4 IO173NDB3

F5 IO174NDB3

F6 VMV3

F7 IO07RSB0

F8 GAC0/IO04RSB0

F9 GAC1/IO05RSB0

F10 IO20RSB0

F11 IO24RSB0

F12 IO33RSB0

F13 IO39RSB0

F14 IO44RSB0

F15 GBC0/IO54RSB0

F16 IO51RSB0

F17 VMV0

F18 IO61NPB1

F19 IO63PDB1

F20 NC

F21 NC

F22 NC

G1 IO170NDB3

G2 IO170PDB3

G3 NC

G4 IO171NDB3

G5 IO171PDB3

G6 GAC2/IO172PDB3

G7 IO06RSB0

G8 GNDQ

G9 IO10RSB0

G10 IO19RSB0

G11 IO26RSB0

G12 IO30RSB0

484-Pin FBGA*

Pin Number A3P600 Function

G13 IO40RSB0

G14 IO45RSB0

G15 GNDQ

G16 IO50RSB0

G17 GBB2/IO61PPB1

G18 IO53RSB0

G19 IO63NDB1

G20 NC

G21 NC

G22 NC

H1 NC

H2 NC

H3 VCC

H4 IO166PDB3

H5 IO167NPB3

H6 IO172NDB3

H7 IO169NDB3

H8 VMV0

H9 VCCIB0

H10 VCCIB0

H11 IO25RSB0

H12 IO31RSB0

H13 VCCIB0

H14 VCCIB0

H15 VMV1

H16 GBC2/IO62PDB1

H17 IO67PPB1

H18 IO64PPB1

H19 IO66PDB1

H20 VCC

H21 NC

H22 NC

J1 NC

J2 NC

J3 NC

J4 IO166NDB3

484-Pin FBGA*

Pin Number A3P600 Function

J5 IO168NPB3

J6 IO167PPB3

J7 IO169PDB3

J8 VCCIB3

J9 GND

J10 VCC

J11 VCC

J12 VCC

J13 VCC

J14 GND

J15 VCCIB1

J16 IO62NDB1

J17 IO64NPB1

J18 IO65PPB1

J19 IO66NDB1

J20 NC

J21 IO68PDB1

J22 IO68NDB1

K1 IO157PDB3

K2 IO157NDB3

K3 NC

K4 IO165NDB3

K5 IO165PDB3

K6 IO168PPB3

K7 GFC1/IO164PPB3

K8 VCCIB3

K9 VCC

K10 GND

K11 GND

K12 GND

K13 GND

K14 VCC

K15 VCCIB1

K16 GCC1/IO69PPB1

K17 IO65NPB1

K18 IO75PDB1

484-Pin FBGA*

Pin Number A3P600 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

v2.1 4-65

K19 IO75NDB1

K20 NC

K21 IO76NDB1

K22 IO76PDB1

L1 NC

L2 IO155PDB3

L3 NC

L4 GFB0/IO163NPB3

L5 GFA0/IO162NDB3

L6 GFB1/IO163PPB3

L7 VCOMPLF

L8 GFC0/IO164NPB3

L9 VCC

L10 GND

L11 GND

L12 GND

L13 GND

L14 VCC

L15 GCC0/IO69NPB1

L16 GCB1/IO70PPB1

L17 GCA0/IO71NPB1

L18 IO67NPB1

L19 GCB0/IO70NPB1

L20 IO77PDB1

L21 IO77NDB1

L22 IO78NPB1

M1 NC

M2 IO155NDB3

M3 IO158NPB3

M4 GFA2/IO161PPB3

M5 GFA1/IO162PDB3

M6 VCCPLF

M7 IO160NDB3

M8 GFB2/IO160PDB3

M9 VCC

M10 GND

484-Pin FBGA*

Pin Number A3P600 Function

M11 GND

M12 GND

M13 GND

M14 VCC

M15 GCB2/IO73PPB1

M16 GCA1/IO71PPB1

M17 GCC2/IO74PPB1

M18 IO80PPB1

M19 GCA2/IO72PDB1

M20 IO79PPB1

M21 IO78PPB1

M22 NC

N1 IO154NDB3

N2 IO154PDB3

N3 NC

N4 GFC2/IO159PDB3

N5 IO161NPB3

N6 IO156PPB3

N7 IO129RSB2

N8 VCCIB3

N9 VCC

N10 GND

N11 GND

N12 GND

N13 GND

N14 VCC

N15 VCCIB1

N16 IO73NPB1

N17 IO80NPB1

N18 IO74NPB1

N19 IO72NDB1

N20 NC

N21 IO79NPB1

N22 NC

P1 NC

P2 IO153PDB3

484-Pin FBGA*

Pin Number A3P600 Function

P3 IO153NDB3

P4 IO159NDB3

P5 IO156NPB3

P6 IO151PPB3

P7 IO158PPB3

P8 VCCIB3

P9 GND

P10 VCC

P11 VCC

P12 VCC

P13 VCC

P14 GND

P15 VCCIB1

P16 GDB0/IO87NPB1

P17 IO85NDB1

P18 IO85PDB1

P19 IO84PDB1

P20 NC

P21 IO81PDB1

P22 NC

R1 NC

R2 NC

R3 VCC

R4 IO150PDB3

R5 IO151NPB3

R6 IO147NPB3

R7 GEC0/IO146NPB3

R8 VMV3

R9 VCCIB2

R10 VCCIB2

R11 IO117RSB2

R12 IO110RSB2

R13 VCCIB2

R14 VCCIB2

R15 VMV2

R16 IO94RSB2

484-Pin FBGA*

Pin Number A3P600 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

4-66 v2.1

R17 GDB1/IO87PPB1

R18 GDC1/IO86PDB1

R19 IO84NDB1

R20 VCC

R21 IO81NDB1

R22 IO82PDB1

T1 IO152PDB3

T2 IO152NDB3

T3 NC

T4 IO150NDB3

T5 IO147PPB3

T6 GEC1/IO146PPB3

T7 IO140RSB2

T8 GNDQ

T9 GEA2/IO143RSB2

T10 IO126RSB2

T11 IO120RSB2

T12 IO108RSB2

T13 IO103RSB2

T14 IO99RSB2

T15 GNDQ

T16 IO92RSB2

T17 VJTAG

T18 GDC0/IO86NDB1

T19 GDA1/IO88PDB1

T20 NC

T21 IO83PDB1

T22 IO82NDB1

U1 IO149PDB3

U2 IO149NDB3

U3 NC

U4 GEB1/IO145PDB3

U5 GEB0/IO145NDB3

U6 VMV2

U7 IO138RSB2

U8 IO136RSB2

484-Pin FBGA*

Pin Number A3P600 Function

U9 IO131RSB2

U10 IO124RSB2

U11 IO119RSB2

U12 IO107RSB2

U13 IO104RSB2

U14 IO97RSB2

U15 VMV1

U16 TCK

U17 VPUMP

U18 TRST

U19 GDA0/IO88NDB1

U20 NC

U21 IO83NDB1

U22 NC

V1 NC

V2 NC

V3 GND

V4 GEA1/IO144PDB3

V5 GEA0/IO144NDB3

V6 IO139RSB2

V7 GEC2/IO141RSB2

V8 IO132RSB2

V9 IO127RSB2

V10 IO121RSB2

V11 IO114RSB2

V12 IO109RSB2

V13 IO105RSB2

V14 IO98RSB2

V15 IO96RSB2

V16 GDB2/IO90RSB2

V17 TDI

V18 GNDQ

V19 TDO

V20 GND

V21 NC

V22 NC

484-Pin FBGA*

Pin Number A3P600 Function

W1 NC

W2 IO148PDB3

W3 NC

W4 GND

W5 IO137RSB2

W6 GEB2/IO142RSB2

W7 IO134RSB2

W8 IO125RSB2

W9 IO123RSB2

W10 IO118RSB2

W11 IO115RSB2

W12 IO111RSB2

W13 IO106RSB2

W14 IO102RSB2

W15 GDC2/IO91RSB2

W16 IO93RSB2

W17 GDA2/IO89RSB2

W18 TMS

W19 GND

W20 NC

W21 NC

W22 NC

Y1 VCCIB3

Y2 IO148NDB3

Y3 NC

Y4 NC

Y5 GND

Y6 NC

Y7 NC

Y8 VCC

Y9 VCC

Y10 NC

Y11 NC

Y12 NC

Y13 NC

Y14 VCC

484-Pin FBGA*

Pin Number A3P600 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

v2.1 4-67

Y15 VCC

Y16 NC

Y17 NC

Y18 GND

Y19 NC

Y20 NC

Y21 NC

Y22 VCCIB1

AA1 GND

AA2 VCCIB3

AA3 NC

AA4 NC

AA5 NC

AA6 IO135RSB2

AA7 IO133RSB2

AA8 NC

AA9 NC

AA10 NC

484-Pin FBGA*

Pin Number A3P600 Function

AA11 NC

AA12 NC

AA13 NC

AA14 NC

AA15 NC

AA16 IO101RSB2

AA17 NC

AA18 NC

AA19 NC

AA20 NC

AA21 VCCIB1

AA22 GND

AB1 GND

AB2 GND

AB3 VCCIB2

AB4 NC

AB5 NC

AB6 IO130RSB2

484-Pin FBGA*

Pin Number A3P600 Function

AB7 IO128RSB2

AB8 IO122RSB2

AB9 IO116RSB2

AB10 NC

AB11 NC

AB12 IO113RSB2

AB13 IO112RSB2

AB14 NC

AB15 NC

AB16 IO100RSB2

AB17 IO95RSB2

AB18 NC

AB19 NC

AB20 VCCIB2

AB21 GND

AB22 GND

484-Pin FBGA*

Pin Number A3P600 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

4-68 v2.1

484-Pin FBGA*

Pin Number A3P1000 Function

A1 GND

A2 GND

A3 VCCIB0

A4 IO07RSB0

A5 IO09RSB0

A6 IO13RSB0

A7 IO18RSB0

A8 IO20RSB0

A9 IO26RSB0

A10 IO32RSB0

A11 IO40RSB0

A12 IO41RSB0

A13 IO53RSB0

A14 IO59RSB0

A15 IO64RSB0

A16 IO65RSB0

A17 IO67RSB0

A18 IO69RSB0

A19 NC

A20 VCCIB0

A21 GND

A22 GND

B1 GND

B2 VCCIB3

B3 NC

B4 IO06RSB0

B5 IO08RSB0

B6 IO12RSB0

B7 IO15RSB0

B8 IO19RSB0

B9 IO24RSB0

B10 IO31RSB0

B11 IO39RSB0

B12 IO48RSB0

B13 IO54RSB0

B14 IO58RSB0

B15 IO63RSB0

B16 IO66RSB0

B17 IO68RSB0

B18 IO70RSB0

B19 NC

B20 NC

B21 VCCIB1

B22 GND

C1 VCCIB3

C2 IO220PDB3

C3 NC

C4 NC

C5 GND

C6 IO10RSB0

C7 IO14RSB0

C8 VCC

C9 VCC

C10 IO30RSB0

C11 IO37RSB0

C12 IO43RSB0

C13 NC

C14 VCC

C15 VCC

C16 NC

C17 NC

C18 GND

C19 NC

C20 NC

C21 NC

C22 VCCIB1

D1 IO219PDB3

D2 IO220NDB3

D3 NC

D4 GND

D5 GAA0/IO00RSB0

D6 GAA1/IO01RSB0

484-Pin FBGA*

Pin Number A3P1000 Function

D7 GAB0/IO02RSB0

D8 IO16RSB0

D9 IO22RSB0

D10 IO28RSB0

D11 IO35RSB0

D12 IO45RSB0

D13 IO50RSB0

D14 IO55RSB0

D15 IO61RSB0

D16 GBB1/IO75RSB0

D17 GBA0/IO76RSB0

D18 GBA1/IO77RSB0

D19 GND

D20 NC

D21 NC

D22 NC

E1 IO219NDB3

E2 NC

E3 GND

E4 GAB2/IO224PDB3

E5 GAA2/IO225PDB3

E6 GNDQ

E7 GAB1/IO03RSB0

E8 IO17RSB0

E9 IO21RSB0

E10 IO27RSB0

E11 IO34RSB0

E12 IO44RSB0

E13 IO51RSB0

E14 IO57RSB0

E15 GBC1/IO73RSB0

E16 GBB0/IO74RSB0

E17 IO71RSB0

E18 GBA2/IO78PDB1

E19 IO81PDB1

E20 GND

484-Pin FBGA*

Pin Number A3P1000 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

v2.1 4-69

E21 NC

E22 IO84PDB1

F1 NC

F2 IO215PDB3

F3 IO215NDB3

F4 IO224NDB3

F5 IO225NDB3

F6 VMV3

F7 IO11RSB0

F8 GAC0/IO04RSB0

F9 GAC1/IO05RSB0

F10 IO25RSB0

F11 IO36RSB0

F12 IO42RSB0

F13 IO49RSB0

F14 IO56RSB0

F15 GBC0/IO72RSB0

F16 IO62RSB0

F17 VMV0

F18 IO78NDB1

F19 IO81NDB1

F20 IO82PPB1

F21 NC

F22 IO84NDB1

G1 IO214NDB3

G2 IO214PDB3

G3 NC

G4 IO222NDB3

G5 IO222PDB3

G6 GAC2/IO223PDB3

G7 IO223NDB3

G8 GNDQ

G9 IO23RSB0

G10 IO29RSB0

G11 IO33RSB0

G12 IO46RSB0

484-Pin FBGA*

Pin Number A3P1000 Function

G13 IO52RSB0

G14 IO60RSB0

G15 GNDQ

G16 IO80NDB1

G17 GBB2/IO79PDB1

G18 IO79NDB1

G19 IO82NPB1

G20 IO85PDB1

G21 IO85NDB1

G22 NC

H1 NC

H2 NC

H3 VCC

H4 IO217PDB3

H5 IO218PDB3

H6 IO221NDB3

H7 IO221PDB3

H8 VMV0

H9 VCCIB0

H10 VCCIB0

H11 IO38RSB0

H12 IO47RSB0

H13 VCCIB0

H14 VCCIB0

H15 VMV1

H16 GBC2/IO80PDB1

H17 IO83PPB1

H18 IO86PPB1

H19 IO87PDB1

H20 VCC

H21 NC

H22 NC

J1 IO212NDB3

J2 IO212PDB3

J3 NC

J4 IO217NDB3

484-Pin FBGA*

Pin Number A3P1000 Function

J5 IO218NDB3

J6 IO216PDB3

J7 IO216NDB3

J8 VCCIB3

J9 GND

J10 VCC

J11 VCC

J12 VCC

J13 VCC

J14 GND

J15 VCCIB1

J16 IO83NPB1

J17 IO86NPB1

J18 IO90PPB1

J19 IO87NDB1

J20 NC

J21 IO89PDB1

J22 IO89NDB1

K1 IO211PDB3

K2 IO211NDB3

K3 NC

K4 IO210PPB3

K5 IO213NDB3

K6 IO213PDB3

K7 GFC1/IO209PPB3

K8 VCCIB3

K9 VCC

K10 GND

K11 GND

K12 GND

K13 GND

K14 VCC

K15 VCCIB1

K16 GCC1/IO91PPB1

K17 IO90NPB1

K18 IO88PDB1

484-Pin FBGA*

Pin Number A3P1000 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

4-70 v2.1

K19 IO88NDB1

K20 IO94NPB1

K21 IO98NDB1

K22 IO98PDB1

L1 NC

L2 IO200PDB3

L3 IO210NPB3

L4 GFB0/IO208NPB3

L5 GFA0/IO207NDB3

L6 GFB1/IO208PPB3

L7 VCOMPLF

L8 GFC0/IO209NPB3

L9 VCC

L10 GND

L11 GND

L12 GND

L13 GND

L14 VCC

L15 GCC0/IO91NPB1

L16 GCB1/IO92PPB1

L17 GCA0/IO93NPB1

L18 IO96NPB1

L19 GCB0/IO92NPB1

L20 IO97PDB1

L21 IO97NDB1

L22 IO99NPB1

M1 NC

M2 IO200NDB3

M3 IO206NDB3

M4 GFA2/IO206PDB3

M5 GFA1/IO207PDB3

M6 VCCPLF

M7 IO205NDB3

M8 GFB2/IO205PDB3

M9 VCC

M10 GND

484-Pin FBGA*

Pin Number A3P1000 Function

M11 GND

M12 GND

M13 GND

M14 VCC

M15 GCB2/IO95PPB1

M16 GCA1/IO93PPB1

M17 GCC2/IO96PPB1

M18 IO100PPB1

M19 GCA2/IO94PPB1

M20 IO101PPB1

M21 IO99PPB1

M22 NC

N1 IO201NDB3

N2 IO201PDB3

N3 NC

N4 GFC2/IO204PDB3

N5 IO204NDB3

N6 IO203NDB3

N7 IO203PDB3

N8 VCCIB3

N9 VCC

N10 GND

N11 GND

N12 GND

N13 GND

N14 VCC

N15 VCCIB1

N16 IO95NPB1

N17 IO100NPB1

N18 IO102NDB1

N19 IO102PDB1

N20 NC

N21 IO101NPB1

N22 IO103PDB1

P1 NC

P2 IO199PDB3

484-Pin FBGA*

Pin Number A3P1000 Function

P3 IO199NDB3

P4 IO202NDB3

P5 IO202PDB3

P6 IO196PPB3

P7 IO193PPB3

P8 VCCIB3

P9 GND

P10 VCC

P11 VCC

P12 VCC

P13 VCC

P14 GND

P15 VCCIB1

P16 GDB0/IO112NPB1

P17 IO106NDB1

P18 IO106PDB1

P19 IO107PDB1

P20 NC

P21 IO104PDB1

P22 IO103NDB1

R1 NC

R2 IO197PPB3

R3 VCC

R4 IO197NPB3

R5 IO196NPB3

R6 IO193NPB3

R7 GEC0/IO190NPB3

R8 VMV3

R9 VCCIB2

R10 VCCIB2

R11 IO147RSB2

R12 IO136RSB2

R13 VCCIB2

R14 VCCIB2

R15 VMV2

R16 IO110NDB1

484-Pin FBGA*

Pin Number A3P1000 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

v2.1 4-71

R17 GDB1/IO112PPB1

R18 GDC1/IO111PDB1

R19 IO107NDB1

R20 VCC

R21 IO104NDB1

R22 IO105PDB1

T1 IO198PDB3

T2 IO198NDB3

T3 NC

T4 IO194PPB3

T5 IO192PPB3

T6 GEC1/IO190PPB3

T7 IO192NPB3

T8 GNDQ

T9 GEA2/IO187RSB2

T10 IO161RSB2

T11 IO155RSB2

T12 IO141RSB2

T13 IO129RSB2

T14 IO124RSB2

T15 GNDQ

T16 IO110PDB1

T17 VJTAG

T18 GDC0/IO111NDB1

T19 GDA1/IO113PDB1

T20 NC

T21 IO108PDB1

T22 IO105NDB1

U1 IO195PDB3

U2 IO195NDB3

U3 IO194NPB3

U4 GEB1/IO189PDB3

U5 GEB0/IO189NDB3

U6 VMV2

U7 IO179RSB2

U8 IO171RSB2

484-Pin FBGA*

Pin Number A3P1000 Function

U9 IO165RSB2

U10 IO159RSB2

U11 IO151RSB2

U12 IO137RSB2

U13 IO134RSB2

U14 IO128RSB2

U15 VMV1

U16 TCK

U17 VPUMP

U18 TRST

U19 GDA0/IO113NDB1

U20 NC

U21 IO108NDB1

U22 IO109PDB1

V1 NC

V2 NC

V3 GND

V4 GEA1/IO188PDB3

V5 GEA0/IO188NDB3

V6 IO184RSB2

V7 GEC2/IO185RSB2

V8 IO168RSB2

V9 IO163RSB2

V10 IO157RSB2

V11 IO149RSB2

V12 IO143RSB2

V13 IO138RSB2

V14 IO131RSB2

V15 IO125RSB2

V16 GDB2/IO115RSB2

V17 TDI

V18 GNDQ

V19 TDO

V20 GND

V21 NC

V22 IO109NDB1

484-Pin FBGA*

Pin Number A3P1000 Function

W1 NC

W2 IO191PDB3

W3 NC

W4 GND

W5 IO183RSB2

W6 GEB2/IO186RSB2

W7 IO172RSB2

W8 IO170RSB2

W9 IO164RSB2

W10 IO158RSB2

W11 IO153RSB2

W12 IO142RSB2

W13 IO135RSB2

W14 IO130RSB2

W15 GDC2/IO116RSB2

W16 IO120RSB2

W17 GDA2/IO114RSB2

W18 TMS

W19 GND

W20 NC

W21 NC

W22 NC

Y1 VCCIB3

Y2 IO191NDB3

Y3 NC

Y4 IO182RSB2

Y5 GND

Y6 IO177RSB2

Y7 IO174RSB2

Y8 VCC

Y9 VCC

Y10 IO154RSB2

Y11 IO148RSB2

Y12 IO140RSB2

Y13 NC

Y14 VCC

484-Pin FBGA*

Pin Number A3P1000 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3 Flash Family FPGAs

4-72 v2.1

Y15 VCC

Y16 NC

Y17 NC

Y18 GND

Y19 NC

Y20 NC

Y21 NC

Y22 VCCIB1

AA1 GND

AA2 VCCIB3

AA3 NC

AA4 IO181RSB2

AA5 IO178RSB2

AA6 IO175RSB2

AA7 IO169RSB2

AA8 IO166RSB2

AA9 IO160RSB2

AA10 IO152RSB2

484-Pin FBGA*

Pin Number A3P1000 Function

AA11 IO146RSB2

AA12 IO139RSB2

AA13 IO133RSB2

AA14 NC

AA15 NC

AA16 IO122RSB2

AA17 IO119RSB2

AA18 IO117RSB2

AA19 NC

AA20 NC

AA21 VCCIB1

AA22 GND

AB1 GND

AB2 GND

AB3 VCCIB2

AB4 IO180RSB2

AB5 IO176RSB2

AB6 IO173RSB2

484-Pin FBGA*

Pin Number A3P1000 Function

AB7 IO167RSB2

AB8 IO162RSB2

AB9 IO156RSB2

AB10 IO150RSB2

AB11 IO145RSB2

AB12 IO144RSB2

AB13 IO132RSB2

AB14 IO127RSB2

AB15 IO126RSB2

AB16 IO123RSB2

AB17 IO121RSB2

AB18 IO118RSB2

AB19 NC

AB20 VCCIB2

AB21 GND

AB22 GND

484-Pin FBGA*

Pin Number A3P1000 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC®3/E Flash Family FPGAs

v2.1 5-1

Datasheet Information

List of Changes

The following table lists critical changes that were made in the current version of the document.

Previous Version Changes in Current Version (v2.1) Page

v2.0

April 2007

In the "Clock Conditioning Circuit (CCC) and PLL (except A3P030)" section, the Wide Input

Frequency Range (1.5 MHz to 200 MHz) was changed to (1.5 MHz to 350 MHz).

Table 3-5 • Package Thermal Resistivities was updated with A3P1000 information. The note

below the table is also new.

3-4

Advanced v0.7

January 2007

The timing characteristics tables were updated. N/A

The "Clock Conditioning Circuit (CCC) and PLL (except A3P030)" section was updated. i

In the "I/Os Per Package1" section, the A3P030, A3P060, A3P125, ACP250, and A3P600

device I/Os were updated.

The "PLL Macro" section was updated to add information on the VCO and PLL outputs during

power-up.

2-17

The following pin tables were updated for A3P600: "208-Pin PQFP*", "256-Pin FBGA*", and

"484-Pin FBGA*". The "144-Pin FBGA*" table for A3P600 is new.

4-27–4-63

In the "ProASIC3 Ordering Information", Ambient was deleted. iii

Ambient was deleted from "Speed Grade and Temperature Grade Matrix" iv

Ambient was deleted from the"Speed Grade and Temperature Grade Matrix".iv

The "PLL Macro" section was updated to include power-up information. 2-17

Table 2-4 • ProASIC3 CCC/PLL Specification was updated. 2-20

Figure 2-19 • Peak-to-Peak Jitter Definition is new. 2-20

The "SRAM and FIFO" section was updated with operation and timing requirement

information.

2-23

The "RESET" section was updated with read and write information. 2-26

The "RESET" section was updated with read and write information. 2-27

The"Introduction" in the "Advanced I/Os" section was updated to include information on input

and output buffers being disabled.

2-29

PCI-X 3.3 V was added to Table 2-12 • VCCI Voltages and Compatible ProASIC3 Standards.2-30

In the Table 2-16 • Levels of Hot-Swap Support, the ProASIC3 compliance descriptions were

updated for levels 3 and 4.

2-36

Table 2-17 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in ProASIC3 Devices was

updated.

2-38

Notes 3, 4, and 5 were added to Table 2-18 • Comparison Table for 5 V–Compliant Receiver

Scheme. 5 x 52.72 was changed to 52.7 and the Maximum current was updated from 4 x 52.7

to 5 x 52.7.

2-42

The "VCCPLF PLL Supply Voltage" section was updated. 2-52

The "VPUMP Programming Supply Voltage" section was updated. 2-52

The "GL Globals" section was updated to include information about direct input into quandrant

clocks.

2-53

ProASIC®3/E Flash Family FPGAs

5-2 v2.1

Advanced v0.7

(continued)

VJTAG was deleted from the "TCK Test Clock" section.2-53

In Table 2-24 • Recommended Tie-Off Values for the TCK and TRST Pins, TSK was changed to

TCK in note 2. Note 3 was also updated.

2-53

Ambient was deleted from Table 3-2 • Recommended Operating Conditions. VPUMP

programming mode was changed from "3.0 to 3.6" to "3.15 to 3.45".

3-2

Note 3 is new in Table 3-4 • Overshoot and Undershoot Limits (as measured on quiet I/Os)1 3-2

In EQ 3-2, 150 was changed to 110 and the result changed from 3.9 to 1.951. 3-4

Table 3-6 • Temperature and Voltage Derating Factors for Timing Delays was updated. 3-5

Table 3-5 • Package Thermal Resistivities was updated. 3-4

Table 3-14 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to

Commercial and Industrial Conditions—Software Default Settings (Advanced) and Table 3-

17 • Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and

Industrial Conditions (Standard Plus) were updated.

3-15 to 3-15

Table 3-20 • Summary of I/O Timing Characteristics—Software Default Settings (Advanced)

and Table 3-21 • Summary of I/O Timing Characteristics—Software Default Settings (Standard

Plus) were updated.

3-18 to 3-18

Table 3-11 • Different Components Contributing to Dynamic Power Consumption in ProASIC3

Devices was updated.

3-7

Table 3-24 • I/O Output Buffer Maximum Resistances1 (Advanced) and Table 3-25 • I/O

Output Buffer Maximum Resistances1 (Standard Plus) were updated.

3-20 to 3-20

Table 3-17 • Summary of Maximum and Minimum DC Input Levels Applicable to Commercial

and Industrial Conditions was updated.

3-16

Table 3-28 • I/O Short Currents IOSH/IOSL (Advanced) and Table 3-29 • I/O Short Currents

IOSH/IOSL (Standard Plus) were updated.

3-22 to 3-23

The note in Table 3-32 • I/O Input Rise Time, Fall Time, and Related I/O Reliability was updated. 3-25

Figure 3-33 • Write Access After Write onto Same Address, Figure 3-34 • Read Access After

Write onto Same Address, and Figure 3-35 • Write Access After Read onto Same Address are

new.

3-80 to 3-82

Figure 3-43 • Timing Diagram was updated. 3-94

Notes were added to the package diagrams identifying if they were top or bottom view. N/A

The A3P030 "132-Pin QFN*" table is new. 4-2

The A3P060 "132-Pin QFN" table is new. 4-4

The A3P125 "132-Pin QFN" table is new. 4-6

The A3P250 "132-Pin QFN" table is new. 4-8

The A3P030 "100-Pin VQFP" table is new. 4-11

Advanced v0.6

(April 2006)

In the "I/Os Per Package1"table, the I/O numbers were added for A3P060, A3P125, and

A3P250. The A3P030-VQ100 I/O was changed from 79 to 77.

Advanced v0.5

(January 2006)

BLVDS and M-LDVS are new I/O standards added to the datasheet. N/A

The term flow-through was changed to pass-through. N/A

Table 1 was updated to include the QN132. i

Previous Version Changes in Current Version (v2.1) Page

ProASIC®3/E Flash Family FPGAs

v2.1 5-3

Advanced v0.5

(January 2006)

The "I/Os Per Package1" table was updated with the QN132. The footnotes were also updated.

The A3P400-FG144 I/O count was updated.

"ProASIC3 Ordering Information" was updated with the QN132. iii

"Temperature Grade Offerings" was updated with the QN132. iv

The "I/Os with Advanced I/O Standards" section was updated to include I/O bank information. 1-5

Figure 2-7 • Efficient Long-Line Resources was updated. 2-8

The footnotes in Figure 2-15 • Clock Input Sources Including CLKBUF, CLKBUF_LVDS/LVPECL,

and CLKINT were updated.

2-18

The Delay Increments in the Programmable Delay Blocks specification in Figure 2-

14 • ProASIC3 CCC Options.

2-16

The "SRAM and FIFO" section was updated. 2-23

The "RESET" section was updated. 2-26

The "WCLK and RCLK" section was updated. 2-27

The "RESET" section was updated. 2-27

The "RESET" section was updated. 2-28

The "Introduction" of the "Advanced I/Os" section 2-29

The "I/O Banks" section is new. This section explains the following types of I/Os:

Advanced

Standard+

Standard

Table 2-13 • ProASIC3 Bank Types Definition and Differences is new. This table describes the

standards listed above.

2-31

PCI-X 3.3 V was added to the Compatible Standards for 3.3 V in Table 2-12 • VCCI Voltages

and Compatible ProASIC3 Standards

2-30

Table 2-14 • ProASIC3 I/O Features was updated. 2-32

The "Double Data Rate (DDR) Support" section was updated to include information concerning

implementation of the feature.

2-34

The "Electrostatic Discharge (ESD) Protection" section was updated to include testing

information.

2-37

Level 3 and 4 descriptions were updated in Table 2-17 • I/O Hot-Swap and 5 V Input Tolerance

Capabilities in ProASIC3 Devices.

2-38

The notes in Table 2-17 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in ProASIC3

Devices were updated.

2-38

The "Simultaneous Switching Outputs (SSOs) and Printed Circuit Board Layout" section is new. 2-43

A footnote was added to Table 2-15 • Maximum I/O Frequency for Single-Ended and

Differential I/Os in All Banks in ProASIC3 Devices (maximum drive strength and high slew

selected).

2-32

Table 2-19 • ProASIC3 I/O Attributes vs. I/O Standard Applications 2-47

Table 2-21 • ProASIC3 Output Drive (OUT_DRIVE) for Standard I/O Bank Type (A3P030 device) 2-48

Table 2-22 • ProASIC3 Output Drive for Standard+ I/O Bank Type was updated. 2-49

Table 2-23 • ProASIC3 Output Drive for Advanced I/O Bank Type was updated. 2-49

The "x" was updated in the "User I/O Naming Convention" section.2-50

The "VCC Core Supply Voltage" pin description was updated. 2-52

Previous Version Changes in Current Version (v2.1) Page

ProASIC®3/E Flash Family FPGAs

5-4 v2.1

Advanced v0.5

(continued)

The "VMVx I/O Supply Voltage (quiet)" pin description was updated to include information

concerning leaving the pin unconnected.

2-52

The "VJTAG JTAG Supply Voltage" pin description was updated. 2-52

The "VPUMP Programming Supply Voltage" pin description was updated to include information

on what happens when the pin is tied to ground.

2-52

The "I/O User Input/Output" pin description was updated to include information on what

happens when the pin is unused.

2-52

The "JTAG Pins" section was updated to include information on what happens when the pin is

unused.

2-53

The "Programming" section was updated to include information concerning serialization. 2-54

The "JTAG 1532" section was updated to include SAMPLE/PRELOAD information. 2-55

"DC and Switching Characteristics" chapter was updated with new information. Starting on

page 3-1

The A3P060 "100-Pin VQFP*" pin table was updated. 4-13

The A3P125 "100-Pin VQFP*" pin table was updated. 4-13

The A3P060 "144-Pin TQFP*" pin table was updated. 4-16

The A3P125 "144-Pin TQFP*" pin table was updated. 4-18

The A3P125 "208-Pin PQFP*" pin table was updated. 4-21

The A3P400 "208-Pin PQFP*" pin table was updated. 4-25

The A3P060 "144-Pin FBGA*" pin table was updated. 4-32

The A3P125 "144-Pin FBGA*" pin table is new. 4-34

The A3P400 "144-Pin FBGA*" is new. 4-38

The A3P400 "256-Pin FBGA" was updated. 4-48

The A3P1000 "256-Pin FBGA*" was updated. 4-54

The A3P400 "484-Pin FBGA*" was updated. 4-58

The A3P1000 "484-Pin FBGA*" was updated. 4-68

Advanced v0.4

(November 2005)

The "I/Os Per Package1" table was updated for the following devices and packages:

Device Package

A3P250/M7ACP250 VQ100

A3P250/M7ACP250 FG144

A3P1000 FG256

Advanced v0.3 M7 device information is new. N/A

The I/O counts in the "I/Os Per Package1" table were updated. ii

The "Security" section was updated to include information concerning M7 ProASIC3 AES

support.

1-1

In the "PLL and CCC" section, the low jitter bullet was updated. 1-5

Table 2-2 • ProASIC3 Globals/Spines/Rows by Device was updated to include the number or

rows in each top or bottom spine.

2-12

EXTFB was removed from Figure 2-14 • ProASIC3 CCC Options.2-16

The "PLL Macro" section was updated. EXTFB information was removed from this section. 2-17

The CCC Output Peak-to-Peak Period Jitter FCCC_OUT was updated in Table 2-4 • ProASIC3

CCC/PLL Specification.

2-20

EXTFB was removed from Figure 2-17 • CCC/PLL Macro.2-19

Previous Version Changes in Current Version (v2.1) Page

ProASIC®3/E Flash Family FPGAs

v2.1 5-5

Advanced v0.3

(continued)

Table 2-14 • ProASIC3 I/O Features was updated. 2-32

The "Hot-Swap Support" section was updated. 2-35

The "Cold-Sparing Support" section was updated. 2-37

"Electrostatic Discharge (ESD) Protection" section was updated. 2-37

The LVPECL specification in Table 2-17 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in

ProASIC3 Devices was updated.

2-38

In the Bank 1 area of Figure 2-37, VMV2 was changed to VMV1 nd VCCIB2 was changed to

VCCIB1.

2-50

The VJTAG and I/O pin descriptions were updated in the "Pin Descriptions" section.2-52

The "JTAG Pins" section was updated. 2-53

"128-Bit AES Decryption" section was updated to include M7 device information. 2-54

Table 3- 6 was updated. 3-5

Table 3- 7 was updated. 3-5

In Tab le 3-1 1, PAC4 was updated. 3-73-7

Table 3- 20 was updated. 3-18

The note in Tab le 3- 32 3-25

All Timing Charactertistics tables were updated from LVTTL to Register Delays 3-29 to 3-71

The Timing Characteristics for RAM4K9, RAM512X18, and FIFO were updated. 3-83 to 3-88

FTCKMAX was updated in Table 3-110 3-95

Advanced v0.2 The "I/Os Per Package1" table was updated. ii

The "Live at Power-Up" section is new. 1-2

Figure 2-5 was updated. 2-6

The "Clock Resources (VersaNets)" section was updated. 2-10

The "VersaNet Global Networks and Spine Access" section was updated. 2-10

The "PLL Macro" section was updated. 2-17

Figure 2-17 was updated. 2-19

Figure 2-20 was updated. 2-21

Table 2- 6 was updated. 2-26

Table 2- 7 was updated. 2-26

The "FIFO Flag Usage Considerations" section was updated. 2-29

Table 2- 14 was updated. 2-32

Figure 2-24 was updated. 2-33

The "Cold-Sparing Support" section is new. 2-37

Table 2- 17 was updated. 2-38

Table 2- 19 was updated. 2-47

Pin descriptions in the "JTAG Pins" section were updated. 2-53

The "User I/O Naming Convention" section was updated. 2-50

Table 3- 7 was updated. 3-5

The "Methodology" section was updated. 3-8

Previous Version Changes in Current Version (v2.1) Page

ProASIC®3/E Flash Family FPGAs

5-6 v2.1

Advanced v0.2

(continued)

Table 3- 40 and Ta bl e 3- 39 were updated. 3-31, 3-30

The A3P250 "100-Pin VQFP*" pin table was updated. 4-14

The A3P250 "208-Pin PQFP*" pin table was updated. 4-23

The A3P1000 "208-Pin PQFP*" pin table was udpated. 4-29

The A3P250 "144-Pin FBGA*" pin table was updated. 4-36

The A3P1000 "144-Pin FBGA*" pin table was updated. 4-32

The A3P250 "256-Pin FBGA*" pin table was updated. 4-45

The A3P1000 "256-Pin FBGA*" pin table was updated. 4-54

The A3P1000 "484-Pin FBGA*" pin table was updated. 4-68

Previous Version Changes in Current Version (v2.1) Page

ProASIC®3/E Flash Family FPGAs

v2.1 5-7

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51700012-8/5.07

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