M41ST84YMH6F - STMicroelectronics

1/31October 2004

M41ST84Y

M41ST84W

5.0 or 3.0V, 512 bit (64 x8) Serial RTC

with Supervisory Functions

* Contact Local Sales Office

FEATURES SUMM ARY

■5.0 OR 3.0V OPERATI NG VOLT AGE

■SERIA L INT ERFACE SUPPORT S I2C BU S

(400kHz)

■O P TI MI ZE D FOR MI NIM AL

INTERCONNECT TO MCU

■2.5 TO 5.5V OSCILLATOR OPERATING

VOLTAGE

■AUTOMATIC SWITCH-OVER AND

DESELECT CIRCUITRY

■CHOICE OF POWER-F AIL DESELECT

VOLTAGES:

– M41S T 84Y : VCC = 4.5 to 5.5V;

4.20V ≤ VPFD ≤ 4.50V

– M41ST84W: VCC = 2.7 to 3.6V;

2.55V ≤ VPFD ≤ 2.70V

■1.25V REFERENCE (for PFI/P FO)

■COUNT ERS FOR TENTHS/HUNDREDTHS

OF SECONDS, SECONDS, MINUTES,

HOURS, DAY, DATE, MONTH, YEAR, AND

CENTURY

■44 BYTES OF GENERAL PURPOSE RAM

■PROGRAMMABLE AL AR M AN D

INTERRUPT FUNCTION (VALID EVEN

DURING BATTERY BACK-UP MODE )

■WA TCHDOG TIMER

■MICROPROCESSOR POWER-ON RESET

■BATTERY L OW FLAG

■POWER -DOWN TIME-S TAMP (HT Bit)

■ULTRA-L OW BA TTERY SUPP LY CURRE NT

OF 500 nA (max)

■OPTIONAL PACKAGING INCLUDES A 28-

LEAD SOIC and SNAPH AT® TOP ( t o be

ord ered separately)

■SNAPHAT PACKAGE PROVIDES DIRECT

CONNECTION FOR A SNAPHAT TOP,

WHICH CONTAIN S THE BATTERY AND

CRYSTAL

Figu re 1. 16- pi n S OI C Package

Figu re 2. 28- pi n S OI C Package*

SO16 (MQ)

SOH28 (MH)

SNAPHAT (SH)

Battery & Crystal

M41ST84Y, M 41ST84W

2/31

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. 16-pin SOIC Packag e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2. 28-pin SOIC Packag e*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 4. 16-pin SO IC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 5. 28-pin SO IC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 6. Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 7. Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2-Wire Bus Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Bus not busy.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Start data transfer.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Stop data transfe r.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Data Valid.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Acknowl edge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 8. Serial Bus Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 9. Ackn owledg eme nt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 10.Bus Timing Requiremen ts Sequenc e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 2. AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 11.Slave Address Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 12.READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 13.Alternate READ Mode Sequenc e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1

Figure 14.WRITE Mode Seq uence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Power-down Time-Sta mp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

TIMEKEEPER® Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2

Table 3. TIMEKEEPER® Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 15.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 16.Clock Calibratio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5

Setting Alarm Clock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6

Figure 17.Alarm Interru pt Reset Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 4. A larm Repeat Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Figure 18.Back-Up Mode Alarm Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3/31

M41ST84Y, M 41ST84W

Sq uare Wave Outp ut . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8

Table 5. S quare Wave Out put Frequen cy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Po wer-o n Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9

R eset Input (RSTIN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 19.RSTIN Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 6. Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Power-fail INPUT/OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0

Century Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0

Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Battery Low Warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0

tREC Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 7. tREC Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 8. Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1

MAXIMU M RATING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 9. Absolute Maximum Rati ngs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2

Table 10. DC and A C Measurem ent Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 20.AC Testing Input/Output W aveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 11. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 12. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3

Table 13. Cry stal Electrical Characteristics (Externally Suppli ed) . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 21.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 14 . Power Down/Up AC Characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

PAC KAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 22.SO16 – 16-lead Plastic Small Outline, Package Outlin e. . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 15. S O16 – 16-lead Plastic Small Outline, Package M ec hanical Data . . . . . . . . . . . . . . . . . 25

Figure 23.SOH28 – 28-lead Plastic Small Outline, Battery SNAPHAT , Package Outline. . . . . . . . 26

Table 16. SOH28 – 28-lead Plastic S mall Outline, battery SNAPHAT, Package Mechani cal Data 26

Figure 24.SH – 4-pin SNAPHA T Housing for 48mAh Ba ttery & Crystal, Package Outline . . . . . . . 27

Table 17. SH – 4-pin SNAPHAT Housi ng for 48mAh Battery & Crystal, Package Mechanical Data27

Figure 25.SH – 4-pin SNAPHA T Housing for 120mAh B attery & Crystal, Pack age Ou tline . . . . . . 28

Table 18. SH – 4-pin SNAPH AT Housing for 120mAh B attery & Crystal, Package M ec h. Data . . . 28

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 19. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 20. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 21. Document Re vision Histo ry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

M41ST84Y, M 41ST84W

4/31

S UM MARY DESCR IPTION

Th e M41ST84Y/W Seria l superv isory TIMEKEEP-

ER® SRAM is a low power 512-bit static CMOS

SRAM organi zed as 64 words by 8 bi ts. A built-in

32.768kHz oscillator (external crystal controlled)

and 8 bytes of the SR AM (see Table 3., page 13)

are used for the clock/calendar function and are

configured in binary co ded decim al (BCD) format.

An addit ional 12 bytes of RAM pr ovide stat us /con-

trol of Alarm, Watchdog and Square Wave func-

tions. Addresses and dat a are transferred serially

via a two line, bi-directional I2C interface. The

built-in address register is incremented automati-

cally after each W RITE or READ data byte.

The M41ST8 4Y/W has a built-in power sense cir-

cuit which detects power failures and aut omatical-

ly switches to the battery supply when a power

failure occurs. The energy needed to sustain the

SRAM and clock opera tions can be supplie d by a

small lithium button-cell supply when a power fail-

ure occurs. Funct ions avai lable to the user include

a non-volatile, time-of-day clock/calendar, Alarm

interrupts, Watchdog Timer and programmable

Square Wave output. Other features include a

Power-On Reset as well as an additional input

(RSTIN) whi ch can also generate an output Reset

(RST). The eight clock address locations contain

the century, year, month, dat e, day, ho ur, min ute,

second and tenths/hundredths of a second in 24

hour BCD format. Corrections for 28, 29 (leap year

- valid until year 21 00), 30 and 31 da y months are

m ade automat ically.

The M41ST84Y/W is supplied in a 28-lead SOIC

SNAPHAT® package (whi ch integrat es both crys-

tal and battery in a single SNAPH AT t op) o r a 16-

pin SOIC. The 28-pi n, 330mi l SOIC provides sock-

ets with gold plated contacts at both ends f or direct

connection to a separa te SNAPHAT hous ing con-

taining the battery and crysta l. The unique d esign

allows the SNAPHAT battery/crystal package to

be mounted on top of th e SOI C pac kage after the

completion of the surface mount process.

Insertion of the SNAPHAT housing after reflow

prevents potent ial bat tery and crystal damage due

to the high temperatures required for device sur-

face-mounting. The SNAPHAT housing is also

keyed to prevent reverse insertion.

The 28-pin SOIC and battery/crystal packages are

shipped separately in plastic anti-static tubes or i n

Tape & Reel form. For the 28-lead SOIC, the bat-

tery/crystal package (e.g., SNAPHAT) part num-

ber is “M4TXX-BR12SH” (see Table

20., page 29).

Caution: Do not place the SNAPHAT battery/crys-

tal top in conductive foam, as this will drain the lith-

ium but ton-cell battery.

Figure 3. Logic Diagram

Note: 1. For SO 16 pack age only .

Table 1. Signal Names

Note: 1. For SO 16 pack age only .

AI03677

SCL

VCC

M41ST84Y

M41ST84W

VSS

SDA

RSTIN

IRQ/FT/OUT

SQW

WDI

PFI

RST

PFO

VBAT

(1)

XI (1) Oscillator Input

XO (1) Oscillator Output

IRQ/FT/OUT Interrupt/Frequency Test/Out

Output (Open Drain)

PFI Power Fail Input

PFO Power Fail Output

RST Reset Output (Open Drain)

RSTIN Reset Input

SCL Serial Clock Input

SDA Serial Data Input/Output

SQW Square Wave Output

WDI Watchdog Input

VCC Supply Voltage

VBAT (1) Battery Supply Voltage

VSS Ground

5/31

M41ST84Y, M 41ST84W

Figu re 4. 16- pi n S O I C Co nnecti ons Figu re 5. 28- pi n S O I C C onnecti ons

Figu re 6. Blo ck Diagram

Note: 1. Ope n drain output

AI03678

RSTIN

WDI IRQ/FT/OUT

SDA

VBAT

PFI

SQW

SCL

PFO

VSS

RST

XI VCC

M41ST84Y

M41ST84W

AI03679

RSTIN

WDI

IRQ/FT/OUT

PFI

SCL

NCNC

PFO

VSS SDA

RST

SQW VCC

M41ST84Y

M41ST84W

AI03931

COMPARE

VPFD = 4.4V

VCC

COMPARE

VSO = 2.5V

POWER

VBL= 2.5V BL

COMPARE

Crystal

I2C

INTERFACE

REAL TIME CLOCK

CALENDAR

44 BYTES

USER RAM

RTC w/ALARM

& CALIBRATION

WATCHDOG

SQU ARE W AVE

SDA

SCL

1.25V

PFI PFO

RSTIN

POR

SQW

RST(1)

WDI

WDF

IRQ/FT/OUT(1)

VBAT

32KHz

OSCILLATOR

COMPARE

(2.65V for ST84W)

(Internal)

M41ST84Y, M 41ST84W

6/31

Figure 7. Hardware Hookup

AI03680

VCC

PFO

SCL

WDI

RSTIN

PFI

VSS

IRQ/FT/OUT

SQW

RST

SDA

M41ST84Y/W

Unregulated

Voltage

Regulator

VCC

VIN

To RST

To LED Display

To NMI

To INT

From MCU

7/31

M41ST84Y, M 41ST84W

OPE RATIN G MODES

The M41ST84Y/W clock operates as a slave de-

vice on the serial bus. Access is obtained by im-

plementing a start condition followed by the

correct slave address (D0h). The 64 bytes con-

tained in the device can then be accessed sequen-

tially in the f ollowing order:

1. Tenths/Hundredths of a S econd Register

2. Seconds Regist er

3. Minutes Register

4. Century/Hours Register

5. Day Register

6. Date Register

7. Month Register

8. Year Register

9. Control Register

10. Watchdog Register

11 - 16. A larm Registers

17 - 19. Reserv ed

20. Square Wave Regi ster

21 - 64. User RAM

The M41ST84Y/ W cloc k continually monitors VCC

for an out-of tolerance condition. Should VCC fa ll

below VPFD, the device terminates an access in

progress and resets the device address counter.

Inputs to the device will not be recognized at this

time to prev ent erroneous data fr om bei ng wri tten

to the device from a an out-of-tolerance system.

When VCC falls below VSO, the device automati-

cally switches over to the battery and powers

down into an ultra low curr ent mode of operation to

conserv e battery life. As system power returns and

VCC rises above V SO, the battery is disconnected,

and the power supply is switched to external V CC.

Write protection continues until VCC reaches

VPFD(mi n) plus tREC (min).

For more information on Battery Storage Li fe refer

to Application Note AN1012.

2-Wire Bus Characteristics

The bus is intended for communication between

different ICs. It consists of two lines: a bi-direction-

al data signal (SDA) and a clock signal (SCL).

Both the SDA and SCL lines mus t be connected to

a positive supply voltage via a p ull-up resistor.

The following protocol has been defined:

– Data transfer may be initiated only when the

bus is not busy.

– During data transfer, the data line must remain

stable whenever the clock line is High.

– Changes in the data line, while the clock line is

H igh, will be interpreted as control signals.

Accordingly, the following bus conditions have

been defined:

Bus not busy. Both data and clock lines remain

High.

Start data transfer. A change in the state of the

data li ne, from Hi gh to Low, while t he clock is High,

defines the START condi tion.

Stop data transfer. A change in the state of the

data line, from Low to High, while the clock is High,

defines the STOP condition .

Data Va lid. The state of the data line repre se nts

valid data when after a start condition, the dat a line

is stable for the duration of the high period of the

clock signal. T he data on the line may be changed

during the Low period of the clock signal. There i s

one clock pulse per bit of data.

Each data transfer is initiated with a start condi tion

and terminated with a stop condition. The number

of data bytes transferred between the start and

stop conditions is not limited. The information is

transmitted byte-wide and each rec eiver ack nowl-

edges with a nin th bit.

By definition a dev ice t hat gives o ut a m essag e is

called “transmitter”, the receiving device t hat g ets

the messa ge is called “receiver”. The device that

controls the message is called “master”. The de-

vices that are controlled by the master are called

“slaves”.

Acknowledge. E ac h byte of eight bits is f oll owed

by one Acknowledge B it. This A cknowledge Bit is

a low level put on t he bus by the receiver whereas

the master generates an extra acknowled ge relat-

ed clock pulse. A slave receiver which is ad-

dressed is obliged to generate an acknowledge

after the reception of each byte that has been

clocked out of the slave transmitter.

The device that acknowledges has to pull down

the SDA line during the acknowledge clock pulse

in such a way that the SDA line is a stable Low dur-

ing the High period of the acknowledge related

clock pulse. Of course, setup and hold times mus t

be taken int o account. A master recei ver must sig-

nal an end of data to the slave transmitter by not

generating an acknowledge on the last byte that

has been cloc ked out of the slave. I n this case the

transmitter must l eave the data l ine High to enable

the mast er to generate the STOP condition.

M41ST84Y, M 41ST84W

8/31

Figure 8. Serial Bus Data Transfer Sequen ce

Figure 9. Ackno wledgement Sequence

AI00587

DATA

CLOCK

DATA LINE

STABLE

DATA VALID

START

CONDITION CHANGE OF

DATA ALLOWED STOP

CONDITION

AI00601

DATA OUTPUT

BY RECEIVER

DATA OUTPUT

BY TRANSMITTER

SCLK FROM

MASTER

START CLOCK PULSE FOR

ACKNOWLEDGEMENT

12 89

MSB LSB

9/31

M41ST84Y, M 41ST84W

Figure 10. Bus Timing Requirements Sequence

Table 2. AC Characteristics

Note: 1. Vali d for Ambient Operating T em perature: TA = –40 t o 85°C; VCC = 2.7 to 3.6V or 4.5 to 5.5V (except where noted).

2. Transmitter mu st in te rnally provide a hold t ime to bridge the un def i ned regi on (300ns max) of the fa lling edge of SCL.

Symbol Parameter(1) Min Max Unit

fSCL SCL Clock Frequency 0 400 kHz

tBUF Time the bus must be free before a new transmission can start 1.3 µs

tFSDA and SCL Fall Time 300 ns

tHD:DAT(2) Data Hold Time 0 µs

tHD:STA START Condition Hold Time

(after this period the first clock pulse is generated) 600 ns

tHIGH Clock High Period 600 ns

tLOW Clock Low Period 1.3 µs

tRSDA and SCL Rise Time 300 ns

tSU:DAT Data Setup Time 100 ns

tSU:STA START Condition Setup Time

(only relevant for a repeated start condition) 600 ns

tSU:STO STOP Condition Setup Time 600 ns

AI00589

SDA

PtSU:STOtSU:STA

tHD:STA

SCL

tSU:DAT

tHD:DAT

tHIGH

tLOW

tHD:STAtBUF

M41ST84Y, M 41ST84W

10/31

READ Mode

In this mode the master reads the M41ST84Y/W

slave after setting the slave address (see Figure

11., page 10). Following the WRITE Mode Control

Bit (R/W=0) and the Acknowledge Bit, the word

address ‘An’ is written to the on-chip address

pointer. Next the START condition and slave ad-

dress are repeated followed by the READ Mode

Control Bit (R/W=1). At this point the master trans-

mitter becomes the master receiver. The data byte

which was addressed will be transmitted and the

master receiver will send an Acknowledge Bit to

the slave transmitter. The address pointe r is only

incremented on reception of an Acknowledge

Clock. The M41ST84Y/W slave transmitter will

now place the data byte at address An+1 on the

bus, the master receiver reads and acknowledges

the new byte and the address pointer is

incremented to “An+2.”

This cycle of reading consecutive addresses will

continue until the master receiver se nds a STOP

condition to the slave transmitter (see Figure

12., page 10).

The system-to-user transfer of clock data will be

halted whenever the address bei ng read is a clock

address (00h to 07h). The update will resume ei-

ther due to a Stop Condition or when the pointer

increments to a non-clock or RAM address .

Note: This is true bot h in READ Mode and WRITE

Mode.

An alternate READ Mode may also be implement -

ed whereby the master reads the M41ST84Y/W

slave without first writing to th e (volatile) address

pointer. The first address that is read is the last

one stored in the pointer (see Figure

13., page 11).

Figure 11. Slave Address Lo cation

Figure 1 2 . RE A D Mode Se quence

AI00602

R/W

SLAVE ADDRESS

START A

0100011

MSB

LSB

AI00899

BUS ACTIVITY:

ACK

NO ACK STOP

START

SDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1

DATA n+X

WORD

ADDRESS (An)

SLAVE

ADDRESS

START

R/W

SLAVE

ADDRESS

ACK

11/31

M41ST84Y, M 41ST84W

Figu re 13 . Al te rnat e R E A D Mo de S equence

WRITE Mod e

In this mode the master transmitter transmits to

the M41ST84Y/W slave receiver. Bus protocol is

shown in Figure 14., page 11. Following the

START condition and slave address, a logic '0' (R/

W=0) is placed on the bus and indicates to t he ad-

dressed device that word address An will follow

and is to be written to t he on-chip address pointer.

The data word to be written to the memory is

strobed in next and t he internal addres s pointer is

incremented to the next memory location within

the RAM on the reception of an acknowledge

clock. The M41ST84Y/W slave receiver will send

an acknowledge clock to the master transmitter af-

ter it has received the slave address (see Figure

11., page 10) and again after it has received the

word address and eac h data byte.

Data Reten tion Mode

With valid VCC applied, t he M41ST 84Y/W can be

accessed as described above with READ or

WRITE cycles. Should the supply voltage decay,

the M41ST84Y/W will automatically deselect,

write protecting itself when VCC falls between

VPFD(max) and VPFD(min). This is accomplished

by internally inhibiting access to the clock regis-

te rs. At thi s time, th e Reset pin (RST ) i s driv en ac-

tive and will remain active until VCC returns to

nominal levels. When VCC falls below the Battery

Back-up Switchover Voltage (VSO), power input i s

switched from the VCC pin to the SNAPHAT® (or

external) battery, and the clock registers and

SRAM are maintained from the attached battery

supply.

All outputs become high impedance. On power up,

when VCC returns to a nominal value, write protec-

tion continues for tREC. The RST signal also re-

mains active during this time (see Figure

21., page 24).

For a further more detailed review of lifetime calcu-

lations, please see Application Note AN1012.

Figure 1 4 . WRI TE Mode Seque nce

AI00895

BUS ACTIVITY:

ACK

NO ACK STOP

START

PSDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1 DATA n+X

SLAVE

ADDRESS

AI00591

BUS ACTIVITY:

ACK

ACK STOP

START

PSDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1 DATA n+X

WORD

ADDRESS (An)

SLAVE

ADDRESS

M41ST84Y, M 41ST84W

12/31

C LOCK OPERATION

The eight byte clock register (see Table

3., page 13) is used to both set the clock and to

read the date and time from the clock, in a binary

coded decimal format . Tenths/Hundredths of Sec-

onds, Sec onds, Mi nut es, and Hours are contained

wi t h i n th e fir st fo u r re g ist e r s.

Note: A W RIT E to any cloc k reg is ter w ill re sult in

the Tenths/Hu ndredths of Seconds bei ng reset to

“00,” and Tenths/Hundredths of Seconds cannot

be written to any value other than “00.”

Bits D6 and D7 of Clock Register 03h (Century/

Hours Register) contain the CENTURY ENABLE

Bit (CEB) and the CENTURY Bit (CB). Setting

CEB to a '1' will cause CB to toggle, either from '0'

to '1' or fr om '1' to '0' at the turn of the century (de-

pending upon its initial state). If CEB is set to a '0,'

CB will not toggle. B its D0 through D2 of Register

04h contain the Day (day of week). Registers 05h,

06h, and 07h contain the Date (day of month),

Month and Years. The ninth clock register is the

Control Register (this is described in the Clock

Calibration section). Bit D7 of Register 01h con-

ta ins the STOP Bit ( ST). Settin g th i s b i t to a ' 1 ' wil l

cause the oscillator to stop. If the device i s expect -

ed to spend a significant amount of time on the

shelf, the oscillator may be stopped t o reduce cur-

rent drain. When reset t o a '0' the oscillator restarts

within one second.

The eight clock reg isters may be read on e by te at

a time, or in a sequ ential block. T he Control Reg-

ister (Address location 08h) may be accessed in-

dependently. Provision has been made to assure

that a cloc k update does not occur while any of the

eight clock addresses are being read. If a clock ad-

dress is being read, an upd ate of the clock regis-

ters will b e halt ed. T his will p reve nt a tr ansit ion of

data during the READ.

Power-down Time-Stamp

When a p ower failure oc curs, the Hal t Update Bit

(HT) will automatically be set to a '1.' This will pre-

vent the clock from updating the TIMEKEEPER®

registers, and will allow the user to read the exact

time of the power-down event. Resetting the HT

Bit to a '0' will allow the clock to update th e TIME-

KEEPER r e g isters with the current time. For mo r e

information, see Application Note AN157 2.

TIMEKEEPER® Registers

The M41ST84Y/W offers 12 additional internal

registers which contain the Alarm, Watchdog,

Flag, Square Wave and Con trol data. These reg-

isters are memory locations which contain external

(user accessible) and internal copies of the data

(usually referred to as BiPORT™ TIMEKEEPER

cells). The external copies are independent of in-

ternal functions except that they are updated peri-

odically by the simultaneous transfer of the

incremented internal copy. The i nternal divider (or

clock) chain wil l be reset upon the completion of a

WRITE to any clock address.

The system-to-user transfer of clock data will be

halted whenever the address bei ng read is a clock

address (00h to 07h). The update will resume ei-

ther due to a Stop Condition or when the pointer

increments to a non-clock or RAM address .

TIMEKEEPER and Alarm Registers store data in

BCD. Control, Watchdog and Sq uare Wave Reg-

isters store data in Binary Format.

13/31

M41ST84Y, M 41ST84W

Table 3. TIME KEEPE R® Re gister Ma p

Keys: S = Sig n Bit

FT = Frequency Test Bit

ST = Sto p Bit

0 = Must be set to zer o

BL = B at tery Low F l ag (Read only)

BMB0-BMB4 = Watchdog Multiplier Bits

CE B = C entury Enable Bit

CB = Century B i t

OUT = Output level

AFE = Ala rm Flag Enable Flag

RB 0-RB1 = Wa tc hdog Resolution Bi t s

WDS = Watchd og Steeri ng Bit

ABE = Alarm in Bat te ry Back-Up Mode Enab le Bit

RP T 1-RPT5 = A l arm Repeat M ode Bits

WDF = Watchdog flag (Read only)

AF = A l arm flag (Read only)

SQWE = Square Wave Enable

RS 0-RS3 = SQ W Frequency

HT = Halt Updat e Bit

TR = tREC Bit

Address Data Function/Range

BCD Format

D7 D6 D5 D4 D3 D2 D1 D0

00h 0.1 Seconds 0.01 Seconds Seconds 00-99

01h ST 10 Seconds Seconds Seconds 00-59

02h 0 10 Minutes Minutes Minutes 00-59

03h CEB CB 10 Hours Hours (24 Hour Format) Century/Hours 0-1/00-23

04hTR0000 Day of Week Day 01-7

05h 0 0 10 Date Date: Day of Month Date 01-31

06h00010M Month Month 01-12

07h 10 Years Year Year 00-99

08h OUT FT S Calibration Control

09h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog

0Ah AFE SQWE ABE Al 10M Alarm Month Al Month 01-12

0Bh RPT4 RPT5 AI 10 Date Alarm Date Al Date 01-31

0Ch RPT3 HT AI 10 Hour Alarm Hour Al Hour 00-23

0Dh RPT2 Alarm 10 Minutes Alarm Minutes Al Min 00-59

0Eh RPT1 Alarm 10 Seconds Alarm Seconds Al Sec 00-59

0FhWDFAF0BL0 0 0 0 Flags

10h00000000Reserved

11h00000000Reserved

12h00000000Reserved

13h RS3 RS2 RS1 RS0 0 0 0 0 SQW

M41ST84Y, M 41ST84W

14/31

Calibrating the Clock

The M41ST84Y/W is driven by a quartz controlled

oscillator with a nominal frequency of 32,768Hz.

The devices are tested not exceed +/–35 ppm

(parts per million) oscillator frequency error at

25oC, which equates to about +/–1.53 minutes per

month. When the Calibration circuit is properly em-

ployed, a ccuracy im proves to b etter than ±2 ppm

at 25°C.

The oscillation rate of crystals changes with tem-

perature (see Figure 15., page 15). Therefore, the

M41ST84Y/W design employs periodic counter

correction. The calibration circuit adds or subtracts

counts from the oscillator divider circuit at the di-

vide by 256 stage, as shown in Figure

16., page 15. The number of times pulses which

are blanked (subtracted, negative calibration) or

split (added, positive calibration) depends upon

the value loaded into t he five Calibration bits found

in the Control Register. Adding counts speeds the

clock up, subtracting count s slows the clock down.

The Calibration bits occupy the five lower order

bits (D4-D0) in the Control Registe r (08 h). These

bits can be set to represent any value between 0

and 31 in binary form. Bit D5 is a Sign Bit; '1' indi-

cates positive calibration, '0' indicates negative

calibration. Calibration occurs within a 64 minute

cycle. The first 62 m inutes i n the cycle m ay, once

per minute, h ave one second either shortened by

128 or lengthened by 256 oscillator cycles. If a bi-

nary '1' is loaded into the register, only the first 2

minute s in the 64 minute cycle will be modified; if

a binary 6 is loaded, the first 12 will be affected,

and so on.

Therefore, each calibration step has the effect of

adding 512 or subtracting 256 osc illator cycles for

every 125,829,120 actual oscillator cycles, that is

+4.068 or –2.034 ppm of adjustment per calibra-

tion step i n t he cal ibration re gister. As sum ing that

the oscillator is running at exactly 32,768Hz, each

of the 31 increm ents in the Calibration byte wou ld

represent +10.7 or –5.35 seconds per month

which corresponds to a total range of +5.5 or –2.75

minutes per month.

Two methods are available for ascertaining how

much calibration a given M41ST84Y/W may re-

quire.

The first involves setting the clock, lett i ng it run for

a month and comparing it to a known accurate r ef-

erence and r ecor ding dev iation over a fixed period

of time. Calibration values, including the number of

seconds lost or gained in a given period, can be

found in Application Note AN934: TIMEKEEPER

CALIBRATION. This allows the designer to give

the end user the ability to calibrate the clock as the

environment requires, even if the final product is

packaged in a non-user serviceable enclosure.

The designer c ould pr ov ide a simple utility that ac-

cesses the Calibration byte.

The second approach is better suited to a m anu-

facturing environment, and involves the use of the

IRQ/FT/OUT pin. The pin will toggle at 512Hz,

when the Stop Bit (ST, D7 of 01h) is '0,' the Fre-

quency Test Bit (FT, D6 of 08h) is '1,' the Alarm

Flag Enable Bit (AFE, D7 of 0Ah) is '0,' and the

Watchdog Steering Bit (WDS, D7 of 09h) is '1' or

the Watchdog Register (09h = 0) is reset.

Any deviation from 512Hz indicates the degree

and direction of oscillator frequency shift at the test

temperature. For example, a reading of

512.010124Hz would indicate a +20 ppm oscillator

frequency error, requiring a –10 (XX001010) to be

loaded into the Calibration Byte for correction.

Note that setting or changing the Calibration Byte

does not af fect the Frequency test output fr equen-

cy.

The IRQ/FT/OUT pin is an open drain output

which requires a pull-up resistor to VCC for proper

operation. A 500 to 10k resistor is recommended

in order to control the rise time. The FT Bit is

cleared on power-down.

15/31

M41ST84Y, M 41ST84W

Figure 15. Crys tal Accuracy Acro ss Tem p eratur e

Figu re 16 . Cl ock C al ib r at i on

AI00999b

–160

0 10203040506070

Frequency (ppm)

Temperature °C

80–10–20–30–40

–100

–120

–140

–40

–60

–80

–20

∆F= K x (T –T

)

K = –0.036 ppm/°C

± 0.006 ppm/°C

= 25°C ± 5°C

AI00594B

NORMAL

POSITIVE

CALIBRATION

NEGATIVE

CALIBRATION

M41ST84Y, M 41ST84W

16/31

Setting Alarm Clock Registers

Address locations 0Ah-0E h cont ain the alarm se t-

tings. The alarm can be configured to go off at a

prescribed time on a specific month, date, hour,

minute, or second, or repeat every year, month,

day, hour, minute, or second. It can also be pro-

grammed to go off while the M41ST84Y/W is in the

battery back-up to serve as a system wake-up call.

Bits RPT5-RPT1 put the alarm in the repeat mode

of operation. Table 4., page 16 shows the possible

configurations. Codes not listed in the table default

to the once per second mode to quickly alert the

user of an incorrect al arm setting.

When the clock information matches the alarm

clock settings based on the match crit eria d efined

by RPT5-RPT1, the AF (Alarm Flag) is set . If AFE

(Alarm Flag Enable) is also set, the alarm condi-

tion ac tivates the IRQ/FT/OUT pin.

Note: If the address pointer is allowed to incre-

ment to the Flag Registe r ad dress, an alarm con-

dition will not cause the Interrupt/Flag to occur until

the address pointer is moved to a different ad-

dress. It should also be noted that if the last ad-

dress written is the “Alarm Seconds,” the address

pointer will increment to t he F lag address, c ausi ng

this situation to occur.

The IRQ/FT/OUT output is cleared by a READ t o

the Flags Regist er as sho wn in Figure 17. A sub-

sequent READ of the Flags Regist er is necessary

to see that the value of the Alarm Flag has been

re set to '0. '

The IRQ/FT/OUT pin can also be activated in t he

battery back-up mode. The IRQ/FT/OUT will go

low if an alarm occurs and both ABE (Alarm in Bat-

tery Back-up M ode E nable ) and A FE are set . The

ABE and AFE Bits are reset during power-up,

therefore an alarm generated during power-up will

only set AF. The user can read the Flag Register

at system boot-up to determine if an alarm was

generated while t he M41ST84 Y/W was in the de-

select mode during power-up. Figure 18. , page 17

illu strat es the back -up mode ala rm ti ming.

Figure 17. Alarm Interrupt Reset Waveform

Table 4. Alarm Repeat Modes

RPT5 RPT4 RPT3 RPT2 RP T1 A larm Settin g

11111Once per Second

11110Once per Minute

11100Once per Hour

11000Once per Day

10000Once per Month

00000Once per Year

AI03664

IRQ/FT/OUT

ACTIVE FLAG

0Fh0Eh 10h

HIGH-Z

17/31

M41ST84Y, M 41ST84W

Figure 18. Back-Up Mode Alarm Waveform

Watchdog Timer

The watchdog timer can be used to detect an out-

of-control microprocessor. The us er program s the

watchdog timer by setting the desired amount of

time-out into the Watchdog Register, address 09h.

Bits BMB4-BMB0 store a binary mul tiplier and the

two lower order bits RB1-RB0 select the resolu-

tion, where 00 = 1/16 second, 01 = 1/4 second,

10 = 1 second, and 11 = 4 seconds. The amount

of time-out is then determined to be the multiplica-

tion of the five-bit multiplie r value wit h the resolu-

tion. (For example: writing 00001110 in the

Watchdog Register = 3*1, or 3 seconds).

Note: Accuracy of timer is within ± the selected

resolution.

If the processor does not reset the t imer within the

specified period, the M 41ST84Y/W s ets the WDF

(Watchdog Flag) and generates a watchdog i nter-

rupt or a m icroproces sor reset.

The most significa nt bit of the Watchdog Regi ster

is the Watc hdog Steering Bit (WDS). When set to

a '0,' the watchdog will activate the IRQ/FT/OUT

pin when timed-out. When WDS is set to a '1,' the

watchdog will output a negat ive pul se on th e RST

pin for tREC. The Watchdog register, FT, AFE, ABE

and SQWE Bits will reset to a '0' at the end of a

Watchdog time-out when the WDS Bit is set to a

'1.'

The watchdog timer can be reset by two methods:

1) a transition (high-to-low or l ow-to-high) can be

applied to the Wat chdog Input pin (WDI) or 2) the

microprocessor can perform a WRITE of the

Watchdog Register. The time-out period then

starts over.

Note: The WDI pin should be tied to VSS if not

used.

In order to perform a software reset of the wa tch-

dog timer, the original time-out period can be writ-

ten into the Watchdog Register, effectively

res tar ti n g the count- do wn cycle .

Should the wat chdog t imer time-out, and the WDS

Bit is programmed to out put an interrupt, a value of

00h needs to be written to the Watchdog Regi ster

in order t o clear the IRQ/FT/OUT pin. This will also

disable the wat c hdog function until it is agai n pro-

grammed correctly. A READ of the Flags Register

will reset the Watchdog Flag (Bit D7; Register

0Fh).

The watchdog function is automatically disabled

upon power-up and the Watchdog Register is

cleared. If the watchdog function is set to out put to

the IRQ/FT /OU T pin and the F requency Test (FT)

function is activated, the watchdog function pre-

vails and the Frequency Test functio n is denied.

AI03920

VCC

IRQ/FT/OUT

VPFD

ABE, AFE Bits in Interrupt Register

AF bit in Flags Register

HIGH-Z

VSO

HIGH-Z

tREC

M41ST84Y, M 41ST84W

18/31

Square Wave Output

The M41ST84Y/W offers the user a programma-

ble square wave function which is output on the

SQW pin. The RS3-RS0 Bits located in 13h estab-

lish the square wave outpu t frequency. T hese fre-

quencies are listed in Table 5. Once the selection

of the SQW frequency has been completed, the

SQW pin can be turned on and off under software

control with the Square Wave Enable Bit (SQWE )

located in Register 0Ah.

Table 5. Square Wave Output Frequency

Square Wave Bits Square Wave

RS3 RS2 RS1 RS0 Frequency Units

0000None–

0 0 0 1 32.768 kHz

0 0 1 0 8.192 kHz

0 0 1 1 4.096 kHz

0 1 0 0 2.048 kHz

0 1 0 1 1.024 kHz

0110512Hz

0111256Hz

1000128Hz

100164Hz

101032Hz

101116Hz

11008Hz

11014Hz

11102Hz

11111Hz

19/31

M41ST84Y, M 41ST84W

Power-on Reset

The M41ST84Y/W continuously monitors VCC.

When VCC falls to the power fail detect trip point,

the RST pulls low ( open drain) and remai ns low on

power-up for tREC after VCC passes VPFD(max).

The RST pin is an open drain output and an appro-

priate pull-up resistor should be chosen to control

rise time.

Reset Input (RSTIN)

The M41 ST84Y / W provid es an i ndependent input

which can generate an output reset. The durat ion

and function of this reset is identical to a reset gen-

erated by a power cycle. Table 6., page 19 and

Figure 19. , page 19 illustrate the AC reset charac-

teristics of this function. Pulses shorter than tRLRH

will no t ge ne r ate a re se t co n dit io n . RSTIN is inter -

nally pulled up to VCC through a 100kΩ resist o r.

Figure 19. RSTIN Ti ming Waveform

N ote: With pul l - up resi stor

Table 6. Reset AC Characteristics

Note: 1. Vali d for Ambient Operating T em perature: TA = –40 t o 85°C; VCC = 2.7 to 3.6V or 4.5 to 5.5V (except where noted).

2. Pu lse width less than 50ns will result in no RESET (for noise immunity).

3. Pr ogrammable (see Table 8., page 21)

Symbol Parameter(1) Min Max Unit

tRLRH(2) RSTIN Low to RSTIN High 200 ns

tRHRSH(3) RSTIN High to RST High 40 200 ms

AI03682

RST (1)

RSTIN

tRLRH

tRHRSH

M41ST84Y, M 41ST84W

20/31

Power- fail INPUT/OUTPUT

The Power-Fail Input (PFI) is compared to an in-

ternal reference voltage (1.25V) . If PFI is less than

the power-fail threshold (VPFI), the Power-Fail

Output (PF O) wi ll go low. Thi s function is intended

for use as an under-voltage detector to signal a

failing power supply. Typically PFI is connected

through an external voltage divider (see Figure

7., page 6) to either the unregulated DC input (if it

is available) or the regulated output of the VCC reg-

ulator. The voltage divider can be set up such that

the voltage at PFI falls below VPFI several millisec-

onds before the regulated VCC input to the

M41ST84Y /W or the m icroproces sor drops be low

the minimum operating volt age.

During battery bac k-up, the power-fail comparator

turns off and PFO goes (or remai ns) low. This oc-

curs after VCC drops below VPFD(min). When pow-

er returns, PFO is forced high, irrespective of VPFI

for the write protect time (tREC), which is the time

from VPFD(max) until the inputs are recognized. At

the end of this time, the power-fail comparator is

enabled and PF O follows PFI. If the comparator is

unused, PFI should be connected to VSS and PFO

left unconnected.

Century Bit

Bits D7 and D6 of Clock Register 03h contain the

CENTURY ENABLE Bi t (CEB) and the CENTURY

Bit (CB). Setting CEB t o a “1” will cause CB to tog-

gle, eith er from a “0” to “1” or from “1” to “0” at the

turn of the century (depending upon its initial

state). If CEB is set to a “0”, CB will not toggle.

Output Driver Pin

When the FT Bit, AFE Bit and watchdog register

are not set, the IRQ/FT/OUT pin becomes an out-

put driver that reflects the contents of D7 of the

Control Register. In other words, when D7 (OUT

Bit) and D6 (FT Bit ) of address location 0 8h are a

'0,' th en the IRQ/FT/OU T pin w ill b e d riv e n low .

Note: The IRQ/F T/OUT pi n is an open drain which

requires an external pull-up resistor.

Batt ery Lo w W arn in g

The M41ST84Y/ W automatically performs battery

voltage monitoring upo n power-up and at factory-

programmed time intervals of approximately 24

hours. The Battery Low (BL) Bit, Bit D4 of Flags

is found to be less than approximately 2.5V. T he

BL Bit will r emain asserted unt i l completion of bat-

tery replacement and subsequent battery low

monitoring tests, either during the next power-up

sequence or the next scheduled 24-hour interval.

If a battery low is generated during a power-up se-

quence, this indicates that the battery i s below ap-

proximately 2.5 volts and may not be able to

maintain data integrity in the SRAM. Data should

be considered suspect and verified as correct. A

fresh battery should be installed.

If a battery low indication is genera ted d uring the

24-hour interval check, this indicates that the bat-

tery is n ear end of life. Howe ve r, dat a i s not com-

promised due to the fact that a nominal VCC is

supplied. In order to insure data integrity during

subsequent pe riods of bat tery back-up m ode, the

battery should be replaced. The SNAPHAT top

may be replaced while VCC is applied to the de-

vice.

Note: T his will cause the clock to lose time during

the interval the SNAPHAT battery/crystal top is

disconnected.

The M41ST84Y /W only monitors the battery when

a nominal VCC is applied to the device. Thus appli-

cations which require extensive durations in the

battery back- up mode should be powered-up peri-

odically (at least once every few mont hs) in order

for this technique to be beneficial. Addit ionally , if a

battery low is indicated, data integrity should be

verified upon power-up via a checksum or other

technique.

tREC Bit

Bit D7 of Clock Register 04h contains t he tREC Bit

(TR). tREC refers to the automatic continuation of

t h e desele ct ti me af t er VCC reaches VPFD. This al-

lows for a voltage setting time before WRI TEs may

again be performed to the device after a power-

down cond ition. The tREC Bit will allow the user to

set the length of this deselect time as defined by

Table 7. , page 21.

In it ial P o wer - o n Defaul ts

Upon initial application of power to the device, the

following register bit s are set to a '0' st ate: Watch-

dog Register , TR, F T, AFE , ABE, and SQ WE. The

following bits are set to a '1' state: ST, OU T, and

HT (see T able 8. , page 21 ).

21/31

M41ST84Y, M 41ST84W

Table 7. tREC Definitions

Note: 1. Default Setting

Table 8. Default Values

No te: 1. WDS, BMB0-B MB4, RB0, RB1.

2. State of other cont rol bits undefi ned.

3. UC = Unchanged

MAXI MUM RAT IN G

Stressing the device ab ove t he rating listed in t he

“Absolute Maximum Ratings” table may cause

permanent damage to the device. These are

stress ratings only and operation of the device at

these or any other conditions above those indicat-

ed in the Oper ating sections of this specification is

not impl ied. Exposure to Absol ute Max imum Ra t-

ing conditions for extended periods may affect de-

vice reliability. Refer also to the

STMicroelectronics S URE P rogram and other rel-

evant quality documents.

Table 9. Absolute Maximum Ratings

Note: 1. For SO package, standard (S nP b) lead fini sh: Reflow at peak temperature of 2 25°C (tot al therm al budget not to exceed 180°C for

betw ee n 90 to 150 second s ).

2. For SO pac kage, Lead-free (P b-f ree) l ead fini sh: Refl ow at peak tem perature of 260°C (t otal thermal budge t n ot to exceed 245°C

fo r greater than 30 seconds).

CAUTION: N egative undershoots be l ow –0.3V a re not allowe d on a ny pin while i n t he Battery B ack-up mode.

CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT so ckets.

tREC Bit (TR) STOP Bi t (ST) tREC Time Units

Min Max

009698ms

0140

200(1) ms

1 X 50 2000 µs

Condition TR ST HT Out FT AFE ABE SQWE WATCHDOG

Initial Po wer-up

(Battery Attach for SNAPHAT)(2) 0111000 0 0

Subsequent Power-up (with

battery back-up)(3) UC UC 1 UC 0 0 0 0 0

Symbol Parameter Value Unit

TSTG Storage Temperature (VCC Off, Oscillator Off) SNAPHAT®–40 to 85 °C

SOIC –55 to 125 °C

TSLD (1) Lead Solder Temperature for 10 seconds 260 °C

VIO Input or Output Voltages –0.3 to VCC + 0.3 V

VCC Supply Vo ltage M41ST84Y –0.3 to 7.0 V

M41ST84W –0.3 to 4.6 V

IOOutput Current 20 mA

PDPower Dissipation 1 W

M41ST84Y, M 41ST84W

22/31

DC AND A C PARAMETE RS

This section summarizes the operating and mea-

surement conditions, as well as the DC and AC

characteristics of the device. The parameters in

the following DC and AC Charact eristic tables are

derived from tests pe rform ed under the Measure-

ment Condition s listed in the relevant tables. De-

signers should check that the operating conditions

in their projects match the measurement condi-

tions when using the quoted parameters.

Table 10. D C and AC Measurem ent Conditions

Note: Output Hi -Z is defi ned as the poin t where dat a i s n o l onger driven.

Figure 20. AC Testing Input/Output Waveforms

Note: 50pF for M 41ST84W.

Table 11. Capacitanc e

Note: 1. Effective c apacitance measured wi t h power supply at 5V. Samp l ed only, not 100% tes ted.

2. At 25°C, f = 1MHz.

3. Out puts desel ected .

Parameter M41ST84Y M41ST84W

VCC Supply Voltage 4.5 to 5.5V 2.7 to 3.6V

Ambient Operating Temperature –40 to 85°C –40 to 85°C

Load Capacitance (CL)100pF 50pF

Input Rise and Fall Times ≤ 50ns ≤ 50ns

Input Pulse Voltages 0.2 to 0.8VCC 0.2 to 0.8VCC

Input and Output Timing Ref. Voltages 0.3 to 0.7VCC 0.3 to 0.7VCC

AI02568

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Symbol Parameter(1,2) Min Max Unit

CIN Input Capacitance 7 pF

CIO(3) Input / Output Capacitance 10 pF

tLP Low-pass filter input time constant (SDA and SCL) 50 ns

23/31

M41ST84Y, M 41ST84W

Table 12. DC Characteristics

Note: 1. Vali d for Ambient Operating T em perature: TA = –40 t o 85°C; VCC = 2.7 to 3.6V or 4.5 to 5.5V (except where noted).

2. RSTIN internally pulled-up to VCC through 100KΩ resi st or. WDI in te rnally pulled- down to VSS through 100KΩ resistor.

3. Out puts desel ected .

4. For PFO an d S Q W pi ns (CMOS).

5. For IRQ/FT/OUT, RST pins ( O pen Dr ain ): i f p ul led -up to supp ly oth e r t han V CC, th is su ppl y mu st be e qual t o, or l ess th an 3. 0V wh en

VCC = 0V (during batter y back-u p m ode).

6. For rechargeabl e back-u p, VBAT (max) may be consi dered V CC.

Table 13. Crystal Electrical Characteristics (Externally Supplied)

Note: 1. Load capacitors are in tegrat ed withi n the M41ST84Y/ W. Ci rcuit board la yout con siderations for the 32.76 8kHz cr ys tal of minimum

trac e l engths an d i solation from RF generating signal s should be taken int o account.

2. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning Fork Type (thru-hole) or the DMX-26S:

1TJ S1 25FH2 A212, (SM D) quart z crystal f or indust ri al te mperat ure operations. KDS can be contacted a t k ouhou@k dsj.co.jp or ht -

tp://www.kdsj.co.jp for further information on this crystal type.

Sym Parameter Test

Condition(1) M41ST84Y M41ST84W Unit

Min Typ Max Min Typ Max

IBAT

Battery Current OSC

ON TA = 25°C,

VCC = 0V,

VBAT = 3V

400 500 400 500 nA

Battery Current OSC

OFF 50 50 nA

ICC1 Supply Current f = 400kHz 1.4 0.75 mA

ICC2 Supply Curre nt

(Standby) SCL, SDA =

VCC – 0.3V 10.50mA

ILI(2) Input Leakage Current 0V ≤ VIN ≤ VCC ±1 ±1 µA

Input Leakage Current

(PFI) –25 2 25 –25 2 25 nA

ILO(3) O utput Leak age

Current 0V ≤ VOUT ≤ VCC ±1 ±1 µA

VIH Input High Voltage 0.7VCC VCC + 0.3 0.7VCC VCC + 0.3 V

VIL Input Low Voltage –0.3 0.3VCC –0.3 0.3VCC V

VBAT Battery Voltage 2.5 3.0 3.5(6) 2.5 3.0 3.5(6) V

VOH Output High Volta ge(4) IOH = –1. 0mA 2.4 2.4 V

VOL

Output Low Vo ltage IOL = 3.0mA 0.4 0.4 V

Output Low Vo ltage

(Open Drain)(5) IOL = 10mA 0.4 0.4 V

Pull-up Supply Voltage

(Open Drain) RST,

IRQ/FT/OUT 5.5 3.6 V

VPFD Power Fail Deselect 4.20 4.40 4.50 2.55 2.60 2.70 V

VPFI PFI Input Threshold VCC = 5V(Y)

VCC = 3V(V) 1.225 1.250 1.275 1.225 1.250 1.275 V

PFI Hysteresis PFI Rising 20 70 20 70 mV

VSO Battery Back-up

Switchover 2.5 2.5 V

Symbol Parameter(1,2) Typ Min Max Unit

f0Resonant Frequency 32.768 kHz

RSSeries Resistance 50 kΩ

CLLoad Capacitance 12.5 pF

M41ST84Y, M 41ST84W

24/31

Figure 21. Power Down /U p Mode AC Waveform s

Table 14. Power Down/U p AC Characteri stics

Note: 1. Vali d for Ambient Operating T em perature: TA = –40 t o 85°C; VCC = 2.7 to 3.6V or 4.5 to 5.5V (except where noted).

2. VPFD(max) to VPFD(min) fall time of less than tF may result in deselection/wri te prot ection not occurring until 200µs after VCC passes

VPFD(min).

3. VPFD( min) to VSS fall time of less than tFB may cause cor ruption of RAM dat a.

4. Pr ogrammable (see Table 7., page 21)

5. At 25°C (when using SOH28 + M4T28-BR12SH SNAPHAT top); VCC = 0V.

Symbol Parameter(1) Min Typ Max Unit

tF(2) VPFD(max) to VPFD(min) VCC Fall T ime 300 µs

tFB(3) VPFD(min) to VSS VCC Fall Time 10 µs

tPFD PFI to PFO Propagation Delay 15 25 µs

tRVPFD(min) to VPFD(max) VCC Rise Time 10 µs

tRB VSS to VPFD(min) VCC Rise Time 1µs

tREC(4) Power up Deselect Time 40 200 ms

tDR(5) Expected Data Retention Time 10 YEARS

AI03681

VCC

INPUTS

(PER CONTROL INPUT)

OUTPUTS

DON'T CARE

HIGH-Z

tF tFB tR

tRB

tDR

VALID VALID

(PER CONTROL INPUT)

RECOGNIZEDRECOGNIZED

VPFD (max)

VPFD (min)

VSO

tREC

RST

PFO

25/31

M41ST84Y, M 41ST84W

P ACKAGE ME CHANICA L INFORMAT ION

Figure 22. SO16 – 16-lead Plas tic Small Outline, Packag e Outline

No te : Drawing is not to scal e.

Table 15. SO16 – 16-lead Plastic Small Outline, Package Mechanical Data

Symbol mm inches

Typ. Min. Max. Typ. Min. Max.

A 1.75 0.069

A1 0.10 0.25 0.004 0.010

A2 1.60 0.063

B 0.35 0.46 0.014 0.018

C 0.19 0.25 0.007 0.010

D 9.80 10.00 0.386 0.394

E 3.80 4.00 0.150 0.158

e1.27––0.050––

H 5.80 6.20 0.228 0.244

L 0.40 1.27 0.016 0.050

a0°8°0°8°

N16 16

CP 0.10 0.004

SO-b

LA1 α

M41ST84Y, M 41ST84W

26/31

Figure 23. SOH28 – 28-lead Plastic Smal l Outline, Battery SNAPHAT, P ackage Outl ine

No te : Drawing is not to scal e.

Table 16. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Pac kage Mecha nical Data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 3.05 0.120

A1 0.05 0.36 0.002 0.014

A2 2.34 2.69 0.092 0.106

B 0.36 0.51 0.014 0.020

C 0.15 0.32 0.006 0.012

D 17.71 18.49 0.697 0.728

E 8.23 8.89 0.324 0.350

e1.27– –0.050– –

eB 3.20 3.61 0.126 0.142

H 11.51 12.70 0.453 0.500

L 0.41 1.27 0.016 0.050

α0° 8° 0° 8°

N 28 28

CP 0.10 0.004

SOH-A

LA1 α

27/31

M41ST84Y, M 41ST84W

Figure 24. SH – 4-pin SNAPHAT Ho using for 48mAh Batter y & Crystal, Package Outline

No te : Drawing is not to scal e.

Table 17. SH – 4-pin S NAPHAT Housing for 48mA h Bat tery & Crystal , Package Mechanical Data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 9.78 0.3850

A1 6.73 7.24 0.2650 0.2850

A2 6.48 6.99 0.2551 0.2752

A3 0.38 0.0150

B 0.46 0.56 0.0181 0.0220

D 21.21 21.84 0.8350 0.8598

E 14.22 14.99 0.5598 0.5902

eA 15.55 15.95 0.6122 0.6280

eB 3.20 3.61 0.1260 0.1421

L 2.03 2.29 0.0799 0.0902

SHTK-A

A1 A

M41ST84Y, M 41ST84W

28/31

Figure 25. SH – 4-pin SNA P HAT Housi ng fo r 120mAh Batt ery & Crystal, Package Outl ine

No te : Drawing is not to scal e.

Table 18. SH – 4-pin SNAPH AT Housi n g for 120mAh Bat tery & Cr yst al, P ackage Mech. Data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 10.54 0.4150

A1 6.73 7.24 0.2650 0.2850

A2 6.48 6.99 0.2551 0.2752

A3 0.38 0.0150

B 0.46 0.56 0.0181 0.0220

D 21.21 21.84 0.8350 0.8598

E 14.22 14.99 0.5598 0.5902

eA 15.55 15.95 0.6122 0.6280

eB 3.20 3.61 0.1260 0.1421

L 2.03 2.29 0.0799 0.0902

SHTK-A

A1 A

29/31

M41ST84Y, M 41ST84W

PART NUMBERING

Table 19. Ordering Information Scheme

Note : 1. The 2 8- pin S OIC pa ckag e (SO H2 8) req uire s the SNA PH AT ® batte ry/c rys tal pac k age w h ich i s ord er ed sep ar ately und er th e part

number “M4T XX-BR12SH X” in plastic tube or “M 4T X X-BR12SHX T R” in Tape & Reel form (see Table 20).

2. Co nta ct Lo cal Sal es Of fice

Caution: Do not place the SNAPHAT battery package “M4TXX-BR12SH” in conductive foam as it will drain the lithium button-cell bat-

tery.

For other options, or for more information on any aspect of this device, please contact the ST Sales Of fice

nearest you.

Table 20. SNAPHAT Battery Table

Example: M41ST 84Y MQ 6 E

Device Type

M41ST

Supply Voltage and Write Protect Voltage

84Y = VCC = 4.5 to 5.5V; 4.20V ≤ VPFD ≤ 4.50V

84W = VCC = 2.7 to 3.6V; 2.55V ≤ VPFD ≤ 2.70V

Package

MQ = SO16

MH(1,2) = SOH28

Temperature Range

6 = –40 to 85°C

Shipping Method

For SO16:

blank = Tubes (Not for New Design - Use E)

E = Lead-free Package (ECO PACK®), Tubes

F = Lead-free Package (ECO PACK®), Tape & Reel

TR = Tape & Reel (Not for New Design - Use F)

For SOH28:

blank = Tubes (Not for New Design - Use E)

E = Lead-free Package (ECO PACK®), Tubes

F = Lead-free Package (ECO PACK®), Tape & Reel

TR = Tape & Reel (Not for New Design - Use F)

Part Number Description Package

M4T28-BR12SH Lithium Battery (48mAh) and Crystal SNAPHAT SH

M4T32-BR12SH Lithium Battery (120mAh) and Crystal SNAPHAT SH

M41ST84Y, M 41ST84W

30/31

REVISION HISTORY

Table 21. Document Revi sion History

M41ST84 , M41ST84Y, M41ST 84W, 41ST84, ST84, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVI-

SOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, Serial, Seria l, Serial, Serial, Serial, Serial, Serial, Serial,

Serial, Serial, Serial , Serial, Seri al, Serial, Serial, Serial, Serial, Serial , Serial, Serial, Serial, Serial, Serial, Serial , Serial, Serial , Serial, Serial, Serial, Serial, Serial , Serial, Serial, Serial, Serial, Serial, Serial, Serial ,

Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, RTC, RTC, RT C, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC,

RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RT C, RTC, RTC, RTC, RT C, RTC, RTC, RTC, RTC, RT C, RTC, RTC, RTC, RT C, RTC, RTC, RTC, RT C, RTC, RTC, RTC, RTC, RT C, RTC, RTC, RTC,

RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RT C, RTC, RTC, R TC, RTC, RTC, RTC, RTC, RTC, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Micro-

processor, Microprocessor, Microprocessor, M icroprocessor, Microprocesso r, Microprocessor, Micro processor, Microprocess or, Microprocessor, M icroprocesso r, Microprocessor, Mi croprocessor, Microproce s-

sor , M i cr oprocessor, Micr op r ocessor, Mi cr oprocessor, Micr op r ocessor, Mi cr oprocessor, Microprocessor , M i cr oprocessor, I 2C, I 2C , I2C, I2C, I2C, I2C, I2C , I2C, I2C , I2C, I2C, I2C, I2C, I2C , I2C, I2C, I2C, I2C,

I2C, I2C, I2C, I2C, I2C, I2 C, I2C, I2C, I2C , I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C , I2 C, I2C, I2C, I2C , I2C, I2C, I2C, I2C, I2C, I2C , Os cillator, Oscillator, O scillator, O scillator, Oscilla tor,

Oscillator, Osci llator, Oscillator, Oscillator, Oscillator, Oscillator, Oscill ator, Oscillator, Oscillator, Oscillator, Oscillator, Oscill a tor, Oscilla tor, Oscillator, Oscillator, Os cillator, Oscillator, Oscilla tor, Oscillator, Oscil-

lator, Osc illa tor, Oscillator, Osc illator, Oscillator, Oscillator, Oscilla tor, O scillator, Oscilla tor, Oscillator, Oscill ator, Os cillator, Oscillato r, Oscilla tor, Oscillator, Oscillator, Crystal, Crystal, Crystal, Crystal, Crystal,

Crystal, Crystal, Crystal, Crystal, Crystal, Crysta l, Crysta l, Crysta l, Crysta l, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal , Cry stal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal,

Crystal, Crystal, Cry stal, Crystal, Crystal, Alarm , Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Ala rm, Alarm, Alarm, Alarm , Alarm, Alarm, Alarm , Alarm, Alarm, Alarm, Alarm, Alarm,

Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm , Alarm, Alarm, Alarm, Ala rm, A larm , A larm, Alarm, Ala rm, A larm, Alarm, A larm, Alarm, Ala rm, A larm,

Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ,

IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IR Q, IRQ, IRQ, IRQ , IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IR Q, PF I, PFI, PFI, PFI, PFI, PFI, PFI,

PFI, PFI, PFI, PFI, PFI, PFI, PFI, PF I, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO,

PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, Ba ttery, Batt ery , Batter y, Batt ery, Ba tter y, Battery , Battery, Batt ery, Ba tte ry, Battery, Ba tte ry, Battery, Ba tte ry, Batt ery,

Battery, Battery, Ba ttery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Ba ttery, Battery, Battery, Batt ery, Battery, Batt ery, Battery , Battery, Batt ery, Battery , Battery, Batt ery, Batt ery, Battery,

Ba t tery, S wi t c hover, Sw itchover, S wi t c hover, Sw itchover, S wi tchove r , Sw itchover, S wi tchove r , Sw itchover, Sw i tchove r , Sw itchover, Sw i tchove r , Sw itchover, Sw i tchove r , Sw itchover, Sw it chove r , Backup , Backup ,

Backup, Backup, Backup, Bac kup, Bac kup, Backup , Backup, Backup, Backup, Backup, Backup, Backup, Bac kup, Backup, Ba ckup, Backup, Backup, Ba ckup, Backup, Backup, Backup, Bac kup, Backup , Write

Protect, Write Protect, Write Protect, Write Protect, W rite Protect, W rite Protect, Write Protect, Write Protect, Write Protec t, Write Protec t, Write Protect, Write Protect, Write Protect, W rite Protect, Write Protect,

Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write

Pr ote ct, Power-fai l, Po wer- fail, Power- fa il, Power-fail, Power-fa il, Power-fa il, Power -fail, Po wer-f a il, Power-fai l, Power-fail , Po wer-f a il, Power-fai l, Po wer- fail, Power- fa il, Power-fai l, Co mpara tor, Comparator , Com-

parator, Com parator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator,

Co mp ar ator, Comp ar ator, Compa r ator, C om parato r , Comparator, Comp ar a t or , Compa r at o r , Compa r at o r , C omparat or , Co mp ar a t or , Compa r ator, Comparator, Comparator, Comparator, Comparator, Comparator,

Co mp ar ator, Compa r at o r , C om pa r ator, C omparat or , Comparato r , Com pa rator, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, S NAPHAT, SNAPHAT, SNAPHAT, SNAPHAT ,

SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT,

SNAPHAT, SNAPHAT, SNAPHAT, SNAP HAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT , SNAPHAT, SNAPHAT, SNAPHAT , SOIC , SOIC, SO IC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC,

SOIC, SOIC, SOIC, SOIC, SOIC, SO IC, SOIC, SOIC, SOIC, SOIC, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V,

5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V

Date Rev. # Revision Details

August 2000 1.0 First Issue

24-Aug-00 1.2 Block Diagram added (Figure 6)

08-Sep-00 1.3 SO16 package measures change

18-Dec-00 2.0 Reformatted, TOC added, and PFI Input Leakage Current added (Table 12)

18-Jun-01 2.1

Addition of tREC information, table changed, one added (Tables 3, 7); changes to PFI/PFO

graphic (see Figure 6); change to DC and AC Characteristics, Order Information (Tables 12, 2,

19); note added to “Setting Alarm Clock Registers” section; added temp./v oltage info . to tables

(Table 11, 12, 13, 2, 14); addition of Default Values (Table 8); textual improvements

25-Jun-01 2.2 Special note added in CLOCK OPERATION, page 12

26-Jul-01 3.0 Change in Product Matu rity

07-Aug-01 3.1 Improve text for “Setting the Alarm Clock” section

20-Aug-01 3.2 Ch ange VPFD values in document

06-Sep-01 3.3 DC Characteristics VBAT changed; PFI Hysteresis (PFI Rising) spec. added; and Crystal

Electrical Characteristics Series Resistance spec. changed (Tables 12, 13)

03-Dec-01 3.4 Change READ/WRITE Mode Sequence drawings (Figure 12, 14); change in VPFD lowe r limit

for 5V (M41ST84Y) part only (Table 12, 19)

14-Jan- 02 3.5 Change Series Resist ance (Table 13)

01-May-02 3.6 Change tREC Definition (Table 7); modify reflow time and temperature footnote (Table 9)

03-Jul-02 3.7 Modify DC and Crystal Electrical Characteristics footnotes, Default Values (Tables 12, 13, 8)

01-Aug-02 3.8 Add marketing status (Figure 2; Table 19)

16-Jun-03 4.0 New Si changes (Table 14, 6, 7, 8)

15-Jun-04 5.0 Reformatted; added Lead-free information; update characteristics (Figure 15; Table 9, 12, 19)

18-Oct-04 6.0 Add Marketing Status (Figure 2; Table 19)

31/31

M41ST84Y, M 41ST84W

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