NCV887301D1R2G - ON SEMICONDUCTOR

September, 2019 − Rev. 10

1Publication Order Number:

NCV8873/D

Automotive Grade

Non-Synchronous Boost

Controller

NCV8873

The NCV8873 is an adjustable output non−synchronous boost

controller which drives an external N−channel MOSFET. The device

uses peak current mode control with internal slope compensation. The

IC incorporates an internal regulator that supplies charge to the gate

driver.

Protection features include internally−set soft−start, undervoltage

lockout, cycle−by−cycle current limiting and thermal shutdown.

Additional features include low quiescent current sleep mode and

externally−synchronizable switching frequency.

Features

•Peak Current Mode Control with Internal Slope Compensation

•0.2 V $3% Reference Voltage for Constant Current Loads

•Fixed Frequency Operation

•Wide Input Voltage Range of 3.2 V to 40 V, 45 V Load Dump

•Input Undervoltage Lockout (UVLO)

•Internal Soft−Start

•Low Quiescent Current in Sleep Mode

•Cycle−by−Cycle Current Limit Protection

•Thermal Shutdown (TSD)

•This is a Pb−Free Device

•NCV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

MARKING

DIAGRAM

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SOIC−8

D SUFFIX

CASE 751

PIN CONNECTIONS

1 8

(Top View)

EN/SYNC

ISNS

GND

GDRV

VFB

VIN

VDRV

8873xx = Specific Device Code

xx = 00, 01 or 02

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G= Pb−Free Package

8873xx

ALYW

Device Package Shipping†

ORDERING INFORMATION

NCV887300D1R2G SOIC−8

(Pb−Free)

2500 / Tape &

Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

NCV887301D1R2G SOIC−8

(Pb−Free)

2500 / Tape &

Reel

NCV887302D1R2G SOIC−8

(Pb−Free)

2500 / Tape &

Reel

NCV8873

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Gm 8

GND

ISNS

GDRV

VIN

VFB

5VDRV

CSA

OSC Q

MURA110T3G

TEMP

VDRV

DRIVE

LOGIC

FAULT

LOGIC

CLK

EN/SYNC

EN/

SYNC

PWM

RSNS

RF1

Vref

CDRV

Figure 1. Simplified Block Diagram and Example Application Schematic

NVTFS5826NL

PACKAGE PIN DESCRIPTIONS

Pin No.

Symbol Function

1 EN/SYNC Enable and synchronization input. The falling edge synchronizes the internal oscillator. The part is disabled

into sleep mode when this pin is brought low for longer than the enable time−out period.

2 ISNS Current sense input. Connect this pin to the source of the external N−MOSFET, through a current−sense

resistor to ground to sense the switching current for regulation and current limiting.

3 GND Ground reference.

4 GDRV Gate driver output. Connect to gate of the external N−MOSFET. A series resistance can be added from

GDRV to the gate to tailor EMC performance. An RGND = 15 kW (typical) GDRV−GND resistor is strongly

recommended.

5 VDRV Driving voltage. Internally−regulated supply for driving the external N−MOSFET, sourced from VIN. Bypass

with a 1.0 mF ceramic capacitor to ground.

6 VIN Input voltage. If bootstrapping operation is desired, connect a diode from the input supply to VIN, in addi-

tion to a diode from the output voltage to VDRV and/or VIN.

7 VC Output of the voltage error amplifier. An external compensator network from VC to GND is used to stabilize

the converter.

8 VFB Output voltage feedback. A resistor from the output voltage to VFB with another resistor from VFB to GND

creates a voltage divider for regulation and programming of the output voltage.

NCV8873

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ABSOLUTE MAXIMUM RATINGS (Voltages are with respect to GND, unless otherwise indicated)

Rating Value Unit

Dc Supply Voltage (VIN) −0.3 to 40 V

Peak Transient Voltage (Load Dump on VIN) 45 V

Dc Supply Voltage (VDRV, GDRV) 12 V

Peak Transient Voltage (VFB) −0.3 to 6 V

Dc Voltage (VC, VFB, ISNS) −0.3 to 3.6 V

Dc Voltage (EN/SYNC) −0.3 to 6 V

Dc Voltage Stress (VIN − VDRV)* −0.7 to 40 V

Operating Junction Temperature −40 to 150 °C

Storage Temperature Range −65 to 150 °C

Peak Reflow Soldering Temperature: Pb−Free, 60 to 150 seconds at 217°C265 peak °C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

*An external diode from the input to the VIN pin is required if bootstrapping VDRV and VIN off of the output voltage.

PACKAGE CAPABILITIES

Characteristic Value Unit

ESD Capability (All Pins) Human Body Model

Machine Model

w2.0

w200

Moisture Sensitivity Level 1

Package Thermal Resistance Junction−to−Ambient, RqJA (Note 1) 100 °C/W

1. 1 in2, 1 oz copper area used for heatsinking.

Ordering Options

The NCV8873 features several variants to better fit a

multitude of applications. The table below shows the typical

values of parameters for the parts that are currently

available.

TYPICAL VALUES

YY Dmax fstss SaVcl Isrc Isink VDRV

NCV887300 86.5% 1000 kHz 1.6 ms 130 mV/ms400 mV 800 mA 600 mA 6.3 V

NCV887301 87.5% 400 kHz 4.0 ms 30 mV/ms200 mV 800 mA 600 mA 6.3 V

NCV887302 92.5% 400 kHz 4.0 ms 51 mV/ms200 mV 800 mA 600 mA 6.3 V

DEFINITIONS

Symbol Characteristic Symbol Characteristic Symbol Characteristic

Dmax Maximum duty cycle fsSwitching frequency tss Soft−start time

SaSlope compensating ramp Vcl Current limit trip voltage Isrc Gate drive sourcing current

Isink Gate drive sinking current VDRV Drive voltage

NCV8873

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ELECTRICAL CHARACTERISTICS (−40°C < TJ < 150°C, 3.2 V < VIN < 40 V, unless otherwise specified) Min/Max values are

guaranteed by test, design or statistical correlation.

Characteristic Symbol Conditions Min Typ Max Unit

GENERAL

Quiescent Current, Sleep Mode Iq,sleep VIN = 13.2 V, EN = 0, TJ = 25°C−2.0 −mA

Quiescent Current, Sleep Mode Iq,sleep VIN = 13.2 V, EN = 0, −40°C < TJ < 125°C−2.0 6.0 mA

Quiescent Current, No switching Iq,off Into VIN pin, EN = 1, No switching −1.5 2.5 mA

Quiescent Current, Switching,

normal operation

Iq,on Into VIN pin, EN = 1, Switching −4.0 6.0 mA

OSCILLATOR

Minimum pulse width ton,min 90 115 140 ns

Maximum duty cycle Dmax YY = 00

YY = 01

YY = 02

86.5

87.5

92.5

Switching frequency fsYY = 00

YY = 01

YY = 02

900

360

1000

400

1100

440

kHz

Soft−start time tss From start of switching with VFB = 0 until

reference voltage = VREF

YY = 00

YY = 01

YY = 02

1.3

3.3

1.6

4.0

1.9

4.7

Soft−start delay tss,dly From EN → 1 until start of switching with

VFB = 0 with floating VC pin −240 280

Slope compensating ramp SaYY = 00

YY = 01

YY = 02

114

130

146

mV/ms

ENABLE/SYNCHRONIZATION

EN/SYNC pull−down current IEN/SYNC VEN/SYNC = 5 V −5.0 10 mA

EN/SYNC input high voltage Vs,ih VIN > VUVLO 2.0 −5.0 V

EN/SYNC input low voltage Vs,il 0−800 mV

EN/SYNC time−out ratio %ten From SYNC falling edge, to oscillator con-

trol (EN high) or shutdown (EN low), Per-

cent of typical switching frequency

− − 350 %

SYNC minimum frequency ratio %fsync,min Percent of fs− − 80 %

SYNC maximum frequency fsync,max 1.1 − − MHz

Synchronization delay ts,dly From SYNC falling edge to GDRV falling

edge under open loop conditions.

−50 100 ns

Synchronization duty cycle Dsync 25 −75 %

CURRENT SENSE AMPLIFIER

Low−frequency gain Acsa Input−to−output gain at dc, ISNS v 1 V 0.9 1.0 1.1 V/V

Bandwidth BWcsa Gain of Acsa − 3 dB 2.5 − − MHz

ISNS input bias current Isns,bias Out of ISNS pin −30 50 mA

Current limit threshold voltage Vcl Voltage on ISNS pin

YY = 00

YY = 01

YY = 02

360

180

400

200

440

220

Current limit,

Response time

tcl CL tripped until GDRV falling edge,

VISNS = Vcl(typ) + 60 mV

−80 125 ns

Overcurrent protection,

Threshold voltage

%Vocp Percent of Vcl 125 150 175 %

NCV8873

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ELECTRICAL CHARACTERISTICS (−40°C < TJ < 150°C, 3.2 V < VIN < 40 V, unless otherwise specified) Min/Max values are

guaranteed by test, design or statistical correlation.

Characteristic UnitMaxTypMinConditionsSymbol

CURRENT SENSE AMPLIFIER

Overcurrent protection,

Response Time

tocp From overcurrent event, Until switching

stops, VISNS = VOCP + 40 mV

−80 125 ns

VOLTAGE ERROR OPERATIONAL TRANSCONDUCTANCE AMPLIFIER

Transconductance gm,vea VFB – Vref = ± 20 mV 0.8 1.2 1.63 mS

VEA output resistance Ro,vea 2.0 − − MW

VFB input bias current Ivfb,bias Current out of VFB pin −0.5 2.0 mA

Reference voltage Vref 0.194 0.200 0.206 V

VEA maximum output voltage Vc,max 2.5 − − V

VEA minimum output voltage Vc,min − − 0.3 V

VEA sourcing current Isrc,vea VEA output current, Vc = 2.0 V 80 100 −mA

VEA sinking current Isnk,vea VEA output current, Vc = 0.7 V 80 100 −mA

GATE DRIVER

Sourcing current Isrc VDRV ≥ 6 V, VDRV − VGDRV = 2 V

YY = 00

YY = 01

YY = 02

600

800

−

Sinking current Isink VGDRV ≥ 2 V

YY = 00

YY = 01

YY = 02

500

600

−

Driving voltage dropout Vdrv,do VIN − VDRV, IvDRV = 25 mA −0.3 0.6 V

Driving voltage source current Idrv VIN − VDRV = 1 V 35 45 −mA

Backdrive diode voltage drop Vd,bd VDRV − VIN, Id,bd = 5 mA − − 0.7 V

Driving voltage VDRV IVDRV = 0.1 − 25 mA

YY = 00

YY = 01

YY = 02

6.0

6.3

6.6

UVLO

Undervoltage lock−out,

Threshold voltage

Vuvlo VIN falling 2.95 3.05 3.15 V

Undervoltage lock−out,

Hysteresis

Vuvlo,hys VIN rising 50 150 250 mV

THERMAL SHUTDOWN

Thermal shutdown threshold Tsd TJ rising 160 170 180 °C

Thermal shutdown hysteresis Tsd,hys TJ falling 10 15 20 °C

Thermal shutdown delay tsd,dly From TJ > Tsd to stop switching − − 100 ns

NCV8873

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TYPICAL PERFORMANCE CHARACTERISTICS

010203040

VIN, INPUT VOLTAGE (V)

Figure 2. Sleep Current vs. Input Voltage

Iq,sleep, SLEEP CURRENT (mA)

TJ = 25°C

Figure 3. Sleep Current vs. Temperature

−40 10 60 110 160

TJ, JUNCTION TEMPERATURE (°C)

Figure 4. Quiescent Current vs. Temperature

ton,min MINIMUM ON TIME (ns)

TJ, JUNCTION TEMPERATURE (°C)

Figure 5. Minimum On Time vs. Temperature

−40 10 60 110 16

TJ, JUNCTION TEMPERATURE (°C)

Figure 6. Normalized Current Limit vs.

Temperature

−40 10 60 110 160

NORMALIZED CURRENT LIMIT (25°C) Iq,on, QUIESCENTCURRENT (mA)

TJ, JUNCTION TEMPERATURE (°C)

Figure 7. Reference Voltage vs. Temperature

Vref, REFERENCE VOLTAGE (V)

−40 10 60 110 16

−50 0 50 100 20

Iq,sleep, SLEEP CURRENT (mA)

VIN = 13.2 V

150

TJ, JUNCTION TEMPERATURE (°C)

4.3

4.4

4.5

4.6

4.7

4.8

4.9

0.990

0.995

1.000

1.005

1.010

201.2

201.4

201.6

201.8

202.2

202

115

117

119

121

125

123

VIN = 13.2 V

4.1

4.2

1.0 MHz

400 kHz

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TYPICAL PERFORMANCE CHARACTERISTICS

Figure 8. Enable Pulldown Current vs. Voltage

TJ, JUNCTION TEMPERATURE (°C)

Figure 9. Enable Pulldown Current vs.

Temperature

Ienable, PULLDOWN CURRENT (mA)

01234

Venable, VOLTAGE (V)

Ienable, PULLDOWN CURRENT (mA)

TJ = 25°C

56 −40 10 60 110 16

5.0

5.5

6.0

6.5

7.0

7.5

8.0

NCV8873

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THEORY OF OPERATION

Figure 10. Current Mode Control Schematic

CSA

Slope

Compensation

PWM

Comparator

Compensation

NCV8873

Gate

Driver

ISNS

GDRV

RF1

VFB

Oscillator

RSNS

VREF

Current Mode Control

The NCV8873 incorporates a current mode control

scheme, in which the PWM ramp signal is derived from the

power switch current. This ramp signal is compared to the

output of the error amplifier to control the on−time of the

power switch. The oscillator is used as a fixed−frequency

clock to ensure a constant operational frequency. The

resulting control scheme features several advantages over

conventional voltage mode control. First, derived directly

from the inductor, the ramp signal responds immediately to

line voltage changes. This eliminates the delay caused by the

output filter and error amplifier, which is commonly found

in voltage mode controllers. The second benefit comes from

inherent pulse−by−pulse current limiting by merely

clamping the peak switching current. Finally, since current

mode commands an output current rather than voltage, the

filter offers only a single pole to the feedback loop. This

allows for a simpler compensation.

The NCV8873 also includes a slope compensation

scheme in which a fixed ramp generated by the oscillator is

added to the current ramp. A proper slope rate is provided to

improve circuit stability without sacrificing the advantages

of current mode control.

Current Limit

The NCV8873 features a peak current−mode current limit

protection. When the current sense amplifier detects a

voltage above the peak current limit between ISNS and

GND after the current limit leading edge blanking time, the

peak current limit causes the power switch to turn off for the

remainder of the cycle. Set the current limit with a resistor

from ISNS to GND, with R = VCL / Ilimit.

If the voltage across the current sense resistor exceeds the

over current threshold voltage the part enters soft−start

mode.

EN/SYNC

This pin has three modes. When a dc logic high

(CMOS/TTL compatible) voltage is applied to this pin the

NCV8873 operates at the programmed frequency. When a

dc logic low voltage is applied to this pin the NCV8873

enters a low quiescent current sleep mode. When a square

wave of at least %fsync,min of the free running switching

frequency is applied to this pin, the switcher operates at the

same frequency as the square wave. If the signal is slower

than this, it will be interpreted as enabling and disabling the

part. The falling edge of the square wave corresponds to the

start of the switching cycle. If an Enable command is

received during normal operation, the minimum duration of

the Enable low−state must be greater than 7 clock cycles.

If the VIN pin voltage falls below VUVLO when

EN/SYNC pin is at logic−high, the IC may not power up

when VIN returns back above the UVLO. To resume a

normal operating state, the EN/SYNC pin must be cycled

with a single logic−low to logic−high transition.

UVLO

Input Undervoltage Lockout (UVLO) is provided to

ensure that unexpected behavior does not occur when VIN

is too low to support the internal rails and power the

controller. The IC will start up when enabled and VIN

surpasses the UVLO threshold plus the UVLO hysteresis

and will shut down when VIN drops below the UVLO

threshold or the part is disabled.

To avoid any lock state under UVLO conditions, the

EN/SYNC pin should be in logic−low state. For further

details, please refer to EN/SYNC paragraph.

Internal Soft−Start

To insure moderate inrush current and reduce output

overshoot, the NCV8873 features a soft start which charges a

capacitor with a fixed current to ramp up the reference voltage.

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This fixed current is based on the switching frequency, so that

if the NCV8873 is synchronized to twice the default switching

frequency the soft start will last half as long.

GDRV

An RGND = 15 kW (typical) GDRV−GND resistor is

strongly recommended.

APPLICATION INFORMATION

Design Methodology

This section details an overview of the component

selection process for the NCV8873 in discontinuous

conduction mode (DCM) Boost converter operation with a

high brightness LED (100−150 mA typical) string as a load.

LED current is used for the feedback signal. It is intended to

assist with the design process but does not remove all

engineering design work. Many of the equations make use

of the small ripple approximation. This process entails the

following steps:

1. Define Operational Parameters

2. Select Current Sense Resistor

3. Select Output Inductor

4. Select Output Capacitors

5. Select Input Capacitors

6. Select Feedback Resistors

7. Select Compensator Components

8. Select MOSFET(s)

9. Select Diode

1. Define Operational Parameters

Before beginning the design, define the operating

parameters of the application. These include:

VIN(min): minimum input voltage [V]

VIN(max): maximum input voltage [V]

VOUT: output voltage [V]

ILED: LED current [A]

ICL: desired typical cycle-by-cycle current limit [A]

Vref: NCV8873 feedback reference voltage = 0.2 V

IL: inductor current [A]

From this the ideal minimum and maximum duty cycles

can be calculated as follows:

Mmin +Vout

Vin(max)

Mmax +Vout

Vin(min)

Rout +Vout

ILED

Dmin +Lfs

2Rout ƪǒ2Mmin *1Ǔ2*1ƫ

Dmax +Lfs

2Rout ƪ(2Mmax *1)2*1ƫ

d+2Vout 2

VinRoutIL,peak *D,

Where: (D + d) < 1 for DCM operation IL.

Both duty cycles will actually be slightly higher due to

power loss in the conversion. The exact duty cycles depend

on conduction and switching losses. If the maximum input

voltage is higher than the output voltage, the minimum duty

cycle will be a complex value. This is because a Boost

converter cannot have an output voltage lower than the input

voltage. In situations where the input voltage is higher than

the output, the output will follow the input (minus the diode

drop of the Boost diode) and the converter will not attempt

to switch.

If the inductor value is too large, continuous conduction

mode (CCM) operation will occur and a right-half-plane

(RHP) zero appears which can result in operation instability.

If the calculated Dmax is higher than the Dmax of the

NCV8873, the conversion will not be possible. It is

important for a Boost converter to have a restricted Dmax,

because while the ideal conversion ration of a Boost

converter goes up to infinity as D approaches 1, a real

converter’s conversion ratio starts to decrease as losses

overtake the increased power transfer. If the converter is in

this range it will not be able to maintain output regulation.

If the following equation is not satisfied, the device will

skip pulses at high VIN:

Dmin

fswton(min)

Where: fs: switching frequency [Hz]

ton(min): minimum on time [s]

2. Select Current Sense Resistor

Current sensing for peak current mode control and current

limit relies on the MOSFET current signal, which is

measured with a ground referenced amplifier. The easiest

method of generating this signal is to use a current sense

resistor between the MOSFET source and ground. The sense

resistor should be selected as follows:

RSNS +VCL

ICL

Where: RSNS: sense resistor [W]

VCL: current limit threshold voltage [V]

ICL: desired current limit [A]

3. Select the Boost Inductor

The Boost inductor controls the current ripple that occurs

over a switching period. A discontinuous current ripple will

result in superior transient response and lower switching

noise at the expense of higher transistor conduction losses

and operating ripple current requirements. A low current

ripple will result in CCM operation having a slower response

current slew rate in case of load steps (e.g. introducing an

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LED series dimming circuit). A good starting point is to

select components for DCM operation at Vin(min), but

operation should be verified empirically. Calculate the

maximum inductor value as follows:

Lmax +ǒ1*1

MmaxǓVin(min) 2ǒVout

ILEDǓ

2fsVout 2

The maximum average inductor current can be calculated

as follows:

IL,avg +

VOUTIOUT(max)

VIN(min)

The peak inductor current can be calculated as follows:

IL,peak +

VIN(min)Dmax

Lfs

Where: IL,peak: Peak inductor current value [A]

4. Select Output Capacitor

The output capacitor smoothes the output voltage and

reduces the overshoot and undershoot associated with line

transients. The steady state output ripple associated with the

output capacitors can be calculated as follows:

VOUT(ripple) +ILEDǒ1*d(Mmax)Ǔ

fsCOUT

The capacitors must withstand an RMS ripple current as

follows:

ICout(RMS) +ILED 2)d(Mmax)ǒIL,pk 2

3*IL,pkILEDǓ

A 2.2 mF ceramic capacitor is usually sufficient for high

brightness LED applications for fs = 1 MHz.

5. Select Input Capacitors

The input capacitor reduces voltage ripple on the input to

the module associated with the ac component of the input

current.

ICin(RMS) +ǒD(Mmax))d(Mmax)

3ǓIL,pk 2*IL,avg 2

6. Select Feedback Resistors

The feedback resistor provides LED current sensing for

the feedback signal. It may be calculated as follows:

RF1 +Vref

ILED

7. Select Compensator Components

Current Mode control method employed by the NCV8873

allows the use of a simple Type II compensation to optimize

the dynamic response according to system requirements. A

transconductance amplifier is used, so compensation

components must be connected between the compensation

pin and ground.

8. Select MOSFET(s)

In order to ensure the gate drive voltage does not drop out,

the selected MOSFET must not violate the following

inequality:

Qg(total) vIdrv

Where: Qg(total): Total Gate Charge of MOSFET(s) [C]

Idrv: Drive voltage current [A]

fs: Switching Frequency [Hz]

The maximum RMS Current can be calculated as follows:

IQ(max) +IL,peak

D(Mmax)

The maximum voltage across the MOSFET will be the

maximum output voltage, which is the higher of the

maximum input voltage and the regulated output voltage:

VQ(max) +VOUT(max)

9. Select Diode

The output diode rectifies the output current. The average

current through diode will be equal to the output current:

ID(avg) +IOUT(max)

Additionally, the diode must block voltage equal to the

higher of the output voltage or the maximum input voltage:

VD(max) +VOUT

The maximum power dissipation in the diode can be

calculated as follows:

PD+Vf(max)IOUT(max)

Where: Pd: Power dissipation in the diode [W]

Vf(max): Maximum forward voltage of the diode

[V]

Low Voltage Operation

If the input voltage drops below the UVLO or MOSFET

threshold voltage, another voltage may be used to power the

device. Simply connect the voltage you would like to boost

to the inductor and connect the stable voltage to the VIN pin

of the device. In Boost configuration, the output of the

converter can be used to power the device. In some cases it

may be desirable to connect 2 sources to VIN pin, which can

be accomplished simply by connecting each of the sources

through a diode to the VIN pin.

SOIC−8 NB

CASE 751−07

ISSUE AK

DATE 16 FEB 2011

SEATING

PLANE

X 45 _

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW

STANDARD IS 751−07.

0.10 (0.004)

SCALE 1:1

STYLES ON PAGE 2

DIM

MIN MAX MIN MAX

INCHES

4.80 5.00 0.189 0.197

MILLIMETERS

B3.80 4.00 0.150 0.157

C1.35 1.75 0.053 0.069

D0.33 0.51 0.013 0.020

G1.27 BSC 0.050 BSC

H0.10 0.25 0.004 0.010

J0.19 0.25 0.007 0.010

K0.40 1.27 0.016 0.050

M0 8 0 8

N0.25 0.50 0.010 0.020

S5.80 6.20 0.228 0.244

−X−

−Y−

0.25 (0.010)

−Z−

0.25 (0.010) ZSXS

____

XXXXX = Specific Device Code

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G= Pb−Free Package

GENERIC

MARKING DIAGRAM*

XXXXX

ALYWX

IC Discrete

XXXXXX

AYWW

1.52

0.060

7.0

0.275

0.6

0.024

1.270

0.050

4.0

0.155

ǒmm

inchesǓ

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

Discrete

XXXXXX

AYWW

(Pb−Free)

XXXXX

ALYWX

(Pb−Free)

XXXXXX = Specific Device Code

A = Assembly Location

Y = Year

WW = Work Week

G= Pb−Free Package

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “G”, may

or may not be present. Some products may

not follow the Generic Marking.

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

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disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

98ASB42564B

DOCUMENT NUMBER:

DESCRIPTION:

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Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 2

SOIC−8 NB

CASE 751−07

ISSUE AK

DATE 16 FEB 2011

STYLE 4:

PIN 1. ANODE

2. ANODE

3. ANODE

4. ANODE

5. ANODE

6. ANODE

7. ANODE

8. COMMON CATHODE

STYLE 1:

PIN 1. EMITTER

2. COLLECTOR

3. COLLECTOR

4. EMITTER

5. EMITTER

6. BASE

7. BASE

8. EMITTER

STYLE 2:

PIN 1. COLLECTOR, DIE, #1

2. COLLECTOR, #1

3. COLLECTOR, #2

4. COLLECTOR, #2

5. BASE, #2

6. EMITTER, #2

7. BASE, #1

8. EMITTER, #1

STYLE 3:

PIN 1. DRAIN, DIE #1

2. DRAIN, #1

3. DRAIN, #2

4. DRAIN, #2

5. GATE, #2

6. SOURCE, #2

7. GATE, #1

8. SOURCE, #1

STYLE 6:

PIN 1. SOURCE

2. DRAIN

3. DRAIN

4. SOURCE

5. SOURCE

6. GATE

7. GATE

8. SOURCE

STYLE 5:

PIN 1. DRAIN

2. DRAIN

3. DRAIN

4. DRAIN

5. GATE

6. GATE

7. SOURCE

8. SOURCE

STYLE 7:

PIN 1. INPUT

2. EXTERNAL BYPASS

3. THIRD STAGE SOURCE

4. GROUND

5. DRAIN

6. GATE 3

7. SECOND STAGE Vd

8. FIRST STAGE Vd

STYLE 8:

PIN 1. COLLECTOR, DIE #1

2. BASE, #1

3. BASE, #2

4. COLLECTOR, #2

5. COLLECTOR, #2

6. EMITTER, #2

7. EMITTER, #1

8. COLLECTOR, #1

STYLE 9:

PIN 1. EMITTER, COMMON

2. COLLECTOR, DIE #1

3. COLLECTOR, DIE #2

4. EMITTER, COMMON

5. EMITTER, COMMON

6. BASE, DIE #2

7. BASE, DIE #1

8. EMITTER, COMMON

STYLE 10:

PIN 1. GROUND

2. BIAS 1

3. OUTPUT

4. GROUND

5. GROUND

6. BIAS 2

7. INPUT

8. GROUND

STYLE 11:

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. DRAIN 2

7. DRAIN 1

8. DRAIN 1

STYLE 12:

PIN 1. SOURCE

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 14:

PIN 1. N−SOURCE

2. N−GATE

3. P−SOURCE

4. P−GATE

5. P−DRAIN

6. P−DRAIN

7. N−DRAIN

8. N−DRAIN

STYLE 13:

PIN 1. N.C.

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 15:

PIN 1. ANODE 1

2. ANODE 1

3. ANODE 1

4. ANODE 1

5. CATHODE, COMMON

6. CATHODE, COMMON

7. CATHODE, COMMON

8. CATHODE, COMMON

STYLE 16:

PIN 1. EMITTER, DIE #1

2. BASE, DIE #1

3. EMITTER, DIE #2

4. BASE, DIE #2

5. COLLECTOR, DIE #2

6. COLLECTOR, DIE #2

7. COLLECTOR, DIE #1

8. COLLECTOR, DIE #1

STYLE 17:

PIN 1. VCC

2. V2OUT

3. V1OUT

4. TXE

5. RXE

6. VEE

7. GND

8. ACC

STYLE 18:

PIN 1. ANODE

2. ANODE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. CATHODE

8. CATHODE

STYLE 19:

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. MIRROR 2

7. DRAIN 1

8. MIRROR 1

STYLE 20:

PIN 1. SOURCE (N)

2. GATE (N)

3. SOURCE (P)

4. GATE (P)

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 21:

PIN 1. CATHODE 1

2. CATHODE 2

3. CATHODE 3

4. CATHODE 4

5. CATHODE 5

6. COMMON ANODE

7. COMMON ANODE

8. CATHODE 6

STYLE 22:

PIN 1. I/O LINE 1

2. COMMON CATHODE/VCC

3. COMMON CATHODE/VCC

4. I/O LINE 3

5. COMMON ANODE/GND

6. I/O LINE 4

7. I/O LINE 5

8. COMMON ANODE/GND

STYLE 23:

PIN 1. LINE 1 IN

2. COMMON ANODE/GND

3. COMMON ANODE/GND

4. LINE 2 IN

5. LINE 2 OUT

6. COMMON ANODE/GND

7. COMMON ANODE/GND

8. LINE 1 OUT

STYLE 24:

PIN 1. BASE

2. EMITTER

3. COLLECTOR/ANODE

4. COLLECTOR/ANODE

5. CATHODE

6. CATHODE

7. COLLECTOR/ANODE

8. COLLECTOR/ANODE

STYLE 25:

PIN 1. VIN

2. N/C

3. REXT

4. GND

5. IOUT

6. IOUT

7. IOUT

8. IOUT

STYLE 26:

PIN 1. GND

2. dv/dt

3. ENABLE

4. ILIMIT

5. SOURCE

6. SOURCE

7. SOURCE

8. VCC

STYLE 27:

PIN 1. ILIMIT

2. OVLO

3. UVLO

4. INPUT+

5. SOURCE

6. SOURCE

7. SOURCE

8. DRAIN

STYLE 28:

PIN 1. SW_TO_GND

2. DASIC_OFF

3. DASIC_SW_DET

4. GND

5. V_MON

6. VBULK

7. VBULK

8. VIN

STYLE 29:

PIN 1. BASE, DIE #1

2. EMITTER, #1

3. BASE, #2

4. EMITTER, #2

5. COLLECTOR, #2

6. COLLECTOR, #2

7. COLLECTOR, #1

8. COLLECTOR, #1

STYLE 30:

PIN 1. DRAIN 1

2. DRAIN 1

3. GATE 2

4. SOURCE 2

5. SOURCE 1/DRAIN 2

6. SOURCE 1/DRAIN 2

7. SOURCE 1/DRAIN 2

8. GATE 1

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