NCP51510MNTAG - ON SEMICONDUCTOR - Datasheet.Directory

April, 2015 − Rev. 2 1Publication Order Number:

NCP51510/D

NCP51510, NCV51510

3 Amp VTT Termination

Source / Sink Regulator for

DDR, DDR-2, DDR-3, DDR-4

The NCP51510 is a source/sink Double Data Rate (DDR)

termination regulator specifically designed for low input voltage and

low−noise systems where space is a key consideration. The

NCP51510 maintains a fast transient response and only requires a

minimum VTT load capacitance of 10 mF for output stability. The

NCP51510 supports remote sensing and all power requirements for

DDR VTT bus termination. The NCP51510 can also be used in

low−power chipsets and graphics processor cores that require

dynamically adjustable output voltages. The NCP51510 is available in

the thermally−efficient DFN10 Exposed Pad package, and is rated

both Green and Pb−Free.

Features

•Generate DDR Memory Termination Voltage (VTT)

•For DDR, DDR−2, DDR−3 and DDR−4 Source / Sink Currents

•Supports Loads Up to ±3 A (Typ), Output is Over−Current Protected

•Integrated MOSFETs with Thermal Shutdown Protection

•Fast Load−Transient Response

•PGOOD Output Pin to Monitor Status of VTT Output Regulation

•SS Input Pin for Suspend Shutdown mode

•VRI Input Reference for Flexible Voltage Tracking

•VTTS Input for Remote Sensing (Kelvin Connection)

•Built−in Soft−Start, Under Voltage Lockout

•Small, Low−Profile 10−pin, 3 x 3 mm DFN Package

•NCV51510MWTAG − Wettable Flank Option for Enhanced Optical

Inspection

•NCV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable*

•This is a Pb−Free Device

Applications

•DDR Memory Termination

•Desktop PC’s, Notebooks, and Workstations

•Servers and Networking equipment

•Telecom/Datacom, GSM Base Station

•Graphics Processor Core Supplies

•Set Top Boxes, LCD−TV/PDP−TV, Copier/Printers

•Supplies Power for Chipset/RAM as Low as 0.5 V

•Active Source/Sink Bus Termination

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Device Package Shipping†

ORDERING INFORMATION

NCP51510MNTAG DFN10

(Pb−Free) 3000 / Tape &

Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer t o our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

DFN10

CASE 485C

MARKING DIAGRAM

PIN CONNECTIONS

51510 = Specific Device Code

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G= Pb−Free Package

51510

ALYWG

(Note: Microdot may be in either location)

(Top View)

VRO

VCC

AGND

VRI

PGOOD

PVCC

VTT

PGND

VTTS

GND

NCV51510MNTAG*

NCV51510MWTAG*

NCP51510, NCV51510

www.onsemi.com

PIN FUNCTION DESCRIPTION

Pin Number Pin Name Pin Function

1 VRO OUTPUT − Buffered Output of VRI Reference Input pin.

2 VCC INPUT − Regulator Analog Power Input pin. Connect to the system supply voltage. Bypass VCC to AGND

with a 1 mF or greater ceramic capacitor.

3 AGND Analog Ground

4 VRI INPUT − External Reference Input for VTT Output (see Figure 1 for typical application)

5 PGOOD OUTPUT − VTT “Power Good” pin (open drain output)

6 VTTS INPUT − Remote Sense Input for VTT. The VTTS pin provides accurate remote feedback sensing of the

VTT output.

7 SS INPUT − Suspend Shutdown Control Input. CMOS compatible. Logic HIGH = enable,

logic LOW = shutdown. Connect to VDDQ for normal operation.

8 PGND Power Ground. Internally connected to Low−side MOSFET

9 VTT OUTPUT − Regulated Power Output pin

10 PVCC INPUT − Regulator Power Input pin. Internally connected to High−side MOSFET

− THERMAL

PAD Pad for thermal connection. The exposed pad must be connected to the ground plane using multiple vias

for maximum power dissipation performance.

ABSOLUTE MAXIMUM RATINGS

Rating Symbol Value Unit

PVCC to PGND (Note 1) −−0.3 to 4.3

VCC to AGND (Note 1) VCC −0.3 to 4.3

VRI, VRO, SS, PGOOD to AGND (Note 1) −−0.3 to (VCC + 0.3)

VTT to PGND (Note 1) −−0.3 to (PVCC + 0.3)

VTTS to AGND (Note 1) VTTS −0.3 to (PVCC + 0.3)

PGND to AGND PGND −0.3 to +0.3

Storage Temperature Tstg −65 to 150 °C

Operating Junction Temperature Range TJ−40 to 125

ESD Capability, Human Body Model (Note 2) ESDHBM 2000 V

ESD Capability, Machine Model (Note 2) ESDMM 200 V

VTT Output Continuous RMS Current 100 sec −±1.6 A

1 sec ±2.5

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be af fected.

1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.

2. This device series incorporates ESD protection and is tested by the following methods:

ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)

ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)

Latchup Current Maximum Rating tested per JEDEC standard: JESD78.

DISSIPATION RATINGS

Package TA =705C Power Rate Derating Factor Above TA = 705C

10−Pin DFN 1951 mW 24.4 mW / °C

NCP51510, NCV51510

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RECOMMENED OPERATING CONDITIONS

Rating Symbol Value Unit

VTT Output Voltage Range VTT, VTTS 0.5 to 1.5

PVCC Input Voltage Range (Power) PVCC 1.1 to 3.6

VCC Input Voltage Range (Analog) VCC 2.7 to 3.6

Logic Voltage Range SS, PGOOD 0 to VCC

Operating Ambient Temperature Range TA−40 to +125 °C

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

ELECTRICAL CHARACTERISTICS

PVCC = 1.8 V; VCC = 3.3 V; VRI = VTTS = 1.25 V; SS = VCC; (circuit of Figure 1, −40°C ≤ (TJ = TA) ≤ 125°C; unless otherwise noted.

Typical values are at TA = +25°C

Parameter Conditions Symbol Min Typ Max Unit

OUTPUT

VTT Output Voltage Range PVCC > (VTT + VDROPOUT) VTT 0.5 1.5 V

VTT Load Regulation −1 A ≤ ITT ≤ +1 A DVLOAD −4 +4 mV

VTT Line−Regulation 1.4 V ≤ PVCC ≤ 3.3 V, IOUT = ±100 mA DVLINE 1

Feedback−Voltage Error VRI to VTTS,

ITT = ±200 mA TA = −40°C to 125°C VTTS −17 +17

VTT Current Slew Rate COUT = 100 mF, ITT = 0.1 A to 2 A ITT di/dt 3 A/ms

VTT Output Power−Supply Rejec-

tion Ratio 10 Hz < f < 10 kHz, ITT = 200 mA,

COUT = 100 mFPSRR 80 dB

VTT Output MOSFET RDS(on) High−side (source) (ITT = +100 mA) RDS(on) 140 250 mW

Low−side (sink) (ITT = −100 mA) 140 250

VTT Output−to−VTTS Input Internal Feedback Resistance RFB 12 kW

Discharge MOSFET RDS(on) SS = 0 V RDIS 8W

SUPPLY CURRENT

Quiescent PVCC Current No Load IPVCC 0.4 10 mA

Quiescent VCC Current VRI > 0.45 V, No Load ICC 0.7 1.3

Shutdown PVCC Current SS = 0 V IPVCC SD 0.1 10 mA

Shutdown VCC Current SS = 0V, VRI = 0 V ICC SD 50 100

SS = 0V, VRI > 0.45 V 350 600

REFERENCE

VRI Input Voltage Range VRI 0.5 1.5 V

VRI Input−Bias current TA = +25°C IRI −1 +1 mA

VRO Output Voltage VCC = 3.3 V, IRO = 0 VRO VRI

−10 VRI VRI

+10 mV

VRO Load Regulation IRO = ±5 mA DVRO −20 +20

SUSPEND SHUTDOWN

SS − Suspend Shutdown Logic

Input Threshold SS Logic HI (VTT Output Enabled) VIH 2.0 V

SS Logic LOW (VTT Suspended) VIL 0.8

SS − Logic Input Current SS = VCC or 0 V, TA = +25°C ISS −1 +1 mA

FAULT CONDITION − CURRENT LIMIT

Current−Limit Threshold TA = −40°C to +125°C ITT LIMIT 1.8 3 4.2 A

Soft−start Current−limit time TSS 200 ms

NCP51510, NCV51510

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ELECTRICAL CHARACTERISTICS

PVCC = 1.8 V; VCC = 3.3 V; VRI = VTTS = 1.25 V; SS = VCC; (circuit of Figure 1, −40°C ≤ (TJ = TA) ≤ 125°C; unless otherwise noted.

Typical values are at TA = +25°C (continued)

Parameter UnitMaxTypMinSymbolConditions

FAULT CONDITION − UNDER−VOLTAGE LOCKOUT

VCC UVLO Threshold W ake−up, rising edge VCC UVLO 2.50 2.70 2.90 V

Hysteresis Voltage − 100 mV

PVCC UVLO Threshold W ake−up, rising edge PVCC

UVLO 0.9 1.1 V

Hysteresis Voltage − 55 mV

VRI UVLO Voltage VRI, rising edge VRI UVLO 350 450

Hysteresis Voltage − 50

FAULT CONDITION − THERMAL SHUTDOWN

Thermal Shutdown Temperature Thermal Shutdown, rising edge TSD 165 °C

Thermal Shutdown Hysteresis Hysteresis Temperature TSH 15

FAULT CONDITION − POWER GOOD

PGOOD Lower trip threshold With respect to feedback threshold,

hysteresis = 12 mV −−200 −150 −100 mV

PGOOD Upper trip threshold − 100 150 200

PGOOD Output Low Voltage ISINK = 4 mA (PGOOD MOSFET = On) − 300

PGOOD start−up delay Start−up rising edge, VTTS within ±100 mV

of the feedback threshold − 1 2 3.5 ms

PGOOD Propagation Delay VTTS forced 25 mV beyond PGOOD trip

threshold TPGOOD 5 10 35 ms

PGOOD Leakage Current VTTS = VRI (PGOOD Hi−impedance),

PGOOD = VCC + 0.3 V, TA = +25°CIPGOOD 1mA

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

NCP51510, NCV51510

www.onsemi.com

General*

The NCP51510 is a source/sink tracking termination

regulator specifically designed for low input voltage and

low external component count systems where space is a key

application parameter. The NCP51510 integrates a

high−performance, low−dropout (LDO) linear regulator

that is capable of both sourcing and sinking current. The

LDO regulator employs a fast feedback loop so that small

ceramic capacitors can be used to support the fast load

transient response. To achieve tight regulation with

minimum effect of trace resistance, a remote sensing input

(VTTS) should be connected to the positive terminal of the

output capacitors as a separate trace from the high current

path of the VTT output.

Generation of Internal Voltage Reference

The VTT output voltage is regulated to (and tracks with)

the voltage on the VRI Reference input. When the VRI input

is configured for standard DDR termination applications,

the V RI Reference input can be set by an external equivalent

ratio voltage divider connected to the memory supply bus

(VDDQ). The NCP51510 supports VTT voltages from 0.5 V

to 1.5 V.

Generation of Internal Voltage Reference (cont)

When the V RO output is configured for DDR termination

applications, it provides a separate VTT output reference

voltage for the memory application. The VRO Reference

Output pin is a buffered version of the VRI Reference Input,

and is capable of sourcing and sinking a load of ±5 mA. The

VRO output becomes active when the VRI input > 0.45 V

and the VCC power rail is above the UVLO threshold. The

VRO Reference Output is independent of the SS pin

(Suspend Shutdown) state.

Fault Detection and Shutdown Function

When the SS “Suspend Shutdown” input pin is driven

high, the NCP51510 regulator begins normal operation,

with the Soft Start circuit gradually increasing output

current during the first 200 ms in order to reduce the input

surge currents at startup, with full current available after the

200 ms Soft−Start circuitry has timed out.

When the SS input is driven low, the VTT output is

discharged t o PGND through an internal 8 W MOSFET. The

VRO output remains on when the SS input is driven low. The

NCP51510 provides an open−drain PGOOD “Power Good”

output that goes high when the VTTS Sense input is within

±150 mV of the VRI Reference Input. The PGOOD output

de−asserts within 10 ms after the VTTS Sense input exceeds

the size of the PGOOD window. During initial VTT startup,

PGOOD asserts high 2 ms after the VTTS Sense input enters

PGOOD window. Because the PGOOD output is open−drain,

an external pull−up resistor is required (100 kW*) between

PGOOD and a stable active supply voltage rail.

Thermal Shutdown with Hysteresis

If the N CP 51 51 0 is t o operate in elevated temperatures for

long durations, care should be taken to ensure that the

maximum operating junction temperature is not exceeded.

To guarantee safe operation, the NCP51510 provides

on−chip thermal shutdown protection. When the chip

junction temperature exceeds 165°C*, the part will

shutdown. When the junction temperature falls back, to

150°C*, the device resumes normal operation. If the

junction temperature exceeds the thermal shutdown

threshold, the VTT output is shut off, discharged by the 8 W

internal discharge MOSFET.

Output Capacitor

Output stability is guaranteed for VTT output capacitance

COUT from 10 mF to 220 mF. The ESR of COUT between

2 mW and 50 mW is required to maintain stability. Use the

formula below to calculate the application’s transient

response:

DITT(pp) ESR +DVTT(pp)

Where:

DITT(pp) is the maximum peak−to−peak load current delta

and DVTT(pp) is the allowable peak−to−peak voltage

tolerance.

*Typical values are used with the application description text. Please refer to the Electrical Specifications Table for a more detailed list of MIN,

MAX and TYPICAL values.

NCP51510, NCV51510

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Figure 1. Standard Application Schematic for NCP51510

NCP51510, NCV51510

www.onsemi.com

PACKAGE DIMENSIONS

DFN10, 3x3, 0.5P

CASE 485C

ISSUE C

10X

SEATING

PLANE

0.15 C

eD2

10 6

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.25 AND 0.30 MM FROM TERMINAL.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

5. TERMINAL b MAY HAVE MOLD COMPOUND

MATERIAL ALONG SIDE EDGE. MOLD

FLASHING MAY NOT EXCEED 30 MICRONS

ONTO BOTTOM SURFACE OF TERMINAL b.

6. DETAILS A AND B SHOW OPTIONAL VIEWS

FOR END OF TERMINAL LEAD AT EDGE OF

PACKAGE.

7. FOR DEVICE OPN CONTAINING W OPTION,

DETAIL B ALTERNATE CONSTRUCTION IS

NOT APPLICABLE.

ÇÇÇ

0.15 CTOP VIEW

SIDE VIEW

BOTTOM VIEW

PIN 1

REFERENCE

0.10 C

0.08 C

(A3)

10X

0.10 C

0.05 C

A B

NOTE 3

10X

DIM MIN MAX

MILLIMETERS

A0.80 1.00

A1 0.00 0.05

A3 0.20 REF

b0.18 0.30

D3.00 BSC

D2 2.40 2.60

E3.00 BSC

E2 1.70 1.90

e0.50 BSC

L0.35 0.45

L1 0.00 0.03

DET AIL A K0.19 TYP

DETAIL A

Bottom View

(Optional)

ÉÉÉ

DETAIL B

Side View

(Optional)

EDGE OF PACKAGE

MOLD CMPD

EXPOSED Cu

DETAIL B

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

2.1746

2.6016

1.8508

0.5000 PITCH

0.5651

10X

3.3048

0.3008

10X

DIMENSIONS: MILLIMETERS

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NCP51510/D

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