NCV97310MW33R2G - ON SEMICONDUCTOR

April, 2018 − Rev. 8 1Publication Order Number:

NCV97310/D

NCV97310

Automotive Battery-

Connected Low-Iq Multi-

Output Power Management

Unit with 3 Buck Regulators

Description

The NCV97310 is a 3−output regulator consisting of a low−Iq

battery−connected 3 A, 2 MHz non−synchronous switcher and two

low−voltage 1.5 A, 2 MHz synchronous switchers; all using integrated

power transistors.

The high−voltage switcher is capable of converting a 4.1 V to 18 V

battery input to a 3.3 V output at a constant 2 MHz switching

frequency, delivering up to 3 A. In overvoltage conditions up to 36 V,

the switching frequency folds back to 1 MHz; in load dump conditions

up to 45 V the regulator shuts down.

The output of the battery−connected buck regulator serves as the low

voltage input for the 2 downstream synchronous switchers. Each

downstream output is adjustable from 1.2 V to 2.8 V, with a 1.5 A

average current limit and a constant 2 MHz switching frequency. Each

switcher has an independent enable and reset pin, giving extra power

management flexibility.

For low−Iq operating mode, the low−voltage switchers are disabled

and the standby rail is supplied by a low−Iq LDO (up to 150 mA) with

a typical Iq of 30 mA. The LDO regulator is in parallel to the

high−voltage switcher, and is activated when the switcher is forced in

standby mode.

All 3 SMPS outputs use peak current mode control with internal

slope compensation, internally−set soft−start, battery undervoltage

lockout, battery overvoltage protection, cycle−by−cycle current

limiting, hiccup mode short−circuit protection and thermal shutdown.

An error flag is available for diagnostics.

Features

•Low Quiescent Current in Standby Mode

•Programmable Spread Spectrum for EMI Reduction

•2 Microcontroller Enabled Low Voltage Synchronous

Buck Converters

•Large Conversion Ratio of 18 V to 3.3 V Battery

Connected Switcher

•Wide Input of 4.1 to 45 V with Undervoltage Lockout

(UVLO)

•Fixed Frequency Operation Adjustable from 2.0 to

2.6 MHz

•Internal 1.5 ms Soft−starts

•Cycle−by−cycle Current Limit Protections

•Hiccup Overcurrent Protections (OCP)

•Individual Reset Pins with Adjustable Delays

•QFN Package with Wettable Flanks (pin edge plating)

•NCV Prefix for Automotive and Other Applications

Requiring Unique Site and Control Change

Requirements; AEC−Q100 Qualified and PPAP

Capable

•These Devices are Pb−Free, Halogen Free/BFR Free

and are RoHS Compliant

Typical Applications

•Infotainment, Body Electronics, Telematics, ECU

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MARKING DIAGRAM

QFN32

MW SUFFIX

CASE 488AM

NCV97310

AWLYYWWG

A = Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

G= Pb−Free Package

See detailed ordering, marking and shipping information on

page 20 of this data sheet.

ORDERING INFORMATION

(Note: Microdot may be in either location)

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LINEAR

REGULATOR

ERR

OSC

REGULATOR 1

3.3 V

STEP DOWN

REGULATOR 2

1.2 V −−> 2.8 V

STEP DOWN

REGULATOR 3

1.2 V −−> 2.8 V

STEP DOWN

VINL

VOUT

VBAT SW1

STBYB

VIN2

SW2

SW3H

FB2

FB3

EN2

EN3

VDRV1

BST1

ROSC

WARNING

VIN_UVLO

ERRB

GND2

RSTB1

RSTB2

TEMP

VIN_OV

RSTB1

RSTB2

RSTB3

GND1

BST2

BST3

RSTB3

VDD

VDRV VDRV2

SW3L

GND3

Master Enable

RSTB

COMP1

VDRV

VIN3

RMOD

RDEPTH

Figure 1. NCV97310 Block Diagram

Exposed

Pad

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TYPICAL APPLICATION

Figure 2. Typical Application

32 25

9 16

VBAT

STBYB

RSTB1

COMP1

ROSC

ERRB EN2 RSTB2 GND1 RSTB3 FB3 EN3 BST3

GND3

SW3L

SW3H

VDRV2

GND2

SW2

VIN2

SW1 VDRV1 BST1 VINL VOUT FB2 BST2

CBST1

CDRV2

CBST2

RFB2D

RFB2U

COUT2

RFB3U

CBST3

ROSC

RCOMP1

CCOMP1

VOUT2

VOUT3

COUT3

VOUT1

COUT1

VBAT

CIN2

CIN1

VIN3

RMOD

RDEPTH RDEPTH

RMOD

Exposed

Pad

CDRV1

RDRV1

VOUT1

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Table 1. MAXIMUM RATINGS

Rating Symbol Value Unit

Min/Max Voltage VBAT, VINL −0.3 to 45 V

Max Voltage VBAT to SW1 45 V

Min/Max Voltage SW1 −0.7 to 40 V

Min Voltage SW1, SW2, SW3 − 20 ns −3.0 V

Min/Max Voltage BST1, STBYB, EN −0.3 to 40 V

Min/Max Voltage VIN2, VIN3, BST2, BST3, SW2, SW3H, SW3L, VOUT −0.3 to 12 V

Min/Max Voltage on RSTB2, RSTB3, EN2, EN3, FB2, FB3 −0.3 to 6 V

Min/Max Voltage on RSTB1, ERRB −0.3 to 3.6 V

Max Voltage BST1 to SW1, BST2 to SW2, BST3 to SW3x 3.6 V

Min/Max Voltage VDRV1, VDRV2, COMP1, ROSC, RMOD, RDEPTH −0.3 to 3.6 V

Thermal Resistance, 5 x 5 QFN Junction – to – Ambient (Note 1) RθJA 25 °C/W

Storage Temperature Range −55 to +150 °C

Operating Junction Temperature Range TJ−40 to +150 °C

ESD Withstand Voltage Human Body Model

Machine Model VESD 2.0*

200 kV

Moisture Sensitivity MSL Level 1

Peak Reflow Soldering Temperature 260 °C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be af fected.

1. Mounted on 1 sq. in. of a 4−layer PCB with 1 oz. copper thickness.

*BST2, BST3 HBM 1.5 kV

Table 2. RECOMMENDED OPERATING CONDITIONS

Rating Value

VIN Range 4.5 V to 36 V

Ambient Temperature Range −40°C to 125°C

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

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Table 3. PIN FUNCTION DESCRIPTIONS

Pin No. Symbol Description

1 VBAT Input voltage from battery. Place an input filter capacitor in close proximity to this pin. Must be tied to Pin 29 −

VINL.

2 EN High−voltage (battery), TTL−compatible, master enable signal. Grounding this input stops all outputs and

reduces Iq to a minimum (shutdown mode).

3 STBYB High−voltage (battery), TTL−compatible, mode selection signal. Grounding this input activates the low−Iq

mode of operation for switcher 1 (standby mode).

4 RDEPTH Modulation depth adjustment (% of FSW) for spread spectrum. Set with a resistor to GND.

5 RMOD Modulation frequency adjustment for spread spectrum. Set with a resistor to GND.

6 RSTB1 Reset with adjustable delay. Goes low when the output is out of regulation. When using Low−Iq LDO Mode,

connect a pull−up resistor to a permanent external supply (e.g. VOUT1).

7 COMP1 Output of the error amplifier for switcher 1

8 ROSC Provides Frequency Adjustment

9 ERRB Error flag combining temperature and input and output voltage sensing

10 EN2 TTL compatible low voltage input. Grounding this input stops switcher 2.

11 RSTB2 Reset with adjustable delay. Goes low when the output is out of regulation.

12 GND1 Ground reference for the IC.

13 RSTB3 Reset with adjustable delay. Goes low when the output is out of regulation.

14 FB3 Output voltage sensing, provides adjustability.

15 EN3 TTL compatible low voltage input. Grounding this input stops switcher 3.

16 BST3 Bootstrap input provides drive voltage higher than VIN3 to the high−side N−channel Switch for optimum

switch RDS(on) and highest efficiency.

17 GND3 Ground connection for the source of the low−side switch of switcher 3.

18 SW3L Drain of the low−side switch. Connect the output inductor to this pin. Must be tied to SW3H.

19 SW3H Source of the high−side switch. Connect the output inductor to this pin. Must be tied to SW3L.

20 VDRV2 Internal supply voltage for driving the low−voltage internal switches. Connect a capacitor for noise filtering

purposes.

21 VIN3 Low Input voltage for switcher 3. Place an input filter capacitor in close proximity to this pin. Must be

connected to Pin 22 − VIN2 and Pin 28 − VOUT.

22 VIN2 Low Input voltage for switcher 2. Place an input filter capacitor in close proximity to this pin. Must be

connected to Pin 21 − VIN3 and Pin 28 − VOUT.

23 SW2 Switching node of the switcher 2 regulator . Connect the output inductor to this pin.

24 GND2 Ground connection for the source of the low−side switch of switcher 2.

25 BST2 Bootstrap input provides drive voltage higher than VIN2 to the high−side N−channel Switch for optimum

switch RDS(on) and highest efficiency.

26 NC This pin is a no−connect. Leave the pin floating.

27 FB2 Output voltage sensing, provides adjustability.

28 VOUT Output voltage sensing. Delivers the output current in low−Iq mode

29 VINL Input voltage from battery. Place an input filter capacitor in close proximity to this pin. Must be tied to Pin1 −

VBAT.

30 BST1 Bootstrap input provides drive voltage higher than VBAT to the N−channel Power Switch for optimum switch

Rdson and highest efficiency.

31 VDRV1 Internal supply voltage for driving the low−voltage internal switch. Connect a capacitor for noise filtering

purposes. (When using Low−Iq LDO Mode, also connect a 100 kW resistor to GND.)

32 SW1 Switching node of the Regulator . Connect the output inductor and cathode of the freewheeling diode to this pin.

Exposed

Pad Must be connected to GND1 (electrical ground) and to a low thermal resistance path to the ambient

temperature environment.

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Table 4. ELECTRICAL CHARACTERISTICS (VBAT = VINL = 4.5 V to 28 V, VEN = VSTBYB = VEN2 = VEN3 = 5 V, VBSTx = VSWx +

3.0 V, CDRV1 = 0.1 mF, CDRV2 = 0.47 mF. Min/Max values are valid for the temperature range −40°C ≤ TJ ≤ 150°C unless noted otherwise,

and are guaranteed by test, design or statistical correlation.)

Parameter Symbol Conditions Min Typ Max Unit

QUIESCENT CURRENT

Quiescent Current, shutdown IqSD VBAT = VINL= 13.2 V, TJ=25°C,

VEN = 0 V 8 12 mA

Quiescent Current, standby IqEN VBAT = VINL = 13.2 V, TJ=25°C

VEN = 3 V,

VSTBYB = VEN2 = VEN3 = 0 V

25 35 mA

UNDERVOLTAGE LOCKOUT – VBAT (UVLO)

VBAT UVLO Start Threshold VUV1ST VBAT rising 4.45 4.85 V

VBAT UVLO Stop Threshold VUV1SP VBAT falling 3.7 4.1 V

VBAT UVLO Hysteresis VUV1HY 0.75 V

ENABLE

Logic Low (Voltage input needed to

guarantee logic low) VENLO, VEN2LO,

VEN3LO, VSTBYBLO 0.8 V

Logic High (Voltage input needed to

guarantee logic high) VENHI, VEN2HI,

VEN3HI, VSTBYBHI 2 V

Enable pin input Current IEN VEN = 5 V 0.125 1.0 mA

ISTBYB VSTBYB = 5 V 0.5 2.0

IEN2, IEN3 VEN2 = VEN3 = 5 V 30 50 70

Switcher 1 start−up time tSTBYB STBYB ‘High’ to Switcher 1 ready 60 200 ms

OUTPUT VOLTAGE

Switcher 1 output VOUT 3.23 3.3 3.37 V

VOUT Line regulation in Low−Iq mode VLine1 IOUT = 50 mA, VSTBYB = 0 V,

6 V < VINL = VBAT < 28 V 5 25 mV

VOUT Load regulation in Low−Iq mode VLoad1 VINL = VBAT = 13.2 V, VSTBYB = 0 V,

1 mA < IOUT < 150 mA 10 35 mV

Voltage drop−out in Low−Iq mode VDROP1 IOUT = 150 mA, VSTBYB = 0 V 500 mV

Switchers 2 and 3 FB Pin Voltage

during regulation VFB2R, VFB3R OUTx connected to FBx

through a 10 kW resistor 1.179 1.200 1.221 V

ERROR AMPLIFIER − SWITCHER 1

Transconductance (Note 2) gm

gm(HV)

VCOMP = 1.1 V

4.5 V < VBAT < 18 V

20 V < VBAT < 28 V 0.6

0.35 1.0

0.55 1.4

0.75

mmho

Output Resistance ROUT 1.4 MW

COMP Source Current Limit ISOURCE VOUT = 4.0 V, VCOMP = 1.1 V

4.5 V < VBAT < 18 V

20 V < VBAT < 28 V 50

25 75

40 100

COMP Sink Current Limit ISINK VOUT = 6.0 V, VCOMP = 1.1 V

4.5 V < VBAT < 18 V

20 V < VBAT < 28 V 50

25 75

40 100

Minimum COMP voltage VCMPMIN VOUT = 6.0 V 0.15 0.3 V

Maximum COMP voltage VCMPMAX VOUT = 4.0 V 1.3 1.6 V

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

2. Not tested in production. Limits are guaranteed by design.

NCV97310

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Table 4. ELECTRICAL CHARACTERISTICS (VBAT = VINL = 4.5 V to 28 V, VEN = VSTBYB = VEN2 = VEN3 = 5 V, VBSTx = VSWx +

3.0 V, CDRV1 = 0.1 mF, CDRV2 = 0.47 mF. Min/Max values are valid for the temperature range −40°C ≤ TJ ≤ 150°C unless noted otherwise,

and are guaranteed by test, design or statistical correlation.)

Parameter UnitMaxTypMinConditionsSymbol

OSCILLATOR

Switching Frequency − switcher 1 fSW1

fSW1(HV) 4.5 < VBAT < 18 V, ROSC = open

20 V < VBAT < 28 V, ROSC = open 1.8

0.9 2.0

1.0 2.2

1.1 MHz

Switching Frequency − switchers 2 & 3 fSW2, fSW3 ROSC = open 1.8 2.0 2.2 MHz

Switching Frequency − ROSC fROSC ROSC = 12.5 kW2.3 2.5 2.8 MHz

ROSC reference voltage VROSC ROSC = 25 kW0.9 1.0 1.1 V

VBAT OVERVOLTAGE SHUTDOWN MONITOR

Overvoltage Stop Threshold VOV1SP 36 V

Overvoltage Start Threshold VOV1ST 30 V

Overvoltage Hysteresis VOV1HY 0.6 1.4 2.4 V

VBAT FREQUENCY FOLDBACK MONITOR

Frequency Foldback Threshold VFL1U

VFL1D VBAT rising

VBAT falling 18.4

18 20

19.8 V

Frequency Foldback Hysteresis VFL1HY 0.2 0.3 0.4 V

SOFT−START

Soft−Start Completion Time tSS1, tSS2, tSS3 0.8 1.4 2.0 ms

SLOPE COMPENSATION

Ramp Slope (Note 2) – switcher 1

(With respect to switch current) Sramp1

Sramp1(HV) 4.5 < VBAT < 18 V

20 V < VBAT < 28 V 1.8

0.8 3.4

1.6 A/ms

Ramp Slope (Note 2) – switchers 2 & 3 Sramp2 1.9 3.7 A/ms

POWER SWITCH − SWITCHER 1

ON Resistance RDS1ON VBST1 = VSW1 + 3.0 V, ISW1 = 500 mA 185 360 mW

Leakage current VBAT to SW1 ILKSW1 VEN = 0 V, VSW1 = 0, VBAT = 18 V 10 mA

Minimum ON Time tON1MIN Measured at SW1 pin 45 70 ns

Minimum OFF Time tOFF1MIN Measured at SW1 pin 30 50 70 ns

POWER SWITCHES − SWITCHER 2

High−Side ON Resistance RHS2ON VBST2 = VSW2 + 3.0 V,

ISW2 = 500 mA 165 300 mW

Low−Side ON Resistance RLS2ON ISW2 = 500 mA 130 230 mW

Leakage current high−side switch ILKSW2 VEN2 = 0 V, VSW2 = 0, VIN2 = 5.5 V 5mA

Minimum ON Time tON2MIN Measured at SW2 pin 60 80 95 ns

Minimum OFF Time tOFF2MIN Measured at SW2 pin 35 55 75 ns

Non−overlap time tNOVLP 10 ns

POWER SWITCHES − SWITCHER 3

High−Side ON Resistance RHS3ON VBST3 = VSW3H + 3.0 V,

ISW3H = 500 mA 140 250 mW

Low−Side ON Resistance RLS3ON ISW3L = 500 mA 130 230 mW

Leakage current high−side switch ILKSW3 VEN3 = 0 V, VSW3H = 0, VIN3 = 5.5 V 5mA

Minimum ON Time tON3MIN Measured at SW3x pin 60 80 95 ns

Minimum OFF Time tOFF3MIN Measured at SW3x pin 35 55 75 ns

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

2. Not tested in production. Limits are guaranteed by design.

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Table 4. ELECTRICAL CHARACTERISTICS (VBAT = VINL = 4.5 V to 28 V, VEN = VSTBYB = VEN2 = VEN3 = 5 V, VBSTx = VSWx +

3.0 V, CDRV1 = 0.1 mF, CDRV2 = 0.47 mF. Min/Max values are valid for the temperature range −40°C ≤ TJ ≤ 150°C unless noted otherwise,

and are guaranteed by test, design or statistical correlation.)

Parameter UnitMaxTypMinConditionsSymbol

POWER SWITCHES − SWITCHER 3

Non−overlap time tNOVLP 10 ns

PEAK CURRENT LIMITS

Current Limit Threshold – switcher 1

Normal mode

Low−Iq mode ILIM1

ILIM1,stby VSTBYB = 5 V

VSTBYB = 0 V 3.9

0.15 4.4

0.2 4.9

0.25

Current Limit Threshold – switcher 2 ILIM2 2.6 2.9 3.2 A

Current Limit Threshold – switcher 3 ILIM3 2.6 2.9 3.2 A

SHORT CIRCUIT FREQUENCY FOLDBACK – SWITCHER1

Lowest Foldback Frequency

Lowest Foldback Frequency – high VIN fSW1AF

fSW1AFHV VOUT = 0 V, 4.5 V < VBAT < 18 V

VOUT = 0 V, 20 V < VBAT < 28 V 450

225 550

275 650

325 kHz

HICCUP MODE

Hiccup Mode fSW1HIC,

fSW2HIC,

fSW3HIC

VSWx = 0 V 24 32 40 kHz

RESET

Reset Threshold − Switcher 1 (as a

ratio of VOUT1)KRES_LO1

KRES_HI1 VOUT1 decreasing

VOUT1 increasing 90

90.5 92.5 95

97 %

Reset Threshold − Switchers 2 & 3 (at

FBx) KRES_LO2

KRES_HI2 FBx decreasing

FBx increasing 1.1 1.164 V

Reset Hysteresis (ratio of VOUTx) KRES_HYS 0.5 %

Noise−filtering delay tRES_FILT 5 25 ms

Reset delay time tRESET IRSTBx = 2 mA

IRSTBx = 1 mA

IRSTBx = 100 mA3.5

1.0

4.5

30 5.5

Reset Output Low level VRESL IRSTBx = 2 mA 0.4 V

BOOTSTRAP VOLTAGE SUPPLY

Output Voltage VDRV1, VDRV2 3.1 3.3 3.5 V

VDRVx POR Start Threshold VDRV1ST

VDRV2ST 2.7

2.35 2.85

2.5 3.05

2.65 V

VDRVx POR Stop Threshold VDRV1SP

VDRV2SP 2.55

2.2 2.75

2.35 2.95

2.5 V

SPREAD SPECTRUM

RMOD Pin Voltage VRMOD RMOD = 10 kW0.54 0.60 0.66 V

RDEPTH Pin Voltage VRDEPTH RDEPTH = 10 kW0.54 0.60 0.66 V

Modulation Frequency fMOD RMOD = RDEPTH = 10 kW22 25 28 kHz

Modulation Depth (Top Frequency) fDEPTH,max RMOD = RDEPTH = 10 kW2.05 2.3 2.55 MHz

Spread Spectrum Disable RSSDIS RMOD or RDEPTH 1.7 150 kW

ERROR FLAG

ERRB Output Low level VERRBL IERRB = 1 mA 0.4 V

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

2. Not tested in production. Limits are guaranteed by design.

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Table 4. ELECTRICAL CHARACTERISTICS (VBAT = VINL = 4.5 V to 28 V, VEN = VSTBYB = VEN2 = VEN3 = 5 V, VBSTx = VSWx +

3.0 V, CDRV1 = 0.1 mF, CDRV2 = 0.47 mF. Min/Max values are valid for the temperature range −40°C ≤ TJ ≤ 150°C unless noted otherwise,

and are guaranteed by test, design or statistical correlation.)

Parameter UnitMaxTypMinConditionsSymbol

THERMAL SHUTDOWN

Thermal Warning Activation

Temperature (Note 2) TWARN 150 °C

Thermal Shutdown Activation

Temperature (Note 2) TSD 150 190 °C

Hysteresis (Note 2) THYS 5 20 °C

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

2. Not tested in production. Limits are guaranteed by design.

NCV97310

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TYPICAL CHARACTERISTICS

Figure 3. Quiescent Current (Shutdown)

vs. Junction Temperature Figure 4. Quiescent Current (Standby)

vs. Junction Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

1251007550250−25−50

Figure 5. UVLO vs. Junction Temperature Figure 6. SW2 VREF vs. Junction Temperature

TJ, JUNCTION TEMPERATURE (°C)

Figure 7. SW3 VREF vs. Junction Temperature Figure 8. F

vs. Junction Temperature

TJ, JUNCTION TEMPERATURE (°C)

qSD

, QUIESCENT CURRENT,

SHUTDOWN (mA)

IqEN, QUIESCENT CURRENT,

STANDBY (mA)

UVLO (V)

VREF, SW2 (V)

VREF, SW3 (V)

150 1251007550250−25−50

1251007550250−25−50

3.0

3.5

4.0

5.0

5.5

150

4.5

1251007550250−25−50

1.2014

1251007550250−25−50

1.2011

150

Rising

Falling

1.2012

1.2010

1.2008

1.2006

1.2004

1.2002

1.2010

1.2009

1.2008

1.2007

1.2006

1.2005

1.2004

1.2003

TJ, JUNCTION TEMPERATURE (°C)

fSW (MHz)

1251007550250−25−50 15

2.016

2.014

2.012

2.010

2.008

2.006

2.004

2.002

2.000

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TYPICAL CHARACTERISTICS

Figure 9. Soft Start Time vs. Junction

Temperature Figure 10. SW1 RDS(on) vs. Junction

Temperature

TJ, JUNCTION TEMPERATURE (°C)

SOFT START TIME (ms)

1251007550250−25−50 150

1.7

SW1

SW3

SW2

1.65

1.6

1.55

1.5

1.45

1.4

TJ, JUNCTION TEMPERATURE (°C)

RDS(on), SW1 (mW)

1251007550250−25−50

100

150

250

150

200

300

Figure 11. SW2 High Side RDS(on) vs. Junction

Temperature Figure 12. SW2 Low Side RDS(on) vs. Junction

Temperature

TJ, JUNCTION TEMPERATURE (°C)

RHS2(on), SW2 (mW)

1251007550250−25−50

100

150

250

150

200

300

TJ, JUNCTION TEMPERATURE (°C)

RLS2(on), SW2 (mW)

1251007550250−25−50

100

150

250

150

200

Figure 13. SW3 High Side RDS(on) vs. Junction

Temperature Figure 14. SW3 Low Side RDS(on) vs. Junction

Temperature

TJ, JUNCTION TEMPERATURE (°C)

RHS3(on), SW3 (mW)

1251007550250−25−50

100

150

250

150

200

TJ, JUNCTION TEMPERATURE (°C)

RLS3(0n), SW3 (mW)

1251007550250−25−50

0150

100

150

200

250

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TYPICAL CHARACTERISTICS

Figure 15. LDO Current Limit vs. Junction

Temperature Figure 16. SW1 Peak Current Limit vs.

Junction Temperature

TJ, JUNCTION TEMPERATURE (°C)

CURRENT LIMIT, LDO (mA)

1251007550250−25−50 150

202

201

200

199

198

197

196

195

TJ, JUNCTION TEMPERATURE (°C)

PEAK CURRENT LIMIT, SW1 (mA)

1251007550250−25−50

4560

150

4540

4520

4500

4480

4460

4440

4420

4400

4380

Figure 17. SW2 Peak Current Limit vs.

Junction Temperature Figure 18. SW3 Peak Current Limit vs.

Junction Temperature

TJ, JUNCTION TEMPERATURE (°C)

PEAK CURRENT LIMIT, SW2 (mA)

1251007550250−25−50

2860

150

2850

2840

2830

2820

2810

2800

2790

TJ, JUNCTION TEMPERATURE (°C)

PEAK CURRENT LIMIT, SW3 (mA)

1251007550250−25−50

2930

150

2920

2910

2900

2890

2880

2870

2860

2850

Figure 19. VDRV1 Voltage vs. Junction

Temperature Figure 20. VDRV2 Voltage vs. Junction

Temperature

TJ, JUNCTION TEMPERATURE (°C)

VDRV1 (V)

1251007550250−25−50 150

3.3325

3.332

3.3315

3.331

3.3305

3.33

TJ, JUNCTION TEMPERATURE (°C)

1251007550250−25−50

VDRV2 (V)

150

3.2985

3.298

3.2975

3.297

3.2965

3.296

3.2955

3.295

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APPLICATION INFORMATION

General Description

The NCV97310 consists of one 2 MHz battery−connected 2.5 A switcher (switcher 1) with a parallel low−Iq 150 mA LDO,

and two low−voltage 2 MHz 1.5 A switchers (switchers 2 and 3).

LINEAR

REGULATOR

ERR

OSC

REGULATOR 1

3V3

STEP DOWN

REGULATOR 2

1V2 ... 2V8

STEP DOWN

REGULATOR 3

1V2...2V8

STEP DOWN

VINL

VOUT

VBAT SW1

STBYB

VIN2

SW2

SW3H

FB2

FB3

EN2

EN3

VDRV1

BST1

ROSC

WARNING

VIN_UVLO

ERRB

GND2

RSTB1

RSTB2

TEMP

VIN_OV

RSTB1

RSTB2

RSTB3

GND1

BST2

BST3

RMIN

RSTB3

VDD

VDRV VDRV2

SW3L

GND3

Master Enable

RSTB

COMP1

VDRV

VIN3

RMOD

RDEPTH

LOGIC

Figure 21. NCV97310 Block Schematic

Switcher 2

Switcher 3

Switcher 1 and low−Iq LDO

Exposed

Pad

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COMMON BLOCKS

Input Voltage

The main supply for the part is taken from the VBAT pin,

which much always be tied to a voltage source between

4.1 V and 36 V.

•Below 4.1 V an Undervoltage Lockout (UVLO) circuit

inhibits all switching, resets the Soft−start circuits, and

turns off the LDO.

•Above 36 V, an Overvoltage Shutdown circuit inhibits

all switching and allows the NCV97310 to survive a

45 V load dump. Normal operation resumes when

VBAT goes back down below 30 V.

Although the LDO has its own input pin VINL (that can

also survive a 45 V load dump), it must always be connected

to VBAT for proper operation.

Switcher 2 and switcher 3 each have a dedicated input pin,

VIN2 and VIN3. VIN2 and VIN3 should be shorted together

right at the pin because they share a common drive pin,

VDRV2. Please note that VIN2 and VIN3 are strictly low

voltage (up to 12 V when disabled and 9.5 V when

switching) and there is no voltage sensing present.

It is recommended to connect VIN2 (and VIN3) to

VOUT1, although a different rail could be used to supply

switchers 2 and 3, as long as VBAT is powered and switcher

1 enabled (see Oscillator section for details).

Oscillator

All three switchers share the same oscillator, which

defaults t o 2.0 MHz and can be adjusted from 2.0 to 2.6 MHz

using an external resistor (ROSC) to ground. The range of

ROSC value for this range of frequency adjustment is

between 12.5 kW and 50 kW (see Figure 22). For resistor

values below 10 kW, the frequency is safely clamped to 2.8

MHz.

Instead of a resistor, one can force a current out of the

ROSC pin, between 20 mA (corresponding to 2 MHz) and

80ĂmA (corresponding to 2.5 MHz), typical.

Figure 22. Oscillator Frequency vs. ROSC Value

0 102030405060

ROSC, (kW)

OSCILLATOR FREQUENCY (MHz)

3.0

2.8

2.6

2.4

2.2

2.0

1.8

Manually adjusting the oscillator frequency using the

ROSC pin changes the switching frequency of all 3

switchers, since they share a common oscillator. When

switcher 1 enters maximum duty cycle frequency foldback,

though, switchers 2 and 3 remain at their nominal switching

frequency. The foldback for switcher 1 takes place in logic

outside of the oscillator. The same applies for both

switcher 2 and switcher 3. When switcher 2, for example,

enters maximum duty cycle frequency foldback, the other

two switchers remain at their nominal switching frequency.

Spread Spectrum

In SMPS devices, switching translates to higher

efficiency. Unfortunately, the switching leads to a much

noisier EMI profile. We can greatly decrease some of the

radiated emissions with some spread spectrum techniques.

Spread spectrum is used to reduce the peak electromagnetic

emissions of a switching regulator.

fc9fc

7fc

5fc

3fc

fc9fc

7fc

5fc

3fc

Time Domain Frequency Domain

Unmodulated

Modulated

Figure 23.

The spread spectrum used in the NCV97310 is an

“up−spread” technique, meaning the switching frequency is

spread upward from the 2.0 MHz base frequency. For

ex a mple, a 5% spread means that the switching frequency is

swept (spread) from 2.0 MHz up to 2.1 MHz in a linear

fashion – this is called the modulation depth. The rate at

which this spread takes place is called the modulation

frequency. For example, a 10 kHz modulation frequency

means that the frequency is swept from 2.0 MHz to 2.1 MHz

in 50 ms and then back down from 2.1 MHz to 2.0 MHz in

50 ms.

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Figure 24.

The modulation depth and modulation frequency are each

set by an external resistor to GND. The modulation

frequency can be set from 5 kHz up to 50 kHz using a resistor

from the RMOD pin to GND. The modulation depth can be

set from 3% up to 30% of the nominal switching frequency

using a resistor from the RDEPTH pin to GND. Please see

the curves below for typical values:

Figure 25. Modulation Frequency vs. RMOD Value

RMOD, (kW)

MODULATION FREQUENCY (kHz)

20102030405060

Figure 26. Modulation Depth vs. RDEPTH Value

RDEPTH, (kW)

MODULATION DEPTH (%FSW)

010203040506

Spread spectrum is automatically turned off when there is

a short to GND or an open circuit on either the RMOD pin

or the RDEPTH pin. Please be sure that the ROSC pin is an

open circuit when using spread spectrum.

Master Enable

The NCV97310 can be completely disabled (shutdown

mode) by connecting the EN pin to ground. As a result, all

outputs are stopped and the internal current consumption

drops below 10 mA.

The EN pin is designed to accept either a logic level signal

or the battery voltage.

Reset

When the voltage on the OUTx pin drops below the reset

threshold (92.5% typically for RSTB1, 93.5% typically for

RSTB2 & RSTB3), the open−drain output RSTBx is pulled

low. The RSTB1 pin is fully operational in Low−Iq mode.

A pull−up resistor must be connected to RSTB1, typically

from RSTB1 to VOUT1 (permanent supply voltage in low−Iq

mode). The RSTB2 & RSTB3 pins are asserted (pulled low)

when the associated switcher is disabled and when in

Low−Iq mode (STBYB low).

Delay

Each o f the RSTB signals can either be used as a reset with

delay or a power good (no delay). The delay is determined

by the current into the RSTBx pin, set by a resistor, shown

in Figure 27.

RRSTBx

VOUT1

RSTx

RSTBx

Figure 27. Reset Delay Time

Use the following equation to determine the ideal reset

delay time using currents less than 1 mA:

tdelay +3000

IRSTBx )1.2 (eq. 1)

where:

tdelay: ideal reset delay time [ms]

IRSTBx: current into the RSTBx pin [mA]

Using I RSTBx = 2 mA re mov es the delay and allows the reset

to act as a “power good” pin.

The RSTBx resistor is commonly tied to VOUT1.

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For a 3.3 V pull−up voltage, typical delay times can be

achieved with the following resistor values:

RRSTBx (kW)tDLY (ms)

1.6 0

3.3 4.5

5 5.9

10 10.3

20 19.3

30 28.9

Minimum Dropout Voltage

When operating at low input voltages, two parameters

play a major role in imposing a minimum voltage drop

across the regulator: the minimum off time (that sets the

maximum duty cycle) and the on−state resistance.

When operating in continuous conduction mode (CCM),

the output voltage is equal to the input voltage multiplied b y

the duty ratio. Because each switcher needs a sufficient

bootstrap voltage to operate, its duty cycle cannot be 100%:

it needs a minimum of f time (toff,min) to periodically re−fuel

the bootstrap capacitor, CBST. This imposes a maximum

duty ratio DMAX= 1 – toff,min ⋅ FSW(min) with the switching

frequency being folded back to FSW(min) = 500 kHz to keep

regulating a t the lowest input voltage possible. The drop due

to the on−state resistance is simply the voltage drop across

the switch at the given output current: VSW,drop = IOUT ⋅

RDS(on). Which leads to the maximum output voltage in low

Vin condition: VOUT = DMAX ⋅ VIN(min) − VSW,drop

Error Flag

An open drain ERRB pin (active low) flags the status of

several internal error detectors: VBAT undervoltage, VBAT

overvoltage, thermal warning, switcher 1 reset, as well as the

reset flags RSTB2 and RSTB3 if their respective switchers

are enabled. Note that overvoltage is not flagged in Low−Iq

standby mode.

When the master enable pin EN is forced low, the error

flag is not active anymore.

Thermal Shutdown

A thermal shutdown circuit inhibits switching, resets the

Soft−start circuits, and removes DRVx voltages if the

internal temperature exceeds a safe level. Switching is

automatically restored when the temperature returns to a

safer level.

Inductor Selection

By default, a 4.7 mH inductor is recommended for the

primary switching output. If you’d like to choose a dif ferent

value, please follow the equation, below.

L+

Voutǒ1*VOUT

VIN,maxǓ

dIr@fsw @Iout

where:

VOUT: dc output voltage [V]

VIN,max: maximum dc input voltage [V]

dIr: inductor current ripple [%]

fSW: switching frequency [Hz]

IOUT: dc output current [A]

Discontinuous Mode

In order to ensure continuous conduction mode, the ripple

(half of the peak−to−peak ripple) needs to be less than the

average current through the inductor. The limit can be found

using the following equation for borderline conduction

mode:

IBCM +1

2@ǒ1*VOUT

VIN,maxǓ

fsw @VOUT

where:

IBCM: borderline conduction mode output current [A]

VOUT: dc output voltage [V]

VIN,max: maximum dc input voltage [V]

fSW: switching frequency [Hz]

L: inductor value [H]

Average output currents above IBCM will operate in

continuous m o d e while average output currents below IBCM

will operate in discontinuous mode.

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SWITCHER 1

Output Voltage

The primary buck output of the NCV97310 and the

low−Iq LDO output are fixed at 3.3 V.

High Voltage Frequency Foldback

To limit the power lost in generating the drive voltage for

the Power Switch, the switching frequency is reduced by a

factor of 2 when the input voltage exceeds the VBAT

Frequency Foldback threshold VFL1U (see Figure 28).

Frequency reduction is automatically terminated when the

input voltage drops back below the VBAT Frequency

Foldback threshold VFL1D.

418 20 36

Figure 28. Switcher 1 Switching Frequency

Reduction at High Input Voltage

FSW

(MHz)

VIN (V)

Low−IQ Mode

The NCV97310 can be put in a low−Iq regulating mode

by connecting the STBYB pin to ground. As a result,

Switcher 1 turns off and the low−Iq LDO turns on,

maintaining regulation on VOUT (up to 150 mA). In this

mode the VOUT reset monitor is still active (RSTB1 pin),

as well as the under−voltage sensing on VBAT and the

thermal sensing, and they’re all flagged on the ERRB pin.

Switchers 2 and 3 are automatically disabled, with their

respective reset pins pulled low.

Upon enabling standard switching mode again (bringing

STBYB high), voltage is established at the DRV1 pin,

followed by a pre−charge of the bootstrap capacitor before

switcher 1 starts switching. There is no soft−start unless

VOUT is below the reset threshold.

It is recommended to wait at least 200 ms after toggling

STBYB before applying a load higher than 150 mA.

The STBYB pin is designed to accept either a logic level

signal or the battery voltage.

Please n ote: w hen u sing L ow−Iq M ode i n y our a pplication,

it is necessary to place a resistor (between 10 kW and 1 M W)

from VDRV1 to GND to discharge CDRV1 while the LDO

is operating. To avoid extra current consumption during

low−Iq mode, it is also necessary to place a pull−up resistor

on RSTB1 so that the internal delay timer is properly settled.

Soft−Start

Upon being enabled or released from a fault condition,

and after the DRV1 voltage is established, a soft−start circuit

ramps the switching regulator error amplifier reference

voltage to the final value. During soft−start, the average

switching frequency is lower than its normal mode value

(typically 2 MHz) until the output voltage approaches

regulation. There is no soft−start if the output is already

above the reset threshold.

Error Amplifier

The error amplifier is a transconductance type amplifier.

The output voltage of the error amplifier controls the peak

inductor current at which the power switch shuts off. The

Current Mode control method employed allows the use of a

simple, type II compensation to optimize the dynamic

response according to system requirements.

The compensation components must be connected

between the output of the error amplifier and the electrical

ground (between pins COMP1 and GND1). For most

applications, the following compensation circuitry is

recommended:

330 pF

12.4k

22 pF

COMP

Figure 29. Recommended Compensation for

Primary Switcher

Slope Compensation

A fixed slope compensation signal is generated internally

and added to the sensed current to avoid increased output

voltage ripple due to bifurcation of inductor ripple current

at duty cycles above 50% (sub−harmonics oscillations). The

fixed amplitude of the slope compensation signal requires

the inductor to be greater than a minimum value, depending

on output voltage, in order to avoid sub−harmonic

oscillations. The recommended inductor value is either

2.2 mH or 4.7 mH.

To determine the minimum inductor required to avoid

sub−harmonic oscillations, please refer to the following

equation:

Lmin +VOUT

ǒ2*SrampǓ

NCV97310

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where:

Lmin: minimum inductor required to avoid sub-harmonic

oscillations [mH]

Vout: output voltage [V]

Sramp: internal slope compensation [A/ms]

Short Circuit Frequency Foldback

During severe output overloads or short circuits,

switcher 1 automatically reduces its switching frequency.

This creates duty cycles small enough to limit the peak

current in the power components, while maintaining the

ability to automatically reestablish the output voltage if the

overload is removed. If the current is still too high after the

switching frequency folds back to 500 kHz (250 kHz for

VIN > 2 0 V), the regulator enters hiccup mode (32 kHz) that

further reduces the dissipated power.

Bootstrap

At the DRV1 pin an internal regulator provides a

ground−referenced voltage to an external capacitor

(CDRV1), to allow fast recharge of the external bootstrap

capacitor ( C BST1) used to supply power to the power switch

gate driver. If the voltage at the DRV1 pin goes below the

DRV UVLO Threshold VDRVSTP, switching is inhibited and

the Soft−start circuit is reset, until the DRV1 pin voltage

goes back up above VDRVSTT.

In order for the bootstrap capacitor to stay charged, the

Switch node needs to be pulled down to ground regularly. In

very light load condition, when switcher 1 skips switching

cycles t o keep the output voltage in regulation, the bootstrap

voltage could collapse and the regulator stop switching. To

prevent this, an internal minimum load is connected on

VOUT to operate correctly in all cases (it is disconnected in

low Iq mode, when the STBYB pin is low).

A fast−charge circuit ensures the bootstrap capacitor is

always charged prior to starting the switcher after it has been

enabled.

Current Limiting

Due to the ripple on the inductor current, the average

output current of a buck converter is lower than the peak

current setpoint of the regulator. Figure 30 shows − for a

4.7 mH inductor − how the variation of inductor peak current

with input voltage affects the maximum DC current

switcher 1 can deliver to a load. Figure 31 shows the same

for 2.2 mH inductor.

Figure 30. Switcher 1 Load Current Capability with a

4.7 mH Inductor

0 5 10 15 20 25 30

INPUT VOLTAGE, (V)

SW1 Maximum Output Current − Worst Case (A)

4.5

Vout1 = 3.3 V

3.5

2.5

1.5

0.5

Figure 31. Switcher 1 Load Current Capability with a

2.2 mH Inductor

0 5 10 15 20 25 30

INPUT VOLTAGE, (V)

SW1 Maximum Output Current − Worst Case (A)

4.5

3.5

2.5

1.5

0.5

Vout1 = 3.3 V

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SWITCHERS 2 & 3

Enable

When a d c logic high (CMOS/TTL compatible) voltage is

applied to the EN2 or EN3 pin and the STBYB pin is high

Switcher 2 or Switcher 3, respectively, are allowed to

operate. Switcher 1 soft start needs to complete before

Switcher 2 or Switcher 3 is allowed to turn on. A dc logic

low on EN2 or EN3 shuts off the respective regulators.

Soft−Start

Upon being enabled or released from a fault condition,

voltage is first established on the VDRV2 pin (for the first

of switcher 2 or 3 to be enabled). Then a soft−start circuit

ramps the switching regulator error amplifier reference

voltage to the final value, for a duration tSS independent of

the switching frequency (1.4 ms typically).

The low−side switch is always turned on first to ensure a

proper charge of the bootstrap capacitor.

Error Amplifier

The error amplifier is a voltage type amplifier with fixed

internal compensation, optimized for the range of input and

output voltage combinations. The output voltage of the error

amplifier controls the peak inductor current at which the

power shuts off (current−mode operation).

Because the compensation is internally fixed, the value of

the upper feedback resistor (in series between the output and

the feedback pin) must be 10 kW to ensure stability,

including in the case of a 1.2 V output, when no lower

feedback resistor is used. In addition, it is recommended to

use 1 or 2 10 mF capacitors on the output, depending on your

ripple requirement; and an inductor value between 1 mH and

4.7 mH (see slope compensation section).

Slope Compensation

A fixed slope compensation signal is generated internally

and added to the sensed current to avoid increased output

voltage ripple due to bifurcation of inductor ripple current

at duty cycles above 50% (sub−harmonic oscillations). The

fixed amplitude of the slope compensation signal requires

the inductor to be greater than a minimum value, dependent

on the output voltage, in order to avoid sub−harmonic

oscillations.

•For 2.8 V or 2.5 V output, the recommended inductor

value is 2.2 mH.

•For 1.2 V or 1.5 V output, the recommended inductor

value is 1.0 mH.

Short Circuit Frequency Foldback

During severe output overloads or short circuits,

switchers 2 and 3 (independently) automatically enter an

auto−recovery burst mode in order to self−protect. When a

short−circuit is detected, the switcher disables its output and

remains off for the hiccup time and then goes through the

power-on reset procedure. If the short has been removed

then the output re−enables and operates normally; if,

however, the short is still present the cycle begins again. Th e

hiccup mode is continuous until the short is removed.

Current Limiting

Due t o t he r ipple o n t he i nductor c urrent, t he a verage o utput

current of a buck converter is lower than the peak current

setpoint of the regulator. Figure 32 shows how the variation

of inductor peak current with input voltage affects the

maximum DC current switcher 2 or 3 can deliver to a load.

Figure 32. Switcher 2 or 3 Load Current

Capability vs. Input Voltage

3 3.5 4 4.5 6.5 7 7.5

INPUT VOLTAGE, (V)

SW2 & SW3 Maximum Output Current − Worst Case (A)

2.5

1.5

0.5

065 5.5

VOUT = 1.2 V (L = 1.0 mH)

VOUT = 1.8 V (L = 1.0 mH)

Output Voltage Selection

The voltage outputs for switcher 2 and switcher 3 are

adjustable and can be set with a resistor divider. The FB

reference for both switchers is 1.2 V.

VOUT2 (VOUT3)

FBx = 1.2 V

RUPPER

RLOWER

Figure 33. Output Voltage Selection with

Feedback Divider

The upper resistor is set to 10 kW and is part of the

feedback loop. To maintain stability over all conditions, it is

recommended t o change the only the lower feedback resistor

to set the output voltage. Use the following equation:

RLOWER +RUPPER VFB

VOUT *VFB

NCV97310

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Some common setups are listed below:

Desired

Output (V) VREF (V) RUPPER

(kW, 1%) RLOWER

(kW, 1%)

1.2 1.2 10.0 NP

1.5 1.2 10.0 40.0

1.8 1.2 10.0 20.0

2.5 1.2 10.0 9.31

Noise Performance for Heavy Load

For heavy load conditions (> 1 A) on the downstream

switching outputs, a snubber circuit is recommended for

improved noise performance. The following circuit can be

used for all output voltage combinations:

100 pF

SW2

(SW3)

Figure 34. RC Snubber Circuit for Noise Performance

at Heavy Loads

ORDERING INFORMATION

Device Package Shipping†

NCV97310MW33R2G QFN32

(Pb−Free) 5000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

NCV97310

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PACKAGE DIMENSIONS

QFN32 5x5, 0.5P

CASE 488AM

ISSUE A

SEATING

NOTE 4

0.15 C

(A3)

32X

BOTTOM VIEW

TOP VIEW

SIDE VIEW

0.15 C

ÉÉ

PIN ONE

LOCATION

0.10 C

0.08 C

NOTES:

1. DIMENSIONS AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.15 AND 0.30MM FROM THE TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

PLANE

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

0.50

3.35

0.30

3.35

32X

0.63

32X

5.30

DETAIL A

ALTERNATE TERMINAL

CONSTRUCTIONS

ÉÉÉ

ÇÇÇ

DETAIL B

MOLD CMPDEXPOSED Cu

ALTERNATE

CONSTRUCTION

DETAIL B

DET AIL A

DIM

AMIN

MILLIMETERS

0.80

A1 −−−

A3 0.20 REF

b0.18

D5.00 BSC

D2 2.95

E5.00 BSC

2.95

e0.50 BSC

0.30

K0.20

1.00

0.05

0.30

3.25

0.50

−−−

MAX

−−−

L1 0.15

e/2 NOTE 3

PITCH DIMENSION: MILLIMETERS

RECOMMENDED

0.10 BC

0.05 C

NCV97310/D

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