4 Ω RON, Triple/Quad SPDT
±15 V/+12 V/±5 V iCMOS Switches
ADG1433/ADG1434
Rev. C
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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©2006–2009 Analog Devices, Inc.
FEATURES
4.7 Ω maximum on resistance @ 25°C
0.5 Ω on resistance flatness
Fully specified at ±15 V/+12 V/±5 V
3 V logic-compatible inputs
Up to 115 mA continuous current per channel
Rail-to-rail operation
Break-before-make switching action
16-/20-lead TSSOP and 4 mm × 4 mm LFCSP_VQ packages
APPLICATIONS
Relay replacement
Audio and video routing
Automatic test equipment
Data acquisition systems
Temperature measurement systems
Avionics
Battery-powered systems
Communication systems
Medical equipment
GENERAL DESCRIPTION
The ADG1433 and ADG1434 are monolithic industrial CMOS
(iCMOS®) analog switches comprising three independently
selectable single-pole, double-throw (SPDT) switches and
four independently selectable SPDT switches, respectively.
All channels exhibit break-before-make switching action that
prevents momentary shorting when switching channels. An EN
input on the ADG1433 (LFCSP and TSSOP packages) and
ADG1434 (LFCSP package only) is used to enable or disable
the device. When disabled, all channels are switched off.
The iCMOS modular manufacturing process combines high
voltage, complementary metal-oxide semiconductor (CMOS),
and bipolar technologies. It enables the development of a wide
range of high performance analog ICs capable of 33 V operation
in a footprint that no other generation of high voltage parts has
been able to achieve. Unlike analog ICs using a conventional
CMOS process, iCMOS components can tolerate high supply
voltages while providing increased performance, dramatically
lower power consumption, and reduced package size.
The ultralow on resistance and on resistance flatness of these
switches make them ideal solutions for data acquisition and gain
switching applications, where low distortion is critical. iCMOS
construction ensures ultralow power dissipation, making the parts
ideally suited for portable and battery-powered instruments.
FUNCTIONAL BLOCK DIAGRAMS
IN1 IN2 IN3 EN
S1A
D1
S1B
S3B
D3
S3A
S2B
D2
S2A
LOGIC
ADG1433
SWITCHES SHOWN FOR
A 1 INPUT LOGIC.
06181-001
Figure 1. ADG1433 TSSOP and LFCSP_VQ
S1
A
D1
S1B
IN1
IN2
S2B
S2
A
D2
S4A
D4
S4B
IN4
IN3
S3B
S3A
D3
ADG1434
SWITCHES SHOWN FOR
A
1 INPUT LOGIC.
06181-002
Figure 2. ADG1434 TSSOP
S1A
D1
S1B
S2B
S2A
D2
S4A
D4
S4B
S3B
S3A
D3
ADG1434
06181-101
SWITCHES SHOWN FOR
A 1 INPUT LOGIC.
IN1 IN2 IN3 IN4 EN
LOGIC
Figure 3. ADG1434 LFCSP_VQ
ADG1433/ADG1434
Rev. C | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
±15 V Dual Supply ....................................................................... 3
12 V Single Supply ........................................................................ 5
±5 V Dual Supply ......................................................................... 6
Absolute Maximum Ratings ............................................................7
Thermal Resistance .......................................................................7
ESD Caution...................................................................................7
Pin Configurations and Function Descriptions ............................8
Typical Performance Characteristics ........................................... 10
Test Circuits ..................................................................................... 13
Terminology .................................................................................... 15
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 17
REVISION HISTORY
6/09—Rev. B to Rev. C
Updated Outline Dimensions ....................................................... 16
Changes to Ordering Guide .......................................................... 17
3/09—Rev. A to Rev. B
Change to IDD Parameter, Table 1 ................................................... 4
Change to IDD Parameter, Table 2 ................................................... 5
Updated Outline Dimensions, Figure 39 ..................................... 17
6/08—Rev. 0 to Rev. A
Added Continuous Current per Channel Parameter, Table 1 ..... 4
Added Continuous Current per Channel Parameter, Table 2 ..... 5
Added Continuous Current per Channel Parameter, Table 3 ..... 6
Changes to Table 4 ............................................................................. 7
Changes to Figure 30 ...................................................................... 13
Updated Outline Dimensions ....................................................... 16
Changes to Ordering Guide .......................................................... 17
10/06—Revision 0: Initial Version
ADG1433/ADG1434
Rev. C | Page 3 of 20
SPECIFICATIONS
±15 V DUAL SUPPLY
VDD = +15 V ± 10%, VSS = –15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter +25°C
−40°C to
+85°C
−40°C to
+125°C1 Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VSS to VDD V
On Resistance, RON 4 Ω typ VS = ±10 V, IS = −10 mA; see Figure 25
4.7 5.7 6.7 Ω max VDD = +13.5 V, VSS = −13.5 V
On Resistance Match Between 0.5 Ω typ VS = ±10 V, IS = −10 mA
Channels, ΔRON 0.78 0.85 1.1 Ω max
On Resistance Flatness, RFLAT(ON) 0.5 Ω typ VS = ±10 V, IS = −10 mA
0.72 0.77 0.92 Ω max
LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V
Source Off Leakage, IS (Off) ±0.04 nA typ VD = ±10 V, VS = ±10 V; see Figure 26
±0.3 ±0.6 ±3 nA max
Drain Off Leakage, ID (Off) ±0.04 nA typ VD = ±10 V, VS = ±10 V; see Figure 26
±0.3 ±0.6 ±3 nA max
Channel On Leakage, ID, IS (On) ±0.05 nA typ VS = VD = ±10 V; see Figure 27
±0.4 ±0.8 ±8 nA max
DIGITAL INPUTS
Input High Voltage, VIH 2.0 V min
Input Low Voltage, VIL 0.8 V max
Input Current, IIL or IIH ±0.005 μA typ VIN = VGND or VDD
±0.1 μA max
Digital Input Capacitance, CIN 3 pF typ
DYNAMIC CHARACTERISTICS2
Transition Time, tTRANS 140 ns typ RL = 100 Ω, CL = 35 pF
170 200 230 ns max VS = 10 V, see Figure 28
Break-Before-Make Time Delay, tD 40 ns typ RL = 100 Ω, CL = 35 pF
30 ns min VS1 = VS2 = 10 V, see Figure 29
tON (EN) 140 ns typ RL = 100 Ω, CL = 35 pF
170 200 230 ns max VS = 10 V, see Figure 30
tOFF (EN) 60 ns typ RL = 100 Ω, CL = 35 pF
75 85 90 ns max VS = 10 V, see Figure 30
Charge Injection −50 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 31
Off Isolation −70 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 32
Channel-to-Channel Crosstalk −70 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 34
Total Harmonic Distortion, THD + N 0.025 % typ RL = 110 Ω, 15 V p-p, f = 20 Hz to 20 kHz, see
Figure 35
−3 dB Bandwidth 200 MHz typ RL = 50 Ω, CL = 5 pF, see Figure 33
Insertion Loss 0.24 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 33
CS (Off) 12 pF typ f = 1 MHz
CD (Off) 22 pF typ f = 1 MHz
CD, CS (On) 72 pF typ f = 1 MHz
ADG1433/ADG1434
Rev. C | Page 4 of 20
Parameter +25°C
−40°C to
+85°C
−40°C to
+125°C1Unit Test Conditions/Comments
POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V
IDD 0.001 μA typ Digital inputs = 0 V or VDD
1 μA max
IDD 260 μA typ Digital inputs = 5 V
475 μA max
ISS 0.001 μA typ Digital inputs = 0 V, 5 V, or VDD
1 μA max
VDD/VSS ±4.5/±16.5 V min/max GND = 0 V
Continuous Current per Channel2
V
DD = +13.5 V, VSS = −13.5 V
ADG1433 115 75 40 mA max
ADG1434 100 65 40 mA max
1 Temperature range for Y version: −40°C to +125°C.
2 Guaranteed by design, not subject to production test.
ADG1433/ADG1434
Rev. C | Page 5 of 20
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameter +25°C
−40°C to
+85°C
−40°C to
+125°C1 Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 to VDD V
On Resistance, RON 6 Ω typ VS = 0 V to 10 V, IS = −10 mA, see Figure 25
8 9.5 11.2 Ω max VDD = 10.8 V, VSS = 0 V
On Resistance Match Between 0.55 Ω typ VS = 0 V to 10 V, IS = −10 mA
Channels, ΔRON 0.82 0.85 1.1 Ω max
On Resistance Flatness, RFLAT(ON) 1.5 Ω typ VS = 0 V to 10 V, IS = −10 mA
2.5 2.5 2.8 Ω max
LEAKAGE CURRENTS VDD = 13.2 V
Source Off Leakage, IS (Off) ±0.04 nA typ VS = 1 V/10 V, VD = 10 V/1 V, see Figure 26
±0.3 ±0.6 ±3 nA max
Drain Off Leakage, ID (Off) ±0.04 nA typ VS = 1 V/10 V, VD = 10 V/1 V, see Figure 26
±0.3 ±0.6 ±3 nA max
Channel On Leakage, ID, IS (On) ±0.06 nA typ VS = VD = 1 V or 10 V, see Figure 27
±0.4 ±0.8 ±8 nA max
DIGITAL INPUTS
Input High Voltage, VIH 2.0 V min
Input Low Voltage, VIL 0.8 V max
Input Current, IIL or IIH ±0.005 μA typ VIN = VGND or VDD
±0.1 μA max
Digital Input Capacitance, CIN 4 pF typ
DYNAMIC CHARACTERISTICS2
Transition Time, tTRANS 200 ns typ RL = 100 Ω, CL = 35 pF
255 310 350 ns max VS = 8 V, see Figure 28
Break-Before-Make Time Delay, tD 80 ns typ RL = 100 Ω, CL = 35 pF
55 ns min
VS1 = VS2 = 8 V, see Figure 29
tON (EN) 210 ns typ RL = 100 Ω, CL = 35 pF
270 320 360 ns max
VS = 8 V, see Figure 30
tOFF (EN) 70 ns typ RL = 100 Ω, CL = 35 pF
86 95 105 ns max
VS = 8 V, see Figure 30
Charge Injection −10 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF, see Figure 31
Off Isolation –70 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 32
Channel-to-Channel Crosstalk –70 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 34
−3 dB Bandwidth 135 MHz typ RL = 50 Ω, CL = 5 pF, see Figure 33
Insertion Loss 0.5 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 33
CS (Off) 25 pF typ f = 1 MHz
CD (Off) 45 pF typ f = 1 MHz
CD, CS (On) 80 pF typ f = 1 MHz
POWER REQUIREMENTS VDD = 13.2 V
IDD 0.002 μA typ Digital inputs = 0 V or VDD
1 μA max
IDD 260 μA typ Digital inputs = 5 V
475 μA max
VDD 5/16.5 V min/max VSS = 0 V, GND = 0 V
Continuous Current per Channel2 V
DD = +10.8 V, VSS = 0 V
ADG1433 100 65 40 mA max
ADG1434 85 60 35 mA max
1 Temperature range for Y version: −40°C to +125°C.
2 Guaranteed by design, not subject to production test.
ADG1433/ADG1434
Rev. C | Page 6 of 20
±5 V DUAL SUPPLY
VDD = +5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V, unless otherwise noted.
Table 3.
Parameter +25°C
−40°C to
+85°C
−40°C to
+125°C1 Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VSS to VDD V
On Resistance (RON) 7 Ω typ VS = ±4.5 V, IS = −10 mA, see Figure 25
9 10.5 12 Ω max VDD = +4.5 V, VSS = −4.5 V
On Resistance Match Between 0.55 Ω typ VS = ±4.5 V, IS = −10 mA
Channels (ΔRON) 0.78 0.91 1.1 Ω max
On Resistance Flatness, RFLAT(ON) 1.5 Ω typ VS = ±4.5 V, IS = −10 mA
2.5 2.5 3 Ω max
LEAKAGE CURRENTS VDD = +5.5 V, VSS = −5.5 V
Source Off Leakage, IS (Off) ±0.02 nA typ
VD = ±4.5 V, VS = ±4.5 V, see Figure 26
±0.3 ±0.6 ±3 nA max
Drain Off Leakage, ID (Off) ±0.02 nA typ VD = ±4.5 V, VS = ±4.5 V, see Figure 26
±0.3 ±0.6 ±3 nA max
Channel On Leakage, ID, IS (On) ±0.04 nA typ VS = VD = ±4.5 V, see Figure 27
±0.4 ±0.8 ±8 nA max
DIGITAL INPUTS
Input High Voltage, VIH 2.0 V min
Input Low Voltage, VIL 0.8 V max
Input Current, IIL or IIH ±0.005 μA typ VIN = VGND or VDD
±0.1 μA max
Digital Input Capacitance, CIN 4 pF typ
DYNAMIC CHARACTERISTICS2
Transition Time, tTRANS 315 ns typ RL = 100 Ω, CL = 35 pF
430 480 550 ns max
VS = 5 V, see Figure 28
Break-Before-Make Time Delay, tD 90 ns typ RL = 100 Ω, CL = 35 pF
55 ns min
VS1 = VS2 = 5 V, see Figure 29
tON (EN) 325 ns typ RL = 100 Ω, CL = 35 pF
425 490 545 ns max
VS = 5 V, see Figure 30
tOFF (EN) 150 ns typ RL = 100 Ω, CL = 35 pF
200 225 240 ns max VS = 5 V, see Figure 30
Charge Injection −10 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 31
Off Isolation −70 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 32
Channel-to-Channel Crosstalk −70 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 34
Total Harmonic Distortion, THD + N 0.06 % typ RL = 110 Ω, 5 V p-p, f = 20 Hz to 20 kHz, see Figure 35
−3 dB Bandwidth 145 MHz typ RL = 50 Ω, CL = 5 pF, see Figure 33
Insertion Loss 0.5 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 33
CS (Off) 18 pF typ f = 1 MHz
CD (Off) 32 pF typ f = 1 MHz
CD, CS (On) 80 pF typ f = 1 MHz
POWER REQUIREMENTS VDD = +5.5 V, VSS = −5.5 V
IDD 0.002 μA typ Digital inputs = 0 V, 5 V, or VDD
1 μA max
ISS 0.001 μA typ Digital inputs = 0 V, 5 V, or VDD
1 μA max
VDD/VSS ±4.5/±16.5 V min/max GND = 0 V
Continuous Current per Channel2 V
DD = +4.5 V, VSS = −4.5 V
ADG1433 95 60 35 mA max
ADG1434 85 55 35 mA max
1 Temperature range for Y version: −40°C to +125°C.
2 Guaranteed by design, not subject to production test.
ADG1433/ADG1434
Rev. C | Page 7 of 20
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter Rating
VDD to VSS 35 V
VDD to GND −0.3 V to +25 V
VSS to GND −25 V to +0.3 V
Analog Inputs, Digital Inputs1 VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
Peak Current, S or D (Pulsed at 1 ms,
10% Duty Cycle Maximum)
250 mA
Continuous Current, S or D2 Data + 15%
Operating Temperature Range
Industrial (Y Version) −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
Reflow Soldering Peak
Temperature (Pb-Free)
260 (+ 0 to −5)°C
1 Overvoltages at A, EN, S, or D pins are clamped by internal diodes. Current
should be limited to the maximum ratings given.
2 See data given in the Specifications section (see Table 1 to Table 3).
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Only one absolute maximum rating may be applied at any
one time.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 5.
Package Type θJA θ
JC Unit
TSSOP 150.4 50 °C/W
LFCSP_VQ 30.4 N/A °C/W
ESD CAUTION
ADG1433/ADG1434
Rev. C | Page 8 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
06181-003
06181-005
PIN 1
INDICATOR
1D1
2S1B
3S2B
4D2
11 VSS
12 EN
10 S3B
9D3
5
S2A
6
IN2
7
IN3
8
S3A
15 V
DD
16 S1A
14 GND
13 IN1
TOP VIEW
(Not to Scale)
ADG1433
1
2
3
4
5
6
7
8
16
15
14
13
12
S1A
D1
S1B
S2B
V
DD
IN1
EN
V
SS
S3B
GND
ADG1433
TOP VIEW
(Not to Scale)
11
10
9
S2A
D2
S3A
IN2 IN3
D3
NOTES
1. EXPOSED PAD IS TIED TO SUBSTRATE, VSS.
Figure 4. ADG1433 TSSOP Pin Configuration Figure 5. ADG1433 LFCSP_VQ Pin Configuration
Table 6. ADG1433 Pin Function Descriptions
Pin No.
Mnemonic Description TSSOP LFCSP_VQ
1 15 VDD Most Positive Power Supply Potential.
2 16 S1A Source Terminal 1A. Can be an input or an output.
3 1 D1 Drain Terminal 1. Can be an input or an output.
4 2 S1B Source Terminal 1B. Can be an input or an output.
5 3 S2B Source Terminal 2B. Can be an input or an output.
6 4 D2 Drain Terminal 2. Can be an input or an output.
7 5 S2A Source Terminal 2A. Can be an input or an output.
8 6 IN2 Logic Control Input 2.
9 7 IN3 Logic Control Input 3.
10 8 S3A Source Terminal 3A. Can be an input or an output.
11 9 D3 Drain Terminal 3. Can be an input or an output.
12 10 S3B Source Terminal 3B. Can be an input or an output.
13 11 VSS Most Negative Power Supply Potential. In single-supply applications, it can be connected to ground.
14 12 EN Active Low Digital Input. When high, the device is disabled and all switches are off. When low, INx
logic inputs determine the on switches.
15 13 IN1 Logic Control Input 1.
16 14 GND Ground (0 V) Reference.
Table 7. ADG1433 Truth Table
EN INx SxA SxB
1 X Off Off
0 0 Off On
0 1 On Off
ADG1433/ADG1434
Rev. C | Page 9 of 20
1
2
3
4
5
6
8
20
19
18
17
16
15
13
S1A
D1
S1B
7
S2B
GND
V
SS
IN1
S4A
D4
S4B
14
S3B
9
S2A
12
S3A
10
IN2
11
IN3
D2 D3
NC
V
DD
IN4
ADG1434
TOP VIEW
(Not to Scale)
NC = NO CONNECT
06181-004
6
PIN 1
INDICATOR
Figure 6. ADG1434 TSSOP Pin Configuration
06181-00
1D1
2S1B
3V
SS
4GND
5S2B
13 V
DD
14 S4B
15 D4
12 S3B
11 D3
6
D2
7
S2A
8
IN2
10
S3A
9
IN3
18 EN
19 IN1
20 S1
A
17 IN4
16 S4
A
TOP VIEW
(Not to Scale)
ADG1434
NOTES
1. EXPOSED PAD IS TIED TO SUBSTRATE,
V
SS
.
Figure 7. ADG1434 LFCSP_VQ Pin Configuration
Table 8. ADG1434 Pin Function Descriptions
Pin No.
TSSOP Mnemonic Description LFCSP_VQ
1 19 IN1 Logic Control Input 1.
2 20 S1A Source Terminal 1A. Can be an input or an output.
3 1 D1 Drain Terminal 1. Can be an input or an output.
4 2 S1B Source Terminal 1B. Can be an input or an output.
5 3 VSS Most Negative Power Supply Potential. In single-supply applications, it can be connected to ground.
6 4 GND Ground (0 V) Reference.
7 5 S2B Source Terminal 2B. Can be an input or an output.
8 6 D2 Drain Terminal 2. Can be an input or an output.
9 7 S2A Source Terminal 2A. Can be an input or an output.
10 8 IN2 Logic Control Input 2.
11 9 IN3 Logic Control Input 3.
12 10 S3A Source Terminal 3A. Can be an input or an output.
13 11 D3 Drain Terminal 3. Can be an input or an output.
14 12 S3B Source Terminal 3B. Can be an input or an output.
15 N/A NC No Connect.
16 13 VDD Most Positive Power Supply Potential.
17 14 S4B Source Terminal 4B. Can be an input or an output.
18 15 D4 Drain Terminal 4. Can be an input or an output.
19 16 S4A Source Terminal 4A. Can be an input or an output.
20 17 IN4 Logic Control Input 4.
N/A 18 EN Active Low Digital Input. When high, the device is disabled and all switches are off. When low, INx
logic inputs determine the on switches.
Table 9. ADG1434 TSSOP Truth Table
INx SxA SxB
0 Off On
1 On Off
Table 10. ADG1434 LFCSP_VQ Truth Table
EN INx SxA
SxB
1 X Off Off
0 0 Off On
0 1 On Off
ADG1433/ADG1434
Rev. C | Page 10 of
–16.5 15.5
SOURCE OR DRAIN VOLTAGE (V)
–12.5 –8.5 –4.5 –0.5 3.5 7.5 11.5
20
TYPICAL PERFORMANCE CHARACTERISTICS
5
6
0
ON RESISTANCE (Ω)
4
3
2
1
V
DD
= +15V, V
SS
= –15V
V
DD
= +13.5V, V
SS
= –13.5V
V
DD
= +12V, V
SS
= –12V
V
DD
= +10V, V
SS
= –10V
V
DD
= +16.5V, V
SS
= –16.5V
T
A
= 25°C
7
0
–15
SOURCE OR DRAIN VOLTAGE (V)
ON RESISTANCE (Ω)
15
TA = +25°C
TA = +85°C
TA = –40°C
TA = +125°C
VDD = +15V
VSS = –15V
6
5
4
3
2
1
–10 –5 0 5 10
06181-010
12
0
–5
SOURCE OR DRAIN VOLTAGE (V)
ON RESISTANCE (Ω)
5
06181-007
Figure 8. On Resistance as a Function of VD (VS), Dual Supply
5
9
6
7
8
0
ON RESISTANCE (Ω)
4
3
2
1
–7 –4–5–6 7
SOURCE OR DRAIN VOLTAGE (V)
–3 –2 –1 0 54312 6
V
DD
= +7V, V
SS
= –7V
V
DD
= +5.5V, V
SS
= –5.5V
V
DD
= +5V, V
SS
= –5V
V
DD
= +4.5V, V
SS
= –4.5V
T
A
= 25°C
06181-008
Figure 9. On Resistance as a Function of VD (VS), Dual Supply
12
13
0
ON RESISTANCE (Ω)
11
10
9
8
7
6
5
4
3
2
1
0
SOURCE OR DRAIN VOLTAGE (V)
1 2 3 4 5 6 7 8 9 10 11 12 13
VDD = 12V
VDD = 13.2V
VDD = 10.8V
VDD = 8V
VDD = 5V
TA = 25°C
VSS = 0V
06181-009
Figure 10. On Resistance as a Function of VD (VS), Single Supply
Figure 11. On Resistance as a Function of VD (VS) for Different Temperatures,
±15 V Dual Supply
10
8
6
4
2
–4–3–2–101234
T
A
= +25°C
T
A
= +85°C
T
A
= –40°C
T
A
= +125°C
V
DD
= +5V
V
SS
= –5V
06181-011
10
0
0
ON RESISTANCE (Ω)
12
Figure 12. On Resistance as a Function of VD (VS) for Different Temperatures,
±5 V Dual Supply
SOURCE OR DRAIN VOLTAGE (V)
9
8
7
6
5
4
3
2
1
246810
T
A
= +25°C
T
A
= +85°C
T
A
= –40°C
T
A
= +125°C
V
DD
= 12V
V
SS
= 0V
181-01206
Figure 13. On Resistance as a Function of VD (VS) for Different Temperatures,
12 V Single Supply
ADG1433/ADG1434
Rev. C | Page 11 of 20
1600
1400
1000
1200
800
600
400
200
0
–200
120100806040200
LEAKAGE CURRENTS (pA)
013
70
0
014
LOGIC, INx (V)
I
DD
(µA)
TEMPERATURE (°C)
06181-
V
DD
= +15V
V
SS
= –15V
V
BIAS
= +10V/–10V 60
50
40
30
20
10
24681012
I
S
(OFF) + –
I
S
(OFF) – +
I
D
,I
S
(ON) – –
I
D
,I
S
(ON) + +
V
DD
= +15V
V
SS
= –15V
V
DD
= +12V
V
SS
= 0V
V
DD
= +5V
V
SS
= –5V
I
DD
PER CHANNEL
T
A
= 25°C
06181-015
200
–200
–150
–100
–50
0
50
100
150
–15 151050–5–10
V
S
(V)
CHARGE INJECTION (pC)
Figure 14. Leakage Currents as a Function of Temperature, ±15 V Dual Supply
1600
1400
1000
1200
800
600
400
200
0
–200
120100806040200
LEAKAGE CURRENTS (pA)
1-014
TEMPERATURE (°C)
0618
V
DD
= +5V
V
SS
= –5V
V
BIAS
= +4.5V/–4.5V
I
S
(OFF) + –
I
S
(OFF) – +
I
D
,I
S
(ON) – –
I
D
,I
S
(ON) + +
Figure 15. Leakage Currents as a Function of Temperature, ±5 V Dual Supply
2000
1600
1800
1400
1000
1200
800
600
400
200
LEAKAGE CURRENTS (pA)
0
–200
120100806040200
TEMPERATURE (°C)
06181-020
V
DD
= 12V
V
SS
= 0V
V
BIAS
= 1V/10V
I
S
(OFF) + –
I
D
,I
S
(ON) – –
I
D
,I
S
(ON) + +
I
S
(OFF) – +
Figure 16. Leakage Currents as a Function of Temperature,
12 V Single Supply
Figure 17. IDD vs. Logic Level
T
A
= 25°C
V
DD
= +15V
V
SS
= –15V
V
DD
= +5V
V
SS
= –5V
V
DD
= +12V
V
SS
= 0V
06181-016
Figure 18. Charge Injection vs. Source Voltage
350
300
250
200
150
100
50
0
TIME (ns)
V
DD
= +15V
V
SS
= –15V
V
DD
= +5V
V
SS
= –5V V
DD
= +12V
V
SS
= 0V
120100806040200–20–40
TEMPERATURE (°C)
06181-017
Figure 19. Transition Time vs. Temperature
ADG1433/ADG1434
Rev. C | Page 12 of 20
0
–110
1k 1G
OFF ISOLATION (dB)
FREQUENCY (Hz)
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
10k 100k 1M 10M 100M
V
DD
= +15V
V
SS
= –15V
T
A
= 25°C
01806181-
Figure 20. Off Isolation vs. Frequency
0
–110
1k 1G
CROSSTALK (dB)
FREQUENCY (Hz)
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
10k 100k 1M 10M 100M
V
DD
= +15V
V
SS
= –15V
T
A
= 25°C
06181-
0
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
ON RESPONSE (dB)
019
–4.0
–3.5
100 1G100M10M1M100k10k1k
FREQUENCY (Hz)
Figure 21. Crosstalk vs. Frequency
V
DD
= +15V
V
SS
= –15V
T
A
= 25°C
06181-100
Figure 22. On Response vs. Frequency
0
10 100k
FREQUENCY (Hz)
THD + N (%)
0.09
0.10
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
100 1k 10k
LOAD = 110Ω
T
A
= 25°C
V
DD
= +5V, V
SS
= –5V, V
S
= +5V p-p
V
DD
= +15V, V
SS
= –15V, V
S
= +15V p-p
06181-032
Figure 23. THD + N vs. Frequency
0
100 1k 10M
FREQUENCY (Hz)
ACPSRR (dB)
–20
–40
–60
–80
–100
–120
10k 100k 1M
VDD = +15V
VSS = –15V
TA = 25°C
V p-p = 0.63V
NO DECOUPLING
CAPACITORS
DECOUPLING
CAPACITORS
ON SUPPLIES
06181-035
Figure 24. ACPSRR vs. Frequency
ADG1433/ADG1434
Rev. C | Page 13 of 20
TEST CIRCUITS
I
DS
SD
V
S
V
06181-021
Figure 25. On Resistance
SD
I
S
(OFF) I
D
(OFF)
A A
V
V
DS
06181-022
Figure 26. Off Leakage
SD
I
D
(ON)
A
V
D
NC
NC = NO CONNECT
06181-023
Figure 27. On Leakage
IN
V
OUT
V
V
DD SS
D
SA
V
DD
V
SS
GND
C
L
35pF
SB
V
S
V
IN
0.1µF0.1µF V
IN
50%
50%
90%
50%
50%
90%
t
ON
t
OFF
R
L
100Ω
V
IN
V
OUT
06181-024
Figure 28. Switching Timing
IN
V
OUT
V
V
DD SS
D
SA
V
DD
V
SS
GND
C
L
35pF
SB
V
S
V
IN
0.1µF0.1µF
R
L
100Ω
80%
V
OUT
V
IN
t
BBM
t
BBM
06181-025
Figure 29. Break-Before-Make Delay, tD
EN
V
INx
V
DD
V
SS
DD
V
SS
ADG1433
GND
INx
S1B
S1A
V
IN
0.1µF0.1µF
INx
V
S
50% 50%
V
0V
ENABLE
DRIVE (V
IN
)
3V
0.9V
OUT
0.9V
OUT
t
ON
(EN)
OUT
0V
OUTPUT
V
OUT
D1
C
L
35pF
t
OFF
(EN)
R
L
100Ω
50Ω
06181-026
Figure 30. Enable Delay, tON (EN), tOFF (EN)
ADG1433/ADG1434
Rev. C | Page 14 of 20
V
IN
(NORMALLY
CLOSED SWITCH)
V
OUT
V
IN
(NORMALLY
OPEN SWITCH)
OFF
ΔV
OUT
ON
Q
INJ
= C
L
× ΔV
OUT
IN
V
OUT
NC
V
V
DD SS
SA
V
DD
V
SS
GND
C
L
1nF
D
V
IN
V
S
0.1µF0.1µF
SB
06181-027
Figure 31. Charge Injection
V
V
VOUT
50Ω
NETWORK
ANALYZER
RL
50Ω
IN
V
IN
SA
D
VS
VDD VSS
0.1µF
V
DD
0.1µF
V
SS
GND
50Ω
NC
SB
OFF ISOLATION = 20 log VOUT
VS
0
6181-028
Figure 32. Off Isolation
VOUT
50Ω
NETWORK
ANALYZER
RL
50Ω
IN
V
IN
SA
D
VS
VDD VSS
0.1µF
V
DD
0.1µF
V
SS
GND
50Ω
NC
SB
INSERTION LOSS = 20 log VOUT WITH SWITCH
VOUT WITHOUT SWITCH
06181-029
Figure 33. Bandwidth
CHANNEL-TO-CHANNEL CROSSTALK = 20 log VOUT
GND
SA
D
SB
VOUT
NETWORK
ANALYZER
RL
50Ω
R
50Ω
VS
VS
VDD VSS
DD
0.1µF
SS
0.1µF
IN
06181-030
Figure 34. Channel-to-Channel Crosstalk
V
V
DD
V
OUT
R
S
AUDIO PRECISION
R
L
110Ω
IN
V
IN
S
D
V
S
V p-p
V
DD
V
SS
0.1µF
SS
0.1µF
GND
06181-031
Figure 35. THD + Noise
ADG1433/ADG1434
Rev. C | Page 15 of 20
TERMINOLOGY
RON
Ohmic resistance between Terminal D and Terminal S.
ΔRON
The difference between the RON of any two channels.
RFLAT(ON)
The difference between the maximum and minimum value of
on resistance as measured.
IS (Off)
Source leakage current when the switch is off.
ID (Off)
Drain leakage current when the switch is off.
ID, IS (On)
Channel leakage current when the switch is on.
VD (VS)
Analog voltage on Terminal D and Terminal S.
CS (Off)
Channel input capacitance for off condition.
CD (Off)
Channel output capacitance for off condition.
CD, CS (On)
On switch capacitance.
CIN
Digital input capacitance.
tON (EN)
Delay time between the 50% and 90% points of the digital input
and switch on condition.
tOFF (EN)
Delay time between the 50% and 90% points of the digital input
and switch off condition.
tTRANS
Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from one
address state to another.
tBBM
Off time measured between the 80% point of both switches
when switching from one address state to another.
VIL
Maximum input voltage for Logic 0.
VIH
Minimum input voltage for Logic 1.
IIL (IIH)
Input current of the digital input.
IDD
Positive supply current.
ISS
Negative supply current.
Off Isolation
A measure of unwanted signal coupling through an off channel.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
Bandwidth
The frequency at which the output is attenuated by 3 dB.
On Response
The frequency response of the on switch.
Total Harmonic Distortion + Noise (THD + N)
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.
AC Power Supply Rejection Ratio (ACPSRR)
A measure of the ability of a part to avoid coupling noise
and spurious signals that appear on the supply voltage pin
to the output of the switch. The dc voltage on the device is
modulated by a sine wave of 0.62 V p-p. The ratio of the
amplitude of signal on the output to the amplitude of the
modulation is the ACPSRR.
ADG1433/ADG1434
Rev. C | Page 16 of 20
OUTLINE DIMENSIONS
16 9
81
4.50
4.40
4.30
PIN 1
SEATING
PLANE
8°
0°
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX
0.20
0.09 0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
COMPLIANT
TO
JEDEC STANDARDS MO-220-VGGC.
Figure 36. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
1
0.65
BSC
0.60 MAX
PIN 1
INDICATOR
1.95 BCS
0.50
0.40
0.30
0.25 MIN
3.75
BSC SQ
TOP VIEW
12° MAX 0.80 MAX
0.65 TYP
SEATING
PLANE
PIN 1
INDI
C
ATOR
COPLANARITY
0.08
1.00
0.85
0.80
0.30
0.23
0.18
0.05 MAX
0.02 NOM
0.20 REF
4.00
BSC SQ
2.65
2.50 SQ
2.35
16
5
13
8
9
12
4
EXPOSED
PAD
BOTTOM VIEW
031006-A
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 37. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-16-13)
Dimensions shown in millimeters
ADG1433/ADG1434
Rev. C | Page 17 of 20
COMPLIANT TO JEDEC STANDARDS MO-153-AC
20
1
11
10
6.40 BSC
4.50
4.40
4.30
PIN 1
6.60
6.50
6.40
SEATING
PLANE
0.15
0.05
0.30
0.19
0.65
BSC
1.20 MAX 0.20
0.09 0.75
0.60
0.45
8°
0°
COPLANARIT
Y
0.10
Figure 38. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
2.65
2.50 SQ
2.35
3.75
BSC SQ
4.00
BSC SQ
1
0.50
BSC
PIN 1
INDICATOR
0.50
0.40
0.30
COMPLIANT
TO
JEDEC STANDARDS MO-220-VGGD-1
090408-B
TOP VIEW
12° MAX 0.80 MAX
0.65 TYP
SEATING
PLANE
PIN 1
INDI
C
ATOR
COPLANARITY
0.08
1.00
0.85
0.80
0.30
0.23
0.18
0.05 MAX
0.02 NOM
0.20 REF
20
6
16
10
11
15
5
EXPOSED
PAD
(BOTTOM VIEW)
0.60 MAX
0.60 MAX
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 39. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-20-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Description EN Pin Package Option
ADG1433YRUZ1−40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] Yes RU-16
ADG1433YRUZ-REEL1−40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] Yes RU-16
ADG1433YRUZ-REEL71−40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] Yes RU-16
ADG1433YCPZ-REEL1−40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Yes CP-16-13
ADG1433YCPZ-REEL71−40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Yes CP-16-13
ADG1434YRUZ1−40°C to +125°C 20-Lead Thin Shrink Small Outline Package [TSSOP] No RU-20
ADG1434YRUZ-REEL1−40°C to +125°C 20-Lead Thin Shrink Small Outline Package [TSSOP] No RU-20
ADG1434YRUZ-REEL71−40°C to +125°C 20-Lead Thin Shrink Small Outline Package [TSSOP] No RU-20
ADG1434YCPZ-REEL1−40°C to +125°C 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Yes CP-20-4
ADG1434YCPZ-REEL71−40°C to +125°C 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Yes CP-20-4
1 Z = RoHS Compliant Part.
ADG1433/ADG1434
Rev. C | Page 18 of 20
NOTES
ADG1433/ADG1434
Rev. C | Page 19 of 20
NOTES
ADG1433/ADG1434
Rev. C | Page 20 of 20
NOTES
©2006–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06181-0-6/09(C)
