CLC1005, CLC1015, CLC2005
Low Cost, +2.7V to 5.5V, 260MHz
Rail-to-Rail Amplifiers
© 2007-2015 Exar Corporation 1 / 19 exar.com/CLC1005
Rev 2D
FEATURES
260MHz bandwidth
Fully specied at +2.7V and +5V supplies
Output voltage range:
0.036V to 4.953V; VS = +5; RL = 2kΩ
Input voltage range:
-0.3V to +3.8V; VS = +5
145V/μs slew rate
4.2mA supply current
Power down to 127μA
±55mA linear output current
±85mA short circuit current
CLC2005 directly replaces AD8052/42/92
in single supply applications
CLC1005 directly replaces AD8051/41/91
in single supply applications
APPLICATIONS
A/D driver
Active lters
CCD imaging systems
CD/DVD ROM
Coaxial cable drivers
High capacitive load driver
Portable/battery-powered applications
Twisted pair driver
Telecom and optical terminals
Video driver
Interactive whiteboards
General Description
The CLC1005 (single), CLC1015 (single with disable), and CLC2005 (dual)
are low cost, voltage feedback ampliers. These ampliers are designed
to operate on +2.7V to +5V, or ±2.5V supplies. The input voltage range
extends 300mV below the negative rail and 1.2V below the positive rail.
The CLC1005, CLC1015, and CLC2005 offer superior dynamic performance
with 260MHz small signal bandwidth and 145V/μs slew rate. The ampliers
consume only 4.2mA of supply current per channel and the CLC1015 offers
a disable supply current of only 127μA. The combination of low power, high
output current drive, and rail-to-rail performance make these ampliers well
suited for battery-powered communication/computing systems.
The combination of low cost and high performance make the CLC1005,
CLC1015, and CLC2005 suitable for high volume applications in both
consumer and industrial applications such as interactive whiteboards,
wireless phones, scanners, color copiers, and video transmission.
Output Swing
Output Voltage (0.5V/div)
Time (0.5μs/div)
2.7
0
Vs = +2.7V
RL = 2kΩ
G = -1
2nd & 3rd Harmonic Distortion; VS = +2.7V
Distortion (dBc)
Frequency (MHz)
0510 15
2nd
RL = 150Ω
20
3rd
RL = 150Ω
3rd
RL = 2kΩ
2nd
RL = 2kΩ
-90
-80
-70
-60
-50
-40
-30
-20 Vo = 1Vpp
Rf = 1kΩ
Ordering Information - backpage
© 2007-2015 Exar Corporation 2 / 19 exar.com/CLC1005
Rev 2D
CLC1005, CLC1015, CLC2005
Absolute Maximum Ratings
Stresses beyond the limits listed below may cause
permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect
device reliability and lifetime.
VS ................................................................................... 0V to +6V
VIN ............................................................ -VS - 0.5V to +VS +0.5V
Operating Conditions
Supply Voltage Range ...................................................2.5 to 5.5V
Operating Temperature Range .................................-40°C to 85°C
Junction Temperature ...........................................................150°C
Storage Temperature Range ...................................-65°C to 150°C
Lead Temperature (Soldering, 10s) ......................................260°C
Package Thermal Resistance
θJA (SOIC-8) .....................................................................150°C/W
θJA (MSOP-8) .................................................................. 200°C/W
θJA (TSOT23-5) ................................................................215°C/W
θJA (TSOT23-6) ................................................................192°C/W
Package thermal resistance (θJA), JEDEC standard, multi-layer
test boards, still air.
ESD Protection
SOIC-8 (HBM) .......................................................................2.5kV
ESD Rating for HBM (Human Body Model) and CDM (Charged
Device Model).
© 2007-2015 Exar Corporation 3 / 19 exar.com/CLC1005
Rev 2D
CLC1005, CLC1015, CLC2005
Electrical Characteristics at +2.7V
TA = 25°C, VS = +2.7V, Rf = 2kΩ, RL = 2kΩ to VS/2; G = 2; unless otherwise noted.
Symbol Parameter Conditions Min Ty p Max Units
Frequency Domain Response
GBWP -3dB Gain Bandwidth Product 86 MHz
UGBW Unity Gain Bandwidth(1) G = +1, VOUT = 0.05Vpp 215 MHz
BWSS -3dB Bandwidth G = +2, VOUT = 0.2Vpp 85 MHz
BWLS Large Signal Bandwidth G = +2, VOUT = 2Vpp 36 MHz
Time Domain
tR, tFRise and Fall Time (1) VOUT = 0.2V step; (10% to 90%) 3.7 ns
tSSettling Time to 0.1% VOUT = 1V step 40 ns
OS Overshoot VOUT = 0.2V step 9 %
SR Slew Rate G = -1, 2.7V step 130 V/μs
Distortion/Noise Response
HD2 2nd Harmonic Distortion (1) 5MHz, VOUT = 1Vpp 79 dBc
HD3 3rd Harmonic Distortion (1) 5MHz, VOUT = 1Vpp 82 dBc
THD Total Harmonic Distortion (1) 5MHz, VOUT = 1Vpp 77 dB
enInput Voltage Noise >1MHz 16 nV/√Hz
inInput Current Noise >1MHz 1. 3 pA/√Hz
XTALK Crosstalk(1) CLC2005, 10MHz 65 dB
DC Performance
VIO Input Offset Voltage -1.6 mV
dVIO Average Drift 10 μV/°C
IBInput Bias Current 3 μA
dIBAverage Drift 7 nA/°C
IOS Input Offset Current 0.1 μA
PSRR Power Supply Rejection Ratio DC 52 57 dB
AOL Open Loop Gain 75 dB
ISSupply Current 3.9 mA
Disable Characteristics (CLC1015)
TON Turn On Time 150 ns
TOFF Turn Off Time 25 ns
OFFISO Off Isolation 5MHz, RL = 100Ω 75 dB
ISD Disable Supply Current DIS tied to GND 58 100 μA
Input Characteristics
RIN Input Resistance 4.3 MΩ
CIN Input Capacitance 1. 8 pF
CMIR Common Mode Input Range -0.3 to 1.5 V
CMRR Common Mode Rejection Ratio DC, VCM = 0 to VS - 1.5V 87 dB
Output Characteristics
VOUT Output Swing
RL = 10kΩ to VS / 2 0.023 to
2.66 V
RL = 2kΩ to VS / 2 0.025 to
2.653 V
RL = 150Ω to VS / 2 0.065 to
2.55 V
IOUT Output Current ±55 mA
-40°C to +85°C ±50 mA
ISC Short Circuit Current VOUT = VS / 2 ±85 mA
VSPower Supply Operating Range 2.5 2.7 5.5 V
Notes:
1. Rf = 1kΩ was used for optimal performance. (For G = +1, Rf = 0)
© 2007-2015 Exar Corporation 4 / 19 exar.com/CLC1005
Rev 2D
CLC1005, CLC1015, CLC2005
Electrical Characteristics at +5V
TA = 25°C, VS = +5V, Rf = 2kΩ, RL = 2kΩ to VS/2; G = 2; unless otherwise noted.
Symbol Parameter Conditions Min Ty p Max Units
Frequency Domain Response
GBWP -3dB Gain Bandwidth Product 90 MHz
UGBW Unity Gain Bandwidth(1) G = +1, VOUT = 0.05Vpp 260 MHz
BWSS -3dB Bandwidth G = +2, VOUT = 0.2Vpp 90 MHz
BWLS Large Signal Bandwidth G = +2, VOUT = 2Vpp 40 MHz
Time Domain
tR, tFRise and Fall Time (1) VOUT = 0.2V step 3.6 ns
tSSettling Time to 0.1% VOUT = 2V step 40 ns
OS Overshoot VOUT = 0.2V step 7 %
SR Slew Rate G = -1, 5V step 145 V/μs
Distortion/Noise Response
HD2 2nd Harmonic Distortion (1) 5MHz, VOUT = 2Vpp 71 dBc
HD3 3rd Harmonic Distortion (1) 5MHz, VOUT = 2Vpp 78 dBc
THD Total Harmonic Distortion (1) 5MHz, VOUT = 2Vpp 70 dB
DG Differential Gain NTSC (3.85MHz), AC-Coupled, RL = 150Ω 0.06 %
NTSC (3.85MHz), DC-Coupled, RL = 150Ω 0.08 %
DP Differential Phase NTSC (3.85MHz), AC-Coupled, RL = 150Ω 0.07 °
NTSC (3.85MHz), DC-Coupled, RL = 150Ω 0.06 °
enInput Voltage Noise >1MHz 16 nV/√Hz
inInput Current Noise >1MHz 1. 3 pA/√Hz
XTALK Crosstalk(1) CLC2005, 10MHz 62 dB
DC Performance
VIO Input Offset Voltage -8 1. 4 8 mV
dVIO Average Drift 10 μV/°C
IBInput Bias Current -8 3 8 μA
dIBAverage Drift 7 nA/°C
IOS Input Offset Current -0.8 0.1 0.8 μA
PSRR Power Supply Rejection Ratio DC 52 57 dB
AOL Open Loop Gain 68 78 dB
ISSupply Current 4.2 5.2 mA
Disable Characteristics (CLC1015)
TON Turn On Time 150 ns
TOFF Turn Off Time 25 ns
OFFISO Off Isolation 5MHz, RL = 100Ω 75 dB
ISD Disable Supply Current DIS tied to GND 127 170 μA
Input Characteristics
RIN Input Resistance 4.3 MΩ
CIN Input Capacitance 1. 8 pF
CMIR Common Mode Input Range -0.3 to
3.8 V
CMRR Common Mode Rejection Ratio DC, VCM = 0 to VS - 1.5V 72 87 dB
© 2007-2015 Exar Corporation 5 / 19 exar.com/CLC1005
Rev 2D
CLC1005, CLC1015, CLC2005
Electrical Characteristics at +5V Continued
TA = 25°C, VS = +5V, Rf = 2kΩ, RL = 2kΩ to VS/2; G = 2; unless otherwise noted.
Symbol Parameter Conditions Min Ty p Max Units
Output Characteristics
VOUT Output Swing
RL = 10kΩ to VS / 2 0.027 to
4.97 V
RL = 2kΩ to VS / 2 0.036 to
4.953 V
RL = 150Ω to VS / 2 0.3 0.12 to
4.8 4.625 V
IOUT Output Current ±55 mA
-40°C to +85°C ±50 mA
ISC Short Circuit Current VOUT = VS / 2 ±85 mA
VSPower Supply Operating Range 2.5 5 5.5 V
Notes:
1. Rf = 1kΩ was used for optimal performance. (For G = +1, Rf = 0)
© 2007-2015 Exar Corporation 6 / 19 exar.com/CLC1005
Rev 2D
CLC1005, CLC1015, CLC2005
CLC1015 Pin Assignments
TSOT-6
Pin No. Pin Name Description
1 OUT Output
2 -VSNegative supply
3 +IN Positive input
4 -IN Negative input
5 DIS
Disable pin. Enabled if pin is left open or tied
to +VS, disabled if pin is tied to -VS (which is
GND in a single supply application.)
6 +VSPositive supply
CLC1015 Pin Congurations
TSOT-6
-
+
2
3
6
4
+IN
+Vs
5DIS
-IN
1
-Vs
OUT
SOIC-8
Pin No. Pin Name Description
1 NC No Connect
2 -IN Negative input
3 +IN Positive input
4 -VSNegative supply
5 NC No Connect
6 OUT Output
7 +VSPositive supply
8 NC No Connect
SOIC-8
-
+
1
2
3
4
NC
-IN
+IN
-Vs
NC
+Vs
OUT
NC
8
7
6
5
CLC1005 Pin Assignments
TSOT-5
Pin No. Pin Name Description
1 OUT Output
2 -VSNegative supply
3 +IN Positive input
4 -IN Negative input
5 +VSPositive supply
CLC1005 Pin Congurations
TSOT-5
-
+
2
3
5
4
+IN
+Vs
-IN
1
-Vs
OUT
© 2007-2015 Exar Corporation 7 / 19 exar.com/CLC1005
Rev 2D
CLC1005, CLC1015, CLC2005
CLC2005 Pin Assignments
SOIC-8 / MSOP-8
Pin No. Pin Name Description
1 OUT1 Output, channel 1
2 -IN1 Negative input, channel 1
3 +IN1 Positive input, channel 1
4 -VSNegative supply
5 +IN2 Positive input, channel 2
6 -IN2 Negative input, channel 2
7 OUT2 Output, channel 2
8 +VSPositive supply
CLC2005 Pin Conguration
SOIC-8 / MSOP-8
-
+
-
+
1
2
3
4
OUT1
-IN1
+IN1
-Vs
+Vs
OUT2
-IN2
+IN2
8
7
6
5
© 2007-2015 Exar Corporation 8 / 19 exar.com/CLC1005
Rev 2D
CLC1005, CLC1015, CLC2005
Typical Performance Characteristics
TA = 25°C, VS = +5V, RL = 2kΩ to VS/2, G = +2, RF = 2kΩ; unless otherwise noted.
Frequency Response vs CL Large Signal Frequency Response
Non-Inverting Frequency Response VS = +2.7V Inverting Frequency Response VS = +2.7V
Non-Inverting Frequency Response VS = +5V Inverting Frequency Response VS = +5V
Normalized Magnitude (2dB/div)
Frequency (MHz)
0.1 1
G = 10
Rf = 2kΩ
10 100
G = 5
Rf = 2kΩ
G = 1
Rf = 0
G = 2
Rf = 1kΩ
Normalized Magnitude (1dB/div)
Frequency (MHz)
0.1 1
G = -10
Rf = 2kΩ
10 100
G = -5
Rf = 2kΩ
G = -2
Rf = 2kΩ
G = -1
Rf = 2kΩ
Normalized Magnitude (2dB/div)
Frequency (MHz)
110 100
0.1
G = 10
Rf = 2kΩ
G = 5
Rf = 2kΩ
G = 1
Rf = 0
G = 2
Rf = 1kΩ
Normalized Magnitude (1dB/div)
Frequency (MHz)
0.1 1
G = -10
Rf = 2kΩ
10 100
G = -5
Rf = 2kΩ
G = -2
Rf = 2kΩ
G = -1
Rf = 2kΩ
Magnitude (1dB/div)
Frequency (MHz)
0.1 110 100
CL = 100pF
Rs = 25Ω
CL = 50pF
Rs = 33Ω
CL = 20pF
Rs = 20Ω
CL = 10pF
Rs = 0Ω
+
-1kW
1kW
Rs
CLRL
Magnitude (1dB/div)
Frequency (MHz)
0.1 110 100
Vo = 1Vpp
Vo = 2Vpp
© 2007-2015 Exar Corporation 9 / 19 exar.com/CLC1005
Rev 2D
CLC1005, CLC1015, CLC2005
Typical Performance Characteristics
TA = 25°C, VS = +5V, RL = 2kΩ to VS/2, G = +2, RF = 2kΩ; unless otherwise noted.
2nd Harmonic Distortion vs VO 3rd Harmonic Distortion vs VO
2nd & 3rd Harmonic Distortion VS = +5V 2nd & 3rd Harmonic Distortion VS = +2.7V
Frequency Response vs. Temperature Input Voltage Noise vs Frequency
Magnitude (0.5dB/div)
Frequency (MHz)
110 100
Voltage Noise (nV/√Hz)
Frequency (Hz)
1k 10k 100k 1M
0
10
20
30
40
50
60
70
80
90
100
Distortion (dBc)
Frequency (MHz)
0510 15
3rd
RL = 150Ω
20
2nd
RL = 150Ω
3rd
RL = 2kΩ
2nd
RL = 2kΩ
-90
-80
-70
-60
-50
-40
-30
-20 Vo = 2Vpp
Rf = 1kΩ
Distortion (dBc)
Frequency (MHz)
0510 15
2nd
RL = 150Ω
20
3rd
RL = 150Ω
3rd
RL = 2kΩ
2nd
RL = 2kΩ
-90
-80
-70
-60
-50
-40
-30
-20 Vo = 1Vpp
Rf = 1kΩ
Distortion (dBc)
Output Amplitude (Vpp)
0.5 1. 0 1. 5 2.0
20MHz
10MHz
5MHz
2.5
-90
-80
-70
-60
-50
-40
-30
-20
Rf = 1kΩ
2MHz
Distortion (dBc)
Output Amplitude (Vpp)
0.5 1. 0 1. 5 2.0
20MHz
10MHz
5MHz
2.5
-90
-80
-70
-60
-50
-40
-30
-20 Rf = 1kΩ
2MHz
© 2007-2015 Exar Corporation 10 / 19 exar.com/CLC1005
Rev 2D
CLC1005, CLC1015, CLC2005
Typical Performance Characteristics
TA = 25°C, VS = +5V, RL = 2kΩ to VS/2, G = +2, RF = 2kΩ; unless otherwise noted.
Small Signal Pulse Response VS = +5V Small Signal Pulse Response VS = +2.7V
Open Loop Gain & Phase vs. Frequency Output Current
PSRR CMRR
PSRR (dB)
Frequency (MHz)
1k 0.01 0.1 1100
-70
-60
-50
-40
-30
-20
-10
0
10
CMRR (dB)
Frequency (MHz)
0.01 0.1 1. 0 10 100
-90
-80
-70
-60
-50
-40
Open Loop Gain (dB)
Frequency (MHz)
-20
-10
0
10
20
-180
-135
-90
-45
0
30
40
50
60
70
80
0.01 0.1 1 10 100
Phase (degrees)
|Gain|
Phase
Output Voltage (V)
Output Current (mA)
-100 -50 050 100
Linear output current ±55mA
-0.8
-0.6
-0.2
0
0.2
0.4
0.6
0.8
-0.4 Short circuit current ±85mA
Output Voltage (0.05V/div)
Time (20ns/div)
Rf = 1kΩ
Output Voltage (0.05V/div)
Time (20ns/div)
Rf = 1kΩ
© 2007-2015 Exar Corporation 11 / 19 exar.com/CLC1005
Rev 2D
CLC1005, CLC1015, CLC2005
Typical Performance Characteristics
TA = 25°C, VS = +5V, RL = 2kΩ to VS/2, G = +2, RF = 2kΩ; unless otherwise noted.
Channel Matching VS = +5V
Large Signal Pulse Response VS = +5V Output Swing
Output Voltage (0.5V/div)
Time (20ns/div)
Rf = 1kΩ
Output Voltage (0.5V/div)
Time (0.5μs/div)
2.7
0
Vs = +2.7V
RL = 2kΩ
G = -1
Magnitude (0.5dB/div)
Frequency (MHz)
0.1 110 100
Channel 1
Rf = 1kΩ
RL = 2kΩ
G = 2
Channel 2
© 2007-2015 Exar Corporation 12 / 19 exar.com/CLC1005
Rev 2D
CLC1005, CLC1015, CLC2005
Application Information
General Description
The CLC1005, CLC1015, and CLC2005 are single supply,
general purpose, voltage-feedback ampliers fabricated
on a complementary bipolar process using a patented
topography. They feature a rail-to-rail output stage and are
unity gain stable. Both gain bandwidth and slew rate are
insensitive to temperature.
The common mode input range extends to 300mV below
ground and to 1.2V below Vs. Exceeding these values will
not cause phase reversal. However, if the input voltage
exceeds the rails by more than 0.5V, the input ESD devices
will begin to conduct. The output will stay at the rail during
this overdrive condition.
The design is short circuit protected and offers “soft”
saturation protection that improves recovery time.
Figures 1, 2, and 3 illustrate typical circuit congurations for
non-inverting, inverting, and unity gain topologies for dual
supply applications. They show the recommended bypass
capacitor values and overall closed loop gain equations. Figure
4 shows the typical non-inverting gain circuit for single supply
applications.
+
-
Rf
0.1μF
6.8μF
Output
G = 1 + (Rf/Rg)
Input
+Vs
-Vs
Rg
0.1μF
6.8μF
RL
Figure 1: Typical Non-Inverting Gain Circuit
+
-
Rf
0.1μF
6.8μF
Output
G = - (Rf/Rg)
For optimum input offset
voltage set R1 = Rf || Rg
Input
+Vs
-Vs
0.1μF
6.8μF
RL
Rg
R1
Figure 2: Typical Inverting Gain Circuit
+
-
0.1μF
6.8μF
Output
G = 1
Input
+Vs
-Vs
0.1μF
6.8μF
RL
Figure 3: Unity Gain Circuit
+
-Rf
0.1μF
6.8μF
Out
In
+Vs
+
Rg
Figure 4: Single Supply Non-Inverting Gain Circuit
At non-inverting gains other than G = +1, keep Rg below 1kΩ
to minimize peaking; thus for optimum response at a gain of
+2, a feedback resistor of 1kΩ is recommended. Figure 5
illustrates the CLC1005, CLC1015 and CLC2005 frequency
response with both 1kΩ and 2kΩ feedback resistors.
Magnitude (1dB/div)
Frequency (MHz)
110 100
Rf = 2kΩ
Rf = 1kΩ
G = 2
RL = 2kΩ
Vs = +5V
Figure 5: Frequency Response vs. Rf
© 2007-2015 Exar Corporation 13 / 19 exar.com/CLC1005
Rev 2D
CLC1005, CLC1015, CLC2005
Overdrive Recovery
For an amplier, an overdrive condition occurs when the
output and/or input ranges are exceeded. The recovery time
varies based on whether the input or output is overdriven
and by how much the ranges are exceeded. The CLC1005,
CLC1015, and CLC2005 will typically recover in less than
20ns from an overdrive condition. Figure 6 shows the
CLC2005 in an overdriven condition.
Input Voltage (0.5V/div)
Time (20ns/div)
Output
Input
RL = 2kΩ
Vin =2Vpp
G = 5
Rf = 1kΩ
Figure 6: Overdrive Recovery
Enable/Disable Function
The CLC1015 offers an active-low disable pin that can be
used to lower its supply current. Leave the pin oating to
enable to part. Pull the disable pin to the negative supply
(which is ground in a single supply application) to disable
the output. During the disable condition, the nominal supply
current will drop below 127μA and the output will be at a
high impedance with about 2pF capacitance.
Power Dissipation
Power dissipation should not be a factor when operating
under the stated 2kΩ load condition. However, applications
with low impedance, DC coupled loads should be analyzed
to ensure that maximum allowed junction temperature is
not exceeded. Guidelines listed below can be used to verify
that the particular application will not cause the device to
operate beyond it’s intended operating range.
Maximum power levels are set by the absolute maximum
junction rating of 150°C. To calculate the junction
temperature, the package thermal resistance value ThetaJA
(θJA) is used along with the total die power dissipation.
TJunction = TAmbient + (θJA × PD)
Where TAmbient is the temperature of the working
environment.
In order to determine PD, the power dissipated in the load
needs to be subtracted from the total power delivered by the
supplies.
PD = Psupply - Pload
Supply power is calculated by the standard power equation.
Psupply = Vsupply × IRMSsupply
Vsupply = VS+ - VS-
Power delivered to a purely resistive load is:
Pload = ((Vload)RMS2)/Rloadeff
The effective load resistor (Rloadeff) will need to include the
effect of the feedback network. For instance,
Rloadeff in Figure 3 would be calculated as:
RL || (Rf + Rg)
These measurements are basic and are relatively easy to
perform with standard lab equipment. For design purposes
however, prior knowledge of actual signal levels and load
impedance is needed to determine the dissipated power.
Here, PD can be found from
PD = PQuiescent + PDynamic - Pload
Quiescent power can be derived from the specied IS values
along with known supply voltage, Vsupply. Load power can
be calculated as above with the desired signal amplitudes
using:
(Vload)RMS = Vpeak / √2
( Iload)RMS = ( Vload)RMS / Rloadeff
The dynamic power is focused primarily within the output
stage driving the load. This value can be calculated as:
PDynamic = (VS+ - Vload)RMS × ( Iload)RMS
Assuming the load is referenced in the middle of the power
rails or Vsupply/2.
The CLC1015 is short circuit protected. However, this may
not guarantee that the maximum junction temperature
(+150°C) is not exceeded under all conditions. Figure 7
shows the maximum safe power dissipation in the package
vs. the ambient temperature for the packages available.
© 2007-2015 Exar Corporation 14 / 19 exar.com/CLC1005
Rev 2D
CLC1005, CLC1015, CLC2005
0
0.5
1
1.5
-40 -20 020 40 60 80
Maximum Power Dissipation (W)
Ambient Temperature (°C)
MSOP-8
SOIC-8
TSOT-5
TSOT-6
Figure 7. Maximum Power Derating
Driving Capacitive Loads
Increased phase delay at the output due to capacitive loading
can cause ringing, peaking in the frequency response, and
possible unstable behavior. Use a series resistance, RS,
between the amplier and the load to help improve stability
and settling performance. Refer to Figure 8.
+
-
Rf
Input
Output
Rg
Rs
CLRL
Figure 8. Addition of RS for Driving Capacitive Loads
Table 1 provides the recommended RS for various capacitive
loads. The recommended RS values result in approximately
<1dB peaking in the frequency response.
CL (pF) RS (Ω) -3dB BW (MHz)
22pF 0 118
47pF 15 112
100pF 15 91
492pF 6.5 59
Table 1: Recommended RS vs. CL
For a given load capacitance, adjust RS to optimize the
tradeoff between settling time and bandwidth. In general,
reducing RS will increase bandwidth at the expense of
additional overshoot and ringing.
Layout Considerations
General layout and supply bypassing play major roles in
high frequency performance. Exar has evaluation boards to
use as a guide for high frequency layout and as an aid in
device testing and characterization. Follow the steps below
as a basis for high frequency layout:
Include 6.8µF and 0.1µF ceramic capacitors for power supply
decoupling
Place the 6.8µF capacitor within 0.75 inches of the power pin
Place the 0.1µF capacitor within 0.1 inches of the power pin
Remove the ground plane under and around the part,
especially near the input and output pins to reduce parasitic
capacitance
Minimize all trace lengths to reduce series inductances
Refer to the evaluation board layouts below for more
information.
Evaluation Board Information
The following evaluation boards are available to aid in the
testing and layout of these devices:
Evaluation Board # Products
CEB002 CLC1005 and CLC1015 in TSOT
CEB003 CLC1005 in SOIC
CEB006 CLC2005 in SOIC
CEB010 CLC2005 in MSOP
Evaluation Board Schematics
Evaluation board schematics and layouts are shown in
Figures 9-18. These evaluation boards are built for dual-
supply operation. Follow these steps to use the board in a
single-supply application:
1. Short -VS to ground.
2. Use C3 and C4, if the -VS pin of the amplier is not
directly connected to the ground plane.
© 2007-2015 Exar Corporation 15 / 19 exar.com/CLC1005
Rev 2D
CLC1005, CLC1015, CLC2005
Figure 9. CEB002 and CEB003 Schematic
Figure 10. CEB002 Top View
Figure 11. CEB002 Bottom View
Figure 12. CEB003 Top View
Figure 13. CEB003 Bottom View
© 2007-2015 Exar Corporation 16 / 19 exar.com/CLC1005
Rev 2D
CLC1005, CLC1015, CLC2005
Figure 14. CEB006 & CEB010 Schematic
Figure 15. CEB006 Top View
Figure 16. CEB006 Bottom View
Figure 17. CEB010 Top View
Figure 18. CEB010 Bottom View
© 2007-2015 Exar Corporation 17 / 19 exar.com/CLC1005
Rev 2D
CLC1005, CLC1015, CLC2005
Mechanical Dimensions
TSOT-6 Package
TSOT-5 Package
© 2007-2015 Exar Corporation 18 / 19 exar.com/CLC1005
Rev 2D
CLC1005, CLC1015, CLC2005
MSOP-8 Package
SOIC-8 Package
For Further Assistance:
Email: CustomerSupport@exar.com or HPATechSupport@exar.com
Exar Technical Documentation: http://www.exar.com/techdoc/
Exar Corporation Headquarters and Sales Offices
48760 Kato Road Tel.: +1 (510) 668-7000
Fremont, CA 94538 - USA Fax: +1 (510) 668-7001
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation
assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free
of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specic application. While the information
in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected
to cause failure of the life support system or to signicantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR
Corporation is adequately protected under the circumstances.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
© 2007-2015 Exar Corporation 19 / 19 exar.com/CLC1005
Rev 2D
CLC1005, CLC1015, CLC2005
Ordering Information
Part Number Package Green Operating Temperature Range Packaging
CLC1005 Ordering Information
CLC1005IST5X TSOT-5 Ye s -40°C to +85°C Tape & Reel
CLC1005IST5MTR TSOT-5 Ye s -40°C to +85°C Mini Tape & Reel
CLC1005IST5EVB Evaluation Board N/A N/A N/A
CLC1005ISO8X SOIC-8 Ye s -40°C to +85°C Tape & Reel
CLC1005ISO8MTR SOIC-8 Ye s -40°C to +85°C Mini Tape & Reel
CLC1005ISO8EVB Evaluation Board N/A N/A N/A
CLC1015 Ordering Information
CLC1015IST6X TSOT-6 Ye s -40°C to +85°C Tape & Reel
CLC1015IST6MTR TSOT-6 Ye s -40°C to +85°C Mini Tape & Reel
CLC1015IST6EVB Evaluation Board N/A N/A N/A
CLC2005 Ordering Information
CLC2005ISO8X SOIC-8 Ye s -40°C to +85°C Tape & Reel
CLC2005ISO8MTR SOIC-8 Ye s -40°C to +85°C Mini Tape & Reel
CLC2005ISO8EVB Evaluation Board N/A N/A N/A
CLC2005IMP8X MSOP-8 Ye s -40°C to +85°C Tape & Reel
CLC2005IMP8MTR MSOP-8 Ye s -40°C to +85°C Mini Tape & Reel
CLC2005IMP8EVB Evaluation Board N/A N/A N/A
Moisture sensitivity level for all parts is MSL-1. Mini tape and reel quantity is 250.
Revision History
Revision Date Description
2D (ECN 1513-01) March 2015
Reformat into Exar data sheet template. Updated ordering information table to include MTR and EVB
part numbers. Updated thermal resistance numbers and package outline drawings. Added CLC1015
back into data sheet.