Enpirion® Power Datasheet
EP5357xUI 600mA PowerSoC
Sy nchrono us Buc k Regulat o r
With Integrated In ductor
Description
The EP5357xUI (x = L or H) is a 600mA
PowerSoC. The EP5357xUI integrates MOSFET
switches, control, compensation, and the
magnetics in an advanced 2.5mm x 2.25mm
Q FN Pac kage.
Integrated magnetics enables a tiny solution
footprint, low output ripple, low part-count, and
high reliability, while maintaining high efficiency.
The complete solution can be implemented in as
little as 14mm2.
A proprietary light load mode (LLM) provides high
effic ienc y in light load c onditions .
The EP5357xUI uses a 3-pin VID to easily select
the output voltage setting. Output voltage
settings are available in 2 optimized ranges
providing c overage for typic al VOUT s ettings .
The VID pins can be changed on the fly for fast
dynamic voltage scaling. EP5357LUI further has
the option to us e an external voltage divider.
EP5357xUI
4.7uF
10uF
4.75mm
2.25mm
Figure 1: Total Sol uti on Footpri nt.
Features
• Integrated Inductor Technology
• 2.5mm x 2.25mm x 1.1mm package
• Total Solution Footprint 14mm2
• Low VOUT ripple for RF compatibility
• High efficiency, up to 93%
• 600mA continuous output current
• 55µA quiescent current
• Less than 1µA standby current
• 5 MHz switching frequency
• 3 pin VID for glitc h free voltage s c aling
• VOUT Range 0.6V to VIN – 0.25V
• Short circuit and over c urrent pr otec tion
• UVLO and therm al protec tion
• IC level reliability in a PowerSOC solution
Application
• Wireless and RF applications
• Wir eles s broad band data c ards
• Sm art phone and portable m edia players
• Advanced Low Power Processors, DSP, IO,
Memory, Video, Multimedia Engines
AVIN
PVIN
ENABLE
VSENSE
VOUT
AGND
PGND
10uF
4.7uF EP5357LUI
VS2
VS1
VSO
VFB
LLM
Figure 2: Typica l Appl i ca ti on S che m ati c.
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03409 October 11, 2013 Rev E
EP5357LUI/EP5357HUI
Ordering Information
Part Num ber
Comment
Package
EP5357LUI LOW VID Range 16-pi n QF N T&R
EP5357HUI
HIGH VID Rang e
16-pi n QF N T&R
EVB-EP5357LUI E P5357LUI E val uat i on B oard
EVB-EP5357HUI E P5357HUI E valuati on B oard
Pin Assignments (Top View)
Figure 3: EP5357LUI P i n Out Diagram (Top Vi e w)
Figure 4: EP5357HUI P i n Out Di agra m (Top Vi ew)
Pin Description
PIN
NAME
1, 15,
16 NC(SW)
internal MOSFET s. NC (SW) pins are not to be electricall y connec ted to any external sign al ,
ground, or voltage. However, they must be soldered to the PCB . Failure to follow this
2 PGND
3 LLM
low places the device in f ixed PWM operation. LLM pin should be connect ed to ENA BLE,
4 VFB/NC
5
VSENSE
PVIN
AVIN
ENABLE
VS0
VS1
VS2
NC(SW)
PGND
LLM
VFB
VSENSE
AGND
VOUT
VOUT
NC(SW)
NC(SW)
EP5357LUI
3
1
4
2
6
5
16 15
7 8
12
11
13
10
9
14
PVIN
AVIN
ENABLE
VS0
VS1
VS2
NC(SW)
PGND
LLM
NC
VSENSE
AGND
VOUT
VOUT
NC(SW)
NC(SW)
EP5357HUI
3
1
4
2
6
5
16 15
7 8
12
11
13
10
9
14
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03409 October 11, 2013 Rev E
EP5357LUI/EP5357HUI
PIN
NAME
6 AGND
7, 8
VOUT
9, 10,
11 VS2, VS1,
VS0
EP5357LUI : Selects one of seven preset output voltages or an external resistor divider.
EP5357HUI: Selects one of eight preset output voltages.
12
ENABLE
13
AVIN
14
PVIN
Absolute Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the
recommended operating conditions is not im plied. S tres s beyond the abs olute m axim um ratings m ay
cause permanent damage to the device. Exposure to absolute maximum rated conditions for
extended periods m ay affec t devic e reliability.
PARAMETER
SYMBOL
MIN
MAX
UNITS
I nput Supply Voltage
V
IN
-0.3
6.0
V
Voltages on: ENABLE, VSENSE, VSO – VS2 -0.3 VIN+ 0.3 V
Voltages on: VFB (EP5357LUI) -0.3 2.7 V
Maximum Operating Junc tion T emperature
T
J-ABS
150
°C
Storage T emperature Range
T
STG
-65
150
°C
Ref low T emp, 10 Sec, MSL3 JEDEC J -STD-020C
260
°C
ESD Rating (based on Human Body Mode)
2000
V
Recommended Operating Conditions
PARAMETER
SYMBOL
MIN
MAX
UNITS
I nput Voltage Range
V
IN
2.4
5.5
V
Operating Ambient T emperature
T
A
-40
+85
°C
Operating Junction T emperature
T
J
-40
+125
°C
Thermal Characteristics
PARAMETER
SYMBOL
TYP
UNITS
T hermal Resistance: Junction to A mbient –0 LFM (Note 1)
θ
JA
85
°C/W
T hermal Overload T rip Point
T
J-TP
+155
°C
T hermal Overload T rip Point Hyster esis
25
°C
No te 1 : Based on a four l ayer copper board and proper t hermal desi gn per JEDEC EIJ/JESD51 standards
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03409 October 11, 2013 Rev E
EP5357LUI/EP5357HUI
Electrical Characteristics
NOTE: TA = -40°C to +85°C unless otherwise noted. Typi cal values are at TA = 25°C, VIN = 3.6V .
CIN = 4.7µF MLCC, COUT = 10µF ML CC
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Operating I nput Voltage
Range VIN 2.4 5.5 V
Under Voltage Lock-out –
VIN Rising VUVLO_R 2.0 V
Under Voltage Lock-out –
VIN Falling VUVLO_F 1.9 V
Drop Out Resistance
R
DO
I nput to Output Resistance
350
500
mΩ
Output Voltage Range VOUT EP5357LUI (VDO = I LOAD X RDO)
EP5357HUI 0.6
1.8 VIN-VDO
3.3 V
Dynamic Voltage Slew
Rate VSLEW
EP5357LUI (VID MODE)
EP5357HUI (VID MODE)
4
8 V/mS
VID Preset VOUT Initial
Accuracy ∆VOUT
T
A
= 25°C, V
IN
= 3.6V;
ILOAD = 100mA ;
0.8V ≤ VOUT ≤ 3.3V -2 +2 %
Line Regulation
∆V
OUT_LINE
2.4V ≤ V
IN
≤ 5.5V
0.03
%/V
Load Regulation
∆VOUT_LOAD
0A ≤ I
LOAD
≤ 600mA
0.48
%/A
Temperature Variation ∆VOUT_TEMPL -40°C ≤ TA ≤ +85°C 24 ppm/°C
Output Current
I
OUT
600
mA
Shut-down C urrent
I
SD
Enable = Low
0.75
µA
EP5357HUI Operating
Quiescent Current IQ ILOAD=0; Preset Output Volt ages,
LLM=High 55 µA
EP5357LUI Operating
Quiescent Current IQ ILOAD=0; Preset Output Volt ages,
LLM=High 65 µA
OCP T hreshold ILIM
2.4V ≤ V
IN
≤ 5.5V
0.6V ≤ VOUT ≤ 3.3V 1.4 A
Feedback Pin Volt age
I nitial Accuracy VFB TA = 25°C, VIN = 3.6V;
ILOAD = 100mA ;
0.8V ≤ VOUT ≤ 3.3V .588 0.6 0.612 V
Feedback Pin Volt age
variation over Line, Load,
and T emperature VFB -40°C ≤ TA ≤ +85°C;
2.4V ≤ VIN ≤ 5.5V
0mA ≤ ILOAD ≤ 600mA .582 0.6 0.618. V
Feedback Pin Input
Current IFB N ote 1 <100 nA
VS0-VS2, Pi n Logic Low
V
VSLO
0.0
0.3
V
VS0-VS2, Pi n Logic High VVSHI 1.4 VIN V
VS0-VS2, Pi n Input
Current IVSX Note 1 <100 nA
Enable Pin Logic Low
V
ENLO
0.3
V
Enable Pin Logic High
V
ENHI
1.4
V
Enable Pin Current
I
ENABLE
Note 1
<100
nA
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03409 October 11, 2013 Rev E
EP5357LUI/EP5357HUI
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
LLM Engage Headroom Min imum VIN-VOUT to ensure
proper LLM operation 600 mV
LLM Pin Logic Low
V
LLMLO
0.3
V
LLM Pin Logic High
V
LLMHI
1.4
V
LLM Pin Curr ent
I
LLM
<100
nA
Operating Frequency
F
OSC
5
MHz
Soft Start Operation
Soft Start Slew Rate ∆VSS
EP5357HUI (VID MODE)
EP5357LUI (VI D MODE)
8
4 V/mS
V
OUT
R ise Time
T
RISE
T ime to 90% V
OUT
( VF B MO D E)
180
250
uSec
No te 1 : Param eter guarant eed by desi gn
Typical Performance Characteristics
Efficiency vs. Load Curre nt: VIN = 5.0V, VOUT (from
top to bottom) = 3.3, 2.5, 1.8, 1.2V
Efficiency vs. Load Curre nt: VIN = 3.7V, VOUT (from
top to bottom) = 2.5, 1.8, 1.2V
Efficiency vs. Load Curre nt: VIN = 3.3V, VOUT (from
top to bottom ) = 2.5, 1.8, 1.2V
45
50
55
60
65
70
75
80
85
90
95
10 100 1000
Load Current (mA)
Efficiency (%)
45
50
55
60
65
70
75
80
85
90
95
10 100 1000
Load Current (m A)
Efficiency (%)
45
50
55
60
65
70
75
80
85
90
95
10 100 1000
Load Current (mA)
Efficiency (%)
LLM
LLM
PWM
PWM
LLM
PWM
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03409 October 11, 2013 Rev E
EP5357LUI/EP5357HUI
S tart Up Wavefo r m: VIN = 5.0V, VOUT = 3.3V;
ILOAD = 10mA (VID MO DE)
S tart Up Wavefo r m: VIN = 5.0V, VOUT = 3. 3V;
ILOAD = 1000mA (VID MO DE)
Shut-down Wave form : VIN = 5.0V, VOUT = 3. 3V;
ILOAD = 10mA, PWM
Shut-down Wave form : VIN = 5.0V, VOUT = 3. 3V;
ILOAD = 500mA, PW M
Out put Ripple: VIN = 5.0V, VOUT = 1. 2V, Load = 10mA
LLM enabl ed
Output Ri ppl e: VIN = 5.0V, VOUT = 1. 2V,
Load = 500mA
50mV/Div
5mV/Div
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03409 October 11, 2013 Rev E
EP5357LUI/EP5357HUI
Out put Ripple: VIN = 5.0V, VOUT = 3.3V, Load = 10mA
LLM enabled
Output Ri ppl e: VIN = 5.0V, VOUT = 3.3V,
Lo ad = 500mA
Out put Ripple: VIN = 3.3V, VOUT = 1.8V, Load = 10mA
LLM enabl ed
Output Ri ppl e: VIN = 3.3V, VOUT = 1.8V
Lo ad = 500mA
Out put Ripple: VIN = 3.3V, VOUT = 1.2V, Load = 10mA
LLM enabled
Output Ri ppl e: VIN = 3.3V, VOUT = 1.2V,
Lo ad = 500mA
5mV/Div
50mV/Div
5mV/Div
50mV/Div
50mV/Div
5mV/Div
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03409 October 11, 2013 Rev E
EP5357LUI/EP5357HUI
Loa d Transient: VIN = 5.0V , VOUT = 1.2V
Loa d stepped from 0mA to 500m A, LLM enabl ed
Loa d Transient: VIN = 5.0V , VOUT = 1.2V
Loa d stepped from 10m A to 500m A
Loa d Transient: VIN = 3.3V, VOUT = 1.8V
Loa d stepped from 0mA to 500m A, LLM enabl ed
Loa d Transient: VIN = 3.3V, VOUT = 1.8V
Loa d stepped from 10m A to 500m A
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03409 October 11, 2013 Rev E
EP5357LUI/EP5357HUI
Functional Block Diagram
Figure 5: Functional Bl ock Di a gram
DAC
Switch
VREF
(+)
(-)
Error
Amp
V
SENSE
V
FB
V
OUT
Package Boundry
P-Drive
N-Drive
UVLO
Thermal Limit
Current Limit
Soft Start
Sawtooth
Generator
(+)
(-)PWM
Comp
PVIN
ENABLE
PGND
Logic
Compensation
Network
NC(SW)
Voltage
Select
VS0VS1
AVIN VS2AGND
Mode Logic
LLM
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03409 October 11, 2013 Rev E
EP5357LUI/EP5357HUI
Detailed Description
Functional Overview
The EP5357xUI requires only 2 small MLCC
capacitors for a complete DC-DC converter
solution. The device integrates MOSFET
switches, PWM controller, Gate-drive,
c om pens ation, and induc tor into a tiny 2.5mm x
2.25mm x 1.1mm QFN package. Advanced
package design, along with the high level of
integration, provides very low output ripple and
noise. The EP5357xUI uses voltage mode
control for high noise immunity and load
matching to advanced ≤90nm loads. A 3-pin
VID allows the user to choose from one of 8
output voltage settings. The EP5357xUI
comes with two VID output voltage ranges.
The EP5357HUI provides VOUT settings from
1.8V to 3.3V, the EP5357LUI provides VID
settings from 0.8V to 1.5V, and also has an
external resistor divider option to program
output setting over the 0.6V to VIN-0.25V
range. The EP5357xUI provides the industry’s
highest power density of any 600mA DCDC
converter solution.
The key enabler of this revolutionary
integration is Altera Enpirion’s proprietary
power MOSFET technology. The advanced
MOSFET switches are implemented in deep-
submicron CMOS to supply very low switching
loss at high switching frequencies and to allow
a high level of integration. The semiconductor
process allows seem-less integration of all
switching, c ontr ol, and c om pens ation c ir c uitry.
The proprietary magnetics design provides
high-density/high-value magnetics in a very
small footprint. Altera Enpirion magnetics are
carefully matched to the control and
compensation circuitry yielding an optimal
solution with assured performance over the
entire operating range.
Protection features include under-voltage lock-
out (UVLO), over-current protection (OCP),
short circuit protection, and thermal overload
protection.
Integrated Inductor
The EP5357xUI utilizes a proprietary low loss
integrated inductor. The integration of the
inductor greatly simplifies the power supply
design process. The inherent shielding and
compact construction of the integrated inductor
reduces the conducted and radiated noise that
can couple into the traces of the printed circuit
board. Further, the package layout is
optimized to reduce the electrical path length
for the high di/dT input AC ripple currents that
are a major source of radiated emissions from
DC-DC converters. The integrated inductor
provides the optimal solution to the complexity,
output ripple, and noise that plague low power
DCDC converter design.
Voltage Mode Control
The EP5357xUI utilizes an integrated type III
compensation network. Voltage mode control
is inherently impedance matched to the sub
90nm process technology that is used in
today’s advanced ICs. Voltage mode control
also provides a high degree of noise immunity
at light load c ur rents s o that low ripple and high
accuracy are maintained over the entire load
range. The very high switching frequency
allows for a very wide control loop bandwidth
and henc e exc ellent tr ans ient perform anc e.
Light Load Mode (LLM) Operation
The EP5357xUI uses a proprietary light load
mode to provide high efficiency in the low load
operating condition. When the LLM pin is high,
the device is in automatic LLM/PWM mode.
When the LLM pin is low , the devic e is in PWM
mode. In automatic LLM/PWM mode, when a
light load condition is detected, the device will
(1) step VOUT up by approximately 1.5% above
the nominal operating output voltage setting,
VNOM, and then (2) shut down unnecessary
c irc uitr y, and (3) m onitor VOUT. When VOUT falls
below VNOM, the device will repeat (1), (2), and
(3). The voltage step up, or pre-positioning,
improves transient droop when a load transient
causes a transition from LLM mode to PWM
mode. If a load transient occurs, causing VOUT
to fall below the threshold VMIN, the device will
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03409 October 11, 2013 Rev E
EP5357LUI/EP5357HUI
exit LLM operation and begin normal PWM
operation. Figure 6 demonstrates VOUT
behavior during transition into and out of LLM
operation.
Figure 6: VOUT Be havior i n LLM Ope ration
Figure 7: VOUT Droop duri ng Periodi c LLM Exi t
Many multi-mode DCDC converters s uffer from
a condition that occurs when the load current
increases only slowly so that there is no load
transient driving VOUT below the VMIN threshold.
In this condition, the device would never exit
LLM operation. This could adversely affect
efficiency and cause unwanted ripple. To
prevent this from occurring, the EP5357xUI
periodically exits LLM mode into PWM mode
and measures the load current. If the load
current is above the LLM threshold current, the
device will remain in PWM mode. If the load
current is below the LLM threshold, the device
will re-enter LLM operation. There will be a
small droop in VOUT at the point where the
device exits and re-enters LLM, as shown in
Figure 7.
Figure 8: Typical load current for LLM e ngage and
di sengage versus V OUT for sel ected i nput volta ges
Table 1: Load cur rent belo w which the device can b e
ce rtai n to be i n LLM opera tion. The se val ue s a re
gua rante ed by de sign
The load current at which the device will enter
LLM mode is a function of input and output
voltage. Figure 8 shows the typical value at
which the device will enter LLM operation. The
actual load current at which the device will
enter LLM operation can vary by +/-30%. Table
1 s how s the m inim um load c urr ent below w hic h
the device is guaranteed to be in LLM
operating mode.
To ensure normal LLM operation, LLM mode
should be enabled/disabled with specific
sequencing. For applications with explicit LLM
pin control, enable LLM after VIN ramp up is
complete; disable LLM before VIN ramp
VOUT
IOUT
LLM
Ripple
PWM
Ripple
V
MAX
V
NOM
V
MIN
Load
Step
LLM Thresh ol d Current vs. VOUT
0
50
100
150
200
250
0.8 1.1 1.4 1.7 2.0 2.3 2.6 2.9 3.2
VOUT (V )
LLM T hresho ld (mA)
VIN=5 V (to p curve)
VIN=4.2V
VIN=3.7V
VIN= 3.3V (bottom curve)
3.3 3.7 4.3 5.0
3.30 105 147
3.00 62 122 156
2.90 89 126 158
2.60 56 106 136 162
2.50 69 111 138 162
2.20 101 120 141 160
2.10 105 122 141 158
1.80 111 124 138 150
1.50 111 120 130 138
1.45 111 119 128 136
1.20 105 111 117 122
1.15 103 108 114 119
1.10 101 106 111 116
1.05 99 104 108 113
0.80 87 89 92 94
VIN
VOUT
Devic e exits LLM,
tests load current
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03409 October 11, 2013 Rev E
EP5357LUI/EP5357HUI
down. For applications with ENABLE control,
tie LLM to ENABLE; enable device after VIN
ramp up is complete and disable device before
VIN ramp down begins. For devices with
ENABLE and LLM tied to VIN, contact Power
Applications support for specific
recommendations
Increased output filter capacitance and/or
increased bulk capacitance at the load will
decrease the magnitude of the LLM ripple.
Refer to the s ec tion on output filter c apac itanc e
for m axim um values of output filter c apac itanc e
and the Soft-Start section for maximum bulk
c apac itanc e at the load.
NOTE: For proper LLM operation the
EP5357xUI requires a minimum difference
between VIN and VOUT of 600mV. If this
condition is not met, the device cannot be
as s ured proper LLM operation.
NOTE: Automatic LLM/PWM is not available
when using the external resistor divider option
for VOUT programming.
S o ft S ta rt
Internal soft start circuits limit in-rush current
when the device starts up from a power down
condition or when the “ENABLE” pin is
asserted “high”. Digital control circuitry limits
the VOUT ramp rate to levels that are safe for
the Power MOSFETS and the integrated
inductor.
The EP5357HUI has a soft-start slew rate that
is twice that of the EP5357LUI.
When the EP5357LUI is configured in external
resistor divider mode, the device has a fixed
VO UT r am p tim e. Therefor e, the ram p rate w ill
vary with the output voltage setting. Output
voltage ramp time is given in the Electrical
Characteristics Table.
Excess bulk capacitance on the output of the
device can cause an over-current condition at
startup. The maximum total capacitance on
the output, including the output filter capacitor
and bulk and decoupling capacitance, at the
load, is given as:
EP5357LUI:
COUT_TOTAL_MAX = COUT_Filter + COUT_BULK = 200uF
EP5357HUI:
COUT_TOTAL_MAX = COUT_Filter + COUT_BULK = 100uF
EP5357LUI in external divider m ode:
COUT_TOTAL_MAX = 2.25x10-4/VOUT Farads
The nominal value for COUT is 10uF. See the
applic ations s ec tion for m ore details .
Over Current/Short Circuit Protection
The current limit function is achieved by
sensing the current flowing through a sense P-
MOSFET which is compared to a reference
current. When this level is exceeded the P-
FET is turned off and the N-FET is turned on,
pulling VOUT low. This condition is maintained
for approximately 0.5mS and then a normal
soft start is initiated. If the over current
c ondition s till pers is ts , this c yc le w ill repeat.
Under Vol t age Lockout
During initial power up an under voltage
lockout circuit will hold-off the switching
circuitry until the input voltage reaches a
sufficient level to insure proper operation. If
the voltage drops below the UVLO threshold
the lockout circuitry will again disable the
switching. Hysteresis is included to prevent
chattering between states.
Enable
The ENABLE pin provides a means to shut
down the converter or enable normal
operation. A logic low will disable the
converter and cause it to shut down. A logic
high will enable the converter into normal
operation.
NOTE: The ENABLE pin must not be left
floating.
Thermal Shutdown
When excessive power is dissipated in the
chip, the junction temperature rises. Once the
junction temperature exceeds the thermal
shutdown temperature the thermal shutdown
circuit turns off the converter output voltage
thus allowing the device to cool. When the
junction temperature decreases by 15C°, the
device will go through the normal startup
process.
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03409 October 11, 2013 Rev E
EP5357LUI/EP5357HUI
Application Information
V
IN
VSENSE
PVIN
V
S1
V
S2
V
S0
10µF
4.7µF
VOUT
VOUT
AGND
ENABLE
PGND
AVIN
LLM
Figure 9: Applic at ion Circuit , EP5357HUI , con figu red
f or LLM E nabled. N ot e tha t all c ontrol signals shoul d
be conne cted to AVI N or AGND.
V
IN V
SENSE
PVIN
VS1
VS2
VS0
10µF
µF
V
OUT
V
OUT
AGND
ENABLE
V
FB
PGND
AVIN
LLM
Figure 10: Applica tion Circuit, EP5357LUI,
confi gured for LLM Enabl ed, showi ng the V FB
function.
Output Voltage Programming
The EP5357xUI utilizes a 3-pin VID to program
the output voltage value. The VID is available
in two sets of output VID programming ranges.
The VID pins should be connected either to
AVIN or to AGND to avoid noise coupling into
the devic e.
The “Low” range is optimized for low voltage
applications. It comes with preset VID settings
ranging from 0.80V and 1.5V. This VID set
als o has an external divider option.
To specify this VID range, order part number
EP5357LUI.
The “High” VID set provides output voltage
settings ranging from 1.8V to 3.3V. This
version does not have an external divider
option. To specify this VID range, order part
num ber EP5357HUI.
Internally, the output of the VID multiplexer
sets the value for the voltage reference DAC,
which in turn is connected to the non-inverting
input of the er ror am plifier. This allow s the us e
of a single feedback divider with constant loop
gain and optimum compensation, independent
of the output voltage s elec ted.
NOTE: The VID pins m us t not be left floating.
EP5357L Low VI D Range Pr ogr am m ing
The EP5357LUI is designed to provide a high
degree of flexibility in powering applications
that require low VOUT settings and dynamic
voltage scaling (DVS). The device employs a
3-pin VID architecture that allows the user to
choose one of seven (7) preset output voltage
settings, or the user can select an external
voltage divider option. The VID pin settings
can be changed on the fly to implement glitch-
free voltage s c aling.
Table 2: EP53 57L UI VID Vo ltag e S el ect Settin g s
Table 2 s how s the VS2-VS0 pin logic s tates for
the EP5357LUI and the associated output
voltage levels. A logic “1” indicates a
connection to AVIN or to a “high” logic voltage
level. A logic “0” indicates a connection to
AGND or to a “low” logic voltage level. These
pins can be either hardwired to AVIN or AGND
or alternatively can be driven by standard logic
levels. Logic levels are defined in the electrical
characteristics table. Any level between the
logic high and logic low is indeterminate.
VS2 VS1 VS0 VOUT
0 0 0 1.50
0 0 1 1.45
0 1 0 1.20
0 1 1 1.15
1 0 0 1.10
1 0 1 1.05
1 1 0 0.8
1 1 1 EXT
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EP5357LUI/EP5357HUI
EP 5357LU I E xternal V oltage D ivider
The external divider option is chosen by
connecting VID pins VS2-VS0 to VIN or a logic
“1” or “high”. The EP5357LUI uses a separate
feedback pin, VFB, when using the external
divider. VSENSE must be connected to VOUT as
indicated in Figure 11. The output voltage is
selec ted by the follow ing for m ula:
( )
Rb
Ra
OUT VV += 16.0
Ra must be chosen as 237KΩ to m aintain loop
gain. Then R b is given as:
Ω
−
=6.0
102.142
3
OUT
b
Vx
R
VOUT can be programmed over the range of
0.6V to (VIN – 0.25V).
NOTE: Dynamic Voltage Scaling is not allowed
between internal preset voltages and external
divider.
NOTE: LLM is not func tional when us ing the
external divider option. Tie the LLM pin to
AGND.
VIN V
Sense
V
S0
V
S2
EP5357L
10µF
4.7uF
VOUT
V
OUT
AGND
ENABLE
Ra
Rb
V
FB
V
S1
PGND
AVIN
PVIN
Figure 11: E P5357LUI us ing external divi der
EP5357HUI High VID Range Programming
The EP5357HUI VOUT settings are optimized
for higher nominal voltages such as those
required to power IO, RF, or IC memory. The
preset voltages range from 1.8V to 3.3V.
There are eight (8) preset output voltage
settings. The EP5357HUI does not have an
external divider option. As with the
EP5357LUI, the VID pin settings can be
c hanged w hile the devic e is enabled.
Table 3 s hows the VS0-VS2 pin logic s tates for
the EP5357HUI and the associated output
voltage levels. A logic “1” indicates a
connection to AVIN or to a “high” logic voltage
level. A logic “0” indicates a connection to
AGND or to a “low” logic voltage level. These
pins can be either hardwired to AVIN or AGND
or alternatively can be driven by standard logic
levels. Logic levels are defined in the electrical
characteristics table. Any level between the
logic high and logic low is indeterminate.
Thes e pins m us t not be left floating.
Table 3: EP 5357HUI VID Volta ge Select Settin g s
Power-Up/Down Sequencing
During power-up, ENABLE should not be
asserted before PVIN, and PVIN should not be
asserted before AVIN. The PVIN should never
be powered when AVIN is off. During power
down, the AVIN should not be powered down
before the PVIN. Tying PVIN and AVIN or all
three pins (AVIN, PVIN, ENABLE) together
during power up or power down meets these
requirements.
Pre-Bias Start-up
The EP5357xUI does not support startup into a
pre-biased condition. Be sure the output
capacitors are not charged or the output of the
EP5357xUI is not pre-biased when the
EP5357xUI is first enabled.
Input Filter C apacitor
For ILOAD ≤ 500m A, C IN = 2.2uF
For ILOAD > 500mA CIN = 4.7uF.
0402 capacitor case size is acceptable.
The input capacitor must use a X5R or X7R or
equivalent dielectric formulation. Y5V or
equivalent dielectric formulations lose
capacitance with frequency, bias, and with
VS2 VS1 VS0 VOUT
0 0 0 3.3
0 0 1 3.0
0 1 0 2.9
0 1 1 2.6
1 0 0 2.5
1 0 1 2.2
1 1 0 2.1
1 1 1 1.8
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03409 October 11, 2013 Rev E
EP5357LUI/EP5357HUI
temperature, and are not suitable for switch-
m ode DC -DC converter input filter applications.
Output Filter Capacitor
F o r VIN ≤ 4.3V, COUT_MIN = 10uF 0603 MLCC.
For V IN > 4.3V, COUT_MIN = 10uF 0805 MLCC.
Ripple performance can be improved by using
2x10µF 0603 MLCC capacitors (for any
allowed VIN).
The maximum output filter capacitance next to
the output pins of the device is 60µF low ESR
MLCC capacitance. VOUT has to be sensed at
the last output filter capacitor next to the
EP5357xUI.
Additional bulk capacitance for decoupling and
bypass can be placed at the load as long as
there is sufficient separation between the VOUT
Sens e point and the bulk c apac itanc e.
Excess total capacitance on the output (Output
Filter + Bulk) can cause an over-current
condition at startup. Refer to the section on
Soft-Start for the maximum total capacitance
on the output.
The output capacitor must use a X5R or X7R
or equivalent dielectric formulation. Y5V or
equivalent dielectric formulations lose
capacitance with frequency, bias, and
temperature and are not suitable for switch-
mode DC-DC converter output filter
applications
.
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03409 October 11, 2013 Rev E
EP5357LUI/EP5357HUI
Layout Recommendation
Figure 12 shows critical components and layer
1 traces of a recommended minimum footprint
EP5357LUI/EP5357HUI layout with ENABLE
tied to VIN. Alternate ENABLE configurations,
and other small signal pins need to be
connected and routed according to specific
customer application. Please see the Gerber
files on the Altera website
www.altera.com/enpirion for exact dimensions
and other layers. Please refer to Figure 12
while reading the layout recommendations in
this s ec tion.
Recommendation 1: Input and output filter
capacitors should be placed on the same side
of the PCB, and as close to the EP5357xUI
package as possible. They should be
connected to the device with very short and
wide traces. Do not use thermal reliefs or
spokes when connecting the capacitor pads to
the respective nodes. The +V and GND traces
between the capacitors and the EP5357xUI
should be as close to each other as possible
so that the gap between the two nodes is
minimized, even under the c apac itor s .
Recommendation 2: Input and output grounds
are separated until they connect at the PGND
pins. The separation shown on Figure 12
between the input and output GND circuits
helps minimize noise coupling between the
converter input and output s w itc hing loops .
Recommendation 3: The system ground
plane should be the first layer immediately
below the surface layer. This ground plane
should be continuous and un-interrupted below
the converter and the input/output capacitors.
Please see the Gerber files on the Altera
website www.altera.com/enpirion.
Figure 12:T op PCB L ay er Critical Compon ent s
and C opper for Min im u m Foot pr i n t
Recommendation 4: Multiple small vias
should be used to connect the ground traces
under the device to the system ground plane
on another layer for heat dissipation. The drill
diameter of the vias should be 0.33mm, and
the vias m us t have at leas t 1 oz . c opper plating
on the inside wall, making the finished hole
size around 0.20-0.26mm. Do not use thermal
reliefs or spokes to connect the vias to the
ground plane. It is preferred to put these vias
under the capacitors along the edge of the
GND copper closest to the +V copper. Please
see Figure 12. These vias connect the
input/output filter capacitors to the GND plane
and help reduce parasitic inductances in the
input and output current loops. If the vias
cannot be placed under CIN and COUT, then put
them just outside the capacitors along the
GND. Do not use thermal reliefs or spokes to
c onnec t thes e vias to the gr ound plane.
Recommendation 5: AVIN is the power supply
for the internal small-signal control circuits. It
should be connected to the input voltage at a
quiet point. In Figure 12 this connection is
made at the input capacitor close to the VIN
connection.
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03409 October 11, 2013 Rev E
EP5357LUI/EP5357HUI
Recommended PCB Footprint
Figure 13: EP5357 Pa cka ge P CB Footpri nt
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03409 October 11, 2013 Rev E
EP5357LUI/EP5357HUI
Package and Mechanical
Figure14: EP5357xUI Package Di m ensi ons
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03409 October 11, 2013 Rev E
EP5357LUI/EP5357HUI
Contact Information
Altera Corporation
101 Innovation D rive
San Jos e, C A 95134
Phone: 408-544-7000
www.altera.com
© 2013 Alter a C or por ati on —Confidential. All r igh ts reser ved. ALTERA, ARRIA, C YCLONE, ENPIRION , HAR DC OPY, MAX, MEGACOR E , N IOS,
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countr ies. All othe r w or ds and logos identi fi ed as tr ademar ks or ser v ice mar ks ar e the pr oper ty of their r espective hold er s as desc r ibed at
w w w.alter a.c om/c o mm on /l egal.h t ml. Al ter a war r ants per for ma nc e of its semiconductor pr oduc t s to cur r ent specificati on s in accor danc e w ith Al ter a' s
standar d war r anty , but r eser v es the r ight to make changes to any pr oducts and ser vices at any time without not ice . Alt er a assumes no r esponsibility or
liabil i ty ar ising out of the app l icati on or use of any infor mati on , pr odu c t, or ser v ice descr ibed her ei n exc ep t as expr essly agr eed to in w r iting by Alter a.
Alter a customer s ar e advised to obtain the late st ver sion of device specifi cat io ns befor e r elyi ng on any published info r matio n and befo r e pla cin g or de r s
for pr oduc ts or ser vices.
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03409 October 11, 2013 Rev E