SY89874UMI - MICROCHIP TECHNOLOGY

SY89874U

2.5GHz, Any Differential, In-to-LVPECL,

Programmable Clock Divider/Fanout Buffer

with Internal Termination

Precision Edge is a registered trademark of Micrel, Inc

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

General Description

This low-skew, low-jitter device is capable of accepting a

high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS

or HSTL clock input signal and dividing down the

frequency using a programmable divider ratio to create a

frequency-locked, lower speed version of the input clock.

Available divider ratios are 2, 4, 8 and 16, or straight pass-

through. In a typical 622MHz clock system this would

provide availability of 311MHz, 155MHz, 77MHz, or

38MHz auxiliary clock com ponents.

The differential input buffer has a unique internal

termination design that allows access to the termination

network through a VT pin. This feature allows the device to

easily interface to different logic standards. A VREF-AC

reference is included for A C-cou pled applications.

The /RESET input asynchronously resets the divider. In

the pass-through function (divide by 1) the /RESET

synchronously enables or disables the outputs on the next

falling edge of IN (rising edge of /N).

Data sheets and support documentation can be found on

Micrel’s web site at: www.micrel.com.

Precision Edge®

Features

• Integrated programmable clock divider and 1:2 fanout

buffer

• Guaranteed AC performance over temperature and

voltage:

− > 2.5GHz fMAX

− < 250ps tr/tf

− < 15ps within device ske w

• Low jitter design:

− < 10psPP total jitter

− < 1psRMS cycle-to-cycle jitter

• Unique input termination and VT pin for DC-coupled and

AC-coupled Inputs; CML, PECL, LVDS, and HSTL

• TTL/CMOS inputs for select and reset

• 100k EP-compatible LVPECL outputs

• Parallel programming capability

• Programmable divider ratios of 1, 2, 4, 8 and 16

• Low-voltage operation 2.5V or 3.3V

• Output disable function

• –40°C to 85°C temperature range

• Available in 16-pin (3mm x 3mm) QFN packag e

Applications

• SONET/SDH line cards

• Transponders

• High-end multiprocessor sensors

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Ordering Information

Part Number Package Type Operating Range Package Marking Lead Finish

SY89874UMI QFN-16 Industrial 874U Sn-Pb

SY89874UMITR(2) QFN-16 Industrial 874U Sn-Pb

Note:

1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC electricals only.

2. Tape and Reel.

Pin Configur ation

Pin Description

Pin Number Pin Name Pin Function

12, 9 IN, /IN Differential Input. Internal 50Ω termination resistors to VT input. Flexible input accepts any differential

input. See “Input Interface Applications” sect ion.

1, 2, 3, 4 Q0, /Q0

Q1, /Q1 Differential Buffered LVPECL Outputs. Divided by 1, 2, 4, 8, or 16. See “Truth Table”. Unused PECL

outputs may be left floating with no impact on jitter performance.

16, 15, 5 S0, S1, S2 Select Pins. See “Truth Table”. LVTTL/CMOS logic levels. Internal 25kΩ pull-up resistor. Logic HIGH

if left unconnected (divided by 16 mode). Input threshold is VCC/2.

6 NC No Connect.

8 /RESET

/DISABLE

LVTTL/CMOS Logic Levels. Internal 25kΩ pull-up resistor. Logic HIGH if l eft unconn ected. Apply

LOW to reset the divider (divided by 2, 4, 8, or 16 mode). Also acts as a synchronous disable/enable

function. The reset and disable function occurs on the next HIGH-to-LOW clock input transition. Input

threshold is VCC/2.

10 VREF-AC

Reference Voltage. Equal to VCC-1.4V (approximately). Used for AC-coupled appl ications only.

Decouple the VREF-AC pin with a 0.01µF capacitor. See “Input Interface Applications” section.

11 VT

Termination Center Tap. For CML or LVDS inputs, leave this floating. Otherwise, see Figures 2a to 2f

within the “Input Interface Applications” section.

7, 14 VCC Positive Power Supply. Bypass with .01µF /0.01µF low-ESR capacit or.

13 GND Ground.

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Functional Block Diagram

Typical Performance

Circuit Name

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Absolute Maximum Ratings(1)

Supply Voltage (VCC)....................................−0.5V to +4.0V

Input Voltage (VIN).................................. −0.5V to VCC+0.3V

ECL Output Current (IOUT)

Continuous............................................................50mA

Surge..................................................................100mA

Input Current IN, /IN (IIN) ...........................................±50mA

VT Current (IVT) ........................................................±100mA

VREF-AC Sink/Source Current (IVREF-AC), Note 3............±2mA

Lead Temperature (soldering, 20s)............................260°C

Storage Temperature (TS).........................−65°C to +150°C

Operating Ratings(2)

Supply Voltage (VCC)................. +3.3V ±10% or +2.5V ±5%

Ambient Temperature (TA)..........................–40°C to +85°C

Package Thermal Resistance

QFN (θJA)

Still-Air.........................................................60°C/W

500lfpm .......................................................54°C/W

QFN (ΨJB), Note 4

Junction-to-Board........................................32°C/W

DC Electrical Characteristics(5, 6)

TA = −40°C to +85°C; unless otherwise noted.

Symbol Parameter Condition Min. Typ. Max. Units

VCC Power Supply 2.375 3.63 V

ICC Power Supply Current No load, maximum VCC 50 75 mA

90 100 110

RIN Differential Input Resistance

(IN-to-/IN)

VIH Input High Voltage (IN, /IN) Note 5 0.1 − VCC + 0.3 V

VIL Input Low Voltage (IN, /IN) Note 5 −0.3 − V

IH − 0.1 V

VIN Input Voltage Swing Notes 5, 6 0.1 − VCC V

VDIFF_IN Differential Input Voltage Swing Notes 5, 6, 7 0.2 − V

⎮IIN⎮ Input Current (IN, /IN) Note 5 − − 45 mA

VREF-AC Reference Voltage Note 8 VCC − 1.525 VCC − 1.425 VCC −

1.325 V

Notes:

1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied

at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended

periods may affect device reliability.

2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.

3. Due to the limited drive capability use for input of the same package only.

4. Junction-to-board resistance assumes exposed pad is soldered (or equivalent) to the device’s most negative potential on the PCB.

5. The circuit is designed to meet the DC specifications shown in the DC Electrical Characteristics table after thermal equilibrium has been

established.

6. Specification for packaged product only.

7. Due to the internal termination (see Input Buffer Structure), the input current depends on the applied voltages at IN, /IN, and VT inputs. Do not apply

a combination of voltages that causes the input current to exceed the maximum limit. Performance might be impacted if the differential inputs are

driven single-ended.

8. See Timing Diagram for VT definition. VIN (maximum) is specified when VT is floating.

9. See Typical Operating Characteristics section for VDIFF definition.

10. Operating using VIN is limited to AC-coupled PECL or CML applications only. Connect directly to the VT pin.

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LVPECL (100KEP) DC Electr ical Characteristics(1, 2)

VCC = 3.3V ±10% or 2.5V ±5%; TA = −40°C to +85°C, RL = 50Ω to VCC − 2V, unless otherwise stated.

Symbol Parameter Condition Min. Typ. Max. Units

VOH Output HIGH Voltage VCC − 1.145 VCC − 1.020 VCC − 0.895 V

VOL Output LOW Voltage VCC − 1.945 VCC − 1.820 VCC − 1.695 V

VOUT Output Voltage Swing 550 800 1050 mV

VDIFF_OUT Differential Output Voltage Swing 1.10 1.60 2.10 V

LVTTL/CMOS DC Electrical Characteristics(2, 3)

VCC = 3.3V ±10% or 2.5V ±5%; TA = −40°C to +85°C, unless otherwise stated.

Symbol Parameter Condition Min. Typ. Max. Units

VIH Input HIGH Voltage 2.0 V

VIL Input LOW Voltage 0.8 V

IIH Input HIGH Current −125 20 µA

IIL Input LOW Current

−300 µA

AC Electrical Characteristics(2, 4)

VCC = 3.3V ±10% or 2.5V ±5%; TA = −40°C to +85°C, unless otherwise stated.

Symbol Parameter Condition Min. Typ. Max. Units

fMAX Maximum Output Toggle Frequency Output Swing ≥ 400mV 2.5 GHz

Maximum Input Frequency Divide b y 2, 4, 8, 16 3.2 GHz

tPD Differential Propagation Delay Input Swing < 400mV 540 650 790 ps

IN to Q Input Swing ≥ 400mV 480 600 730

tSKEW Within-Device Skew (differential) Note 5 7 15 ps

Q0 − Q1

Part-to-Part Skew (differential) Note 5 250

tRR Reset Recovery Time Note 6 600 ps

tJITTER Cycle-to-Cycle Jitter Note 7 1 psRMS

Total Jitter Note 8 10 psPP

tr, tf Rise/Fall Time (20% to 80%) 70 150 250 ps

Notes:

1. The circuit is designed to meet the DC specifications shown in the LVPECL (100KEP) Electrical Characteristics table after thermal equilibrium has

been established.

2. Specification for packaged product only.

3. The circuit is designed to meet the DC specifications shown in the LVTTL/CMOS Electrical Characteristics table after thermal equilibrium has been

established.

4. Measured with 400mV signal, 50% duty cycle, all outputs loaded with 50Ω to VCC − 2V, unless otherwise stated.

5. Skew is measured between outputs under identical transitions.

6. See Timing Diagram section.

7. Cycle-to-cycle Jitter Definition: The variation in period between adjacent cycles over a random sample of adjacent cycle pairs. TJITTER_CC = Tn − Tn+1,

where T is the time between rising edges of the output signal.

8. Total Jitter Definition: With an ideal clock input, of frequency ≤ fMAX (device), no more than one output edge in 1012 output edges will deviate by

more than the specified peak-to-peak jitter value.

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Timing Diagram

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Typical Characteristics

VCC = 3.3V, VIN = 400mV, TA = +25°C, unless otherwise stated.

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Definition of Single-Ended and Differential Swing

Figure 1a. Single-Ended Swing(1) Figure 1b . Differential Swing(2)

Notes:

1. Single-ended swing is the amplitude of the signal when driven differentially.

2. Differential swing is defined as IN − /IN (or Q − /Q).

Input Buffer Structure

Figure 1a. Single-Ended Swing(1) Figure 1b . Differential Swing(2)

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Input Interface Applications

Figure 3a. DC-Coupled CML

Input Interface Figure 3b. AC-Coupled CML

Input Interface Figure 3c. DC-Coupled PECL

Input Interface

Figure 3d. AC-Coupled PECL

Input Interface Figure 3e. LVDS Input Interface Figure 3f. HSTL Input Interface

Related Product an d S u pport Documentation

Part Number Function Data Sheet Link

SY89871U 2.5GHz Any Differential In-to-LVPECL

Programmable Clock Divider/Fanout Buffer with

Internal Termination www.micrel.com/product-info/products/sy89871u.shtml

QFN Application Note www.amkor.com/products/notes_papers/mlf_appnote_0902.pdf

HBW

Solutions New Products and Applications www.micrel.com/product-info/products/solutions.shtml

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LVPECL Output Termination Recommendations

Figure 4a. Parallel Termination-Thevenin Equivalent

Note:

For +2.5V Systems: R1 = 250Ω, R2 = 62.5Ω.

Figure 4b. Three-Resisto r “Y-Termination”

Notes:

Power-saving alternative to Thevenin termination.

Place termination resistors as close to destination inputs as possible.

Rb resistor sets the DC bias voltage, equal to Vt. For +3.3V systems Rb = 46Ω to 50Ω. For +2.5V systems, Rb = 39Ω.

C1 is an optional bypass capacitor intended to compensate for any tr/tf mismatches.

Figure 4c. Terminating Unused I/O

Notes:

Unused output (/Q) must be terminated to balance the output.

For +2.5V Systems: R1 = 250Ω, R2 = 62.5Ω, R3 = 1.25kΩ, R4 = 1.2kΩ.

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Package Information

PCB Thermal Consideratio n for 16-Pin QFN Package

(Always solder, or equivalent, the exposed pad to the PCB)

Notes:

Package meets Level 2 moisture sensitivity classification, and is shipped in dry-pack.

Exposed pads must be soldered to a ground for proper thermal management.

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com

Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This

information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry,

specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual

property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability

whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties

relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product

reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical impla

into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A

Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully

indemnify Micrel for any damages resulting from such use or sale.

can nt

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