IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 1 ©2014 Integrated Device Technology, Inc.
DATASHEET
Programmable FemtoClock® NG LVPECL/LVDS
Clock Generator with 6-Outputs
IDT8T49N006I
General Description
The IDT8T49N006I is a six output Clock Generator with selectable
LVDS or LVPECL outputs. The IDT8T49N006I can generate any one
of four frequencies from a single crystal or reference clock. The four
frequencies are selected from the Frequency Selection Table (Table
3A) and are programmed via I2C interface. The four predefined
frequencies are selected in the user application by two frequency
selection pins. Note the desired programmed frequencies must be
used with the corresponding crystal or clock frequency as indicated
in Table 3A.
Excellent phase noise performance is maintained with IDT’s Fourth
Generation FemtoClock® NG PLL technology, which delivers
sub-400fs RMS phase jitter.
Features
•Fourth Generation FemtoClock NG PLL technology
•Six selectable LVPECL or LVDS outputs via I2C
•CLK, nCLK input pair can accept the following differential input
levels: LVPECL, LVDS, HCSL
•FemtoClock NG VCO Range: 1.91GHz - 2.5GHz
•RMS phase jitter at 156.25MHz (12kHz - 20MHz): 228fs (typical)
•RMS phase jitter at 156.25MHz (10kHz - 1MHz): 175fs (typical)
•Full 2.5V or 3.3V power supply
•I2C programming interface
•PCI Express (2.5 Gb/S), Gen 2 (5 Gb/s) and Gen 3 (8 Gb/s) jitter
compliant
•-40°C to 85°C ambient operating temperature
•Lead-free (RoHS 6) packaging
Pin Assignment
IDT8T49N006I
40-Lead VFQFN
6mm x 6mm x 0.95mm package body
4.65mm x 4.65mm E-Pad
NL Package
Top View
1234 56 78 910
31
32
33
34
35
36
37
38
39
40
20
19
18
17
16
15
14
13
12
11
30 29 28 27 26 25 24 23 22 21
nc
nc
Q0
nQ0
V
CCO
Q1
nQ1
Q2
nQ2
V
EE
XTAL_OUT
XTAL_IN
V
EE
CLK
nCLK
FSEL0
ADDR_SEL
V
EE
V
CC
FSEL1
nc
nc
Q3
nQ3
V
CCO
Q4
nQ4
Q5
nQ5
V
EE
S D ATA
SCLK
VEE
VEE
VEE
VEE
VCCA
LOCK
VCC
CLK_SEL
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 2 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Block Diagram
CLK S E L
XTAL_IN
XTAL_OUT
Xtal
Osc
FemtoClock®NG
VCO
Divider,
Output Type
&
Output
Enable
Selection
÷P[1:0]
0
1
OUTPUT ENABLE
OUTPUT STYLE
6
6
Phase
Detector
+
Charge
Pump
PS
Pulldown
Pulldown
Pullup
Pullup
Pulldown
Pulldown
PU/PD
Pulldown
VPP/FSEL 0
PROG_CLK/FSEL 1
SCLK
SDATA
ADDR_SEL
CLK
nCLK
÷M [8:1]
1
0
LOCK
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
÷N[6:0]
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 3 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1, 2, 29, 30 nc Unused Not connected
3, 4 Q0, nQ0 Output Differential output pair. LVPECL or LVDS interface levels.
5, 26 VCCO Power Output supply pins.
6, 7 Q1, nQ1 Output Differential output pair. LVPECL or LVDS interface levels.
8, 9 Q2, nQ2 Output Differential output pair. LVPECL or LVDS interface levels.
10, 13, 18,
21, 31, 34,
37, 40
VEE Power Negative supply pins.
11,
12
XTAL_IN
XTAL_OUT Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Crystal frequency is selected from Table 3A.
14 CLK Input Pulldown Non-inverting differential clock input.
15 nCLK Input Pullup/
Pulldown Inverting differential clock input. Internal resistor bias to VCC/2.
16, 20 FSEL0,
FSEL1 Input Pulldown
Frequency and configuration. Selects between one of four factory
programmable power-up default configurations. The four configurations can
have different PLL states, output frequencies, output styles and output
states. These default configurations can be overwritten after power-up via
I2C.LVCMOS/LVTTL interface levels.
00 = Configuration 0 (default)
01 = Configuration 1
10 = Configuration 2
11 = Configuration 3
17 ADDR_SEL Input Pulldown I2C Address select pin. LVCMOS/LVTTL interface levels.
19, 38 VCC Power Core supply pins.
22, 23 nQ5, Q5 Output Differential output pair. LVPECL or LVDS interface levels.
24, 25 nQ4, Q4 Output Differential output pair. LVPECL or LVDS interface levels.
27, 28 nQ3, Q3 Output Differential output pair. LVPECL or LVDS interface levels.
32 SCLK Input Pullup I2C Clock Input. LVCMOS/LVTTL interface levels.
33 SDATA Input/Output Pullup I2C Data Input. Input: LVCMOS/LVTTL interface levels. Output: Open
Drain.
35 VCCA Power Analog supply pin.
36 LOCK Output PLL Lock Indicator.
39 CLK_SEL Input Pulldown
Input source select pin. LVCMOS/LVTTL interface levels.
0 = XTAL (default)
1 = CLK, nCLK
Symbol Parameter Test Conditions Minimum Typical Maximum Units
CIN Input Capacitance 3.5 pF
RPULLDOWN Input Pulldown Resistor 51 k
RPULLUP Input Pullup Resistor 51 k
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 4 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Frequency Configuration
Table 3A. Frequency Configuration Examples
NOTE: Each device supports 4 output frequencies (with related input or crystal value) as selected from this table Register Settings.
NOTE: XTAL operation: fOUT = fREF * PS * M / N; CLK, nCLK input operation: fOUT = (fREF / P) * PS * M / N.
Output Frequencies
(MHz)
Input Frequency or
Crystal Frequency
(MHz)
Input Clock
Divider
P
Input Clock
Prescaler
PS
Feedback
Divider
M
Output
Divider
N
VCO Frequency
(MHz)
30.72 30.72 1 x2 32 64 1966.08
61.44 30.72 1 x2 32 32 1966.08
62.5 25 1 x2 40 32 2000
76.8 30.72 1 x2 40 32 2457.6
78.125 25 1 x2 50 32 2500
100 25 1 x2 40 20 2000
106.25 26.5625 1 x2 40 20 2125
122.8 30.72 1 x2 32 16 1966.08
125 25 1 x2 40 16 2000
133.33 25 1 x2 48 18 2400
148.5 27 1 x2 44 16 2376
150 25 1 x2 42 14 2100
153.6 30.72 1 x2 40 16 2457.6
155.52 19.44 1 x2 64 16 2488.32
156.25
25 1 x2 50 16 2500
100 2 x1 50 16 2500
125 5 x2 50 16 2500
159.375 26.5625 1 x2 36 12 1912.5
160 20 1 x2 48 12 1920
166.66 25 1 x2 40 12 2000
184.32 30.72 1 x2 36 12 2211.84
61.44 1 x1 36 12 2211.84
187.5 25 1 x1 90 12 2250
200 25 1 x2 40 10 2000
212.5 26.5625 1 x2 40 10 2125
250 25 1 x2 40 8 2000
300 25 1 x2 48 8 2400
311.04
19.44 1 x2 64 8 2488.32
77.76 1 x1 32 8 2488.32
155.52 2 x1 32 8 2488.32
312.5
25 1 x2 50 8 2500
125 2 x1 40 8 2500
156.25 5 x2 40 8 2500
318.75 26.5625 1 x2 36 6 1912.5
322.265625 25.78125 2 x1 150 6 1933.59375
375 25 1 x1 90 6 2250
400 25 1 x2 40 5 2000
425 26.5625 1 x2 40 5 2125
491.52 30.72 1 x2 32 4 1966.08
614.4
30.72 1 x2 40 4 2457.6
122.88 2 x1 40 4 2457.6
153.6 5 x2 40 4 2457.6
622.08 19.44 1 x2 64 4 2488.32
625 25 1 x2 50 4 2500
1228.88 30.72 1 x2 40 2 2457.6
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 5 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Table 3B. I2C Register Map
Register
Binary
Register
Address
Register Bit
D7 D6 D5 D4 D3 D2 D1 D0
0 00000 M0[8] M0[7] M0[6] M0[5] M0[4] M0[3] M0[2] M0[1]
1 00001 M1[8] M1[7] M1[6] M1[5] M1[4] M1[3] M1[2] M1[1]
2 00010 M2[8] M2[7] M2[6] M2[5] M2[4] M2[3] M2[2] M2[1]
3 00011 M3[8] M3[7] M3[6] M3[5] M3[4] M3[3] M3[2] M3[1]
4 00100 unused N0[6] N0[5] N0[4] N0[3] N0[2] N0[1] N0[0]
5 00101 unused N1[6] N1[5] N1[4] N1[3] N1[2] N1[1] N1[0]
6 00110 unused N2[6] N2[5] N2[4] N2[3] N2[2] N2[1] N2[0]
7 00111 unused N3[6] N3[5] N3[4] N3[3] N3[2] N3[1] N3[0]
8 01000 unused BYPASS0 PS0[1] PS0[0] P0[1] P0[0] CP0[1] CP0[0]
9 01001 unused BYPASS1 PS1[1] PS1[0] P1[1] P1[0] CP1[1] CP1[0]
10 01010 unused BYPASS2 PS2[1] PS2[0] P2[1] P2[0] CP2[1] CP2[0]
11 01011 unused BYPASS3 PS3[1] PS3[0] P3[1] P3[0] CP3[1] CP3[0]
12 01100 LVDS_SEL0[Q5] LVDS_SEL0[Q4] LVDS_SEL0[Q3] reserved LVDS_SEL0[Q2] LVDS_SEL0[Q1] LVDS_SEL0[Q0] reserved
13 01101 LVDS_SEL1[Q5] LVDS_SEL1[Q4] LVDS_SEL1[Q3] reserved LVDS_SEL1[Q2] LVDS_SEL1[Q1] LVDS_SEL1[Q0] reserved
14 01110 LVDS_SEL2[Q5] LVDS_SEL2[Q4] LVDS_SEL2[Q3] reserved LVDS_SEL2[Q2] LVDS_SEL2[Q1] LVDS_SEL2[Q0] reserved
15 01111 LVDS_SEL3[Q5] LVDS_SEL3[Q4] LVDS_SEL3[Q3] reserved LVDS_SEL3[Q2] LVDS_SEL3[Q1] LVDS_SEL3[Q0] reserved
16 10000 OE0[Q5] OE0[Q4] OE0[Q3] reserved OE0[Q2] OE0[Q1] OE0[Q0] reserved
17 10001 OE1[Q5] OE1[Q4] OE1[Q3] reserved OE1[Q2] OE1[Q1] OE1[Q0] reserved
18 10010 OE2[Q5] OE2[Q4] OE2[Q3] reserved OE2[Q2] OE2[Q1] OE2[Q0] reserved
19 10011 OE3[Q5] OE3[Q4] OE3[Q3] reserved OE3[Q2] OE3[Q1] OE3[Q0] reserved
20 10100 reserved reserved reserved reserved reserved reserved unused unused
21 10101 unused unused unused unused unused unused unused unused
22 10110 unused unused unused unused unused unused unused unused
23 10111 unused unused unused unused unused unused unused unused
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 6 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Table 3C. I2C Function Descriptions
Bits Name Function
Pn[1:0] Input Clock Divider Register
(n = 0...3)
Sets the PLL input clock divider. The divider value has the range of 1, 2, 4
and 5. See Table 3F. Pn[1:0] bits are programmed with values to support
default configuration settings for FSEL[1:0].
PSn(1:0) Input Prescaler Register n
(n = 0...3)
Sets the PLL input clock prescaler value. Valid prescaler values are x0.5, x1
or x2. See Table 3F. Set prescaler to x2 for optimum phase noise
performance. PSn[1:0] bits are programmed with values to support default
configuration settings for FSEL[1:0].
Mn[8:1]
Integer Feedback Divider
Register n
(n = 0...3)
Sets the integer feedback divider value. Based on the FemtoClock NG VCO
range, the applicable feedback dividers settings are 16 thru 250. Please
note the register value presents bits [8:1] of Mn, the LSB of Mn is not in the
register. Mn[8;1] bits are programmed with values to support default
configuration settings for FSEL[1:0].
Nn[6:0] Output Divider Register n
(n = 0...3)
Sets the output divider. The output divider value can range from 2, 3, 4, 5, 6
and 8, 10, 12 to 126 (step: 2). See Table 3G for the output divider coding.
Nn[6:0] bits are programmed with values to support default configuration
settings for FSEL[1:0].
CPn[1:0] PLL Bandwidth Register n
(n = 0...3)
Sets the FemtoClock NG PLL bandwidth by controlling the charge pump
current. See Table 3H. CPn[1:0] bits are programmed with values to
support default configuration settings for FSEL[1:0].
BYPASSn PLL Bypass Register n
(n = 0...3)
Bypasses PLL. Output of the prescaler is routed through the output divider
N to the output fanout buffer. Programming a 1 to this bit bypasses the PLL.
Programming a 0 to this bit routes the output of the prescaler through the
PLL. BYPASSn bits are programmed with values to support default
configuration settings for FSEL[1:0].
OEn[Q0]
OEn[Q1]
OEn[Q2]
OEn[Q3]
OEn[Q4]
OEn[Q5]
Output Enable Register n
(n = 0...3)
Sets the outputs to Active or High Impedance. Programming a 0 to this bit
sets the outputs to High Impedance. Programming a 1 sets the outputs to
active status. OEn[Q0], OEn[Q1], OEn[Q2], OEn[Q3], OEn[Q4], and
OEn[Q5] bits are programmed with values to support default configuration
settings for FSEL[1:0].
LVDS_SELn[Q0]
LVDS_SELn[Q1]
LVDS_SELn[Q2]
LVDS_SELn[Q3]
LVDS_SELn[Q4]
LVDS_SELn[Q5]
Output Style Register n
(n = 0...3)
Sets the differential output style to either LVDS or LVPECL interface levels.
Programming a 1 to this bit sets the output styles to LVDS levels.
Programming a 0 to this bit sets the output styles to LVPECL levels.
LVDS_SELn[Q0], LVDS_SELn[Q1], LVDS_SELn[Q2], LVDS_SELn[Q3],
LVDS_SELn[Q4], and LVDS_SELn[Q5] bits are programmed with values to
support default configuration settings for FSEL[1:0].
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 7 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Table 3D. Feedback Divider Mn Coding
NOTE: Mn is always an even value. The Mn[0] bits are not implemented.
Register Bit
Feedback Divider MnMn[8:1]
Do Not Use 1 thru 15
00001000 16
00001001 18
00001010 20
00001011 22
00001100 thru 00011111 24 thru 62
00100000 64
00100001 66
00100010 68
00100011 70
00100100 72
... Mn
00110010 100
00110011 102
00110100 104
00110101 106
... Mn
01111010 244
01111011 246
01111100 248
01111101 250
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 8 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Table 3E. Input Clock Divider Pn and Prescaler PSn Coding
Table 3F. Output Divider Nn Coding
NOTE: X denotes “don’t care”.
CLK_SEL Input P[1:0] PS[1:0]
Input Clock
Divider
P
Input Clock
Prescaler
PS
Input Frequency (MHz)
Minimum Maximum
0XTALxx
00 1 x1 10 40
01 1 x0.5 20 40
1x1x2540
1CLK
00
00 1 x1 10 120
01 1 x0.5 20 240
1x1x2560
01
00 2 x1 20 240
01 2 x0.5 40 480
1x 2 x2 10 120
10
00 4 x1 40 480
01 4 x0.5 80 800
1x 4 x2 20 240
11
00 5 x1 50 600
01 5 x0.5 100 800
1x 5 x2 25 300
Register Bit
Frequency N
Output Frequency Range
Nn[6:0] fOUT_MIN (MHz) fOUT_MAX (MHz)
000000X 2 955 1250
0000010 2 955 1250
0000011 3 636.667 833.333
0000100 4 477.5 625
0000101 5 382 500
000011X 6 318.333 416.667
000100X 8 238.75 312.5
000101X 10 191 250
000110X 12 159.167 208.333
000111X 14 136.429 178.571
001000X 16 119.375 156.25
... N (even integer) (1910 ÷ N) (2500 ÷ N)
111101X 124 15.403 20.161
111111X 126 15.159 19.841
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 9 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Table 3G. Charge Pump CP Settings
NOTE: FemtoClock NG PLL stability is only guaranteed over the feedback divider ranges listed is Table 3G.
Power-up Default Configuration Description
The IDT8T49N006I supports a variety of options such as different
output styles, number of programmed default frequencies, output en-
able and operating temperature range. The device options and de-
fault frequencies must be specified at the time of order and are
programmed by IDT prior to shipment. The document, Programma-
ble FemtoClock® NG Product Ordering Guide specifies the available
order codes, including the device options and default frequency con-
figurations. Example part number: 8T49N004A-007NLGI, specifies a
quad frequency clock generator with default frequencies of
106.25MHz, 133.333MHz, 156.25MHz and 156.25MHz, with four
LVDS outputs that are enabled after power-up, specified over the in-
dustrial temperature range and housed in a lead-free (6/6 RoHS)
VFQFN package.
Other order codes with respective programmed frequencies are
available from IDT upon request. After power-up changes to the
output frequencies are controlled by FSEL[1:0] or the I2C interface.
Changes to the style (LVDS or LVPECL) and state (active or high
impedance) of each individual output can also be controlled with the
I2C interface after power up.
Table 3H. Power-up Default Settings
Register Bit Feedback Divider (M) Value Range
CPn1 CPn0 Minimum Maximum
0 0 16 48
0 1 48 100
10 100 250
11 192 250
FSEL1 FSEL0 Frequency
PLL State
(On or Bypass)
Output State
(Active or High
Impedance)
Output Style
(LVDS or LVPECL)
0 (default) 0 (default) Frequency 0 PLL State 0 Output State 0 Output Style 0
0 1 Frequency 1 PLL State 1 Output State 1 Output Style 1
1 0 Frequency 2 PLL State 2 Output State 2 Output Style 2
1 1 Frequency 3 PLL State 3 Output State 3 Output Style 3
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 10 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Serial Interface Configuration Description
The IDT8T49N006I has an I2C-compatible configuration interface to
access any of the internal registers (Table 3B) for frequency and PLL
parameter programming. The IDT8T49N006I acts as a slave device
on the I2C bus and has the address 0b110111x, where x is set by the
value on ADDR_SEL input. (See Tables 3I & 3J). The interface
accepts byte-oriented block write and block read operations. An
address byte (P) specifies the register address (Table 3B) as the byte
position of the first register to write or read. Data bytes (registers) are
accessed in sequential order from the lowest to the highest byte
(most significant bit first, see Table 3K, 3L).
Read and write block transfers can be stopped after any complete
byte transfer. It is recommended to terminate the I2C read or write
transfer after accessing byte #23 by sending a stop command.
For full electrical I2C compliance, it is recommended to use external
pull-up resistors for SDATA and SCLK. The internal pull-up resistors
have a size of 50kW typical.
Table 3I. I2C Device Slave Address ADDR_SEL = 0 (default)
Table 3J. I2C Device Slave Address ADDR_SEL = 1
Table 3K. Block Write Operation
Table 3L. Block Read Operation
1101110R/W
1101111R/W
Bit 1 2:8 9 10 11:18 19 20:27 28 29-36 37 ... ... ...
Description START Slave Address W (0) ACK Address Byte P ACK Data Byte
(P) ACK Data Byte
(P+1) ACK Data Byte
... ACK STOP
Length (bits) 1711818181811
Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39-46 47 ... ... ...
Description
START Slave
Address
W
(0)
A
C
K
Address
byte P
A
C
K
Repeated
START
Slave
Address
R
(1)
A
C
K
Data Byte
(P)
A
C
K
Data Byte
(P+1)
A
C
K
Data Byte
...
A
C
K
STOP
Length (bits) 1711811 7118181811
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 11 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Table 4B. Power Supply DC Characteristics, VCC = VCCO = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Item Rating
Supply Voltage, VCC 3.63V
Inputs, VI
XTAL_IN
Other Input
0V to 2V
-0.5V to VCC + 0.5V
Outputs, IO (LVPECL)
Continuous Current
Surge Current
Outputs, IO (SDATA)
Outputs, IO (LVDS)
Continuous Current
Surge Current
50mA
100mA
10mA
10mA
15mA
Package Thermal Impedance, JA 32.4C/W (0 mps)
Storage Temperature, TSTG -65C to 150C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC Core Supply Voltage 3.135 3.3 3.465 V
VCCA Analog Supply Voltage VCC – 0.32 3.3 VCC V
VCCO Output Supply Voltage 3.135 3.3 3.465 V
ICCA Analog Supply Current 32 mA
IEE Power Supply Current LVPECL 208 mA
ICC Power Supply Current LVDS 125 mA
ICCO Output Supply Current LVDS 124 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC Core Supply Voltage 2.375 2.5 2.625 V
VCCA Analog Supply Voltage VCC – 0.28 2.5 VCC V
VCCO Output Supply Voltage 2.375 2.5 2.625 V
ICCA Analog Supply Current 28 mA
IEE Power Supply Current LVPECL 200 mA
ICC Power Supply Current LVDS 122 mA
ICCO Output Supply Current LVDS 121 mA
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 12 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Table 4C. LVCMOS/LVTTL DC Characteristics, VCC = VCCO = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
NOTE 1: Outputs terminated with 50W to VCCO/2. In the Parameter Measurement Information Section, see Output Load Test Circuit
Diagrams.
Table 4D. Differential DC Characteristics, VCC = VCCO = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
NOTE 1: Common mode input voltage is at the cross point.
Table 4E. LVPECL DC Characteristics, VCC = VCCO = 3.3V±5%, VEE = 0V, TA = -40°C to 85°C
NOTE 1: Outputs termination with 50W to VCCO – 2V.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH
Input
High Voltage
SCLK, SDATA,
CLK_SEL, FSEL[1:0]
VCC = 3.3V 2 VCC + 0.3 V
VCC = 2.5V 1.7 VCC + 0.3 V
VIL
Input
Low Voltage
SCLK, SDATA,
CLK_SEL VCC = 3.3V -0.3 0.8 V
SCLK, SDATA,
CLK_SEL VCC = 2.5V -0.3 0.7 V
FSEL[1:0] VCC = 3.3V or 2.5V 0.5 V
IIH
Input
High Current
SCLK, SDATA VCC = VIN = 3.465V or 2.625V 5 µA
CLK_SEL, FSEL[1:0] VCC = VIN = 3.465V or 2.625V 150 µA
IIL
Input
Low Current
SCLK, SDATA VCC = 3.465V or 2.625V, VIN = 0V -150 µA
CLK_SEL, FSEL[1:0] VCC = 3.465V or 2.625V, VIN = 0V -5 µA
VOH
Output
High Voltage;
NOTE 1
LOCK VCCO = 3.465V 2.6 V
LOCK VCCO = 2.625V 1.8 V
VOL
Output
Low Voltage;
NOTE 1
LOCK VCCO = 3.465V or 2.625V 0.5 V
Symbol Parameter Test Conditions Minimum Typical Maximum Units
IIH
Input
High Current CLK, nCLK VCC = VIN = 3.465V or 2.625V 150 µA
IIL
Input
Low Current
nCLK VCC = 3.465V or 2.625V, VIN = 0V -150 µA
CLK VCC = 3.465V or 2.625V, VIN = 0V -5 µA
VPP Peak-to-Peak Voltage 0.15 1.3 V
VCMR
Common Mode Input Voltage;
NOTE 1 VEE VCC – 0.85 V
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH
Output High Voltage;
NOTE 1 VCCO – 1.1 VCCO – 0.75 V
VOL
Output Low Voltage;
NOTE 1 VCCO – 2.0 VCCO – 1.6 V
VSWING
Peak-to-Peak Output Voltage
Swing 0.6 1.0 V
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 13 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Table 4F. LVPECL DC Characteristics, VCC = VCCO = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
NOTE 1: Outputs termination with 50W to VCCO – 2V.
Table 4G. LVDS DC Characteristics, VCC = VCCO = 3.3V±5%, VEE = 0V, TA = -40°C to 85°C
Table 4H. LVDS DC Characteristics, VCC = VCCO = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
.
Table 5. Crystal Characteristics
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH Output High Voltage; NOTE 1 VCCO – 1.2 VCCO – 0.75 V
VOL Output Low Voltage; NOTE 1 VCCO – 2.0 VCCO – 1.5 V
VSWING
Peak-toPeak Output Voltage
Swing 0.5 1.0 V
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOD Differential Output Voltage 247 345 454 mV
VOD VOD Magnitude Change 50 mV
VOS Offset Voltage 1.15 1.25 1.375 V
VOS VOS Magnitude Change 50 mV
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOD Differential Output Voltage 230 340 454 mV
VOD VOD Magnitude Change 50 mV
VOS Offset Voltage 1.15 1.25 1.375 V
VOS VOS Magnitude Change 50 mV
Parameter Test Conditions Minimum Typical Maximum Units
Mode of Oscillation Fundamental
Frequency 10 40 MHz
Equivalent Series Resistance (ESR) 50
Load Capacitance (CL)1018pF
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 14 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
AC Electrical Characteristics
Table 6A. PCI Express Jitter Specifications, VCC = VCCO = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions. For additional information, refer to the PCI Express Application Note section in the datasheet.
NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1
is 86ps peak-to-peak for a sample size of 106 clock periods.
NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS
(High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band).
NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Express
Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification.
NOTE 4: This parameter is guaranteed by characterization. Not tested in production.
Symbol Parameter Test Conditions Minimum Typical Maximum
PCIe Industry
Specification Units
tj
(PCIe Gen 1)
Phase Jitter
Peak-to-Peak;
NOTE 1, 4
ƒ = 100MHz, 25MHz Crystal Input
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
8.3 13.2 86 ps
tREFCLK_HF_RMS
(PCIe Gen 2)
Phase Jitter
RMS; NOTE 2, 4
ƒ = 100MHz, 25MHz Crystal Input
High Band: 1.5MHz - Nyquist
(clock frequency/2)
0.78 1.35 3.1 ps
tREFCLK_LF_RMS
(PCIe Gen 2)
Phase Jitter
RMS; NOTE 2, 4
ƒ = 100MHz, 25MHz Crystal Input
Low Band: 10kHz - 1.5MHz 0.05 0.10 3.0 ps
tREFCLK_RMS
(PCIe Gen 3)
Phase Jitter
RMS;
NOTE 3, 4
ƒ = 100MHz, 25MHz Crystal Input
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
0.175 0.34 0.8 ps
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 15 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Table 6B. AC Characteristics, VCC = VCCO = 3.3V ± 5% or 2.5V ± 5% VEE = 0V, TA = -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Refer to Phase Noise Plots.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoints.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: Refer to tLOCK and tTRANSITION in Parameter Measurement Information.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
fDIFF_IN Differential Input Frequency 10 312.5 MHz
fVCO VCO Frequency 1910 2500 MHz
tjit(Ø)
RMS Phase Jitter, Random;
NOTE 1
25MHz Crystal, fOUT = 100MHz,
Integration Range:
12kHz – 20MHz
258 332 fs
25MHz Crystal, fOUT = 125MHz,
Integration Range: 12kHz –
20MHz
220 291 fs
25MHz Crystal, fOUT = 125MHz,
Integration Range: 10kHz – 1MHz 164 232 fs
25MHz Crystal, fOUT =
156.25MHz, Integration Range:
12kHz – 20MHz
228 306 fs
25MHz Crystal, fOUT =
156.25MHz, Integration Range:
10kHz – 1MHz
175 234 fs
25MHz Crystal, fOUT = 250MHz,
Integration Range: 12kHz –
20MHz
212 292 fs
30.72MHz Crystal, fOUT =
491.52MHz, Integration Range:
12kHz – 20MHz
213 299 fs
19.44MHz Crystal, fOUT =
622.08MHz, Integration Range:
12kHz – 20MHz
280 386 fs
tsk(o) Output Skew;
NOTE 2, 3
LVPECL
Outputs LVDS_SEL = 0 50 ps
LVDS
Outputs LVDS_SEL = 1 50 ps
tR / tF
Output
Rise/Fall
Time
LVPECL
Outputs 20% - 80%, LVDS_SEL = 0 100 400 ps
LVDS
Outputs 20% - 80%, LVDS_SEL = 1 100 400 ps
odc Output Duty Cycle
N > 3 Output Divider;
LVDS_SEL = 0 or 1 47 53 %
N 3 Output Divider;
LVDS_SEL = 0 or 1 42 58 %
tLOCK
PLL Lock
Time;
NOTE 3, 4
LOCK Output 20 ms
tTRANSITION
Transition
Time;
NOTE 3, 4
LOCK Output 20 ms
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 16 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Typical Phase Noise at 100MHz (3.3V)
Typical Phase Noise at 125MHz (3.3V)
Noise Power (dBc/Hz)
Offset Frequency (Hz)
Noise Power (dBc/Hz)
Offset Frequency (Hz)