IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 1 ©2014 Integrated Device Technology, Inc.
DATASHEET
Programmable FemtoClock® NG LVPECL/LVDS
Clock Generator with 6-Outputs
IDT8T49N006I
General Description
The IDT8T49N006I is a six output Clock Generator with selectable
LVDS or LVPECL outputs. The IDT8T49N006I can generate any one
of four frequencies from a single crystal or reference clock. The four
frequencies are selected from the Frequency Selection Table (Table
3A) and are programmed via I2C interface. The four predefined
frequencies are selected in the user application by two frequency
selection pins. Note the desired programmed frequencies must be
used with the corresponding crystal or clock frequency as indicated
in Table 3A.
Excellent phase noise performance is maintained with IDT’s Fourth
Generation FemtoClock® NG PLL technology, which delivers
sub-400fs RMS phase jitter.
Features
Fourth Generation FemtoClock NG PLL technology
Six selectable LVPECL or LVDS outputs via I2C
CLK, nCLK input pair can accept the following differential input
levels: LVPECL, LVDS, HCSL
FemtoClock NG VCO Range: 1.91GHz - 2.5GHz
RMS phase jitter at 156.25MHz (12kHz - 20MHz): 228fs (typical)
RMS phase jitter at 156.25MHz (10kHz - 1MHz): 175fs (typical)
Full 2.5V or 3.3V power supply
I2C programming interface
PCI Express (2.5 Gb/S), Gen 2 (5 Gb/s) and Gen 3 (8 Gb/s) jitter
compliant
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
Pin Assignment
IDT8T49N006I
40-Lead VFQFN
6mm x 6mm x 0.95mm package body
4.65mm x 4.65mm E-Pad
NL Package
Top View
1234 56 78 910
31
32
33
34
35
36
37
38
39
40
20
19
18
17
16
15
14
13
12
11
30 29 28 27 26 25 24 23 22 21
nc
nc
Q0
nQ0
V
CCO
Q1
nQ1
Q2
nQ2
V
EE
XTAL_OUT
XTAL_IN
V
EE
CLK
nCLK
FSEL0
ADDR_SEL
V
EE
V
CC
FSEL1
nc
nc
Q3
nQ3
V
CCO
Q4
nQ4
Q5
nQ5
V
EE
S D ATA
SCLK
VEE
VEE
VEE
VEE
VCCA
LOCK
VCC
CLK_SEL
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 2 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Block Diagram
CLK S E L
XTAL_IN
XTAL_OUT
Xtal
Osc
FemtoClock®NG
VCO
Divider,
Output Type
&
Output
Enable
Selection
÷P[1:0]
0
1
OUTPUT ENABLE
OUTPUT STYLE
6
6
Phase
Detector
+
Charge
Pump
PS
Pulldown
Pulldown
Pullup
Pullup
Pulldown
Pulldown
PU/PD
Pulldown
VPP/FSEL 0
PROG_CLK/FSEL 1
SCLK
SDATA
ADDR_SEL
CLK
nCLK
÷M [8:1]
1
0
LOCK
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
÷N[6:0]
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 3 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1, 2, 29, 30 nc Unused Not connected
3, 4 Q0, nQ0 Output Differential output pair. LVPECL or LVDS interface levels.
5, 26 VCCO Power Output supply pins.
6, 7 Q1, nQ1 Output Differential output pair. LVPECL or LVDS interface levels.
8, 9 Q2, nQ2 Output Differential output pair. LVPECL or LVDS interface levels.
10, 13, 18,
21, 31, 34,
37, 40
VEE Power Negative supply pins.
11,
12
XTAL_IN
XTAL_OUT Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Crystal frequency is selected from Table 3A.
14 CLK Input Pulldown Non-inverting differential clock input.
15 nCLK Input Pullup/
Pulldown Inverting differential clock input. Internal resistor bias to VCC/2.
16, 20 FSEL0,
FSEL1 Input Pulldown
Frequency and configuration. Selects between one of four factory
programmable power-up default configurations. The four configurations can
have different PLL states, output frequencies, output styles and output
states. These default configurations can be overwritten after power-up via
I2C.LVCMOS/LVTTL interface levels.
00 = Configuration 0 (default)
01 = Configuration 1
10 = Configuration 2
11 = Configuration 3
17 ADDR_SEL Input Pulldown I2C Address select pin. LVCMOS/LVTTL interface levels.
19, 38 VCC Power Core supply pins.
22, 23 nQ5, Q5 Output Differential output pair. LVPECL or LVDS interface levels.
24, 25 nQ4, Q4 Output Differential output pair. LVPECL or LVDS interface levels.
27, 28 nQ3, Q3 Output Differential output pair. LVPECL or LVDS interface levels.
32 SCLK Input Pullup I2C Clock Input. LVCMOS/LVTTL interface levels.
33 SDATA Input/Output Pullup I2C Data Input. Input: LVCMOS/LVTTL interface levels. Output: Open
Drain.
35 VCCA Power Analog supply pin.
36 LOCK Output PLL Lock Indicator.
39 CLK_SEL Input Pulldown
Input source select pin. LVCMOS/LVTTL interface levels.
0 = XTAL (default)
1 = CLK, nCLK
Symbol Parameter Test Conditions Minimum Typical Maximum Units
CIN Input Capacitance 3.5 pF
RPULLDOWN Input Pulldown Resistor 51 k
RPULLUP Input Pullup Resistor 51 k
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 4 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Frequency Configuration
Table 3A. Frequency Configuration Examples
NOTE: Each device supports 4 output frequencies (with related input or crystal value) as selected from this table Register Settings.
NOTE: XTAL operation: fOUT = fREF * PS * M / N; CLK, nCLK input operation: fOUT = (fREF / P) * PS * M / N.
Output Frequencies
(MHz)
Input Frequency or
Crystal Frequency
(MHz)
Input Clock
Divider
P
Input Clock
Prescaler
PS
Feedback
Divider
M
Output
Divider
N
VCO Frequency
(MHz)
30.72 30.72 1 x2 32 64 1966.08
61.44 30.72 1 x2 32 32 1966.08
62.5 25 1 x2 40 32 2000
76.8 30.72 1 x2 40 32 2457.6
78.125 25 1 x2 50 32 2500
100 25 1 x2 40 20 2000
106.25 26.5625 1 x2 40 20 2125
122.8 30.72 1 x2 32 16 1966.08
125 25 1 x2 40 16 2000
133.33 25 1 x2 48 18 2400
148.5 27 1 x2 44 16 2376
150 25 1 x2 42 14 2100
153.6 30.72 1 x2 40 16 2457.6
155.52 19.44 1 x2 64 16 2488.32
156.25
25 1 x2 50 16 2500
100 2 x1 50 16 2500
125 5 x2 50 16 2500
159.375 26.5625 1 x2 36 12 1912.5
160 20 1 x2 48 12 1920
166.66 25 1 x2 40 12 2000
184.32 30.72 1 x2 36 12 2211.84
61.44 1 x1 36 12 2211.84
187.5 25 1 x1 90 12 2250
200 25 1 x2 40 10 2000
212.5 26.5625 1 x2 40 10 2125
250 25 1 x2 40 8 2000
300 25 1 x2 48 8 2400
311.04
19.44 1 x2 64 8 2488.32
77.76 1 x1 32 8 2488.32
155.52 2 x1 32 8 2488.32
312.5
25 1 x2 50 8 2500
125 2 x1 40 8 2500
156.25 5 x2 40 8 2500
318.75 26.5625 1 x2 36 6 1912.5
322.265625 25.78125 2 x1 150 6 1933.59375
375 25 1 x1 90 6 2250
400 25 1 x2 40 5 2000
425 26.5625 1 x2 40 5 2125
491.52 30.72 1 x2 32 4 1966.08
614.4
30.72 1 x2 40 4 2457.6
122.88 2 x1 40 4 2457.6
153.6 5 x2 40 4 2457.6
622.08 19.44 1 x2 64 4 2488.32
625 25 1 x2 50 4 2500
1228.88 30.72 1 x2 40 2 2457.6
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 5 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Table 3B. I2C Register Map
Register
Binary
Register
Address
Register Bit
D7 D6 D5 D4 D3 D2 D1 D0
0 00000 M0[8] M0[7] M0[6] M0[5] M0[4] M0[3] M0[2] M0[1]
1 00001 M1[8] M1[7] M1[6] M1[5] M1[4] M1[3] M1[2] M1[1]
2 00010 M2[8] M2[7] M2[6] M2[5] M2[4] M2[3] M2[2] M2[1]
3 00011 M3[8] M3[7] M3[6] M3[5] M3[4] M3[3] M3[2] M3[1]
4 00100 unused N0[6] N0[5] N0[4] N0[3] N0[2] N0[1] N0[0]
5 00101 unused N1[6] N1[5] N1[4] N1[3] N1[2] N1[1] N1[0]
6 00110 unused N2[6] N2[5] N2[4] N2[3] N2[2] N2[1] N2[0]
7 00111 unused N3[6] N3[5] N3[4] N3[3] N3[2] N3[1] N3[0]
8 01000 unused BYPASS0 PS0[1] PS0[0] P0[1] P0[0] CP0[1] CP0[0]
9 01001 unused BYPASS1 PS1[1] PS1[0] P1[1] P1[0] CP1[1] CP1[0]
10 01010 unused BYPASS2 PS2[1] PS2[0] P2[1] P2[0] CP2[1] CP2[0]
11 01011 unused BYPASS3 PS3[1] PS3[0] P3[1] P3[0] CP3[1] CP3[0]
12 01100 LVDS_SEL0[Q5] LVDS_SEL0[Q4] LVDS_SEL0[Q3] reserved LVDS_SEL0[Q2] LVDS_SEL0[Q1] LVDS_SEL0[Q0] reserved
13 01101 LVDS_SEL1[Q5] LVDS_SEL1[Q4] LVDS_SEL1[Q3] reserved LVDS_SEL1[Q2] LVDS_SEL1[Q1] LVDS_SEL1[Q0] reserved
14 01110 LVDS_SEL2[Q5] LVDS_SEL2[Q4] LVDS_SEL2[Q3] reserved LVDS_SEL2[Q2] LVDS_SEL2[Q1] LVDS_SEL2[Q0] reserved
15 01111 LVDS_SEL3[Q5] LVDS_SEL3[Q4] LVDS_SEL3[Q3] reserved LVDS_SEL3[Q2] LVDS_SEL3[Q1] LVDS_SEL3[Q0] reserved
16 10000 OE0[Q5] OE0[Q4] OE0[Q3] reserved OE0[Q2] OE0[Q1] OE0[Q0] reserved
17 10001 OE1[Q5] OE1[Q4] OE1[Q3] reserved OE1[Q2] OE1[Q1] OE1[Q0] reserved
18 10010 OE2[Q5] OE2[Q4] OE2[Q3] reserved OE2[Q2] OE2[Q1] OE2[Q0] reserved
19 10011 OE3[Q5] OE3[Q4] OE3[Q3] reserved OE3[Q2] OE3[Q1] OE3[Q0] reserved
20 10100 reserved reserved reserved reserved reserved reserved unused unused
21 10101 unused unused unused unused unused unused unused unused
22 10110 unused unused unused unused unused unused unused unused
23 10111 unused unused unused unused unused unused unused unused
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 6 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Table 3C. I2C Function Descriptions
Bits Name Function
Pn[1:0] Input Clock Divider Register
(n = 0...3)
Sets the PLL input clock divider. The divider value has the range of 1, 2, 4
and 5. See Table 3F. Pn[1:0] bits are programmed with values to support
default configuration settings for FSEL[1:0].
PSn(1:0) Input Prescaler Register n
(n = 0...3)
Sets the PLL input clock prescaler value. Valid prescaler values are x0.5, x1
or x2. See Table 3F. Set prescaler to x2 for optimum phase noise
performance. PSn[1:0] bits are programmed with values to support default
configuration settings for FSEL[1:0].
Mn[8:1]
Integer Feedback Divider
Register n
(n = 0...3)
Sets the integer feedback divider value. Based on the FemtoClock NG VCO
range, the applicable feedback dividers settings are 16 thru 250. Please
note the register value presents bits [8:1] of Mn, the LSB of Mn is not in the
register. Mn[8;1] bits are programmed with values to support default
configuration settings for FSEL[1:0].
Nn[6:0] Output Divider Register n
(n = 0...3)
Sets the output divider. The output divider value can range from 2, 3, 4, 5, 6
and 8, 10, 12 to 126 (step: 2). See Table 3G for the output divider coding.
Nn[6:0] bits are programmed with values to support default configuration
settings for FSEL[1:0].
CPn[1:0] PLL Bandwidth Register n
(n = 0...3)
Sets the FemtoClock NG PLL bandwidth by controlling the charge pump
current. See Table 3H. CPn[1:0] bits are programmed with values to
support default configuration settings for FSEL[1:0].
BYPASSn PLL Bypass Register n
(n = 0...3)
Bypasses PLL. Output of the prescaler is routed through the output divider
N to the output fanout buffer. Programming a 1 to this bit bypasses the PLL.
Programming a 0 to this bit routes the output of the prescaler through the
PLL. BYPASSn bits are programmed with values to support default
configuration settings for FSEL[1:0].
OEn[Q0]
OEn[Q1]
OEn[Q2]
OEn[Q3]
OEn[Q4]
OEn[Q5]
Output Enable Register n
(n = 0...3)
Sets the outputs to Active or High Impedance. Programming a 0 to this bit
sets the outputs to High Impedance. Programming a 1 sets the outputs to
active status. OEn[Q0], OEn[Q1], OEn[Q2], OEn[Q3], OEn[Q4], and
OEn[Q5] bits are programmed with values to support default configuration
settings for FSEL[1:0].
LVDS_SELn[Q0]
LVDS_SELn[Q1]
LVDS_SELn[Q2]
LVDS_SELn[Q3]
LVDS_SELn[Q4]
LVDS_SELn[Q5]
Output Style Register n
(n = 0...3)
Sets the differential output style to either LVDS or LVPECL interface levels.
Programming a 1 to this bit sets the output styles to LVDS levels.
Programming a 0 to this bit sets the output styles to LVPECL levels.
LVDS_SELn[Q0], LVDS_SELn[Q1], LVDS_SELn[Q2], LVDS_SELn[Q3],
LVDS_SELn[Q4], and LVDS_SELn[Q5] bits are programmed with values to
support default configuration settings for FSEL[1:0].
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 7 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Table 3D. Feedback Divider Mn Coding
NOTE: Mn is always an even value. The Mn[0] bits are not implemented.
Register Bit
Feedback Divider MnMn[8:1]
Do Not Use 1 thru 15
00001000 16
00001001 18
00001010 20
00001011 22
00001100 thru 00011111 24 thru 62
00100000 64
00100001 66
00100010 68
00100011 70
00100100 72
... Mn
00110010 100
00110011 102
00110100 104
00110101 106
... Mn
01111010 244
01111011 246
01111100 248
01111101 250
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 8 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Table 3E. Input Clock Divider Pn and Prescaler PSn Coding
Table 3F. Output Divider Nn Coding
NOTE: X denotes “don’t care”.
CLK_SEL Input P[1:0] PS[1:0]
Input Clock
Divider
P
Input Clock
Prescaler
PS
Input Frequency (MHz)
Minimum Maximum
0XTALxx
00 1 x1 10 40
01 1 x0.5 20 40
1x1x2540
1CLK
00
00 1 x1 10 120
01 1 x0.5 20 240
1x1x2560
01
00 2 x1 20 240
01 2 x0.5 40 480
1x 2 x2 10 120
10
00 4 x1 40 480
01 4 x0.5 80 800
1x 4 x2 20 240
11
00 5 x1 50 600
01 5 x0.5 100 800
1x 5 x2 25 300
Register Bit
Frequency N
Output Frequency Range
Nn[6:0] fOUT_MIN (MHz) fOUT_MAX (MHz)
000000X 2 955 1250
0000010 2 955 1250
0000011 3 636.667 833.333
0000100 4 477.5 625
0000101 5 382 500
000011X 6 318.333 416.667
000100X 8 238.75 312.5
000101X 10 191 250
000110X 12 159.167 208.333
000111X 14 136.429 178.571
001000X 16 119.375 156.25
... N (even integer) (1910 ÷ N) (2500 ÷ N)
111101X 124 15.403 20.161
111111X 126 15.159 19.841
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 9 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Table 3G. Charge Pump CP Settings
NOTE: FemtoClock NG PLL stability is only guaranteed over the feedback divider ranges listed is Table 3G.
Power-up Default Configuration Description
The IDT8T49N006I supports a variety of options such as different
output styles, number of programmed default frequencies, output en-
able and operating temperature range. The device options and de-
fault frequencies must be specified at the time of order and are
programmed by IDT prior to shipment. The document, Programma-
ble FemtoClock® NG Product Ordering Guide specifies the available
order codes, including the device options and default frequency con-
figurations. Example part number: 8T49N004A-007NLGI, specifies a
quad frequency clock generator with default frequencies of
106.25MHz, 133.333MHz, 156.25MHz and 156.25MHz, with four
LVDS outputs that are enabled after power-up, specified over the in-
dustrial temperature range and housed in a lead-free (6/6 RoHS)
VFQFN package.
Other order codes with respective programmed frequencies are
available from IDT upon request. After power-up changes to the
output frequencies are controlled by FSEL[1:0] or the I2C interface.
Changes to the style (LVDS or LVPECL) and state (active or high
impedance) of each individual output can also be controlled with the
I2C interface after power up.
Table 3H. Power-up Default Settings
Register Bit Feedback Divider (M) Value Range
CPn1 CPn0 Minimum Maximum
0 0 16 48
0 1 48 100
10 100 250
11 192 250
FSEL1 FSEL0 Frequency
PLL State
(On or Bypass)
Output State
(Active or High
Impedance)
Output Style
(LVDS or LVPECL)
0 (default) 0 (default) Frequency 0 PLL State 0 Output State 0 Output Style 0
0 1 Frequency 1 PLL State 1 Output State 1 Output Style 1
1 0 Frequency 2 PLL State 2 Output State 2 Output Style 2
1 1 Frequency 3 PLL State 3 Output State 3 Output Style 3
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 10 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Serial Interface Configuration Description
The IDT8T49N006I has an I2C-compatible configuration interface to
access any of the internal registers (Table 3B) for frequency and PLL
parameter programming. The IDT8T49N006I acts as a slave device
on the I2C bus and has the address 0b110111x, where x is set by the
value on ADDR_SEL input. (See Tables 3I & 3J). The interface
accepts byte-oriented block write and block read operations. An
address byte (P) specifies the register address (Table 3B) as the byte
position of the first register to write or read. Data bytes (registers) are
accessed in sequential order from the lowest to the highest byte
(most significant bit first, see Table 3K, 3L).
Read and write block transfers can be stopped after any complete
byte transfer. It is recommended to terminate the I2C read or write
transfer after accessing byte #23 by sending a stop command.
For full electrical I2C compliance, it is recommended to use external
pull-up resistors for SDATA and SCLK. The internal pull-up resistors
have a size of 50kW typical.
Table 3I. I2C Device Slave Address ADDR_SEL = 0 (default)
Table 3J. I2C Device Slave Address ADDR_SEL = 1
Table 3K. Block Write Operation
Table 3L. Block Read Operation
1101110R/W
1101111R/W
Bit 1 2:8 9 10 11:18 19 20:27 28 29-36 37 ... ... ...
Description START Slave Address W (0) ACK Address Byte P ACK Data Byte
(P) ACK Data Byte
(P+1) ACK Data Byte
... ACK STOP
Length (bits) 1711818181811
Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39-46 47 ... ... ...
Description
START Slave
Address
W
(0)
A
C
K
Address
byte P
A
C
K
Repeated
START
Slave
Address
R
(1)
A
C
K
Data Byte
(P)
A
C
K
Data Byte
(P+1)
A
C
K
Data Byte
...
A
C
K
STOP
Length (bits) 1711811 7118181811
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 11 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Table 4B. Power Supply DC Characteristics, VCC = VCCO = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Item Rating
Supply Voltage, VCC 3.63V
Inputs, VI
XTAL_IN
Other Input
0V to 2V
-0.5V to VCC + 0.5V
Outputs, IO (LVPECL)
Continuous Current
Surge Current
Outputs, IO (SDATA)
Outputs, IO (LVDS)
Continuous Current
Surge Current
50mA
100mA
10mA
10mA
15mA
Package Thermal Impedance, JA 32.4C/W (0 mps)
Storage Temperature, TSTG -65C to 150C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC Core Supply Voltage 3.135 3.3 3.465 V
VCCA Analog Supply Voltage VCC – 0.32 3.3 VCC V
VCCO Output Supply Voltage 3.135 3.3 3.465 V
ICCA Analog Supply Current 32 mA
IEE Power Supply Current LVPECL 208 mA
ICC Power Supply Current LVDS 125 mA
ICCO Output Supply Current LVDS 124 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC Core Supply Voltage 2.375 2.5 2.625 V
VCCA Analog Supply Voltage VCC – 0.28 2.5 VCC V
VCCO Output Supply Voltage 2.375 2.5 2.625 V
ICCA Analog Supply Current 28 mA
IEE Power Supply Current LVPECL 200 mA
ICC Power Supply Current LVDS 122 mA
ICCO Output Supply Current LVDS 121 mA
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 12 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Table 4C. LVCMOS/LVTTL DC Characteristics, VCC = VCCO = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
NOTE 1: Outputs terminated with 50W to VCCO/2. In the Parameter Measurement Information Section, see Output Load Test Circuit
Diagrams.
Table 4D. Differential DC Characteristics, VCC = VCCO = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
NOTE 1: Common mode input voltage is at the cross point.
Table 4E. LVPECL DC Characteristics, VCC = VCCO = 3.3V±5%, VEE = 0V, TA = -40°C to 85°C
NOTE 1: Outputs termination with 50W to VCCO – 2V.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH
Input
High Voltage
SCLK, SDATA,
CLK_SEL, FSEL[1:0]
VCC = 3.3V 2 VCC + 0.3 V
VCC = 2.5V 1.7 VCC + 0.3 V
VIL
Input
Low Voltage
SCLK, SDATA,
CLK_SEL VCC = 3.3V -0.3 0.8 V
SCLK, SDATA,
CLK_SEL VCC = 2.5V -0.3 0.7 V
FSEL[1:0] VCC = 3.3V or 2.5V 0.5 V
IIH
Input
High Current
SCLK, SDATA VCC = VIN = 3.465V or 2.625V 5 µA
CLK_SEL, FSEL[1:0] VCC = VIN = 3.465V or 2.625V 150 µA
IIL
Input
Low Current
SCLK, SDATA VCC = 3.465V or 2.625V, VIN = 0V -150 µA
CLK_SEL, FSEL[1:0] VCC = 3.465V or 2.625V, VIN = 0V -5 µA
VOH
Output
High Voltage;
NOTE 1
LOCK VCCO = 3.465V 2.6 V
LOCK VCCO = 2.625V 1.8 V
VOL
Output
Low Voltage;
NOTE 1
LOCK VCCO = 3.465V or 2.625V 0.5 V
Symbol Parameter Test Conditions Minimum Typical Maximum Units
IIH
Input
High Current CLK, nCLK VCC = VIN = 3.465V or 2.625V 150 µA
IIL
Input
Low Current
nCLK VCC = 3.465V or 2.625V, VIN = 0V -150 µA
CLK VCC = 3.465V or 2.625V, VIN = 0V -5 µA
VPP Peak-to-Peak Voltage 0.15 1.3 V
VCMR
Common Mode Input Voltage;
NOTE 1 VEE VCC – 0.85 V
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH
Output High Voltage;
NOTE 1 VCCO – 1.1 VCCO – 0.75 V
VOL
Output Low Voltage;
NOTE 1 VCCO – 2.0 VCCO – 1.6 V
VSWING
Peak-to-Peak Output Voltage
Swing 0.6 1.0 V
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 13 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Table 4F. LVPECL DC Characteristics, VCC = VCCO = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
NOTE 1: Outputs termination with 50W to VCCO – 2V.
Table 4G. LVDS DC Characteristics, VCC = VCCO = 3.3V±5%, VEE = 0V, TA = -40°C to 85°C
Table 4H. LVDS DC Characteristics, VCC = VCCO = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
.
Table 5. Crystal Characteristics
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH Output High Voltage; NOTE 1 VCCO – 1.2 VCCO – 0.75 V
VOL Output Low Voltage; NOTE 1 VCCO – 2.0 VCCO – 1.5 V
VSWING
Peak-toPeak Output Voltage
Swing 0.5 1.0 V
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOD Differential Output Voltage 247 345 454 mV
VOD VOD Magnitude Change 50 mV
VOS Offset Voltage 1.15 1.25 1.375 V
VOS VOS Magnitude Change 50 mV
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOD Differential Output Voltage 230 340 454 mV
VOD VOD Magnitude Change 50 mV
VOS Offset Voltage 1.15 1.25 1.375 V
VOS VOS Magnitude Change 50 mV
Parameter Test Conditions Minimum Typical Maximum Units
Mode of Oscillation Fundamental
Frequency 10 40 MHz
Equivalent Series Resistance (ESR) 50
Load Capacitance (CL)1018pF
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 14 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
AC Electrical Characteristics
Table 6A. PCI Express Jitter Specifications, VCC = VCCO = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions. For additional information, refer to the PCI Express Application Note section in the datasheet.
NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1
is 86ps peak-to-peak for a sample size of 106 clock periods.
NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS
(High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band).
NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Express
Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification.
NOTE 4: This parameter is guaranteed by characterization. Not tested in production.
Symbol Parameter Test Conditions Minimum Typical Maximum
PCIe Industry
Specification Units
tj
(PCIe Gen 1)
Phase Jitter
Peak-to-Peak;
NOTE 1, 4
ƒ = 100MHz, 25MHz Crystal Input
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
8.3 13.2 86 ps
tREFCLK_HF_RMS
(PCIe Gen 2)
Phase Jitter
RMS; NOTE 2, 4
ƒ = 100MHz, 25MHz Crystal Input
High Band: 1.5MHz - Nyquist
(clock frequency/2)
0.78 1.35 3.1 ps
tREFCLK_LF_RMS
(PCIe Gen 2)
Phase Jitter
RMS; NOTE 2, 4
ƒ = 100MHz, 25MHz Crystal Input
Low Band: 10kHz - 1.5MHz 0.05 0.10 3.0 ps
tREFCLK_RMS
(PCIe Gen 3)
Phase Jitter
RMS;
NOTE 3, 4
ƒ = 100MHz, 25MHz Crystal Input
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
0.175 0.34 0.8 ps
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 15 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Table 6B. AC Characteristics, VCC = VCCO = 3.3V ± 5% or 2.5V ± 5% VEE = 0V, TA = -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Refer to Phase Noise Plots.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoints.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: Refer to tLOCK and tTRANSITION in Parameter Measurement Information.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
fDIFF_IN Differential Input Frequency 10 312.5 MHz
fVCO VCO Frequency 1910 2500 MHz
tjit(Ø)
RMS Phase Jitter, Random;
NOTE 1
25MHz Crystal, fOUT = 100MHz,
Integration Range:
12kHz – 20MHz
258 332 fs
25MHz Crystal, fOUT = 125MHz,
Integration Range: 12kHz –
20MHz
220 291 fs
25MHz Crystal, fOUT = 125MHz,
Integration Range: 10kHz – 1MHz 164 232 fs
25MHz Crystal, fOUT =
156.25MHz, Integration Range:
12kHz – 20MHz
228 306 fs
25MHz Crystal, fOUT =
156.25MHz, Integration Range:
10kHz – 1MHz
175 234 fs
25MHz Crystal, fOUT = 250MHz,
Integration Range: 12kHz –
20MHz
212 292 fs
30.72MHz Crystal, fOUT =
491.52MHz, Integration Range:
12kHz – 20MHz
213 299 fs
19.44MHz Crystal, fOUT =
622.08MHz, Integration Range:
12kHz – 20MHz
280 386 fs
tsk(o) Output Skew;
NOTE 2, 3
LVPECL
Outputs LVDS_SEL = 0 50 ps
LVDS
Outputs LVDS_SEL = 1 50 ps
tR / tF
Output
Rise/Fall
Time
LVPECL
Outputs 20% - 80%, LVDS_SEL = 0 100 400 ps
LVDS
Outputs 20% - 80%, LVDS_SEL = 1 100 400 ps
odc Output Duty Cycle
N > 3 Output Divider;
LVDS_SEL = 0 or 1 47 53 %
N 3 Output Divider;
LVDS_SEL = 0 or 1 42 58 %
tLOCK
PLL Lock
Time;
NOTE 3, 4
LOCK Output 20 ms
tTRANSITION
Transition
Time;
NOTE 3, 4
LOCK Output 20 ms
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 16 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Typical Phase Noise at 100MHz (3.3V)
Typical Phase Noise at 125MHz (3.3V)
Noise Power (dBc/Hz)
Offset Frequency (Hz)
Noise Power (dBc/Hz)
Offset Frequency (Hz)
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 17 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Typical Phase Noise at 156.25MHz (3.3V)
Noise Power (dBc/Hz)
Offset Frequency (Hz)
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 18 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Parameter Measurement Information
3.3V LVPECL Output Load AC Test Circuit
3.3V LVDS Output Load AC Test Circuit
Differential Input Levels
2.5V LVPECL Output Load AC Test Circuit
2.5V LVDS Output Load AC Test Circuit
RMS Phase Jitter
VCC,
2V
-1.3V ± 0.165V
2V
VCCA
VCCO
3.3V ±5%
VCC,
VCCO VCCA
VCC
VEE
nCLK
CLK
-0.5V ± 0.125V
VCC,
2V
2V
VCCA
VCCO
SCOPE
Qx
nQx
2.5V±5%
POWER SUPPLY
+–
Float GND
VCC,
VCCO VCCA
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 19 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Parameter Measurement Information, continued
Output Skew
LVPECL Output Rise/Fall Time
Offset Voltage Setup
Output Duty Cycle/Pulse Width/Period
LVDS Output Rise/Fall Time
Differential Output Voltage Setup
nQx
Qx
nQy
Qy
nQ[0:5]
Q[0:5]
nQ[0:5]
Q[0:5]
20%
80% 80%
20%
tRtF
VOD
nQ[0:5]
Q[0:5]
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 20 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Parameter Measurement Information, continued
Lock Time and Transition Time
Applications Information
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1kW resistor can be used.
CLK/nCLK Inputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1kW resistor can be tied from CLK to ground.
Crystal Inputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kW resistor can be tied from
XTAL_IN to ground.
Outputs:
LVPECL Outputs
All unused LVPECL output pairs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
LVDS Outputs
All unused LVDS output pairs can be either left floating or terminated
with 100W across. If they are left floating, there should be no trace
attached.
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 21 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept single
ended levels. The reference voltage V1= VCC/2 is generated by the
bias resistors R1 and R2. The bypass capacitor (C1) is used to help
filter noise on the DC bias. This bias circuit should be located as close
to the input pin as possible. The ratio of R1 and R2 might need to be
adjusted to position the V1 in the center of the input voltage swing.
For example, if the input clock swing is 2.5V and VCC = 3.3V, R1 and
R2 value should be adjusted to set V1 at 1.25V. The values below are
for when both the single ended swing and VCC are at the same
voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
line impedance. For most 50W applications, R3 and R4 can be 100W.
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VCC + 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
Receiv er
+
-R4
100
R3
100
RS Zo = 50 Ohm
Ro
Driver
VCC
VCC
R2
1K
R1
1K
C1
0.1uF
Ro + Rs = Zo
V1
VCC VCC
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 22 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Overdriving the XTAL Interface
The XTAL_IN input can be overdriven by an LVCMOS driver or by one
side of a differential driver through an AC coupling capacitor. The
XTAL_OUT pin can be left floating. The amplitude of the input signal
should be between 500mV and 1.8V and the slew rate should not be
less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be
reduced from full swing to at least half the swing in order to prevent
signal interference with the power rail and to reduce internal noise.
Figure 2A shows an example of the interface diagram for a high
speed 3.3V LVCMOS driver. This configuration requires that the sum
of the output impedance of the driver (Ro) and the series resistance
(Rs) equals the transmission line impedance. In addition, matched
termination at the crystal input will attenuate the signal in half. This
can be done in one of two ways. First, R1 and R2 in parallel should
equal the transmission line impedance. For most 50 applications,
R1 and R2 can be 100. This can also be accomplished by removing
R1 and changing R2 to 50. The values of the resistors can be
increased to reduce the loading for a slower and weaker LVCMOS
driver. Figure 2B shows an example of the interface diagram for an
LVPECL driver. This is a standard LVPECL termination with one side
of the driver feeding the XTAL_IN input. It is recommended that all
components in the schematics be placed in the layout. Though some
components might not be used, they can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a quartz crystal as the input.
Figure 2A. General Diagram for LVCMOS Driver to XTAL Input Interface
Figure 2B. General Diagram for LVPECL Driver to XTAL Input Interface
VCC XTAL_OUT
XTAL_IN
R1
100
R2
100
Z o = 50 ohmsRs
Ro
Zo = Ro + Rs
C1
.1uf
LVCMOS Driver
XTAL_OUT
XTAL_IN
Zo = 50 ohms C2
.1uf
LV P E CL Driver
Zo = 50 ohms
R1
50 R2
50
R3
50
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 23 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
3.3V Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, HCSL and other differential
signals. Both VSWING and VOH must meet the VPP and VCMR input
requirements. Figures 3A to 3D show interface examples for the
CLK/nCLK input driven by the most common driver types. The input
interfaces suggested here are examples only. If the driver is from
another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the driver
termination requirements.
Figure 3A. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 3C. CLK/nCLK Input Driven by a
3.3V HCSL Driver
Figure 3B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 3D. CLK/nCLK Input Driven by a 3.3V LVDS Driver
3
.
3V
C
L
K
n
L
3
.
3V
3
.
3V
LVPE
CL
Differential
In
p
u
t
H
CSL
*R
3
*
R4
C
L
K
n
L
3
.
3V
3
.
3V
Diff
e
r
e
nti
a
l
In
p
u
t
CLK
nCLK
Differential
Input
LVPECL
3.3V
Zo = 50Ω
Zo = 50Ω
3.3V
R1
50Ω
R2
50Ω
R2
50Ω
3.3V
R1
100Ω
LVDS
CLK
nCLK
3.3V
Receiver
Zo = 50Ω
Zo = 50Ω
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 24 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
2.5V Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, HCSL and other differential
signals. Both VSWING and VOH must meet the VPP and VCMR input
requirements. Figures 4A to 4D show interface examples for the
CLK/nCLK input driven by the most common driver types. The input
interfaces suggested here are examples only. If the driver is from
another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the driver
termination requirements.
Figure 4A. CLK/nCLK Input Driven by a
2.5V LVPECL Driver
Figure 4C. CLK/nCLK Input Driven by a
2.5V HCSL Driver
Figure 4B. CLK/nCLK Input Driven by a
2.5V LVPECL Driver
Figure 4D. CLK/nCLK Input Driven by a 2.5V LVDS Driver
R3
250
R4
250
R1
6
2.
5
R2
6
2.
5
2
.
5V
Zo
=
50
Zo
=
50
C
L
K
nC
L
K
2
.
5V
2
.
5V
L
VPE
CL
Differential
I
nput
HCSL
*
R
3
33
*R4
33
C
L
K
nC
L
K
2
.
5V
2
.
5V
Zo
=
50
Zo
=
50
D
i
ffe
r
e
nti
a
l
I
nput
R1
50
R2
50
*O
ptional
R
3
a
n
d
R4
ca
n
be
0
C
L
K
nC
L
K
D
i
ffe
r
e
nti
a
l
I
nput
L
VPE
CL
2
.
5V
Zo
=
50
Zo
=
50
2
.
5V
R1
50
R2
50
R3
1
8
2
.
5V
R1
1
00
L
VD
S
C
L
K
nC
L
K
2
.
5V
Differential
I
nput
Zo
=
50
Zo
=
50
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 25 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
LVDS Driver Termination
For a general LVDS interface, the recommended value for the
termination impedance (ZT) is between 90W and 132W. The actual
value should be selected to match the differential impedance (Z0) of
your transmission line. A typical point-to-point LVDS design uses a
100W parallel resistor at the receiver and a 100W differential
transmission-line environment. In order to avoid any
transmission-line reflection issues, the components should be
surface mounted and must be placed as close to the receiver as
possible. IDT offers a full line of LVDS compliant devices with two
types of output structures: current source and voltage source. The
standard termination schematic as shown in Figure 5A can be used
with either type of output structure. Figure 5B, which can also be
used with both output types, is an optional termination with center tap
capacitance to help filter common mode noise. The capacitor value
should be approximately 50pF. If using a non-standard termination, it
is recommended to contact IDT and confirm if the output structure is
current source or voltage source type. In addition, since these
outputs are LVDS compatible, the input receiver’s amplitude and
common-mode input range should be verified for compatibility with
the output.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50W
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 6A and 6B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
Figure 6A. 3.3V LVPECL Output Termination Figure 6B. 3.3V LVPECL Output Termination
LVDS
Driver
LVDS
Driver
LVDS
Receiver
LVDS
Receiver
ZT
C
ZO ZT
ZO ZT
ZT
2
ZT
2
Figure 5A. Standard Termination
Figure 5B. Optional Termination
R1
84
R2
84
3.3V
R3
125
R4
125
Zo = 50
Zo = 50
LVPECL Input
3.3V
3.3V
+
_
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 26 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Termination for 2.5V LVPECL Outputs
Figure 7A and Figure 9B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating
50W to VCCO – 2V. For VCCO = 2.5V, the VCCO – 2V is very close to
ground level. The R3 in Figure 7B can be eliminated and the
termination is shown in Figure 7C.
Figure 7A. 2.5V LVPECL Driver Termination Example
Figure 7C. 2.5V LVPECL Driver Termination Example
Figure 7B. 2.5V LVPECL Driver Termination Example
2.5V LVPECL Driver
V
CCO
= 2.5V
2.5V
2.5V
50
50
R1
250
R3
250
R2
62.5
R4
62.5
+
2.5V LVPECL Driver
V
CCO
= 2.5V
2.5V
50
50
R1
50
R2
50
+
2.5V LVPECL Driver
VCCO = 2.5V
2.5V
50
50
R1
50
R2
50
R3
18
+
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 27 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 8. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
Figure 8. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
SOLDERSOLDER PINPIN EXPOSED HEAT SLUG
PIN PAD PIN PADGROUND PLANE LAND PATTERN
(GROUND PAD)
THERMAL VIA
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 28 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Schematic Layout
Figure 9 (next page) shows an example of IDT8T49N006I application
schematic. The schematic focuses on functional connections and is
not configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure that the logic control inputs are
properly set.
In this example, the device is operated at VCC = VCCO = VCCA = 3.3V.
The CLK, nCLK inputs are provided by a 3.3V LVPECL driver and
depicted with a Y-termination rather than the standard four resistor
VCC - 2V Thevinin termination for reasons of minimum termination
power and layout simplicity. Three examples of LVPECL
terminations are shown for the outputs to demonstrate mixing of
LVPECL termination design options.
As with any high speed analog circuitry, the power supply pins are
vulnerable to noise. To achieve optimum jitter performance, power
supply isolation is required. The IDT8T49N006I provides separate
power supplies to isolate from coupling into the internal PLL.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1uF capacitor in each power pin filter should be placed on the
device side of the PCB and the other components can be placed on
the opposite side. Power supply filter recommendations are a general
guideline to be used for reducing external noise from coupling into
the devices.
The VCC and VCCO filters start to attenuate noise at approximately
10kHz. If a specific frequency noise component is known, such as
switching power supplies frequencies, it is recommended that
component values be adjusted and if required, additional filtering be
added. Additionally, good general design practices for power plane
voltage stability suggests adding bulk capacitance in the local area of
all devices.
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 29 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Figure 9. IDT8T49N006I Application Schematic
Q 1_N
Q 4_P
Q 1_P
Q 0_P
Q5_N
For AC termination options consult the IDT Applications Note
"Termination - 3.3V LVPECL"
Optional F our R esis tor
T hev inin Termination
C9
0 .1uF
C17
0.1u F
VCCO
C7
0.1uF
VCC_38
VCCA
Zo = 50 Ohm
R9
82.5
R14
50
R15
50
Zo = 50 Ohm
Zo = 50 Ohm
+
-
R13
50
RU2
Not Insta ll
RU1
1K
VCC
RD2
1K
RD1
Not Install
VC C
C6
0.1uF
C10
0.1uF
3.3V
C14
10uF
FB1
BLM18BB221SN1
1 2
3.3V
C16
10uF
FB2
BLM18BB221SN1
1 2
C19
0.1uF
Set Logic
In put to '1'
To L ogic
Input
pins
Set Logic
In p ut to '0 '
Logic Control I np ut Ex am ples
SD ATA
SC LK
3.3V
C21
10uF
3.3V
FB3
BLM18BB221SN 1
1 2
C22
0.1uF
VCCO
VC C_19
VCC_38
Zo = 50 Ohm
R4 50
R5
50
Zo = 50 Ohm R3 50
C8
10uF
R16
10
Q 5_P
R1
4.7K
3.3V
R2
4.7K
R6
330
C15
0.1u F
R10
82.5
R8
133
R7
133
+
-
Zo = 50 Ohm
C23
9pF
C18
9pF
X1
25MHz(12pf)
U1
VEE 37
VCC
38
CLK_SEL
39
VEE 40
nc 1
nc 2
nQ0 4
Q0 3
VCCO
5
Q1 6
nQ1 7
Q2 8
nQ2 9
VEE 10
XTAL_IN
11
XTAL_OU T
12
nQ4 24
Q5 23
nQ5 22
VEE 21
FSEL1
20
VCC
19
VEE 18
ADDR_SEL
17
FSEL0
16
nC LK
15 CLK
14
VEE 13
LOCK 36
VCCA
35
VEE 34
SDATA
33
SCLK
32
VEE 31
nc 30
nc 29
Q3 28
nQ3 27
VCCO
26
Q4 25
epad 41
VCC_19
PECL Driv er
To Logic
Input
pins
FSEL1
ADDR_SEL
VCCA
CLK_SEL
FSEL0
LOCK
Q 0_N
Q 2_P
Q 2_N
Q 4_N
Q 3_P
Q 3_N
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 30 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
PCI Express Application Note
PCI Express jitter analysis methodology models the system
response to reference clock jitter. The block diagram below shows the
most frequently used Common Clock Architecture in which a copy of
the reference clock is provided to both ends of the PCI Express Link.
In the jitter analysis, the transmit (Tx) and receive (Rx) serdes PLLs
are modeled as well as the phase interpolator in the receiver. These
transfer functions are called H1, H2, and H3 respectively. The overall
system transfer function at the receiver is:
The jitter spectrum seen by the receiver is the result of applying this
system transfer function to the clock spectrum X(s) and is:
In order to generate time domain jitter numbers, an inverse Fourier
Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)].
PCI Express Common Clock Architecture
For PCI Express Gen 1, one transfer function is defined and the
evaluation is performed over the entire spectrum: DC to Nyquist (e.g
for a 100MHz reference clock: 0Hz – 50MHz) and the jitter result is
reported in peak-peak.
PCIe Gen 1 Magnitude of Transfer Function
For PCI Express Gen 2, two transfer functions are defined with 2
evaluation ranges and the final jitter number is reported in rms. The
two evaluation ranges for PCI Express Gen 2 are 10kHz – 1.5MHz
(Low Band) and 1.5MHz – Nyquist (High Band). The plots show the
individual transfer functions as well as the overall transfer function Ht.
PCIe Gen 2A Magnitude of Transfer Function
PCIe Gen 2B Magnitude of Transfer Function
For PCI Express Gen 3, one transfer function is defined and the
evaluation is performed over the entire spectrum. The transfer
function parameters are different from Gen 1 and the jitter result is
reported in RMS.
PCIe Gen 3 Magnitude of Transfer Function
For a more thorough overview of PCI Express jitter analysis
methodology, please refer to IDT Application Note PCI Express
Reference Clock Requirements.
Ht s H3 s H1 s H2 s=
Ys Xs H3 sH1 s H2 s=
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 31 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
LVPECL Power Considerations
This section provides information on power dissipation and junction temperature for the IDT8T49N006I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the IDT8T49N006I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 208mA = 720.72mW
Power (outputs)MAX = 31.55mW/Loaded Output pair
If all outputs are loaded, the total power is 6 * 31.55mW = 189.3mW
Total Power_MAX (3.465V, with all outputs switching) = 720.72W + 189.3mW = 910.02W
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = qJA * Pd_total + TA
Tj = Junction Temperature
qJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance qJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 32.4°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.910W * 32.4°C/W = 114.5°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance qJA for 40-Lead VFQFN, Forced Convection
JA by Velocity
Meters per Second 013
Multi-Layer PCB, JEDEC Standard Test Boards 32.4°C/W 25.7°C/W 23.4°C/W
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 32 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.
LVPECL output driver circuit and termination are shown in Figure 10.
Figure 10. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50W load, and a termination voltage of
VCC O – 2V.
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.75V
(VCCO_MAX – VOH_MAX) = 0.75V
For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.6V
(VCCO_MAX – VOL_MAX) = 1.6V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) =
[(2V – 0.75V)/50W] * 0.75V = 18.75mW
Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) =
[(2V – 1.6V)/50W] * 1.6V = 12.80mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 31.55mW
VOUT
VCCO
VCCO
- 2V
Q1
RL
50Ω
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 33 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
LVDS Power Considerations
This section provides information on power dissipation and junction temperature for the IDT8T49N006I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the IDT8T49N006I is the sum of the core power plus the analog power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V +5% = 3.465V, which gives worst case results.
Power (core)MAX = VCC_MAX * (ICC_MAX + ICCA_MAX) = 3.465V * (125mA + 32mA) = 544.05mW
Power (outputs)MAX = VCCO_MAX * ICCO_MAX = 3.465V * 124mA = 433.125mW
Total Power_MAX = 544.05mW + 433.125mW = 977.175mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = qJA * Pd_total + TA
Tj = Junction Temperature
qJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance qJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 32.4°C/W per Table 8 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.977W * 32.4°C/W = 116.7°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 8. Thermal Resistance qJA for 40-Lead VFQFN, Forced Convection
JA by Velocity
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 32.4°C/W 25.7°C/W 23.4°C/W
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 34 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Reliability Information
Table 9. qJA vs. Air Flow Table for a 40-Lead VFQFN
Transistor Count
The transistor count for IDT8T49N006I is: 26,856
JA vs. Air Flow
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 32.4°C/W 25.7°C/W 23.4°C/W
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 35 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
40-Lead VFQFN Package Outline and Package Dimensions
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 36 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
40-Lead VFQFN Package Outline and Package Dimensions, continued
40-Lead VFQFN, D2/E2 EPAD Dimensions: 4.65mm x 4.65mm
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 37 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Ordering Information
Table 10. Ordering Information
NOTE: For the specific -ddd order codes, refer to the document Programmable FemtoClock® NG Product Ordering Guide.
Part/Order Number Marking Package Shipping Packaging Temperature
8T49N006A-dddNLGI IDT8T49N006A-dddNLGI “Lead-Free” 40-Lead VFQFN Tray -40C to 85C
8T49N006A-dddNLGI8 IDT8T49N006A-dddNLGI “Lead-Free” 40-Lead VFQFN Tape & Reel -40C to 85C
IDT8T49N006A-dddNLGI REVISION A OCTOBER 22, 2013 38 ©2014 Integrated Device Technology, Inc.
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
Revision History Sheet
Rev Table Page Description of Change Date
AT10 37 Ordering Information Table - changed Shipping Packaging from 2500 Tape & Reel to
5000 Tape & Reel. 4/23/12
AT1 3 Pin Description Table - corrected pin numbering for pins “nc” and “Q[3:5], nQ[3:5]”. 6/28/12
AT10
11, 39
39
Changed name of the IDT8T49N00xI Programmable FemtoClock® NG Product
Ordering Information document to Programmable FemtoClock® Ordering Product
Information
Deleted quantity from Tape & Reel, Deleted Lead Free note.
8/21/2013
A
T10
1
11
39
Changed title to Programmable FemtoClock® NG LVPECL/LVDS Clock Generator
with 6-Outputs.
Changed text from ‘Programmable FemtoClock® Ordering Product Information’ to
Programmable FemtoClock® NG Product Ordering Guide’.
Changed Note from ‘Programmable FemtoClock® Ordering Product Information’ to
Programmable FemtoClock® NG Product Ordering Guide’.
9/26/13
A T5 15 Changed the min load capacitance from 12pF to 10pF 10/22/13
A Corrected orderable part number in the datasheet header. 2/18/14
IDT8T49N006I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 6-OUTPUTS
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein a t any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Pe rformance specifications and the operating parameter s of the described products are determined in the independent state and are not
guaranteed to perform the same w ay when installed in customer products. The information contained herein is provided without repr esentation or warranty of any kind, whether express or implied, including, but not limited to, the
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party owners.
Copyright 2014. All rights reserved.
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