INDUSTRIAL TEMPERATURE RANGE
IDT74LVC16373A
3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH
1 OCTOBER 2008INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
© 2006 Integrated Device Technology, Inc. DSC-4624/5
FEATURES:
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
•VCC = 3.3V ± 0.3V, Normal Range
•VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4μμ
μμ
μ W typ. static)
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in SSOP and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
IDT74LVC16373A
DESCRIPTION:
The LVC16373A 16-bit transparent D-type latch is built using advanced
dual metal CMOS technology. This high-speed, low-power latch is ideal
for temporary storage of data. The LVC16373A can be used for implement-
ing memory address latches, I/O ports, and bus drivers. The Output Enable
and Latch Enable controls are organized to operate each device as two 8-
bit latches or one 16-bit latch. Flow-through organization of signal pins
simplifies layout. All inputs are designed with hysteresis for improved noise
margin.
All pins of the LVC16373A can be driven from either 3.3V or 5V devices.
This feature allows the use of this device as a translator in a mixed 3.3V/
5V supply system.
The LVC16373A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
1OE
D
C
1LE
1D1
1Q1
TO SEVEN OTHER CHANNELS
2OE
D
C
2LE
2D1
2Q1
1
48
47
24
25
36
213
Q
Q
TO SEVEN OTHER CHANNELS
3.3V CMOS 16-BIT
TRANSPARENT D-TYPE
LATCH WITH 3-STATE OUTPUTS
AND 5 VOLT TOLERANT I/O
INDUSTRIAL TEMPERATURE RANGE
2
IDT74LVC16373A
3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH
SSOP/ TSSOP
TOP VIEW
PIN CONFIGURATION Symbol Description Max Unit
VTERM Terminal Voltage with Respect to GND –0.5 to +6.5 V
TSTG Storage Temperature –65 to +150 °C
IOUT DC Output Current –50 to +50 mA
IIK Continuous Clamp Current, –50 mA
IOK VI < 0 or VO < 0
ICC Continuous Current through each ±100 mA
ISS VCC or GND
ABSOLUTE MAXIMUM RATINGS(1)
NOTE:
1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
NOTE:
1. As applicable to the device type.
Symbol Parameter(1) Conditions Typ. Max. Unit
CIN Input Capacitance VIN = 0V 4.5 6 pF
COUT Output Capacitance VOUT = 0V 6.5 8 pF
CI/O I/O Port Capacitance VIN = 0V 6.5 8 pF
CAPACITANCE (TA = +25°C, F = 1.0MHz)
1Q2
GND
VCC
GND
GND
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
40
41
42
43
44
45
46
47
481
1Q1
1OE
1Q4
1Q3
1Q6
1Q5
1Q8
1Q7
2Q1
2Q3
2Q2
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1D2
GND
VCC
GND
GND
1D1
1LE
1D4
1D3
1D6
1D5
1D8
1D7
2D1
2D3
2D2
2D4
VCC
2D5
2D6
GND
2D7
2D8
2LE
NOTES:
1 . H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
Z = High-Impedance
2. Output level before the indicated steady-state input conditions were established.
Inputs Outputs
xDx xLE xOE xQx
HH L H
LH L L
XL LQ
(2)
XXH Z
FUNCTION TABLE(1)
Pin Names Description
xDx Data Inputs
xLE Latch Enable Input (Active HIGH)
xOE Output Enable Inputs (Active LOW)
xQx 3-State Outputs
PIN DESCRIPTION
INDUSTRIAL TEMPERATURE RANGE
IDT74LVC16373A
3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH
3
Symbol Parameter Test Conditions Min. Typ.(1) Max. Unit
VIH Input HIGH Voltage Level VCC = 2.3V to 2.7V 1.7 — — V
VCC = 2.7V to 3.6V 2 — —
VIL Input LOW Voltage Level VCC = 2.3V to 2.7V — — 0.7 V
VCC = 2.7V to 3.6V — — 0.8
IIH Input Leakage Current VCC = 3.6V VI = 0 to 5.5V — — ±5µA
IIL
IOZH High Impedance Output Current VCC = 3.6V VO = 0 to 5.5V — — ±10 µA
IOZL (3-State Output pins)
IOFF Input/Output Power Off Leakage VCC = 0V, VIN or VO ≤ 5.5V — — ±50 µA
VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V
VHInput Hysteresis VCC = 3.3V — 100 — mV
ICCL Quiescent Power Supply Current VCC = 3.6V VIN = GND or VCC —— 10µA
ICCH
ICCZ 3.6 ≤ VIN ≤ 5.5V(2) —— 10
ΔICC Quiescent Power Supply Current One input at VCC - 0.6V, other inputs at VCC or GND — — 500 µA
Variation
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = –40°C to +85°C
NOTES:
1. Typical values are at VCC = 3.3V, +25°C ambient.
2. This applies in the disabled state only.
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Test Conditions(1) Min. Max. Unit
VOH Output HIGH Voltage VCC = 2.3V to 3.6V IOH = – 0.1mA VCC – 0.2 — V
VCC = 2.3V IOH = – 6mA 2 —
VCC = 2.3V IOH = – 12mA 1 .7 —
VCC = 2.7V 2.2 —
VCC = 3V 2.4 —
VCC = 3V IOH = – 24mA 2 .2 —
VOL Output LOW Voltage VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 V
VCC = 2.3V IOL = 6mA — 0.4
IOL = 12mA — 0. 7
VCC = 2.7V IOL = 12mA — 0 .4
VCC = 3V IOL = 24mA — 0.55
INDUSTRIAL TEMPERATURE RANGE
4
IDT74LVC16373A
3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH
OPERA TING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C
Symbol Parameter Test Conditions Typical Unit
CPD Power Dissipation Capacitance per Latch Outputs enabled CL = 0pF, f = 10Mhz 39 pF
CPD Power Dissipation Capacitance per Latch Outputs disabled 6
SWITCHING CHARACTERISTICS(1)
VCC = 2.7V VCC = 3.3V ± 0.3V
Symbol Parameter Min. Max. Min. Max. Unit
tPLH Propagation Delay — 4.9 1.6 4.2 ns
tPHL xDx to xQx
tPLH Propagation Delay — 5.3 2.1 4.6 ns
tPHL xLE to xQx
tPZH Output Enable Time — 5.7 1.3 4.7 ns
tPZL xOE to xQx
tPHZ Output Disable Time — 6.3 2.5 5.9 ns
tPLZ xOE to xQx
tSU Set-up Time, data before LE↓ HIGH or LOW 1. 7 — 1 .7 — n s
tHHold Time, data after LE↓ HIGH or LOW 1 . 2 — 1 . 2 — n s
tWPulse Width LE HIGH 3.3 — 3.3 — ns
tSK(o) Output Skew(2) ———500 ps
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
INDUSTRIAL TEMPERATURE RANGE
IDT74LVC16373A
3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH
5
Open
VLOAD
GND
VCC
Pulse
Generator D.U.T.
500Ω
500Ω
CL
RT
VIN VOUT
(1, 2)
LVC Link
INPUT
VIH
0V
VOH
VOL
tPLH1
tSK (x)
OUTPUT 1
OUTPUT 2
tPHL1
tSK (x)
tPLH2 tPHL2
VT
VT
VOH
VT
VOL
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
LVC Link
SAME PHASE
INPUT TRANSITION
OPPOSITE PHASE
INPUT TRANSITION
0V
0V
VOH
VOL
tPLH tPHL
tPHL
tPLH
OUTPUT
VIH
VT
VT
VIH
VT
LVC Link
DATA
INPUT 0V
0V
0V
0V
tREM
TIMING
INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
tSU tH
tSU tH
VIH
VT
VIH
VT
VIH
VT
VIH
VT
LVC Link
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
VT
tW
VT
LVC Link
CONTROL
INPUT
tPLZ 0V
OUTPUT
NORMALLY
LOW tPZH
0V
SWITCH
CLOSED
OUTPUT
NORMALLY
HIGH
ENABLE DISABLE
SWITCH
OPEN
tPHZ
0V
VOL+VLZ
VOH
VT
VT
tPZL
VLOAD/2 VLOAD/2
VIH
VT
VOL
VOH-VHZ
LVC Link
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuit for All Outputs
Enable and Disable Times
Set-up, Hold, and Release Times
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
Output Skew - tSK(X)
Pulse Width
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Symbol VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit
VLOAD 6 6 2 x Vcc V
VIH 2.7 2.7 Vcc V
VT1.5 1.5 Vcc / 2 V
VLZ 300 300 150 mV
VHZ 300 300 150 mV
CL50 50 30 pF
TEST CONDITIONS
SWITCH POSITION
Test Switch
Open Drain
Disable Low VLOAD
Enable Low
Disable High GND
Enable High
All Other Tests Open
INDUSTRIAL TEMPERATURE RANGE
6
IDT74LVC16373A
3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH
ORDERING INFORMATION
XX LVC XXXX XX
Package
Device Type
Temp. Range
PV
PVG
PA
PAG
16
74
Shrink Small Outline Package
SSOP - Green
Thin Shrink Small Outline Package
TSSOP - Green
16-Bit Transparent D-Type Latch with 3-State Outputs
-40°C to +85°C
XXX
FamilyBus-Hold
373A
No Bus-hold
Double-Density, ±24mA
Blank
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 logichelp@idt.com
San Jose, CA 95138 fax: 408-284-2775
www.idt.com
