MOTOROLA SEMICONDUCTOR TECHNICAL DATA Product Preview MC100EP223 Low-Voltage 1:22 Differential PECL/HSTL Clock Driver The MC100EP223 is a low skew 1-to-22 differential driver, designed with clock distribution in mind. It accepts two clock sources into an input multiplexer. The selected signal is fanned out to 22 identical differential outputs. * 200ps Part-to-Part Skew * 50ps Output-to-Output Skew LOW-VOLTAGE 1:22 DIFFERENTIAL PECL/HSTL CLOCK DRIVER * Differential Design * Open Emitter HSTL Compatible Outputs * 3.3V VCC * Both PECL and HSTL Inputs * 75k Input Pulldown Resistors * Thermally Enhanced 64 lead Exposed Pad LQFP The EP223 is specifically designed, modeled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate-to-gate skew within a device, and empirical modeling is used to determine process control limits that ensure consistent tpd distributions from lot to lot. The net result is a dependable, guaranteed low skew device. TC SUFFIX 64-LEAD LQFP PACKAGE CASE 840K-01 The EP223 HSTL outputs are not realized in the conventional manner. To minimize part-to-part and output-to-output skew, the HSTL compatible output levels are generated with an open emitter architecture. The outputs are pulled down with 50 to ground, rather than the typical 50 to VDDQ pullup of a "standard" HSTL output. Because the HSTL outputs are pulled to ground, the EP223 does not utilize the VDDQ supply of the HSTL standard. The output levels are derived from VCC. In the case of an asynchronous control, there is a chance of generating a `runt' clock pulse when the device is enabled/disabled. To avoid this, the output enable (OE) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. To ensure that the tight skew specification is met it is necessary that both sides of the differential output are terminated into 50, even if only one side is being used. In most applications, all 22 differential pairs will be used and therefore terminated. In the case where fewer than 22 pairs are used, it is necessary to terminate at least the output pairs on the same package side as the pair(s) being used on that side, in order to maintain minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10-20ps) of the output(s) being used which, while not being catastrophic to most designs, will mean a loss of skew margin. This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. 03/01 Motorola, Inc. 2001 1 REV 2 VCCO Q7 Q7B Q8 Q8B Q9 Q9B Q10 Q10B Q11 Q11B Q12 Q12B Q13 Q13B VCCO MC100EP223 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VCCO 49 32 VCCO Q6B 50 31 Q14 Q6 51 30 Q14B Q5B 52 29 Q15 Q5 53 28 Q15B Q4B 54 27 Q16 Q4 55 26 Q16B Q3B 56 25 Q17 MC100EP223 Q1 61 20 Q19B Q0B 62 19 Q20 Q0 63 18 Q20B VCCO 64 17 VCCO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VCCO Q19 Q21 21 Q21B 60 NC Q1B NC Q18B OE 22 GND 59 PECL_CLKB Q2 PECL_CLK Q18 CLK_SEL 23 HSTL_CLKB 58 HSTL_CLK Q2B VCCI Q17B NC 24 NC 57 VCCO Q3 Figure 1. 64-Lead Pinout (Top View) CLK_SEL PIN NAMES HSTL_CLK HSTL_CLK Function Pins HSTL_CLK, HSTL_CLKB PECL_CLK, PECL_CLKB Q0:21, Q0B:21B CLK_SEL OE GND VCCI VCCO Differential HSTL Inputs Differential PECL Inputs Differential HSTL Outputs Active Clock Select Input Output Enable Ground Core VCC I/O VCC 22 Q0 - Q21 Q0 - Q21 LVPECL_CLK LVPECL_CLK 1 22 LEN Q OE D Figure 2. Logic Symbol FUNCTION SIGNAL GROUPS OE CLK_SEL 0 0 1 1 0 1 0 1 MOTOROLA 0 Q0:21, Q0B:21B Q = Low, QB = High Q = Low, QB = High HSTL_CLK, HSTL_CLKB PECL_CLK, PECL_CLKB 2 Level Direction Signal HSTL HSTL LVPECL LVCMOS/LVTTL Input Output Input Input HSTL_CLK, HSTL_CLKB Q0:21, Q0B:21B PECL_CLK, PECL_CLKB CLK_SEL, OE TIMING SOLUTIONS DL207 -- Rev 0 MC100EP223 HSTL DC CHARACTERISTICS 0C Symbol Characteristic Min Typ 25C Max Min VOH Output HIGH Voltage VOL Output LOW Voltage VIH Input HIGH Voltage VX+0.1 VIL Input LOW Voltage -0.3 VX Input Crossover Voltage 0.68 Typ 85C Max Min Typ Max Unit 1.0 V 0.4 V 1.6 V VX-0.1 V 0.9 V PECL DC CHARACTERISTICS 0C Symbol Characteristic Min Typ 25C Max Min Typ 85C Max Min Typ Max Unit VIH Input HIGH Voltage (Note 1.) 2.135 2.420 2.135 2.420 2.135 2.420 V VIL Input LOW Voltage (Note 1.) 1.490 1.825 1.490 1.825 1.490 1.825 V 150 A Max Unit IIH Input HIGH Current 150 1. These values are for VCC = 3.3V. Level specifications vary 1:1 with VCC. 150 AC CHARACTERISTICS (VEE = GND, VCC =VCC(min) to VCC(max)) 0C Symbol Characteristic Min Typ 25C Max Min Typ 85C Max Min Typ tPLH, tPHL Propagation Delay to Output IN (Differential) ns tskew Within-Device Skew Part-to-Part Skew (Diff) 50 200 50 200 50 200 ps fmax Maximum Input Frequency 250 250 250 MHz VPP Minimum Input Swing PECL_CLK VCMR Common Mode Range PECL_CLK tr, tf Output Rise/Fall Time (20-80%) 1.0 1.0 600 1.0 600 600 mV V 300 600 300 600 300 600 ps Power Supply Characteristics Symbol Characteristic Min Typ Max Unit VCCI Core VCC 3.0 3.3 3.6 V VCCO I/O VCC 1.6 1.8 2.0 V ICC Power Supply Current mA IEE Power Supply Current mA TIMING SOLUTIONS DL207 -- Rev 0 3 MOTOROLA MC100EP223 APPLICATIONS INFORMATION Using the thermally enhanced package of the MC100EP223 The MC100EP223 uses a thermally enhanced 64 lead LQFP package. This package provides the low thermal impedance that supports the power consumption of the MC100EP223 high-speed bipolar integrated circuit and eases the power management task for the system design. An exposed pad at the bottom of the package establishes thermal conductivity from the package to the printed circuit board. In order to take advantage of the enhanced thermal capabilitites of this package, it is recommended to solder the exposed pad of the package to the printed circuit board. The attachment process for exposed pad package is the same as for any standard surface mount package. Vias are recommended from the pad on the board down to an appropriate plane in the board that is capable of distributing the heat. In order to supply enough solder paste to fill those vias and not starve the solder joints, it may be required to stencil print solder paste onto the printed circuit pad. This pad should match the dimensions of the exposed pad. The dimensions of the exposed pad are shown on the package outline in this specification. For thermal system analysis and junction temperature calculation the thermal resistance parameters of the package is provided: MOTOROLA Thermal Resistance Convection LFPM RTHJAa C/W RTHJAb C/W Natural 57.1 24.9 100 50.0 21.3 200 46.9 20.0 400 43.4 18.7 800 38.6 16.9 a. b. c. d. RTHJCc C/W RTHJBd C/W 15.8 9.7 Junction to ambient, single layer test board, per JESD51-6 Junction to ambient, four conductor layer test board (2S2P), per JES51-6 Junction to case, per MIL-SPEC 883E, method 1012.1 Junction to board, four conductor layer test board (2S2P) per JESD 51-8 It is recommended that users employ thermal modeling analysis to assist in applying the general recommendations to their particular application. The exposed pad of the MC100EP223 package does not have an electrical low impedance path to the substrate of the integrated circuit and its terminals. 4 TIMING SOLUTIONS DL207 -- Rev 0 MC100EP223 OUTLINE DIMENSIONS TC SUFFIX PLASTIC LQFP PACKAGE, EXPOSED PAD CASE 840K-01 ISSUE O 4X 4X 16 TIPS 0.2 H A-B D A2 0.2 C A-B D 0.05 S D PIN 1 IDENTIFIER (S) 64 49 1 Z1 48 0.25 Z A 3X 16 E/2 32 D1/2 D/2 D1 D 4X A Z2 0.08 C C 64X SEATING PLANE 0.08 M b 4X J Z3 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 mm AND 0.25 mm FROM THE LEAD TIP. VIEW AA C A-B D X X=A, B OR D CL AB e/2 AB BASE METAL 60X e F VIEW Y 8 b1 8 c CCCC EEEE EEEE CCCC EEEE CCCC c1 8 G 8 b PLATING SECTION AB-AB DIM A A1 A2 b b1 c c1 D D1 e E E1 L L1 R1 R2 S F G Z Z1 Z2 Z3 MILLIMETERS MIN MAX --- 1.60 0.05 0.15 1.35 1.45 0.17 0.27 0.17 0.23 0.09 0.20 0.09 0.16 12.00 BSC 10.00 BSC 0.50 BSC 12.00 BSC 10.00 BSC 0.45 0.75 1.00 REF 0.08 --- 0.08 --- 0.20 --- 6.00 7.00 6.00 7.00 0_ 7_ 0_ --- 11 _ 13 _ 11 _ 13 _ EXPOSED PAD ROTATED 90 _ CLOCKWISE TIMING SOLUTIONS DL207 -- Rev 0 L (L1) NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M-1994. 3. DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE H. 4. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE C. 5. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08 mm. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 mm. 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 mm PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 33 17 R1 A1 E VIEW AA E1/2 VIEW Y J GAGE PLANE B E1 H R VIEW J-J 5 MOTOROLA MC100EP223 NOTES MOTOROLA 6 TIMING SOLUTIONS DL207 -- Rev 0 MC100EP223 NOTES TIMING SOLUTIONS DL207 -- Rev 0 7 MOTOROLA MC100EP223 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. 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Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA / PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2, Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852-26668334 HOME PAGE: http://www.motorola.com/semiconductors/ MOTOROLA 8 TIMING SOLUTIONS MC100EP223/D DL207 -- Rev 0