MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
1REV 2
Motorola, Inc. 2001
03/01
Product Preview
Low-Voltage 1:22 Differential
PECL/HSTL Clock Driver
The MC100EP223 is a low skew 1–to–22 differential driver, designed
with clock distribution in mind. It accepts two clock sources into an input
multiplexer. The selected signal is fanned out to 22 identical differential
outputs.
•200ps Part–to–Part Skew
•50ps Output–to–Output Skew
•Differential Design
•Open Emitter HSTL Compatible Outputs
•3.3V VCC
•Both PECL and HSTL Inputs
•75kΩ Input Pulldown Resistors
•Thermally Enhanced 64 lead Exposed Pad LQFP
The EP223 is specifically designed, modeled and produced with low
skew as the key goal. Optimal design and layout serve to minimize
gate–to–gate skew within a device, and empirical modeling is used to
determine process control limits that ensure consistent tpd distributions
from lot to lot. The net result is a dependable, guaranteed low skew
device.
The EP223 HSTL outputs are not realized in the conventional
manner. To minimize part–to–part and output–to–output skew, the HSTL
compatible output levels are generated with an open emitter
architecture. The outputs are pulled down with 50Ω to ground, rather
than the typical 50Ω to VDDQ pullup of a “standard” HSTL output.
Because the HSTL outputs are pulled to ground, the EP223 does not
utilize the VDDQ supply of the HSTL standard. The output levels are
derived from VCC.
In the case of an asynchronous control, there is a chance of
generating a ‘runt’ clock pulse when the device is enabled/disabled. To
avoid this, the output enable (OE) is synchronous so that the outputs
will only be enabled/disabled when they are already in the LOW state.
To ensure that the tight skew specification is met it is necessary that both sides of the differential output are terminated into
50Ω, even if only one side is being used. In most applications, all 22 differential pairs will be used and therefore terminated. In
the case where fewer than 22 pairs are used, it is necessary to terminate at least the output pairs on the same package side as
the pair(s) being used on that side, in order to maintain minimum skew. Failure to do this will result in small degradations of
propagation delay (on the order of 10–20ps) of the output(s) being used which, while not being catastrophic to most designs, will
mean a loss of skew margin.
This document contains information on a product under development. Motorola reserves the right to change or
discontinue this product without notice.
MC100EP223
LOW–VOLTAGE
1:22 DIFFERENTIAL
PECL/HSTL CLOCK DRIVER
TC SUFFIX
64–LEAD LQFP PACKAGE
CASE 840K–01
MC100EP223
MOTOROLA TIMING SOLUTIONS
DL207 — Rev 0
2
Figure 1. 64–Lead Pinout (Top View)
Q = Low, QB = High
Q = Low, QB = High
HSTL_CLK, HSTL_CLKB
PECL_CLK, PECL_CLKB
PIN NAMES
Function
Differential HSTL Inputs
Differential PECL Inputs
Differential HSTL Outputs
Active Clock Select Input
Output Enable
Ground
Core VCC
I/O VCC
Pins
HSTL_CLK, HSTL_CLKB
PECL_CLK, PECL_CLKB
Q0:21, Q0B:21B
CLK_SEL
OE
GND
VCCI
VCCO
FUNCTION
Q0:21, Q0B:21BOE
0
0
1
1
Figure 2. Logic Symbol
0
1
LVPECL_CLK
LVPECL_CLK
HSTL_CLK
HSTL_CLK
CLK_SEL
Q0 – Q21
Q0 – Q21
22
VCCO
Q6B
Q6
Q5B
Q5
Q4B
Q4
Q3B
Q3
Q2B
Q2
Q1B
Q1
Q0B
Q0
VCCO
VCCO
Q14
Q14B
Q15
Q15B
Q16
Q16B
Q17
Q17B
Q18
Q18B
Q19
Q19B
Q20
Q20B
VCCO
VCCO
Q7
Q7B
Q8
Q8B
Q9
Q9B
Q10
Q10B
Q11
Q11B
Q12
Q12B
Q13
Q13B
VCCO
VCCO
NC
NC
VCCI
HSTL_CLK
HSTL_CLKB
CLK_SEL
PECL_CLK
PECL_CLKB
GND
OE
NC
NC
Q21B
Q21
VCCO
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
12345678910111213141516
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
MC100EP223
CLK_SEL
0
1
0
1
OE
HSTL_CLK, HSTL_CLKB
Q0:21, Q0B:21B
PECL_CLK, PECL_CLKB
CLK_SEL, OE
SIGNAL GROUPS
SignalLevel
HSTL
HSTL
LVPECL
LVCMOS/LVTTL
Direction
Input
Output
Input
Input
22
LEN
DQ
MC100EP223
TIMING SOLUTIONS
DL207 — Rev 0 3 MOTOROLA
HSTL DC CHARACTERISTICS
0°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
VOH Output HIGH Voltage 1.0 V
VOL Output LOW Voltage 0.4 V
VIH Input HIGH Voltage V
X
+0.1 1.6 V
VIL Input LOW Voltage –0.3 V
X
–0.1 V
V
X
Input Crossover Voltage 0.68 0.9 V
PECL DC CHARACTERISTICS
0°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
VIH Input HIGH Voltage (Note 1.) 2.135 2.420 2.135 2.420 2.135 2.420 V
VIL Input LOW Voltage (Note 1.) 1.490 1.825 1.490 1.825 1.490 1.825 V
IIH Input HIGH Current 150 150 150 µA
1. These values are for VCC = 3.3V. Level specifications vary 1:1 with VCC.
AC CHARACTERISTICS (VEE = GND, VCC =VCC(min) to VCC(max))
0°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
tPLH,
tPHL Propagation Delay to Output
IN (Differential) 1.0 1.0 1.0 ns
tskew Within–Device Skew
Part–to–Part Skew (Diff) 50
200 50
200 50
200 ps
fmax Maximum Input Frequency 250 250 250 MHz
VPP Minimum Input Swing PECL_CLK 600 600 600 mV
VCMR Common Mode Range PECL_CLK V
tr, tfOutput Rise/Fall Time (20–80%) 300 600 300 600 300 600 ps
Power Supply Characteristics
Symbol Characteristic Min Typ Max Unit
VCCI Core VCC 3.0 3.3 3.6 V
VCCO I/O VCC 1.6 1.8 2.0 V
ICC Power Supply Current mA
IEE Power Supply Current mA
MC100EP223
MOTOROLA TIMING SOLUTIONS
DL207 — Rev 0
4
APPLICATIONS INFORMATION
Using the thermally enhanced package of the
MC100EP223
The MC100EP223 uses a thermally enhanced 64 lead
LQFP package. This package provides the low thermal
impedance that supports the power consumption of the
MC100EP223 high-speed bipolar integrated circuit and
eases the power management task for the system design. An
exposed pad at the bottom of the package establishes
thermal conductivity from the package to the printed circuit
board. In order to take advantage of the enhanced thermal
capabilitites of this package, it is recommended to solder the
exposed pad of the package to the printed circuit board. The
attachment process for exposed pad package is the same as
for any standard surface mount package. Vias are
recommended from the pad on the board down to an
appropriate plane in the board that is capable of distributing
the heat. In order to supply enough solder paste to fill those
vias and not starve the solder joints, it may be required to
stencil print solder paste onto the printed circuit pad. This pad
should match the dimensions of the exposed pad. The
dimensions of the exposed pad are shown on the package
outline in this specification. For thermal system analysis and
junction temperature calculation the thermal resistance
parameters of the package is provided:
Thermal Resistance
Convection
LFPM RTHJAa
°C/W RTHJAb
°C/W RTHJCc
°C/W RTHJBd
°C/W
Natural 57.1 24.9
100 50.0 21.3
200 46.9 20.0 15.8 9.7
400 43.4 18.7
800 38.6 16.9
a. Junction to ambient, single layer test board, per JESD51-6
b. Junction to ambient, four conductor layer test board (2S2P),
per JES51-6
c. Junction to case, per MIL-SPEC 883E, method 1012.1
d. Junction to board, four conductor layer test board (2S2P) per
JESD 51-8
It is recommended that users employ thermal modeling
analysis to assist in applying the general recommendations
to their particular application. The exposed pad of the
MC100EP223 package does not have an electrical low
impedance path to the substrate of the integrated circuit and
its terminals.
MC100EP223
TIMING SOLUTIONS
DL207 — Rev 0 5 MOTOROLA
OUTLINE DIMENSIONS
TC SUFFIX
PLASTIC LQFP PACKAGE, EXPOSED PAD
CASE 840K–01
ISSUE O
AB
AB
e/2
e60X
X=A, B OR D
C
L
VIEW Y
S
0.05
Z1
Z2
0.25
GAGE PLANE
SEATING
PLANE
A2
(S)
R
(L1)
L
A1
VIEW AA
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
b1
SECTION AB–AB
b
c1
c
PLATING
BASE METAL
ROTATED 90 CLOCKWISE
_
64
0.2 H A–B D
1
49
48
17
16
32
33
B
E/2
E
E1
D1
D/2
D
D1/2
3X
VIEW Y
A4X
VIEW AA
0.08 C
Z34X
4X 4X 16 TIPS
0.2 CA–B D
E1/2
A
D
C
H
XDIM MIN MAX
MILLIMETERS
A––– 1.60
A1 0.05 0.15
A2 1.35 1.45
b0.17 0.27
b1 0.17 0.23
c0.09 0.20
c1 0.09 0.16
D12.00 BSC
D1 10.00 BSC
e0.50 BSC
E12.00 BSC
E1 10.00 BSC
L0.45 0.75
L1 1.00 REF
S
F6.00 7.00
G0 7
0 –––
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER
ASME Y14.5M–1994.
3. DATUMS A, B AND D TO BE DETERMINED AT DATUM
PLANE H.
4. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE C.
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED
THE MAXIMUM b DIMENSION BY MORE THAN 0.08 mm.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN
PROTRUSION AND ADJACENT LEAD OR
PROTRUSION 0.07 mm.
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 mm
PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY
SIZE DIMENSIONS INCLUDING MOLD MISMATCH.
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT SECTION
OF THE LEAD BETWEEN 0.10 mm AND 0.25 mm FROM
THE LEAD TIP.
Z1
Z2
Z3
_
__
Z
0.20 –––
6.00 7.00
R1
R2 0.08 –––
0.08 –––
11 13
__
11 13
__
A–B
M
0.08 DC
64X bJJ
PIN 1
IDENTIFIER
Z
R1
8
8
8
8
G
F
VIEW J–J EXPOSED PAD
MC100EP223
MOTOROLA TIMING SOLUTIONS
DL207 — Rev 0
6
NOTES
MC100EP223
TIMING SOLUTIONS
DL207 — Rev 0 7 MOTOROLA
NOTES
MC100EP223
MOTOROLA TIMING SOLUTIONS
DL207 — Rev 0
8
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and actual performance may vary over time. All operating parameters, including “T ypicals” must be validated for each customer application
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MC100EP223/D
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