LM25069
LM25069 Positive Low Voltage Power Limiting Hot Swap Controller
Literature Number: SNVS607D
LM25069
December 9, 2010
Positive Low Voltage Power Limiting Hot Swap Controller
General Description
The LM25069 positive hot swap controller provides intelligent
control of the power supply voltage to the load during insertion
and removal of circuit cards from a live system backplane or
other "hot" power sources. The LM25069 provides in-rush
current control to limit system voltage droop and transients.
The current limit and power dissipation in the external series
pass N-Channel MOSFET are programmable, ensuring op-
eration within the Safe Operating Area (SOA). The POWER
GOOD output indicates when the output voltage is within 1.3V
of the input voltage. The input under-voltage and over-voltage
lockout levels and hysteresis are programmable, as well as
the initial insertion delay time and fault detection time. The
LM25069-1 latches off after a fault detection, while the
LM25069-2 automatically restarts at a fixed duty cycle. The
LM25069 is available in a 10 pin MSOP package.
Features
■Operating range: +2.9V to +17V
■In-rush current limit for safe board insertion into live power
sources
■Programmable maximum power dissipation in the external
pass device
■Adjustable current limit
■Circuit breaker function for severe over-current events
■Internal high side charge pump and gate driver for external
N-channel MOSFET
■Adjustable under-voltage lockout (UVLO) and hysteresis
■Adjustable over-voltage lockout (OVLO) and hysteresis
■Initial insertion timer allows ringing and transients to
subside after system connection
■Programmable fault timer avoids nuisance trips
■Active high open drain POWER GOOD output
■Available in latched fault and automatic restart versions
Applications
■Server Backplane Systems
■Base Station Power Distribution Systems
■Solid State Circuit Breaker
Package
■MSOP-10
Typical Application
30086701
Positive Power Supply Control
© 2010 National Semiconductor Corporation 300867 www.national.com
LM25069 Positive Low Voltage Power Limiting Hot Swap Controller
Connection Diagram
30086702
Top View
10-Lead MSOP
Ordering Information
Order Number Fault Response Package Type NSC Package
Drawing Supplied As
LM25069PMME-1 Latch Off
MSOP-10 MUB10A
250 Units on Tape and Reel
LM25069PMM-1 Latch Off 1000 Units on Tape and Reel
LM25069PMMX-1 Latch Off 3500 Units on Tape and Reel
LM25069PMME-2 Auto Restart 250 Units on Tape and Reel
LM25069PMM-2 Auto Restart 1000 Units on Tape and Reel
LM25069PMMX-2 Auto Restart 3500 Units on Tape and Reel
Pin Descriptions
Pin # Name Description Applications Information
1 SENSE Current sense input The voltage across the current sense resistor (RS) is measured from VIN to this
pin. If the voltage across RS reaches 50mV the load current is limited and the fault
timer activates.
2 VIN Positive supply input A small ceramic bypass capacitor close to this pin is recommended to suppress
transients which occur when the load current is switched off.
3 UVLO/EN Under-voltage lockout An external resistor divider from the system input voltage sets the under-voltage
turn-on threshold. An internal 20 µA current source provides hysteresis. The
enable threshold at the pin is 1.17V. This pin can also be used for remote
shutdown control.
4 OVLO Over-voltage lockout An external resistor divider from the system input voltage sets the over-voltage
turn-off threshold. An internal 20 µA current source provides hysteresis. The
disable threshold at the pin is 1.16V.
5 GND Circuit ground
6 TIMER Timing capacitor An external capacitor connected to this pin sets the insertion time delay and the
Fault Timeout Period. The capacitor also sets the restart timing of the LM25069-2.
7 PWR Power limit set An external resistor connected to this pin, in conjunction with the current sense
resistor (RS), sets the maximum power dissipation allowed in the external series
pass MOSFET.
8 PGD Power Good indicator An open drain output. When the external MOSFET VDS decreases below 1.3V,
the PGD indicator is active (high). When the external MOSFET VDS increases
above 1.9V the PGD indicator switches low.
9 OUT Output feedback Connect to the output rail (external MOSFET source). Internally used to determine
the MOSFET VDS voltage for power limiting, and to control the PGD indicator.
10 GATE Gate drive output Connect to the external MOSFET’s gate. This pin's voltage is limited at 19.5V
above ground.
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LM25069
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
VIN to GND (Note 5) -0.3V to 20V
SENSE, OUT, PGD to GND -0.3V to 20V
UVLO to GND -0.3V to 20V
OVLO to GND -0.3V to 20V
VIN to SENSE -0.3V to +0.3V
ESD Rating (Note 2)
Human Body Model
2kV
Storage Temperature -65°C to +150°C
Junction Temperature +150°C
Lead Temperature (soldering 4 sec) +260°C
Operating Ratings
VIN Supply Voltage +2.9V to 17V
PGD Off Voltage 0V to 17V
Junction Temp. Range −40°C to +85°C
Electrical Characteristics Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the
junction temperature (TJ) range of -40°C to +85°C. Minimum and Maximum limits are guaranteed through test, design, or statistical
correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
Unless otherwise stated the following conditions apply: VIN = 12V.
Symbol Parameter Conditions Min. Typ. Max. Units
Input (VIN pin)
IIN-EN Input Current, enabled UVLO = 2V and OVLO = 0.7V, VIN = 14V 1.6 2.4 mA
IIN-DIS Input Current, disabled UVLO = 0.7V or OVLO = 2V 1.0 1.6 mA
POR Power On Reset threshold at VIN VIN Increasing 2.6 2.8 V
PORHYS POR hysteresis VIN decreasing 150 mV
OUT pin
IOUT-EN OUT bias current, enabled OUT = VIN, Normal operation 0.30 µA
IOUT-DIS OUT bias current, disabled (Note 3) Disabled, OUT = 0V, SENSE = VIN -12
UVLO, OVLO pins
UVLOTH UVLO threshold 1.154 1.17 1.183 V
UVLOHYS UVLO hysteresis current UVLO = 1V 15 20 26 µA
UVLODEL UVLO delay Delay to GATE high 15 µs
Delay to GATE low 8.3
UVLOBIAS UVLO bias current UVLO = 3V 1µA
OVLOTH OVLO threshold 1.142 1.16 1.185 V
OVLOHYS OVLO hysteresis current OVLO = 2V -26 -20 -15 µA
OVLODEL OVLO delay Delay to GATE high 16 µs
Delay to GATE low 8.2
OVLOBIAS OVLO bias current OVLO = 1V 1µA
Power Limit (PWR pin)
PWRLIM-1 Power limit sense voltage (VIN-SENSE) SENSE-OUT = 12V, RPWR = 69.8 kΩ19 25 31 mV
PWRLIM-2 SENSE-OUT = 6V, RPWR = 34.8 kΩ19 25 31 mV
IPWR PWR pin current VPWR = 2.5V -15 µA
RSAT(PWR) PWR pin impedance when disabled UVLO = 0.7V 140 Ω
Gate Control (GATE pin)
IGATE Source current Normal Operation -27 -20 -13 µA
Sink current UVLO = 1V 1.5 22.7 mA
VIN - SENSE = 150 mV or VIN < POR,
VGATE = 5V
160 260 375 mA
VGATE Gate output voltage in normal operation GATE voltage with respect to ground 18 19.5 21 V
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LM25069
Symbol Parameter Conditions Min. Typ. Max. Units
Current Limit
VCL Threshold voltage VIN-SENSE voltage 45 50 55 mV
tCL Response time VIN-SENSE stepped from 0 mV to 80
mV
15 µs
ISENSE SENSE input current Enabled, SENSE = OUT 23 µA
Disabled, OUT = 0V 12
Enabled, OUT = 0V 62
Circuit Breaker
VCB Threshold voltage VIN - SENSE 75 95 110 mV
tCB Response time VIN - SENSE stepped from 0 mV to 150
mV, time to GATE low, no load
0.19 0.36 µs
Timer (TIMER pin)
VTMRH Upper threshold 1.6 1.72 1.85 V
VTMRL Lower threshold Restart cycles (LM25069-2) 0.9 1.0 1.1 V
End of 8th cycle (LM25069-2) 0.3 V
Re-enable Threshold (LM25069-1) 0.3 V
ITIMER Insertion time current -7.5 -5.5 -3.5 µA
Sink current, end of insertion time TIMER pin = 2V 1.5 22.5 mA
Fault detection current -110 -80 -50 µA
Fault sink current 1.6 2.5 3.4 µA
DCFAULT Fault Restart Duty Cycle LM25069-2 only 0.67 %
tFAULT Fault to GATE low delay TIMER pin reaches the upper threshold 20 µs
Power Good (PGD pin)
PGDTH Threshold measured at SENSE-OUT Decreasing 1.3 1.9 V
Threshold Hysteresis 0.6
PGDVOL Output low voltage ISINK = 2 mA 15 30 mV
PGDIOH Off leakage current VPGD = 17V 1µA
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and conditions see the Electrical Characteristics.
Note 2: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.
Note 3: OUT bias current (disabled) due to leakage current through an internal 1.0 MΩ resistance from SENSE to VOUT.
Note 4: For detailed information on soldering plastic MSOP packages refer to the Packaging Databook available from National Semiconductor Corporation.
Note 5: Current out of a pin is indicated as a negative number.
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LM25069
Typical Performance Characteristics Unless otherwise specified the following conditions apply: TJ =
25°C, VIN = 12V
VIN Pin Input Current vs. VIN
30086703
SENSE Pin Input Current
30086704
OUT Pin Input Current
30086705
GATE Pin Voltage
30086706
GATE Pin Source Current
30086707
MOSFET Power Dissipation Limit
30086709
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LM25069
PGD Pin Low Voltage vs. Sink Current
30086708
Input Current, Enabled vs. Temperature
30086758
UVLO Threshold vs. Temperature
30086757
UVLO Hysteresis Current vs. Temperature
30086755
OVLO Threshold vs. Temperature
30086766
OVLO Hysteresis Current vs. Temperature
30086756
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LM25069
Current Limit Threshold vs. Temperature
30086759
Circuit Breaker Threshold vs. Temperature
30086760
Power Limit Threshold vs. Temperature
30086761
GATE Output Voltage vs. Temperature
30086762
GATE Source Current vs. Temperature
30086763
PGD Low Voltage vs. Temperature
30086765
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LM25069
Block Diagram
30086710
30086711
FIGURE 1. Basic Application Circuit
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LM25069
Functional Description
The LM25069 is designed to control the in-rush current to the
load upon insertion of a circuit card into a live backplane or
other "hot" power source, thereby limiting the voltage sag on
the backplane’s supply voltage, and the dV/dt of the voltage
applied to the load. Effects on other circuits in the system are
minimized, preventing possible unintended resets. A con-
trolled shutdown when the circuit card is removed can also be
implemented using the LM25069. In addition to a pro-
grammable current limit, the LM25069 monitors and limits the
maximum power dissipation in the series pass device to main-
tain operation within the device Safe Operating Area (SOA).
Either current limiting or power limiting for an extended period
of time results in the shutdown of the series pass device. In
this event, the LM25069-1 latches off until the circuit is re-
enabled by external control, while the LM25069-2 automati-
cally restarts with defined timing. The circuit breaker function
quickly switches off the series pass device upon detection of
a severe over-current condition. The Power Good (PGD) out-
put pin indicates when the output voltage is within 1.3V of the
system input voltage (VSYS). Programmable under-voltage
lock-out (UVLO) and over-voltage lock-out (OVLO) circuits
enable the LM25069 when the system input voltage is be-
tween the desired thresholds. The typical configuration of a
circuit card with LM25069 hot swap protection is shown in
Figure 2.
30086712
FIGURE 2. LM25069 Application
Power Up Sequence
The VIN operating range of the LM25069 is +2.9V to +17V,
with a transient capability to 20V. Referring to the Block Dia-
gram and Figure 1 and Figure 3, as the voltage at VIN initially
increases, the external N-channel MOSFET (Q1) is held off
by an internal 260 mA pull-down current at the GATE pin. The
strong pull-down current at the GATE pin prevents an inad-
vertent turn-on as the MOSFET’s gate-to-drain (Miller) ca-
pacitance is charged. Additionally, the TIMER pin is initially
held at ground. When the VIN voltage reaches the POR
threshold the insertion time begins. During the insertion time,
the capacitor at the TIMER pin (CT) is charged by a 5.5 µA
current source, and Q1 is held off by a 2 mA pull-down current
at the GATE pin regardless of the VIN voltage. The insertion
time delay allows ringing and transients at VIN to settle before
Q1 is enabled. The insertion time ends when the TIMER pin
voltage reaches 1.72V. CT is then quickly discharged by an
internal 2 mA pull-down current. The GATE pin then switches
on Q1 when VSYS exceeds the UVLO threshold. If VSYS is
above the UVLO threshold at the end of the insertion time, Q1
switches on at that time. The GATE pin charge pump sources
20 µA to charge Q1’s gate capacitance. The maximum volt-
age at the GATE pin is limited by an internal 19.5V zener
diode.
As the voltage at the OUT pin increases, the LM25069 mon-
itors the drain current and power dissipation of MOSFET Q1.
In-rush current limiting and/or power limiting circuits actively
control the current delivered to the load. During the in-rush
limiting interval (t2 in Figure 3) an internal 80 µA fault timer
current source charges CT. If Q1’s power dissipation and the
input current reduce below their respective limiting thresholds
before the TIMER pin reaches 1.72V the 80 µA current source
is switched off, and CT is discharged by the internal 2.5 µA
current sink (t3 in Figure 3). The in-rush limiting interval is
complete when the voltage at the OUT pin increases to within
1.3V of the input voltage (VSYS), and the PGD pin switches
high.
If the TIMER pin voltage reaches 1.72V before in-rush current
limiting or power limiting ceases (during t2), a fault is declared
and Q1 is turned off. See the Fault Timer & Restart section
for a complete description of the fault mode.
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LM25069
30086713
FIGURE 3. Power Up Sequence (Current Limit only)
Gate Control
A charge pump provides the voltage at the GATE pin to en-
hance the N-Channel MOSFET’s gate. During normal oper-
ating conditions (t3 in Figure 3) the gate of Q1 is held charged
by an internal 20 µA current source. The voltage at the GATE
pin (with respect to ground) is limited by an internal 19.5V
zener diode. See the graph “GATE Pin voltage. Since the
gate-to-source voltage applied to Q1 could be as high as
19.5V during various conditions, a zener diode with the ap-
propriate voltage rating must be added between the GATE
and OUT pins if the maximum VGS rating of the selected
MOSFET is less than 19.5V. The external zener diode must
have a forward current rating of at least 260 mA.
When the system voltage is initially applied, the GATE pin is
held low by a 260 mA pull-down current. This helps prevent
an inadvertent turn-on of the MOSFET through its drain-gate
capacitance as the applied system voltage increases.
During the insertion time (t1 in Figure 3) the GATE pin is held
low by a 2 mA pull-down current. This maintains Q1 in the off-
state until the end of t1, regardless of the voltage at VIN or
UVLO.
Following the insertion time, during t2 in Figure 3, the gate
voltage of Q1 is modulated to keep the current or power dis-
sipation level from exceeding the programmed levels. While
in the current or power limiting mode the TIMER pin capacitor
is charging. If the current and power limiting cease before the
TIMER pin reaches 1.72V the TIMER pin capacitor then dis-
charges, and the circuit enters normal operation.
If the in-rush limiting condition persists such that the TIMER
pin reached 1.72V during t2, the GATE pin is then pulled low
by the 2 mA pull-down current. The GATE pin is then held low
until either a power up sequence is initiated (LM25069-1), or
until the end of the restart sequence (LM25069-2). See the
Fault Timer & Restart section.
If the system input voltage falls below the UVLO threshold, or
rises above the OVLO threshold, the GATE pin is pulled low
by the 2 mA pull-down current to switch off Q1.
Current Limit
The current limit threshold is reached when the voltage across
the sense resistor RS (VIN to SENSE) reaches 50 mV. In the
current limiting condition, the GATE voltage is controlled to
limit the current in MOSFET Q1. While the current limit circuit
is active, the fault timer is active as described in the Fault
Timer & Restart section. If the load current falls below the
current limit threshold before the end of the Fault Timeout
Period, the LM25069 resumes normal operation. For proper
operation, the RS resistor value should be no larger than 200
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LM25069
mΩ. Higher values may result in instability in the current limit
control loop.
Circuit Breaker
If the load current increases rapidly (e.g., the load is short-
circuited) the current in the sense resistor (RS) may exceed
the current limit threshold before the current limit control loop
is able to respond. If the current exceeds approximately twice
the current limit threshold (95 mV/RS), Q1 is quickly switched
off by the 260 mA pull-down current at the GATE pin, and a
Fault Timeout Period begins. When the voltage across RS
falls below 95 mV the 260 mA pull-down current at the GATE
pin is switched off, and the gate voltage of Q1 is then deter-
mined by the current limit or the power limit functions. If the
TIMER pin reaches 1.72V before the current limiting or power
limiting condition ceases, Q1 is switched off by the 2 mA pull-
down current at the GATE pin as described in the Fault Timer
& Restart section.
Power Limit
An important feature of the LM25069 is the MOSFET power
limiting. The Power Limit function can be used to maintain the
maximum power dissipation of MOSFET Q1 within the device
SOA rating. The LM25069 determines the power dissipation
in Q1 by monitoring its drain-source voltage (SENSE to OUT),
and the drain current through the sense resistor (VIN to
SENSE). The product of the current and voltage is compared
to the power limit threshold programmed by the resistor at the
PWR pin. If the power dissipation reaches the limiting thresh-
old, the GATE voltage is modulated to regulate the current in
Q1. While the power limiting circuit is active, the fault timer is
active as described in the Fault Timer & Restart section.
Fault Timer & Restart
When the current limit or power limit threshold is reached
during turn-on or as a result of a fault condition, the gate-to-
source voltage of Q1 is modulated to regulate the load current
and power dissipation in Q1. When either limiting function is
activated, an 80 µA fault timer current source charges the ex-
ternal capacitor (CT) at the TIMER pin as shown in Figure 5
(Fault Timeout Period). If the fault condition subsides during
the Fault Timeout Period before the TIMER pin reaches
1.72V, the LM25069 returns to the normal operating mode
and CT is discharged by the 2.5 µA current sink. If the TIMER
pin reaches 1.72V during the Fault Timeout Period, Q1 is
switched off by a 2 mA pull-down current at the GATE pin.
The subsequent restart procedure then depends on which
version of the LM25069 is in use.
The LM25069-1 latches the GATE pin low at the end of the
Fault Timeout Period. CT is then discharged to ground by the
2.5 µA fault current sink. The GATE pin is held low by the 2
mA pull-down current until a power up sequence is externally
initiated by cycling the input voltage (VSYS), or momentarily
pulling the UVLO pin below its threshold with an open-collec-
tor or open-drain device as shown in Figure 4. The voltage at
the TIMER pin must be less than 0.3V for the restart proce-
dure to be effective.
30086715
FIGURE 4. Latched Fault Restart Control
The LM25069-2 provides an automatic restart sequence
which consists of the TIMER pin cycling between 1.72V and
1V seven times after the Fault Timeout Period, as shown in
Figure 5. The period of each cycle is determined by the 80 µA
charging current, and the 2.5 µA discharge current, and the
value of the capacitor CT. When the TIMER pin reaches 0.3V
during the eighth high-to-low ramp, the 20 µA current source
at the GATE pin turns on Q1. If the fault condition is still
present, the Fault Timeout Period and the restart cycle repeat.
The Fault Timeout Period during restart cycles is approxi-
mately 18% shorter than the initial fault timeout period which
initiated the restart cycle. This is due to the fact that the
TIMER pin transitions from 0.3V to 1.72V after each restart
time, rather than from ground.
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LM25069
30086716
FIGURE 5. Restart Sequence (LM25069-2)
Under-Voltage Lock-Out (UVLO)
The series pass MOSFET (Q1) is enabled when the input
supply voltage (VSYS) is within the operating range defined by
the programmable under-voltage lockout (UVLO) and over-
voltage lock-out (OVLO) levels. Typically the UVLO level at
VSYS is set with a resistor divider (R1-R3) as shown in Figure
1. Refering to the Block Diagram when VSYS is below the UV-
LO level, the internal 20 µA current source at UVLO is en-
abled, the current source at OVLO is off, and Q1 is held off
by the 2 mA pull-down current at the GATE pin. As VSYS is
increased, raising the voltage at UVLO above its threshold the
20 µA current source at UVLO is switched off, increasing the
voltage at UVLO, providing hysteresis for this threshold. With
the UVLO pin above its threshold, Q1 is switched on by the
20 µA current source at the GATE pin if the insertion time
delay has expired. See the Applications Section for a proce-
dure to calculate the values of the threshold setting resistors
(R1-R3). The minimum possible UVLO level at VSYS can be
set by connecting the UVLO pin to VIN. In this case Q1 is
enabled after the insertion time.
Over-Voltage Lock-Out (OVLO)
The series pass MOSFET (Q1) is enabled when the input
supply voltage (VSYS) is within the operating range defined by
the programmable under-voltage lockout (UVLO) and over-
voltage lock-out (OVLO) levels. If VSYS raises the OVLO pin
voltage above its threshold Q1 is switched off by the 2 mA
pull-down current at the GATE pin, denying power to the load.
When the OVLO pin is above its threshold, the internal 20 µA
current source at OVLO is switched on, raising the voltage at
OVLO to provide threshold hysteresis. When VSYS is reduced
below the OVLO level Q1 is enabled. See the Applications
Section for a procedure to calculate the threshold setting re-
sistor values.
Shutdown Control
The load current can be remotely switched off by taking the
UVLO pin below its threshold with an open collector or open
drain device, as shown in Figure 6. Upon releasing the UVLO
pin the LM25069 switches on the load current with in-rush
current and power limiting.
30086717
FIGURE 6. Shutdown Control
Power Good Pin
The Power Good indicator pin (PGD) is connected to the drain
of an internal N-channel MOSFET capable of sustaining 17V
in the off-state, and transients up to 20V. An external pull-up
resistor is required at PGD to an appropriate voltage to indi-
cate the status to downstream circuitry. The off-state voltage
at the PGD pin can be higher or lower than the voltages at
VIN and OUT. PGD is switched high when the voltage from
SENSE to OUT (the external MOSFET’s VDS) decreases be-
low 1.3V. PGD switches low when the MOSFET’s VDS is
increased past 1.9V. If the UVLO pin is taken below its thresh-
old or the OVLO pin taken above its threshold, to disable the
LM25069, PGD switches low within 10 µs without waiting for
the voltage at OUT to fall. The PGD output pin is high when
the voltage at VIN is less than 1.6V.
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LM25069
Application Information
(Refer to Figure 1)
CURRENT LIMIT, RS
The LM25069 monitors the current in the external MOSFET
(Q1) by measuring the voltage across the sense resistor
(RS), connected from VIN to SENSE. The required resistor
value is calculated from:
(1)
where ILIM is the desired current limit threshold. If the voltage
across RS reaches 50 mV, the current limit circuit modulates
the gate of Q1 to regulate the current at ILIM. While the current
limiting circuit is active, the fault timer is active as described
in the Fault Timer & Restart section. For proper operation,
RS must be no larger than 200 mΩ.
While the maximum load current in normal operation can be
used to determine the required power rating for resistor RS,
basing it on the current limit value provides a more reliable
design since the circuit can operate near the current limit
threshold continuously. The resistor’s surge capability must
also be considered since the circuit breaker threshold is ap-
proximately twice the current limit threshold. Connections
from RS to the LM25069 should be made using Kelvin tech-
niques. In the suggested layout of Figure 7 the small pads at
the lower corners of the sense resistor connect only to the
sense resistor terminals, and not to the traces carrying the
high current. With this technique, only the voltage across the
sense resistor is applied to VIN and SENSE, eliminating the
voltage drop across the high current solder connections.
30086719
FIGURE 7. Sense Resistor Connections
POWER LIMIT THRESHOLD
The LM25069 determines the power dissipation in the exter-
nal MOSFET (Q1) by monitoring the drain current (the current
in RS), and the VDS of Q1 (SENSE to OUT pins). The resistor
at the PWR pin (RPWR) sets the maximum power dissipation
for Q1, and is calculated from the following equation:
RPWR = 2.32 x 105 x RS x PFET(LIM) (2)
where PFET(LIM) is the desired power limit threshold for Q1,
and RS is the current sense resistor described in the Current
Limit section. For example, if RS is 10 mΩ , and the desired
power limit threshold is 20W, RPWR calculates to 46.4 kΩ. If
Q1’s power dissipation reaches the threshold Q1’s gate is
modulated to regulate the load current, keeping Q1’s power
from exceeding the threshold. For proper operation of the
power limiting feature, RPWR must be ≤150 kΩ. While the
power limiting circuit is active, the fault timer is active as de-
scribed in the Fault Timer & Restart section. Typically, power
limit is reached during startup, or if the output voltage falls due
to a severe overload or short circuit.
The programmed maximum power dissipation should have a
reasonable margin from the maximum power defined by the
FET's SOA chart if the LM25069-2 is used since the FET will
be repeatedly stressed during fault restart cycles. The FET
manufacturer should be consulted for guidelines.
If the application does not require use of the power limit func-
tion the PWR pin can be left open.
The accuracy of the power limit function at turn-on may de-
grade if a very low value power dissipation limit is set. The
reason for this caution is that the voltage across the sense
resistor, which is monitored and regulated by the power limit
circuit, is lowest at turn-on when the regulated current is at
minimum. The voltage across the sense resistor during power
limit can be expressed as follows:
where IL is the current in RS, and VDS is the voltage across
Q1. For example, if the power limit is set at 20W with RS = 10
mohms, and VDS = 15V the sense resistor voltage calculates
to 13.3 mV, which is comfortably regulated by the LM25069.
However, if a lower power limit is set lower (e.g., 2W), the
sense resistor voltage calculates to 1.33 mV. At this low level
noise and offsets within the LM25069 may degrade the power
limit accuracy. To maintain accuracy, the sense resistor volt-
age should not be less than 5 mV.
TURN-ON TIME
The output turn-on time depends on whether the LM25069
operates in current limit, or in both power limit and current
limit, during turn-on.
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LM25069
A) Turn-on with current limit only: The current limit thresh-
old (ILIM) is determined by the current sense resistor (RS). If
the current limit threshold is less than the current defined by
the power limit threshold at maximum VDS the circuit operates
at the current limit threshold only during turn-on. Referring to
Figure 10a, as the load current reaches ILIM, the gate-to-
source voltage is controlled at VGSL to maintain the current at
ILIM. As the output voltage reaches its final value, (VDS ≊ 0V)
the drain current reduces to its normal operating value. The
time for the OUT pin voltage to transition from zero volts to
VSYS is equal to:
where CL is the load capacitance. For example, if VSYS = 12V,
CL = 1000 µF, and ILIM = 1A, tON calculates to 12 ms. The
maximum instantaneous power dissipated in the MOSFET is
12W. This calculation assumes the time from t1 to t2 in Figure
10a is small compared to tON, and the load does not draw any
current until after the output voltage has reached its final val-
ue, and PGD switches high (Figure 8). If the load draws
current during the turn-on sequence (Figure 9), the turn-on
time is longer than the above calculation, and is approximate-
ly equal to:
where RL is the load resistance. The Fault Timeout Period
must be set longer than tON to prevent a fault shutdown before
the turn-on sequence is complete.
30086722
FIGURE 8. No Load Current During Turn-On
30086723
FIGURE 9. Load Draws Current During Turn-On
B) Turn-on with power limit and current limit: The maxi-
mum allowed power dissipation in Q1 (PFET(LIM)) is defined by
the resistor at the PWR pin, and the current sense resistor
RS. See the Power Limit Threshold section. If the current limit
threshold (ILIM) is higher than the current defined by the power
limit threshold at maximum VDS (PFET(LIM)/VSYS) the circuit op-
erates initially in the power limit mode when the VDS of Q1 is
high, and then transitions to current limit mode as the current
increases to ILIM and VDS decreases. See Figure 10b. As-
suming the load (RL) is not connected during turn-on, the time
for the output voltage to reach its final value is approximately
equal to:
For example, if VSYS = 12V, CL = 1000 µF, ILIM = 1A, and
PFET(LIM) = 10W, tON calculates to ≊12.2 ms, and the initial
current level (IP) is approximately 0.83A. The Fault Timeout
Period must be set longer than tON.
www.national.com 14
LM25069
30086725
FIGURE 10. MOSFET Power Up Waveforms
MOSFET SELECTION
It is recommended that the external MOSFET (Q1) selection
be based on the following criteria:
- The BVDSS rating should be greater than the maximum
system voltage (VSYS), plus ringing and transients which can
occur at VSYS when the circuit card, or adjacent cards, are
inserted or removed.
- The maximum continuous current rating should be based
on the current limit threshold (50 mV/RS), not the maximum
load current, since the circuit can operate near the current
limit threshold continuously.
- The Pulsed Drain Current spec (IDM) must be greater than
the current threshold for the circuit breaker function (95 mV/
RS).
- The SOA (Safe Operating Area) chart of the device, and
the thermal properties, should be used to determine the max-
imum power dissipation threshold set by the RPWR resistor.
The programmed maximum power dissipation should have a
reasonable margin from the maximum power defined by the
FET's SOA chart if the LM25069-2 is used since the FET will
be repeatedly stressed during fault restart cycles. The FET
manufacturer should be consulted for guidelines.
- RDS(on) should be sufficiently low that the power dissipa-
tion at maximum load current (IL(max)2 x RDS(on)) does not raise
its junction temperature above the manufacturer’s recom-
mendation.
If the circuit’s input voltage is at the low end of the LM25069’s
operating range (<3.5V), or at the high end of the operating
range (>14V), the gate-to-source voltage applied to the MOS-
FET by the LM25069 is less than 5V, and can approach 1V
in a worst case situation. See the graph “GATE Pin Voltage”.
The selected device must have a suitable Gate-to-Source
Threshold Voltage.
The gate-to-source voltage provided by the LM25069 can be
as high as 19.5V at turn-on when the output voltage is zero.
At turn-off the reverse gate-to-source voltage will be equal to
the output voltage at the instant the GATE pin is pulled low.
If the device chosen for Q1 is not rated for these voltages, an
external zener diode must be added from its gate to source,
with the zener voltage less than the device maximum VGS
rating. The zener diode’s working voltage protects the MOS-
FET during turn-on, and its forward voltage protects the MOS-
FET during shutoff. The zener diode’s forward current rating
must be at least 260 mA to conduct the GATE pull-down cur-
rent when a circuit breaker condition is detected.
TIMER CAPACITOR, CT
The TIMER pin capacitor (CT) sets the timing for the insertion
time delay, fault timeout period, and restart timing of the
LM25069-2.
A) Insertion Delay - Upon applying the system voltage
(VSYS) to the circuit, the external MOSFET (Q1) is held off
during the insertion time (t1 in Figure 3) to allow ringing and
transients at VSYS to settle. Since each backplane’s response
to a circuit card plug-in is unique, the worst case settling time
must be determined for each application. The insertion time
starts when VIN reaches the POR threshold, at which time the
internal 5.5 µA current source charges CT from 0V to 1.72V.
The required capacitor value is calculated from:
For example, if the desired insertion delay is 250 ms, CT cal-
culates to 0.8 µF. At the end of the insertion delay, CT is
quickly discharged by a 2 mA current sink.
B) Fault Timeout Period - During in-rush current limiting or
upon detection of a fault condition where the current limit and/
or power limit circuits regulate the current through Q1, the
fault timer current source (80 µA) switches on to charge CT.
The Fault Timeout Period is the time required for the voltage
at the TIMER pin to transition from ground to 1.72V, at which
time Q1 is switched off. If the LM25069-1 is in use, the re-
quired capacitor value is calculated from:
(3)
For example, if the desired Fault Timeout Period is 17 ms,
CT calculates to 0.8 µF. When the Fault Timeout Period ex-
pires, the LM25069-1 latches the GATE pin low until a power-
up sequence is initiated by external circuitry. If the LM25069-2
is in use, the Fault Timeout Period during restart cycles is
approximately 18% shorter than the initial fault timeout period
which initiated the restart cycles since the voltage at the
TIMER pin transitions from 0.3V to 1.72V. Since the Fault
Timeout Period must always be longer than the turn-on-time,
15 www.national.com
LM25069
the required capacitor value for the LM25069-2 is calculated
using this shorter time period:
(4)
For example, if the desired Fault Timeout Period is 17 ms,
CT calculates to 0.96 µF. When the Fault Timeout Period of
the LM25069-2 expires, a restart sequence starts as de-
scribed below (Restart Timiing). Since the LM25069 normally
operates in power limit and/or current limit during a power-up
sequence, the Fault Timeout Period MUST be longer than the
time required for the output voltage to reach its final value.
See the Turn-on Time section
C) Restart Timing For the LM25069-2, after the Fault Time-
out Period described above, CT is discharged by the 2.5 µA
current sink to 1.0V. The TIMER pin then cycles through sev-
en additional charge/discharge cycles between 1V and 1.72V
as shown in Figure 5. The restart time ends when the TIMER
pin voltage reaches 0.3V during the final high-to-low ramp.
The restart time, after the Fault Timeout Period, is equal to:
= CT x 2.65 x 106
For example, if CT = 0.8 µF, tRESTART = 2.12 seconds. At the
end of the restart time, Q1 is switched on. If the fault is still
present, the fault timeout and restart sequence repeats. The
on-time duty cycle of Q1 is approximately 0.67% in this mode.
UVLO, OVLO
By programming the UVLO and OVLO thresholds the
LM25069 enables the series pass device (Q1) when the input
supply voltage (VSYS) is within the desired operational range.
If VSYS is below the UVLO threshold, or above the OVLO
threshold, Q1 is switched off, denying power to the load. Hys-
teresis is provided for each threshold.
Option A: The configuration shown in Figure 11 requires
three resistors (R1-R3) to set the thresholds.
30086729
FIGURE 11. UVLO and OVLO Thresholds Set By R1-R3
The procedure to calculate the resistor values is as follows:
- Choose the upper UVLO threshold (VUVH), and the lower
UVLO threshold (VUVL).
- Choose the upper OVLO threshold (VOVH).
- The lower OVLO threshold (VOVL) cannot be chosen in
advance in this case, but is determined after the values for
R1-R3 are determined. If VOVL must be accurately defined in
addition to the other three thresholds, see Option B below.
The resistors are calculated as follows:
The lower OVLO threshold is calculated from:
As an example, assume the application requires the following
thresholds: VUVH = 8V, VUVL = 7V, VOVH = 15V.
The lower OVLO threshold calculates to 13.9V, and the OVLO
hysteresis is 1.1V. Note that the OVLO hysteresis is always
slightly greater than the UVLO hysteresis in this configuration.
When the R1-R3 resistor values are known, the threshold
voltages and hysteresis are calculated from the following:
VUV(HYS) = R1 x 20 µA
VOV(HYS) = (R1 + R2) x 20 µA
Option B: If all four thresholds must be accurately defined,
the configuration in Figure 12 can be used.
www.national.com 16
LM25069
30086741
FIGURE 12. Programming the Four Thresholds
The four resistor values are calculated as follows:
- Choose the upper and lower UVLO thresholds (VUVH) and
(VUVL).
-Choose the upper and lower OVLO threshold (VOVH) and
(VOVL).
As an example, assume the application requires the following
thresholds: VUVH = 8V, VUVL = 7V, VOVH = 15.5V, and VOVL =
14V. Therefore VUV(HYS) = 1V, and VOV(HYS) = 1.5V. The re-
sistor values are:
R1 = 50 kΩ, R2 = 10 kΩ
R3 = 75 kΩ, R4 = 6.07 kΩ
Where the R1-R4 resistor values are known, the threshold
voltages and hysteresis are calculated from the following:
VUV(HYS) = R1 x 20 µA
VOV(HYS) = R3 x 20 µA
Option C: The minimum UVLO level is obtained by connect-
ing the UVLO pin to VIN as shown in Figure 13. Q1 is switched
on when the VIN voltage reaches the POR threshold (≊2.6V).
The OVLO thresholds are set using R3, R4. Their values are
calculated using the procedure in Option B.
30086750
FIGURE 13. UVLO = POR with Shutdown/Restart Control
Option D: The OVLO function can be disabled by grounding
the OVLO pin. The UVLO thresholds are set as described in
Option B or Option C.
POWER GOOD PIN
During turn-on, the Power Good pin (PGD) is high until the
voltage at VIN increases above ≊ 1.6V. PGD then switches
low, remaining low as the VIN voltage increases. When the
voltage at OUT increases to within 1.3V of the SENSE pin
(VDS <1.3V), PGD switches high. PGD switches low if the
17 www.national.com
LM25069
VDS of Q1 increases above 1.9V. A pull-up resistor is required
at PGD as shown in Figure 14. The pull-up voltage (VPGD) can
be as high as 17V, and can be higher or lower than the volt-
ages at VIN and OUT.
30086751
FIGURE 14. Power Good Output
If a delay is required at PGD, suggested circuits are shown in
Figure 15. In Figure 15a, capacitor CPG adds delay to the ris-
ing edge, but not to the falling edge. In Figure 15b, the rising
edge is delayed by RPG1 + RPG2 and CPG, while the falling
edge is delayed a lesser amount by RPG2 and CPG. Adding a
diode across RPG2 (Figure 15c) allows for equal delays at the
two edges, or a short delay at the rising edge and a long delay
at the falling edge.
30086752
FIGURE 15. Adding Delay to the Power Good Output Pin
Design-in Procedure
The recommended design-in procedure is as follows:
•Determine the current limit threshold (ILIM). This threshold
must be higher than the normal maximum load current,
allowing for tolerances in the current sense resistor value
and the LM25069 Current Limit threshold voltage. Use
equation 1 to determine the value for RS.
•Determine the maximum allowable power dissipation for
the series pass FET (Q1), using the device’s SOA
information. Use equation 2 to determine the value for
RPWR.
•Determine the value for the timing capacitor at the TIMER
pin (CT) using equation 3 or equation 4. The fault timeout
period (tFAULT) must be longer than the circuit’s turn-on-
time. The turn-on time can be estimated using the
equations in the TURN-ON TIME section of this data
sheet, but should be verified experimentally. Review the
resulting insertion time, and restart timing if the
LM25069-2 is used.
•Choose option A, B, C, or D from the UVLO, OVLO section
of the Application Information for setting the UVLO and
OVLO thresholds and hysteresis. Use the procedure for
the appropriate option to determine the resistor values at
the UVLO and OVLO pins.
•Choose the appropriate voltage, and pull-up resistor, for
the Power Good output.
PC Board Guidelines
The following guidelines should be followed when designing
the PC board for the LM25069:
•Place the LM25069 close to the board’s input connector
to minimize trace inductance from the connector to the
FET.
•Place a small capacitor (1000 pF) directly adjacent to the
VIN and GND pins of the LM25069 to help minimize
transients which may occur on the input supply line.
Transients of several volts can easily occur when the load
current is shut off.
•The sense resistor (RS) should be close to the LM25069,
and connected to it using the Kelvin techniques shown in
Figure 7.
•The high current path from the board’s input to the load
(via Q1), and the return path, should be parallel and close
to each other to minimize loop inductance.
•The ground connection for the various components
around the LM25069 should be connected directly to each
other, and to the LM25069’s GND pin, and then connected
to the system ground at one point. Do not connect the
various component grounds to each other through the high
current ground line.
•Provide adequate heat sinking for the series pass device
(Q1) to help reduce stresses during turn-on and turn-off.
•The board’s edge connector can be designed to shut off
the LM25069 as the board is removed, before the supply
www.national.com 18
LM25069
voltage is disconnected from the LM25069. In Figure 16
the voltage at the UVLO pin goes to ground before VSYS
is removed from the LM25069 due to the shorter edge
connector pin. When the board is inserted into the edge
connector, the system voltage is applied to the LM25069’s
VIN pin before the UVLO voltage is taken high.
30086753
FIGURE 16. Recommended Board Connector Design
19 www.national.com
LM25069
System Considerations
A) Continued proper operation of the LM25069 hot swap cir-
cuit requires capacitance be present on the supply side of the
connector into which the hot swap circuit is plugged in, as
depicted in Figure 2. The capacitor in the “Live Power Source”
section is necessary to absorb the transient generated when-
ever the hot swap circuit shuts off the load current. If the
capacitance is not present, inductance in the supply lines will
generate a voltage transient at shut-off which can exceed the
absolute maximum rating of the LM25069, resulting in its de-
struction.
B) If the load powered by the LM25069 hot swap circuit has
inductive characteristics, a Schottky diode is required across
the LM25069’s output, along with some load capacitance.
The capacitance and the diode are necessary to limit the
negative excursion at the OUT pin when the load current is
shut off. If the OUT pin transitions more than 0.3V negative
the LM25069 will internally reset, interfering with the latch-off
feature of the LM25069-1, or the restart cycle of the
LM25069-2. See Figure 17.
30086754
FIGURE 17. Output Diode Required for Inductive Loads
www.national.com 20
LM25069
Physical Dimensions inches (millimeters) unless otherwise noted
NS Package Number MUB10A
21 www.national.com
LM25069
Notes
LM25069 Positive Low Voltage Power Limiting Hot Swap Controller
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