LM98516CCMTNOPB - NATIONAL SEMICONDUCTOR

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General Description

The LM9833 is a complete USB image scanner system on a sin-

gle IC. The LM9833 provides all the functions (image sensor

control, illumination control, analog front end, pixel processing

function image data buffer/DRAM controller, microstepping

motor contr oller, and USB interfa ce) necessary to create a high

perform ance col or scanner. The LM9833 scan s images i n 48 bit

color/16 bit gray, and has output data formats for 48 and 24bit

color/1 6 an d 8 b it gra y. The LM9833 su pp orts sensors wi t h pixe l

counts of up to 16384 pixels x 3 colors (1200 dpi x 13.6 inches).

The LM9833’s low operating and suspend mode supply currents

allow design of USB b us- powe re d scan ne rs. The onl y a ddit io nal

active components required are an external 4Mbit or 16Mbit

DRAM for data buffering and power transistors for the stepper

motor.

Applications

• Color Flatbed Document Scanners

• Color Sheetfed Document Scanners

Key Specificati ons

• Analog to Digital Converter Resolution 16 Bits

• Maximum Pixel Conversion Rate 6MHz

• A4 Color 150dpi scan time <10 seconds

• A4 Color 300dpi scan time <40 seconds

• A4 Color 600dpi scan time <160 seconds

• Supply Voltage

- LM9833 +4.75V to +5.25V

- LM9833 DRAM I/O +2.85 to +5.25V

• Maximum Operating Current Consumption 136mA

• Maximum Suspend Current Consumption 175µA

Features

• 16 bit ADC digitizes at up to 6Mpixels/s (2M RGB pixels/sec).

• Digital Pixel Processing provides 1200, 800, 600, 400, 300,

200, 150, and 100dpi horizontal resolution from a 1200dpi

sensor and 600, 400, 300, 200, 150, 100, 75, and 50dpi

horizontal resolution from a 600dpi sensor.

• Provides 50-2400dpi vertical resolution in 1 dpi increments.

• Pixel rate error correction for gain (shading) and offset errors.

• Supports 4 or 16Mbit ext ernal DRAMs.

• Multiple CCD clocking rates allows match ing of CCD clock to

scan resolution and pixel depth for maximum scan speed.

• Stepper motor control tightly coupled with image data buffer

management to maximize data transfer efficiency.

• PWM stepp er motor current control allows microsteppin g for

the price of fullstepping.

• USB int erface for P lug and Play o perat ion on USB-eq uipped

computers.

• Serial EEPROM option for custom Vendor and Product IDs.

• Support for USB bus-powered operation.

• Pixel depths of 1, 2, or 4 bits are packed into bytes for faster

scans of line art and low pixel depth images.

• Supports 3 channel CCDs and 1 channel CIS sensors.

• 3 (R, G, a nd B ) 12- bit, u ser -pr ogrammabl e gam ma cor rect i on

tables.

• Compatible with a wide range of color linear CCDs and

Contact Ima ge Senso rs (CIS ).

• Operates with 48MHz external crystal.

• Internal bandgap voltage reference.

• 100 pin TQFP package

LM9833 48-Bit Color, 1200dpi USB Image Scanner

CCD/CIS

Illumination

+12V

Stepper

Motor

1-3

2-6 Power

Transistors

DRAM

LM9833CCVJD

USB

Port

48MHz Crystal

Serial

EEPROM

8MISC

I/O

LM9833 Scanner System Block Diagram

Ordering Information

Commercial (0°C ≤ TA ≤ +70°C) Package

LM9833CCV JD VJD100A 100 Pin Thin Quad Flatpac

LM9833 48-Bit Color 1200 dpi USB Image Scanner

October 2001

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Connection Diagram

Ordering Information

Commercial (0°C ≤ TA ≤ +70°C) Package

LM9833CCVJD VJD100A 100 Pin Thin Quad Flatpac

100999897969594939291908988878685848382818079787776

VBANDGAP

VREF LO

OSR

VREF MI D

OSG

VREF HI

OSB

AGND

D15

VDRAM

DGND

D14

D13

D12

D11

D10

VDRAM

DGND

CAS

RAS

VDRAM

DGND

SDA

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

ø1

TR2

TR1

MISC I/O 6

MISC I/O 5

MISC I/O 4

DGND

MISC I/O 3

MISC I/O 2

MISC I/O 1

PAPER SENSE 1

PAPER SENSE 2

DGND

LAMPB

LAMPG

LAMPR

DGND

24/48

CRYSTAL/EXT CLK

CRYSTAL IN

CRYSTAL OUT

SCL

AGND

DGND

TEST

SENSEGND

SENSEA

SENSEB

CMODE

RESET

DGND

BUS POWR

D+

D-

VREGULATOR

DGND

ACTIVE/SUSPENDED

CP2

CP1

ø2

LM9833CCVJD

LM9833

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Pin Descriptions

USB Interface

D+, D- Digital I/O. USB Interface signals

BUS POWER Digital Input. Tie low for bus powered sys-

tems, tie high for external power.

ACTIVE/

SUSPENDED

Digital Output. Low in Suspend mode. High in

operational mode. Used to control external

regulators, other components.

SDA Digital I/O. Serial Data to/from external

EEPROM.

SCL Digital Output. S erial Clock Out put to exte rna l

EEPROM.

Analog

OSR,

OSG,

OSB

Analog Inputs. T hese i nputs (for Red, Gre en,

and Blue) should be tied to the sensor ’s out-

put signal through DC blocking capacitors. If

unused, tie to ground through DC blocking

capacitors.

VREF LO Analog Output/Input . Bypass to AGND with a

0.047µF monolithic capacitor. Do not put a

DC load on this pin.

VREF MID Analog Output/Input . Bypass to AGND with a

0.047µF monolithic capacitor. Do not put a

DC load on this pin.

VREF HI Analog Output/Input . Bypass to AGND with a

0.047µF monolithic capacitor. Do not put a

DC load on this pin.

VBANDGAP Analog Output. Bypass to AGND with a

0.047µF monolithic capacitor. Do not put a

DC load on this pin.

DRAM

D0 (LSB) -D15

(MSB) Digital Inputs/Outputs. This is the 16 bit data

path between the external DRAM and the

LM9833.

RD Digital Output. Read signal to external DRAM.

WR Digital Output. Write signal to external DRAM.

A0-A9 Digital Outputs. Address pins for up to 1M x

16 external DRAM.

RAS Digital Output. Row Address Strobe signal.

CAS Digital Output. Column Address Strobe sig-

nal.

Scanner Support I/O

PAPER

SENSE 1-2 Digital Inputs. Programmable, used for sens-

ing home position, paper, front panel

switches, etc.

MISC I/O 1-6 Digital Inputs/Outputs. Programmable, used

for front panel switches, status LEDs, etc. At

power-on and in Suspend Mode, MISC I/Os

1-3 are inputs and MISC I/Os 4-6 are outputs.

Step per Motor

A, B, A, B Digital Outputs. Puls es to stepper motor drive

circuitry.

SENSEA,

SENSEB

Analog Inputs. Current sensing for stepper

motor’s PWM current control.

SENSEGND Anal og Input. Gr ound sense in put for st epper

motor’s PWM current control.

Senso r Control

ø1 Digital Output. CCD/CIS clock signal phase 1.

ø2 Digital Output. CCD/CIS clock signal phase 2.

RS Digital Output. Reset pulse for the CCD/CIS.

CP1 Digital Output. Clamp pulse for the CCD/CIS.

CP2 Digital Output. Clamp pulse for the CCD/CIS.

TR1, TR2 Digital Outputs. Transfer pulses for the

CCD/CIS.

LAMPR,

LAMPG,

LAMPB

Digital Outputs. Used to control R, G, and B

LEDs of single output CIS, as well as bright-

ness of CCFL. The CDS signal can be seen

on LAMP B in a te st mo de (see registe r 5E, bi t

7).

Master Clock Generation

CRYSTAL IN Digital Input. Used with CRYSTAL OUT and

an external 48MHz crystal to form a crystal

oscillator.

CRYSTAL

OUT Digital Output. Used with CR YSTAL IN and an

external 48 MHz cr ystal to form a cryst al oscil-

lator.

CRYSTAL/

EXT CLOCK

Digital Input. Tie to DGND for operation with

an external crystal. Pull up to VD to drive

CRYSTAL OUT with an external TTL or

CMOS clock source.

24/48 Dig ital Input. Tie to DGND for operation with a

48MHz crysta l or e xter nal clo ck. P ull up to V D

for oper ation with a 2 4M Hz cr ystal or externa l

clock. NOTE: Operation at 24MHz is not guar-

anteed - always use a 48MHz crystal.

Miscellaneous

VREGULATOR Digital Output. This is the regu l ate d 3.3 V sup-

ply (g enera ted fro m V D) that powers the USB

transcei ver. It sh ould be u sed as th e termi nal

voltage for the 1.5k D+ pullup resistor, and

bypassed to DGND with a 0.047µF monolithic

capacitor.

RESET Digital input. Take high to force device into

Power On Reset state, low to exit reset state.

TEST Analog Output.

CMODE Digital Input. Test mode, always tie high.

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Analog Power Supplies (4 pins)

VA (2) This is the positive supply pin for the analog

supply. It should be connected to a voltage

source of +5V and bypassed to AGND with a

0.1µF monolithic capacitor in parallel with a

10µF tantalum capacitor.

AGND (2) This is the ground return for the analog sup-

ply.

Digital Power Supplies (17 pins)

VD (5) This is the positive supply pin for the digital

supply. It should be connected to a voltage

source of +5V and bypassed to DGND wit h a

0.1µF monolithic capacitor.

VDRAM(3) This is the positive supply pin for the digital

supply for the LM9833’s external DRAM I/O. It

also po wers the A, B , A , an d B ste pper mo tor

outputs. It should be connected to a 3 or 5V

supply and bypassed to the closest DGND pin

with a 0.1µF monolithic capacitor.

DGND (9) This is the ground return for VD and VDRAM.

Pin Descriptions (Continued)

LM9833

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Electrical Characteristics

The following specifications apply for AGND=DGND=0V, VA=VD=VDRAM=+5.0VDC, fCRYST AL IN= 48MHz, Analo g Bias Current =

100%, unless otherwise noted. Boldface limits apply for T A=TJ=TMIN to TMAX; all other limits TA=TJ=25°C. (Notes 8, 9, & 10)

Symbol Parameter Conditions Typical

(Note 9) Limits

(Note 10) Units

(Limits)

Full Channel Characteristics (in units of 12 bit LSBs unless otherwise noted)

Resolution with No Missing Codes 16 12 bits (min)

DNL Differential Non- Lin ear i ty

(Note 14) Bias Current = 80%,

VDRAM=3.3V -0.45

+0.75 -0.9

+2.4 LSB (min)

LSB (max)

INL Integral Non- Line ar i ty Error

(Notes 11 & 14) Bias Current = 80%,

VDRAM=3.3V -2.3

+1.7 -8.5

+7.5 LSB (min)

LSB (max)

CAnalog Channel Gain Constant

(ADC Code s/V), refer red to 16 bi ts. Includes voltage reference

variation, gain setting = 1 32768 29648

37200 LSB (min)

LSB (max)

VOS1 Pre-Boost Analog Channel Offset Error 26 -34

+76 mV (min )

mV (max)

VOS2 Pre-PGA Analog Channel Offset Error -30 -80

+31 mV (min )

mV (max)

VOS3 Post-PGA Analog Channel Offset Error -26 -75

+26 mV (min )

mV (max)

Coarse Color Balance PGA Characteristics (Configuration Registers 3B, 3C, and 3D)

Monotonicity 5bits (min)

G0 (Minimum PGA Gain) PGA Setting = 0 0.93 0.90

0.96 V/V (min)

V/V (max)

G31 (Maximum PGA Gain) PGA Setting = 31 3.00 2.95

3.10 V/V (min)

V/V (max)

x3 Boost Gain x3 Boost Setting On

(bit B5 of Gain Register is set) 2.94 2.85

3.04 V/V (min)

V/V (max)

Gain Error at any gain (Note 13) 0.3 -0.6

+0.9 % (min)

% (max)

Static Offset DAC Characteristics (Configuration Registers 38, 39, and 3A)

Monotonicity 6bits (min)

Offset DAC LSB size PGA gain = 1 9 6

12 mV (min )

mV (max)

Offset DAC Adjustment Range PGA gain = 1 ±278 ±256 mV (min )

Positive Supply Voltage (V+=VA=VD=VDRAM)

With Respect to GND=AGND=DGND 6.5V

Voltage On Any Input or Output Pin -0.3V to V++0.3V

Input Curr ent at any pin (Not e 3) ±25mA

Package Inp ut Curr ent (Note 3) ±50mA

Package Dissipa ti on at TA = 25°C (Note 4)

ESD Susceptibility (Note 5)

Human Body Mo del 2000 V

Machine Model 250 V

Soldering Information

Infrared, 10 seconds (Note 6) 235°C

Storage Temperature -65°C to +150°

Operating Temperature Range TMIN≤TA≤TMAX

LM9833CCVJD 0°C≤TA≤+70°C

VA Supply Voltage +4.75V to +5.25V

VD Supply Voltage +4.75V to +5.25V

VDRAM Supply Voltage +2.85V ≤ VDRAM ≤ VD+100mV

|VA-VD|≤ 100mV

Input Voltage Range -0.05V to V+ + 0.05V

Absolute Maximum Ratings (Notes 1 & 2) Operating Ratings (Notes 1 & 2)

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CCD/CIS Source Requirements for Full Specified Accuracy an d Dynamic Range (Note 12)

VCCDPEAK

Sensor’s Maximu m Outp ut Sig nal

Amplitude before LM9833 Analog Front

End Saturatio n

Gain = 0.933

Gain = 3.0

Gain = 9.0

1.9

0.6

0.19

Analog Input Characteristics

Average OSR, OSG, OSB Input Current CDS Enabled, OS = 3.5VDC ±3 nA

OSR, OSG, OSB Input Current CDS Disabled, OS = 3.5VDC ±26 ±30 µA (max)

Internal Voltage Reference Characteristics

VBANDGAP Voltage R efe ren ce Outp ut Voltage 1.23 V

VREF LO Negative Reference Output Voltage VREF MID-1.0 V

VREF M I D Midpoint Reference Output Voltage VA/2.0 V

VREF HI Positive Reference Output Voltage VREF MID+1.0 V

VREGULA-

TOR USB I/O Voltage Regulator 3.3 V

DC and Logic Electrical Characteristics

The following specifications apply for AGND=DGND=0V, VA=VD=VDRAM=+5.0VDC unless otherwise noted,

fCRYSTAL IN= 48MHz. Boldface limits apply for TA=TJ=TMIN to TMAX; all other limits TA=TJ=25°C. (Notes 8, 9, & 10)

Symbol Parameter Conditions Typical

(Note 9) Limits

(Note 10) Units

(Limits)

Digital Input Characteristics for D0-D15 (DRAM Interface)

VIN(1) Logical “1” Input Voltage VDRAM=5.25V

VDRAM=3.6V 2.0

2.0 V (min )

V (min)

VIN(0) Logical “0” Input Voltage VDRAM=4.75V

VDRAM=2.85V 0.8

0.8 V (max)

V (max)

IIN Input Leakage Current ±0.1 µA

CIN Input Capacitance 5 pF

Digital Input Characteristics for P APER SENSE 1-2, MISC I/O 1-6, SDA, BUS POWER, CRYSTAL/EXT CLOCK, 24/48, RESET,

CMODE

VIN(1) Logical “1” Input Voltage VD=5.25V 2.0 V (min )

VIN(0) Logical “0” Input Voltage VD=4.75V 0.8 V (max)

IIN Input Leakage Current ±0.1 µA

CIN Input Capacitance 5 pF

Digital Input Characteristics for D+, D-

VIN(1) Logical “1” Input Voltage VD=5.25V 2.0 V (min )

VIN(0) Logical “0” Input Voltage VD=4.75V 0.8 V (max)

IIN Input Leakage Current ±0.1 µA

CIN Input Capacitance 5 pF

Electrical Characteristics (Continued)

The following specifications apply for AGND=DGND=0V, VA=VD=VDRAM=+5.0VDC, fCRYST AL IN= 48MHz, Analo g Bias Current =

100%, unless otherwise noted. Boldface limits apply for T A=TJ=TMIN to TMAX; all other limits TA=TJ=25°C. (Notes 8, 9, & 10)

Symbol Parameter Conditions Typical

(Note 9) Limits

(Note 10) Units

(Limits)

LM9833

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Digital Output Characteristics for D0-D15, A0-A9, RD, WR, RAS, CAS (DRAM Interface)

VOUT(1) Logi cal “1” Output Voltage VDRAM=4.75V, IOUT=-4mA

VDRAM=2.85V, IOUT=-4mA 2.4

2.4 V (min )

V (min)

VOUT(0) Logi cal “0” Output Voltage VDRAM=4.75V, IOUT=4mA

VDRAM=2.85V, IOUT=4mA 0.4

0.4 V (max)

V (max)

Digital Output Characteristics for A, B, A, B

VOUT(1) Logi cal “1” Output Voltage VDRAM=4.75V, IOUT=-10mA

VDRAM=2.85V, IOUT=-10mA 2.4

2.4 V (min )

V (min)

VOUT(0) Logi cal “0” Output Voltage VDRAM=4.75V, IOUT=4mA

VDRAM=2.85V, IOUT=4mA 0.4

0.4 V (max)

V (max)

Digital Output Characteristics for MISC I/O 1-6, TR1, TR2, ø1, ø2, RS, CP1, CP2, LAMPR, LAMPG, LAMPB

VOUT(1) Logi cal “1” Output Voltage VD=4.75V, IOUT=-4mA 2.4 V (m in )

VOUT(0) Logi cal “0” Output Voltage VD=4.75V, IOUT=4mA 0.4 V (max)

Digital Output Characteristics for D+, D-

VOUT(1) Logi cal “1” Output Voltage VD=4.75V, IOUT=-1mA 2.4 V (m in )

VOUT(0) Logi cal “0” Output Voltage VD=4.75V, IOUT=3mA 0.4 V (max)

CRYSTAL IN, CRYSTAL OUT Characteristics

XTALOUT DC CRYSTAL OUT Bias Level (Offset) 0.8 V

XTALOUT AC CRYSTAL OUT Amplitude fCRYSTAL = 48MHz 0.8 VP-P

Power Supply Characteristics (Note 14)

IAAnalog S upp ly Curren t

(VA pins) Operating (Bi as Current = 80%) 65 91 mA (max)

IDDigital Supply Current

(VD pins) Ope rating (Bias Current = 80%) 35 41 mA (max)

IDRAM DRAM Supply Current

(VDRAM pins) Operatin g, VDRAM = 5V

Operating, VDRAM = 3V 2

5mA (max)

mA (max)

ISUSPEND Total Suspend Current (IA+ID+IDRAM)19175 µA (max)

DC and Logic Electrical Characteristics (Continued)

The following specifications apply for AGND=DGND=0V, VA=VD=VDRAM=+5.0VDC unless otherwise noted,

fCRYSTAL IN= 48MHz. Boldface limits apply for TA=TJ=TMIN to TMAX; all other limits TA=TJ=25°C. (Notes 8, 9, & 10)

Symbol Parameter Conditions Typical

(Note 9) Limits

(Note 10) Units

(Limits)

LM9833

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Note 1: Absolute Maximum Ratings indicate limi ts beyon d which damage to the device may occur. Operatin g Rat i ngs indica te conditi o ns for which the devi ce is functi o nal ,

but do not guarantee spec ific perfo rm ance lim it s . For guaranteed specificat ions and tes t c onditions, see the Electrica l C haracte ris t ic s . The gua ranteed specifications apply

only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.

Note 2: All voltages are measu red with resp ec t to GN D = AGND=D GND=0V, unles s otherwis e specifie d.

Note 3: When the inp ut voltag e (VIN) at any pin exceeds the power supplies (VIN<GND or VIN>VA or VD), the current at that pin should be limited to 25mA. The 50mA

maximum package input current rating limits the number of pins that can simultaneously safely exceed the power supplies with an input current of 25mA to two.

Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax, ΘJA and the ambient t em perature , TA. The maximum allow-

able power dis s ipation at any tempe rat ure is PD = (TJmax - TA) / ΘJA. TJmax = 150°C for this device. The typical thermal resistance (ΘJA) of this pa rt w hen board m ounted

is 53°C/ W.

Note 5: Human body m odel, 100pF capac it or discharged throug h a 1.5kΩ resistor. Machine model, 200pF capacitor discharged through a 0Ω resistor.

Note 6: See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any Na t ional Sem ic onductor Linear

Data Book for other methods of solder ing surface mo unt devices.

Note 7: Two diodes clamp the OS analog inputs to AGND and VA as shown below. This input protection, in combination with the external clamp capacitor and the output

imped ance of the s ensor, pre ve nt s damage t o th e LM9833 f rom transie nts during power-up.

Note 8: For best performance, it is required that all supply pins be powered from the same power supply with separate bypass capacitors at each supply pin.

Note 9: Typicals are at TJ=TA=25°C, fCRYSTAL IN = 48MHz , an d represen t most likely parametr ic norm.

Note 10: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).

Note 11: Integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that best fits the actual tr ansfe r fu nct i on o f the ADC.

Note 12: VREF is defined as the CCD OS volt age f or th e re fere nce per i od foll o wing the r eset feedthrough pulse. VWHITE is defined as the peak CCD pi xel o utpu t vo lt ag e f or

a white (fu ll scale) image with r es pect to the refe renc e leve l, VREF . VRFT is defined as the peak positive deviation above VREF of the reset feedthrough pulse. The maximum

correctable range of pixel-to-pixel VWHITE variation is defined as the maximum variation in VWHITE (due to PRNU, light source intensity variation, optics, etc.) that the

LM9833 can correct for using its internal PGA.

Note 13: PGA Gain Error is the maximum difference between the measured gain for any PGA code and the ideal gain calculated by using the formula

where .

Note 14: DN L, INL, and Po wer Supp ly Curre nt are spec ified at the 80 % Bias Curre nt Settin g (Regis ter 9). This is the maximum recomm ended Bias Curr ent sett ing, and

gives t he best ana log performance as we ll as lower power consu m pt ion for USB-bus powered applic ations.

AC Electrical Characteristics

The following specifications apply for AGND=DGND=0V, VA=VD=VDRAM=+5.0VDC unless otherwise noted,

fCRYSTAL IN= 48MHz, MCLK DIVIDER = 1.0 (unless otherwise noted), fMCLK = fCRYSTAL IN/MCLK DIVIDER, fADC CLK = fMCLK/8,

CL (databus loading) = 20pF/pin. Boldface limits apply for TA=TJ=TMIN to TMAX; all other limits TA=TJ=25°C. (Notes 8, 9, & 10)

Symbol Parameter Conditions Typical

(Note 9) Limits

(Note 10) Units

(Limits)

DRAM Timing (Figure 1)

tRD SETUP Data valid to RD rising edge VDRAM=5.0V

VDRAM=3.3V 26

35 ns (min)

ns (min)

tRD HOLD Data valid after RD rising edge 0ns (min)

tWR SETUP Data valid before WR falling edge 5ns (min)

tWR HOLD Data valid after WR rising edge 10 ns (min)

OS Input

AGND

To Internal

Circuitry

VWHITE

VREF

VRFT

CCD Output Signal

GainPGA V

----



 G0XPGA cod e

---------------------------+=XG

31 G0

–()

------=

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Timing Diagrams

Figure 1: DRAM Read and Write

Column Addressn

A0-A9 Row AddressnRow Addressn+1

RAS

CAS

DataD0-D15

tRD SETUP

tRD HOLD

DataD0-D15

tWR SETUP

tWR HOLD

01234560

48MHz Internal Clock

(tPERIOD = 20.83ns)

Read Ope rat ion

Write Operation

RAS

CAS

01234560

48MHz Internal Clock

(tPERIOD = 20.83ns)

Figure 2: DRAM Refresh (CAS before RAS)

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Registers in bold boxes are reset to that value on power-up. All register addresses are in hexadecimal. All other numbers are

decimal unless otherwise noted.

Address Function D

0Value

IMAGE BUFFER (READ ONLY)

00 Pixel (Image) Data nnnnnnnnOne byte of image data.

STATUS REGISTERS (READ ONLY)

01 Image Data Available In Buffer nnnnnnnnn*2 (256k x 16 DRAM) or n*8 (1M x 16 DRAM)

kilobytes of image data is available

PAPER SENSE 1 State

read clears bit if edge sensitive input. 0False

1True

PAPER SENSE 2 State

read clears bit if edge sensitive input. 0False

1True

MISC I/O 1 State

read clears bit if edge sensitive input. 0False

1True

MISC I/O 2 State

read clears bit if edge sensitive input. 0False

1True

MISC I/O 3 State

read clears bit if edge sensitive input. 0False

1True

MISC I/O 4 State

read clears bit if edge sensitive input. 0False

1True

MISC I/O 5 State

read clears bit if edge sensitive input. 0False

1True

MISC I/O 6 State

read clears bit if edge sensitive input. 0False

1True

DATAPORT REGISTERS

DataPort Target

0 0 Offset Coefficient Data

0 1 Gain Coeffic ient Data

1 0 Gamma Lookup Table

11N/A

DataPort Target Color

00 Red

01 Green

10 Blue

11 N/A

Pause (Read Only)

This bit indicates whether or not the scanner

is currently paused due to a buffer full

condition.

0Normal State

1 The scanner is currently in the pause/reverse cycle.

DRAM Test 0 Normal Operation

1 DRAM Test mode

04 DataPort Address - MSB R

WaaaaaaAddress of location to be read/written to.

a = 0 to 4095 for gamma tables,

0 to 16383 for Offset and Gain Coefficient Data

Addresses greater than these are illegal.

Bit D6 of register 4 indicates whether next operation

will be a Read (D6=1) or a Write (D6=0).

05 DataPort Address - LSB aaaaaaaa

06 DataPort nnnnnnnn

Data to be read from or written to the address of the

currently selected Dataport Target. The DataPort

Address is automatically incremented whenever one

(gamma data) or two (Gain/Offset Data) bytes are

read from or written to this register.

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COMMAND REGISTER

Command Register

This register is used to start and end a scan.

It is also used to home the sensor in a

flatbed scanner or eject the image in a

sheetfed scanner. No te: Always make sure

the Co m ma nd Reg i st er i s i n th e id le s t at e

(=0) before issuing a new command.

000Idle - Stops motor (A, B, A, B = 0),

completes current line of data (if scanning).

Note: CCD/CIS clocks continue clocking.

001High Speed Forward - Moves motor forward at a

speed determined by the Fast Feed Step Size

(r egisters 48 and 49).

010High Speed Reverse - Moves motor backward at a

speed determined by the Fast Feed Step Size

(r egisters 48 and 49).

011Start Scan - Resets the LM9833’s data pointers and

starts an image scan.

101

Programmed High Speed Forward - Moves motor

forward at a speed determined by the Fast Feed Step

Size (registers 48 and 49) for the number of lines

programmed in registers 4A and 4B.

110

Programmed High Speed Reverse - Moves motor

backward at a speed determined by the Fast Feed

Step Size (registers 48 and 49) for the number of lines

programmed in registers 4A and 4B.

Standby

When this bit is set the entire chip enters a

low power state.

Warning: A Standby command will stop

DRAM refresh.

0 Normal Operation.

1 Low Power Standby Mode.

Soft Reset

Write a 1 then a 0 to reset the LM9833’s

state machines.

Warning: A Reset will stop DRAM refresh.

0 Normal Operation.

1Resets the LM9833. See section 10.2 Soft Reset for

instructions on using this bit.

MASTER CLOCK DIVIDER

MCLK Divider

This register sets the master clock frequency

for the enti re scan ner.

fMCLK = 48MHz/MCLK_Divider

fADC = fMCLK/8

000000÷1.0

000001÷1.5

000110÷4

aaaaaa÷ ((aaaaaa/2)+1)

111110÷32.0

111111÷32.5

Address Function D

0Value

LM9833

12 www.national.com

HORIZONTAL RESOLUTION AND DATAMODE SETTINGS

Horizontal DPI Divider

This register determines the horizontal

resolution of the scan.

Scan resolution = Optical resolution divided

by the Horizontal_DPI_Divider.

000÷1

001÷1.5

010÷2

011÷3

100÷4

101÷6

110÷8

111÷12

Pixel P ack ing

This register determines how many bits in

each byte of data are transmitted to the host

when DataMode = 0

0 0 1 bit/pixel (1 bit grayscale/3 bit color)

0 1 2 bits/pixel (2 bit grayscale/6 bit color)

1 0 4 bits/pixel (4 bit grayscale/12 bit color)

1 1 8 bits/pixel (8 bit grayscale/24 bit color)

DataMode

When DataMode = 0, the pixel data is fully

processed, going through the Offset,

Shading, Horizontal DPI Adjust, Gamma,

and Pixel Packing blocks.

When D ataMode = 1, 16 bit da ta is extract ed

following the Shading Multiplier stage.

Gamma and any other post processing must

be done by the host.

01, 2, 4, or 8 bit image data,

as determined by the Pixel Size setting.

16 bit image data - sent in 2 bytes, MSB first:

15 14 13 12 11 10 09 08 - 07 06 05 04 03 02 01 00

Analog Bias Current (Percent of Nominal)

The recomm ended setting is 80% for best

performance. Lower settings will reduce

power consumption further but may degrade

ADC IN L and DNL performance.

0 0 100% (analog supply current = ~81mA)

0 1 80% (analog supply current = ~65mA)

1 0 70% (analog supply current = ~57mA)

1 1 50% (analog supply current = ~41mA)

TURBO AND PREVIEW MODE SETTINGS

Turbo/Preview Mode Select

0 0 Normal Operation

0 1 Preview Mode (for CCD Sensors)

1 0 Turbo Mode (for CIS Sensors)

11 N/A

Turbo/Preview Mode Speed

00 x2

0 1 x3 (3 Channel Pixel Rate Mode Only)

1 0 x4 (3 Channel Pixel Rate Mode Only)

1 1 x6 (3 Channel Pixel Rate Mode Only)

SENSOR CONFIGURATION

Input Si gnal Polarity 0 Negative (Most CCD Sensors and Toshiba CIS)

1 Positive (Most CIS Sensors)

CDS On/Off 0 CDS Off

1 CDS On

Standard/Even-Odd Sensor 0 Standard (1 pixels per Ø period)

1 Even/Odd (2 pixels per Ø period)

CIS TR1 Timing Mode

0 0 Off - use standard CCD Timing

01 CIS TR1 Timing Mode 1:

TR1 pulse = exactly one Ø clock,

starting at rising edge of Ø1

10 CIS TR1 Timing Mode 2:

TR1 pulse = exactly one Ø clock,

TR1 centered around Ø1 high.

11 N/A

Fake Optical Black Pixels

(for Dyna-type CIS sensors) 0 Off: Normal operation

1 On: RS pulse held high for entire Optical Black period

Address Function D

0Value

LM9833

13 www.national.com

SENSOR CONTROL SETTINGS

Ø1 Polarity 0 Positive

1 Negative

Ø2 Polarity 0 Positive

1 Negative

RS Polarity 0 Positive

1 Negative

CP1 Polarity 0 Positive

1 Negative

CP2 Polarity 0 Positive

1 Negative

TR1 Polarity 0 Positive

1 Negative

TR2 Polarity 0 Positive

1 Negative

Ø1 Active/Off 0Off

1Active

Ø2 Active/Off 0Off

1Active

RS Acti ve/ Off 0Off

1Active

CP1 Active/Off 0Off

1Active

CP2 Active/Off 0Off

1Active

TR1 Act ive/ Off 0Off

1Active

TR2 Act ive/ Off 0Off

1Active

Number of TR Pulses 01 TR Pulse

12 TR Pulses

0E TR Pulse Duration nnnnn+1 pixel periods (1-16)

TR-Ø1 Guardband Dura tion n n n n n pixel per iods (0-15)

0F Optical Black Clamp Start nnnnnpixel rate: n=0-23, line rate: n=0-7 MCLKs from Ø1 edge

10 Optical Black Clamp End nnnnnpixel rate: n=0-23, line rate: n=0-7 MCLKs from Ø1 edge

11 Reset Pulse Start nnnnnpixel rate: n=0-23, line rate: n=0-7 MCLKs from Ø1 edge

12 Reset Pulse Stop nnnnnpixel rate: n=0-23, line rate: n=0-7 MCLKs from Ø1 edge

13 CP1 Pulse Start nnnnnpixel rate: n=0-23, line rate: n=0-7 MCLKs from Ø1 edge

14 CP1 Pulse Stop nnnnnpixel rate: n=0-23, line rate: n=0-7 MCLKs from Ø1 edge

15 CP2 Pulse Start nnnnnpixel rate: n=0-23, line rate: n=0-7 MCLKs from Ø1 edge

16 CP2 Pulse Stop nnnnnpixel rate: n=0-23, line rate: n=0-7 MCLKs from Ø1 edge

17 Reference Sample Position nnnnnpixel rate: n=0-23, line rate: n=0-7 MCLKs from Ø1 edge

18 Signal Sampl e Position nnnnnpixel rate: n=0-23, line rate: n=0-7 MCLKs from Ø1 edge

INTEGR ATION TIME ADJUST

19 Integra tion Time Adjustm ent Funct ion nnnnnnntREADOUT = n*tINT, n = 1 to 127. n=0 turns off function.

STEPPER PHASE CORRECTION

1A TR to Stepper Phase Correction - MSB nnnnnnFirst step of scan occurs n pixels (1 - 16383) after first

TR pulse. This register can be used to set the phase

between the TR pulses and the stepper motor pulses.

NOTE: a setting of n = 0 creates the maximum delay

(16384) pixels, which will increase scan time. If this

function is not used, this register should be set to 1.

1B TR to Stepper Phase Correction - LSB nnnnnnnn

Address Function D

0Value

LM9833

14 www.national.com

SENSOR PIXEL CONFIGURAT IO N

1C Optical Black Pixels Start nnnnnnnnn pixels (0 - 255)

1D Optical Black Pixels End nnnnnnnnn pixels (0 - 255)

1E Active Pixels Start - MSB nnnnnnn pixels (0 - 16383)

Set to the same value as register D a ta Pi xel s Sta rt.

1F Active Pixels Start - LS B nnnnnnnn

20 Line End - MSB nnnnnnn pixels (0 - 16383)

This selects the pixel count at which the current line is

ended and the next line begins. This determines the

integration time of one line.

21 Line End - LSB nnnnnnnn

PIXEL DATA RANGE TO PROCESS

22 Data Pixels Start - MSB nnnnnnn pixels (A cti ve Pi xel s Sta rt - 16383)

This selects the start of the range of pixels transmitted

to the PC and determines the pixel location where

offset and shading cor rect ion beg ins (pix el 0 in the

DataPort). This value must be >= Active Pixels Start

23 Data Pixels Start - LSB nnnnnnnn

24 Data Pixels End - MSB nnnnnnn pixels (Data Pixels Start - [Line End - 20])

This selects the end of the range of pixels transmitted

to the PC. This value must be <= [Line End - 20]

25 Data Pixels End - LSB nnnnnnnn

COLOR MODE SETTINGS

AFE Operation

3 Channel or 1 Channel

0003 Channel Pixel Rate Color

0013 Channel Line Rate Color

1001 Channel Grayscale

1011 Channel Color

1 Channel Grayscale Input Source

(1 Channel Color always uses the

Blue Channel as the input)

0 0 Red Chan ne l

0 1 Green Chan ne l

1 0 Blue Channel

11 N/A

TRRED (=TR1) position

(3 Channel Line Rate Mode only) 0 1st TR pulse position (inside Ø1 high)

1 2nd TR pulse position (inside Ø1 low)

TRGREEN (=TR2) position

(3 Channel Line Rate Mode only) 0 1st TR pulse position (inside Ø1 high)

1 2nd TR pulse position (inside Ø1 low)

TRBLUE (=CP2) position

(3 Channel Line Rate Mode only) 0 1st TR pulse position (inside Ø1 high)

1 2nd TR pulse position (inside Ø1 low)

3 Channel Line Rate TRRED drop

(3 Channel Line Rate Mode only)

0 0 Do not drop any TRRED pulses

01Drop 1 TR

RED pulse (double integration time)

10Drop 2 TR

RED pulses (triple integration time)

11N/A

3 Channel Line Rate TRGREEN dr op

(3 Channel Line Rate Mode only)

0 0 Do not drop any TR GREEN pulses

0 1 Drop 1 TRGREEN pulse (double integration time)

1 0 Drop 2 TRGREEN pulses (triple integration time)

11 N/A

3 Channel Line Rate TRBLUE drop

(3 Channel Line Rate Mode only)

0 0 Do not drop any TRBLUE pulses

0 1 Drop 1 TRBLUE pulse (double integration time)

1 0 Drop 2 TRBLUE pulses (triple integration time)

11 N/A

Triple TR output 0 Normal operation

1 Outputs single TR pulse on TR1, TR2, and CP2 pins

RESERVED

28 Reserved 00000000Write 00 to this register

Address Function D

0Value

LM9833

15 www.national.com

ILLUMINATION SETTINGS

Illumination Mode

Cont ro ls t h e fu nc t io n of t he 3 L A M P o ut put s :

LAMPR, LAMP G, and LAMPB

Mode 0 is the Off/Reset state.

Mode 1 is typically used for CCFL lamps.

Mode 2 is for color scanning with tri-color

LEDs.

Mode 3 is for grayscale scanning with tri-

color LEDs.

00LAMPR = LAMPG = LAMPB = 0V

(Power-On/Reset Default)

Illumination Mode 1 - LAMPR and LA MPB turn on

every line, with their on and off points controlled by

the Pixel Counter settings. LAMPG Output is

continuous PWM pulse stream. (Figure 20)

LAMPR and/or LAMPB may be set to stay on or off at

all times by setting the LAMP Off or LAMP On settings

(registers 2C-37) greater than the L ine End value

(registers 20 and 21).

Illumination Mode 2 - LAMPR, LAMPG, LAMPB turn on

sequentially at the line rate, with their on and off

points controlled by Pixel Counter settings. (Figure

21)

11Illumination Mode 3 - LAMPR, LAMPG, LAMPB turn on

every line, with their on and off points controlled by

the Pixel Counter settings. (Figures 22 and 23)

LAMPB for INT IME ADJ 0LAMP

B operates normally

1LAMPB outp ut is enabled during short integration

time, low during long integration time.

2A LAMPG PWM - MSB (Illumination Mode 1) nnnnLAMP

G output is a PWM pulse stream. Duty cycle is

n/4095. Frequency = 48Mhz/4096 = 11.7kHz2B LAMPG PWM - LSB (Illumination Mode 1) nnnnnnnn

2C LAMPR On - MSB nnnnnnn pixels (1 - 16384)

This selects the pixel count at which the LAMPR

output goes high (if programmed)

2D LAMPR On - LSB nnnnnnnn

2E LAMPR Off - MSB nnnnnnn pixels (1 - 16384)

This selects the pixel count at which the LAMPR

output goes low (if progra mmed)

2F LAMPR Off - LSB nnnnnnnn

30 LAMPG On - MSB nnnnnnn pixels (1 - 16384)

This selects the pixel count at which the LAMPG

output goes high (if programmed)

31 LAMPG On - LSB nnnnnnnn

32 LAMPG Off - MSB nnnnnnn pixels (1 - 16384)

This selects the pixel count at which the LAMPG

output goes low (if progra mmed)

33 LAMPG Off - LSB nnnnnnnn

34 LAMPB On - MSB nnnnnnn pixels (1 - 16384)

This selects the pixel count at which the LAMPB

output goes high (if programmed)

35 LAMPB On - LSB nnnnnnnn

36 LAMPB Off - MSB nnnnnnn pixels (1 - 16384)

This selects the pixel count at which the LAMPB

output goes low (if progra mmed)

37 LAMPB Off - LSB nnnnnnnn

STATIC OFFSET AND GAIN SETTINGS FOR ANALOG FRONT END

38 Static Offset (Red) 0nnnnnOffset = +n*9.3mV, n = 0 to 31

1nnnnnOffset = -n*9.3mV, n = 0 to 31

39 Static Offset (Green) 0nnnnnOffset = +n*9.3mV, n = 0 to 31

1nnnnnOffset = -n*9.3mV, n = 0 to 31

3A Static Offset (Blue) 0nnnnnOffset = +n*9.3mV, n = 0 to 31

1nnnnnOffset = -n*9.3mV, n = 0 to 31

3B Static Gain (Red) 0nnnnnGain = 0.93 + 0.067*n (V/V), n = 0 to 31

1nnnnnGain = 3(0.93 + 0.067*n) (V/V), n = 0 to 31

3C Static Gain (Green) 0nnnnnGain = 0.93 + 0.067*n (V/V), n = 0 to 31

1nnnnnGain = 3(0.93 + 0.067*n) (V/V), n = 0 to 31

3D Static Gain (Blue) 0nnnnnGain = 0.93 + 0.067*n (V/V), n = 0 to 31

1nnnnnGain = 3(0.93 + 0.067*n) (V/V), n = 0 to 31

Address Function D

0Value

LM9833

16 www.national.com

DIGITAL PIXEL RATE OFFSET AND GAIN SETTINGS

3E Fixed Offset Coefficient - MSB nnnnnnnnFixed Offs et to use for calibration

3F Fixed Offset Coefficient - LSB nnnnnnnn

40 Fixed Mu ltip lie r Coeffi cie nt - MSB nnnnnnnnFixed Gain to use for calibration

41 Fixed Mu ltip lie r Coeffi cie nt - LSB nnnnnnnn

DIGITAL PIXEL RATE OFFSET AND GAIN/DRAM SETTINGS

Shading Multiplier 0 Gain = [Multiplier Coefficent]/16384

1 Bypass Multiplier

Multiplier Coefficient Source 0 Configuration Register 40 and 41 (Fixed)

1 External DRAM

Offset Coefficient Source 0 Configuration Register 3 E and 3F (Fixed)

1 External DRAM

Reserved 1 0 Set to 10

DRAM Size 0 256k x 16

11M x 16

Address Function D

0Value

LM9833

17 www.national.com

STEPPER MOTOR CONTROL SETTINGS

43 n (Line Skipping)

Part of the “n out of m” function, consisting of

registers 43, 44, and 54 (bits 3-7). tttttttt

n lines saved in DRAM for every m lines (register 44)

scanned, function bypassed if register value = 0.

n (lines saved per m lines scanned) = 256 - t

t = 256 - n

If t = 0 then function is bypassed.

44 m (Line Skipping)

Part of the “n out of m” function, consisting of

registers 43, 44, and 54 (bits 3-7). mmmmmmmmn lines (register 43) saved in DRAM for every m lines

scanned. m = 1 to 255.

If m = 0 then function is bypassed.

Full/Microstepping 0 Full Step Mo de

1 Microstepping Mode

Current Sensing Phases

= 0 for fullstepping

= 1 for micr ostepping

01 Phase - No microstepping, just kickstart/stop

functions

1 2 Phases - necessary for microstepping

Stepper Motor Phase A Polarity

0Positive (A/B/A/B Output high = winding energized)

Negative (A/B/A/B output low = winding energized )

WARNING: When idle, this setting leaves the motor

energized for unipolar motors, and will destroy bipolar

motor drivers. Keep this bit set to a 0.

Stepper Motor Phase B Polarity

0Positive (A/B/A/B Output high = winding energized)

Negative (A/B/A/B output low = winding energized )

WARNING: When idle, this setting leaves the motor

energized for unipolar motors, and will destroy bipolar

motor drivers. Keep this bit set to a 0.

A, B, A, and B stepper motor status 0A, B, A, and B output pins in Tri-Sta te

1A, B, A

, and B outp ut pins active

Swap A/A with B/B

(Reverses motor direction ) 0 Default polarity

1 Reverse Polarity

Fullstep During FastFeed at Start of Scan 0 Traditional Operation

1 Fullstep during fastfeed at start of scan

46 Scanning Step Size - MSB nnnnnnnnThe step size of one microstep while scanning, in

units of pixel periods (minimu m 2)47 Scanning Step Siz e - LSB nnnnnnnn

48 Fast Feed Step Size - MSB nnnnnnThe step size of one microstep while fast feeding, in

units of pixel periods (minimu m 2)49 Fast Feed Step Size - LSB nnnnnnnn

4A Fullsteps to Skip at Start of Scan - MSB nnnnnnnWhen scan starts, paper is fed forward n full steps (0 -

32767) at highest speed. For “zooming” in flatbeds4B Fullsteps to Skip at Start of Scan - LSB nnnnnnnn

4C Step Counter - MSB nnnnnnCounts n (0-16383) full steps. See register 58, bit 5

for more in for ma tion.4D Step Counter - LSB nnnnnnnn

4E Pause scanning, stop/reverse motor nnnnnnnnPause scan when buffer is n*2 (16 x 256k) or

n*8 (16x1M) kby tes full

4F Resume scanning, start motor nnnnnnnnResume scan when buffer is n*2 (16 x 256k) or

n*8 (16x1M) kby tes full

50 Full steps to reverse when buffer is full nnnnnnnnn (0-255) full steps (0 = do not reverse)

Acceleration Profile (stopped) n n n (0,1 , 2, or 8) ful l st ep t ime un i ts pa use w hil e s top pe d

Acceleration Profile (25%) n n n (0,1, 2, or 8) full steps at 25% speed

Acceleration Profile (50%) n n n (0,1, 2, or 8) full steps at 50% spee d

Default Phase Difference - High Byte n n 18 bit word used to calculate when motor resumes

after reversing and stopping. 1 < n < 262143. 2 bits in

52 Defau lt Pha se Diff er en ce - Mid B yte nnnnnnnn

53 Default Phase Difference - Low Byte nnnnnnnn

Lines to Process After Pause/

Lines to Disc ar d aft er Resum e nnnn (0-7) lines. This only applies if the motor doesn’t

reverse (reverse steps = 0)

Line Sk ipping Phase

Part of the “n out of m” function, consisting of

registers 43, 44, and 54 (bits 3-7).

0 Red sensor data arrives before Green sensor

1 Blue sensor data arrives before Green sensor

Line Sk ipping Color Phase Delay

Part of the “n out of m” function, consisting of

registers 43, 44, and 54 (bits 3-7). n n n n n lines, n = 0-15

Address Function D

0Value

LM9833

18 www.national.com

55 Kicks tar t ste ps (fullstepping mode) nnnMotor gets maximum current for first n (0-7) full steps

Hold Current Timeout nnnnn Full step time units (1-31) (do not set to 0)

56 Stepper Moto r PWM Frequency nnnnnnnn=CRYSTAL OUT/(256*n) (0 < n < 256)

=CRYSTAL OUT/(256*256) (n = 0)

57 Stepper Motor PWM Set Duty Cyc le nnnnnn= minimum of n/64 (default = 0)

PAPER SENSE SETTINGS

PAPER SENSE 1: Polarity 0 A low input on PAPER SENSE 1 is True

1 A high input on PAPER SENSE 1 is True

PAPER SENSE 1: Level /Edge sensitive

0Level sensitive: PAPER SENSE 1 State bit (in Status

True.

1Edge sensitive: PAPER SENSE 1 State bit (in Status

True since the last time the Status Register was read.

PAPER SENSE 1: Stop Scan, High Speed

Forward, and High Speed Re verse

Use this input for the home sensor in flatbed

scanners.

0Transitions on PAPER SENSE 1 will not clear the

command register.

1A False-to-Tru e transiti on on PAPER SENSE 1 will

clear the Command Register and stop the scan.

PAPER SENSE 2: Polarity 0 A low input on PAPER SENSE 2 is True

1 A high input on PAPER SENSE 2 is True

PAPER SENSE 2: Level /Edge sensitive

0Level sensitive: PAPER SENSE 2 State bit (in Status

True.

1Edge sensitive: PAPER SENSE 2 State bit (in Status

True since the last time the Status Register was read.

PAPER SENSE 2: Stop Scan an d High

Speed Forward

The scan will automatically stop after scanning for the

number of fullsteps specified in the Step Counter

(registers 4C and 4D). (The full steps moved dur ing

the “FastFeed At Start of scan period are not

counted.) If the value in the Step Counter is 0, the

scan can only be stopped by writing a 0 to register 07.

A False-to-Tru e transiti on on PAPER SENSE 2 will

stop a scan or a High Speed Forward command after

the number of fullsteps specified in the Step Counter

(registers 4C and 4D). It will not stop a High Speed

Reverse, and therefore should not be used as a home

position sensor input.

Address Function D

0Value

LM9833

19 www.national.com

MISC I/O PIN SETTINGS

MISC I/O 1: Input or Output 0 The MISC I/O 1 pin is configured as an input.

1 The MISC I/O 1 pin is configured as an output.

MISC I/O 1: Polarity

(if configured as an input) 0 A low input on MISC I/O 1 is True

1 A high input on MISC I/O 1 is True

MISC I/O 1: Level/Edge sensitive

(if configured as an input)

0Level sensitive: MISC I/ O 1 State bit (in Status

1Edge sensitive: MISC I/O 1 State bit (in Status

since the last time the Status Register was read.

MISC I/O 1: Output State

(if configured as an output)

Power On/USB Suspend Default: Input

0The output of the MISC I/O 1 pin will be a logic low

(0V).

1The output of the MISC I/O 1 pin will be a logic high

(5V).

MISC I/O 2: Input or Output 0 The MISC I/O 2 pin is configured as an input.

1 The MISC I/O 2 pin is configured as an output.

MISC I/O 2: Polarity

(if configured as an input) 0 A low input on MISC I/O 2 is True

1 A high input on MISC I/O 2 is T r ue

MISC I/O 2: Level/Edge sensitive

(if configured as an input)

0Level sensitive: MISC I/ O 2 State bit (in Status

1Edge sensitive: MISC I/O 2 State bit (in Status

since the last time the Status Register was read.

MISC I/O 2: Output State

(if configured as an output)

Power On/USB Suspend Default: Input

0The output of the MISC I/O 2 pin will be a logic low

(0V).

1The output of the MISC I/O 2 pin will be a logic high

(5V).

(NEW)

MISC I/O 3: Input or Output 0 The MISC I/O 3 pin is configured as an input.

1 The MISC I/O 3 pin is configured as an output.

MISC I/O 3: Polarity

(if configured as an input) 0 A low input on MISC I/O 3 is True

1 A high input on MISC I/O 3 is True

MISC I/O 3: Level/Edge sensitive

(if configured as an input)

0Level sensitive: MISC I/ O 3 State bit (in Status

1Edge sensitive: MISC I/O 3 State bit (in Status

since the last time the Status Register was read.

MISC I/O 3: Output State

(if configured as an output)

Power On/USB Suspend Default: Input

0The output of the MISC I/O 3 pin will be a logic low

(0V).

1The output of the MISC I/O 3 pin will be a logic high

(5V).

MISC I/O 4: Input or Output 0 The MISC I/O 4 pin is configured as an input.

1 The MISC I/O 4 pin is configured as an output.

MISC I/O 4: Polarity

(if configured as an input) 0 A low input on MISC I/O 4 is True

1 A high input on MISC I/O 4 is T r ue

MISC I/O 4: Level/Edge sensitive

(if configured as an input)

0Level sensitive: MISC I/ O 4 State bit (in Status

1Edge sensitive: MISC I/O 4 State bit (in Status

since the last time the Status Register was read.

MISC I/O 4: Output State

(if configured as an output)

Power On/USB Suspend Default: Output,

Logic High

0The output of the MISC I/O 4 pin will be a logic low

(0V).

1The output of the MISC I/O 4 pin will be a logic high

(5V).

Address Function D

0Value

LM9833

20 www.national.com

(NEW)

MISC I/O 5: Input or Output 0 The MISC I/O 5 pin is configured as an input.

1 The MISC I/O 5 pin is configured as an output.

MISC I/O 5: Polarity

(if configured as an input) 0 A low input on MISC I/O 5 is True

1 A high input on MISC I/O 5 is True

MISC I/O 5: Level/Edge sensitive

(if configured as an input)

0Level sensitive: MISC I/ O 5 State bit (in Status

1Edge sensitive: MISC I/O 5 State bit (in Status

since the last time the Status Register was read.

MISC I/O 5: Output State

(if configured as an output)

Power On/USB Suspend Default: Output,

Logic High

0The output of the MISC I/O 5 pin will be a logic low

(0V).

1The output of the MISC I/O 5 pin will be a logic high

(5V).

MISC I/O 6: Input or Output 0 The MISC I/O 6 pin is configured as an input.

1 The MISC I/O 6 pin is configured as an output.

MISC I/O 6: Polarity

(if configured as an input) 0 A low input on MISC I/O 6 is True

1 A high input on MISC I/O 6 is T r ue

MISC I/O 6: Level/Edge sensitive

(if configured as an input)

0Level sensitive: MISC I/ O 6 State bit (in Status

1Edge sensitive: MISC I/O 6 State bit (in Status

since the last time the Status Register was read.

MISC I/O 6: Output State

(if configured as an output)

Power On/USB Suspend Default: Output,

Logic Low

0The output of the MISC I/O 6 pin will be a logic low

(0V).

1The output of the MISC I/O 6 pin will be a logic high

(5V).

TEST MODE SETTINGS

5C ADC Output Code - MSB nnnnnnnnUsed to force the input to the HDPI Divider to a known

value for digital tests5D ADC Output Code - LSB nnnnnnnn

ADC Test Mode

0 0 Normal Operation

0 1 Bypass AFE, Normal ADC Operation

10Bypa ss AFE, bypass ADC digital correction,

output uncorrected ADC MSB

11Bypa ss AFE, bypass ADC digital correction,

output uncorrected ADC LSB

Pixel Processing Input Select

0 0 Normal Operation - ADC Output

0 1 Registers 5C and 5D

1 0 16 bit counter, reset at the start of every scan

1 1 16 bit counter, reset at the start of every line

16 bit Counter Increment Select

(16 bit counter starts at 0, increments every

datapixel)

0 0 Increments by 1

0 1 Increments by 4

1 0 Increments by 16

11 N/A

MCLK edge fo r AFE (S et this bit to 0) 0 Rising

1 Falling

CDS Signal 0 Normal Operation

1 CDS signal is output on LAMPB pin

5F-68 Reserved 00000000Write 00 to these registers

69 Version Number 100100 = LM9832 or LM9833

(011 = LM9831, 010 = LM9830)

6A-7F Reserved 00000000Write 00 to these registers

Address Function D

0Value

LM9833

21 www.national.com

Applications Information

1.0 OVERVIEW

The LM983 3 is a USB, 1200d pi, 16 bit (4 8 bit color) scanne r-on-

a-chip. The LM9833 is an improved, 16 bit version of the

LM9831, pr ovidi n g all o f the L M9 831 ’s funct io na lity w h ile i mpr ov-

ing performance and adding several new features. See 12.0

CHANGES FROM THE LM9831 for a complete list of additions

and enhancements.

2.0 ANALOG SIGNAL PROCESSING

One channel of the LM9833’s analog front end is shown in Figure

3. The gain through each channel can be set between 0.93V/V

and 9.0V/ V using reg isters 3B, 3 C, and 3D. The offset DAC p ro-

vides up to ±278mV of offset correction using registers 38, 39,

and 3A. T he offset DA C an d ga i n s tage s sh ould be adjusted d ur-

ing coarse calibration so that the input signal is a maximum of

1.9Vp-p at the ADC input.

3.0 DIGITAL SIGNAL PROCESSING

3.1 ADC

The digital pixel data comes from a 6MHz 16 bit pipelined ADC.

3.2 Pixel Processing Block

The Pixel P roce ssing stag e is used to digit ally redu ce t he optica l

resolution of the sensor. The optical resolution can be reduced by

a factor of 1, 1.5, 2, 3, 4, 6 , 8, o r 1 2. F or a 12 00 d pi (optica l ) sys-

tem, this would pr oduce res olutions o f 1200 , 800, 6 00, 40 0, 300 ,

200, 150, and 100 . A 600 dpi (optical) system would be cap able

of 600, 400, 300, 200, 150, 100, 75, and 50 dpi. (Resolution in the

vertical direction is controlled by the stepper motor speed.)

Horizontal resolution reduction is accomplished by averaging

adjacent pixels. Averaging produces better image quality and

reduces aliasing versus the traditional technique of simply dis-

carding pixels to r educe resolution. For example, to get 100 dpi

from a 300dpi optical sensor, you would average 3 300dpi pixels:

The nu mb er of pixels coming o ut of the P ixel Processing blo ck i s

equal to the integer portion of the number of pixels going in to the

Pixel Processing block divided by the “Divide By” setting, from the

table show n in F igure 4.

This equation also applies to the divide by 1.5 function.

If there are not enough pi xels at the end of a li ne to form a com-

plete pixel, th e last pixel will be eliminated. F or example, if a line

is 35 pixels wide and the Ho rizon tal DPI setting i s set to divide by

6, then the output of the Pixel Processing block will be 5 pixels

(the integer portion of 35/6). The last 5 pixels will be discarded,

since 6 pixels would be required to form a new pixel in this mode.

The output of this stage is sent to the Pixel Rate Offset Correction

Block.

3.3 Pixel Rate Offset Correction Block

Offset correction words for every pixel of the CCD are stored in

Figure 3: Analog Front End (AFE) Model

VDAC

DAC

Offset

GPGA

++16 Bit

ADC

++++

VOS3

VOS2

ΣDOUT

VOS1

VIN Σ

Gain Boost

1V/V or

3V/V

PGA

0.9 3 V/V to

3V/V

DOUT = (((VIN + VOS1)GB + VDAC + VOS2)GPGA + VOS3)C

simplified, with all offsets = 0, this is:

DOUT = (VINGB + VDAC)GPGAC

C is a const ant that co mbines the gain erro r throu gh the AF E, refere nce vol tage var iance, and anal og voltage

to digital code conversion into one constant. Ideally, C = 32768 codes/V.

Manufacturing tolerances widen the range of C. See Electrical Specifications.

Divide

DPI

(1200

DPI

system)

DPI

(800

DPI

system)

DPI

(600

DPI

system)

DPI

(300

DPI

system)

1 1200 800 600 300

1.5 800 533 400 200

2 600 400 300 150

3 400 267 200 100

4 300 200 150 75

6 200 133 100 50

8 150 100 75 37.5

12 100 67 50 25

Figure 4: Decr ea sing Horizo nta l Resolutio n

pixel100dpi pn-2 pn-1 pn

--------------------------------------------=

PixelsOUT INT PixelsIN

Divide By

-------------------------





LM9833

22 www.national.com

the external DRAM and acce ssed at the pixel rate. A digital sub-

tractor subtracts the 16 bit offset word (corresponding to that

pixel’s offset error) from each pix el.

The subtractor saturates at 0, i.e. if the coefficient to be sub-

tracted is greater than the ADC output code, the result is an out-

put of 0.

The offset words stored in DRAM are typically calculated by

scanning a black calibration strip at 16 bits, and storing the

results in the DRAM using the DataPort.

The offset correcti on equ atio n is:

3.4 Pixel Rate Gain Correction Block

This is a digital m ultiplier that m ultiplies the outp ut word from the

subtrac tor by a 16 bit digi tal correction coefficient corres ponding

to that pixel’s gain error. The coefficients a re stored i n the ext er-

nal RAM and accessed at the pixel rate.

The mult iplier saturate s at 65535, i.e. if th e result of the mul tipli-

cation is greater than 65535, the multiplier output is 65535.

The gain equation is:

Not e t h at a c o effic i en t of 0 r ep r es ent s a g ain of 0. O n the LM 98 3 0

and prev ious parts, a coefficient of 0 represen ted a gain o f 1. To

achieve a gain of 1, the coefficient should be set to 16384.

3.5 Gamma Correction Tables

There are 3 gamma lookup tables for R, G, and B. The input to

the tabl e is the 12 MSBs ( most sign ifican t bit s) of th e 16 b it pixel

data comi ng from the previous st age (3.4 Pixe l Rate Gain Cor-

rection Block). The output is the 8 bit gamma corrected pixel

data. The tables consume 12k words (4K bytes x 16 bits, only the

8 LSBs of each word is used) of the external DRAM. Each

gamma tab le (r ed, gre en, an d blue) c an b e loaded with a ny arbi -

trary user-defined transfer curve.

The gamm a tabl es are loa ded thr ough th e datapo rt (see 6.1 The

DataPort: Reading and Writing to Gamma, Offset, and Gain

Memory). The DataPort selects which color (Red, Green or Blue)

gamma table will be read from or written to.

3.6 Pixel Packing/Thresholding Block

Some scans require only one bit per pixel (“line art” mode), others

may need only 2 or 4 bits/ pixel. To increase scanning speed for

lower pixel dept hs, the LM9833 packs th e desir ed MSBs of multi-

ple pixels together into 1 16 bit word, increasing the transmission

speed to the host by a factor of 2, 4, 8, or 16. Figure 6 shows how

the pix els are packed together f or 8, 4, 2, an d 1 bit pixe l depths.

In Figure 6, “b” indicates the bit position (b7 = the most significant

and b0 = the least significant bit) of the original 8 bit pixel data,

and pn indicates the original pixel sequence, i.e p0, p1, p2, p3...

If there are not enough unpacked pixels at the end of a line to

complete the pa cked wor d for t ransmissio n, that fina l word is not

sent. For example, doing an 8 bit pixel rate scan with a HDPI

divider of 1 and an odd number of pixels will truncate the blue

component of the last pixel.

The gamma table in 3.5 Gamma Correction Tables allows the

user to se t the threshold o f each transiti on for various li ne art or

reduced pixel depth modes.

3.7 16 Bit Output Mode

The LM 98 3 3 als o s upp or t s a 16 b i t o ut m o de . Th i s c a n be u sed t o

get very a ccurate data for calibration o r to scan a 16 gray/4 8 bit

color im age. This mode is set through regist er 9, bit 5. In the 16

bit output mode, the gamma and pixel packing stages are

bypa ssed, and the 16 bit da ta from the ADC is store d in DRAM,

formatted as shown in Figure 7.

The memory reserved for the gamma table is used to store image

data in the 16 bit mode. After scanning in 16 bit mode, the

gamma table must be reloaded for operation in 8, 4, 2, or 1 bit

mode.

3.8 Line Buf fer

The li ne buffer uses the external DRA M as a FIFO l ine buffer to

store the p ixel data (whi ch is generated at a fixe d rate, synchro-

nous to the CC D clocks) and send it back to the PC at an as yn-

chronous, unpredictable, and non-constant rate.

The LM9833 supports 2 sizes of DRAM, 256k x 16bit and 1M x

16bit. 216kbytes (108kwords) of the capacity of the DRAM is con-

PixelOUT PixelIN coefficient

–

PixelOUT PixelIN coefficient

16384

---------------------------

⋅

12MSBs of 16 bit Output

8 Bit Pixel Out

255

04095

Figure 5: Gamma Tabl e

Pixel

Depth bit

15 bit

14 bit

13 bit

12 bit

11 bit

10 bit

9bit

8b7 p

0b6 p0b5 p0b4 p0b3 p0b2 p0b1 p0b0 p0

4b7 p

0b6 p0b5 p0b4 p0b7 p1b6 p1b5 p1b4 p1

2b7 p

0b6 p0b7 p1b6 p1b7 p2b6 p2b7 p3b6 p3

1b7 p

0b7 p1b7 p2b7 p3b7 p4b7 p5b7 p6b7 p7

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

8b7 p

1b6 p1b5 p1b4 p1b3 p1b2 p1b1 p1b0 p1

4b7 p

2b6 p2b5 p2b4 p2b7 p3b6 p3b5 p3b4 p3

2b7 p

4b6 p4b7 p5b6 p5b7 p6b6 p6b7 p7b6 p7

1b7 p

8b7 p9b7 p10b7 p11b7 p12b7 p13b7 p14b7 p15

Figure 6: Packing Multiple Pixels Into One Word

MSB 151413121110 9 8

b15 b14 b13 b12 b11 b10 b9 b8

LSB76543210

b7 b6 b5 b4 b3 b2 b1 b0

Figure 7: 16 Bit Output Mode Data Format

Applications Information (Continued)

LM9833

23 www.national.com

sumed by the offset and shading coefficients and the gamma

tables. T hat leaves 296kbyte s of memo ry avai lable for line bu ffer

when using a 256k x 16 bit DRAM, or 1832kbytes of memory

when using a 1M x 16 bit DRAM.

The line buffer is tightly co upled to the st epper motor (4.0 Step-

per Mo tor Con trol ler ), and is res ponsible for stoppi ng the motor

before the buffer overflows and starting the motor again as the

buffer nears emp ty.

If the scanner is generating pixel data faster than the PC can

acquire it, the line buffer will start to fill up. As the buffer nears

100% of its capacity, the scan must be paused before it starts

acquiring a line which will overflow the buffer . This Pause Thresh-

old limit (register 4E) is programmable in 2 kbyte (256k x 16 bit

DRAM) or 8kbyte (1M x 16 bit DRAM ) incre me nts be twee n 0 and

255.

To maximize scanner perfo rmance and min imize pausing d ue to

buffer full conditions, the pause threshold should be set using this

formula:

Pause Threshold (kB) = Available_Memory - (Line_Length + 1)

where Available_Memory = 296kbytes (256k x 16b DRAM) or

1832kbytes (1M x 16 bit DRAM),

Line_Length = (Bytes/Line)/1024

Where C = 1 for “1 Channel Grayscale”, 3 for all other modes,

Data_Pixels = Data Pixels End (registers 24, 25) - Data Pixels

Start (registers 22, 23)

HDPI_Divider = Horizontal DPI divider = 1, 1.5, 2, 3, 4, 6, 8, or 12

B = Bits per Pixel = 16 (16 bit mode), 8, 4, 2, or 1

or Pause Threshold (kB)/8 (1M x 16 DRAM)

When the Pause Threshold is reached the buffer sends a com-

mand to the stepper motor controller to stop scanning. The

remainder of the line being processed will continue being pro-

cessed and be sent to the buffer. If the Lines To Process After

Pause Scan Signal register (register 54) is greater than 0, then

room for these ad dition al lines nee ds to be added into the Pause

Threshol d value calc ulatio n.

Note that the sc anner softw are on th e host PC must s et a Pause

Threshol d value low enough to ensure that any d ata that comes

after a pause re quest (th e rest of t he current l ine and any sub se-

quent lines if register 54 bits 0-2 are greater than 0) will fit into the

DRAM buffer. If the Pause Threshold is set too high, the Line

Buffer may overflow, creating discontinuities in the scanned

image.

After a pause, the buffer will continue to transm it data to the PC

until it hits the Resume Threshold limit (register 4F), which is also

programm able in 2 kbyt e (256k x 16 bit D RAM) or 8kby te (1M x

16 bit DRAM) increments between 0 and 255. When the Resume

Threshold is reached, the Line Buffer sends the motor controller a

command to res ume.

4.0 Stepper Motor Controller

The stepper motor controller sends a series of pulses to the step-

per motor to move the paper past the sensor (sheetfed) or the

sensor past the paper (flatbed). The speed at which the paper

moves re lative to the sen sor, combined wi th the integ ration time

of the image sensor, determines the effective vertical resolution

(Lines Per Inch, or LPI).

The ste ppe r m oto r i s mo ved for w ard s a nd back w ard s by two sig-

nals, A and B, 90° out of phase with each other. The phase for

the forward direction is set in Configuration Register 45.

The A a nd B signals ar e either squ arewaves (in F ull Step Mode,

Figure 8), or a staircase approximation of a sine wave (in

Microstep mode, Figures 10 and 11).

The LM9833 always counts stepper motor steps in units of

microsteps. A full step is equal to four microsteps. Even when the

LM9833 is in Full Step Mode, it is counting in microsteps, and will

increment the stepper motor (generating a full step) every four

microsteps.

The microstep Step Size is defined in units of time. These units of

time are pi xel periods, as de fined in the hor izontal pixel coun ter.

In the 3 Channel Pixel Rate input mode, the pixel period is the

fADC/3 (= fMCLK/24). In the 3 Channel Line Rate and 1 channel

modes, the pixel period is equal to fADC (= fMCLK/8). The Step

Size is stored in the Scanning Step Size configuration register

as a 14 bit value. During normal operation, the stepper motor is

advanced 1 microstep every Step Size pixel periods. The LPI can

be calculated as follows:

Where FSPI = the number of full steps required to move the

image one inch, p ixels/li ne is the nu mber of pixel pe riods it takes

to scan one horizonta l line (equi valent to the value stored in the

Line End registers), StepSize is the number of pixel peri-

ods/microstep, and X = 3 for line rate and 1 for pixel rate modes.

Whenever the stepper motor has been moving and then comes to

a stop, the LM9 833 waits for the time specified in the Hold Cur-

rent Timeout re gi ste r a nd th en de -asserts th e A, B , A, a nd B out-

puts to cut power to the motor. When the stepper motor is not

scanning or fast-feeding (Command = 00), A, B, A, and B are de-

asserted in all stepper modes.

There are two modes of stepper motor operation: fullstepping and

microstepping.

4.1 Full Step Mode

In Full S tep Mode th e output is a pul se stream, as sh own in Fig-

ure 8. The amplitude of the pulses is controlled by the output of

Bytes/Line 2 INT

⋅INT Data Pixels

HDPI_Divider

------------------------------------





CB⋅⋅

------------------------------------------------------------------------







Figure 8: Stepper Motor Waveform - Full Stepping

1 full step = 4

microsteps

LPI 4FSPI StepSize

pixels/line X

⋅

------------------------------------=

Applicati ons Information (Continued)

LM9833

24 www.national.com

the 2 bit DAC, shown in Figure 9.

4.2 Microstep Mode

Microstepping is a technique of driving the stepper motor with a

staircase approximation of a sine wave, as shown in Figure 10.

This technique maximizes the torque of a given motor , resulting in

a higher ma ximum speed. In additio n, it increases the reso lution

of the stepper m otor. If a stepper motor moves 3.6 ° per full step,

microste pping can crea te positions inside the 3.6 °: 1.8°, 0.9° , or

0.45°, fo r example. This increases the maximum vertical resolu-

tion of the scanner. Microstepping also results in quieter motor

movement.

The amplitude of the micro stepp ed sine wave is controlled by the

output of th e stepper motor DAC (Figure 11). The current in the

stepper motor winding is measured as a voltage across the sense

resistor, and the transistor drive signals are pulse width modu-

lated (PWM) to force the average current through the winding

equal t o VDAC/RSENSE. Register 56 co ntrols t he frequency of the

PWM, and Register 57 controls the minimum time the driver is on

every period . Reg ister 57 should be set as sh ort as po ssible , the

driver only needs to be on long enough to mask any transient

noise generated by the driver transistor turning on.

Figure 12 shows the LM9833’s DAC volta ges. The peak current

through the stepper motor winding will be 0.484V/RSENSE. The

table index is incremented every microstep (StepSize pixel pe ri-

ods).

4.3 Pause Behavior - N on-Reversing M o de

When th e Full Steps to Reverse When Buffer is Full register is

0, the steppe r motor si mply stop s moving when the Pause signal

is received, as shown in Figure 13. The line of data currently

being processed (section “a” in Figure 13) will continue to be pro-

cessed and stored in DRAM. Additional lines may be digitized

and st ore d as wel l, de pending on th e nu mb er p ro gra mm ed i n the

Lines to Process After Pause Scan Signal register (Figure 14).

This value is different for different scanner designs and should be

empirically set to the value that minimizes the spatial distortion

created by the motor slowing dow n and stop ping .

Scan Mode DAC Voltage

Starting from

a dead stop

0.484V for number of steps specified

in Kickstart Steps register (0-7). If

current-movement begins at 0.347V.

Scanning 0.347V

Stopped 0.133V for number of steps specified

in Hold Current Timeout register (1 -

31), 0V after time out.

Figure 9: Full Step Current Control

Figure 10: Bipolar Microstepping Waveform

1 microstep

Table

Index A (B) A (B)DAC

Voltage

000N/A

1100.195V

2100.347V

3100.448V

4100.484V

-0 0 0 N/A

-1 0 1 0.195V

-2 0 1 0.347V

-3 0 1 0.448V

-4 0 1 0.484V

Figure 12: Microstepping Current Control

Figure 11: Stepper Motor Waveform - LM9833 Signals

DAC A

DAC B

Figure 13: Stepper Motor Stopping

Microstep

Pulse

Pause

Scanning

Signal

abcd

Applicati ons Information (Continued)

LM9833

25 www.national.com

When the Resume Scan signal is received, the stepper motor

controlle r waits the appr opriate n umber of pixel p eriods aft er the

next TR pulse and th en starts st epping aga in at th e normal r ate.

The first ne w line transm itted is determi ned by the Lines to Dis-

card After Resume Scan Signal register. The discard value

must be the same as the value in the Lines to Process After

Pause Scan Signal regi ster.

4.4 Pause Behavi or - Reve rsin g Mo de

If the F ull Ste ps to Reve rse When Buffe r is Fu ll register is >0,

then the Reversing Mode is enabled.

The Reversing Mode eliminates spatial distortion due to the

pausing of a scan. Wh en the Pause Scan sign al is rece ived, the

line currently being processed is completed and stored in RAM

(line “b” in Figure 17). When the scan resumes, ideally the

LM9833 w ould send out line s “c” and af ter unde r the exact same

speed and positional conditions the scanner was in before the

scan paused (as indicated by the dotted line in Figure 17).

When the Pau se Scan si gnal is received , the LM9 833 pro cesses

the remainder of the line currently b eing read from the CCD (line

b), and stores the offset (in pixel periods) between the last TR

pulse and the l ast step. It then stop s, reverses, stops, a nd waits

for the Resume Scan signal. Once Resume Scan is asserted, the

motor contr oller waits for the previously stored number of pixels

periods , then starts moving f orward ag ain, maintai ning the sa me

phase rel ationship betw een the TR pulse and t he stepper mo tor

control signals. The result is as if the stepper motor had never

paused.

Stopping, reversing, and resuming forward motion all follow the

curv e pr og r am me d in th e Acceleration Profile configuration reg-

ister. There are 3 segments (Stopped, 25%, and 50%), and the

number in e ach register ind i cates the nu mb er o f fu ll step s to stay

at that acceleratio n. A va l ue o f 0 in dicat es th at th at segment i s to

be sk ippe d. For e xam pl e, a v al ue of 0 in a ll thr ee re gi ste rs wo ul d

mean that the motor would instantly reverse when the buffer is

full, then instantly sto p after going back t he specified number of

lines.

This acceleration profile is used any time the motor is started,

stopped, or reversed.

The acceleration profile for stopping, reversing, stopping, and

going forward again is this:

• Full speed forward (1 microstep = #pixels in Scanning Step

Size register) unt il the Pause Scanning signal is received.

• 50% sp eed forwar d for z ful l steps (1 microstep = 2* #pix els in

Fa st Feed Step Size register)

• 25% speed forward for y full steps (1 microstep = 4*#pixels in

Fa st Feed Step Size register)

• Stopped for x full steps (1 microstep = #pixels in Fast Feed

Step Size regi ster ).

• 25% speed backward for y full steps (1 microstep = 4*#pixels in

Fa st Feed Step Size register)

• 50% speed backward for z full steps (1 microstep = 2* #pixels in

Fa st Feed Step Size register)

• Full speed backw ard (1 micr ostep = # pixels i n Fast Feed Step

Size register) for number of microsteps in the Steps to

Reverse register

• 50% speed backward for z full steps (1 microstep = 2* #pixels in

Fa st Feed Step Size register)

• 25% speed backward for y full steps (1 microstep = 4*#pixels in

Value Additional Lines to Store in DRAM

00(a only)

1 1 (a and b)

2 2 (a, b and c)

... ...

Figure 14: Lines to Process after Pause Scan Signal Register

Value First Line to Transmit After Pause

... ...

Figure 15: Lines to Discard After Resume Scan Signal

Figure 16: Stepper Motor Resuming

Microstep

Pulse Resume

Scanning

Signal

abcd

Speed

Stopped

(x = 0 to 3) x = number of full step clocks to wait

before reversing motor.

25%

(y = 0 to 3)

y = nu mber of ful l st eps at 25% of fi nal

speed. Full step period = 4 full step

clocks.

50%

(z = 0 to 3)

z = nu mber of ful l st eps at 50% of fi nal

speed. Full step period = 2 full step

clocks.

Figure 18: Acceleration Profile Settings

Figure 17: Reversing - The Goal

Microstep

Pulse

Pause

Scanning

Signal

abcd

Microstep Pulse

(if motor had not

paused)

Applicati ons Information (Continued)

LM9833

26 www.national.com

Fast Feed Step Size register)

• Paused until a Resume Scan signal is received, whichever

event happ ens firs t. During the hol d curre nt timeo ut period , the

DAC output is held at 0.133V (the hold current) for FullStep

mode, o r the D AC out puts are held as they we re prior to stop-

ping for the microstep mode. After the hold current timeout

period, output drivers A, B, A, and B will be deasserted.

• Wait for Resume Scan signal

• Wait for correct number o f pixel pe riods to res ynchroni ze step-

per motor with sensor timing.

• 25% speed forward for y full steps (1 microstep = 4*#pixels in

Fast Feed Step Size register)

• 50% spee d forward for z full steps (1 mic rostep = 2* #pixels in

Fast Feed Step Size register).

• Full speed forward (1 microstep = #pixels in Scanning Step

Size register), with TR pulses synchronized to sa me the posi-

tion on image that they would have been had scanner not

stopped.

The Line s to Process Af ter Pause Scan Signal /Lines to Dis-

card After Resume Scan Signal register is not used in reversing

mode.

4.5 Fast Feed Step Size Register

When the mo tor is being mov ed quickly (High Speed Forwa rd or

Reverse command or Steps to Skip at Start of Scan register), the

microstep period comes from this register.

For all other m otor movement, the micro step size is given in the

Scanning Step Size register.

4.6 Stepper Motor C urrent Control Usi ng PWM

There is an option to use Pulse Width Modulation of the current in

the stepper motor to increase high speed torque, optimize effi-

ciency, and allow use of a lower current, less expensive motor.

Precisely controlling the current in the motor provides several

benefits. In Full Step Mode, the motor can start moving faster and

overcome ine rtia by increasin g the current to th e motor to 100%

when it i s starting from a dead st op. After a pr ogramma ble num-

ber of steps, the inertia is overcome and the current can be

reduced to 7 0% to reduce heat in the stepper motor (allowing a

less expensive motor to be used). When stopping the stepper

motor, the current i s increased to 100 % for a short t ime to over-

come the forward momentum, then the motor is held in position

with a low-level standby current of 25%. If the motor is motionless

for more than the Hold Curre nt Timeou t period, the current goes

to 0%.

In micr ostepping mod e, the PWM i s used to a pproximate a sine

wave as shown in Figure 10.

The current control is accomplished by measuring the average

motor winding current through a sense resistor to ground, com-

paring it to a reference voltage, and PWMing the motor driver

transistor(s ) to forc e th e current to be equ al to the r efere nce cur-

rent. See the Ste pper Mo to r Cu rren t Co nt ro lle r Blo ck Di a gram

at the end of this document.

5.0 Scanner Support Functions

5.1 Illuminatio n Control Block

Scanner systems require an illumination source to supply the

light to the image being scanned. This source may be white (typi-

cally a fl uore scent lamp ), or re d, gree n, and/o r blue LE Ds. There

are four illumination modes in the LM9833:

In Illu mination Mode 1, the lam p connected to the LAMPR pin is

controll ed by the LA M PR On/O ff settin gs in th e co nfigura tion re g-

ister. The LAMPB output (if used) is controlled the same way. If

the lamp is supposed to be on all the time, then the On setting

should be set to a number between 0 and the value in the L ine

End register, and the Off register should be set to a number

greater than th e value in the Li ne End registe r. Conver sely, if the

lamp is supposed to be off all the time, then the On setting should

be set to a number greater than the value in the Line End register,

and the Off register should be set to a number between 0 and the

value in the Line End register. The LAMPG output is a Pulse-

Width-Mod ulated pulse str eam whose d uty cycle is contr olled by

the value in the PWM reg ister (0-4095). The d uty cycle is there-

fore equal to the register value/4096. The PWM counter is

clocked with the 48MHz clock so the output frequency is

48MHz/40 96 = 11.7kHz. This P WM ou tpu t can be use d to con tro l

the brightness of a fluorescent lamp.

In Illum inat io n M ode 2 (wh i ch is typ i cally us ed in c onju nctio n w ith

1 Channel Co lor), the LAMPR, LAMPG, and LAMPB outputs are

cycled through sequentially, one line at a time. An intern al color

counter k eeps track of the color of the line to be integrate d, and

takes that color’s LAMP output high when the pixel counter

Illumination

Mode Description

0LAMPR, LAMPG, LAMPB outputs = 0.

This is the power-on default.

Scanning with white light:

LAMPR and LAMPB controlled by

LAMP On/Off pointers in horizontal

pixel counter (as in Mode 3),

LAMPG is a PWM pulse stream

Scanning with 3 LEDs in color:

LAMPR turns on for Red lines

LAMPG turns on for Green lines

LAMPB turns on for Blue lines

Scanning with 3 LEDs in gray:

LAMPR turns on for all lines

LAMPG turns on for all lines

LAMPB turns on for all lines

Figure 19: Illumination Modes

Figure 20: Illumination Mode 1

LAMPG

LAMPR (LAMPR On < Line End, LAMPR Off > Line End

LAMPB (LAMPB On > Line End, LAMPB Off < Line End

Applicati ons Information (Continued)

LM9833

27 www.national.com

reaches the value stored i n that color ’s LAMP On registe r (Con-

figuration Registers 2C-37). If the On value is greater than the

value in the Line End register, then that lamp never turns on. That

color’s LAMP output goes low when the pixel counter reaches

that color ’s Off value. If the Off value is greater than the value in

the Line End register, then the pixel counter will never reach the

Off value and the lamp will always stay on. Illumination Mode 2

timing is shown in Fi gure 2 1, and in sligh tly m ore de tail in Figure

33.

Illumination Mode 3 is similar to Illumination Mode 2, except that

the LAMP ou tput s for all th ree col ors ar e turne d on and off every

line. Illumination Mode 3 timing is shown in Figures 22 and 23.

The Lamp On and Lamp Off settings work the same as in Mode 2

to control the on and off points for the different lamp signals. In

systems with a limited power budget, care should be taken to pre-

vent turning multiple lamps on at the same time. This can also be

importa nt for CIS sensor s that limit th e maximum co mbined cur-

rent of the three lamps.

These mode s are in opera tion whenever the chip is powere d on

and not i n st and by m od e. For exa mp le, th e L AM P ou tpu t s in F ig-

ures 21 and 22 keep pulsing whether the LM9833 is in the Idle ,

High Spee d Forward or Rev erse, or Scanning states. This el imi-

nates light amplitude variations due to the lamp/LEDs warm-up

characteristics. Since the LAMP pulses are synchronized to the

TR pulse, which is determined by the horizontal pixel counter , this

means tha t the pixel counte r is constantly runni ng, and any new

scans can only be started by waiting for the next new line (the

next Red line in the case of Illumination Mode 2).

5.2 CCD/CIS Control Block

This function generat es the clock signals nece ssary to control a

CCD or CIS sensor. Refer to the descriptions for r egisters 0B to

18 for more de tails on the timing of spe cific s ignals . The LM9833

features:

• Indepe nde nt contro l over the polari ty (inv erting or no ninve rting)

of the input stage to accommodate CIS or CDS signals.

• Full timing control of the CIS and CDS sample points. Refer-

ence and si gnal sampl e points ca n be indep endently a djusted.

Note that the absolute time between reference sample and sig-

nal sample must be 2 MCL Ks or great er, whether CDS is on or

off.

• Ability to turn off CDS. When CDS is on, traditional CDS is per-

formed. W hen CDS is off, th e signal i s sampled at the S ample

Signal point, but the interna l reference is used for the Sample

Reference voltage (not a point on the input signal itself).

• The CP 1 output sup plies the CP pulse need ed on some popu-

lar Toshiba CCDs. This looks and acts just like another, inde-

pendent RS pulse.

• A CP2 output is another independent pixel rate pulse that (if

needed) can be programmed to supply an additional clock.

• CCD clock signals RS, CP1, CP2 are reset when Line Ends

• The internal Clamp signal is reset with Optical Black Pixels

End.

• TR1 and TR2 pulse widths are always the same width, as

determined by Register 0E.

• The TR- Ø1 guardb and may be equal to 0, ca using T R and Ø1

to go high simultaneou sly and low simultaneously (Figure 24).

Th is is a requirement of s ome Canon CIS sensors.

• CIS TR 1 Timing Mo de 1. In this mode t he TR1 puls e is e xactly

one Ø cl ock lon g, occu rring on th e rising e dge o f Ø1. The T R1

pulse width and guardband settings are ignored. For Dyna CIS.

• CIS TR1 Timing Mode 2. In this mode the TR pulse is again

equal to 1 Ø period, but no w it is cent ered aroun d Ø1. The TR

pulse width and guardband settings are ignored. For Canon

CIS.

Figure 21: Illumination Mode 2

LAMPG

LAMPB

LAMPR

Figure 22: Illumination Mode 3 (grayscale)

LAMPG

LAMPB

LAMPR

Figure 23: Illumination Mode 3 (green on ly)

LAMPG

LAMPR (LAM PR On > Line End, LAMPR Off < Line End

LAMPB (LAMPB On > Line End, LAMPB Off < Line End

TR Pulse same as first clock pulse

ø1

Figure 24: TR-Ø1Guardband Can Be Equal To 0

Figure 25: CIS TR1 Timing Mode 1

Dummy

Pixels

TR1

Ø1

T ransfer

Phase

Line

Applicati ons Information (Continued)

LM9833

28 www.national.com

• To prevent sensor saturation, the LM9833 is always clocking

the CCD/CIS, except when it is in Reset or Standby (Register 7

bit 2 or 3 = 1).

• There is a bit for Fake Optical Black Pixels (register 19, bit 2).

This is used with Dyna CIS sensors. In this mode, the RS out-

put pulses once inside the TR1 pulse, then is held high until the

end of the op tical bla ck pixe ls. The TR1 pulse is extende d unti l

the trailing edge of the first RS pulse. This mode works for TR1

only, under all TR1 settings (normal and CIS TR1 Timing

modes 1 and 2).

5.3 AFE Operation

The LM9833 supports the following operation modes, controlled

by registers 26 and 27:

• 3 Channel Pixel Rate Mode. In this mode all three channels are

converted with the multiplexer in front of the ADC switching at

the ADC conversion rate, producing interleaved RGB data that

is transferred to RAM. The ADC runs at MCLK/8, each chan-

nel’s pixel rate is MCLK/24. Each color has its own offset and

gain coefficients. This mode typically uses Illumination Mode 1.

• 3 Channel Line Rate Mode . In this mo de all three ch ann els are

converted with the multiplexer in front of the ADC switching at

the line rate, producing a line of Red data, followed by a line of

Green data, followed by a line of Blue data, etc. that is trans-

ferred to R AM. The selected chann el and the ADC both run at

MCLK/8. Each color has its own offset and gain coefficients.

This mode typically uses Illumination Mode 1.

In the 3 Channel Line Rate Mode three TR pulses are generated.

TRRED is the TR1 output, TRGREEN is the TR2 output, and

TRBLUE is the CP2 output. In this mode TR pulses for a particular

color can be “skipped”, increasing the integration time for that

color. In the examp le sh own in Figur e 30 , the re d ch ann el se es 2

times the integration time of the green channel, and the blue

channel sees 3 times the integration time of the green channel.

Each chan nel can be indepen dently progr amme d to drop 0, 1, or

2 TR pulses.

Each co lor ’s TR pulse can be pr ogram med t o occur in posi tion 1

(inside Ø1 hig h) or po sition 2 (insi d e Ø1 lo w ), as show n in Figu re

31.

• 1 Channel Grayscale: Uses the selected channel’s offset and

gain coefficients for all lines. 1 Channel Grayscale is used to

scan a grayscale images. This mode typically uses Illumination

Mode 1 w hen used with a 3 Ch annel Color sensor, or Ill umina-

tion Mode 3 when used with a 1 Channel sensor.

ø1 inside TR1 pulse

TR1

ø1

tø1/4

tø1/4tø1/4

tø1

Figure 26: CIS TR1 Timing Mode 2

Figure 27: Fake Optical Black Pixels

Trail ing edg e of

first RS pulse End of Optical

Black Pixels

TR1

Red Channel

Figure 28: 3 Channel Pixel Rate Mode

Green Channel

Blue Channel

ADC

ADC Out LIne 1: RGBRGBRGBRGBRGB...

ADC Out LIne 2: RGBRGBRGBRGBRGB...

ADC Out LIne 3: RGBRGBRGBRGBRGB...

Pixel-Rate

Multiplexing

Red Channel

Figure 29: 3 Channel Line Rate Mode

Green Channel

Blue Channel

ADC

ADC Out LIne 1: RRRRRRRRRRRRRRR...

ADC Out LIne 2: GGGGGGGGGGGGGG...

ADC Out LIne 3: BBBBBBBBBBBBBBBBB...

Line-Rate

Multiplexing

Figure 30: 3 Channel Line Rate TR Pulse Timing

TRRED

TRGREEN

TRBLUE

Multiplexer Red Green Blue Red Green

tINT (RED)

tINT (GREEN)

tINT (BLUE)

TRRED

TRGREEN

TRBLUE

Ø1 12 12

Figure 31: 3 Channel Line Rate Mode with 2 TR

Pulse Position s

Applicati ons Information (Continued)

LM9833

29 www.national.com

• 1 Channel Color: T his m ode use s a senso r tied to th e Blue OS

input only. Illumination is switched in RGBRGB pattern at the

line rat e. E a ch co lor ha s own di g ital o ffset an d g ai n coefficients

as well as stati c Gain and Offset data. N ote that the re is a one

line delay be twee n when a li ne is expose d to a color an d when

pixels of that color are clocked out of the sensor. For example,

the Green LEDs should be on while you are clocking out Red

pixels. This mode uses Illumination Mode 2.

5.4 External DRAM Interface

The LM9833 supports two external DRAM sizes: 256k x 16 and

1M x 16. The DRAM is used for line buffering, gain (shading)

coefficient data, offset coefficient data, and gamma correction.

48kwords (16k pixels * 3 colors) are used for gain coefficients,

and another 48kwords (16k pix els * 3 colors) fo r the offset coeffi-

cients. Gamma correction consumes 12kwords (4k x 3 colors).

The remaining RAM (148kwords = 296kB for 256k DRAM, or

916kwords = 1,832kB for 1M DRAM) is used for the circular

image data buffer. The 1M size does not necessarily provide a

performance advantage (except perhaps when the USB bus is

heavily loaded and I/O is very slow) - the option is there to pro-

vide an alternative to the 256k in case of a supply shortage of

256k DRAMs.

Because the LM 98 33 doe s n ot use an y E DO or F ast P age M ode

features, it can work with either EDO or Fast Page Mode DRAM.

The LM98 3 3 should work with most 50-60ns 256k x 16 or 1Mx16

DRAM. Examples:

Samsung: KM416C1000C/C-L- 5, KM416C1200C/C-L-5,

KM416C1004C/C-L-5, KM416C1204C/C-L-5 (5V)

KM416V1000C/C-L-5, KM416V1200C/C-L-5, KM416V1004C/C-

L-5, KM416V1204C/C-L-5 (3V)

Alliance: AS4C1M16E5-50 (5V), AS4LC1M16E5-50 (3V)

Micron: MT4LC1M16E5DJ-5, MT4LC1M16E5TG-5 (3V)

There are 2 scan modes: 8 bit and 16 bit. The 8 bit mode is used

for norma l scann ing to appl ica t ion so ftwar e to ge ner ate 8 bit gray

or 24 bit color images. The 16 bit mode is used for calibration.

The AD C always conve rts at 1/8 o f the MCLK frequency ( fADC =

fMCLK/8). The datarate to the DRAM is the ADC rate divided by

the HDPI divider setting ( fDRAM = fADC/HDPI_DIVIDER. The off-

set correction data and the gain correction coefficient data are

provided at the DRAM datarate.

The DRAM timing is shown in Figure 34. All the read and write

operati ons shown in Fig ure 34 must be done for every pi xel writ-

ten to DRAM. That limits the pixel datarate to the DRAM to

1/875n s = 1.14 MHz. The fol lowing equ ation must be adhered to

in order to limit the DRAM datarate to 1MHz or slower:

(MCLK div)(HDPI divider)(Int Time Adj) >= 6

Int Time Adj refers to the value in register 19, and will be dis-

cussed in a later section. If register 1 9 = 0, then the value o f Int

Time Adj = 1 (for the purpose of this equation).

5.5 PAPER SENSE and MISC I/O

These 8 pins are used for home and paper sensing, LED dis-

plays, user start butt ons, etc.

Two pins are dedicated inputs: PAPER SENSE 1 and PAPER

SENSE 2. The other six pins, MISC I/O 1-6, can be configured as

Figure 32: 1 Channel Grayscale

G LED

B LED

R LED

COEF.

DATA SC SC SC

SC = selec ted channel (=green in this example)

Figure 33: 1 Channel Color

G LED

B LED

R LED

COEF.

DATA R G B

Figure 34: DRAM Timing per P ixel

356

RO: Offset Coefficient read

RS: Shadi ng (Ga in) Coefficient read

RG: Gamma Table read

WP8: 8 bit pi xe l wr i t e (wr i te 2 p i xe l s as 16 b i ts

every other cycle)

WP16: 16 bit pixel write

RP: read pixel

RF: refresh

RO RS RG WP8 RP RF

48MHz

RO RS RP WP16 RP RF

875ns

8 bit

16 bit

Figur e 35: Memory Map of External DRAM

Red Gamma

Green Gamma

Blue Gamma

Red Shadi ng

Green Shad ing

Blue Shading

Red Offset

Green Offset

Blue Offset

Pixel Data

(256k an d 1M)

Pixel Data (1M)

16kwords

Red Shading

Green Shading

Blue Shading

Red Offset

Green Offset

Blue Offset

16kwords

Pixel Data

(256k and 1M)

160

kwords

768

kwords

8 bit Datamode 16 bit Datamode

16kwords

768

kwords

16kwords

148

kwords

4kwords

Pixel Data (1M)

Applicati ons Information (Continued)

LM9833

30 www.national.com

inputs or outputs.

The state of each pin, True or False (1 or 0), is reflected in the

Status R egister.

These are the configurable aspects of these I/O pins:

• Input or Output function. If this bit is set to a 0, the pin is config-

ured as a n inpu t. If this bit is se t to a 1 the pin i s configu red a s

an output.

• The polarity of the input. I f this bit is set to a 1 (Active High ), a

high level on that input pin will p roduce a True reading (1) in the

Status Register. If this bit is set to a 0 (Active Low), a low leve l

on that input pin will produce a True reading (1) in the Status

• Level or Edg e Sensi tive. If this bit is set to 0 (Level Sensitive),

the Status Register will reflect the current state at that sensor

input p in. If th is b it is s et t o 1 (E d ge Sensi t iv e), the Status Reg-

ister for that input will be True (1) if there were any False to

True transitions at t hat sensor inp ut pin since the last time the

Status Register was read. Reading the status register clears

the state of all the edge sensitive inputs to False (0).

• PAPER SENSE 1 can be programmed to stop a scan, high

speed forward, or high speed reverse command (by clearing

the Scanning bit) when its state (as reflected in the Status Reg-

ister) changes from False to True. For flatbed scanners this

sensor can be used to detect the home position. In sheetfed

systems, PAPER SENSE 1 can be used to detect whether or

not the user has inserted a document to be scanned.

• PAPER SENSE 2 can be programmed to stop the scan or high

speed forward (by clearing the Scanning bit), and also set its bit

in the St atus Register to True a pr ogram mable numbe r of l ines

after i ts in put pi n ch ang es stat e f rom F alse to True. In sh ee tfed

scanners this is useful if the PAPER SENSE is located before

the scanner array, where the sensor will change states before

all of the paper has been scanned. This can be used in flatbeds

to prevent th e motor from tryi ng to step pa st the limits of trave l

of the syste m. T his inpu t sho uld not be used as the ho me posi-

tion sensor in flatbed scanners, since it will not stop a high

speed rev erse command.

• If they are configured as outputs, the MISC I/O 1-6 pins can

have thei r outputs s et to +5V or 0V by writing a 1 or a 0 to the

appropri a te bit.

The default state of the MISC I/O pins is described in detail in the

states on power-on, after entering USB Suspend, or when the

RESET pin is pulsed high. A Soft Reset (register 07) does not

reset the M ISC I/O pin s. The de fault stat es of the MIS C I/O pin s

are:

• MISC I/O 1: Input, edg e sensitive, h igh- to- low tra nsitio n sets bit

2 of register 2.

• MISC I/O 2: Input, edg e sensitive, h igh- to- low tra nsitio n sets bit

3 of register 2.

• MISC I/O 3: Input, edg e sensitive, h igh- to- low tra nsitio n sets bit

4 of register 2.

• MISC I/O 4: Output, voltage on MISC I/O 4 pin = VD.

• MISC I/O 5: Output, voltage on MISC I/O 5 pin = VD.

• MISC I/O 6: Output, voltage on MISC I/O 6 pin = 0V.

5.5.1 Adding Function Buttons

Many scanners today feature multiple buttons to select scan,

copy, fax, em ail , etc. fu nctio ns. Th e L M9 833 ’s M ISC I/O pins can

be used for t hese fu nctions. To free up MISC I/O inpu ts for other

functions, or if more than 6 buttons are required, you can multi-

plex th e b utto ns t oge the r. Figure 36 show s h ow 7 but ton s can be

multiplexed into only 3 MISC I/O lines. Figure 37 shows how to

decode the data in register 2 to determine which button was

pressed. This multiplexing technique can easily be scaled to

allow for mor e or l ess b utto ns wit h the m ini mu m n umb er of MI SC

I/O lines.

5.6 The Brains

This is the m aster contr ol section that keeps tr ack of the position

of the CCD pixel going th rough the a nalog front e nd, the co lor of

that line of CCDs (for single output CCD illumination control), the

stepper motor, and all other system coordination.

6.0 Communicating with the LM9833

Everything on the LM9833 (configuration settings, image data,

coefficient data, and gamma tables) is accessed through the

Configuration Register. Configuration Register I/O is done

through two steps. The first step is to write the address (0 through

7F) of the con figur ati o n reg ister to be rea d fro m or wri tt en to. The

second access is the data operation (a read or a write) for that

address. The address only needs to be written once. After an

address is written, any number of reads and/or writes may be

made to that address.

Registers 0, 1, and 2 are read-only registers. Writing to these

addresses may affect various counters inside the LM9833 and

Switch MISC I/O 1 MISC I/O 2 MISC I/O 3

No Switch

Pressed 111

A0 0 0

B0 0 1

C0 1 0

D1 0 0

E0 1 1

F1 0 1

G1 1 0

Figure 37: Truth Table for Remote W akeup With Up T o

7 Switches

Figure 36: Remote Wakeup With Up T o 7 Switches

ABCDEFG

MISC I/O 1

MISC I/O 2

MISC I/O 3

+5V

22k 22k 22k

Applicati ons Information (Continued)

LM9833

31 www.national.com

should the ref ore be avo ided . Bits 4 of regi st er 3 is also re ad on ly,

however it is OK to write to register 3. All of the remaining config-

uration reg ister s can b e re ad fr om and wri tte n to u si ng th is pro to-

col.

Registers 03-06 (the Dataport), 2A-27 (Illumination), 38-3D

(Static Gain and Offset), 42 (Offset and Gain Source, bits 0-2), 45

(Stepper Motor Status) , and 58-5B (Paper Sens e and Misc. I/O)

may be written to while the chip is in the Idle state. The LM9833

must be in Soft Re set mod e to write all ot her con figu ration r egis-

ters (see 10.2 Soft Reset).

6.1 The DataPort: Reading and Writing to Gamma, Offset,

and Gai n Memory

Because t he gamma table and the shadi ng and offse t correction

blocks of RAM are very large, the LM9833 uses an indexed

method of reading and writing them, called the DataPort. Four

addresses in the Configuration Register are used to implement

this feature, as shown in Figure 38.

The Da taPort al lows the u ser to s elect a m emor y blo ck (gam ma,

gain coefficient, or offset coefficient) and color (red, green, or

blue) to be read from or written to, by writing to Configuration

The starting address of that block (usually 0) is written into the

DataPort Address register (at Configuration Register Addresses

4 and 5). Bit D6 of regi ster 4 should also be set to a 0 or a 1 to

indicate whether the DataPort will be read from (D6 = 1) or written

to (D6 = 0) in subsequent operations. This is required so the

LM9833 can prefetch the data for faster access. The DataPort

Address is automatically incremented after every word (2 bytes)

of Offset, Shading, or Gamma data is read/written.

Once the memory block, color, and starting address are written, a

series of reads or writes to the DataPort will read from or write to

the selected memory block at maximum speed.

Registers 4 and 5 should always be written to after Register 3 has

been changed.

Reading and writin g the Da taPort shou ld only be done when the

LM9833 is not scanning (Register 07 = 0).

6.1.1 DataPort Type and Color

These 3 bits determine which memory block (gamma, gain, or off-

set coefficie nts, Figu re 39) and which c olor of th at mem ory bl ock

(red, green, or blue, Figure 40) is to be read from or written to.

6.1.2 DataPort Address

This 14 bit regist er (at Configur ati on Registe r ad dre sses 4 an d 5)

determ ines what the starting address is fo r the rea d/write oper a-

tion. This address is automatically incremented after every 2 byte

word r ead/write operat ion to the actual D ataPor t. For the gamma

table the ra nge is 0 to 4093. For th e Gain and Offset Co efficie nts

this range is 0 (corresponding the first valid pixel as programmed

in the Valid Pixels Start register) to 16383 (the maximum number

of im age pixels) . If read s or w rites continu e pas t 4093 or 1 6383,

the DataPort address counter wraps back around to 0 and contin-

ues counting.

6.1.3 DataPort

The DataPort is the 8 bit register (Configuration Register address

06) where the data is sequentially read from or written to. The for-

mats for Offset, Ga in, and Gam ma data ar e sho wn in Fig ure s 41,

42, and 43.

Configuration

Address Name Bits

3DataPort

Target/

Color b3- b0

4DataPort

Address

(MSB) b13 - b8

5DataPort

Address

(LSB) b7 - b 0

6 DataPort b7 - b0

Figure 38: DataPort

76543210 Type

------00 Offset

------01 Gain

------10 Gamma

------11 Undefined

Figure 39: DataPort Target Pointer

76543210 Color

----00-- Red

----01-- Green

----10-- Blue

----11-- Undefined

Figure 40: DataPort Color Pointer

76543210 Type

b15 b14 b13 b12 b11 b10 b9 b8 First Byte

b7 b6 b5 b4 b3 b2 b1 b0 Seco nd By te

Figure 41: DataPort Offset Format

76543210 Type

b15 b14 b1 3 b1 2 b11 b10 b9 b8 First Byt e

b7 b6 b5 b4 b3 b2 b1 b0 S eco nd By te

Figure 42: DataPort Gain Format

76543210 Type

0000b11b10b9b8 First Byte

b7 b6 b5 b4 b3 b2 b1 b0 S eco nd By te

Figure 43: DataPort Gamma Format

Applicati ons Information (Continued)

LM9833

32 www.national.com

7.0 The USB Interfa ce

The LM9833 uses the USB (Universal Serial Bus) interface.

Refer t o the LM98 33 software p ackage for deta ils on USB co m-

munication.

7.1 The USB Pins

Data is received and transmitted through the D+ and D- pins.

These are 3V differential signals. Figure 44 shows the recom-

mended circuitry between the LM9833’s D+ and D- pins and the

scanner’s USB connector .

8.0 Scanning

The following sections describe the typical steps taken to scan an

image.

8.1 Start Scann ing - Initia tin g an Imag e Sca n

An image scan is initiated by writing a Scan command to Register

07. The LM983 3 will mo ve the sensor forward the number of full-

steps specif ied in registe rs 4A/4B and begi n scanning. Sc anning

ends when the host wr ites a new co mm and to the command r eg-

ister (Idle , High Sp eed Fo rw a rd o r High Speed Reve rse) or when

PAPER SENSE 1 or PAPER SENSE 2 changes state (if pro-

grammed to do so).

The line buffer is reset when the Scan ning bit is SET, not w hen it

is cleared. The host c an continue to read stored data out of the

line buffer after a scan has stopped.

Pixel dat a is read from config uration regi ster address 00. Regis-

ters at other addresses can be read during a scan (to read the

LM9833’s status registers, abort the scan, etc.).

If for some reason you want to pause the scan for some length of

time and resume later, do NOT stop the scan (return to Idle). Sim-

ply stop reading pixel da ta. When the buffer fills up, th e LM9833

will automa ti cally sto p sca nn ing a nd t urn off pow e r to the step per

motor (when the delay goes beyond the time specified in the Hold

Current Timeout register).

The last 2 bytes of every line is a status word indicating how

much d ata is in the im age b uffer at the t ime the status w ord w as

written. T his informati on is in the 8 LSBs of the sta tus word , and

has the same format as Register 01.

8.2 Reconstructing 8 bit Image Data Received By the PC

When reco nstructing an ima ge from the strea m of data recei ved

from th e LM98 33, it i s usef ul to kno w th e form at of th e data . The

LM9833 does not perform deinterleaving on the pixel data, it

comes out exactly as the sensor sends it. Deinterleaving must be

performe d on th e host PC.

For a single output CCD/CIS that outputs one line of data with

colors alternating at the line rate, the output format is:

R1, R2, R3, R4,..., Rn-2, Rn-1, Rn (line m)

G1, G2, G3, G4,..., Gn-2, Gn-1, Gn (line m + 1)

B1, B2, B3, B4,..., Bn-2, Bn-1, Bn (line m + 2)

For a triple output CC D/CIS that outputs 3 lines of data (each x

pixels apart in the ve rtical direction) with colors alt ernating at the

pixel rate, the output would be:

R1, G1, B1, R2, G2, B2,..., Rn-1, Gn-1, Bn-1, Rn, Gn, Bn

with the Red data representing line m+x, the Green data repre-

sentin g lin e m , and the B lue data repres enting line m -x. “x” is the

separation between lines, which depends on the physical dis-

tance betwe en the R , G, an d B sensors and th e rat e at which the

sensor is moving over the image.

The length of a line of image data sent to the PC depends on sev-

eral factors:

• The ran ge of pixels to be scanne d (Data Pixe ls): Data Pixel s =

(Data Pixels End - Data Pixels Start),

• The horizontal resolution set in the configuration register

(HDPI_Divider)

• The number of bits per pixel (1, 2, 4, or 8, called B), and

• The color mode: pixel rate (C=3) or line rate (C=1).

The scanner software on the host must strip the 2 byte status

word from the end of each line before reconstructing the image.

8.2.1 Reconstructing 16 bit Image Data Received By the PC

In the 16 bit Data Mode the Gamma Correction and Pixel Packing

stages are bypass ed. E ach pixel com es out as 2 byt es inste ad of

1, doubl ing th e amou nt of me mory neede d to stor e one li ne. The

data fo rm at i s sho w n in F igu re 45. Thi s mo de i s o the rwi se i de nti-

cal to the 8 bit mode. The number of bytes per line in 16 bit mode

is given in this equation:

The 16 bit mo de is used to acqu ire 16 bit data for accurate gain

and offset calibra tion .

8.3 High Speed Forward

When register 07 is se t to a 1, t he LM9 833 move s the m otor fo r-

ward at maximum speed (determined by the fast feed stepsize,

registers 48 and 49) until a 0 is written to register 07 or either one

Figure 44: Recommended USB C omponent Values

LM9833 D-

(pin 83)

1.5k

22Ω

LM9833 VREGULATOR

(pin82)

LM9833 D+

(pin 84)

22ΩD+ USB

Connector

1MΩ∗

D- USB

Connector

∗Optional - forces LM9833 into

suspend mode if US B cable is

not attached to scanner.

10pF 10pF

76543210 Type

b15 b14 b1 3 b1 2 b11 b10 b9 b8 First Byt e

b7 b6 b5 b4 b3 b2 b1 b0 S eco nd By te

Figure 45: 16 bit Data Format

Bytes/Line 2 INT⋅INT Data Pixels

HDPI_Divider

------------------------------------





⋅⋅

------------------------------------------------------------------------







Bytes/Line 2 INT Data Pixels

HDPI_Divider

------------------------------------

()

⋅⋅

Applicati ons Information (Continued)

LM9833

33 www.national.com

of the PAPER SENSE inputs becomes True (if that sensor has

been properly programmed to interrupt scanner movement).

PAPER SENSE 2 can be used to cause a delayed stop. If the

FullSteps to Scan after PAPER SENSE 2 trips register is

greater than 0, motor movement will continue for the pro-

grammed number of full steps. This can be used to eject paper in

sheetfed scanners.

The LM9833 also features a Programmed High Speed Forward

command. This is identical to the High Speed Forward function,

except that it will automatically stop moving once the motor has

moved the number of lines specified in registers 4A and 4B.

8.4 High Speed Reverse

When register 07 is set to a 2, the LM9833 moves the motor

backwards at maximum speed (determined by the fast feed step-

size, registers 48 and 49) until a 0 is written to register 07 or

either one of the PAPER SENSE inputs becomes True (if that

sensor has been properly programmed to interrupt scanner

movement). The FullSteps to Scan after PAPER SENSE 2 trip s

tion is generally used to home the sensor in flatbed scanning

applications.

The LM9833 also features a Programmed High Speed Reverse

command. This is ide ntical to t he High Sp eed Reverse function,

except that it will automatically stop moving once the motor has

moved the number of lines specified in registers 4A and 4B.

8.5 Short Example of a Scan

• PC config ur es the LM9 83 3 by writ in g to the con figu ra tion r egi s-

ters.

• PC has the LM9833 scan a calibration image, then calculates

the calibration coefficients for the scanner.

• PC transmits the calibration information to the LM9833.

• If a sheetfed, the PC now polls the LM9833 status registers to

see if there is any paper inserted. If a flatbed, it moves the scan

head to the home position.

• PC sets the Scanning bit in the Configuration Register.

• PC calculates the size of the image to be scanned in bytes,

then read s bu l k da ta f rom re gi ste r 0 0 o f th e LM 98 33 unt i l i t ha s

read the e ntire image. If for som e reaso n the sca n needs to be

aborted, the PC writes a 0 to register 07.

• After all i ma ge dat a is read, PC w rite s a 0 to r egi st er 0 7 to stop

scan.

• If this is a flatbed scanner, the PC should now send a High

Speed Reverse command to send the sensor back to the home

position. For a shee tfeeder, it can send a Hig h Speed For ward

command to eject the remainder of the image.

• The scanner is now in the idle state.

9.0 Master Clock Source

The timing for the entire chip comes from the CRYSTAL OUT pin.

Typically th is pin is used (with the CRYSTAL IN p in) as a crystal

oscillator. The clock frequency should be 48MHz. This 48MHz

clock is divided by the MCLK divider (register 08), and the divided

output is MCLK (Master CLocK). The MCLK divider range is from

1.0 to 32.5 in steps of 0.5. A configuration register code of 0

divides th e clock by 1.0, wh ile a code of 63 divides the c lock b y

32.5. AT 48MHz, this provides an MCLK range of 1.48MHz to

48MHz and a corresponding ADC conversion rate of 184kHz to

6.00MHz. This divider can be used to closely match the output

data rate to the PC’s input data rate, minimizing scan time.

MCLK is use d to clock the vast major ity of the LM 9833’s circ uits.

CRYSTAL OUT is directly used in the USB I/O section, DRAM

timing, and a few subsections where the highest possible clock

speed is re quired (su ch as the PW M pulse gene rator for the light

source and the stepper motors).

To use the LM9833’s crystal oscillator feature, tie the CRYS-

TAL/EX T CLK pin to DG ND. Fig ure 46 shows the reco mmended

loading circuit and values for a 48MHz oscillator. These compo-

nent va lues assume 10pF of stray capacitanc e between CRYS-

TAL IN and ground, and 10pF between CRYSTAL OUT and

ground, for a total CRYSTAL IN and CRYSTAL OUT loading of

15pF and 25pF.

A 2.7k pullup to a 5V source is necessary to ensure oscillator

start-up . F or se lf-power ed syst em s, a ny clea n s our ce of +5V can

be used. For bus-powered systems, this pin must be connected

to the ACTIVE/SUSPENDED pin in order to me et USB suspend

power consumption requirements.

When laying out the crystal oscillator components, always keep

the traces as short as possible, to minimize stray capacitance

and inductive noise coupling, particularly on the CRYSTAL IN pin.

Operation at 24MHz (24/48 = VD) is not reliab le and should not

be used.

To drive the LM9833 with an external 48MHz clock, tie CRYS-

TAL/EXT CLK (pin 54) to VD, tie CRYSTAL_IN to DGND, and

drive the TTL or CMOS-level clock signal into CRYSTAL_OUT

(pin 52) .

10.0 INITIALIZATION

10.1 Power On Reset (POR)

POR is generated by the ramp of the VA supply pins from 0V to

+5V. A low to high to low signal on the external RESET pin will

also generate a POR. A POR event:

• Res e ts th e US B t ra nsc e i ver. All en um er a t ion an d c on fi g ur at io n

data will be reset to its default setting.

• The oscillator will start (or continue) oscillating.

• Forces a l l conf i gur atio n re gisters that ha ve de fau lts ( shown as

black box es in the confi g ura tion register tables ) to their default

settings (i nclu ding the Rese t and Sta ndby bi ts) . See the Reset

and Standby mode descriptions for more information.

• MISC I/O 1-3 will be co nfigured as input s and could generate

ure 4 6: 48 MHz Cr

stal Oscilla to r Circ ui t

5pF 15pF

300pF

1.2µH

CRYSTAL

48MHz Third

Overt one C rystal

Ecliptek

EC-T-48.000M

C1 C2

24/48 = DGND

CRYSTAL

OUT

2.7k

ACTIVE/SUSPENDED pin

or +5V (see text)

10Ω

Applicati ons Information (Continued)

LM9833

34 www.national.com

remote wakeup signals (after the device is initialized).

• MISC I/O 4-6 are configured as outputs.

10.2 Soft Reset

A Soft Reset is generated by setting bit 5 of register 07. A Soft

Reset:

• Stops most of the internal clocks inside the system to save

power.

• Does NOT stop 48MHz oscillator.

• Resets internal state machines for correct operation after

• Stops DRAM refresh. This will corrupt all the gamma, offset,

gain values, as well as any image data, stored in the external

DRAM.

• Does NOT prevent configuration register rea d/writes.

The following procedure should be followed to produce a Soft

Reset:

• Set register 0x07 to 0x00 (Idle)

• Set register 0x18 to 0x18 (disabling sampling)

• Set register 0x07 to 0x20 (Reset)

• Write original value back into register 0x18, write additional

configuration registers (if desired)

• Set register 0x07 to 0x00 (Idle)

10.3 Standby

The LM983 3 ent ers the St andby mode by sett ing bit 4 of register

07. Standby Mod e:

• Powers down the analog section to conserve power.

• Tristates th e stepper motor outpu ts (rega rdless o f the state of

• Does NOT prevent configuration register rea d/writes.

10.4 Suspend Mode: Entering

Suspend M ode is e nte red w h en th e US B b us ha s had no acti v ity

for 3ms. The Su spe nd state for ces the LM9 833 into a l ow curr en t

idle state. Suspend Mode:

• Stops the oscillator.

• Forces all b lack-b ox highlighted c onf ig ur atio n r egisters to t heir

default settings (including the Reset and Standby bits). See

the Reset and Standby mode descriptions for more

information.

• MISC I/O 1-3 will be configured as inputs and can be used as

remote wakeup signals.

10.5 Suspend Mode: Exiting

When the LM98 33 exits Su spe nd Mo de:

• The oscillator is restarted.

• The Reset and Standby bits are still set. The driver software is

responsible for clearing them and setting the configuration

regis ter s aga in to re sum e op er ation . A ll confi g ura tion reg ister s

and DRAM data should be re-written after a Suspend

sequence.

11.0 USEFUL EQUATIONS

The integration time (tINT) for 1 line is always:

where pixel_period is the time it takes to clock one pixel out of the

sensor (C = 3 for Pixel Rate Color, and 1 for all other modes):

and line_length is the length of an entire line, measured in units of

pixels. Note that this includes the transfer portion of the line:

These equ ati o ns ap ply for any ITA (Integ ratio n Time Adjust, Reg-

ister 19) sett ing.

To max imize scann er throughput , it is desira ble to genera te data

at the same rate as the digital I/O to the host PC. Under some

conditions (slow digital I/O, or very high resolution scans), the

time to gener ate one line may be gr eat er th an the maxim um inte-

gration time. In this case, the integration time may be set to an

acceptable value using the previous equations, and the time to

process a line extended using Register 19 (the ITA function).

Using the ITA function, the time to process 1 line can be extended

to match the digital I/O rate required:

The maximum DRAM write pixel rate allowed is 1MHz. If you con-

figure the LM9833 to generate data any faster then 1Mpixel/s, the

LM9833 will not function co rrectly. To e nsure that the LM 9833 is

programmed to a legal datarate, ensure that this constraint is

met:

When using the ITA function (ITA > 0), use this version of the

equation:

Use this equation to calculate the stepsize for a scan:

where vertical_resolution = the desired vertical resolution of the

scan, and FSPI = the number of full steps required to move the

sensor one inch.

When using the ITA function (ITA > 0), use this version of the

equation to compensate for the ITA function:

12.0 CHANGES FROM THE LM9831

12.1 FullStep Timeout Function

The LM9833 fe atures a mo tor step counter that will aut omatica lly

stop the scan after a certain number of motor steps. To enable

this m ode, s et reg ister 58 , bit 5 = 0 , then progr am the numb er of

fullsteps to scan.

12.2 16 Bit Output Mode

The LM 9833 ’s 16 bit outpu t mode is fully functi onal. I t is capable

of scanning any image that the LM9833 can scan at 8 bits, and

does not require any polling of register 01.

tINT pixel_period line_length⋅=

pixel_period mclk_div C 8⋅⋅

48MHz

----------------------------------------=

line_length line_end TR_time

tLINE 1+ ITA()tINT

mclk_divider HDPI_divider 6

≥⋅

mclk_divider HDPI_divider ITA 6≥⋅⋅

scan_stepsize line_length vertical_resolution

⋅

FSPI 4

⋅

-----------------------------------------------------------------------------------=

scan_stepsize line_length vert_res

⋅

FSPI 4

⋅

-------------------------------------------------------- ITA 1+()

ITA

------------------------

⋅

Applicati ons Information (Continued)

LM9833

35 www.national.com

12.3 Steps to Reverse Register Increased

To improve performance with some mechanical designs, the

number of bits in r egist er 50 wa s increas ed from 6 to 8 bi ts. Th is

allows the scan ner to re vers e up to 255 steps when pa using due

to a buffer full condition.

12.4 - Acceleration Profile Modified

The high est sett ing of th e Ac celer ation Profile (bi ts 2- 7 of reg ister

51) has been modified to give the motor more time during the

acceleration/deceleration phases. In the LM9831, a setting of 3

for the “stopped” time, “25%” time, and “50%” time caused the

state machine to spend 3 full steps in that state. In the LM9833, a

setting of 3 will cause th e state machine to spend 8 full ste ps in

that state.

12.5 1 Channel Color Mode

When usin g the LM9831 i n 1 Channel C olor Mode wi th the hold

current timeout set to 0, the LM9831 would sometimes skip a line

during a p ause /re sum e c ycle. T his pro ble m h as b ee n fixe d i n the

LM9833.

12.6 DRAM Control Signals

The RD, WR, CAS, and RAS pins are now tri-stated when the

LM9833 is in Suspend Mode. In a USB bus-powered application

where the DRAM is powered down in suspend mode but the

LM9833’s VDRAM supply still has power, this change prevents

the RD, WR, CAS, and RAS pins from potentially forw ard biasi ng

the input protection diodes of the external DRAM which could

cause th e curr en t dr awn fr om the U SB ’s power so urce to exceed

the 2.5mA maximum allowable current draw when in suspend

mode.

12.7 Start of Scan Reset

In the LM9831, the value in register 01 is not reset (and therefore

not accurate) until the first line of the image has been scanned.

The LM9833 resets this counter as soon as a scan is initiated, so

the value in register 01 is always valid.

12.8 Power-On Reset (POR)

The LM98 31 has a power- on rese t circui t that cau ses the c hip to

be reset during power-up when the analog power supply (VA)

passes 2V. If VA ramped very slowly (2V/ms), this could cause

the LM9831 to be reset and start trying to load data from the

external EEPROM before the external was EEPROM became

active, which could cause the LM9831 to think there was no

external EEPROM attached.

The LM98 33 ha s a power- on re set thr esho ld to 3V, to reduce the

chance of this occurring. Additionally , the input to the POR comes

from VD, not VA. This allows the VA supply to be switched off

when in Suspend mode, allowing more flexibility in USB bus-pow-

ered des igns.

12.9 Remote Wakeup

The LM9833 supports enabling and disabling remote wakeup

through the LM9833 minidriver software.

12.10 Reduced Current Consumption

The LM9833 includ es 4 current sett ings (10 0%, 80%, 70%, and

50%) to contro l the curr ent con sumed b y th e analog supply (VA).

The LM9833 is tested and guaranteed at the 100% setting, which

is the same as the LM 9831’s analog sectio n. For USB bus-p ow-

ered settings, To reduce the current consumption (for bus-pow-

ered appli cations) set this re gister to one of the 3 other settin gs.

The performance of the analog section (INL, DNL, and noise) will

degrade at the lower settings, but this may not be noticeable in

the final image, particularly with CIS sensors where the noise and

non-linearities of the sensor may be far greater than that of the

LM9833’s analog front end.

12.1 1 Motor Phase Swap

Bit 5 has been added to register 45 to “swap” the A and B stepper

motor phases. This will reverse the stepper motor’s direction of

movement. This can be used to make the scanner scan in the

opposite (or both) directions, provides an alternative means of

sensing the ho me position by scan ning towar ds hom e un til a pat-

tern on the calibration strip (instead of an optical sensor) is

detected, and also provides a software fix for a motor that hap-

pens to be wired backwards. Note that this on ly works in fullstep

mode.

12.12 ITA Output on LAMPB

The LM9833 adds 1 bit (register 29 bit 2) that, when set, will out-

put the ITA (Integratio n Time Adjust) pha se o n th e LA M P B out put

pin. This signal can poten tially be u sed to tur n off the illumina tion

source during the ITA’s long integration time period.

12.13 Faster Fullstep Movement

In Fullstep Mode, the LM9831 and LM9833 normally move the

motor with the motor winding current set to 0.35V/RSENSE

(0.5V/RSENSE during the Kickstart period at the start of move-

ment). The problem is that the ideal RSENSE value for microste p-

ping was too small for fullstepping, and vice-versa. So if the

scanner needed to use both modes (fullstepping for high speed

movement and low resolution scans, microstepping for high reso-

lution scans), there wasn’t a sense resistor value that worked well

for both.

The LM98 33 impro ves this situation by add ing this function: if the

Kickstart Steps value (register 55 bits 0-2) is set to 0, the LM9833

will set the winding current to 0.5V/RSENSE f or all fullst ep move-

ment. This provid es more curren t to the stepper motor in fullstep

mode, w h il e all o wi n g the s en s e re s i st or t o be a t a v alu e op t imi ze d

for microstepping.

12.14 Fullstepping Fastfeed, Microstepping Scan

The L M9833 a dds 1 bit (regi ster 4 5 bit 6) that, w hen set, makes

the scanner automatically use fullstep mode for fastfeeding at the

start of scan, then switch to micr oste pping when scan begins.

12.15 Device and Vendor IDs for USB Interface

The LM9833’s internal (default) ROM is programmed for a Ven-

dor I D of 0x0400 an d Device ID of 0x1002 . The Vendor String is

“National Semiconductor” and the Device String is “LM9833 48

Bit Scanner”.

Applicati ons Information (Continued)

LM9833

36 www.national.com

12.16 Paper Sensor #2 Doesn’t Stop High Speed Reverse

In the LM9831, a false-to-true transition on Paper Sensor #2

would stop a high spe ed rever se (usuall y used for hom ing in flat-

bed scanners). Due to the changes made to accommodate the

FullStep Timeout Function function, the ability to stop a high

speed reverse function was removed.

12.17 Turbo and Prev iew Modes

These mod es actually ex isted i n t he LM9 83 1, b ut were no t do cu-

mented.

The Turbo and Preview modes allow additional pixel averaging

(horizontal resolution reduction) to be done in the analog domain.

This can be useful, for example, when you have a 1200 dpi scan-

ner and w ish to scan at 75 or 50dp i. The HDP I divider function’s

lowest resolution is divide-by-12. With the HDPI divider set to

divide-by-8 and turbo or preview mode set to x2, the horizontal

resolution will be 1200/16 = 75dpi. With the HDPI divider set to

divide-by -12 and turbo or preview mode s et to x2, the horiz ontal

resolution will be 1200/24 = 50dpi. The HDPI divider and

Turbo/Preview modes can be used in any combination.

For a Preview factor of xN, the Preview Mode operates by

increasing the pixel clocks to the CCD by a factor of N, while sup-

pressing (N-1) reset pulses out of every N pixels. This is only use-

ful for CCDs (or CIS sensors made with CCD technology).

In the Turbo Mode, the entire analog front end is run N times

faster, and eve ry N pixels are averaged toge ther befor e they are

converted to digital by the ADC. When using Turbo Mode, the

range of reg isters 0F to 18 is reduce d by the Turbo Mode factor,

according to the following table:

13.0 PORTING SOFTWARE FOR LM9830 TO LM9833

The LM9833 is similar in architecture to the LM9830. Porting a

TWAIN driver from the LM9830 to the LM9833 is relatively

straightforward if consideration is given to the following issues.

The LM9833 includes almost all the features of the LM9830, plus

several new ones. The first st ep is to c hange the LM9830 Twain

driver so that it works with the LM9833. The second step is to

take advantage o f the new features of the LM9833 that will allow

you to obtain even better, faster scans than you obtained with the

LM9830.

13.1 Porting Step 1

13.1.1 Adjust for Register Changes

While more than 50% of the registers in the LM9833 are in the

same location and perform the same function as they did in the

LM9830, many other registers have changed. Sometimes the

address of a re gi ste r ch an ged , so me time s the loca ti on of the bits

inside a register were moved, some register settings were com-

bined or deleted, and the size of some registers was changed.

Please co mp are the reg i ster li sting s for the LM9 83 0 an d LM 98 33

carefully. This is a list of registers that have changed:

Registe rs 1, 2, 3 , 4 , 7 , 9 , B, 19, 1A , 1B , 3 E-41 , 42, 43-44 , 4 E- 4F,

51-53, 54, 5A, 5B, 5E.

13.1.2 Choosing the MCLK Divider (Regist er 0x08)

The datarate coming out of the Horizontal DPI Divider must be

1.1MHz or less. If it is fast er than this, the LM9833 will not oper-

ate correctly. Since the maximum USB datarate is about 1MHz,

this does not impact the performance of the scanner in any way.

This is the Clock Divider Rule:

(MCLK_divider)(HDPI_divider)(ITA) >= 6

The IT A (Integration Time Adjust) refers to register 19, and will be

discussed in a later section. If register 19 = 0, then the value of

ITA = 1 for the purposes of this formula.

If register 19 = 0, this formula means that if the HDPI_divider = 1,

the MC LK_divider mu st be set to divide-b y-6 (reg 08 = 10 [d eci-

mal]) or higher. If the HDPI_divider = 4, the MCLK_divider must

be set to di vide -by -2 ( re g 0 8 = 2) or hi g her. If the HDPI_ divid er i s

6 or larger, then the MCLK_divider can be set to divide-by-1

(reg08 = 0).

See 13.2.2 Integration Time Adjustment Function for addi-

tional informa tion .

13.1.3 Calibration

In the LM9830, calibration was always performed at the optical

resoluti on of the scan ne r. For example, if the optical reso luti on of

the scanner was 600dpi, then calibration was performed at

600dpi even if the scan was going to be at 300dpi or 150dpi.

To kee p th e sp ee d of the LM 98 33 h i gh whil e u sing sl owe r DR AM

(inste ad of SRAM), the a rchitectu re of the L M9833 wa s chang ed

so that the H orizo nta l DPI ad just fun cti on is perfo rm ed before the

pixel rat e offset and shad ing cor re c tion , instea d of af ter ( as i n the

LM9830).

This means that the calibration rou tine needs to be changed so

that regi ste r 9 is set to the de sired scan resolu ti on be for e calibr a-

tion.

13.1.4 Pixel Rate Offset Correction

The LM9833 uses 16 bits for the offset correction of each pixel.

Mode Pixe l Ra te Registers

0F to 18

Range

3 Channel,

Turbo off MCLK/24 0 - 23

3 Channel,

Turbo x2 MCLK/12 0 - 11

3 Channel,

Turbo x3 MCLK/8 0 - 7

3 Channel,

Turbo x4 MCLK/6 0 - 5

3 Channel,

Turbo x6 MCLK/4 0 - 3

1 Channel,

Turbo off MCLK/8 0 - 7

1 Channel,

Turbo x2 MCLK/4 0 - 3

Applicati ons Information (Continued)

LM9833

37 www.national.com

13.1.5 Pixel Rate Shading Multiplier

The shading multiplier uses all 16 bits of data.

There is an important difference between the pixel rate shading

multiplier of the LM9830 and the LM9833. In the LM9830, if the

value for th e sh adin g m ulti plie r w a s 0, t he gai n thr oug h t he m ulti -

plier was 1 V/V. T he LM98 30 also had 3 multiplier gain ra nges: 1

to 1.5, 1 to 2.0, and 1 to 3.0 V/V.

The LM9833 has a simpler multiplier with only one gain range: 0

to 4 V/V. The gain of the multiplier is

Gain = (gain code)/16384 V/V

Note that if the gain code = 0, then the pixel is multiplied by 0! In

other words, if the gain coefficient is set to 0, the output of the

multiplier will be all 0s. A gain code of 0 was not unusual for the

LM9830, but will not work with the LM9833. To maintain a mini-

mum gain of 1V/V, make sure the gain code is 16384 or higher.

If desired, gains betwee n 0 and 1 V/V can be used, but they will

usually result in less dynamic range and noisier images.

13.1.6 The Gamm a Table

The LM9833’s 3 gamma tables are 12 bits wide, instead of 10 bits

(LM9830) . This means each gamma curve has 4 times the num-

ber of datapoints and you can now get 4 times the accuracy avail-

able with the LM9830.

Since most consumer CCDs have a true SNR of less than 12 bits,

the LM9833 does not support a 16 bit gamma table, freeing up an

additional 180kwords of DRAM memory.

13.1.7 General DataPort Information

There have been several important changes to the dataport.

The read-only Pause bit is now in register 3. You can write this bit

in order to write to the other bits in the reg ister, but anythin g you

write to the Pause bit will be igno red .

There ar e now 2 bits to se lect betwee n Offset Coe fficients, Gain

Coefficients, and Gamma data.

In the LM9830, Offset and Gain coefficients were combined to

make one 16 bit word, written to register 6 as 2 bytes.

In the LM 98 3 3, Offset is a 16 bit word , and Gain is a 1 6 bi t wo rd .

Offset and Gain data each have a separate dataport address.

6 in Offset mode or Gain mode (reg03b1 = 0).

Gamma data is 8 bits wide, as in the LM9830. Register 5 will auto

increment aft er 1 gamma byte is written to register 6 in Gamma

mode (reg03b1 = 1).

The bit locations for selecting color (R, G, or B), have been

shifted left by 1 bit.

The Data Port addr ess width is no w 14 b it s wi de. This ca use d the

R/W bit to be shifted left by 1 bit.

When using 1 Channel Gra yscale, the LM983 0 ignored the color

bits in reg ister 3. This has b een fixed in the LM 9833. Regi ster 3

controls the gamma table color.

Make sure your software takes all of these changes into account.

13.2 Porting Step 2

Once your TWAIN drive r is operating with t he LM9833, you can

start taking advantage of the LM9833’s additional features.

13.2.1 1200 DPI

The LM 9833 can sup port line widt hs up to 1638 4 pixels x 3 col-

ors. This allows 1200dpi scanners with a maximum width of 13.6”

(B-size).

13.2.2 Integration Time Adjustment Function

Due to DRAM speed limitations, the maximum speed at which the

LM9833 can store pixels is 1MHz. The ADC can run at speeds up

to 6MH z, but only when the H DPI divider is set to d ivide- by-6 or

greater, which results in a pixel rate of 1MHz or less.

This can b e a challenge when scanning at high resolutions. For

example, a 600dpi 8.5” wide color CCD scanner digitizes 15,300

pixels/line. At a 1MHz rate, the resulting integration time

is15.3ms. Integration times above 10ms may be problematic in

some designs.

To allow shorter integra ti on tim es wi tho ut viola ti ng the 1M Hz max

pixel r ate , th e L M98 33 ha s an Int egr atio n Time Adjust (ITA) func-

tion (Figure 47). ITA generates 2 alternating timebases for the

CCD timing, a high frequency timebase, and a lower frequency

timebase. During the high frequency timebase, the integration

time (tINT1) is short, as short as the total number of pixels in a line

divided by 6MHz. (Using the previous example, that would be

2.5ms). D uring tINT1, data is clocked out of the CCD but it is not

digitized by the AFE. The CCD output signal (representing line “n-

1”) is disca rd ed.

After the short integration time, the clock is slowed for the next

integration time (tINT2). Integration for line “n+1” is done during

this period. Since tINT2 is longer, there is more time to read out

pixel data for line “n”. As long as tINT2 corresponds to a pixel r ate

of 1MHz or slower, the line can be digitized and written to the

DRAM.

tINT 1 is determined by the traditional calculations, primarily the

MCLK divider and line end settings. tINT2 = ITA * tINT1.

There ar e two more consid eration s when using th e ITA . The first

is CCD image lag. Image lag is a sensor phenomenon in which a

perc entage o f th e pixel volt age fr om th e pre vious line a ppear s in

the pixe l volta ge fo r th e cur ren t l ine. In the exam pl e abo ve, so me

of the signal from line n-1 will leak into lin e n. Since the integr a-

tion time for line n-1 (tINT2) is 2 to 6 times longer than tINT1, the

leakage may be as much as 2 to 6 times the sensor specified

image lag. This is usually not a problem. If it is, use a sensor with

a low image lag specification, or reduce the brightness of the

CCFL light sour ce.

The second consideration is the stepsize calculation. Using the

ITA’s dual timebases affects the stepsize required to produce an

image with the correct vertical resolution. The solution is to calcu-

late the stepsize using the traditiona l formula, the n multiply it by

the factor (ITA+1)/ITA:

discard

Figure 47: Integration Time Adjust Function

tINT1 tINT2

line n line n+1line n-1

tINT2 = ITA * tINT1

Pixel

Data line nline n-2

Applicati ons Information (Continued)

LM9833

38 www.national.com

14.0 QUESTIONS AND ANSWERS

Q Where is calibration done?

A Calibration is done on the host computer.

Q Does the LM9833 support 800dpi sensors? 400dpi? XXXdpi?

A Yes. The L M9833 will sup por t any se nso r up to a m axim um o f

16383 pixels x 3 colors. Available horizontal resolutions are

calculated by the optical resolution of the scanner divided by

the HDPI _divider.

15.0 GENERAL NOTES AND TROUBLESHOOTING TIPS

(mclk_divider)(HDPI_divider)(ITA) must be grea ter than or equal

to 6. If this condition is not met, the LM9833 will not work.

Make sure the gamma tables are programmed with a valid

gamma curve.

Make s ure th e m ultiplier ga in c oeff icients are l oad ed an d corr ect .

(Remember, a gain coefficient of 0 means a GAIN of x0, not x1. If

the gain coefficient = 0 the output code will always be 0.)

Remember that when the LM9833 is reset (reg08 = 0x20) or in

suspend for long er than a few milliseco nds (consult your DRAM

datasheet), DRAM refresh will stop and the Gamma and Coeffi-

cient data may be corrupted.

Some of the CCD signals (RS, CP1, and CP2) can have a small

pulse when line_end occurs. Line_end resets these signals and

depending on how they are programmed to go on and off,

line_end can cho p off the sign al before its progra mmed off time.

This is not a problem because the truncation occurs at the end of

every line, after all the image data for that line has been digitized.

Registers 4 and 5 on ly autowr ap to 0 fr om their h ighest possi ble

legal address. If an address higher than the highest legal address

is written, it will continue to increment from the illegal address, not

wrap to 0, and unknown o peration may occur. This c an not h ap-

pen unless the host writes an illegal address to the dataport.

The absolute distance between reference sample and signal

sample must be 2 MCLKs or greater, whether CDS is on or off.

The range of values for the Optical Black (r egisters 0F and 10),

Reset Pul se (11 and 1 2), CP1 pulse (13 and 14), CP2 pul se (15

and 16), Reference Sample (17), and Signal Sample (18) settings

depend on the rate of the pixel data coming from the sensor.

Always make sure line len gth (data pixe ls end - data pixels sta rt)

is >= the horizontal divider . For example, if you are dividing by 12,

the line length must be >=12.

The Lin e End ( regi sters 20 and 2 1) setti ng m ust be progr ammed

as follows relative to the Data Pixels End (registers 24 and 25)

setting:

Line End must be >= Data Pixels End + 20

The Data Pixels Start (registers 22 and 23) setting must be >=the

Active Pixels Start (registers 1E and 1F) setting.

The correct Default Phase Difference (registers 51, 52, and 53)

must be set fo r a sca n to re star t pro pe rly fol lo w ing a p ause in the

scanning. See the LM9833 software for information on setting the

DPD register.

The num b er of f ull st e ps sk ipp e d a t t h e st ar t of a s c an may be on e

less than the Fulls teps to Skip at Start of Scan (re gisters 4A and

4B) setting.

The Scanning Step Size (registers 46 and 47) and Fast Feed

Step Size (registers 48 and 49) settings must be > 2.

When re verse is enab led, the LM983 3 always stops on Red (line

rate color). When reverse is disabled, it will stop on any color.

The contents of register 01 is not reset by the start of a new scan,

but it is updated to t he correct val ue after the fi rst line has be en

scanned. To reset this counter prior to starting a scan, the chip

can be briefly reset (register 7 = 0x20). Since res etting the chip

may have undesired consequences (turning the lamp off briefly,

interrupting DRAM refresh), it is also acceptable to simply wait

until r egister 01 start s increment ing. At tha t point the reg ister 01

data will be correct.

Gamma and gain/offset coefficient data should be written with

reg07=0 (idle).

When configured to do so, changes on the Paper Sense and

MISC I/O pins were supposed to generate USB Interrupts. This

functio na lity is n ot wor king at the time of this d atas hee t’s pub lica-

tion. The sol ut ion ( as d emo nst rat ed i n our Twain Driver softw ar e)

is to poll register 02 every 200 to 500ms. This uses very little

additional bandwidth compared to the USB interrupt solution.

Paper Senso r #2 Doesn’t Stop Se nsor When Hom ing: See Sec-

tion 12.16.

Mode Pixel Ra te Registers 0F to 18

Range

Pixel Rate Modes MCLK/24 0 - 23

Line Rate Modes MCLK/8 0 - 7

stepsize_ITA stepsize ITA+1

ITA

------------⋅

Applicati ons Information (Continued)

LM9833

39 www.national.com

Sensor (Offset and Shading)

16 x 16

Pixel-Rate

Multiplier

(Shading)

Pixel

Processing

(Horizontal

DPI adjust) Pixel

Processing

(Packing)

Buffer In Address Coun ter

Buffer Out Address Counter

DRAM

Address

Multiplexer

and

Controller 10 A0-A9

DRAM

Address Bus

D0-D15

DRAM

Data Bus

USB

Interface

Configuration

Registers

Line Buffer Controller Pause Scanning

Resume Scanning

Power

Transistors

3Current

Feedback

48MHz

System Clock

Generation

The Brains

System Synchronization and Control

Pixel Counter, Stepper Counter,

Lamp Counter, Command Interpreter

2D+, D-

Test

RAS

CAS

Stepper

Motor

Controller

PAPER

SENSORS 1,2

Test

Modes

Analog

Front

End

SDA

MISC I/O 1-6

SCL

Active/Suspend

Bus Power

Internal ROM

Pixel-Rate

Offset

Subtraction

Gamma

Table

Address

16 Bit

Pixel Data

16 16

External EEPROM

CMODE

Lamp Control

CRYSTAL

OUT CRYSTAL

24/48

CRYSTAL/ EXT

CLOCK

CCD

CIS

Image

Sensor

EXTERNAL

EEPROM

RESET

LM9833

3V (USB I/O)

Regulator

VREGULATOR

Digital Block Diagram

40 www.national.com

-1

Coarse Color

Balance PGAs

DACR

Offset

OSR

RED OS

from sensor CDS

OSGCDS

OSBCDS

x0.93

to x3

DACG

Offset

DACB

Offset

x1or x3

Static

Offset

DACs

-1

ø1

ø2

CP1

TR1

TR2

1.2V Bandgap

Reference

VBANDGAP CP2

x1or x3

Gain

Boost

Analog Front End Block Diagram

x0.93

to x3

x0.93

to x3

1.5V (CDS)

3.5V (CCD)

VREF LO

VREF MID

VREF HI Sensor

Clock

Generation

GREEN OS

from sensor

BLUE OS

from sensor

16 Bit

ADC 16

LM9833

41 www.national.com

+Vmotor

–Reset

Phase A

Invert

Set-Dominant

S/R Flipflop

+Vmotor

Stepper

Phase A

Stepper

Phase A

Stepper

Phase B

Stepper

Phase B

DAC code for

phase A 3

SENSE1

SENSE2

HIGH CURRENT

GND SENSE

1Ω

DAC A:

0.133V,

0.195V,

0.347V,

0.448V,

0.484V

Comparators need no hysteresis. SR flipflops are set periodi-

cally by pu lse from PWM Generato r. Flipflops ca n only be re set

after SR goes low when Reset (comparator output) is high

(VSENSE > VDAC).

Reset is level sensitive, not edge sensitive.

12MHz

÷1 to 256

÷64 PWM

Generator

0/64 to

63/64 high

time

–Reset

Set-Dominant

S/R Flipflop

Set

DAC code for

phase B

Phase B

Invert

TriState Stepper

Motor Out puts LM9833

Stepper Motor Current Control ler Block Diagram

External Components

LM9833

DAC B:

0.133V,

0.195V,

0.347V,

0.448V,

0.484V

42 www.national.com

Physical Dimensions (millimeters)

100-Pin Thin Plastic Quad FlatPac (JEDEC) (TQFP)

NS Package Number VJD100A

Order Number LM9833CCVJD

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LM9833 48-Bit Color 1200dpi USB Image Scanner