BQ24157SYFFR - Texas Instruments - Datasheet.Directory

CVREF

33 nF

CBOOT

PACK–

PACK+

CCSOUT

SCL

SDA

CSOUT

CSIN

PGND

I2C BUS

VAUX

HOST

SCL

SDA

STAT

VREF

STAT

PMID

VBUS

CIN

BOOT

OTG

RSNS

CCSIN

VBAT

1 Fm

4.7 Fm

10 kW

L 1 mH

CO1

22 Fm

0.1 mF

1mF

bq24157S

CO2

33 mF

OTG

10 kW

CIN

Product

Folder

Sample &

Buy

Technical

Documents

Tools &

Software

Support &

Community

bq24157S

SLUSB76B –FEBRUARY 2013–REVISED MAY 2015

bq24157S 1.55-A Fully Integrated Switch-Mode One-Cell Li-Ion Charger

With Full USB Compliance and USB-OTG Support

Not Recommended for New Designs

1 Features • Boost Mode Operation for USB OTG:

– Input Voltage Range (from Battery):

1• Integrated Power FETs for up to 1.55-A Charge 3.2 to 4.5 V

Rate – Output for VBUS: 5.05 V, 350 mA

• Spread Spectrum Frequency Control for Improved

EMI Performance • 2.1 × 2.0-mm, 20-Pin DSBGA Package

• High-Accuracy Voltage and Current Regulation • Pin-to-Pin Compatible With bq24157 and bq24158

– Input Current Regulation Accuracy: 2 Applications

±5% (100 mA and 500 mA) • Mobile and Smart Phones

– Charge Voltage Regulation Accuracy:

±0.5% (25°C), ±1% (0°C to 125°C) • MP3 Players

– Charge Current Regulation Accuracy: ±5% • Handheld Devices

• Factory Test-Mode for GSM Calibration Without a 3 Description

Battery The bq24157S is a compact, flexible, high-efficiency,

• Input Voltage Based Dynamic Power USB-friendly switch-mode charge management

Management (VIN DPM) device for single-cell Li-ion and Li-polymer batteries

• Bad Adaptor Detection and Rejection used in a wide range of portable applications. The

• Safety Limit Register for Maximum Charge charge parameters can be programmed through an

Voltage and Current Limiting I2C interface. The IC integrates a synchronous PWM

controller, power MOSFETs, input current sensing,

• High-Efficiency Mini-USB/AC Battery Charger for high-accuracy current and voltage regulation, and

Single-Cell Li-Ion and Li-Polymer Battery Packs charge termination, into a small DSBGA package.

• 20-V Absolute Maximum Input Voltage Rating The IC charges the battery in three phases:

• 6.5-V Maximum Operating Input Voltage conditioning, constant current, and constant voltage.

• Programmable Charge Parameters through I2CThe input current is automatically limited to the value

Compatible Interface (up to 3.4 Mbps): set by the host.

– Input Current Limit Device Information(1)

– VIN DPM Threshold PART NUMBER PACKAGE BODY SIZE (NOM)

– Fast-Charge/Termination Current bq24157S DSBGA (20) 2.10 mm × 2.00 mm

– Charge Regulation Voltage (3.5 to 4.44 V) (1) For all available packages, see the orderable addendum at

– Low Charge Current Mode Enable/Disable the end of the data sheet.

– Termination Enable/Disable Typical Application Circuit

• Synchronous Fixed-Frequency PWM Controller

Operating at 3 MHz With 0% to 99.5% Duty Cycle

• Automatic High Impedance Mode for Low Power

Consumption

• Robust Protection

– Reverse Leakage Protection Prevents Battery

Drainage

– Thermal Regulation and Protection

– Input/Output Overvoltage Protection A. Use RSNS = 68 mΩto program up to 1.25-A

• Status Output for Charging and Faults charge current, use RSNS = 55 mΩto

program up to 1.55-A charge current. For

• USB Friendly Boot-Up Sequence detailed instructions, refer to the Detailed

• Automatic Charging Design Procedure.

• Power Up System Without Battery

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

Not Recommended for New Designs

bq24157S

SLUSB76B –FEBRUARY 2013–REVISED MAY 2015

www.ti.com

Table of Contents

8.5 Register Maps......................................................... 26

1 Features.................................................................. 19 Application and Implementation ........................ 29

2 Applications ........................................................... 19.1 Application Information............................................ 29

3 Description............................................................. 19.2 Typical Application.................................................. 29

4 Revision History..................................................... 210 Power Supply Recommendations ..................... 34

5 Description (continued)......................................... 310.1 System Load After Sensing Resistor.................... 34

6 Pin Configuration and Functions......................... 311 Layout................................................................... 36

7 Specifications......................................................... 411.1 Layout Guidelines ................................................. 36

7.1 Absolute Maximum Ratings ..................................... 411.2 Layout Example .................................................... 36

7.2 ESD Ratings.............................................................. 412 Device and Documentation Support................. 38

7.3 Recommended Operating Conditions....................... 412.1 Device Support...................................................... 38

7.4 Thermal Information.................................................. 412.2 Documentation Support ........................................ 38

7.5 Electrical Characteristics........................................... 512.3 Trademarks........................................................... 38

7.6 Typical Performance Characteristics ........................ 812.4 Electrostatic Discharge Caution............................ 38

8 Detailed Description............................................ 11 12.5 Glossary................................................................ 38

8.1 Overview................................................................. 11 13 Mechanical, Packaging, and Orderable

8.2 Functional Block Diagrams ..................................... 12 Information ........................................................... 39

8.3 Feature Description................................................. 15 13.1 Package Summary................................................ 39

8.4 Device Functional Modes........................................ 24

4 Revision History

Changes from Revision A (June 2014) to Revision B Page

• Deleted "Safety Timer with Reset Control" from the Features .............................................................................................. 1

• Changed the package Features From: 2.25 x 2.65 mm To: 2.1 x 2.0 mm............................................................................ 1

• Changed the BODY SIZE values in the Device Information table ......................................................................................... 1

• Moved Tstg Storage Temperature From: ESD Ratings To: Absolute Maximum Ratings(1) (2) ............................................... 4

• Changed the title of Figure 3 From Battery Detection at Power Up To: Power Up in DEFAULT Mode................................ 8

• Changed "32S Mode" To: "HOST Mode" and 15 Minute Mode To: DEFAULT Mode in Figure 5......................................... 8

• Changed 32-second mode To: HOST mode in the Overview section ................................................................................. 11

• Changed 15-minute operation To: default mode in the Overview section ........................................................................... 11

• Changed 100-ms power-up delay From: No To: Yes in Table 1.......................................................................................... 11

• Changed Figure 19 .............................................................................................................................................................. 14

• Changed text From: "During the normal charging process with HOST control..." To: "During the normal charging

process with HOST control and termination enabled.." ....................................................................................................... 17

• Changed Title From: 15-Minute Safety Timer To: DEFAULT Mode ................................................................................... 17

• Changed 32-second mode To: HOST mode in USB Friendly Power Up ............................................................................ 17

• Changed 15-minute mode To: DEFAULT mode and 32-s mode To: HOST mode in Input Current Limiting at Power

Up ........................................................................................................................................................................................ 17

• Added a NOTE to the Application and Implementation section........................................................................................... 29

• Changed Figure 30 .............................................................................................................................................................. 33

• Changed Figure 31 .............................................................................................................................................................. 33

• Added Figure 30 .................................................................................................................................................................. 33

Changes from Original (February 2013) to Revision A Page

• Added the Handling Ratings table, Detailed Description section, Feature Description section, Device Functional

Modes section, Register Maps section, Application and Implementation section. Power Supply Recommendations

section, Layout section, Device and Documentation Support section, Mechanical, Packaging, and Orderable

Information section ................................................................................................................................................................. 1

Product Folder Links: bq24157S

PMID

PGND

PMID

PGND

PMID

PGND

STAT

SDA

OTG

VBUS

BOOT

SCL

CSIN

VREF

CSOUT

Not Recommended for New Designs

bq24157S

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SLUSB76B –FEBRUARY 2013–REVISED MAY 2015

5 Description (continued)

Charge is terminated based on battery voltage and user-selectable minimum current level. During normal

operation, the IC automatically restarts the charge cycle if the battery voltage falls below an internal threshold

and automatically enters sleep mode or high impedance mode when the input supply is removed. The charge

status can be reported to the host using the I2C interface. During the charging process, the IC monitors its

junction temperature (TJ) and reduces the charge current after TJincreases to about 125°C. To support a USB

OTG device, bq24157S can provide VBUS (5.05 V) by boosting the battery voltage. The IC is available in 20-pin

DSBGA package.

6 Pin Configuration and Functions

20-Bump DSBGA Package

(Top View)

Pin Functions

PIN I/O DESCRIPTION

NAME NUMBER

Bootstrap capacitor connection for the high-side FET gate driver. Connect a 33-nF ceramic capacitor (voltage rating ≥10 V)

BOOT A3 I/O from BOOT pin to SW pin.

CD E2 I Charge disable control pin. CD = 0, charge is enabled. CD = 1, charge is disabled and VBUS pin is high impedance to GND.

Charge current-sense input. Battery current is sensed across an external sense resistor. A 0.1-μF ceramic capacitor to PGND

CSIN E1 I is required.

Battery voltage and current sense input. Bypass it with a ceramic capacitor (minimum 0.1 μF) to PGND if there are long

CSOUT E4 I inductive leads to battery.

Boost mode enable control or input current limiting selection pin. When OTG is in active status, the device is forced to

operate in boost mode. It has higher priority over I2C control and can be disabled using the control register. At POR while in

OTG D4 I DEFAULT mode, the OTG pin is the default to be used as the input current limiting selection pin. The I2C register is ignored

at startup. When OTG = High, IIN_LIMIT = 500 mA and when OTG = Low, IIN_LIMIT = 100 mA.

PGND D1, D2, D3 Power ground

Connection point between reverse blocking FET and high-side switching FET. Bypass it with a minimum of 3.3-μF capacitor

PMID B1, B2, B3 I/O from PMID to PGND.

SCL A4 I I2C interface clock. Connect a 10-kΩpullup resistor to 1.8-V rail (VAUX= VCC_HOST)

SDA B4 I/O I2C interface data. Connect a 10-kΩpullup resistor to 1.8-V rail (VAUX= VCC_HOST)

Charge status pin. Pull low when charge in progress. Open drain for other conditions. During faults, a 128-μs pulse is sent

STAT C4 O out. STAT pin can be disabled by the EN_STAT bit in control register. STAT can be used to drive a LED or communicate with

a host processor.

SW C1, C2, C3 O Internal switch to output inductor connection

Charger input voltage. Bypass it with a 1-μF ceramic capacitor from VBUS to PGND. It also provides power to the load during

VBUS A1, A2 I/O boost mode.

Internal bias regulator voltage. Connect a 1-µF ceramic capacitor from this output to PGND. TI does not recommend an

VREF E3 O external load on VREF.

Product Folder Links: bq24157S

Not Recommended for New Designs

bq24157S

SLUSB76B –FEBRUARY 2013–REVISED MAY 2015

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7 Specifications

7.1 Absolute Maximum Ratings(1) (2)

over operating free-air temperature (unless otherwise noted) MIN MAX UNIT

Supply voltage (with respect to PGND(3)) VBUS; VPMID ≥VBUS – 0.3 V –2 20 V

Input voltage (with respect to PGND(3)) SCL, SDA, OTG, SLRST, CSIN, CSOUT, CD –0.3 7 V

PMID, STAT –0.3 20 V

Output voltage (with respect to PGND(3)) VREF -0.3 7 V

SW, BOOT –0.7 20 V

Voltage difference between CSIN and CSOUT inputs (V(CSIN) – V(CSOUT)) ±7 V

Voltage difference between BOOT and SW inputs (V(BOOT) – V(SW)) –0.3 7 V

Voltage difference between VBUS and PMID inputs (V(VBUS) – V(PMID)) –7 0.7 V

Voltage difference between PMID and SW inputs (V(PMID) – V(SW)) –0.7 20 V

Output sink STAT 10 10 mA

Output current (average) SW 1.55(2) A

TAOperating free-air temperature range –30 85 °C

Tstg Storage temperature range –45 150 °C

TJJunction temperature –40 125 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage

values are with respect to the network ground terminal unless otherwise noted.

(2) Duty cycle for output current should be less than 50% for 10-year lifetime when output current is above 1.5 A.

(3) All voltages are with respect to PGND if not specified. Currents are positive into, negative out of the specified terminal, if not specified.

For thermal limitations and considerations of packages, see Thermal Information .

7.2 ESD Ratings MIN MAX UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) 0 2000

Electrostatic

V(ESD) V

discharge Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) 0 500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions MIN NOM MAX UNIT

VBUS Supply voltage, bq24157S 4 6(1) V

TJOperating junction temperature range –40 125 °C

(1) The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BOOST or SW pins. A tight

layout minimizes switching noise.

7.4 Thermal Information bq24157S

THERMAL METRIC(1) UNIT

YFF (20 PINS)

RθJA Junction-to-ambient thermal resistance 85

RθJC(top) Junction-to-case (top) thermal resistance 25

RθJB Junction-to-board thermal resistance 55 °C/W

ψJT Junction-to-top characterization parameter 4

ψJB Junction-to-board characterization parameter 50

RθJC(bot) Junction-to-case (bottom) thermal resistance N/A

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

Product Folder Links: bq24157S

Not Recommended for New Designs

bq24157S

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SLUSB76B –FEBRUARY 2013–REVISED MAY 2015

7.5 Electrical Characteristics

Circuit of Figure 28, VBUS = 5 V, HZ_MODE = 0, OPA_MODE = 0 (CD = 0), TJ= –40°C to 125°C, TJ= 25°C for typical

values (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

INPUT CURRENTS

VBUS > VBUS(min), PWM switching 10 mA

I(VBUS) VBUS supply current control VBUS > VBUS(min), PWM not switching 5

0°C < TJ< 85°C, CD = 1 or HZ_MODE = 1 15 23 μA

0°C < TJ< 85°C, V(CSOUT) = 4.2 V, high impedance

Ilgk Leakage current from battery to VBUS pin 5 μA

mode, VBUS = 0 V

Battery discharge current in high impedance 0°C < TJ< 85°C, V(CSOUT) = 4.2 V, high impedance 23 μA

mode, (CSIN, CSOUT, SW pins) mode, V = 0 V, SCL, SDA, OTG = 0 V or 1.8 V

VOLTAGE REGULATION

V(OREG) Output regulation voltage programable range Operating in voltage regulation, programmable 3.5 4.44 V

TA= 25°C –0.5% 0.5%

Voltage regulation accuracy TA= -40°C to 125°C –1% 1%

CURRENT REGULATION (FAST CHARGE)

V(LOWV) ≤V(CSOUT) < V(OREG),

IO(CHARGE) Output charge current programmable range VBUS > V(SLP), R(SNS) = 68 mΩ, LOW_CHG = 0, 550 1250 mA

Programmable

VLOWV ≤VCSOUT < VOREG, VBUS > VSLP,325 350

RSNS= 68 mΩ, LOW_CHG = 1, OTG = High

Low charge current (default after POR in 15 mA

min mode) VLOWV ≤VCSOUT < VOREG, VBUS > VSLP,550 569

RSNS= 68 mΩ, LOW_CHG = 0, OTG = High

Regulation accuracy of the voltage across 37.4 mV ≤V(IREG)< 44.2 mV –3.5% 3.5%

R(SNS) (for charge current regulation) 44.2 mV ≤V(IREG) –3% 3%

V(IREG) = IO(CHARGE) × R(SNS)

WEAK BATTERY DETECTION

V(LOWV) Weak battery voltage threshold programmable Adjustable using I2C control 3.4 3.7 V

range2 (1)

Weak battery voltage accuracy –5% 5%

Hysteresis for V(LOWV) Battery voltage falling 100 mV

Deglitch time for weak battery threshold Rising voltage, 2-mV overdrive, tRISE = 100 ns 30 ms

CD, OTG, AND SLRST PIN LOGIC LEVEL

VIL Input low threshold level 0.4 V

VIH Input high threshold level 1.3 V

I(bias) Input bias current Voltage on control pin is 5 V 1.0 µA

CHARGE TERMINATION DETECTION

Termination charge current programmable V(CSOUT) > V(OREG) – V(RCH),

I(TERM) 50 400 mA

range VBUS > V(SLP), R(SNS) = 68 mΩ, programmable

Deglitch time for charge termination Both rising and falling, 2-mV overdrive, 30 ms

tRISE, tFALL = 100 ns

3.4 mV ≤V(IREG_TERM) ≤6.8 mV –15% 15%

Regulation accuracy for termination current

across R(SNS) 6.8 mV < V(IREG_TERM) ≤17 mV –10% 10%

V(IREG_TERM) = IO(TERM) × R(SNS) 17 mV < V(IREG_TERM) ≤27.2 mV –5.5% 5.5%

BAD ADAPTOR DETECTION

VIN(min) Input voltage lower limit Bad adaptor detection 3.6 3.8 4.0 V

Deglitch time for VBUS rising above VIN(min) Rising voltage, 2-mV overdrive, tRISE = 100 ns 30 ms

Hysteresis for VIN(min) Input voltage rising 100 200 mV

ISHORT Current source to GND During bad adaptor detection 20 30 40 mA

tINT Detection Interval Input power source detection 2 s

INPUT BASED DYNAMIC POWER MANAGEMENT

Input Voltage DPM threshold programmable

VIN_DPM 4.2 4.76 V

range

VIN DPM threshold accuracy –3% 1%

(1) While in DEFAULT mode, if a battery that is charged to a voltage higher than this voltage is inserted, the charger enters Hi-Z mode and

awaits I2C commands.

Product Folder Links: bq24157S

Not Recommended for New Designs

bq24157S

SLUSB76B –FEBRUARY 2013–REVISED MAY 2015

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Electrical Characteristics (continued)

Circuit of Figure 28, VBUS = 5 V, HZ_MODE = 0, OPA_MODE = 0 (CD = 0), TJ= –40°C to 125°C, TJ= 25°C for typical

values (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

INPUT CURRENT LIMITING

TJ= 0°C to 125°C 88 93 98

IIN = 100 mA mA

TJ= –40°C to 125°C 86 93 98

IIN_LIMIT Input current limiting threshold TJ= 0°C to 125°C 450 475 500

IIN = 500 mA mA

TJ= –40°C to 125°C 440 475 500

VREF BIAS REGULATOR

VBUS > VIN(min) or V(CSOUT) > VBUS(min),

VREF Internal bias regulator voltage 2 6.5 V

I(VREF) = 1 mA, C(VREF) = 1 μF

VREF output short current limit 30 mA

BATTERY RECHARGE THRESHOLD

V(RCH) Recharge threshold voltage Below V(OREG) 100 120 150 mV

V(SCOUT) decreasing below threshold,

Deglitch time 130 ms

tFALL = 100 ns, 10-mV overdrive

STAT OUTPUTS

Low-level output saturation voltage, STAT pin IO= 10 mA, sink current 0.55 V

VOL(STAT) High-level leakage current for STAT Voltage on STAT pin is 5 V 1 μA

I2C BUS LOGIC LEVELS AND TIMING CHARACTERISTICS

VOL Output low threshold level IO= 10 mA, sink current 0.4 V

VIL Input low threshold level V(pullup) = 1.8 V, SDA and SCL 0.4 V

VIH Input high threshold level V(pullup) = 1.8 V, SDA and SCL 1.2 V

I(BIAS) Input bias current V(pullup) = 1.8 V, SDA and SCL 1 μA

f(SCL) SCL clock frequency 3.4 MHz

BATTERY DETECTION

Battery detection current before charge done Begins after termination detected,

I(DETECT) –0.5 mA

(sink current) (2) V(CSOUT) ≤V(OREG)

tDETECT Battery detection time 262 ms

SLEEP COMPARATOR

Sleep-mode entry threshold,

V(SLP) 2.3 V ≤V(CSOUT) ≤V(OREG), VBUS falling 0 40 100 mV

VBUS – VCSOUT

V(SLP_EXIT) Sleep-mode exit hysteresis 2.3 V ≤V(CSOUT) ≤V(OREG) 140 200 260 mV

Deglitch time for VBUS rising above V(SLP) +Rising voltage, 2-mV overdrive, tRISE = 100 ns 30 ms

V(SLP_EXIT)

UNDERVOLTAGE LOCKOUT (UVLO)

UVLO IC active threshold voltage VBUS rising – exits UVLO 3.05 3.3 3.55 V

UVLO(HYS) IC active hysteresis VBUS falling below UVLO – enters UVLO 120 150 mV

Power up delay 140 ms

PWM

Voltage from BOOT pin to SW pin During charge or boost operation 6.5 V

Internal top reverse blocking MOSFET on- IIN(LIMIT) = 500 mA, measured from VBUS to PMID 180 250

resistance

Internal top N-channel switching MOSFET on- Measured from PMID to SW, 120 250 mΩ

resistance VBOOT – VSW= 4 V

Internal bottom N-channel MOSFET on- Measured from SW to PGND 110 210

resistance

f(OSC) Oscillator frequency 3.0 MHz

Frequency accuracy –10% 10%

D(MAX) Maximum duty cycle 99.5%

D(MIN) Minimum duty cycle 0

Synchronous mode to non-synchronous mode Low-side MOSFET cycle-by-cycle current sensing 100 mA

transition current threshold(2)

(2) Bottom N-channel FET always turns on for approximately 30 ns, and then turns off if current is too low.

Product Folder Links: bq24157S

Not Recommended for New Designs

bq24157S

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SLUSB76B –FEBRUARY 2013–REVISED MAY 2015

Electrical Characteristics (continued)

Circuit of Figure 28, VBUS = 5 V, HZ_MODE = 0, OPA_MODE = 0 (CD = 0), TJ= –40°C to 125°C, TJ= 25°C for typical

values (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CHARGE MODE PROTECTION

VOVP_IN_USB Input VBUS OVP threshold voltage VBUS threshold to turn off converter during charge 6.3 6.5 6.7 V

V(CSOUT) threshold over V(OREG) to turn off charger

Output OVP threshold voltage 110 117 121

during charge

VOVP %VOREG

V(OVP) hysteresis Lower limit for V(CSOUT) falling from above V(OVP) 11

ILIMIT Cycle-by-cycle current limit for charge Charge mode operation 1.8 2.4 3.0 A

Trickle to fast charge threshold V(CSOUT) rising 2.0 2.1 2.2 V

VSHORT VSHORT hysteresis V(CSOUT) falling below VSHORT 100 mV

ISHORT Trickle charge charging current V(CSOUT) ≤VSHORT) 20 30 40 mA

BOOST MODE OPERATION FOR VBUS (OPA_MODE = 1, HZ_MODE = 0)

VBUS_B Boost output voltage (to VBUS pin) 2.5 V < V(CSOUT) < 4.5 V 5.05 V

Boost output voltage accuracy Including line and load regulation –3% 3%

VBUS_B = 5.05 V, 3.3 V < V(CSOUT) < 4.5 V,

IBO Maximum output current for boost 350 mA

TJ= 0°C – 125°C

IBLIMIT Cycle by cycle current limit for boost VBUS_B = 5.05 V, 2.5 V < V(CSOUT) < 4.5 V 1.0 A

Overvoltage protection threshold for boost Threshold over VBUS to turn off converter during 5.8 6.0 6.2 V

(VBUS pin) boost

VBUSOVP VBUSOVP hysteresis VBUS falling from above VBUSOVP 162 mV

Maximum battery voltage for boost V(CSOUT) rising edge during boost 4.75 4.9 5.05 V

(CSOUT pin)

VBATMAX VBATMAX hysteresis V(CSOUT) falling from above VBATMAX 200 mV

During boosting 2.5 V

Minimum battery voltage for boost

VBATMIN (CSOUT pin) Before boost starts 2.9 3.05 V

Boost output resistance at high-impedance CD = 1 or HZ_MODE = 1 217 kΩ

mode (from VBUS to PGND)

PROTECTION

TSHTDWN) Thermal trip 165

Thermal hysteresis 10 °C

TCF Thermal regulation threshold Charge current begins to reduce 120

Product Folder Links: bq24157S

500 s/divμ

VBUS

1 V/div

200 mA/div

BUS

IBUS

VBUS

OTG

2 V/div

200 mA/div

BAT

1 s/div

OTG

IBAT

DEFAULT Mode HOST Mode

Write Command

VBAT

2 V/div

VBUS

4 V/div

100 ms/div

VSW

5 V/div

IBUS

100 mA/div

VBUS

2 V/div

VSW

2 V/div

20 mA/div

BUS

10 ms/div

2 s/divμ

VSW

5 V/div

I Inductor

500 mA/div

VSW

IND

200 s/divμ

VSW

5 V/div

200 mA/div

BAT

VSW

IBAT

Not Recommended for New Designs

bq24157S

SLUSB76B –FEBRUARY 2013–REVISED MAY 2015

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7.6 Typical Performance Characteristics

Using circuit shown in Figure 28, TA= 25°C, unless otherwise specified.

VBUS = 5 V VBAT = 3.5 V VIN = 5 V VBAT = 3.2 V ICHG = 950 mA

Figure 1. Cycle by Cycle Current Limiting In Charge Mode Figure 2. Charge Current Ramp Up

Overload Operation No Input Current Limit

VBUS = 5 V No Battery Connected VBUS = 5 V at 8 mA VBAT = 3.2 V IIN_limit = 100 mA

Termination Disabled ICHG = 550 mA

Figure 3. Power Up in DEFAULT Mode Figure 4. Poor Source Detection

OTG Control, DEFAULT Mode: VBUS = 5 V, VBAT = 3.1 V, VBUS = 5 V at 500 mA VBAT = 3.5 V ICHG = 1550 mA

IIN_limit = 100 and 500 mA VIN_DPM = 4.52 V

I2C Control, HOST Mode: IIN_limit = 100 mA

Figure 5. Input Current Control Figure 6. VIN Based DPM

Product Folder Links: bq24157S

100 s/divμ

VBUS

100 mV/div

5.05 V Offset

VSW

5 V/div

0.1 A/div

BAT

VBAT

0.2 V/div

3.5 V Offset

VBUS

2 V/div

VSW

5 V/div

0.5 A/div

BUS

10 ms/div

VBUS

VSW

IBUS

OTG

5 V/div

100 s/divμ

VBUS

200 mV/div,

5.05 V Offset

VSW

5 V/div

500 mV/div

BAT

VBAT

200 mV/div,

3.5 V Offset

5 ms/div

VBUS

5 V/div

VSW

5 V/div

0.5 A/div

BUS

VBUS

VSW

VPMID

2 V/div

IBUS

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5

Efficiency (%)

Charge Current (A)

VBAT = 3.0 V

VBAT = 3.6 V

VBAT = 4.2 V

5 s/divμ

AC Coupled

VBUS

100 mV/div

AC Coupled

VSW 2 V/div

I Inductor

0.2 A/div

VBUS

VSW

VBAT

AC Coupled

VBAT

100 mV/div

IND

Not Recommended for New Designs

bq24157S

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SLUSB76B –FEBRUARY 2013–REVISED MAY 2015

Typical Performance Characteristics (continued)

Using circuit shown in Figure 28, TA= 25°C, unless otherwise specified.

VBUS = 5.05 V VBAT = 3.5 V IBUS = 42 mA

Figure 8. Boost Waveform (PFM Mode)

Figure 7. Charger Efficiency

VBUS = 5.05 V VBAT = 3.5 V VBUS = 5.05 V VBAT = 3.5 V IBUS = 0 to 360 mA

ILOAD (at VBUS) = 5 to 450 mA

Figure 9. VBUS Overload Waveforms (Boost Mode) Figure 10. Load Step Up Response (Boost Mode)

VBUS = 4.5 V (Charge Mode) VBUS = 5.1 V (Boost Mode)

VBUS = 5.05 V VBAT = 3.5 V IBUS = 0 to 217 mA VBAT = 3.5 V, IIN_LIM = 500 mA, (HOST Mode)

Figure 12. Boost to Charge Mode Transition (OTG Control)

Figure 11. Load Step Up Response (Boost Mode)

Product Folder Links: bq24157S

0 50 100 150 200

Load Current at VBUS (mA)

5.01

5.02

5.03

5.04

5.05

5.06

5.07

5.08

5.09

VBUS

VBAT = 2.7 V

VBAT = 3.6 V

VBAT = 4.2 V

200 ns/div

AC Coupled

10 mV/div

AC Coupled

10 mA/div

VOUT

AC Coupled

50 mA/div

IBAT

INDUCTOR

0 50 100 150 200

Efficiency (%)

Load Current at VBUS (mA)

VBAT = 2.7 V

VBAT = 3.6 V

VBAT = 4.2 V

5.01

5.02

5.03

5.04

5.05

5.06

5.07

5.08

5.09

2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2

VBUS (V)

VBAT (V)

IBUS = 50 mA

IBUS = 100 mA

IBUS = 200 mA

IBUS = 375 mA

Not Recommended for New Designs

bq24157S

SLUSB76B –FEBRUARY 2013–REVISED MAY 2015

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Typical Performance Characteristics (continued)

Using circuit shown in Figure 28, TA= 25°C, unless otherwise specified.

Figure 13. Boost Efficiency Figure 14. Line Regulation For Boost

ICHG = 1.2 A

Figure 16. Output Ripple for Voltage and Current

Figure 15. Load Regulation for Boost

Product Folder Links: bq24157S

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SLUSB76B –FEBRUARY 2013–REVISED MAY 2015

8 Detailed Description

8.1 Overview

For a current-restricted power source, such as a USB host or hub, a high-efficiency converter is critical to fully

use the input power capacity for quickly charging the battery. Due to the high efficiency for a wide range of input

voltages and battery voltages, the switch mode charger is a good choice for high speed charging with less power

loss and better thermal management than a linear charger.

The bq24157S includes highly integrated synchronous switch-mode chargers, featuring integrated FETs and

small external components, targeted at extremely space-limited portable applications powered by 1-cell Li-Ion or

Li-polymer battery pack. Furthermore, the device has bidirectional operation to achieve boost function for USB-

OTG support.

The bq24157S has three operation modes: charge mode, boost mode, and high impedance mode. In charge

mode, the IC supports a precision Li-ion or Li-polymer charging system for single-cell applications. In boost

mode, the IC boosts the battery voltage to VBUS for powering attached OTG devices. In high impedance mode,

the IC stops charging or boosting and operates in a mode with very-low current from VBUS or battery, to

effectively reduce the power consumption when the portable device is in standby mode. Through I2C

communication with a host (referred to as HOST mode), the IC achieves smooth transition among the different

operation modes. During DEFAULT operation, the charger will still charge the battery but uses each register's

default values.

Table 1. Device Features

Features bq24157S

VOVP (V) 6.5

D4 pin definition OTG

ICHARGE(MAX) at POR in DEFAULT mode with R(SNS) = 68 mΩand OTG = High 550 mA

ICHARGE(MAX) in HOST mode with R(SNS) = 68 mΩand safety limit register increased from default (A) 1.5

Output regulation voltage at POR (V) 3.54

Boost function Yes

100 mA (OTG = Low);

Input current limit in DEFAULT mode 500 mA (OTG = High)

Battery detection at power up No

6AH

I2C address

PN1 (bit4 of 03H) 1

PN0 (bit3 of 03H) 0

Safety timer and WD timer Disabled

100-ms power-up delay Yes

Spread Spectrum Yes

Factory test mode Yes

Product Folder Links: bq24157S

bq24157S

CHARGE CONTROL

TIMER and DISPLAY

LOGIC

*Sleep

CSOUT

CSIN

STAT

PGND

PGND SCL

NMOS NMOS

NMOS

PMID

SDA

( I 2 C Control )

Decoder

DAC

Q2 Q 3

VREF

PMID

Q 1

BOOT

REFERNCES

and BIAS

PMID

VBUS SW

VPMID

PGND

VBUS

VPMID

OTG (bq 24153 /8)

ISHORT

VREF

LINEAR _CHG

TCF

IOCHARGE

VOREG

VREF

Charge

Pump

VREF 1

IIN _ LIMIT

OSC

VOVP_IN

VBUS

VUVLO

VBUS

VIN(MIN)

VBUS

TSHTDWN

CBC

Current

Limiting

PWM

Controller

ILIMIT

VBAT

VBUS

VOUT

V CSIN

*Battery OVP

VOUT

VOVP

VBUS UVLO

Poor Input

Source

VBUS OVP

Thermal

Shutdown

*Recharge+

VOUT

VOREG - VRCH

*Signal Deglitched

VCSIN

ITERM *

Termination

PWM _ CHG

*PWM Charge

Mode

VBAT

SHORT

VIN _ DPM

SLRST(bq24156)

VOUT

Not Recommended for New Designs

bq24157S

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8.2 Functional Block Diagrams

Figure 17. Function Block Diagram of bq24157S in Charge Mode

Product Folder Links: bq24157S

bq24157S

CHARGE CONTROL,

TIMER and DISPLAY

LOGIC

*Low Battery

CSOUT

CSIN

STAT

PGND

SCL

NMOS NMOS

NMOS

PMID

SDA

(I2 C Control)

Decoder

DAC

VREF

PMID

BOOT

REFERNCES

and BIAS

PMID

VBUS SW

VPMID

PGND

VBUS

VPMID

OTG

VBUS_B VREF

Charge

Pump

VREF 1

IBO

OSC

VBUSOVP

VBUS

TSHTDWN

CBC

Current

Limiting

PWM

Controller

IBLIMIT

VBAT

VBATMIN

VOUT

*Battery OVP

VOUT

VBATMAX

VBUS OVP

Thermal

Shutdown

*Signal Deglitched

PWM _BOOST

-75 mA

PFM Mode

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Functional Block Diagrams (continued)

Figure 18. Function Block Diagram of bq24157S in Boost Mode

Product Folder Links: bq24157S

VCSOPUT <V SHORT ? Yes

Enable I SHORT

Indicate Charge- In -

Progress

Regulate

Input Current , Charge

Current or Voltage

High Impedance Mode or Host

Controlled Operation Mode

Termination Enabled

ITERM detected

and V

CSOUT >V OREG -V RCH

VCSOUT < V OREG -

VRCH ?

CSOUT < V SHORT ?

Yes

Indicate Short

Circuit condition

Yes

Indicate DONE

Charge Complete

VBUS < V IN ( MIN ) ?

Yes

Indicate Power

not Good

Disable Charge

Wait Mode

Delay TINT

VBUS < V IN ( MIN ) ?

Yes

VCSOUT < VOREG -

VRCH ?

Enable I DETECT for

tDETECT

Turn Off Charge

Reset Charge

Parameters

Battery Removed

Wait Mode

Delay TINT

Yes

VCSOUT < V LOWV

Power Up

VBUS > V UVLO

Yes

Any Charge State/CE = HIGH

Charge Configure

Mode

Disable Charge

/CE = LOW

POR

Load I2C Registers

with Default Value

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bq24157S

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Functional Block Diagrams (continued)

Figure 19. Operational Flow Chart of bq24157S in Charge Mode

Product Folder Links: bq24157S

AdaptorDetectionControl

VBUS

START

Adpator

VBUS

GND

PGND

ISHORT

(30mA)

Deglitch

30ms

VIN(MIN)

VIN_GOOD

VIN_POOR

Delay

TINT

VIN

Not Recommended for New Designs

bq24157S

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SLUSB76B –FEBRUARY 2013–REVISED MAY 2015

8.3 Feature Description

8.3.1 Input Voltage Protection

8.3.1.1 Input Overvoltage Protection

The IC provides built-in input overvoltage protection to protect the device and other components against damage

if the input voltage (voltage from VBUS to PGND) goes too high. When an input overvoltage condition is

detected, the IC turns off the PWM converter, sets fault status bits, and sends out a fault pulse from the STAT

pin. Once VBUS drops below the input overvoltage exit threshold, the fault is cleared and the charge process

resumes.

8.3.1.2 Bad Adaptor Detection/Rejection

Although not shown in Figure 20, at power-on-reset (POR) of VBUS, the IC performs the bad adaptor detection

by applying a current sink to VBUS. If the VBUS is higher than VIN(MIN) for 30 ms, the adaptor is good and the

charge process begins. If the VBUS drops below VIN(MIN), a bad adaptor is detected. Then, the IC disables the

current sink, sends a send fault pulse in FAULT pin, and sets the bad adaptor flag (B2 – B0 = 011 for register

00H). After a delay of TINT, the IC repeats the adaptor detection process, as shown in Figure 20 and Figure 21.

Figure 20. Bad Adaptor Detection Circuit

Product Folder Links: bq24157S

Charge Command

(HostControlorVBUS

RampsUp)

Bad AdaptorDetected

PulsingSTAT Pin

SetBad AdaptorFlag

VBUS>VIN(MIN)?

Yes

Enable AdaptorDetection

Start 30ms Timer

EnableInputCurrentSink

(30mA, toGND)

30ms Timer

Expired?

Yes

Delay TINT

(2 Seconds)

Good AdaptorDetected

Disable AdaptorDetection

ChargeStart

EnableVIN BasedDPM

Delay 10mS

Not Recommended for New Designs

bq24157S

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Feature Description (continued)

Figure 21. Bad Adaptor Detection Scheme Flow Chart

8.3.1.3 Sleep Mode

The IC enters the low-power sleep mode if the VBUS pin voltage falls below the sleep-mode entry threshold,

VCSOUT + VSLP, and VBUS is higher than the bad adaptor detection threshold, VIN(MIN). This feature prevents

draining the battery during the absence of VBUS. During sleep mode, both the reverse blocking switch Q1 and

PWM are turned off.

8.3.1.4 Input Voltage Based DPM (Special Charger Voltage Threshold)

During the charging process, if the input power source is not able to support the programmed or default charging

current, the VBUS voltage will decrease. After the VBUS drops to VIN_DPM (default 4.52 V), the charge current

begins to taper down to prevent any further drop of VBUS. When the IC enters this mode, the charge current is

lower than the set value and the special charger bit is set (B4 in register 05H). This feature makes the IC

compatible with adapters having different current capabilities.

8.3.2 Battery Protection

8.3.2.1 Output Overvoltage Protection

The IC provides a built-in overvoltage protection to protect the device and other components against damage if

the battery voltage goes too high, as when the battery is suddenly removed. When an overvoltage condition is

detected, the IC turns off the PWM converter, sets fault status bits, and sends out a fault pulse from the STAT

pin. When V(CSOUT) drops to the battery overvoltage exit threshold, the fault is cleared and the charge process

resumes.

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Feature Description (continued)

8.3.2.2 Battery Short Protection

During the normal charging process, if the battery voltage is lower than the short-circuit threshold, VSHORT, the

charger operates in short circuit mode with a lower charge rate of ISHORT.

8.3.2.3 Battery Detection in HOST Mode

For applications with removable battery packs, the IC provides a battery absent detection scheme to reliably

detect insertion or removal of battery packs.

During the normal charging process with HOST control and termination enabled, when the voltage at the CSOUT

pin is above the battery recharge threshold, VOREG – VRCH, and the termination charge current is detected, the IC

turns off the PWM charge and enables a discharge current, IDETECT, for a period of tDETECT, (262-ms typical), then

checks the battery voltage. If the battery voltage is still above the recharge threshold after tDETECT, the battery is

present. On the other hand, if the battery voltage is below the battery recharge threshold, the battery is absent.

Under this condition, the charge parameters (such as input current limit) are reset to the default values and

charge resumes after a delay of tINT. This function ensures that the charge parameters are reset whenever the

battery is replaced.

8.3.3 DEFAULT Mode

After the battery and input bus voltages are removed from the IC and replaced, the bq24157S enters DEFAULT

mode until I2C communication begins.

8.3.4 USB Friendly Power Up

Prior to POR, if the host continues to write the TMR_RST bit to 1, to stay in HOST mode, then at POR, the

charger enters normal charge mode (using the desired control bits). If not in HOST mode at POR, the charge will

operate with default bit values, until the host updates the control registers.

The default control bits set the charging current and regulation voltage low as a safety feature to avoid violating

USB specifications and overcharging any of the Li-Ion chemistries, while the host has lost communication. The

input current limiting is described in the following sections.

8.3.5 Input Current Limiting at Power Up

The input current sensing circuit and control loop are integrated into the IC. When operating in DEFAULT mode,

the OTG pin logic level sets the input current limit to 100 mA for a logic low and 500 mA for a logic high. In

HOST mode, the input current limit is set by the programmed control bits in register 01H.

8.3.6 Factory Mode

The factory mode can be enabled only when the battery is removed. This can be done through an I2C register 05

bit 6 (see Table 9). The purpose of the mode is to operate the phone in a GSM phone call with no-battery

connected and do a calibration of the system. Setting the factory mode bit enables the following changes:

• 20X ICHG amp is disabled – that is, output current limit is disabled

• Cycle-by-cycle HS current limit threshold is doubled (current typical is 2.4 A, shifts to 4.8 A)

• CCM mode is always enabled (because the current could go from 0 to full GSM pulse)

8.3.7 Spread Spectrum Mode

The purpose of the spread spectrum clock modulation is to reduce EMI. In the spread spectrum mode, the

switching frequency is not fixed to 3 MHz. It is instead shifted by ±10% from the fixed 3-MHz switching

frequency. The shift is happening in eight steps, four steps in the upper range and four steps in the lower range

every 170 µs. By modulating the clock frequency, the energy of the switching converter’s EMI is distributed over

a wider range of frequencies thereby lowering the magnitude of EMI at 3 MHz ±10% as well as harmonic

frequencies.

Product Folder Links: bq24157S

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Feature Description (continued)

8.3.8 PWM Controller in Charge Mode

The IC provides an integrated, fixed 3-MHz frequency voltage-mode controller to regulate charge current or

voltage. This type of controller is used to improve line transient response, thereby, simplifying the compensation

network used for both continuous and discontinuous current conduction operation. The voltage and current loops

are internally compensated using a Type-III compensation scheme that provides enough phase margin for stable

operation, allowing the use of small ceramic capacitors with a low ESR. The device operates between 0% to

99.5% duty cycles.

The IC has back-to-back common-drain N-channel FETs at the high side and one N-channel FET at the low side.

The input N-FET (Q1) prevents battery discharge when VBUS is lower than VCSOUT. The second high-side N-FET

(Q2) is the switching control switch. A charge pump circuit is used to provide gate drive for Q1, while a bootstrap

circuit with an external bootstrap capacitor is used to supply the gate drive voltage for Q2.

Cycle-by-cycle current limit is sensed through the FETs Q2 and Q3. The threshold for Q2 is set to a nominal 2.4-

A peak current. The low-side FET (Q3) also has a current limit that decides if the PWM controller will operate in

synchronous or non-synchronous mode. This threshold is set to 100 mA and it turns off the low-side N-channel

FET (Q3) before the current reverses, preventing the battery from discharging. Synchronous operation is used

when the current of the low-side FET is greater than 100 mA to minimize power losses.

8.3.9 Battery Charging Process

At the beginning of precharge, while battery voltage is below the V(SHORT) threshold, the IC applies a short-circuit

current, I(SHORT), to the battery. When the battery voltage is above VSHORT and below VOREG, the charge current

ramps up to fast charge current, IOCHARGE, or a charge current that corresponds to the input current of IIN_LIMIT.

The slew rate for fast charge current is controlled to minimize the current and voltage overshoot during transient.

Both the input current limit, IIN_LIMIT, and fast charge current, IOCHARGE, can be set by the host. When the battery

voltage reaches the regulation voltage, VOREG, the charge current is tapered down, as shown in Figure 27. The

voltage regulation feedback occurs by monitoring the battery-pack voltage between the CSOUT and PGND pins.

In HOST mode, the regulation voltage is adjustable (3.5 to 4.44 V) and is programmed through I2C interface. In

DEFAULT mode, the regulation voltage is fixed at 3.54 V.

The IC monitors the charging current during the voltage regulation phase. If termination is enabled, during the

normal charging process with HOST control, after the voltage at the CSOUT pin is above the battery recharge

threshold, VOREG – VRCH for the 32-ms (typical) deglitch period, and the termination charge current ITERM is

detected, the IC turns off the PWM charge and enables a discharge current, IDETECT, for a period of tDETECT (262-

ms typical), then checks the battery voltage. If the battery voltage is still above the recharge threshold after

tDETECT, the battery charging is complete. The battery detection routine is used to ensure termination did not

occur because the battery was removed. After 40 ms (typical) for synchronization purposes of the EOC state and

the counter, the status bit and pin are updated to indicate charging has completed. The termination current level

is programmable. To disable the charge current termination, the host can set the charge termination bit (TE) of

charge control register to 0, refer to I2C Update Sequence for details.

A new charge cycle is initiated when one of the following conditions is detected:

• The battery voltage falls below the V(OREG) – V(RCH) threshold.

• VBUS POR, if battery voltage is below the V(LOWV) threshold.

• CE bit toggle or RESET bit is set (host controlled)

8.3.10 Thermal Regulation and Protection

To prevent overheating of the chip during the charging process, the IC monitors the junction temperature, TJ, of

the die and begins to taper down the charge current after TJreaches the thermal regulation threshold, TCF. The

charge current is reduced to 0 when the junction temperature increases approximately 10°C above TCF. In any

state, if TJexceeds TSHTDWN, the IC suspends charging. In thermal shutdown mode, PWM is turned off and all

timers are frozen. Charging resumes when TJfalls below TSHTDWN by approximately 10°C.

Product Folder Links: bq24157S

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Feature Description (continued)

8.3.11 Charge Status Output, STAT Pin

The STAT pin is used to indicate operation conditions. STAT is pulled low during charging when EN_STAT bit in

control register (00H) is set to 1. Under other conditions, STAT pin behaves as a high impedance (open-drain)

output. Under fault conditions, a 128-µs pulse will be sent out to notify the host. The status of STAT pin at

different operation conditions is summarized in Table 2. The STAT pin can be used to drive an LED or

communicate to the host processor.

Table 2. STAT Pin Summary

Charge State Stat

Charge in progress and EN_STAT = 1 Low

Other normal conditions Open-drain

Charge mode faults: Timer fault, sleep mode, VBUS or battery overvoltage, poor input source, VBUS 128-μs pulse, then open-drain

UVLO, no battery, thermal shutdown

Boost mode faults: Timer fault, over load, VBUS or battery overvoltage, low battery voltage, thermal 128-μs pulse, then open-drain

shutdown

8.3.12 Control Bits in Charge Mode

8.3.12.1 CE Bit (Charge Mode)

The CE bit in the control register is used to disable or enable the charge process. A low logic level (0) on this bit

enables the charge and a high logic level (1) disables the charge.

8.3.12.2 RESET Bit

The RESET bit in the Battery Termination/Fast Charge Current register is used to reset all the charge

parameters. Writing 1 to the RESET bit will reset all the charge parameters to default values except the safety

limit register, and RESET bit is automatically cleared to 0 when the charge parameters are reset. It is designed

for charge parameter reset before charge starts and TI does not recommended to set the RESET bit while

charging or boosting are in progress.

8.3.12.3 OPA_MODE Bit

OPA_MODE is the operation mode control bit. When OPA_MODE = 0, the IC operates as a charger; if

HZ_MODE is set to 0, refer to Table 3 for details. When OPA_MODE = 1 and HZ_MODE = 0, the IC operates in

boost mode.

Table 3. Operation Mode Summary

OPA_MODE HZ_MODE Operation Mode

Charge (no fault)

0 0 Charge configure (fault, Vbus > UVLO)

High impedance (Vbus < UVLO)

Boost (no faults)

1 0 Any fault go to charge configure mode

X 1 High impedance

8.3.13 Control Pins in Charge Mode

8.3.13.1 CD Pin (Charge Disable)

The CD pin is used to disable the charging process. When the CD pin is low, charge is enabled. When the CD

pin is high, charge is disabled and the charger enters high impedance (Hi-Z) mode.

Product Folder Links: bq24157S

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8.3.14 Boost Mode Operation

In HOST mode, when OTG pin is high (and OTG_EN bit is high thereby enabling OTG functionality) or the

operation mode bit (OPA_MODE) is set to 1, the device operates in boost mode and delivers the power to VBUS

from the battery. In normal boost mode, the device converts the battery voltage to VBUS-B (about 5.05 V) and

delivers a current as much as IBO (about 375 mA for bq24157S) to support other USB OTG devices connected to

the USB connector.

8.3.14.1 PWM Controller in Boost Mode

Similar to charge mode operation, in boost mode, the IC provides an integrated, fixed 3-MHz frequency voltage-

mode controller to regulate output voltage at PMID pin (VPMID). The voltage control loop is internally

compensated using a Type-III compensation scheme that provides enough phase margin for stable operation

with a wide load range and battery voltage range.

In boost mode, the input N-FET (Q1) prevents battery discharge when VBUS pin is over loaded. Cycle-by-cycle

current limit is sensed through the internal sense FET for Q3. The cycle-by-cycle current limit threshold for Q3 is

set to a nominal 1.0-A peak current. Synchronous operation is used in PWM mode to minimize power losses.

8.3.14.2 Boost Start Up

To prevent the inductor saturation and limit the inrush current, a soft-start control is applied during the boost start

up.

8.3.14.3 PFM Mode at Light Load

In boost mode, under light load conditions, the IC operates in pulse skipping mode (PFM mode) to reduce the

power loss and improve the converter efficiency. During boosting, the PWM converter is turned off when the

inductor current is less than 75 mA, and the PWM is turned back on only when the voltage at PMID pin drops to

about 99.5% of the rated output voltage. A unique pre-set circuit is used to make the smooth transition between

PWM and PFM mode.

8.3.14.4 Protection in Boost Mode

8.3.14.4.1 Output Overvoltage Protection

The IC provides built-in overvoltage protection to protect the device and other components against damage if the

VBUS voltage goes too high. When an overvoltage condition is detected, the IC turns off the PWM converter,

resets OPA_MODE bit to 0, sets fault status bits, and sends out a fault pulse from the STAT pin. When VBUS

drops to the normal level, the boost starts after host sets OPA_MODE to 1 or OTG pin stays in active status.

8.3.14.4.2 Output Overload Protection

The IC provides built-in overload protection to prevent the device and battery from damage when VBUS is

overloaded. After the overload condition is detected, Q1 operates in linear mode to limit the output current. If the

overload condition lasts for more than 30 ms, the overload fault is detected. When an overload condition is

detected, the IC turns off the PWM converter, resets OPA_MODE bit to 0, sets fault status bits, and sends out

fault pulse in STAT pin. The boost will not start until the host clears the fault register.

8.3.14.4.3 Battery Overvoltage Protection

During boosting, when the battery voltage is above the battery overvoltage threshold, VBATMAX, or below the

minimum battery voltage threshold, VBATMIN, the IC turns off the PWM converter, resets OPA_MODE bit to 0, sets

fault status bits, and sends out fault pulse in STAT pin. After the battery voltage goes above VBATMIN, the boost

will start after the host sets OPA_MODE to 1 or OTG pin stays in active status.

8.3.14.5 STAT Pin in Boost Mode

During normal boosting operation, the STAT pin behaves as a high impedance (open-drain) output. Under fault

conditions, a 128-μs pulse is sent out to notify the host.

Product Folder Links: bq24157S

STARTCondition

DATA

CLK

STOP Condition

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SLUSB76B –FEBRUARY 2013–REVISED MAY 2015

8.3.15 High Impedance (Hi-Z) Mode

In Hi-Z mode, the charger stops charging and enters a low quiescent current state to conserve power. Taking the

CD pin high causes the charger to enter Hi-Z mode. When in DEFAULT mode and the CD pin is low, the charger

automatically enters Hi-Z mode if either:

• VBUS > UVLO and a battery with VBAT > VLOWV is inserted, or

• VBUS falls below UVLO.

When in HOST mode and the CD is low, the charger can be placed into Hi-Z mode if the HZ-MODE control bit is

set to 1 and OTG pin is not in active status.

To exit Hi-Z mode, the CD pin must be low, VBUS must be higher than UVLO, and the HOST must write a 0 to

the HZ-MODE control bit.

8.3.16 Serial Interface Description

I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1,

January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus

is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through

open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor,

controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also

generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or

transmits data on the bus under control of the master device.

The IC works as a slave and is compatible with the following data transfer modes, as defined in the I2C-Bus

Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (up to 3.4 Mbps in write

mode). The interface adds flexibility to the battery charge solution, enabling most functions to be programmed to

new values depending on the instantaneous application requirements. Register contents remain intact as long as

supply voltage remains above 2.2 V (typical). I2C is asynchronous, which means that it runs off of SCL. The

device has no noise or glitch filtering on SCL, so SCL input needs to be clean. Therefore, TI recommends that

SDA changes while SCL is low.

The data transfer protocol for standard and fast modes is the same; therefore, they are referred to as F/S-mode

in this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to as HS-

mode. The bq24157S device supports 7-bit addressing only. The device 7-bit address is defined as 1101010

(6AH).

8.3.16.1 F/S Mode Protocol

The master initiates data transfer by generating a start condition. The start condition is when a high-to-low

transition occurs on the SDA line while SCL is high, as shown in Figure 22. All I2C-compatible devices should

recognize a start condition.

Figure 22. Start and Stop Condition

The master then generates the SCL pulses, and transmits the 8-bit address and the Read or Write direction bit

R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition

requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 23). All devices

recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device

with a matching address generates an acknowledge (see Figure 23) by pulling the SDA line low during the entire

high period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link

with a slave has been established.

Product Folder Links: bq24157S

DataOutput

byTransmitter

DataOutput

byReceiver

SCL From

Master

Not Acknowledge

Acknowledge

ClockPulsefor

Acknowledgement

1 2 89

START

Condition

DATA

CLK

DataLine

Stable;

DataValid

Change

ofData

Allowed

Not Recommended for New Designs

bq24157S

SLUSB76B –FEBRUARY 2013–REVISED MAY 2015

www.ti.com

Figure 23. Bit Transfer on the Serial Interface

The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the

slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an

acknowledge signal can either be generated by the master or by the slave, depending on which one is the

receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as

necessary. To signal the end of the data transfer, the master generates a STOP condition by pulling the SDA line

from low to high while the SCL line is high (see Figure 25). This releases the bus and stops the communication

link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a

stop condition, all devices know that the bus is released, and they wait for a start condition followed by a

matching address. If a transaction is terminated prematurely, the master needs to send a STOP condition to

prevent the slave I2C logic from getting stuck in a bad state. Attempting to read data from register addresses not

listed in this section will result in FFh being read out.

Figure 24. Acknowledge on the I2C Bus

Product Folder Links: bq24157S

SDA

SCL

RecognizeSTARTor

REPEATEDSTART

Condition

RecognizeSTOP or

REPEATEDSTART

Condition

Generate ACKNOWLEDGE

Signal

Acknowledgement

SignalFromSlave

MSB

Address

R/W

ACK

ClockLineHeldLowWhile

InterruptsareServiced

ACK

Not Recommended for New Designs

bq24157S

www.ti.com

SLUSB76B –FEBRUARY 2013–REVISED MAY 2015

Figure 25. Bus Protocol

8.3.16.2 HS Mode Protocol

When the bus is idle, both SDA and SCL lines are pulled high by the pullup devices.

The master generates a START condition followed by a valid serial byte containing HS master code 00001XXX.

This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the HS

master code, but all devices must recognize it and switch their internal setting to support 3.4-Mbps operation.

The master then generates a repeated START condition (a repeated START condition has the same timing as

the start condition). After this repeated START condition, the protocol is the same as F/S-mode, except that

transmission speeds up to 3.4 Mbps are allowed. A STOP condition ends the HS-mode and switches all the

internal settings of the slave devices to support the F/S-mode. Instead of using a STOP condition, repeated

START conditions should be used to secure the bus in HS-mode. If a transaction is terminated prematurely, the

master needs to send a STOP condition to prevent the slave I2C logic from getting stuck in a bad state.

Attempting to read data from register addresses not listed in this section results in FFh being read out.

8.3.16.3 I2C Update Sequence

The IC requires a start condition, a valid I2C address, a register address byte, and a data byte for a single

update. After the receipt of each byte, the IC acknowledges by pulling the SDA line low during the high period of

a single clock pulse. A valid I2C address selects the IC. The IC performs an update on the falling edge of the

acknowledge signal that follows the LSB byte.

For the first update, the IC requires a START condition, a valid I2C address, a register address byte, and a data

byte. For all consecutive updates, the IC needs a register address byte and a data byte. When a STOP condition

is received, the IC releases the I2C bus and awaits new start conditions.

Product Folder Links: bq24157S

S SLAVE ADDRESS R/W A REGISTER ADDRESS A DATA A/A P

Data Transferred

‘0’ (Write) (n Bytes+ Acknowledge)

Frommasterto IC A = Acknowledge(SDA LOW)

A = Notacknowledge(SDA

HIGH)

From ICto master S =STARTcondition

Sr =RepeatedSTARTcondition

P =STOP condition

(a) F/S-Mode

F/S-Mode HS-Mode

S HS-MASTERCODE ASr SLAVE ADDRESS R/W A REGISTER ADDRESS A DATA A/A P

Data Transferred

‘0’ (write) (n Bytes+ Acknowledge)

Sr Slave A.

(b)HS- Mode

F/S-Mode

HS-Mode

Continues

Not Recommended for New Designs

bq24157S

SLUSB76B –FEBRUARY 2013–REVISED MAY 2015

www.ti.com

Figure 26. Data Transfer Format In F/S Mode And HS Mode

8.3.16.4 Slave Address Byte

The slave address byte is the first byte received following the START condition from the master device.

MSB LSB

X1101011

8.3.16.5 Register Address Byte

Following the successful acknowledgment of the slave address, the bus master will send a byte to the IC, which

contains the address of the register to be accessed. The IC contains five 8-bit registers accessible through a

bidirectional I2C-bus interface. Among them, four internal registers have read and write access; and one has only

read access.

MSB LSB

0 0 0 0 0 D2 D1 D0

8.4 Device Functional Modes

8.4.1 Charge Mode Operation

8.4.1.1 Charge Profile

When a good battery with voltage below the recharge threshold has been inserted and a good adapter is

attached, the bq24157S enters charge mode. In charge mode, the IC has five control loops to regulate input

voltage, input current, charge current, charge voltage, and device junction temperature. During the charging

process, all five loops are enabled and the one that is dominant takes control. The IC supports a precision Li-ion

or Li-polymer charging system for single-cell applications. Figure 27 (a) indicates a typical charge profile without

input current regulation loop. It is the traditional CC/CV charge curve, while Figure 27 (b) shows a typical charge

profile when input current limiting loop is dominant during the constant current mode. In this case, the charge

current is higher than the input current, so the charge process is faster than the linear chargers. The input

voltage threshold for DPM loop, input current limits, charge current, termination current, and charge voltage are

all programmable using I2C interface.

Product Folder Links: bq24157S

Precharge

(LinearCharge)

FastCharge

(PWMCharge)

ISHORT

Termination

VSHORT

Regulation

Current

Regulation

Voltage

Precharge

Phase

CurrentRegulation

Phase

VoltageRegulation

Phase

ChargeCurrent

ChargeVoltage

Precharge

(LinearCharge)

FastCharge

(PWMCharge)

ISHORT

Termination

VSHORT

Regulation

voltage

Precharge

Phase

CurrentRegulation

Phase

VoltageRegulation

Phase

ChargeCurrent

ChargeVoltage

(a)

(b)

Not Recommended for New Designs

bq24157S

www.ti.com

SLUSB76B –FEBRUARY 2013–REVISED MAY 2015

Device Functional Modes (continued)

Figure 27. Typical Charging Profile:

(a) Without Input Current Limit

(b) With Input Current Limit

Product Folder Links: bq24157S

Not Recommended for New Designs

bq24157S

SLUSB76B –FEBRUARY 2013–REVISED MAY 2015

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8.5 Register Maps

Table 4. Status/Control Register (Read or Write)

Memory Location: 00, Reset State: x1xx 0xxx

BIT NAME Read or Write FUNCTION

Write: TMR_RST function, write 1 to reset the safety timer (auto clear)

Read: OTG pin status

B7 (MSB) TMR_RST/OTG Read or Write 0 – OTG pin at low level

1 – OTG pin at high level

0 – Disable STAT pin function

B6 EN_STAT Read or Write 1 – Enable STAT pin function (default 1)

B5 STAT2 Read only 00 – Ready

01 – Charge in progress

10 – Charge done

B4 STAT1 Read only 11 – Fault

B3 BOOST Read only 1 – Boost mode, 0 – Not in boost mode

B2 FAULT_3 Read only Charge mode:

000 – Normal

B1 FAULT_2 Read only 001 – VBUS OVP

010 – Sleep mode

011 – Bad Adaptor or VBUS < VUVLO

100 – Output OVP

101 – Thermal shutdown

110 – Timer fault

111 – No battery

Boost mode:

B0 (LSB) FAULT_1 Read only 000 – Normal

001 – VBUS OVP

010 – Overload

011 – Battery voltage is too low

100 – Battery OVP

101 – Thermal shutdown

110 – Timer fault

111 – N/A

Table 5. Control Register (Read or Write)

Memory Location: 01, Reset State: 0011 0000

BIT NAME Read or Write FUNCTION

B7 (MSB) Iin_Limit_2 Read or Write 00 – USB host with 100-mA current limit

01 – USB host with 500-mA current limit

10 – USB host/charger with 800-mA current limit

B6 Iin_Limit_1 Read or Write 11 – No input current limit

B5 V(LOWV_2) (1) Read or Write Weak battery voltage threshold: 200-mV step (default 1)

B4 V(LOWV_1) (1) Read or Write Weak battery voltage threshold: 100-mV step (default 1)

1 – Enable charge current termination

B3 TE Read or Write 0 – Disable charge current termination (default 0)

1 – Charger is disabled

B2 CE Read or Write 0 – Charger enabled (default 0)

1 – High impedance mode

B1 HZ_MODE Read or Write 0 – Not high impedance mode (default 0)

1 – Boost mode

B0 (LSB) OPA_MODE Read or Write 0 – Charger mode (default 0)

(1) The range of the weak battery voltage threshold (V(LOWV)) is 3.4 to 3.7 V with an offset of 3.4 V and steps of 100 mV (default 3.7 V,

using bits B4 to B5).

Product Folder Links: bq24157S

Not Recommended for New Designs

bq24157S

www.ti.com

SLUSB76B –FEBRUARY 2013–REVISED MAY 2015

Table 6. Control/Battery Voltage Register (Read or Write)

Memory Location: 02, Reset State: 0000 1010(1)

BIT NAME Read or Write FUNCTION

B7 (MSB) VO(REG5) Read or Write Battery Regulation Voltage: 640-mV step (default 0)

B6 VO(REG4) Read or Write Battery Regulation Voltage: 320-mV step (default 0)

B5 VO(REG3) Read or Write Battery Regulation Voltage: 160-mV step (default 0)

B4 VO(REG2) Read or Write Battery Regulation Voltage: 80-mV step (default 0)

B3 VO(REG1) Read or Write Battery Regulation Voltage: 40-mV step (default 1)

B2 VO(REG0) Read or Write Battery Regulation Voltage: 20-mV step (default 0)

1 – OTG boost enable with high level

B1 OTG_PL Read or Write 0 – OTG boost enable with low level (default 1); not applicable to OTG pin control of

current limit at POR in DEFAULT mode

1 – Enable OTG Pin in HOST mode

B0 (LSB) OTG_EN Read or Write 0 – Disable OTG pin in HOST mode (default 0), not applicable to OTG pin control of

current limit at POR in DEFAULT mode

(1) Charge voltage range is 3.5 to 4.44 V with the offset of 3.5 V and steps of 20 mV (default 3.54 V), using bits B2 to B7.

Table 7. Vender/Part/Revision Register (Read only)

Memory Location: 03, Reset State: 0101 000x

BIT NAME Read or Write FUNCTION

B7 (MSB) Vender2 Read only Vender Code: bit 2 (default 0)

B6 Vender1 Read only Vender Code: bit 1 (default 1)

B5 Vender0 Read only Vender Code: bit 0 (default 0)

B4 PN1 Read only For I2C Address 6AH:

01–N/A

10–bq24157S

B3 PN0 Read only 11–N/A

B2 Revision2 Read only 011: Revision 1.0;

B1 Revision1 Read only 001: Revision 1.1;

100 – 111: Future Revisions

B0 (LSB) Revision0 Read only

Table 8. Battery Termination/Fast Charge Current Register (Read or Write)

Memory Location: 04, Reset State: 0000 0001(1)

BIT NAME Read or Write FUNCTION

Write:

B7 (MSB) Reset Read or Write 1 – Charger in reset modes

0 – No effect, Read: always get 0

B6 VI(CHRG3) (2) Read or Write Charge current sense voltage: 27.2-mV step

B5 VI(CHRG2) (2) Read or Write Charge current sense voltage: 13.6-mV step

B4 VI(CHRG1) (2) Read or Write Charge current sense voltage: 6.8-mV step

B3 VI(CHRG0) (2) Read or Write N/A

B2 VI(TERM2) (3) Read or Write Termination current sense voltage: 13.6-mV step (default 0)

B1 VI(TERM1) (3) Read or Write Termination current sense voltage: 6.8-mV step (default 0)

B0 (LSB) VI(TERM0) (3) Read or Write Termination current sense voltage: 3.4-mV step (default 1)

(1) Charge current sense voltage offset is 37.4 mV and default charge current is 550 mA, if 68-mΩsensing resistor is used and

LOW_CHG = 0.

(2) See Table 13

(3) See Table 12

Product Folder Links: bq24157S

Not Recommended for New Designs

bq24157S

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Table 9. Special Charger Voltage/Enable Pin Status Register

Memory Location: 05, Reset state: 000X X100(1) (2)

BIT NAME Read or Write FUNCTION

B7 (MSB) NA Read or Write NA

0 – Disables factory test mode

B6 FAC_MODE Read or Write 1 – Enables the factory test mode

0 – Normal charge current sense voltage at 04H,

B5 LOW_CHG Read or Write 1 – Low charge current sense voltage of 22.1 mV (default 0)

0 – DPM mode is not active,

B4 DPM_STATUS Read only 1 – DPM mode is active

0 – CD pin at LOW level,

B3 CD_STATUS Read only 1 – CD pin at HIGH level

B2 VSREG2 Read or Write Special charger voltage: 320mV step (default 1)

B1 VSREG1 Read or Write Special charger voltage: 160mV step (default 0)

B0 (LSB) VSREG0 Read or Write Special charger voltage: 80mV step (default 0)

(1) Special charger voltage offset is 4.2 V and default special charger voltage is 4.52 V.

(2) Default charge current will be 550 mA, if 68-mΩsensing resistor is used, since default LOW_CHG = 0.

Table 10. Safety Limit Register (Read or Write, Write Only One Time After Reset)

Memory Location: 06, Reset State: 01000000

BIT NAME Read or Write FUNCTION

B7 (MSB) VMCHRG3 (1) Read or Write Maximum charge current sense voltage: 54.4-mV step (default 0) (2)

B6 VMCHRG2 (1) Read or Write Maximum charge current sense voltage: 27.2-mV step (default 1)

B5 VMCHRG1 (1) Read or Write Maximum charge current sense voltage: 13.6-mV step (default 0)

B4 VMCHRG0 (1) Read or Write Maximum charge current sense voltage: 6.8-mV step (default 0)

B3 VMREG3 Read or Write Maximum battery regulation voltage: 160-mV step (default 0)

B2 VMREG2 Read or Write Maximum battery regulation voltage: 80-mV step (default 0)

B1 VMREG1 Read or Write Maximum battery regulation voltage: 40-mV step (default 0)

B0 (LSB) VMREG0 Read or Write Maximum battery regulation voltage: 20-mV step (default 0)

(1) Refer to Table 13

SPACE

• Maximum charge current sense voltage offset is 37.4 mV (550 mA), default at 64.6 mV (950 mA) and the

maximum charge current option is 1.55 A (105.4 mV), if 55-mΩsensing resistor is used.

• Maximum battery regulation voltage offset is 4.2 V (default at 4.2 V) and maximum battery regulation voltage

option is 4.44 V.

• Memory location 06H resets only when V(CSOUT) drops below either 1) V(SHORT) threshold (typical 2.05 V) if

VBUS>V(UVLO) or 2) the digital reset threshold (typ 2.4V) if VBUS<V(UVLO). After reset, the maximum

values for battery regulation voltage and charge current can be programmed until any writing to other register

locks the safety limits. Programmed values exclude higher values from memory locations 02 (battery

regulation voltage), and from memory location 04 (fast charge current).

• If host accesses (write command) to some other register before safety limit register, the safety default values

are used.

Product Folder Links: bq24157S

CVREF

33 nF

CBOOT

PACK–

PACK+

CCSOUT

SCL

SDA

CSOUT

CSIN

PGND

I2C BUS

VAUX

HOST

SCL

SDA

STAT

VREF

STAT

PMID

VBUS

CIN

BOOT

RSNS

CCSIN

VBAT

1 Fm

4.7 Fm

10 kW

L 1 Hm

CO1

22 Fm

0.1 Fm

1 Fm

bq24157S

CO2

33 Fm

SLRST

10 kWCD

SLRST

CIN

Not Recommended for New Designs

bq24157S

www.ti.com

SLUSB76B –FEBRUARY 2013–REVISED MAY 2015

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The bq24157S is a compact, flexible, high-efficiency, USB-friendly, switch-mode charge management solution for

single-cell Li-ion and Li-polymer batteries used in a wide range of portable applications. The bq24157S integrates

a synchronous PWM controller, power MOSFETs, input current sensing, high-accuracy current and voltage

regulation, and charge termination, into a small DSBGA package. The charge parameters can be programmed

through an I2C interface.

9.2 Typical Application

VBUS =5V,ICHARGE = 1250 mA, VBAT = 3.5 to 4.44 V (adjustable).

Figure 28. I2C Controlled 1-Cell USB Charger Application Circuit With USB-OTG Support

9.2.1 Design Requirements

Use the following typical application design procedure to select external components values for the bq24157S

device.

Specification Test Condition MIN TYP MAX UNIT

Input DC voltage, VIN Input voltage from AC adapter input 4 5 6 V

Input current Maximum input current from AC adapter input 0.1 0.1 to 0.5 1.5 A

Charge current Battery charge current 0.325 0.7 1.55 A

Output regulation voltage Voltage applied at VBAT 0 3 to 4.2 4.44 V

Operating junction temperature range, TJ0 125 °C

Product Folder Links: bq24157S

2 3 2 -6

OUT

4 (40 10 ) (1 10 )

p ´ ´ ´ ´

2 2

OUT

4 L

p ´ ´

OUT OUT

o2 L C

p ´ ´

LPK

0.42

I 1.25

= +

LPK OUT

I I

= +

L-6

2.5 (5 - 2.5)

I = 6

5 (3 10 ) (1 10 )

´ ´ ´ ´

´ ´

LOUT

VBAT (VBUS - VBAT)

I = VBUS Lf

OUT 6

2.5 (5 - 2.5)

L =

5 (3 10 ) 1.25 0.3

´ ´ ´ ´

´ ´ D

OUT L

VBAT (VBUS - VBAT)

L = VBUS If

Not Recommended for New Designs

bq24157S

SLUSB76B –FEBRUARY 2013–REVISED MAY 2015

www.ti.com

9.2.2 Detailed Design Procedure

Systems design specifications:

• VBUS = 5 V

• VBAT = 4.2 V (1 cell)

• I(charge) = 1.25 A

• Inductor ripple current = 30% of fast charge current

SPACE

1. Determine the inductor value (LOUT) for the specified charge current ripple:

, the worst case is when battery voltage is as close as to half of the input

voltage.

(1)

LOUT = 1.11 μH

Select the output inductor to standard 1 μH. Calculate the total ripple current with using the 1-μH inductor:

(2)

(3)

ΔIL= 0.42 A

Calculate the maximum output current:

(4)

(5)

ILPK = 1.46 A

Select 2.5-mm by 2-mm, 1-μH, 1.5-A surface mount multi-layer inductor. The suggested inductor part

numbers are shown in Table 11.

Table 11. Inductor Part Numbers

Part Number Inductance Size Manufacturer

LQM2HPN1R0MJ0 1 μH 2.5 × 2.0 mm Murata

MIPS2520D1R0 1 μH 2.5 × 2.0 mm FDK

MDT2520-CN1R0M 1 μH 2.5 × 2.0 mm TOKO

CP1008 1 μH 2.5 × 2.0 mm Inter-Technical

2. Determine the output capacitor value (COUT) using 40 kHz as the resonant frequency:

(6)

(7)

(8)

Product Folder Links: bq24157S

100

200

300

400

500

600

700

800

Loss (mW)

Battery Charge Efficiency Battery Charge Loss

500 600 700 800 900 1000 1100 1200 1300

Efficiency (%)

Charge Current (mA)

FDK

TOKO

Inter-Technical

muRata

500 600 700 800 900 1000 1100 1200 1300

Charge Current (mA)

FDK

TOKO

Inter-Technical

muRata

T = 25°C

VBUS = 5 V

VBAT = 3 V

AT = 25°C

VBUS = 5 V

VBAT = 3 V

(SNS)

85mV

R1.25A

(RSNS)

(SNS) (CHARGE)

Not Recommended for New Designs

bq24157S

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SLUSB76B –FEBRUARY 2013–REVISED MAY 2015

COUT = 15.8 μF

Select two 0603 X5R 6.3-V 10-μF ceramic capacitors in parallel, that is, Murata GRM188R60J106M.

3. Determine the sense resistor using Equation 9:

(9)

The maximum sense voltage across the sense resistor is 85 mV. To get a better current regulation accuracy,

V(RSNS) should equal 85 mV, and calculate the value for the sense resistor.

(10)

R(SNS) = 68 mΩ

This is a standard value. If it is not a standard value, then choose the next close value and calculate the real

charge current. Calculate the power dissipation on the sense resistor:

P(RSNS) = I(CHARGE) 2× R(SNS)

P(RSNS) = 1.252× 0.068

P(RSNS) = 0.106 W

Select 0402 0.125-W 68-mΩ2% sense resistor, that is, Panasonic ERJ2BWGR068.

For 1.5A application, R(SNS)= 85mV/1.55A = 55 mΩ

4. Measured efficiency and total power loss with different inductors are shown in Figure 29. SW node and

inductor current waveform are shown in Figure 37.

Figure 29. Measured Efficiency and Power Loss

Product Folder Links: bq24157S

OUT OUT

o2 L C

p ´ ´

I(CHRG0)

O(CHARGE_STEP) (SNS)

I = R

I(TERM0)

O(TERM_STEP) (SNS)

I = R

Not Recommended for New Designs

bq24157S

SLUSB76B –FEBRUARY 2013–REVISED MAY 2015

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9.2.2.1 Charge Current Sensing Resistor Selection Guidelines

Both the termination current range and charge current range depend on the sensing resistor (RSNS). The

termination current step (IOTERM_STEP) can be calculated using Equation 11.

(11)

Table 12 shows the termination current settings for three sensing resistors.

Table 12. Termination Current Settings for 55-mΩ, 68-mΩ, and 100-mΩSense Resistors

I(TERM) (mA) I(TERM) (mA) I(TERM) (mA)

BIT VI(TERM) (mV) R(SNS) = 55 mΩR(SNS) = 68 mΩR(SNS) = 100 mΩ

VI(TERM2) 13.6 247 200 136

VI(TERM1) 6.8 124 100 68

VI(TERM0) 3.4 62 50 34

Offset 3.4 62 50 34

For example, with a 68-mΩsense resistor, V(ITERM2) = 1, V(ITERM1) = 0, and V(ITERM0) = 1, ITERM = [(13.6 mV × 1) +

(6.8 mV × 0) + (3.4 mV × 1) + 3.4 mV] / 68 mΩ=200mA+0+50mA+50mA=300mA.

The charge current step (IO(CHARGE_STEP)) is calculated using Equation 12.

(12)

Table 13 shows the charge current settings for three sensing resistors.

Table 13. Charge Current Settings for 55-mΩ, 68-mΩ, and 100-mΩSense Resistors

IO(CHARGE) (mA) IO(CHARGE) (mA) IO(CHARGE) (mA)

BIT VI(REG) (mV) R(SNS) = 55 mΩR(SNS) = 68 mΩR(SNS) = 100 mΩ

VI(CHRG3) 54.4 989 800 544

VI(CHRG2) 27.2 495 400 272

VI(CHRG1) 13.6 247 200 136

VI(CHRG0) 6.8 124 100 68

Offset 37.4 680 550 374

For example, with a 68-mΩsense resistor, V(CHRG3) = 1, V(CHRG2) = 0, V(ICHRG1) = 0, and V(ICHRG0) = 1, ITERM =

[(54.4 mV × 1) + (27.2 mV × 0) + (13.6 mV × 0) + (6.8 mV × 1) + 37.4 mV] / 68 mΩ=800mA+0+0+100mA

= 900 mA.

9.2.2.2 Output Inductor and Capacitance Selection Guidelines

The IC provides internal loop compensation. With the internal loop compensation, the highest stability occurs

when the LC resonant frequency, ƒo, is approximately 40 kHz (20 to 80 kHz). Equation 13 can be used to

calculate the value of the output inductor, LOUT, and output capacitor, COUT.

(13)

To reduce the output voltage ripple, TI recommends a ceramic capacitor with the capacitance between 4.7 to 47

μF for COUT. See previous sections in the Detailed Design Procedure for components selection.

Product Folder Links: bq24157S

VBAT

2 V/div

1 A/div

BAT

200 s/divμ

VBAT

IBAT

AC Coupled

VBUS

100 mV/div

VSW

2 V/div

I Inductor

200 mA/div

100 ns/div

VBUS

VSW

VBAT

AC Coupled

VBAT

100 mV/div

IND

2 V/div

(VBUS)

500 mA/div

(BAT)

1 s/div

V(VBUS)

2 V/div

(BAT) V(BAT)

2 V/div

(SW)

V(SW)

I(BAT)

VSW

2 V/div

I Inductor

500 ms/div

200 ns/div

VSW

IND

2 V/div

(VBUS)

500 mA/div

(BAT)

1 s/div

V(VBUS)

2 V/div

(BAT) V(BAT)

2 V/div

(SW) V(SW)

I(BAT)

2 V/div

(VBUS)

500 mA/div

(BAT)

100 ms/div

V(VBUS)

2 V/div

(BAT) V(BAT)

2 V/div

(SW)

V(SW)

I(BAT)

Not Recommended for New Designs

bq24157S

www.ti.com

SLUSB76B –FEBRUARY 2013–REVISED MAY 2015

9.2.3 Application Curves

VBUS = 0 to 5 V IIN_limit = 500 mA VBATREG = 4.2 V VBUS = 5 V VBAT = 3.5 V IIN_limit = 500 mA

VBAT = 3.5 V ICHG = 550 mA VBATREG = 4.2 V ICHG = 550 mA

Termination Enabled

Figure 30. Adapter Insertion (HOST Mode) Figure 31. Battery Insertion/Removal Termination Enabled

(HOST Mode)

VBUS = 5 V VBAT = 3.5 V IIN_limit = 500 mA VBUS = 5 V VBAT = 2.6 V VOREG = 4.2 V

VBATREG = 4.2 V ICHG = 550 mA Termination ICHG = 950 mA

Enabled Figure 33. PWM Charging Waveforms

Figure 32. Battery Insertion/Removal Termination Disabled

(HOST Mode)

VBUS = 5.05 V VBAT = 3.5 V IBUS = 217 mA 5.5-V input voltage

Figure 34. Boost Waveform (PWM Mode) Figure 35. Step Load from 0 to 2 A During Factory Mode

Product Folder Links: bq24157S

VIN +

PMID

VBUS SW

PGND

bq2415x

Isns

Rsns

Ichg

BAT

Isys

System

Load

Not Recommended for New Designs

bq24157S

SLUSB76B –FEBRUARY 2013–REVISED MAY 2015

www.ti.com

10 Power Supply Recommendations

10.1 System Load After Sensing Resistor

One of the simpler high-efficiency topologies connects the system load directly across the battery pack, as

shown in Figure 36. The input voltage has been converted to a usable system voltage with good efficiency from

the input. When the input power is on, it supplies the system load and charges the battery pack at the same time.

When the input power is off, the battery pack powers the system directly.

Figure 36. System Load After Sensing Resistor

The advantages:

1. When the AC adapter is disconnected, the battery pack powers the system load with minimum power

dissipation. Consequently, the time that the system runs on the battery pack can be maximized.

2. It reduces the number of external path selection components and offers a low-cost solution.

3. Dynamic power management (DPM) can be achieved. The total of the charge current and the system current

can be limited to a desired value by setting the charge current value. When the system current increases, the

charge current drops by the same amount. As a result, no potential overcurrent or overheating issues are

caused by excessive system load demand.

4. The total input current can be limited to a desired value by setting the input current limit value. USB

specifications can be met easily.

5. The supply voltage variation range for the system can be minimized.

6. The input current soft-start can be achieved by the generic soft-start feature of the IC.

Design considerations and potential issues:

1. If the system always demands a high current (but lower than the regulation current), the battery charging

never terminates. Thus, the battery is always charged, and its lifetime may be reduced.

2. Because the total current regulation threshold is fixed and the system always demands some current, the

battery may not be charged with a full-charge rate and thus may lead to a longer charge time.

3. If the system load current is large after the charger has been terminated, the IR drop across the battery

impedance may cause the battery voltage to drop below the refresh threshold and start a new charge cycle.

The charger would then terminate due to low charge current. Therefore, the charger would cycle between

charging and terminating. If the load is smaller, the battery has to discharge down to the refresh threshold,

resulting in a much slower cycling.

4. In a charger system, the charge current is typically limited to about 30 mA, if the sensed battery voltage is

below the 2-V short circuit protection threshold. This results in low power availability at the system bus. If an

external supply is connected and the battery is deeply discharged below the short circuit protection threshold,

the charge current is clamped to the short circuit current limit. This then is the current available to the system

during the power-up phase. Most systems cannot function with such limited supply current, and the battery

supplements the additional power required by the system. Note that the battery pack is already at the

depleted condition, and it discharges further until the battery protector opens, resulting in a system shutdown.

5. If the battery is below the short circuit threshold and the system requires a bias current budget lower than the

short circuit current limit, the end-equipment will be operational, but the charging process can be affected

Product Folder Links: bq24157S

Not Recommended for New Designs

bq24157S

www.ti.com

SLUSB76B –FEBRUARY 2013–REVISED MAY 2015

System Load After Sensing Resistor (continued)

depending on the current left to charge the battery pack. Under extreme conditions, the system current is

close to the short circuit current levels and the battery may not reach the fast-charge region in a timely

manner. As a result, the safety timers flag the battery pack as defective, terminating the charging process.

Because the safety timer cannot be disabled, the inserted battery pack must not be depleted to make the

application possible.

6. If the battery pack voltage is too low, highly depleted, totally dead or even shorted, the system voltage is

clamped by the battery and it cannot operate even if the input power is on.

Product Folder Links: bq24157S

High

Frequency

Current

Path

L1 R1

VBUS

PMID

PGND

SW VBAT

BAT

VIN

Not Recommended for New Designs

bq24157S

SLUSB76B –FEBRUARY 2013–REVISED MAY 2015

www.ti.com

11 Layout

11.1 Layout Guidelines

Give special attention to the PCB layout. The following list provides guidelines:

• To obtain optimal performance, the power input capacitors, connected from input to PGND, should be placed

as close as possible to the pin. The output inductor should be placed close to the IC and the output capacitor

connected between the inductor and PGND of the IC. The intent is to minimize the current path loop area

from the SW pin through the LC filter and back to the PGND pin. To prevent high frequency oscillation

problems, proper layout to minimize high frequency current path loop is critical (see Figure 37). The sense

resistor should be adjacent to the junction of the inductor and output capacitor. Route the sense leads

connected across the RSNS back to the IC, close to each other (minimize loop area) or on top of each other

on adjacent layers (do not route the sense leads through a high-current path, see Figure 38).

• Place all decoupling capacitors close to their respective IC pins and close to PGND (do not place components

such that routing interrupts power stage currents). All small control signals should be routed away from the

high current paths.

• The PCB should have a ground plane (return) connected directly to the return of all components through vias

(two vias per capacitor for power-stage capacitors, two vias for the IC PGND, and one via per capacitor for

small-signal components). A star ground design approach is typically used to keep circuit block currents

isolated (high-power/low-power small-signal), which reduces noise-coupling and ground-bounce issues. A

single ground plane for this design gives good results. With this small layout and a single ground plane, there

is no ground-bounce issue, and having the components segregated minimizes coupling between signals.

• The high-current charge paths into VBUS, PMID, and from the SW pins must be sized appropriately for the

maximum charge current in order to avoid voltage drops in these traces. The PGND pins should be

connected to the ground plane to return current through the internal low-side FET.

• Place 4.7-μF input capacitor as close to PMID pin and PGND pin as possible to make the high frequency

current loop area as small as possible. Place 1-μF input capacitor as close to VBUS pin and PGND pin as

possible to make high frequency current loop area as small as possible (see Figure 39).

11.2 Layout Example

Figure 37. High Frequency Current Path

Product Folder Links: bq24157S

VBUS

PMID

PGND

4.7µF

1µF

Vin+

Vin–

ChargeCurrentDirection

ToCSINandCSOUTpin

RSNS

ToInductor ToCapacitorandbattery

CurrentSensingDirection

Not Recommended for New Designs

bq24157S

www.ti.com

SLUSB76B –FEBRUARY 2013–REVISED MAY 2015

Layout Example (continued)

Figure 38. Sensing Resistor PCB Layout

Figure 39. Input Capacitor Position and PCB Layout Example

Product Folder Links: bq24157S

Not Recommended for New Designs

bq24157S

SLUSB76B –FEBRUARY 2013–REVISED MAY 2015

www.ti.com

12 Device and Documentation Support

12.1 Device Support

12.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 Documentation Support

12.2.1 Related Documentation

bq24157S User’s Guide (SLUU453)

12.3 Trademarks

NanoFree is a trademark of Texas Instruments.

12.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

12.5 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

Product Folder Links: bq24157S

A1 A2 A3 A4

E1 E2 E3 E4

DSBGA Package

(Top View)

Chip Scale Package

(Top Side Symbol)

TIYMLLLLS

bq24157S

Not Recommended for New Designs

bq24157S

www.ti.com

SLUSB76B –FEBRUARY 2013–REVISED MAY 2015

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

13.1 Package Summary

0-Pin A1 Marker , TI-TI Letters, YM = Year Month Date Code, LLLL = Lot T race Code, S = Assembly Site Code

13.1.1 Chip Scale Packaging Dimensions

The bq24157S device is available in a 20-bump chip scale package (DSBGA, NanoFree™).

The package dimensions are:

D E

Max = 2.17 mm Max = 2.03 mm

Min = 2.11 mm Min = 1.97 mm

Product Folder Links: bq24157S

PACKAGE OPTION ADDENDUM

www.ti.com 28-May-2015

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

BQ24157SYFFR NRND DSBGA YFF 20 3000 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM BQ24157S

BQ24157SYFFT NRND DSBGA YFF 20 250 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM BQ24157S

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

PACKAGE OPTION ADDENDUM

www.ti.com 28-May-2015

Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

BQ24157SYFFR DSBGA YFF 20 3000 180.0 8.4 2.2 2.35 0.8 4.0 8.0 Q1

BQ24157SYFFT DSBGA YFF 20 250 180.0 8.4 2.2 2.35 0.8 4.0 8.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 17-Jun-2015

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

BQ24157SYFFR DSBGA YFF 20 3000 182.0 182.0 20.0

BQ24157SYFFT DSBGA YFF 20 250 182.0 182.0 20.0

PACKAGE MATERIALS INFORMATION

www.ti.com 17-Jun-2015

Pack Materials-Page 2

D: Max =

E: Max =

2.172 mm, Min =

2.03 mm, Min =

2.112 mm

1.97 mm

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Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Texas Instruments:

BQ24157SYFFT BQ24157SYFFR