Revised August 2000 100302 Low Power Quint 2-Input OR/NOR Gate General Description Features The 100302 is a monolithic quint 2-input OR/NOR gate with common enable. All inputs have 50 k pull-down resistors and all outputs are buffered. 43% power reduction of the 100102 2000V ESD protection Pin/function compatible with 100102 Voltage compensated operating range = -4.2V to -5.7V Available to industrial grade temperature range (PLCC package only) Ordering Code: Order Number Package Number Package Description 100302SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 100302PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 100302QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 100302QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (-40C to +85C) Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Connection Diagrams 24-Pin DIP/SOIC 28-Pin PLCC Pin Descriptions Pin Names Description Dna-Dne Data Inputs E Enable Input Oa-Oe Data Outputs Oa-Oe Complementary Data Outputs (c) 2000 Fairchild Semiconductor Corporation DS010580 www.fairchildsemi.com 100302 Low Power Quint 2-Input OR/NOR Gate August 1989 100302 Logic Symbol Truth Table D1X D2X E OX OX L L L L H L L H H L L H L H L L H H H L H L L H L H L H H L H H L H L H H H H L H = HIGH Voltage Level www.fairchildsemi.com 2 L = LOW Voltage Level Storage Temperature (TSTG) VEE Pin Potential to Ground Pin Recommended Operating Conditions -65C to +150C +150C Maximum Junction Temperature (TJ) Case Temperature (TC) -7.0V to +0.5V Output Current (DC Output HIGH) -50 mA ESD (Note 2) 2000V 0C to +85C Commercial VEE to +0.5V Input Voltage (DC) 100302 Absolute Maximum Ratings(Note 1) -40C to +85C Industrial -5.7V to -4.2V Supply Voltage (VEE) Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Commercial Version DC Electrical Characteristics (Note 3) VEE = -4.2V to -5.7V, VCC = VCCA = GND, TC = 0C to +85C Min Typ Max Units VOH Symbol Output HIGH Voltage Parameter -1025 -955 -870 mV VOL Output LOW Voltage -1830 -1705 -1620 mV VOHC Output HIGH Voltage -1035 VOLC Output LOW Voltage VIH Input HIGH Voltage VIL IIL IIH Input HIGH Current IEE Power Supply Current mV Conditions Loading with VIN = VIH(Max) or VIL(Min) 50 to -2.0V Loading with VIN = VIH(Min) or VIL(Max) -1610 mV -1165 -870 mV Guaranteed HIGH Signal for All Inputs Input LOW Voltage -1830 -1475 mV Guaranteed LOW Signal for All Inputs Input LOW Current 0.50 A VIN = VIL(Min) -45 -36 240 A VIN = VIH(Max) -20 mA Inputs OPEN 50 to -2.0V Note 3: The specified limits represent the "worst case" value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under "worst case" conditions. DIP AC Electrical Characteristics VEE = -4.2V to -5.7V, VCC = VCCA = GND Symbol Parameter tPLH Propagation Delay tPHL Data to Output tPLH Propagation Delay tPHL Enable to Output tTLH Transition Time tTHL 20% to 80%, 80% to 20% TC = 0C TC = +25C TC = +85C Units Min Max Min Max Min Max 0.50 1.15 0.50 1.15 0.50 1.25 ns 0.70 1.90 0.70 1.90 0.80 2.00 ns 0.40 1.20 0.40 1.20 0.40 1.20 ns Conditions Figures 1, 2 (Note 4) Figures 1, 2 Note 4: The propagation delay specified is for single output switching. Delays may vary up to 100 ps with multiple outputs switching. 3 www.fairchildsemi.com 100302 Commercial Version (Continued) SOIC and PLCC AC Electrical Characteristics VEE = -4.2V to -5.7V, VCC = VCCA = GND Symbol Parameter tPLH Propagation Delay tPHL Data to Output tPLH Propagation Delay tPHL Enable to Output tTLH Transition Time tTHL 20% to 80%, 80% to 20% tOSHL Maximum Skew Common Edge Output-to-Output Variation TC = 0C TC = +25C TC = +85C Units Min Max Min Max Min Max 0.50 1.05 0.50 1.05 0.50 1.15 ns 0.70 1.80 0.70 1.80 0.80 1.90 ns 0.40 1.10 0.40 1.10 0.40 1.10 ns Conditions Figures 1, 2 (Note 5) Figures 1, 2 PLCC Only 250 250 250 ps 310 310 310 ps 200 200 200 ps 330 330 330 ps 250 250 250 ps 330 330 330 ps 200 200 200 ps 280 280 280 ps (Note 6) Data to Output Path tOSHL Maximum Skew Common Edge Output-to-Output Variation PLCC Only (Note 6) Enable to Output Path tOSLH Maximum Skew Common Edge Output-to-Output Variation PLCC Only (Note 6) Data to Output Path tOSLH Maximum Skew Common Edge Output-to-Output Variation PLCC Only (Note 6) Enable to Output Path tOST Maximum Skew Opposite Edge Output-to-Output Variation PLCC Only (Note 6) Data to Output Path tOST Maximum Skew Opposite Edge Output-to-Output Variation PLCC Only ((Note 6) Enable to Output Path tPS Maximum Skew Pin (Signal) Transition Variation PLCC Only (Note 6) Data to Output Path tPS Maximum Skew Pin (Signal) Transition Variation PLCC Only (Note 6) Enable to Output Path Note 5: The propagation delay specified is for single output switching. Delays may vary up to 100 ps with multiple outputs switching. Note 6: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite directions both HL and LH (tOST). Parameters tOST and tPS guaranteed by design. www.fairchildsemi.com 4 100302 Industrial Version PLCC DC Electrical Characteristics (Note 7) VEE = -4.2V to -5.7V, VCC = VCCA = GND, TC = -40C to +85C TC = -40C TC = 0C to +85C Symbol Parameter Min Max Min Max Units Conditions VOH Output HIGH Voltage -1085 -870 -1025 -870 VOL Output LOW Voltage -1830 -1575 -1830 -1620 VOHC Output HIGH Voltage -1095 VOLC Output LOW Voltage VIH Input HIGH Voltage -1170 -870 -1165 -870 mV Guaranteed HIGH Signal for ALL Inputs -1480 -1830 -1475 mV Guaranteed LOW Signal for ALL Inputs A VIN = VIL(Min) -1035 -1565 VIL Input LOW Voltage -1830 IIL Input LOW Current 0.05 IIH Input HIGH Current IEE Power Supply Current -1610 0.05 300 -45 -20 -45 mV mV VIN = VIH(Max) Loading with or VIL(Min) 50 to -2.0V VIN = VIH(Min) Loading with or VIL(Max) 50 to -2.0V 240 A VIN = VIH(Max) -20 mA Inputs OPEN Note 7: The specified limits represent the "worst case" value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under the "worst case" conditions. PLCC AC Electrical Characteristics VEE = -4.2V to -5.7V, VCC = VCCA = GND Symbol Parameter tPLH Propagation Delay tPHL Data to Output tPLH Propagation Delay tPHL Enable to Output tTLH Transition Time tTHL 20% to 80%, 80% to 20% TC = -40C TC = +25C TC = +85C Units Min Max Min Max Min Max 0.40 1.05 0.50 1.05 0.50 1.15 ns 0.70 1.80 0.70 1.80 0.80 1.90 ns 0.30 1.10 0.40 1.10 0.40 1.10 ns Conditions Figures 1, 2 (Note 8) Figures 1, 2 Note 8: The propagation delay specified is for single output switching. Delays may vary up to 200 ps with multiple outputs switching. 5 www.fairchildsemi.com 100302 Test Circuitry Notes: VCC, VCCA = +2V, VEE = -2.5V L1 and L2 = equal length 50 impedance lines RT = 50 terminator internal to scope Decoupling 0.1 F from GND to VCC and VEE All unused outputs are loaded with 50 to GND CL = Fixture and stray capacitance 3 pF FIGURE 1. AC Test Circuit Switching Waveforms FIGURE 2. Propagation Delay and Transition Times www.fairchildsemi.com 6 100302 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number N24E 7 www.fairchildsemi.com 100302 Low Power Quint 2-Input OR/NOR Gate Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8